drivers/mmc/host/renesas_sdhi_internal_dmac.c

   1 /*
   2  * DMA support for Internal DMAC with SDHI SD/SDIO controller
   3  *
   4  * Copyright (C) 2016-17 Renesas Electronics Corporation
   5  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/device.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/io-64-nonatomic-hi-lo.h>
  16 #include <linux/mfd/tmio.h>
  17 #include <linux/mmc/host.h>
  18 #include <linux/mod_devicetable.h>
  19 #include <linux/module.h>
  20 #include <linux/pagemap.h>
  21 #include <linux/scatterlist.h>
  22 #include <linux/sys_soc.h>
  23
  24 #include "renesas_sdhi.h"
  25 #include "tmio_mmc.h"
  26
  27 #define DM_CM_DTRAN_MODE        0x820
  28 #define DM_CM_DTRAN_CTRL        0x828
  29 #define DM_CM_RST               0x830
  30 #define DM_CM_INFO1             0x840
  31 #define DM_CM_INFO1_MASK        0x848
  32 #define DM_CM_INFO2             0x850
  33 #define DM_CM_INFO2_MASK        0x858
  34 #define DM_DTRAN_ADDR           0x880
  35
  36 /* DM_CM_DTRAN_MODE */
  37 #define DTRAN_MODE_CH_NUM_CH0   0       /* "downstream" = for write commands */
  38 #define DTRAN_MODE_CH_NUM_CH1   BIT(16) /* "uptream" = for read commands */
  39 #define DTRAN_MODE_BUS_WID_TH   (BIT(5) | BIT(4))
  40 #define DTRAN_MODE_ADDR_MODE    BIT(0)  /* 1 = Increment address */
  41
  42 /* DM_CM_DTRAN_CTRL */
  43 #define DTRAN_CTRL_DM_START     BIT(0)
  44
  45 /* DM_CM_RST */
  46 #define RST_DTRANRST1           BIT(9)
  47 #define RST_DTRANRST0           BIT(8)
  48 #define RST_RESERVED_BITS       GENMASK_ULL(32, 0)
  49
  50 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */
  51 #define INFO1_CLEAR             0
  52 #define INFO1_DTRANEND1         BIT(17)
  53 #define INFO1_DTRANEND0         BIT(16)
  54
  55 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */
  56 #define INFO2_DTRANERR1         BIT(17)
  57 #define INFO2_DTRANERR0         BIT(16)
  58
  59 /*
  60  * Specification of this driver:
  61  * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
  62  * - Since this SDHI DMAC register set has 16 but 32-bit width, we
  63  *   need a custom accessor.
  64  */
  65
  66 static unsigned long global_flags;
  67 /*
  68  * Workaround for avoiding to use RX DMAC by multiple channels.
  69  * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use
  70  * RX DMAC simultaneously, sometimes hundreds of bytes data are not
  71  * stored into the system memory even if the DMAC interrupt happened.
  72  * So, this driver then uses one RX DMAC channel only.
  73  */
  74 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY  0
  75 #define SDHI_INTERNAL_DMAC_RX_IN_USE    1
  76
  77 /* Definitions for sampling clocks */
  78 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
  79         {
  80                 .clk_rate = 0,
  81                 .tap = 0x00000300,
  82         },
  83 };
  84
  85 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
  86         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  87                           TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
  88         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  89                           MMC_CAP_CMD23,
  90         .capabilities2  = MMC_CAP2_NO_WRITE_PROTECT,
  91         .bus_shift      = 2,
  92         .scc_offset     = 0x1000,
  93         .taps           = rcar_gen3_scc_taps,
  94         .taps_num       = ARRAY_SIZE(rcar_gen3_scc_taps),
  95         /* DMAC can handle 0xffffffff blk count but only 1 segment */
  96         .max_blk_count  = 0xffffffff,
  97         .max_segs       = 1,
  98 };
  99
 100 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
 101         { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
 102         { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
 103         { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
 104         {},
 105 };
 106 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
 107
 108 static void
 109 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
 110                                     int addr, u64 val)
 111 {
 112         writeq(val, host->ctl + addr);
 113 }
 114
 115 static void
 116 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
 117 {
 118         struct renesas_sdhi *priv = host_to_priv(host);
 119
 120         if (!host->chan_tx || !host->chan_rx)
 121                 return;
 122
 123         if (!enable)
 124                 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
 125                                                     INFO1_CLEAR);
 126
 127         if (priv->dma_priv.enable)
 128                 priv->dma_priv.enable(host, enable);
 129 }
 130
 131 static void
 132 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
 133         u64 val = RST_DTRANRST1 | RST_DTRANRST0;
 134
 135         renesas_sdhi_internal_dmac_enable_dma(host, false);
 136
 137         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
 138                                             RST_RESERVED_BITS & ~val);
 139         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
 140                                             RST_RESERVED_BITS | val);
 141
 142         if (host->data && host->data->flags & MMC_DATA_READ)
 143                 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
 144
 145         renesas_sdhi_internal_dmac_enable_dma(host, true);
 146 }
 147
 148 static void
 149 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) {
 150         struct renesas_sdhi *priv = host_to_priv(host);
 151
 152         tasklet_schedule(&priv->dma_priv.dma_complete);
 153 }
 154
 155 static void
 156 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
 157                                      struct mmc_data *data)
 158 {
 159         struct scatterlist *sg = host->sg_ptr;
 160         u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
 161
 162         if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len,
 163                         mmc_get_dma_dir(data)))
 164                 goto force_pio;
 165
 166         /* This DMAC cannot handle if buffer is not 8-bytes alignment */
 167         if (!IS_ALIGNED(sg_dma_address(sg), 8)) {
 168                 dma_unmap_sg(&host->pdev->dev, sg, host->sg_len,
 169                              mmc_get_dma_dir(data));
 170                 goto force_pio;
 171         }
 172
 173         if (data->flags & MMC_DATA_READ) {
 174                 dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
 175                 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) &&
 176                     test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
 177                         goto force_pio;
 178         } else {
 179                 dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
 180         }
 181
 182         renesas_sdhi_internal_dmac_enable_dma(host, true);
 183
 184         /* set dma parameters */
 185         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
 186                                             dtran_mode);
 187         renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
 188                                             sg_dma_address(sg));
 189
 190         return;
 191
 192 force_pio:
 193         host->force_pio = true;
 194         renesas_sdhi_internal_dmac_enable_dma(host, false);
 195 }
 196
 197 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
 198 {
 199         struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
 200
 201         tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
 202
 203         /* start the DMAC */
 204         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
 205                                             DTRAN_CTRL_DM_START);
 206 }
 207
 208 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
 209 {
 210         struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
 211         enum dma_data_direction dir;
 212
 213         spin_lock_irq(&host->lock);
 214
 215         if (!host->data)
 216                 goto out;
 217
 218         if (host->data->flags & MMC_DATA_READ)
 219                 dir = DMA_FROM_DEVICE;
 220         else
 221                 dir = DMA_TO_DEVICE;
 222
 223         renesas_sdhi_internal_dmac_enable_dma(host, false);
 224         dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
 225
 226         if (dir == DMA_FROM_DEVICE)
 227                 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
 228
 229         tmio_mmc_do_data_irq(host);
 230 out:
 231         spin_unlock_irq(&host->lock);
 232 }
 233
 234 static void
 235 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
 236                                        struct tmio_mmc_data *pdata)
 237 {
 238         struct renesas_sdhi *priv = host_to_priv(host);
 239
 240         /* Each value is set to non-zero to assume "enabling" each DMA */
 241         host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
 242
 243         tasklet_init(&priv->dma_priv.dma_complete,
 244                      renesas_sdhi_internal_dmac_complete_tasklet_fn,
 245                      (unsigned long)host);
 246         tasklet_init(&host->dma_issue,
 247                      renesas_sdhi_internal_dmac_issue_tasklet_fn,
 248                      (unsigned long)host);
 249 }
 250
 251 static void
 252 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
 253 {
 254         /* Each value is set to zero to assume "disabling" each DMA */
 255         host->chan_rx = host->chan_tx = NULL;
 256 }
 257
 258 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
 259         .start = renesas_sdhi_internal_dmac_start_dma,
 260         .enable = renesas_sdhi_internal_dmac_enable_dma,
 261         .request = renesas_sdhi_internal_dmac_request_dma,
 262         .release = renesas_sdhi_internal_dmac_release_dma,
 263         .abort = renesas_sdhi_internal_dmac_abort_dma,
 264         .dataend = renesas_sdhi_internal_dmac_dataend_dma,
 265 };
 266
 267 /*
 268  * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
 269  * implementation as others may use a different implementation.
 270  */
 271 static const struct soc_device_attribute gen3_soc_whitelist[] = {
 272         /* specific ones */
 273         { .soc_id = "r8a7795", .revision = "ES1.*",
 274           .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
 275         { .soc_id = "r8a7796", .revision = "ES1.0",
 276           .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
 277         /* generic ones */
 278         { .soc_id = "r8a7795" },
 279         { .soc_id = "r8a7796" },
 280         { .soc_id = "r8a77965" },
 281         { .soc_id = "r8a77980" },
 282         { .soc_id = "r8a77995" },
 283         { /* sentinel */ }
 284 };
 285
 286 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
 287 {
 288         const struct soc_device_attribute *soc = soc_device_match(gen3_soc_whitelist);
 289
 290         if (!soc)
 291                 return -ENODEV;
 292
 293         global_flags |= (unsigned long)soc->data;
 294
 295         return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
 296 }
 297
 298 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
 299         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 300                                 pm_runtime_force_resume)
 301         SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
 302                            tmio_mmc_host_runtime_resume,
 303                            NULL)
 304 };
 305
 306 static struct platform_driver renesas_internal_dmac_sdhi_driver = {
 307         .driver         = {
 308                 .name   = "renesas_sdhi_internal_dmac",
 309                 .pm     = &renesas_sdhi_internal_dmac_dev_pm_ops,
 310                 .of_match_table = renesas_sdhi_internal_dmac_of_match,
 311         },
 312         .probe          = renesas_sdhi_internal_dmac_probe,
 313         .remove         = renesas_sdhi_remove,
 314 };
 315
 316 module_platform_driver(renesas_internal_dmac_sdhi_driver);
 317
 318 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
 319 MODULE_AUTHOR("Yoshihiro Shimoda");
 320 MODULE_LICENSE("GPL v2");