drivers/mmc/host/renesas_sdhi_internal_dmac.c

   1 /*
   2  * DMA support for Internal DMAC with SDHI SD/SDIO controller
   3  *
   4  * Copyright (C) 2016-17 Renesas Electronics Corporation
   5  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/device.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/io-64-nonatomic-hi-lo.h>
  16 #include <linux/mfd/tmio.h>
  17 #include <linux/mmc/host.h>
  18 #include <linux/mod_devicetable.h>
  19 #include <linux/module.h>
  20 #include <linux/pagemap.h>
  21 #include <linux/scatterlist.h>
  22 #include <linux/sys_soc.h>
  23
  24 #include "renesas_sdhi.h"
  25 #include "tmio_mmc.h"
  26
  27 #define DM_CM_DTRAN_MODE        0x820
  28 #define DM_CM_DTRAN_CTRL        0x828
  29 #define DM_CM_RST               0x830
  30 #define DM_CM_INFO1             0x840
  31 #define DM_CM_INFO1_MASK        0x848
  32 #define DM_CM_INFO2             0x850
  33 #define DM_CM_INFO2_MASK        0x858
  34 #define DM_DTRAN_ADDR           0x880
  35
  36 /* DM_CM_DTRAN_MODE */
  37 #define DTRAN_MODE_CH_NUM_CH0   0       /* "downstream" = for write commands */
  38 #define DTRAN_MODE_CH_NUM_CH1   BIT(16) /* "uptream" = for read commands */
  39 #define DTRAN_MODE_BUS_WID_TH   (BIT(5) | BIT(4))
  40 #define DTRAN_MODE_ADDR_MODE    BIT(0)  /* 1 = Increment address */
  41
  42 /* DM_CM_DTRAN_CTRL */
  43 #define DTRAN_CTRL_DM_START     BIT(0)
  44
  45 /* DM_CM_RST */
  46 #define RST_DTRANRST1           BIT(9)
  47 #define RST_DTRANRST0           BIT(8)
  48 #define RST_RESERVED_BITS       GENMASK_ULL(32, 0)
  49
  50 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */
  51 #define INFO1_CLEAR             0
  52 #define INFO1_DTRANEND1         BIT(17)
  53 #define INFO1_DTRANEND0         BIT(16)
  54
  55 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */
  56 #define INFO2_DTRANERR1         BIT(17)
  57 #define INFO2_DTRANERR0         BIT(16)
  58
  59 /*
  60  * Specification of this driver:
  61  * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
  62  * - Since this SDHI DMAC register set has 16 but 32-bit width, we
  63  *   need a custom accessor.
  64  */
  65
  66 static unsigned long global_flags;
  67 /*
  68  * Workaround for avoiding to use RX DMAC by multiple channels.
  69  * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use
  70  * RX DMAC simultaneously, sometimes hundreds of bytes data are not
  71  * stored into the system memory even if the DMAC interrupt happened.
  72  * So, this driver then uses one RX DMAC channel only.
  73  */
  74 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY  0
  75 #define SDHI_INTERNAL_DMAC_RX_IN_USE    1
  76
  77 /* Definitions for sampling clocks */
  78 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
  79         {
  80                 .clk_rate = 0,
  81                 .tap = 0x00000300,
  82         },
  83 };
  84
  85 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
  86         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  87                           TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
  88         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  89                           MMC_CAP_CMD23,
  90         .capabilities2  = MMC_CAP2_NO_WRITE_PROTECT,
  91         .bus_shift      = 2,
  92         .scc_offset     = 0x1000,
  93         .taps           = rcar_gen3_scc_taps,
  94         .taps_num       = ARRAY_SIZE(rcar_gen3_scc_taps),
  95         /* DMAC can handle 0xffffffff blk count but only 1 segment */
  96         .max_blk_count  = 0xffffffff,
  97         .max_segs       = 1,
  98 };
  99
 100 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
 101         { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
 102         { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
 103         { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
 104         {},
 105 };
 106 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
 107
 108 static void
 109 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
 110                                     int addr, u64 val)
 111 {
 112         writeq(val, host->ctl + addr);
 113 }
 114
 115 static void
 116 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
 117 {
 118         struct renesas_sdhi *priv = host_to_priv(host);
 119
 120         if (!host->chan_tx || !host->chan_rx)
 121                 return;
 122
 123         if (!enable)
 124                 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
 125                                                     INFO1_CLEAR);
 126
 127         if (priv->dma_priv.enable)
 128                 priv->dma_priv.enable(host, enable);
 129 }
 130
 131 static void
 132 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
 133         u64 val = RST_DTRANRST1 | RST_DTRANRST0;
 134
 135         renesas_sdhi_internal_dmac_enable_dma(host, false);
 136
 137         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
 138                                             RST_RESERVED_BITS & ~val);
 139         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
 140                                             RST_RESERVED_BITS | val);
 141
 142         clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
 143
 144         renesas_sdhi_internal_dmac_enable_dma(host, true);
 145 }
 146
 147 static void
 148 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) {
 149         struct renesas_sdhi *priv = host_to_priv(host);
 150
 151         tasklet_schedule(&priv->dma_priv.dma_complete);
 152 }
 153
 154 static void
 155 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
 156                                      struct mmc_data *data)
 157 {
 158         struct scatterlist *sg = host->sg_ptr;
 159         u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
 160
 161         if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len,
 162                         mmc_get_dma_dir(data)))
 163                 goto force_pio;
 164
 165         /* This DMAC cannot handle if buffer is not 8-bytes alignment */
 166         if (!IS_ALIGNED(sg_dma_address(sg), 8))
 167                 goto force_pio_with_unmap;
 168
 169         if (data->flags & MMC_DATA_READ) {
 170                 dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
 171                 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) &&
 172                     test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
 173                         goto force_pio_with_unmap;
 174         } else {
 175                 dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
 176         }
 177
 178         renesas_sdhi_internal_dmac_enable_dma(host, true);
 179
 180         /* set dma parameters */
 181         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
 182                                             dtran_mode);
 183         renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
 184                                             sg_dma_address(sg));
 185
 186         return;
 187
 188 force_pio_with_unmap:
 189         dma_unmap_sg(&host->pdev->dev, sg, host->sg_len, mmc_get_dma_dir(data));
 190
 191 force_pio:
 192         host->force_pio = true;
 193         renesas_sdhi_internal_dmac_enable_dma(host, false);
 194 }
 195
 196 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
 197 {
 198         struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
 199
 200         tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
 201
 202         /* start the DMAC */
 203         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
 204                                             DTRAN_CTRL_DM_START);
 205 }
 206
 207 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
 208 {
 209         struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
 210         enum dma_data_direction dir;
 211
 212         spin_lock_irq(&host->lock);
 213
 214         if (!host->data)
 215                 goto out;
 216
 217         if (host->data->flags & MMC_DATA_READ)
 218                 dir = DMA_FROM_DEVICE;
 219         else
 220                 dir = DMA_TO_DEVICE;
 221
 222         renesas_sdhi_internal_dmac_enable_dma(host, false);
 223         dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
 224
 225         if (dir == DMA_FROM_DEVICE)
 226                 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
 227
 228         tmio_mmc_do_data_irq(host);
 229 out:
 230         spin_unlock_irq(&host->lock);
 231 }
 232
 233 static void
 234 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
 235                                        struct tmio_mmc_data *pdata)
 236 {
 237         struct renesas_sdhi *priv = host_to_priv(host);
 238
 239         /* Each value is set to non-zero to assume "enabling" each DMA */
 240         host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
 241
 242         tasklet_init(&priv->dma_priv.dma_complete,
 243                      renesas_sdhi_internal_dmac_complete_tasklet_fn,
 244                      (unsigned long)host);
 245         tasklet_init(&host->dma_issue,
 246                      renesas_sdhi_internal_dmac_issue_tasklet_fn,
 247                      (unsigned long)host);
 248 }
 249
 250 static void
 251 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
 252 {
 253         /* Each value is set to zero to assume "disabling" each DMA */
 254         host->chan_rx = host->chan_tx = NULL;
 255 }
 256
 257 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
 258         .start = renesas_sdhi_internal_dmac_start_dma,
 259         .enable = renesas_sdhi_internal_dmac_enable_dma,
 260         .request = renesas_sdhi_internal_dmac_request_dma,
 261         .release = renesas_sdhi_internal_dmac_release_dma,
 262         .abort = renesas_sdhi_internal_dmac_abort_dma,
 263         .dataend = renesas_sdhi_internal_dmac_dataend_dma,
 264 };
 265
 266 /*
 267  * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
 268  * implementation as others may use a different implementation.
 269  */
 270 static const struct soc_device_attribute gen3_soc_whitelist[] = {
 271         /* specific ones */
 272         { .soc_id = "r8a7795", .revision = "ES1.*",
 273           .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
 274         { .soc_id = "r8a7796", .revision = "ES1.0",
 275           .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
 276         /* generic ones */
 277         { .soc_id = "r8a7795" },
 278         { .soc_id = "r8a7796" },
 279         { .soc_id = "r8a77965" },
 280         { .soc_id = "r8a77980" },
 281         { .soc_id = "r8a77995" },
 282         { /* sentinel */ }
 283 };
 284
 285 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
 286 {
 287         const struct soc_device_attribute *soc = soc_device_match(gen3_soc_whitelist);
 288
 289         if (!soc)
 290                 return -ENODEV;
 291
 292         global_flags |= (unsigned long)soc->data;
 293
 294         return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
 295 }
 296
 297 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
 298         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 299                                 pm_runtime_force_resume)
 300         SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
 301                            tmio_mmc_host_runtime_resume,
 302                            NULL)
 303 };
 304
 305 static struct platform_driver renesas_internal_dmac_sdhi_driver = {
 306         .driver         = {
 307                 .name   = "renesas_sdhi_internal_dmac",
 308                 .pm     = &renesas_sdhi_internal_dmac_dev_pm_ops,
 309                 .of_match_table = renesas_sdhi_internal_dmac_of_match,
 310         },
 311         .probe          = renesas_sdhi_internal_dmac_probe,
 312         .remove         = renesas_sdhi_remove,
 313 };
 314
 315 module_platform_driver(renesas_internal_dmac_sdhi_driver);
 316
 317 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
 318 MODULE_AUTHOR("Yoshihiro Shimoda");
 319 MODULE_LICENSE("GPL v2");