drivers/mmc/host/atmel-mci.c

   1 /*
   2  * Atmel MultiMedia Card Interface driver
   3  *
   4  * Copyright (C) 2004-2008 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/blkdev.h>
  11 #include <linux/clk.h>
  12 #include <linux/debugfs.h>
  13 #include <linux/device.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/gpio.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/ioport.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_gpio.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <linux/stat.h>
  31 #include <linux/types.h>
  32
  33 #include <linux/mmc/host.h>
  34 #include <linux/mmc/sdio.h>
  35
  36 #include <linux/atmel-mci.h>
  37 #include <linux/atmel_pdc.h>
  38 #include <linux/pm.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/pinctrl/consumer.h>
  41
  42 #include <asm/cacheflush.h>
  43 #include <asm/io.h>
  44 #include <asm/unaligned.h>
  45
  46 /*
  47  * Superset of MCI IP registers integrated in Atmel AT91 Processor
  48  * Registers and bitfields marked with [2] are only available in MCI2
  49  */
  50
  51 /* MCI Register Definitions */
  52 #define ATMCI_CR                        0x0000  /* Control */
  53 #define         ATMCI_CR_MCIEN                  BIT(0)          /* MCI Enable */
  54 #define         ATMCI_CR_MCIDIS                 BIT(1)          /* MCI Disable */
  55 #define         ATMCI_CR_PWSEN                  BIT(2)          /* Power Save Enable */
  56 #define         ATMCI_CR_PWSDIS                 BIT(3)          /* Power Save Disable */
  57 #define         ATMCI_CR_SWRST                  BIT(7)          /* Software Reset */
  58 #define ATMCI_MR                        0x0004  /* Mode */
  59 #define         ATMCI_MR_CLKDIV(x)              ((x) <<  0)     /* Clock Divider */
  60 #define         ATMCI_MR_PWSDIV(x)              ((x) <<  8)     /* Power Saving Divider */
  61 #define         ATMCI_MR_RDPROOF                BIT(11)         /* Read Proof */
  62 #define         ATMCI_MR_WRPROOF                BIT(12)         /* Write Proof */
  63 #define         ATMCI_MR_PDCFBYTE               BIT(13)         /* Force Byte Transfer */
  64 #define         ATMCI_MR_PDCPADV                BIT(14)         /* Padding Value */
  65 #define         ATMCI_MR_PDCMODE                BIT(15)         /* PDC-oriented Mode */
  66 #define         ATMCI_MR_CLKODD(x)              ((x) << 16)     /* LSB of Clock Divider */
  67 #define ATMCI_DTOR                      0x0008  /* Data Timeout */
  68 #define         ATMCI_DTOCYC(x)                 ((x) <<  0)     /* Data Timeout Cycles */
  69 #define         ATMCI_DTOMUL(x)                 ((x) <<  4)     /* Data Timeout Multiplier */
  70 #define ATMCI_SDCR                      0x000c  /* SD Card / SDIO */
  71 #define         ATMCI_SDCSEL_SLOT_A             (0 <<  0)       /* Select SD slot A */
  72 #define         ATMCI_SDCSEL_SLOT_B             (1 <<  0)       /* Select SD slot A */
  73 #define         ATMCI_SDCSEL_MASK               (3 <<  0)
  74 #define         ATMCI_SDCBUS_1BIT               (0 <<  6)       /* 1-bit data bus */
  75 #define         ATMCI_SDCBUS_4BIT               (2 <<  6)       /* 4-bit data bus */
  76 #define         ATMCI_SDCBUS_8BIT               (3 <<  6)       /* 8-bit data bus[2] */
  77 #define         ATMCI_SDCBUS_MASK               (3 <<  6)
  78 #define ATMCI_ARGR                      0x0010  /* Command Argument */
  79 #define ATMCI_CMDR                      0x0014  /* Command */
  80 #define         ATMCI_CMDR_CMDNB(x)             ((x) <<  0)     /* Command Opcode */
  81 #define         ATMCI_CMDR_RSPTYP_NONE          (0 <<  6)       /* No response */
  82 #define         ATMCI_CMDR_RSPTYP_48BIT         (1 <<  6)       /* 48-bit response */
  83 #define         ATMCI_CMDR_RSPTYP_136BIT        (2 <<  6)       /* 136-bit response */
  84 #define         ATMCI_CMDR_SPCMD_INIT           (1 <<  8)       /* Initialization command */
  85 #define         ATMCI_CMDR_SPCMD_SYNC           (2 <<  8)       /* Synchronized command */
  86 #define         ATMCI_CMDR_SPCMD_INT            (4 <<  8)       /* Interrupt command */
  87 #define         ATMCI_CMDR_SPCMD_INTRESP        (5 <<  8)       /* Interrupt response */
  88 #define         ATMCI_CMDR_OPDCMD               (1 << 11)       /* Open Drain */
  89 #define         ATMCI_CMDR_MAXLAT_5CYC          (0 << 12)       /* Max latency 5 cycles */
  90 #define         ATMCI_CMDR_MAXLAT_64CYC         (1 << 12)       /* Max latency 64 cycles */
  91 #define         ATMCI_CMDR_START_XFER           (1 << 16)       /* Start data transfer */
  92 #define         ATMCI_CMDR_STOP_XFER            (2 << 16)       /* Stop data transfer */
  93 #define         ATMCI_CMDR_TRDIR_WRITE          (0 << 18)       /* Write data */
  94 #define         ATMCI_CMDR_TRDIR_READ           (1 << 18)       /* Read data */
  95 #define         ATMCI_CMDR_BLOCK                (0 << 19)       /* Single-block transfer */
  96 #define         ATMCI_CMDR_MULTI_BLOCK          (1 << 19)       /* Multi-block transfer */
  97 #define         ATMCI_CMDR_STREAM               (2 << 19)       /* MMC Stream transfer */
  98 #define         ATMCI_CMDR_SDIO_BYTE            (4 << 19)       /* SDIO Byte transfer */
  99 #define         ATMCI_CMDR_SDIO_BLOCK           (5 << 19)       /* SDIO Block transfer */
 100 #define         ATMCI_CMDR_SDIO_SUSPEND         (1 << 24)       /* SDIO Suspend Command */
 101 #define         ATMCI_CMDR_SDIO_RESUME          (2 << 24)       /* SDIO Resume Command */
 102 #define ATMCI_BLKR                      0x0018  /* Block */
 103 #define         ATMCI_BCNT(x)                   ((x) <<  0)     /* Data Block Count */
 104 #define         ATMCI_BLKLEN(x)                 ((x) << 16)     /* Data Block Length */
 105 #define ATMCI_CSTOR                     0x001c  /* Completion Signal Timeout[2] */
 106 #define         ATMCI_CSTOCYC(x)                ((x) <<  0)     /* CST cycles */
 107 #define         ATMCI_CSTOMUL(x)                ((x) <<  4)     /* CST multiplier */
 108 #define ATMCI_RSPR                      0x0020  /* Response 0 */
 109 #define ATMCI_RSPR1                     0x0024  /* Response 1 */
 110 #define ATMCI_RSPR2                     0x0028  /* Response 2 */
 111 #define ATMCI_RSPR3                     0x002c  /* Response 3 */
 112 #define ATMCI_RDR                       0x0030  /* Receive Data */
 113 #define ATMCI_TDR                       0x0034  /* Transmit Data */
 114 #define ATMCI_SR                        0x0040  /* Status */
 115 #define ATMCI_IER                       0x0044  /* Interrupt Enable */
 116 #define ATMCI_IDR                       0x0048  /* Interrupt Disable */
 117 #define ATMCI_IMR                       0x004c  /* Interrupt Mask */
 118 #define         ATMCI_CMDRDY                    BIT(0)          /* Command Ready */
 119 #define         ATMCI_RXRDY                     BIT(1)          /* Receiver Ready */
 120 #define         ATMCI_TXRDY                     BIT(2)          /* Transmitter Ready */
 121 #define         ATMCI_BLKE                      BIT(3)          /* Data Block Ended */
 122 #define         ATMCI_DTIP                      BIT(4)          /* Data Transfer In Progress */
 123 #define         ATMCI_NOTBUSY                   BIT(5)          /* Data Not Busy */
 124 #define         ATMCI_ENDRX                     BIT(6)          /* End of RX Buffer */
 125 #define         ATMCI_ENDTX                     BIT(7)          /* End of TX Buffer */
 126 #define         ATMCI_SDIOIRQA                  BIT(8)          /* SDIO IRQ in slot A */
 127 #define         ATMCI_SDIOIRQB                  BIT(9)          /* SDIO IRQ in slot B */
 128 #define         ATMCI_SDIOWAIT                  BIT(12)         /* SDIO Read Wait Operation Status */
 129 #define         ATMCI_CSRCV                     BIT(13)         /* CE-ATA Completion Signal Received */
 130 #define         ATMCI_RXBUFF                    BIT(14)         /* RX Buffer Full */
 131 #define         ATMCI_TXBUFE                    BIT(15)         /* TX Buffer Empty */
 132 #define         ATMCI_RINDE                     BIT(16)         /* Response Index Error */
 133 #define         ATMCI_RDIRE                     BIT(17)         /* Response Direction Error */
 134 #define         ATMCI_RCRCE                     BIT(18)         /* Response CRC Error */
 135 #define         ATMCI_RENDE                     BIT(19)         /* Response End Bit Error */
 136 #define         ATMCI_RTOE                      BIT(20)         /* Response Time-Out Error */
 137 #define         ATMCI_DCRCE                     BIT(21)         /* Data CRC Error */
 138 #define         ATMCI_DTOE                      BIT(22)         /* Data Time-Out Error */
 139 #define         ATMCI_CSTOE                     BIT(23)         /* Completion Signal Time-out Error */
 140 #define         ATMCI_BLKOVRE                   BIT(24)         /* DMA Block Overrun Error */
 141 #define         ATMCI_DMADONE                   BIT(25)         /* DMA Transfer Done */
 142 #define         ATMCI_FIFOEMPTY                 BIT(26)         /* FIFO Empty Flag */
 143 #define         ATMCI_XFRDONE                   BIT(27)         /* Transfer Done Flag */
 144 #define         ATMCI_ACKRCV                    BIT(28)         /* Boot Operation Acknowledge Received */
 145 #define         ATMCI_ACKRCVE                   BIT(29)         /* Boot Operation Acknowledge Error */
 146 #define         ATMCI_OVRE                      BIT(30)         /* RX Overrun Error */
 147 #define         ATMCI_UNRE                      BIT(31)         /* TX Underrun Error */
 148 #define ATMCI_DMA                       0x0050  /* DMA Configuration[2] */
 149 #define         ATMCI_DMA_OFFSET(x)             ((x) <<  0)     /* DMA Write Buffer Offset */
 150 #define         ATMCI_DMA_CHKSIZE(x)            ((x) <<  4)     /* DMA Channel Read and Write Chunk Size */
 151 #define         ATMCI_DMAEN                     BIT(8)  /* DMA Hardware Handshaking Enable */
 152 #define ATMCI_CFG                       0x0054  /* Configuration[2] */
 153 #define         ATMCI_CFG_FIFOMODE_1DATA        BIT(0)          /* MCI Internal FIFO control mode */
 154 #define         ATMCI_CFG_FERRCTRL_COR          BIT(4)          /* Flow Error flag reset control mode */
 155 #define         ATMCI_CFG_HSMODE                BIT(8)          /* High Speed Mode */
 156 #define         ATMCI_CFG_LSYNC                 BIT(12)         /* Synchronize on the last block */
 157 #define ATMCI_WPMR                      0x00e4  /* Write Protection Mode[2] */
 158 #define         ATMCI_WP_EN                     BIT(0)          /* WP Enable */
 159 #define         ATMCI_WP_KEY                    (0x4d4349 << 8) /* WP Key */
 160 #define ATMCI_WPSR                      0x00e8  /* Write Protection Status[2] */
 161 #define         ATMCI_GET_WP_VS(x)              ((x) & 0x0f)
 162 #define         ATMCI_GET_WP_VSRC(x)            (((x) >> 8) & 0xffff)
 163 #define ATMCI_VERSION                   0x00FC  /* Version */
 164 #define ATMCI_FIFO_APERTURE             0x0200  /* FIFO Aperture[2] */
 165
 166 /* This is not including the FIFO Aperture on MCI2 */
 167 #define ATMCI_REGS_SIZE         0x100
 168
 169 /* Register access macros */
 170 #define atmci_readl(port, reg)                          \
 171         __raw_readl((port)->regs + reg)
 172 #define atmci_writel(port, reg, value)                  \
 173         __raw_writel((value), (port)->regs + reg)
 174
 175 #define AUTOSUSPEND_DELAY       50
 176
 177 #define ATMCI_DATA_ERROR_FLAGS  (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
 178 #define ATMCI_DMA_THRESHOLD     16
 179
 180 enum {
 181         EVENT_CMD_RDY = 0,
 182         EVENT_XFER_COMPLETE,
 183         EVENT_NOTBUSY,
 184         EVENT_DATA_ERROR,
 185 };
 186
 187 enum atmel_mci_state {
 188         STATE_IDLE = 0,
 189         STATE_SENDING_CMD,
 190         STATE_DATA_XFER,
 191         STATE_WAITING_NOTBUSY,
 192         STATE_SENDING_STOP,
 193         STATE_END_REQUEST,
 194 };
 195
 196 enum atmci_xfer_dir {
 197         XFER_RECEIVE = 0,
 198         XFER_TRANSMIT,
 199 };
 200
 201 enum atmci_pdc_buf {
 202         PDC_FIRST_BUF = 0,
 203         PDC_SECOND_BUF,
 204 };
 205
 206 struct atmel_mci_caps {
 207         bool    has_dma_conf_reg;
 208         bool    has_pdc;
 209         bool    has_cfg_reg;
 210         bool    has_cstor_reg;
 211         bool    has_highspeed;
 212         bool    has_rwproof;
 213         bool    has_odd_clk_div;
 214         bool    has_bad_data_ordering;
 215         bool    need_reset_after_xfer;
 216         bool    need_blksz_mul_4;
 217         bool    need_notbusy_for_read_ops;
 218 };
 219
 220 struct atmel_mci_dma {
 221         struct dma_chan                 *chan;
 222         struct dma_async_tx_descriptor  *data_desc;
 223 };
 224
 225 /**
 226  * struct atmel_mci - MMC controller state shared between all slots
 227  * @lock: Spinlock protecting the queue and associated data.
 228  * @regs: Pointer to MMIO registers.
 229  * @sg: Scatterlist entry currently being processed by PIO or PDC code.
 230  * @pio_offset: Offset into the current scatterlist entry.
 231  * @buffer: Buffer used if we don't have the r/w proof capability. We
 232  *      don't have the time to switch pdc buffers so we have to use only
 233  *      one buffer for the full transaction.
 234  * @buf_size: size of the buffer.
 235  * @phys_buf_addr: buffer address needed for pdc.
 236  * @cur_slot: The slot which is currently using the controller.
 237  * @mrq: The request currently being processed on @cur_slot,
 238  *      or NULL if the controller is idle.
 239  * @cmd: The command currently being sent to the card, or NULL.
 240  * @data: The data currently being transferred, or NULL if no data
 241  *      transfer is in progress.
 242  * @data_size: just data->blocks * data->blksz.
 243  * @dma: DMA client state.
 244  * @data_chan: DMA channel being used for the current data transfer.
 245  * @cmd_status: Snapshot of SR taken upon completion of the current
 246  *      command. Only valid when EVENT_CMD_COMPLETE is pending.
 247  * @data_status: Snapshot of SR taken upon completion of the current
 248  *      data transfer. Only valid when EVENT_DATA_COMPLETE or
 249  *      EVENT_DATA_ERROR is pending.
 250  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
 251  *      to be sent.
 252  * @tasklet: Tasklet running the request state machine.
 253  * @pending_events: Bitmask of events flagged by the interrupt handler
 254  *      to be processed by the tasklet.
 255  * @completed_events: Bitmask of events which the state machine has
 256  *      processed.
 257  * @state: Tasklet state.
 258  * @queue: List of slots waiting for access to the controller.
 259  * @need_clock_update: Update the clock rate before the next request.
 260  * @need_reset: Reset controller before next request.
 261  * @timer: Timer to balance the data timeout error flag which cannot rise.
 262  * @mode_reg: Value of the MR register.
 263  * @cfg_reg: Value of the CFG register.
 264  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
 265  *      rate and timeout calculations.
 266  * @mapbase: Physical address of the MMIO registers.
 267  * @mck: The peripheral bus clock hooked up to the MMC controller.
 268  * @pdev: Platform device associated with the MMC controller.
 269  * @slot: Slots sharing this MMC controller.
 270  * @caps: MCI capabilities depending on MCI version.
 271  * @prepare_data: function to setup MCI before data transfer which
 272  * depends on MCI capabilities.
 273  * @submit_data: function to start data transfer which depends on MCI
 274  * capabilities.
 275  * @stop_transfer: function to stop data transfer which depends on MCI
 276  * capabilities.
 277  *
 278  * Locking
 279  * =======
 280  *
 281  * @lock is a softirq-safe spinlock protecting @queue as well as
 282  * @cur_slot, @mrq and @state. These must always be updated
 283  * at the same time while holding @lock.
 284  *
 285  * @lock also protects mode_reg and need_clock_update since these are
 286  * used to synchronize mode register updates with the queue
 287  * processing.
 288  *
 289  * The @mrq field of struct atmel_mci_slot is also protected by @lock,
 290  * and must always be written at the same time as the slot is added to
 291  * @queue.
 292  *
 293  * @pending_events and @completed_events are accessed using atomic bit
 294  * operations, so they don't need any locking.
 295  *
 296  * None of the fields touched by the interrupt handler need any
 297  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
 298  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
 299  * interrupts must be disabled and @data_status updated with a
 300  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
 301  * CMDRDY interrupt must be disabled and @cmd_status updated with a
 302  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
 303  * bytes_xfered field of @data must be written. This is ensured by
 304  * using barriers.
 305  */
 306 struct atmel_mci {
 307         spinlock_t              lock;
 308         void __iomem            *regs;
 309
 310         struct scatterlist      *sg;
 311         unsigned int            sg_len;
 312         unsigned int            pio_offset;
 313         unsigned int            *buffer;
 314         unsigned int            buf_size;
 315         dma_addr_t              buf_phys_addr;
 316
 317         struct atmel_mci_slot   *cur_slot;
 318         struct mmc_request      *mrq;
 319         struct mmc_command      *cmd;
 320         struct mmc_data         *data;
 321         unsigned int            data_size;
 322
 323         struct atmel_mci_dma    dma;
 324         struct dma_chan         *data_chan;
 325         struct dma_slave_config dma_conf;
 326
 327         u32                     cmd_status;
 328         u32                     data_status;
 329         u32                     stop_cmdr;
 330
 331         struct tasklet_struct   tasklet;
 332         unsigned long           pending_events;
 333         unsigned long           completed_events;
 334         enum atmel_mci_state    state;
 335         struct list_head        queue;
 336
 337         bool                    need_clock_update;
 338         bool                    need_reset;
 339         struct timer_list       timer;
 340         u32                     mode_reg;
 341         u32                     cfg_reg;
 342         unsigned long           bus_hz;
 343         unsigned long           mapbase;
 344         struct clk              *mck;
 345         struct platform_device  *pdev;
 346
 347         struct atmel_mci_slot   *slot[ATMCI_MAX_NR_SLOTS];
 348
 349         struct atmel_mci_caps   caps;
 350
 351         u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
 352         void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
 353         void (*stop_transfer)(struct atmel_mci *host);
 354 };
 355
 356 /**
 357  * struct atmel_mci_slot - MMC slot state
 358  * @mmc: The mmc_host representing this slot.
 359  * @host: The MMC controller this slot is using.
 360  * @sdc_reg: Value of SDCR to be written before using this slot.
 361  * @sdio_irq: SDIO irq mask for this slot.
 362  * @mrq: mmc_request currently being processed or waiting to be
 363  *      processed, or NULL when the slot is idle.
 364  * @queue_node: List node for placing this node in the @queue list of
 365  *      &struct atmel_mci.
 366  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
 367  * @flags: Random state bits associated with the slot.
 368  * @detect_pin: GPIO pin used for card detection, or negative if not
 369  *      available.
 370  * @wp_pin: GPIO pin used for card write protect sending, or negative
 371  *      if not available.
 372  * @detect_is_active_high: The state of the detect pin when it is active.
 373  * @detect_timer: Timer used for debouncing @detect_pin interrupts.
 374  */
 375 struct atmel_mci_slot {
 376         struct mmc_host         *mmc;
 377         struct atmel_mci        *host;
 378
 379         u32                     sdc_reg;
 380         u32                     sdio_irq;
 381
 382         struct mmc_request      *mrq;
 383         struct list_head        queue_node;
 384
 385         unsigned int            clock;
 386         unsigned long           flags;
 387 #define ATMCI_CARD_PRESENT      0
 388 #define ATMCI_CARD_NEED_INIT    1
 389 #define ATMCI_SHUTDOWN          2
 390
 391         int                     detect_pin;
 392         int                     wp_pin;
 393         bool                    detect_is_active_high;
 394
 395         struct timer_list       detect_timer;
 396 };
 397
 398 #define atmci_test_and_clear_pending(host, event)               \
 399         test_and_clear_bit(event, &host->pending_events)
 400 #define atmci_set_completed(host, event)                        \
 401         set_bit(event, &host->completed_events)
 402 #define atmci_set_pending(host, event)                          \
 403         set_bit(event, &host->pending_events)
 404
 405 /*
 406  * The debugfs stuff below is mostly optimized away when
 407  * CONFIG_DEBUG_FS is not set.
 408  */
 409 static int atmci_req_show(struct seq_file *s, void *v)
 410 {
 411         struct atmel_mci_slot   *slot = s->private;
 412         struct mmc_request      *mrq;
 413         struct mmc_command      *cmd;
 414         struct mmc_command      *stop;
 415         struct mmc_data         *data;
 416
 417         /* Make sure we get a consistent snapshot */
 418         spin_lock_bh(&slot->host->lock);
 419         mrq = slot->mrq;
 420
 421         if (mrq) {
 422                 cmd = mrq->cmd;
 423                 data = mrq->data;
 424                 stop = mrq->stop;
 425
 426                 if (cmd)
 427                         seq_printf(s,
 428                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 429                                 cmd->opcode, cmd->arg, cmd->flags,
 430                                 cmd->resp[0], cmd->resp[1], cmd->resp[2],
 431                                 cmd->resp[3], cmd->error);
 432                 if (data)
 433                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 434                                 data->bytes_xfered, data->blocks,
 435                                 data->blksz, data->flags, data->error);
 436                 if (stop)
 437                         seq_printf(s,
 438                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 439                                 stop->opcode, stop->arg, stop->flags,
 440                                 stop->resp[0], stop->resp[1], stop->resp[2],
 441                                 stop->resp[3], stop->error);
 442         }
 443
 444         spin_unlock_bh(&slot->host->lock);
 445
 446         return 0;
 447 }
 448
 449 DEFINE_SHOW_ATTRIBUTE(atmci_req);
 450
 451 static void atmci_show_status_reg(struct seq_file *s,
 452                 const char *regname, u32 value)
 453 {
 454         static const char       *sr_bit[] = {
 455                 [0]     = "CMDRDY",
 456                 [1]     = "RXRDY",
 457                 [2]     = "TXRDY",
 458                 [3]     = "BLKE",
 459                 [4]     = "DTIP",
 460                 [5]     = "NOTBUSY",
 461                 [6]     = "ENDRX",
 462                 [7]     = "ENDTX",
 463                 [8]     = "SDIOIRQA",
 464                 [9]     = "SDIOIRQB",
 465                 [12]    = "SDIOWAIT",
 466                 [14]    = "RXBUFF",
 467                 [15]    = "TXBUFE",
 468                 [16]    = "RINDE",
 469                 [17]    = "RDIRE",
 470                 [18]    = "RCRCE",
 471                 [19]    = "RENDE",
 472                 [20]    = "RTOE",
 473                 [21]    = "DCRCE",
 474                 [22]    = "DTOE",
 475                 [23]    = "CSTOE",
 476                 [24]    = "BLKOVRE",
 477                 [25]    = "DMADONE",
 478                 [26]    = "FIFOEMPTY",
 479                 [27]    = "XFRDONE",
 480                 [30]    = "OVRE",
 481                 [31]    = "UNRE",
 482         };
 483         unsigned int            i;
 484
 485         seq_printf(s, "%s:\t0x%08x", regname, value);
 486         for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
 487                 if (value & (1 << i)) {
 488                         if (sr_bit[i])
 489                                 seq_printf(s, " %s", sr_bit[i]);
 490                         else
 491                                 seq_puts(s, " UNKNOWN");
 492                 }
 493         }
 494         seq_putc(s, '\n');
 495 }
 496
 497 static int atmci_regs_show(struct seq_file *s, void *v)
 498 {
 499         struct atmel_mci        *host = s->private;
 500         u32                     *buf;
 501         int                     ret = 0;
 502
 503
 504         buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
 505         if (!buf)
 506                 return -ENOMEM;
 507
 508         pm_runtime_get_sync(&host->pdev->dev);
 509
 510         /*
 511          * Grab a more or less consistent snapshot. Note that we're
 512          * not disabling interrupts, so IMR and SR may not be
 513          * consistent.
 514          */
 515         spin_lock_bh(&host->lock);
 516         memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
 517         spin_unlock_bh(&host->lock);
 518
 519         pm_runtime_mark_last_busy(&host->pdev->dev);
 520         pm_runtime_put_autosuspend(&host->pdev->dev);
 521
 522         seq_printf(s, "MR:\t0x%08x%s%s ",
 523                         buf[ATMCI_MR / 4],
 524                         buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
 525                         buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
 526         if (host->caps.has_odd_clk_div)
 527                 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
 528                                 ((buf[ATMCI_MR / 4] & 0xff) << 1)
 529                                 | ((buf[ATMCI_MR / 4] >> 16) & 1));
 530         else
 531                 seq_printf(s, "CLKDIV=%u\n",
 532                                 (buf[ATMCI_MR / 4] & 0xff));
 533         seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
 534         seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
 535         seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
 536         seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
 537                         buf[ATMCI_BLKR / 4],
 538                         buf[ATMCI_BLKR / 4] & 0xffff,
 539                         (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
 540         if (host->caps.has_cstor_reg)
 541                 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
 542
 543         /* Don't read RSPR and RDR; it will consume the data there */
 544
 545         atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
 546         atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
 547
 548         if (host->caps.has_dma_conf_reg) {
 549                 u32 val;
 550
 551                 val = buf[ATMCI_DMA / 4];
 552                 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
 553                                 val, val & 3,
 554                                 ((val >> 4) & 3) ?
 555                                         1 << (((val >> 4) & 3) + 1) : 1,
 556                                 val & ATMCI_DMAEN ? " DMAEN" : "");
 557         }
 558         if (host->caps.has_cfg_reg) {
 559                 u32 val;
 560
 561                 val = buf[ATMCI_CFG / 4];
 562                 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
 563                                 val,
 564                                 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
 565                                 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
 566                                 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
 567                                 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
 568         }
 569
 570         kfree(buf);
 571
 572         return ret;
 573 }
 574
 575 DEFINE_SHOW_ATTRIBUTE(atmci_regs);
 576
 577 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
 578 {
 579         struct mmc_host         *mmc = slot->mmc;
 580         struct atmel_mci        *host = slot->host;
 581         struct dentry           *root;
 582         struct dentry           *node;
 583
 584         root = mmc->debugfs_root;
 585         if (!root)
 586                 return;
 587
 588         node = debugfs_create_file("regs", S_IRUSR, root, host,
 589                                    &atmci_regs_fops);
 590         if (IS_ERR(node))
 591                 return;
 592         if (!node)
 593                 goto err;
 594
 595         node = debugfs_create_file("req", S_IRUSR, root, slot,
 596                                    &atmci_req_fops);
 597         if (!node)
 598                 goto err;
 599
 600         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 601         if (!node)
 602                 goto err;
 603
 604         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 605                                      (u32 *)&host->pending_events);
 606         if (!node)
 607                 goto err;
 608
 609         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 610                                      (u32 *)&host->completed_events);
 611         if (!node)
 612                 goto err;
 613
 614         return;
 615
 616 err:
 617         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 618 }
 619
 620 #if defined(CONFIG_OF)
 621 static const struct of_device_id atmci_dt_ids[] = {
 622         { .compatible = "atmel,hsmci" },
 623         { /* sentinel */ }
 624 };
 625
 626 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
 627
 628 static struct mci_platform_data*
 629 atmci_of_init(struct platform_device *pdev)
 630 {
 631         struct device_node *np = pdev->dev.of_node;
 632         struct device_node *cnp;
 633         struct mci_platform_data *pdata;
 634         u32 slot_id;
 635
 636         if (!np) {
 637                 dev_err(&pdev->dev, "device node not found\n");
 638                 return ERR_PTR(-EINVAL);
 639         }
 640
 641         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 642         if (!pdata)
 643                 return ERR_PTR(-ENOMEM);
 644
 645         for_each_child_of_node(np, cnp) {
 646                 if (of_property_read_u32(cnp, "reg", &slot_id)) {
 647                         dev_warn(&pdev->dev, "reg property is missing for %pOF\n",
 648                                  cnp);
 649                         continue;
 650                 }
 651
 652                 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
 653                         dev_warn(&pdev->dev, "can't have more than %d slots\n",
 654                                  ATMCI_MAX_NR_SLOTS);
 655                         of_node_put(cnp);
 656                         break;
 657                 }
 658
 659                 if (of_property_read_u32(cnp, "bus-width",
 660                                          &pdata->slot[slot_id].bus_width))
 661                         pdata->slot[slot_id].bus_width = 1;
 662
 663                 pdata->slot[slot_id].detect_pin =
 664                         of_get_named_gpio(cnp, "cd-gpios", 0);
 665
 666                 pdata->slot[slot_id].detect_is_active_high =
 667                         of_property_read_bool(cnp, "cd-inverted");
 668
 669                 pdata->slot[slot_id].non_removable =
 670                         of_property_read_bool(cnp, "non-removable");
 671
 672                 pdata->slot[slot_id].wp_pin =
 673                         of_get_named_gpio(cnp, "wp-gpios", 0);
 674         }
 675
 676         return pdata;
 677 }
 678 #else /* CONFIG_OF */
 679 static inline struct mci_platform_data*
 680 atmci_of_init(struct platform_device *dev)
 681 {
 682         return ERR_PTR(-EINVAL);
 683 }
 684 #endif
 685
 686 static inline unsigned int atmci_get_version(struct atmel_mci *host)
 687 {
 688         return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
 689 }
 690
 691 /*
 692  * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
 693  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 694  * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
 695  * 8 -> 3, 16 -> 4.
 696  *
 697  * This can be done by finding most significant bit set.
 698  */
 699 static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
 700                                                  unsigned int maxburst)
 701 {
 702         unsigned int version = atmci_get_version(host);
 703         unsigned int offset = 2;
 704
 705         if (version >= 0x600)
 706                 offset = 1;
 707
 708         if (maxburst > 1)
 709                 return fls(maxburst) - offset;
 710         else
 711                 return 0;
 712 }
 713
 714 static void atmci_timeout_timer(struct timer_list *t)
 715 {
 716         struct atmel_mci *host;
 717
 718         host = from_timer(host, t, timer);
 719
 720         dev_dbg(&host->pdev->dev, "software timeout\n");
 721
 722         if (host->mrq->cmd->data) {
 723                 host->mrq->cmd->data->error = -ETIMEDOUT;
 724                 host->data = NULL;
 725                 /*
 726                  * With some SDIO modules, sometimes DMA transfer hangs. If
 727                  * stop_transfer() is not called then the DMA request is not
 728                  * removed, following ones are queued and never computed.
 729                  */
 730                 if (host->state == STATE_DATA_XFER)
 731                         host->stop_transfer(host);
 732         } else {
 733                 host->mrq->cmd->error = -ETIMEDOUT;
 734                 host->cmd = NULL;
 735         }
 736         host->need_reset = 1;
 737         host->state = STATE_END_REQUEST;
 738         smp_wmb();
 739         tasklet_schedule(&host->tasklet);
 740 }
 741
 742 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
 743                                         unsigned int ns)
 744 {
 745         /*
 746          * It is easier here to use us instead of ns for the timeout,
 747          * it prevents from overflows during calculation.
 748          */
 749         unsigned int us = DIV_ROUND_UP(ns, 1000);
 750
 751         /* Maximum clock frequency is host->bus_hz/2 */
 752         return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
 753 }
 754
 755 static void atmci_set_timeout(struct atmel_mci *host,
 756                 struct atmel_mci_slot *slot, struct mmc_data *data)
 757 {
 758         static unsigned dtomul_to_shift[] = {
 759                 0, 4, 7, 8, 10, 12, 16, 20
 760         };
 761         unsigned        timeout;
 762         unsigned        dtocyc;
 763         unsigned        dtomul;
 764
 765         timeout = atmci_ns_to_clocks(host, data->timeout_ns)
 766                 + data->timeout_clks;
 767
 768         for (dtomul = 0; dtomul < 8; dtomul++) {
 769                 unsigned shift = dtomul_to_shift[dtomul];
 770                 dtocyc = (timeout + (1 << shift) - 1) >> shift;
 771                 if (dtocyc < 15)
 772                         break;
 773         }
 774
 775         if (dtomul >= 8) {
 776                 dtomul = 7;
 777                 dtocyc = 15;
 778         }
 779
 780         dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
 781                         dtocyc << dtomul_to_shift[dtomul]);
 782         atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
 783 }
 784
 785 /*
 786  * Return mask with command flags to be enabled for this command.
 787  */
 788 static u32 atmci_prepare_command(struct mmc_host *mmc,
 789                                  struct mmc_command *cmd)
 790 {
 791         struct mmc_data *data;
 792         u32             cmdr;
 793
 794         cmd->error = -EINPROGRESS;
 795
 796         cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
 797
 798         if (cmd->flags & MMC_RSP_PRESENT) {
 799                 if (cmd->flags & MMC_RSP_136)
 800                         cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
 801                 else
 802                         cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
 803         }
 804
 805         /*
 806          * This should really be MAXLAT_5 for CMD2 and ACMD41, but
 807          * it's too difficult to determine whether this is an ACMD or
 808          * not. Better make it 64.
 809          */
 810         cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
 811
 812         if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
 813                 cmdr |= ATMCI_CMDR_OPDCMD;
 814
 815         data = cmd->data;
 816         if (data) {
 817                 cmdr |= ATMCI_CMDR_START_XFER;
 818
 819                 if (cmd->opcode == SD_IO_RW_EXTENDED) {
 820                         cmdr |= ATMCI_CMDR_SDIO_BLOCK;
 821                 } else {
 822                         if (data->blocks > 1)
 823                                 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
 824                         else
 825                                 cmdr |= ATMCI_CMDR_BLOCK;
 826                 }
 827
 828                 if (data->flags & MMC_DATA_READ)
 829                         cmdr |= ATMCI_CMDR_TRDIR_READ;
 830         }
 831
 832         return cmdr;
 833 }
 834
 835 static void atmci_send_command(struct atmel_mci *host,
 836                 struct mmc_command *cmd, u32 cmd_flags)
 837 {
 838         WARN_ON(host->cmd);
 839         host->cmd = cmd;
 840
 841         dev_vdbg(&host->pdev->dev,
 842                         "start command: ARGR=0x%08x CMDR=0x%08x\n",
 843                         cmd->arg, cmd_flags);
 844
 845         atmci_writel(host, ATMCI_ARGR, cmd->arg);
 846         atmci_writel(host, ATMCI_CMDR, cmd_flags);
 847 }
 848
 849 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
 850 {
 851         dev_dbg(&host->pdev->dev, "send stop command\n");
 852         atmci_send_command(host, data->stop, host->stop_cmdr);
 853         atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
 854 }
 855
 856 /*
 857  * Configure given PDC buffer taking care of alignement issues.
 858  * Update host->data_size and host->sg.
 859  */
 860 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
 861         enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
 862 {
 863         u32 pointer_reg, counter_reg;
 864         unsigned int buf_size;
 865
 866         if (dir == XFER_RECEIVE) {
 867                 pointer_reg = ATMEL_PDC_RPR;
 868                 counter_reg = ATMEL_PDC_RCR;
 869         } else {
 870                 pointer_reg = ATMEL_PDC_TPR;
 871                 counter_reg = ATMEL_PDC_TCR;
 872         }
 873
 874         if (buf_nb == PDC_SECOND_BUF) {
 875                 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
 876                 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
 877         }
 878
 879         if (!host->caps.has_rwproof) {
 880                 buf_size = host->buf_size;
 881                 atmci_writel(host, pointer_reg, host->buf_phys_addr);
 882         } else {
 883                 buf_size = sg_dma_len(host->sg);
 884                 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
 885         }
 886
 887         if (host->data_size <= buf_size) {
 888                 if (host->data_size & 0x3) {
 889                         /* If size is different from modulo 4, transfer bytes */
 890                         atmci_writel(host, counter_reg, host->data_size);
 891                         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
 892                 } else {
 893                         /* Else transfer 32-bits words */
 894                         atmci_writel(host, counter_reg, host->data_size / 4);
 895                 }
 896                 host->data_size = 0;
 897         } else {
 898                 /* We assume the size of a page is 32-bits aligned */
 899                 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
 900                 host->data_size -= sg_dma_len(host->sg);
 901                 if (host->data_size)
 902                         host->sg = sg_next(host->sg);
 903         }
 904 }
 905
 906 /*
 907  * Configure PDC buffer according to the data size ie configuring one or two
 908  * buffers. Don't use this function if you want to configure only the second
 909  * buffer. In this case, use atmci_pdc_set_single_buf.
 910  */
 911 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
 912 {
 913         atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
 914         if (host->data_size)
 915                 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
 916 }
 917
 918 /*
 919  * Unmap sg lists, called when transfer is finished.
 920  */
 921 static void atmci_pdc_cleanup(struct atmel_mci *host)
 922 {
 923         struct mmc_data         *data = host->data;
 924
 925         if (data)
 926                 dma_unmap_sg(&host->pdev->dev,
 927                                 data->sg, data->sg_len,
 928                                 mmc_get_dma_dir(data));
 929 }
 930
 931 /*
 932  * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
 933  * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
 934  * interrupt needed for both transfer directions.
 935  */
 936 static void atmci_pdc_complete(struct atmel_mci *host)
 937 {
 938         int transfer_size = host->data->blocks * host->data->blksz;
 939         int i;
 940
 941         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
 942
 943         if ((!host->caps.has_rwproof)
 944             && (host->data->flags & MMC_DATA_READ)) {
 945                 if (host->caps.has_bad_data_ordering)
 946                         for (i = 0; i < transfer_size; i++)
 947                                 host->buffer[i] = swab32(host->buffer[i]);
 948                 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
 949                                     host->buffer, transfer_size);
 950         }
 951
 952         atmci_pdc_cleanup(host);
 953
 954         dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
 955         atmci_set_pending(host, EVENT_XFER_COMPLETE);
 956         tasklet_schedule(&host->tasklet);
 957 }
 958
 959 static void atmci_dma_cleanup(struct atmel_mci *host)
 960 {
 961         struct mmc_data                 *data = host->data;
 962
 963         if (data)
 964                 dma_unmap_sg(host->dma.chan->device->dev,
 965                                 data->sg, data->sg_len,
 966                                 mmc_get_dma_dir(data));
 967 }
 968
 969 /*
 970  * This function is called by the DMA driver from tasklet context.
 971  */
 972 static void atmci_dma_complete(void *arg)
 973 {
 974         struct atmel_mci        *host = arg;
 975         struct mmc_data         *data = host->data;
 976
 977         dev_vdbg(&host->pdev->dev, "DMA complete\n");
 978
 979         if (host->caps.has_dma_conf_reg)
 980                 /* Disable DMA hardware handshaking on MCI */
 981                 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
 982
 983         atmci_dma_cleanup(host);
 984
 985         /*
 986          * If the card was removed, data will be NULL. No point trying
 987          * to send the stop command or waiting for NBUSY in this case.
 988          */
 989         if (data) {
 990                 dev_dbg(&host->pdev->dev,
 991                         "(%s) set pending xfer complete\n", __func__);
 992                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
 993                 tasklet_schedule(&host->tasklet);
 994
 995                 /*
 996                  * Regardless of what the documentation says, we have
 997                  * to wait for NOTBUSY even after block read
 998                  * operations.
 999                  *
1000                  * When the DMA transfer is complete, the controller
1001                  * may still be reading the CRC from the card, i.e.
1002                  * the data transfer is still in progress and we
1003                  * haven't seen all the potential error bits yet.
1004                  *
1005                  * The interrupt handler will schedule a different
1006                  * tasklet to finish things up when the data transfer
1007                  * is completely done.
1008                  *
1009                  * We may not complete the mmc request here anyway
1010                  * because the mmc layer may call back and cause us to
1011                  * violate the "don't submit new operations from the
1012                  * completion callback" rule of the dma engine
1013                  * framework.
1014                  */
1015                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1016         }
1017 }
1018
1019 /*
1020  * Returns a mask of interrupt flags to be enabled after the whole
1021  * request has been prepared.
1022  */
1023 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
1024 {
1025         u32 iflags;
1026
1027         data->error = -EINPROGRESS;
1028
1029         host->sg = data->sg;
1030         host->sg_len = data->sg_len;
1031         host->data = data;
1032         host->data_chan = NULL;
1033
1034         iflags = ATMCI_DATA_ERROR_FLAGS;
1035
1036         /*
1037          * Errata: MMC data write operation with less than 12
1038          * bytes is impossible.
1039          *
1040          * Errata: MCI Transmit Data Register (TDR) FIFO
1041          * corruption when length is not multiple of 4.
1042          */
1043         if (data->blocks * data->blksz < 12
1044                         || (data->blocks * data->blksz) & 3)
1045                 host->need_reset = true;
1046
1047         host->pio_offset = 0;
1048         if (data->flags & MMC_DATA_READ)
1049                 iflags |= ATMCI_RXRDY;
1050         else
1051                 iflags |= ATMCI_TXRDY;
1052
1053         return iflags;
1054 }
1055
1056 /*
1057  * Set interrupt flags and set block length into the MCI mode register even
1058  * if this value is also accessible in the MCI block register. It seems to be
1059  * necessary before the High Speed MCI version. It also map sg and configure
1060  * PDC registers.
1061  */
1062 static u32
1063 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1064 {
1065         u32 iflags, tmp;
1066         int i;
1067
1068         data->error = -EINPROGRESS;
1069
1070         host->data = data;
1071         host->sg = data->sg;
1072         iflags = ATMCI_DATA_ERROR_FLAGS;
1073
1074         /* Enable pdc mode */
1075         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
1076
1077         if (data->flags & MMC_DATA_READ)
1078                 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
1079         else
1080                 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
1081
1082         /* Set BLKLEN */
1083         tmp = atmci_readl(host, ATMCI_MR);
1084         tmp &= 0x0000ffff;
1085         tmp |= ATMCI_BLKLEN(data->blksz);
1086         atmci_writel(host, ATMCI_MR, tmp);
1087
1088         /* Configure PDC */
1089         host->data_size = data->blocks * data->blksz;
1090         dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
1091                    mmc_get_dma_dir(data));
1092
1093         if ((!host->caps.has_rwproof)
1094             && (host->data->flags & MMC_DATA_WRITE)) {
1095                 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
1096                                   host->buffer, host->data_size);
1097                 if (host->caps.has_bad_data_ordering)
1098                         for (i = 0; i < host->data_size; i++)
1099                                 host->buffer[i] = swab32(host->buffer[i]);
1100         }
1101
1102         if (host->data_size)
1103                 atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ?
1104                                        XFER_RECEIVE : XFER_TRANSMIT);
1105         return iflags;
1106 }
1107
1108 static u32
1109 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
1110 {
1111         struct dma_chan                 *chan;
1112         struct dma_async_tx_descriptor  *desc;
1113         struct scatterlist              *sg;
1114         unsigned int                    i;
1115         enum dma_transfer_direction     slave_dirn;
1116         unsigned int                    sglen;
1117         u32                             maxburst;
1118         u32 iflags;
1119
1120         data->error = -EINPROGRESS;
1121
1122         WARN_ON(host->data);
1123         host->sg = NULL;
1124         host->data = data;
1125
1126         iflags = ATMCI_DATA_ERROR_FLAGS;
1127
1128         /*
1129          * We don't do DMA on "complex" transfers, i.e. with
1130          * non-word-aligned buffers or lengths. Also, we don't bother
1131          * with all the DMA setup overhead for short transfers.
1132          */
1133         if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1134                 return atmci_prepare_data(host, data);
1135         if (data->blksz & 3)
1136                 return atmci_prepare_data(host, data);
1137
1138         for_each_sg(data->sg, sg, data->sg_len, i) {
1139                 if (sg->offset & 3 || sg->length & 3)
1140                         return atmci_prepare_data(host, data);
1141         }
1142
1143         /* If we don't have a channel, we can't do DMA */
1144         chan = host->dma.chan;
1145         if (chan)
1146                 host->data_chan = chan;
1147
1148         if (!chan)
1149                 return -ENODEV;
1150
1151         if (data->flags & MMC_DATA_READ) {
1152                 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1153                 maxburst = atmci_convert_chksize(host,
1154                                                  host->dma_conf.src_maxburst);
1155         } else {
1156                 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1157                 maxburst = atmci_convert_chksize(host,
1158                                                  host->dma_conf.dst_maxburst);
1159         }
1160
1161         if (host->caps.has_dma_conf_reg)
1162                 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1163                         ATMCI_DMAEN);
1164
1165         sglen = dma_map_sg(chan->device->dev, data->sg,
1166                         data->sg_len, mmc_get_dma_dir(data));
1167
1168         dmaengine_slave_config(chan, &host->dma_conf);
1169         desc = dmaengine_prep_slave_sg(chan,
1170                         data->sg, sglen, slave_dirn,
1171                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1172         if (!desc)
1173                 goto unmap_exit;
1174
1175         host->dma.data_desc = desc;
1176         desc->callback = atmci_dma_complete;
1177         desc->callback_param = host;
1178
1179         return iflags;
1180 unmap_exit:
1181         dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
1182                      mmc_get_dma_dir(data));
1183         return -ENOMEM;
1184 }
1185
1186 static void
1187 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1188 {
1189         return;
1190 }
1191
1192 /*
1193  * Start PDC according to transfer direction.
1194  */
1195 static void
1196 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1197 {
1198         if (data->flags & MMC_DATA_READ)
1199                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1200         else
1201                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1202 }
1203
1204 static void
1205 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1206 {
1207         struct dma_chan                 *chan = host->data_chan;
1208         struct dma_async_tx_descriptor  *desc = host->dma.data_desc;
1209
1210         if (chan) {
1211                 dmaengine_submit(desc);
1212                 dma_async_issue_pending(chan);
1213         }
1214 }
1215
1216 static void atmci_stop_transfer(struct atmel_mci *host)
1217 {
1218         dev_dbg(&host->pdev->dev,
1219                 "(%s) set pending xfer complete\n", __func__);
1220         atmci_set_pending(host, EVENT_XFER_COMPLETE);
1221         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1222 }
1223
1224 /*
1225  * Stop data transfer because error(s) occurred.
1226  */
1227 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1228 {
1229         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1230 }
1231
1232 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1233 {
1234         struct dma_chan *chan = host->data_chan;
1235
1236         if (chan) {
1237                 dmaengine_terminate_all(chan);
1238                 atmci_dma_cleanup(host);
1239         } else {
1240                 /* Data transfer was stopped by the interrupt handler */
1241                 dev_dbg(&host->pdev->dev,
1242                         "(%s) set pending xfer complete\n", __func__);
1243                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1244                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1245         }
1246 }
1247
1248 /*
1249  * Start a request: prepare data if needed, prepare the command and activate
1250  * interrupts.
1251  */
1252 static void atmci_start_request(struct atmel_mci *host,
1253                 struct atmel_mci_slot *slot)
1254 {
1255         struct mmc_request      *mrq;
1256         struct mmc_command      *cmd;
1257         struct mmc_data         *data;
1258         u32                     iflags;
1259         u32                     cmdflags;
1260
1261         mrq = slot->mrq;
1262         host->cur_slot = slot;
1263         host->mrq = mrq;
1264
1265         host->pending_events = 0;
1266         host->completed_events = 0;
1267         host->cmd_status = 0;
1268         host->data_status = 0;
1269
1270         dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1271
1272         if (host->need_reset || host->caps.need_reset_after_xfer) {
1273                 iflags = atmci_readl(host, ATMCI_IMR);
1274                 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1275                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1276                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1277                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1278                 if (host->caps.has_cfg_reg)
1279                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1280                 atmci_writel(host, ATMCI_IER, iflags);
1281                 host->need_reset = false;
1282         }
1283         atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1284
1285         iflags = atmci_readl(host, ATMCI_IMR);
1286         if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1287                 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1288                                 iflags);
1289
1290         if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1291                 /* Send init sequence (74 clock cycles) */
1292                 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1293                 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1294                         cpu_relax();
1295         }
1296         iflags = 0;
1297         data = mrq->data;
1298         if (data) {
1299                 atmci_set_timeout(host, slot, data);
1300
1301                 /* Must set block count/size before sending command */
1302                 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1303                                 | ATMCI_BLKLEN(data->blksz));
1304                 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1305                         ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1306
1307                 iflags |= host->prepare_data(host, data);
1308         }
1309
1310         iflags |= ATMCI_CMDRDY;
1311         cmd = mrq->cmd;
1312         cmdflags = atmci_prepare_command(slot->mmc, cmd);
1313
1314         /*
1315          * DMA transfer should be started before sending the command to avoid
1316          * unexpected errors especially for read operations in SDIO mode.
1317          * Unfortunately, in PDC mode, command has to be sent before starting
1318          * the transfer.
1319          */
1320         if (host->submit_data != &atmci_submit_data_dma)
1321                 atmci_send_command(host, cmd, cmdflags);
1322
1323         if (data)
1324                 host->submit_data(host, data);
1325
1326         if (host->submit_data == &atmci_submit_data_dma)
1327                 atmci_send_command(host, cmd, cmdflags);
1328
1329         if (mrq->stop) {
1330                 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1331                 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1332                 if (!(data->flags & MMC_DATA_WRITE))
1333                         host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1334                 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1335         }
1336
1337         /*
1338          * We could have enabled interrupts earlier, but I suspect
1339          * that would open up a nice can of interesting race
1340          * conditions (e.g. command and data complete, but stop not
1341          * prepared yet.)
1342          */
1343         atmci_writel(host, ATMCI_IER, iflags);
1344
1345         mod_timer(&host->timer, jiffies +  msecs_to_jiffies(2000));
1346 }
1347
1348 static void atmci_queue_request(struct atmel_mci *host,
1349                 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1350 {
1351         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1352                         host->state);
1353
1354         spin_lock_bh(&host->lock);
1355         slot->mrq = mrq;
1356         if (host->state == STATE_IDLE) {
1357                 host->state = STATE_SENDING_CMD;
1358                 atmci_start_request(host, slot);
1359         } else {
1360                 dev_dbg(&host->pdev->dev, "queue request\n");
1361                 list_add_tail(&slot->queue_node, &host->queue);
1362         }
1363         spin_unlock_bh(&host->lock);
1364 }
1365
1366 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1367 {
1368         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1369         struct atmel_mci        *host = slot->host;
1370         struct mmc_data         *data;
1371
1372         WARN_ON(slot->mrq);
1373         dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1374
1375         /*
1376          * We may "know" the card is gone even though there's still an
1377          * electrical connection. If so, we really need to communicate
1378          * this to the MMC core since there won't be any more
1379          * interrupts as the card is completely removed. Otherwise,
1380          * the MMC core might believe the card is still there even
1381          * though the card was just removed very slowly.
1382          */
1383         if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1384                 mrq->cmd->error = -ENOMEDIUM;
1385                 mmc_request_done(mmc, mrq);
1386                 return;
1387         }
1388
1389         /* We don't support multiple blocks of weird lengths. */
1390         data = mrq->data;
1391         if (data && data->blocks > 1 && data->blksz & 3) {
1392                 mrq->cmd->error = -EINVAL;
1393                 mmc_request_done(mmc, mrq);
1394         }
1395
1396         atmci_queue_request(host, slot, mrq);
1397 }
1398
1399 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1400 {
1401         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1402         struct atmel_mci        *host = slot->host;
1403         unsigned int            i;
1404
1405         slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1406         switch (ios->bus_width) {
1407         case MMC_BUS_WIDTH_1:
1408                 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1409                 break;
1410         case MMC_BUS_WIDTH_4:
1411                 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1412                 break;
1413         case MMC_BUS_WIDTH_8:
1414                 slot->sdc_reg |= ATMCI_SDCBUS_8BIT;
1415                 break;
1416         }
1417
1418         if (ios->clock) {
1419                 unsigned int clock_min = ~0U;
1420                 int clkdiv;
1421
1422                 spin_lock_bh(&host->lock);
1423                 if (!host->mode_reg) {
1424                         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1425                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1426                         if (host->caps.has_cfg_reg)
1427                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1428                 }
1429
1430                 /*
1431                  * Use mirror of ios->clock to prevent race with mmc
1432                  * core ios update when finding the minimum.
1433                  */
1434                 slot->clock = ios->clock;
1435                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1436                         if (host->slot[i] && host->slot[i]->clock
1437                                         && host->slot[i]->clock < clock_min)
1438                                 clock_min = host->slot[i]->clock;
1439                 }
1440
1441                 /* Calculate clock divider */
1442                 if (host->caps.has_odd_clk_div) {
1443                         clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1444                         if (clkdiv < 0) {
1445                                 dev_warn(&mmc->class_dev,
1446                                          "clock %u too fast; using %lu\n",
1447                                          clock_min, host->bus_hz / 2);
1448                                 clkdiv = 0;
1449                         } else if (clkdiv > 511) {
1450                                 dev_warn(&mmc->class_dev,
1451                                          "clock %u too slow; using %lu\n",
1452                                          clock_min, host->bus_hz / (511 + 2));
1453                                 clkdiv = 511;
1454                         }
1455                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1456                                          | ATMCI_MR_CLKODD(clkdiv & 1);
1457                 } else {
1458                         clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1459                         if (clkdiv > 255) {
1460                                 dev_warn(&mmc->class_dev,
1461                                          "clock %u too slow; using %lu\n",
1462                                          clock_min, host->bus_hz / (2 * 256));
1463                                 clkdiv = 255;
1464                         }
1465                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1466                 }
1467
1468                 /*
1469                  * WRPROOF and RDPROOF prevent overruns/underruns by
1470                  * stopping the clock when the FIFO is full/empty.
1471                  * This state is not expected to last for long.
1472                  */
1473                 if (host->caps.has_rwproof)
1474                         host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1475
1476                 if (host->caps.has_cfg_reg) {
1477                         /* setup High Speed mode in relation with card capacity */
1478                         if (ios->timing == MMC_TIMING_SD_HS)
1479                                 host->cfg_reg |= ATMCI_CFG_HSMODE;
1480                         else
1481                                 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1482                 }
1483
1484                 if (list_empty(&host->queue)) {
1485                         atmci_writel(host, ATMCI_MR, host->mode_reg);
1486                         if (host->caps.has_cfg_reg)
1487                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1488                 } else {
1489                         host->need_clock_update = true;
1490                 }
1491
1492                 spin_unlock_bh(&host->lock);
1493         } else {
1494                 bool any_slot_active = false;
1495
1496                 spin_lock_bh(&host->lock);
1497                 slot->clock = 0;
1498                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1499                         if (host->slot[i] && host->slot[i]->clock) {
1500                                 any_slot_active = true;
1501                                 break;
1502                         }
1503                 }
1504                 if (!any_slot_active) {
1505                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1506                         if (host->mode_reg) {
1507                                 atmci_readl(host, ATMCI_MR);
1508                         }
1509                         host->mode_reg = 0;
1510                 }
1511                 spin_unlock_bh(&host->lock);
1512         }
1513
1514         switch (ios->power_mode) {
1515         case MMC_POWER_OFF:
1516                 if (!IS_ERR(mmc->supply.vmmc))
1517                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1518                 break;
1519         case MMC_POWER_UP:
1520                 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1521                 if (!IS_ERR(mmc->supply.vmmc))
1522                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1523                 break;
1524         default:
1525                 break;
1526         }
1527 }
1528
1529 static int atmci_get_ro(struct mmc_host *mmc)
1530 {
1531         int                     read_only = -ENOSYS;
1532         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1533
1534         if (gpio_is_valid(slot->wp_pin)) {
1535                 read_only = gpio_get_value(slot->wp_pin);
1536                 dev_dbg(&mmc->class_dev, "card is %s\n",
1537                                 read_only ? "read-only" : "read-write");
1538         }
1539
1540         return read_only;
1541 }
1542
1543 static int atmci_get_cd(struct mmc_host *mmc)
1544 {
1545         int                     present = -ENOSYS;
1546         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1547
1548         if (gpio_is_valid(slot->detect_pin)) {
1549                 present = !(gpio_get_value(slot->detect_pin) ^
1550                             slot->detect_is_active_high);
1551                 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1552                                 present ? "" : "not ");
1553         }
1554
1555         return present;
1556 }
1557
1558 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1559 {
1560         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1561         struct atmel_mci        *host = slot->host;
1562
1563         if (enable)
1564                 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1565         else
1566                 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1567 }
1568
1569 static const struct mmc_host_ops atmci_ops = {
1570         .request        = atmci_request,
1571         .set_ios        = atmci_set_ios,
1572         .get_ro         = atmci_get_ro,
1573         .get_cd         = atmci_get_cd,
1574         .enable_sdio_irq = atmci_enable_sdio_irq,
1575 };
1576
1577 /* Called with host->lock held */
1578 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1579         __releases(&host->lock)
1580         __acquires(&host->lock)
1581 {
1582         struct atmel_mci_slot   *slot = NULL;
1583         struct mmc_host         *prev_mmc = host->cur_slot->mmc;
1584
1585         WARN_ON(host->cmd || host->data);
1586
1587         /*
1588          * Update the MMC clock rate if necessary. This may be
1589          * necessary if set_ios() is called when a different slot is
1590          * busy transferring data.
1591          */
1592         if (host->need_clock_update) {
1593                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1594                 if (host->caps.has_cfg_reg)
1595                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1596         }
1597
1598         host->cur_slot->mrq = NULL;
1599         host->mrq = NULL;
1600         if (!list_empty(&host->queue)) {
1601                 slot = list_entry(host->queue.next,
1602                                 struct atmel_mci_slot, queue_node);
1603                 list_del(&slot->queue_node);
1604                 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1605                                 mmc_hostname(slot->mmc));
1606                 host->state = STATE_SENDING_CMD;
1607                 atmci_start_request(host, slot);
1608         } else {
1609                 dev_vdbg(&host->pdev->dev, "list empty\n");
1610                 host->state = STATE_IDLE;
1611         }
1612
1613         del_timer(&host->timer);
1614
1615         spin_unlock(&host->lock);
1616         mmc_request_done(prev_mmc, mrq);
1617         spin_lock(&host->lock);
1618 }
1619
1620 static void atmci_command_complete(struct atmel_mci *host,
1621                         struct mmc_command *cmd)
1622 {
1623         u32             status = host->cmd_status;
1624
1625         /* Read the response from the card (up to 16 bytes) */
1626         cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1627         cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1628         cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1629         cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1630
1631         if (status & ATMCI_RTOE)
1632                 cmd->error = -ETIMEDOUT;
1633         else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1634                 cmd->error = -EILSEQ;
1635         else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1636                 cmd->error = -EIO;
1637         else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1638                 if (host->caps.need_blksz_mul_4) {
1639                         cmd->error = -EINVAL;
1640                         host->need_reset = 1;
1641                 }
1642         } else
1643                 cmd->error = 0;
1644 }
1645
1646 static void atmci_detect_change(struct timer_list *t)
1647 {
1648         struct atmel_mci_slot   *slot = from_timer(slot, t, detect_timer);
1649         bool                    present;
1650         bool                    present_old;
1651
1652         /*
1653          * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1654          * freeing the interrupt. We must not re-enable the interrupt
1655          * if it has been freed, and if we're shutting down, it
1656          * doesn't really matter whether the card is present or not.
1657          */
1658         smp_rmb();
1659         if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1660                 return;
1661
1662         enable_irq(gpio_to_irq(slot->detect_pin));
1663         present = !(gpio_get_value(slot->detect_pin) ^
1664                     slot->detect_is_active_high);
1665         present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1666
1667         dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1668                         present, present_old);
1669
1670         if (present != present_old) {
1671                 struct atmel_mci        *host = slot->host;
1672                 struct mmc_request      *mrq;
1673
1674                 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1675                         present ? "inserted" : "removed");
1676
1677                 spin_lock(&host->lock);
1678
1679                 if (!present)
1680                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1681                 else
1682                         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1683
1684                 /* Clean up queue if present */
1685                 mrq = slot->mrq;
1686                 if (mrq) {
1687                         if (mrq == host->mrq) {
1688                                 /*
1689                                  * Reset controller to terminate any ongoing
1690                                  * commands or data transfers.
1691                                  */
1692                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1693                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1694                                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1695                                 if (host->caps.has_cfg_reg)
1696                                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1697
1698                                 host->data = NULL;
1699                                 host->cmd = NULL;
1700
1701                                 switch (host->state) {
1702                                 case STATE_IDLE:
1703                                         break;
1704                                 case STATE_SENDING_CMD:
1705                                         mrq->cmd->error = -ENOMEDIUM;
1706                                         if (mrq->data)
1707                                                 host->stop_transfer(host);
1708                                         break;
1709                                 case STATE_DATA_XFER:
1710                                         mrq->data->error = -ENOMEDIUM;
1711                                         host->stop_transfer(host);
1712                                         break;
1713                                 case STATE_WAITING_NOTBUSY:
1714                                         mrq->data->error = -ENOMEDIUM;
1715                                         break;
1716                                 case STATE_SENDING_STOP:
1717                                         mrq->stop->error = -ENOMEDIUM;
1718                                         break;
1719                                 case STATE_END_REQUEST:
1720                                         break;
1721                                 }
1722
1723                                 atmci_request_end(host, mrq);
1724                         } else {
1725                                 list_del(&slot->queue_node);
1726                                 mrq->cmd->error = -ENOMEDIUM;
1727                                 if (mrq->data)
1728                                         mrq->data->error = -ENOMEDIUM;
1729                                 if (mrq->stop)
1730                                         mrq->stop->error = -ENOMEDIUM;
1731
1732                                 spin_unlock(&host->lock);
1733                                 mmc_request_done(slot->mmc, mrq);
1734                                 spin_lock(&host->lock);
1735                         }
1736                 }
1737                 spin_unlock(&host->lock);
1738
1739                 mmc_detect_change(slot->mmc, 0);
1740         }
1741 }
1742
1743 static void atmci_tasklet_func(unsigned long priv)
1744 {
1745         struct atmel_mci        *host = (struct atmel_mci *)priv;
1746         struct mmc_request      *mrq = host->mrq;
1747         struct mmc_data         *data = host->data;
1748         enum atmel_mci_state    state = host->state;
1749         enum atmel_mci_state    prev_state;
1750         u32                     status;
1751
1752         spin_lock(&host->lock);
1753
1754         state = host->state;
1755
1756         dev_vdbg(&host->pdev->dev,
1757                 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1758                 state, host->pending_events, host->completed_events,
1759                 atmci_readl(host, ATMCI_IMR));
1760
1761         do {
1762                 prev_state = state;
1763                 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1764
1765                 switch (state) {
1766                 case STATE_IDLE:
1767                         break;
1768
1769                 case STATE_SENDING_CMD:
1770                         /*
1771                          * Command has been sent, we are waiting for command
1772                          * ready. Then we have three next states possible:
1773                          * END_REQUEST by default, WAITING_NOTBUSY if it's a
1774                          * command needing it or DATA_XFER if there is data.
1775                          */
1776                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1777                         if (!atmci_test_and_clear_pending(host,
1778                                                 EVENT_CMD_RDY))
1779                                 break;
1780
1781                         dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1782                         host->cmd = NULL;
1783                         atmci_set_completed(host, EVENT_CMD_RDY);
1784                         atmci_command_complete(host, mrq->cmd);
1785                         if (mrq->data) {
1786                                 dev_dbg(&host->pdev->dev,
1787                                         "command with data transfer");
1788                                 /*
1789                                  * If there is a command error don't start
1790                                  * data transfer.
1791                                  */
1792                                 if (mrq->cmd->error) {
1793                                         host->stop_transfer(host);
1794                                         host->data = NULL;
1795                                         atmci_writel(host, ATMCI_IDR,
1796                                                      ATMCI_TXRDY | ATMCI_RXRDY
1797                                                      | ATMCI_DATA_ERROR_FLAGS);
1798                                         state = STATE_END_REQUEST;
1799                                 } else
1800                                         state = STATE_DATA_XFER;
1801                         } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1802                                 dev_dbg(&host->pdev->dev,
1803                                         "command response need waiting notbusy");
1804                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1805                                 state = STATE_WAITING_NOTBUSY;
1806                         } else
1807                                 state = STATE_END_REQUEST;
1808
1809                         break;
1810
1811                 case STATE_DATA_XFER:
1812                         if (atmci_test_and_clear_pending(host,
1813                                                 EVENT_DATA_ERROR)) {
1814                                 dev_dbg(&host->pdev->dev, "set completed data error\n");
1815                                 atmci_set_completed(host, EVENT_DATA_ERROR);
1816                                 state = STATE_END_REQUEST;
1817                                 break;
1818                         }
1819
1820                         /*
1821                          * A data transfer is in progress. The event expected
1822                          * to move to the next state depends of data transfer
1823                          * type (PDC or DMA). Once transfer done we can move
1824                          * to the next step which is WAITING_NOTBUSY in write
1825                          * case and directly SENDING_STOP in read case.
1826                          */
1827                         dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1828                         if (!atmci_test_and_clear_pending(host,
1829                                                 EVENT_XFER_COMPLETE))
1830                                 break;
1831
1832                         dev_dbg(&host->pdev->dev,
1833                                 "(%s) set completed xfer complete\n",
1834                                 __func__);
1835                         atmci_set_completed(host, EVENT_XFER_COMPLETE);
1836
1837                         if (host->caps.need_notbusy_for_read_ops ||
1838                            (host->data->flags & MMC_DATA_WRITE)) {
1839                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1840                                 state = STATE_WAITING_NOTBUSY;
1841                         } else if (host->mrq->stop) {
1842                                 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1843                                 atmci_send_stop_cmd(host, data);
1844                                 state = STATE_SENDING_STOP;
1845                         } else {
1846                                 host->data = NULL;
1847                                 data->bytes_xfered = data->blocks * data->blksz;
1848                                 data->error = 0;
1849                                 state = STATE_END_REQUEST;
1850                         }
1851                         break;
1852
1853                 case STATE_WAITING_NOTBUSY:
1854                         /*
1855                          * We can be in the state for two reasons: a command
1856                          * requiring waiting not busy signal (stop command
1857                          * included) or a write operation. In the latest case,
1858                          * we need to send a stop command.
1859                          */
1860                         dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1861                         if (!atmci_test_and_clear_pending(host,
1862                                                 EVENT_NOTBUSY))
1863                                 break;
1864
1865                         dev_dbg(&host->pdev->dev, "set completed not busy\n");
1866                         atmci_set_completed(host, EVENT_NOTBUSY);
1867
1868                         if (host->data) {
1869                                 /*
1870                                  * For some commands such as CMD53, even if
1871                                  * there is data transfer, there is no stop
1872                                  * command to send.
1873                                  */
1874                                 if (host->mrq->stop) {
1875                                         atmci_writel(host, ATMCI_IER,
1876                                                      ATMCI_CMDRDY);
1877                                         atmci_send_stop_cmd(host, data);
1878                                         state = STATE_SENDING_STOP;
1879                                 } else {
1880                                         host->data = NULL;
1881                                         data->bytes_xfered = data->blocks
1882                                                              * data->blksz;
1883                                         data->error = 0;
1884                                         state = STATE_END_REQUEST;
1885                                 }
1886                         } else
1887                                 state = STATE_END_REQUEST;
1888                         break;
1889
1890                 case STATE_SENDING_STOP:
1891                         /*
1892                          * In this state, it is important to set host->data to
1893                          * NULL (which is tested in the waiting notbusy state)
1894                          * in order to go to the end request state instead of
1895                          * sending stop again.
1896                          */
1897                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1898                         if (!atmci_test_and_clear_pending(host,
1899                                                 EVENT_CMD_RDY))
1900                                 break;
1901
1902                         dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1903                         host->cmd = NULL;
1904                         data->bytes_xfered = data->blocks * data->blksz;
1905                         data->error = 0;
1906                         atmci_command_complete(host, mrq->stop);
1907                         if (mrq->stop->error) {
1908                                 host->stop_transfer(host);
1909                                 atmci_writel(host, ATMCI_IDR,
1910                                              ATMCI_TXRDY | ATMCI_RXRDY
1911                                              | ATMCI_DATA_ERROR_FLAGS);
1912                                 state = STATE_END_REQUEST;
1913                         } else {
1914                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1915                                 state = STATE_WAITING_NOTBUSY;
1916                         }
1917                         host->data = NULL;
1918                         break;
1919
1920                 case STATE_END_REQUEST:
1921                         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1922                                            | ATMCI_DATA_ERROR_FLAGS);
1923                         status = host->data_status;
1924                         if (unlikely(status)) {
1925                                 host->stop_transfer(host);
1926                                 host->data = NULL;
1927                                 if (data) {
1928                                         if (status & ATMCI_DTOE) {
1929                                                 data->error = -ETIMEDOUT;
1930                                         } else if (status & ATMCI_DCRCE) {
1931                                                 data->error = -EILSEQ;
1932                                         } else {
1933                                                 data->error = -EIO;
1934                                         }
1935                                 }
1936                         }
1937
1938                         atmci_request_end(host, host->mrq);
1939                         goto unlock; /* atmci_request_end() sets host->state */
1940                         break;
1941                 }
1942         } while (state != prev_state);
1943
1944         host->state = state;
1945
1946 unlock:
1947         spin_unlock(&host->lock);
1948 }
1949
1950 static void atmci_read_data_pio(struct atmel_mci *host)
1951 {
1952         struct scatterlist      *sg = host->sg;
1953         unsigned int            offset = host->pio_offset;
1954         struct mmc_data         *data = host->data;
1955         u32                     value;
1956         u32                     status;
1957         unsigned int            nbytes = 0;
1958
1959         do {
1960                 value = atmci_readl(host, ATMCI_RDR);
1961                 if (likely(offset + 4 <= sg->length)) {
1962                         sg_pcopy_from_buffer(sg, 1, &value, sizeof(u32), offset);
1963
1964                         offset += 4;
1965                         nbytes += 4;
1966
1967                         if (offset == sg->length) {
1968                                 flush_dcache_page(sg_page(sg));
1969                                 host->sg = sg = sg_next(sg);
1970                                 host->sg_len--;
1971                                 if (!sg || !host->sg_len)
1972                                         goto done;
1973
1974                                 offset = 0;
1975                         }
1976                 } else {
1977                         unsigned int remaining = sg->length - offset;
1978
1979                         sg_pcopy_from_buffer(sg, 1, &value, remaining, offset);
1980                         nbytes += remaining;
1981
1982                         flush_dcache_page(sg_page(sg));
1983                         host->sg = sg = sg_next(sg);
1984                         host->sg_len--;
1985                         if (!sg || !host->sg_len)
1986                                 goto done;
1987
1988                         offset = 4 - remaining;
1989                         sg_pcopy_from_buffer(sg, 1, (u8 *)&value + remaining,
1990                                         offset, 0);
1991                         nbytes += offset;
1992                 }
1993
1994                 status = atmci_readl(host, ATMCI_SR);
1995                 if (status & ATMCI_DATA_ERROR_FLAGS) {
1996                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1997                                                 | ATMCI_DATA_ERROR_FLAGS));
1998                         host->data_status = status;
1999                         data->bytes_xfered += nbytes;
2000                         return;
2001                 }
2002         } while (status & ATMCI_RXRDY);
2003
2004         host->pio_offset = offset;
2005         data->bytes_xfered += nbytes;
2006
2007         return;
2008
2009 done:
2010         atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
2011         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2012         data->bytes_xfered += nbytes;
2013         smp_wmb();
2014         atmci_set_pending(host, EVENT_XFER_COMPLETE);
2015 }
2016
2017 static void atmci_write_data_pio(struct atmel_mci *host)
2018 {
2019         struct scatterlist      *sg = host->sg;
2020         unsigned int            offset = host->pio_offset;
2021         struct mmc_data         *data = host->data;
2022         u32                     value;
2023         u32                     status;
2024         unsigned int            nbytes = 0;
2025
2026         do {
2027                 if (likely(offset + 4 <= sg->length)) {
2028                         sg_pcopy_to_buffer(sg, 1, &value, sizeof(u32), offset);
2029                         atmci_writel(host, ATMCI_TDR, value);
2030
2031                         offset += 4;
2032                         nbytes += 4;
2033                         if (offset == sg->length) {
2034                                 host->sg = sg = sg_next(sg);
2035                                 host->sg_len--;
2036                                 if (!sg || !host->sg_len)
2037                                         goto done;
2038
2039                                 offset = 0;
2040                         }
2041                 } else {
2042                         unsigned int remaining = sg->length - offset;
2043
2044                         value = 0;
2045                         sg_pcopy_to_buffer(sg, 1, &value, remaining, offset);
2046                         nbytes += remaining;
2047
2048                         host->sg = sg = sg_next(sg);
2049                         host->sg_len--;
2050                         if (!sg || !host->sg_len) {
2051                                 atmci_writel(host, ATMCI_TDR, value);
2052                                 goto done;
2053                         }
2054
2055                         offset = 4 - remaining;
2056                         sg_pcopy_to_buffer(sg, 1, (u8 *)&value + remaining,
2057                                         offset, 0);
2058                         atmci_writel(host, ATMCI_TDR, value);
2059                         nbytes += offset;
2060                 }
2061
2062                 status = atmci_readl(host, ATMCI_SR);
2063                 if (status & ATMCI_DATA_ERROR_FLAGS) {
2064                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
2065                                                 | ATMCI_DATA_ERROR_FLAGS));
2066                         host->data_status = status;
2067                         data->bytes_xfered += nbytes;
2068                         return;
2069                 }
2070         } while (status & ATMCI_TXRDY);
2071
2072         host->pio_offset = offset;
2073         data->bytes_xfered += nbytes;
2074
2075         return;
2076
2077 done:
2078         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
2079         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2080         data->bytes_xfered += nbytes;
2081         smp_wmb();
2082         atmci_set_pending(host, EVENT_XFER_COMPLETE);
2083 }
2084
2085 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
2086 {
2087         int     i;
2088
2089         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2090                 struct atmel_mci_slot *slot = host->slot[i];
2091                 if (slot && (status & slot->sdio_irq)) {
2092                         mmc_signal_sdio_irq(slot->mmc);
2093                 }
2094         }
2095 }
2096
2097
2098 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2099 {
2100         struct atmel_mci        *host = dev_id;
2101         u32                     status, mask, pending;
2102         unsigned int            pass_count = 0;
2103
2104         do {
2105                 status = atmci_readl(host, ATMCI_SR);
2106                 mask = atmci_readl(host, ATMCI_IMR);
2107                 pending = status & mask;
2108                 if (!pending)
2109                         break;
2110
2111                 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2112                         dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2113                         atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2114                                         | ATMCI_RXRDY | ATMCI_TXRDY
2115                                         | ATMCI_ENDRX | ATMCI_ENDTX
2116                                         | ATMCI_RXBUFF | ATMCI_TXBUFE);
2117
2118                         host->data_status = status;
2119                         dev_dbg(&host->pdev->dev, "set pending data error\n");
2120                         smp_wmb();
2121                         atmci_set_pending(host, EVENT_DATA_ERROR);
2122                         tasklet_schedule(&host->tasklet);
2123                 }
2124
2125                 if (pending & ATMCI_TXBUFE) {
2126                         dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2127                         atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2128                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2129                         /*
2130                          * We can receive this interruption before having configured
2131                          * the second pdc buffer, so we need to reconfigure first and
2132                          * second buffers again
2133                          */
2134                         if (host->data_size) {
2135                                 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2136                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2137                                 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2138                         } else {
2139                                 atmci_pdc_complete(host);
2140                         }
2141                 } else if (pending & ATMCI_ENDTX) {
2142                         dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2143                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2144
2145                         if (host->data_size) {
2146                                 atmci_pdc_set_single_buf(host,
2147                                                 XFER_TRANSMIT, PDC_SECOND_BUF);
2148                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2149                         }
2150                 }
2151
2152                 if (pending & ATMCI_RXBUFF) {
2153                         dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2154                         atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2155                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2156                         /*
2157                          * We can receive this interruption before having configured
2158                          * the second pdc buffer, so we need to reconfigure first and
2159                          * second buffers again
2160                          */
2161                         if (host->data_size) {
2162                                 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2163                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2164                                 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2165                         } else {
2166                                 atmci_pdc_complete(host);
2167                         }
2168                 } else if (pending & ATMCI_ENDRX) {
2169                         dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2170                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2171
2172                         if (host->data_size) {
2173                                 atmci_pdc_set_single_buf(host,
2174                                                 XFER_RECEIVE, PDC_SECOND_BUF);
2175                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2176                         }
2177                 }
2178
2179                 /*
2180                  * First mci IPs, so mainly the ones having pdc, have some
2181                  * issues with the notbusy signal. You can't get it after
2182                  * data transmission if you have not sent a stop command.
2183                  * The appropriate workaround is to use the BLKE signal.
2184                  */
2185                 if (pending & ATMCI_BLKE) {
2186                         dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2187                         atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2188                         smp_wmb();
2189                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2190                         atmci_set_pending(host, EVENT_NOTBUSY);
2191                         tasklet_schedule(&host->tasklet);
2192                 }
2193
2194                 if (pending & ATMCI_NOTBUSY) {
2195                         dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2196                         atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2197                         smp_wmb();
2198                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2199                         atmci_set_pending(host, EVENT_NOTBUSY);
2200                         tasklet_schedule(&host->tasklet);
2201                 }
2202
2203                 if (pending & ATMCI_RXRDY)
2204                         atmci_read_data_pio(host);
2205                 if (pending & ATMCI_TXRDY)
2206                         atmci_write_data_pio(host);
2207
2208                 if (pending & ATMCI_CMDRDY) {
2209                         dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2210                         atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2211                         host->cmd_status = status;
2212                         smp_wmb();
2213                         dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2214                         atmci_set_pending(host, EVENT_CMD_RDY);
2215                         tasklet_schedule(&host->tasklet);
2216                 }
2217
2218                 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2219                         atmci_sdio_interrupt(host, status);
2220
2221         } while (pass_count++ < 5);
2222
2223         return pass_count ? IRQ_HANDLED : IRQ_NONE;
2224 }
2225
2226 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2227 {
2228         struct atmel_mci_slot   *slot = dev_id;
2229
2230         /*
2231          * Disable interrupts until the pin has stabilized and check
2232          * the state then. Use mod_timer() since we may be in the
2233          * middle of the timer routine when this interrupt triggers.
2234          */
2235         disable_irq_nosync(irq);
2236         mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2237
2238         return IRQ_HANDLED;
2239 }
2240
2241 static int atmci_init_slot(struct atmel_mci *host,
2242                 struct mci_slot_pdata *slot_data, unsigned int id,
2243                 u32 sdc_reg, u32 sdio_irq)
2244 {
2245         struct mmc_host                 *mmc;
2246         struct atmel_mci_slot           *slot;
2247
2248         mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2249         if (!mmc)
2250                 return -ENOMEM;
2251
2252         slot = mmc_priv(mmc);
2253         slot->mmc = mmc;
2254         slot->host = host;
2255         slot->detect_pin = slot_data->detect_pin;
2256         slot->wp_pin = slot_data->wp_pin;
2257         slot->detect_is_active_high = slot_data->detect_is_active_high;
2258         slot->sdc_reg = sdc_reg;
2259         slot->sdio_irq = sdio_irq;
2260
2261         dev_dbg(&mmc->class_dev,
2262                 "slot[%u]: bus_width=%u, detect_pin=%d, "
2263                 "detect_is_active_high=%s, wp_pin=%d\n",
2264                 id, slot_data->bus_width, slot_data->detect_pin,
2265                 slot_data->detect_is_active_high ? "true" : "false",
2266                 slot_data->wp_pin);
2267
2268         mmc->ops = &atmci_ops;
2269         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2270         mmc->f_max = host->bus_hz / 2;
2271         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
2272         if (sdio_irq)
2273                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2274         if (host->caps.has_highspeed)
2275                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2276         /*
2277          * Without the read/write proof capability, it is strongly suggested to
2278          * use only one bit for data to prevent fifo underruns and overruns
2279          * which will corrupt data.
2280          */
2281         if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) {
2282                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2283                 if (slot_data->bus_width >= 8)
2284                         mmc->caps |= MMC_CAP_8_BIT_DATA;
2285         }
2286
2287         if (atmci_get_version(host) < 0x200) {
2288                 mmc->max_segs = 256;
2289                 mmc->max_blk_size = 4095;
2290                 mmc->max_blk_count = 256;
2291                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2292                 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2293         } else {
2294                 mmc->max_segs = 64;
2295                 mmc->max_req_size = 32768 * 512;
2296                 mmc->max_blk_size = 32768;
2297                 mmc->max_blk_count = 512;
2298         }
2299
2300         /* Assume card is present initially */
2301         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2302         if (gpio_is_valid(slot->detect_pin)) {
2303                 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
2304                                       "mmc_detect")) {
2305                         dev_dbg(&mmc->class_dev, "no detect pin available\n");
2306                         slot->detect_pin = -EBUSY;
2307                 } else if (gpio_get_value(slot->detect_pin) ^
2308                                 slot->detect_is_active_high) {
2309                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2310                 }
2311         }
2312
2313         if (!gpio_is_valid(slot->detect_pin)) {
2314                 if (slot_data->non_removable)
2315                         mmc->caps |= MMC_CAP_NONREMOVABLE;
2316                 else
2317                         mmc->caps |= MMC_CAP_NEEDS_POLL;
2318         }
2319
2320         if (gpio_is_valid(slot->wp_pin)) {
2321                 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
2322                                       "mmc_wp")) {
2323                         dev_dbg(&mmc->class_dev, "no WP pin available\n");
2324                         slot->wp_pin = -EBUSY;
2325                 }
2326         }
2327
2328         host->slot[id] = slot;
2329         mmc_regulator_get_supply(mmc);
2330         mmc_add_host(mmc);
2331
2332         if (gpio_is_valid(slot->detect_pin)) {
2333                 int ret;
2334
2335                 timer_setup(&slot->detect_timer, atmci_detect_change, 0);
2336
2337                 ret = request_irq(gpio_to_irq(slot->detect_pin),
2338                                 atmci_detect_interrupt,
2339                                 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2340                                 "mmc-detect", slot);
2341                 if (ret) {
2342                         dev_dbg(&mmc->class_dev,
2343                                 "could not request IRQ %d for detect pin\n",
2344                                 gpio_to_irq(slot->detect_pin));
2345                         slot->detect_pin = -EBUSY;
2346                 }
2347         }
2348
2349         atmci_init_debugfs(slot);
2350
2351         return 0;
2352 }
2353
2354 static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2355                 unsigned int id)
2356 {
2357         /* Debugfs stuff is cleaned up by mmc core */
2358
2359         set_bit(ATMCI_SHUTDOWN, &slot->flags);
2360         smp_wmb();
2361
2362         mmc_remove_host(slot->mmc);
2363
2364         if (gpio_is_valid(slot->detect_pin)) {
2365                 int pin = slot->detect_pin;
2366
2367                 free_irq(gpio_to_irq(pin), slot);
2368                 del_timer_sync(&slot->detect_timer);
2369         }
2370
2371         slot->host->slot[id] = NULL;
2372         mmc_free_host(slot->mmc);
2373 }
2374
2375 static int atmci_configure_dma(struct atmel_mci *host)
2376 {
2377         host->dma.chan = dma_request_slave_channel_reason(&host->pdev->dev,
2378                                                         "rxtx");
2379
2380         if (PTR_ERR(host->dma.chan) == -ENODEV) {
2381                 struct mci_platform_data *pdata = host->pdev->dev.platform_data;
2382                 dma_cap_mask_t mask;
2383
2384                 if (!pdata || !pdata->dma_filter)
2385                         return -ENODEV;
2386
2387                 dma_cap_zero(mask);
2388                 dma_cap_set(DMA_SLAVE, mask);
2389
2390                 host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
2391                                                      pdata->dma_slave);
2392                 if (!host->dma.chan)
2393                         host->dma.chan = ERR_PTR(-ENODEV);
2394         }
2395
2396         if (IS_ERR(host->dma.chan))
2397                 return PTR_ERR(host->dma.chan);
2398
2399         dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
2400                  dma_chan_name(host->dma.chan));
2401
2402         host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2403         host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2404         host->dma_conf.src_maxburst = 1;
2405         host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2406         host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2407         host->dma_conf.dst_maxburst = 1;
2408         host->dma_conf.device_fc = false;
2409
2410         return 0;
2411 }
2412
2413 /*
2414  * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2415  * HSMCI provides DMA support and a new config register but no more supports
2416  * PDC.
2417  */
2418 static void atmci_get_cap(struct atmel_mci *host)
2419 {
2420         unsigned int version;
2421
2422         version = atmci_get_version(host);
2423         dev_info(&host->pdev->dev,
2424                         "version: 0x%x\n", version);
2425
2426         host->caps.has_dma_conf_reg = 0;
2427         host->caps.has_pdc = 1;
2428         host->caps.has_cfg_reg = 0;
2429         host->caps.has_cstor_reg = 0;
2430         host->caps.has_highspeed = 0;
2431         host->caps.has_rwproof = 0;
2432         host->caps.has_odd_clk_div = 0;
2433         host->caps.has_bad_data_ordering = 1;
2434         host->caps.need_reset_after_xfer = 1;
2435         host->caps.need_blksz_mul_4 = 1;
2436         host->caps.need_notbusy_for_read_ops = 0;
2437
2438         /* keep only major version number */
2439         switch (version & 0xf00) {
2440         case 0x600:
2441         case 0x500:
2442                 host->caps.has_odd_clk_div = 1;
2443         case 0x400:
2444         case 0x300:
2445                 host->caps.has_dma_conf_reg = 1;
2446                 host->caps.has_pdc = 0;
2447                 host->caps.has_cfg_reg = 1;
2448                 host->caps.has_cstor_reg = 1;
2449                 host->caps.has_highspeed = 1;
2450         case 0x200:
2451                 host->caps.has_rwproof = 1;
2452                 host->caps.need_blksz_mul_4 = 0;
2453                 host->caps.need_notbusy_for_read_ops = 1;
2454         case 0x100:
2455                 host->caps.has_bad_data_ordering = 0;
2456                 host->caps.need_reset_after_xfer = 0;
2457         case 0x0:
2458                 break;
2459         default:
2460                 host->caps.has_pdc = 0;
2461                 dev_warn(&host->pdev->dev,
2462                                 "Unmanaged mci version, set minimum capabilities\n");
2463                 break;
2464         }
2465 }
2466
2467 static int atmci_probe(struct platform_device *pdev)
2468 {
2469         struct mci_platform_data        *pdata;
2470         struct atmel_mci                *host;
2471         struct resource                 *regs;
2472         unsigned int                    nr_slots;
2473         int                             irq;
2474         int                             ret, i;
2475
2476         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2477         if (!regs)
2478                 return -ENXIO;
2479         pdata = pdev->dev.platform_data;
2480         if (!pdata) {
2481                 pdata = atmci_of_init(pdev);
2482                 if (IS_ERR(pdata)) {
2483                         dev_err(&pdev->dev, "platform data not available\n");
2484                         return PTR_ERR(pdata);
2485                 }
2486         }
2487
2488         irq = platform_get_irq(pdev, 0);
2489         if (irq < 0)
2490                 return irq;
2491
2492         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2493         if (!host)
2494                 return -ENOMEM;
2495
2496         host->pdev = pdev;
2497         spin_lock_init(&host->lock);
2498         INIT_LIST_HEAD(&host->queue);
2499
2500         host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2501         if (IS_ERR(host->mck))
2502                 return PTR_ERR(host->mck);
2503
2504         host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2505         if (!host->regs)
2506                 return -ENOMEM;
2507
2508         ret = clk_prepare_enable(host->mck);
2509         if (ret)
2510                 return ret;
2511
2512         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2513         host->bus_hz = clk_get_rate(host->mck);
2514
2515         host->mapbase = regs->start;
2516
2517         tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2518
2519         ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2520         if (ret) {
2521                 clk_disable_unprepare(host->mck);
2522                 return ret;
2523         }
2524
2525         /* Get MCI capabilities and set operations according to it */
2526         atmci_get_cap(host);
2527         ret = atmci_configure_dma(host);
2528         if (ret == -EPROBE_DEFER)
2529                 goto err_dma_probe_defer;
2530         if (ret == 0) {
2531                 host->prepare_data = &atmci_prepare_data_dma;
2532                 host->submit_data = &atmci_submit_data_dma;
2533                 host->stop_transfer = &atmci_stop_transfer_dma;
2534         } else if (host->caps.has_pdc) {
2535                 dev_info(&pdev->dev, "using PDC\n");
2536                 host->prepare_data = &atmci_prepare_data_pdc;
2537                 host->submit_data = &atmci_submit_data_pdc;
2538                 host->stop_transfer = &atmci_stop_transfer_pdc;
2539         } else {
2540                 dev_info(&pdev->dev, "using PIO\n");
2541                 host->prepare_data = &atmci_prepare_data;
2542                 host->submit_data = &atmci_submit_data;
2543                 host->stop_transfer = &atmci_stop_transfer;
2544         }
2545
2546         platform_set_drvdata(pdev, host);
2547
2548         timer_setup(&host->timer, atmci_timeout_timer, 0);
2549
2550         pm_runtime_get_noresume(&pdev->dev);
2551         pm_runtime_set_active(&pdev->dev);
2552         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2553         pm_runtime_use_autosuspend(&pdev->dev);
2554         pm_runtime_enable(&pdev->dev);
2555
2556         /* We need at least one slot to succeed */
2557         nr_slots = 0;
2558         ret = -ENODEV;
2559         if (pdata->slot[0].bus_width) {
2560                 ret = atmci_init_slot(host, &pdata->slot[0],
2561                                 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2562                 if (!ret) {
2563                         nr_slots++;
2564                         host->buf_size = host->slot[0]->mmc->max_req_size;
2565                 }
2566         }
2567         if (pdata->slot[1].bus_width) {
2568                 ret = atmci_init_slot(host, &pdata->slot[1],
2569                                 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2570                 if (!ret) {
2571                         nr_slots++;
2572                         if (host->slot[1]->mmc->max_req_size > host->buf_size)
2573                                 host->buf_size =
2574                                         host->slot[1]->mmc->max_req_size;
2575                 }
2576         }
2577
2578         if (!nr_slots) {
2579                 dev_err(&pdev->dev, "init failed: no slot defined\n");
2580                 goto err_init_slot;
2581         }
2582
2583         if (!host->caps.has_rwproof) {
2584                 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2585                                                   &host->buf_phys_addr,
2586                                                   GFP_KERNEL);
2587                 if (!host->buffer) {
2588                         ret = -ENOMEM;
2589                         dev_err(&pdev->dev, "buffer allocation failed\n");
2590                         goto err_dma_alloc;
2591                 }
2592         }
2593
2594         dev_info(&pdev->dev,
2595                         "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2596                         host->mapbase, irq, nr_slots);
2597
2598         pm_runtime_mark_last_busy(&host->pdev->dev);
2599         pm_runtime_put_autosuspend(&pdev->dev);
2600
2601         return 0;
2602
2603 err_dma_alloc:
2604         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2605                 if (host->slot[i])
2606                         atmci_cleanup_slot(host->slot[i], i);
2607         }
2608 err_init_slot:
2609         clk_disable_unprepare(host->mck);
2610
2611         pm_runtime_disable(&pdev->dev);
2612         pm_runtime_put_noidle(&pdev->dev);
2613
2614         del_timer_sync(&host->timer);
2615         if (!IS_ERR(host->dma.chan))
2616                 dma_release_channel(host->dma.chan);
2617 err_dma_probe_defer:
2618         free_irq(irq, host);
2619         return ret;
2620 }
2621
2622 static int atmci_remove(struct platform_device *pdev)
2623 {
2624         struct atmel_mci        *host = platform_get_drvdata(pdev);
2625         unsigned int            i;
2626
2627         pm_runtime_get_sync(&pdev->dev);
2628
2629         if (host->buffer)
2630                 dma_free_coherent(&pdev->dev, host->buf_size,
2631                                   host->buffer, host->buf_phys_addr);
2632
2633         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2634                 if (host->slot[i])
2635                         atmci_cleanup_slot(host->slot[i], i);
2636         }
2637
2638         atmci_writel(host, ATMCI_IDR, ~0UL);
2639         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2640         atmci_readl(host, ATMCI_SR);
2641
2642         del_timer_sync(&host->timer);
2643         if (!IS_ERR(host->dma.chan))
2644                 dma_release_channel(host->dma.chan);
2645
2646         free_irq(platform_get_irq(pdev, 0), host);
2647
2648         clk_disable_unprepare(host->mck);
2649
2650         pm_runtime_disable(&pdev->dev);
2651         pm_runtime_put_noidle(&pdev->dev);
2652
2653         return 0;
2654 }
2655
2656 #ifdef CONFIG_PM
2657 static int atmci_runtime_suspend(struct device *dev)
2658 {
2659         struct atmel_mci *host = dev_get_drvdata(dev);
2660
2661         clk_disable_unprepare(host->mck);
2662
2663         pinctrl_pm_select_sleep_state(dev);
2664
2665         return 0;
2666 }
2667
2668 static int atmci_runtime_resume(struct device *dev)
2669 {
2670         struct atmel_mci *host = dev_get_drvdata(dev);
2671
2672         pinctrl_pm_select_default_state(dev);
2673
2674         return clk_prepare_enable(host->mck);
2675 }
2676 #endif
2677
2678 static const struct dev_pm_ops atmci_dev_pm_ops = {
2679         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2680                                 pm_runtime_force_resume)
2681         SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2682 };
2683
2684 static struct platform_driver atmci_driver = {
2685         .probe          = atmci_probe,
2686         .remove         = atmci_remove,
2687         .driver         = {
2688                 .name           = "atmel_mci",
2689                 .of_match_table = of_match_ptr(atmci_dt_ids),
2690                 .pm             = &atmci_dev_pm_ops,
2691         },
2692 };
2693 module_platform_driver(atmci_driver);
2694
2695 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2696 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2697 MODULE_LICENSE("GPL v2");