1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Oleksij Rempel <linux@rempel-privat.de>
5 * Driver for Alcor Micro AU6601 and AU6621 controllers
8 /* Note: this driver was created without any documentation. Based
9 * on sniffing, testing and in some cases mimic of original driver.
10 * As soon as some one with documentation or more experience in SD/MMC, or
11 * reverse engineering then me, please review this driver and question every
12 * thing what I did. 2018 Oleksij Rempel <linux@rempel-privat.de>
15 #include <linux/delay.h>
16 #include <linux/pci.h>
17 #include <linux/module.h>
20 #include <linux/irq.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/mmc.h>
27 #include <linux/alcor_pci.h>
35 struct alcor_pll_conf {
36 unsigned int clk_src_freq;
37 unsigned int clk_src_reg;
42 struct alcor_sdmmc_host {
44 struct alcor_pci_priv *alcor_pci;
47 struct mmc_request *mrq;
48 struct mmc_command *cmd;
49 struct mmc_data *data;
50 unsigned int dma_on:1;
52 struct mutex cmd_mutex;
54 struct delayed_work timeout_work;
56 struct sg_mapping_iter sg_miter; /* SG state for PIO */
57 struct scatterlist *sg;
58 unsigned int blocks; /* remaining PIO blocks */
62 unsigned char cur_power_mode;
65 static const struct alcor_pll_conf alcor_pll_cfg[] = {
66 /* MHZ, CLK src, max div, min div */
67 { 31250000, AU6601_CLK_31_25_MHZ, 1, 511},
68 { 48000000, AU6601_CLK_48_MHZ, 1, 511},
69 {125000000, AU6601_CLK_125_MHZ, 1, 511},
70 {384000000, AU6601_CLK_384_MHZ, 1, 511},
73 static inline void alcor_rmw8(struct alcor_sdmmc_host *host, unsigned int addr,
76 struct alcor_pci_priv *priv = host->alcor_pci;
79 var = alcor_read8(priv, addr);
82 alcor_write8(priv, var, addr);
85 /* As soon as irqs are masked, some status updates may be missed.
88 static inline void alcor_mask_sd_irqs(struct alcor_sdmmc_host *host)
90 struct alcor_pci_priv *priv = host->alcor_pci;
92 alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
95 static inline void alcor_unmask_sd_irqs(struct alcor_sdmmc_host *host)
97 struct alcor_pci_priv *priv = host->alcor_pci;
99 alcor_write32(priv, AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK |
100 AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE |
101 AU6601_INT_OVER_CURRENT_ERR,
102 AU6601_REG_INT_ENABLE);
105 static void alcor_reset(struct alcor_sdmmc_host *host, u8 val)
107 struct alcor_pci_priv *priv = host->alcor_pci;
110 alcor_write8(priv, val | AU6601_BUF_CTRL_RESET,
111 AU6601_REG_SW_RESET);
112 for (i = 0; i < 100; i++) {
113 if (!(alcor_read8(priv, AU6601_REG_SW_RESET) & val))
117 dev_err(host->dev, "%s: timeout\n", __func__);
120 static void alcor_data_set_dma(struct alcor_sdmmc_host *host)
122 struct alcor_pci_priv *priv = host->alcor_pci;
129 dev_err(host->dev, "have blocks, but no SG\n");
133 if (!sg_dma_len(host->sg)) {
134 dev_err(host->dev, "DMA SG len == 0\n");
139 addr = (u32)sg_dma_address(host->sg);
141 alcor_write32(priv, addr, AU6601_REG_SDMA_ADDR);
142 host->sg = sg_next(host->sg);
146 static void alcor_trigger_data_transfer(struct alcor_sdmmc_host *host)
148 struct alcor_pci_priv *priv = host->alcor_pci;
149 struct mmc_data *data = host->data;
152 if (data->flags & MMC_DATA_WRITE)
153 ctrl |= AU6601_DATA_WRITE;
155 if (data->host_cookie == COOKIE_MAPPED) {
156 alcor_data_set_dma(host);
157 ctrl |= AU6601_DATA_DMA_MODE;
159 alcor_write32(priv, data->sg_count * 0x1000,
160 AU6601_REG_BLOCK_SIZE);
162 alcor_write32(priv, data->blksz, AU6601_REG_BLOCK_SIZE);
165 alcor_write8(priv, ctrl | AU6601_DATA_START_XFER,
166 AU6601_DATA_XFER_CTRL);
169 static void alcor_trf_block_pio(struct alcor_sdmmc_host *host, bool read)
171 struct alcor_pci_priv *priv = host->alcor_pci;
179 dev_err(host->dev, "configured DMA but got PIO request.\n");
183 if (!!(host->data->flags & MMC_DATA_READ) != read) {
184 dev_err(host->dev, "got unexpected direction %i != %i\n",
185 !!(host->data->flags & MMC_DATA_READ), read);
188 if (!sg_miter_next(&host->sg_miter))
191 blksize = host->data->blksz;
192 len = min(host->sg_miter.length, blksize);
194 dev_dbg(host->dev, "PIO, %s block size: 0x%zx\n",
195 read ? "read" : "write", blksize);
197 host->sg_miter.consumed = len;
200 buf = host->sg_miter.addr;
203 ioread32_rep(priv->iobase + AU6601_REG_BUFFER, buf, len >> 2);
205 iowrite32_rep(priv->iobase + AU6601_REG_BUFFER, buf, len >> 2);
207 sg_miter_stop(&host->sg_miter);
210 static void alcor_prepare_sg_miter(struct alcor_sdmmc_host *host)
212 unsigned int flags = SG_MITER_ATOMIC;
213 struct mmc_data *data = host->data;
215 if (data->flags & MMC_DATA_READ)
216 flags |= SG_MITER_TO_SG;
218 flags |= SG_MITER_FROM_SG;
219 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
222 static void alcor_prepare_data(struct alcor_sdmmc_host *host,
223 struct mmc_command *cmd)
225 struct alcor_pci_priv *priv = host->alcor_pci;
226 struct mmc_data *data = cmd->data;
233 host->data->bytes_xfered = 0;
234 host->blocks = data->blocks;
236 host->sg_count = data->sg_count;
237 dev_dbg(host->dev, "prepare DATA: sg %i, blocks: %i\n",
238 host->sg_count, host->blocks);
240 if (data->host_cookie != COOKIE_MAPPED)
241 alcor_prepare_sg_miter(host);
243 alcor_write8(priv, 0, AU6601_DATA_XFER_CTRL);
246 static void alcor_send_cmd(struct alcor_sdmmc_host *host,
247 struct mmc_command *cmd, bool set_timeout)
249 struct alcor_pci_priv *priv = host->alcor_pci;
250 unsigned long timeout = 0;
254 alcor_prepare_data(host, cmd);
256 dev_dbg(host->dev, "send CMD. opcode: 0x%02x, arg; 0x%08x\n",
257 cmd->opcode, cmd->arg);
258 alcor_write8(priv, cmd->opcode | 0x40, AU6601_REG_CMD_OPCODE);
259 alcor_write32be(priv, cmd->arg, AU6601_REG_CMD_ARG);
261 switch (mmc_resp_type(cmd)) {
263 ctrl = AU6601_CMD_NO_RESP;
266 ctrl = AU6601_CMD_6_BYTE_CRC;
269 ctrl = AU6601_CMD_6_BYTE_CRC | AU6601_CMD_STOP_WAIT_RDY;
272 ctrl = AU6601_CMD_17_BYTE_CRC;
275 ctrl = AU6601_CMD_6_BYTE_WO_CRC;
278 dev_err(host->dev, "%s: cmd->flag (0x%02x) is not valid\n",
279 mmc_hostname(host->mmc), mmc_resp_type(cmd));
284 if (!cmd->data && cmd->busy_timeout)
285 timeout = cmd->busy_timeout;
289 schedule_delayed_work(&host->timeout_work,
290 msecs_to_jiffies(timeout));
293 dev_dbg(host->dev, "xfer ctrl: 0x%02x; timeout: %lu\n", ctrl, timeout);
294 alcor_write8(priv, ctrl | AU6601_CMD_START_XFER,
295 AU6601_CMD_XFER_CTRL);
298 static void alcor_request_complete(struct alcor_sdmmc_host *host,
301 struct mmc_request *mrq;
304 * If this work gets rescheduled while running, it will
305 * be run again afterwards but without any active request.
311 cancel_delayed_work(&host->timeout_work);
320 mmc_request_done(host->mmc, mrq);
323 static void alcor_finish_data(struct alcor_sdmmc_host *host)
325 struct mmc_data *data;
332 * The specification states that the block count register must
333 * be updated, but it does not specify at what point in the
334 * data flow. That makes the register entirely useless to read
335 * back so we have to assume that nothing made it to the card
336 * in the event of an error.
339 data->bytes_xfered = 0;
341 data->bytes_xfered = data->blksz * data->blocks;
344 * Need to send CMD12 if -
345 * a) open-ended multiblock transfer (no CMD23)
346 * b) error in multiblock transfer
353 * The controller needs a reset of internal state machines
354 * upon error conditions.
357 alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA);
359 alcor_unmask_sd_irqs(host);
360 alcor_send_cmd(host, data->stop, false);
364 alcor_request_complete(host, 1);
367 static void alcor_err_irq(struct alcor_sdmmc_host *host, u32 intmask)
369 dev_dbg(host->dev, "ERR IRQ %x\n", intmask);
372 if (intmask & AU6601_INT_CMD_TIMEOUT_ERR)
373 host->cmd->error = -ETIMEDOUT;
375 host->cmd->error = -EILSEQ;
379 if (intmask & AU6601_INT_DATA_TIMEOUT_ERR)
380 host->data->error = -ETIMEDOUT;
382 host->data->error = -EILSEQ;
384 host->data->bytes_xfered = 0;
387 alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA);
388 alcor_request_complete(host, 1);
391 static int alcor_cmd_irq_done(struct alcor_sdmmc_host *host, u32 intmask)
393 struct alcor_pci_priv *priv = host->alcor_pci;
395 intmask &= AU6601_INT_CMD_END;
400 /* got CMD_END but no CMD is in progress, wake thread an process the
406 if (host->cmd->flags & MMC_RSP_PRESENT) {
407 struct mmc_command *cmd = host->cmd;
409 cmd->resp[0] = alcor_read32be(priv, AU6601_REG_CMD_RSP0);
410 dev_dbg(host->dev, "RSP0: 0x%04x\n", cmd->resp[0]);
411 if (host->cmd->flags & MMC_RSP_136) {
413 alcor_read32be(priv, AU6601_REG_CMD_RSP1);
415 alcor_read32be(priv, AU6601_REG_CMD_RSP2);
417 alcor_read32be(priv, AU6601_REG_CMD_RSP3);
418 dev_dbg(host->dev, "RSP1,2,3: 0x%04x 0x%04x 0x%04x\n",
419 cmd->resp[1], cmd->resp[2], cmd->resp[3]);
424 host->cmd->error = 0;
426 /* Processed actual command. */
430 alcor_trigger_data_transfer(host);
435 static void alcor_cmd_irq_thread(struct alcor_sdmmc_host *host, u32 intmask)
437 intmask &= AU6601_INT_CMD_END;
442 if (!host->cmd && intmask & AU6601_INT_CMD_END) {
443 dev_dbg(host->dev, "Got command interrupt 0x%08x even though no command operation was in progress.\n",
447 /* Processed actual command. */
449 alcor_request_complete(host, 1);
451 alcor_trigger_data_transfer(host);
455 static int alcor_data_irq_done(struct alcor_sdmmc_host *host, u32 intmask)
459 intmask &= AU6601_INT_DATA_MASK;
461 /* nothing here to do */
465 /* we was too fast and got DATA_END after it was processed?
466 * lets ignore it for now.
468 if (!host->data && intmask == AU6601_INT_DATA_END)
471 /* looks like an error, so lets handle it. */
475 tmp = intmask & (AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY
476 | AU6601_INT_DMA_END);
480 case AU6601_INT_READ_BUF_RDY:
481 alcor_trf_block_pio(host, true);
483 case AU6601_INT_WRITE_BUF_RDY:
484 alcor_trf_block_pio(host, false);
486 case AU6601_INT_DMA_END:
490 alcor_data_set_dma(host);
493 dev_err(host->dev, "Got READ_BUF_RDY and WRITE_BUF_RDY at same time\n");
497 if (intmask & AU6601_INT_DATA_END) {
498 if (!host->dma_on && host->blocks) {
499 alcor_trigger_data_transfer(host);
509 static void alcor_data_irq_thread(struct alcor_sdmmc_host *host, u32 intmask)
511 intmask &= AU6601_INT_DATA_MASK;
517 dev_dbg(host->dev, "Got data interrupt 0x%08x even though no data operation was in progress.\n",
519 alcor_reset(host, AU6601_RESET_DATA);
523 if (alcor_data_irq_done(host, intmask))
526 if ((intmask & AU6601_INT_DATA_END) || !host->blocks ||
527 (host->dma_on && !host->sg_count))
528 alcor_finish_data(host);
531 static void alcor_cd_irq(struct alcor_sdmmc_host *host, u32 intmask)
533 dev_dbg(host->dev, "card %s\n",
534 intmask & AU6601_INT_CARD_REMOVE ? "removed" : "inserted");
537 dev_dbg(host->dev, "cancel all pending tasks.\n");
540 host->data->error = -ENOMEDIUM;
543 host->cmd->error = -ENOMEDIUM;
545 host->mrq->cmd->error = -ENOMEDIUM;
547 alcor_request_complete(host, 1);
550 mmc_detect_change(host->mmc, msecs_to_jiffies(1));
553 static irqreturn_t alcor_irq_thread(int irq, void *d)
555 struct alcor_sdmmc_host *host = d;
556 irqreturn_t ret = IRQ_HANDLED;
559 mutex_lock(&host->cmd_mutex);
561 intmask = host->irq_status_sd;
564 if (unlikely(!intmask || AU6601_INT_ALL_MASK == intmask)) {
565 dev_dbg(host->dev, "unexpected IRQ: 0x%04x\n", intmask);
570 tmp = intmask & (AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK);
572 if (tmp & AU6601_INT_ERROR_MASK)
573 alcor_err_irq(host, tmp);
575 alcor_cmd_irq_thread(host, tmp);
576 alcor_data_irq_thread(host, tmp);
578 intmask &= ~(AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK);
581 if (intmask & (AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE)) {
582 alcor_cd_irq(host, intmask);
583 intmask &= ~(AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE);
586 if (intmask & AU6601_INT_OVER_CURRENT_ERR) {
588 "warning: over current detected!\n");
589 intmask &= ~AU6601_INT_OVER_CURRENT_ERR;
593 dev_dbg(host->dev, "got not handled IRQ: 0x%04x\n", intmask);
596 mutex_unlock(&host->cmd_mutex);
597 alcor_unmask_sd_irqs(host);
602 static irqreturn_t alcor_irq(int irq, void *d)
604 struct alcor_sdmmc_host *host = d;
605 struct alcor_pci_priv *priv = host->alcor_pci;
608 int cmd_done, data_done;
610 status = alcor_read32(priv, AU6601_REG_INT_STATUS);
614 alcor_write32(priv, status, AU6601_REG_INT_STATUS);
616 tmp = status & (AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY
617 | AU6601_INT_DATA_END | AU6601_INT_DMA_END
618 | AU6601_INT_CMD_END);
620 cmd_done = alcor_cmd_irq_done(host, tmp);
621 data_done = alcor_data_irq_done(host, tmp);
622 /* use fast path for simple tasks */
623 if (cmd_done && data_done) {
629 host->irq_status_sd = status;
630 ret = IRQ_WAKE_THREAD;
631 alcor_mask_sd_irqs(host);
636 static void alcor_set_clock(struct alcor_sdmmc_host *host, unsigned int clock)
638 struct alcor_pci_priv *priv = host->alcor_pci;
639 int i, diff = 0x7fffffff, tmp_clock = 0;
644 alcor_write16(priv, 0, AU6601_CLK_SELECT);
648 for (i = 0; i < ARRAY_SIZE(alcor_pll_cfg); i++) {
649 unsigned int tmp_div, tmp_diff;
650 const struct alcor_pll_conf *cfg = &alcor_pll_cfg[i];
652 tmp_div = DIV_ROUND_UP(cfg->clk_src_freq, clock);
653 if (cfg->min_div > tmp_div || tmp_div > cfg->max_div)
656 tmp_clock = DIV_ROUND_UP(cfg->clk_src_freq, tmp_div);
657 tmp_diff = abs(clock - tmp_clock);
659 if (tmp_diff >= 0 && tmp_diff < diff) {
661 clk_src = cfg->clk_src_reg;
666 clk_src |= ((clk_div - 1) << 8);
667 clk_src |= AU6601_CLK_ENABLE;
669 dev_dbg(host->dev, "set freq %d cal freq %d, use div %d, mod %x\n",
670 clock, tmp_clock, clk_div, clk_src);
672 alcor_write16(priv, clk_src, AU6601_CLK_SELECT);
676 static void alcor_set_timing(struct mmc_host *mmc, struct mmc_ios *ios)
678 struct alcor_sdmmc_host *host = mmc_priv(mmc);
680 if (ios->timing == MMC_TIMING_LEGACY) {
681 alcor_rmw8(host, AU6601_CLK_DELAY,
682 AU6601_CLK_POSITIVE_EDGE_ALL, 0);
684 alcor_rmw8(host, AU6601_CLK_DELAY,
685 0, AU6601_CLK_POSITIVE_EDGE_ALL);
689 static void alcor_set_bus_width(struct mmc_host *mmc, struct mmc_ios *ios)
691 struct alcor_sdmmc_host *host = mmc_priv(mmc);
692 struct alcor_pci_priv *priv = host->alcor_pci;
694 if (ios->bus_width == MMC_BUS_WIDTH_1) {
695 alcor_write8(priv, 0, AU6601_REG_BUS_CTRL);
696 } else if (ios->bus_width == MMC_BUS_WIDTH_4) {
697 alcor_write8(priv, AU6601_BUS_WIDTH_4BIT,
698 AU6601_REG_BUS_CTRL);
700 dev_err(host->dev, "Unknown BUS mode\n");
704 static int alcor_card_busy(struct mmc_host *mmc)
706 struct alcor_sdmmc_host *host = mmc_priv(mmc);
707 struct alcor_pci_priv *priv = host->alcor_pci;
710 /* Check whether dat[0:3] low */
711 status = alcor_read8(priv, AU6601_DATA_PIN_STATE);
713 return !(status & AU6601_BUS_STAT_DAT_MASK);
716 static int alcor_get_cd(struct mmc_host *mmc)
718 struct alcor_sdmmc_host *host = mmc_priv(mmc);
719 struct alcor_pci_priv *priv = host->alcor_pci;
722 detect = alcor_read8(priv, AU6601_DETECT_STATUS)
723 & AU6601_DETECT_STATUS_M;
724 /* check if card is present then send command and data */
725 return (detect == AU6601_SD_DETECTED);
728 static int alcor_get_ro(struct mmc_host *mmc)
730 struct alcor_sdmmc_host *host = mmc_priv(mmc);
731 struct alcor_pci_priv *priv = host->alcor_pci;
734 /* get write protect pin status */
735 status = alcor_read8(priv, AU6601_INTERFACE_MODE_CTRL);
737 return !!(status & AU6601_SD_CARD_WP);
740 static void alcor_request(struct mmc_host *mmc, struct mmc_request *mrq)
742 struct alcor_sdmmc_host *host = mmc_priv(mmc);
744 mutex_lock(&host->cmd_mutex);
748 /* check if card is present then send command and data */
749 if (alcor_get_cd(mmc))
750 alcor_send_cmd(host, mrq->cmd, true);
752 mrq->cmd->error = -ENOMEDIUM;
753 alcor_request_complete(host, 1);
756 mutex_unlock(&host->cmd_mutex);
759 static void alcor_pre_req(struct mmc_host *mmc,
760 struct mmc_request *mrq)
762 struct alcor_sdmmc_host *host = mmc_priv(mmc);
763 struct mmc_data *data = mrq->data;
764 struct mmc_command *cmd = mrq->cmd;
765 struct scatterlist *sg;
766 unsigned int i, sg_len;
771 data->host_cookie = COOKIE_UNMAPPED;
773 /* FIXME: looks like the DMA engine works only with CMD18 */
774 if (cmd->opcode != 18)
777 * We don't do DMA on "complex" transfers, i.e. with
778 * non-word-aligned buffers or lengths. Also, we don't bother
779 * with all the DMA setup overhead for short transfers.
781 if (data->blocks * data->blksz < AU6601_MAX_DMA_BLOCK_SIZE)
787 for_each_sg(data->sg, sg, data->sg_len, i) {
788 if (sg->length != AU6601_MAX_DMA_BLOCK_SIZE)
792 /* This data might be unmapped at this time */
794 sg_len = dma_map_sg(host->dev, data->sg, data->sg_len,
795 mmc_get_dma_dir(data));
797 data->host_cookie = COOKIE_MAPPED;
799 data->sg_count = sg_len;
802 static void alcor_post_req(struct mmc_host *mmc,
803 struct mmc_request *mrq,
806 struct alcor_sdmmc_host *host = mmc_priv(mmc);
807 struct mmc_data *data = mrq->data;
812 if (data->host_cookie == COOKIE_MAPPED) {
813 dma_unmap_sg(host->dev,
816 mmc_get_dma_dir(data));
819 data->host_cookie = COOKIE_UNMAPPED;
822 static void alcor_set_power_mode(struct mmc_host *mmc, struct mmc_ios *ios)
824 struct alcor_sdmmc_host *host = mmc_priv(mmc);
825 struct alcor_pci_priv *priv = host->alcor_pci;
827 switch (ios->power_mode) {
829 alcor_set_clock(host, ios->clock);
830 /* set all pins to input */
831 alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE);
833 alcor_write8(priv, 0, AU6601_POWER_CONTROL);
838 /* This is most trickiest part. The order and timings of
839 * instructions seems to play important role. Any changes may
840 * confuse internal state engine if this HW.
841 * FIXME: If we will ever get access to documentation, then this
842 * part should be reviewed again.
845 /* enable SD card mode */
846 alcor_write8(priv, AU6601_SD_CARD,
848 /* set signal voltage to 3.3V */
849 alcor_write8(priv, 0, AU6601_OPT);
850 /* no documentation about clk delay, for now just try to mimic
853 alcor_write8(priv, 0x20, AU6601_CLK_DELAY);
854 /* set BUS width to 1 bit */
855 alcor_write8(priv, 0, AU6601_REG_BUS_CTRL);
856 /* set CLK first time */
857 alcor_set_clock(host, ios->clock);
859 alcor_write8(priv, AU6601_SD_CARD,
860 AU6601_POWER_CONTROL);
861 /* wait until the CLK will get stable */
863 /* set CLK again, mimic original driver. */
864 alcor_set_clock(host, ios->clock);
867 alcor_write8(priv, AU6601_SD_CARD,
868 AU6601_OUTPUT_ENABLE);
869 /* The clk will not work on au6621. We need to trigger data
872 alcor_write8(priv, AU6601_DATA_WRITE,
873 AU6601_DATA_XFER_CTRL);
874 /* configure timeout. Not clear what exactly it means. */
875 alcor_write8(priv, 0x7d, AU6601_TIME_OUT_CTRL);
879 dev_err(host->dev, "Unknown power parameter\n");
883 static void alcor_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
885 struct alcor_sdmmc_host *host = mmc_priv(mmc);
887 mutex_lock(&host->cmd_mutex);
889 dev_dbg(host->dev, "set ios. bus width: %x, power mode: %x\n",
890 ios->bus_width, ios->power_mode);
892 if (ios->power_mode != host->cur_power_mode) {
893 alcor_set_power_mode(mmc, ios);
894 host->cur_power_mode = ios->power_mode;
896 alcor_set_timing(mmc, ios);
897 alcor_set_bus_width(mmc, ios);
898 alcor_set_clock(host, ios->clock);
901 mutex_unlock(&host->cmd_mutex);
904 static int alcor_signal_voltage_switch(struct mmc_host *mmc,
907 struct alcor_sdmmc_host *host = mmc_priv(mmc);
909 mutex_lock(&host->cmd_mutex);
911 switch (ios->signal_voltage) {
912 case MMC_SIGNAL_VOLTAGE_330:
913 alcor_rmw8(host, AU6601_OPT, AU6601_OPT_SD_18V, 0);
915 case MMC_SIGNAL_VOLTAGE_180:
916 alcor_rmw8(host, AU6601_OPT, 0, AU6601_OPT_SD_18V);
919 /* No signal voltage switch required */
923 mutex_unlock(&host->cmd_mutex);
927 static const struct mmc_host_ops alcor_sdc_ops = {
928 .card_busy = alcor_card_busy,
929 .get_cd = alcor_get_cd,
930 .get_ro = alcor_get_ro,
931 .post_req = alcor_post_req,
932 .pre_req = alcor_pre_req,
933 .request = alcor_request,
934 .set_ios = alcor_set_ios,
935 .start_signal_voltage_switch = alcor_signal_voltage_switch,
938 static void alcor_timeout_timer(struct work_struct *work)
940 struct delayed_work *d = to_delayed_work(work);
941 struct alcor_sdmmc_host *host = container_of(d, struct alcor_sdmmc_host,
943 mutex_lock(&host->cmd_mutex);
945 dev_dbg(host->dev, "triggered timeout\n");
947 dev_err(host->dev, "Timeout waiting for hardware interrupt.\n");
950 host->data->error = -ETIMEDOUT;
953 host->cmd->error = -ETIMEDOUT;
955 host->mrq->cmd->error = -ETIMEDOUT;
958 alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA);
959 alcor_request_complete(host, 0);
963 mutex_unlock(&host->cmd_mutex);
966 static void alcor_hw_init(struct alcor_sdmmc_host *host)
968 struct alcor_pci_priv *priv = host->alcor_pci;
969 struct alcor_dev_cfg *cfg = priv->cfg;
971 /* FIXME: This part is a mimics HW init of original driver.
972 * If we will ever get access to documentation, then this part
973 * should be reviewed again.
976 /* reset command state engine */
977 alcor_reset(host, AU6601_RESET_CMD);
979 alcor_write8(priv, 0, AU6601_DMA_BOUNDARY);
980 /* enable sd card mode */
981 alcor_write8(priv, AU6601_SD_CARD, AU6601_ACTIVE_CTRL);
983 /* set BUS width to 1 bit */
984 alcor_write8(priv, 0, AU6601_REG_BUS_CTRL);
986 /* reset data state engine */
987 alcor_reset(host, AU6601_RESET_DATA);
988 /* Not sure if a voodoo with AU6601_DMA_BOUNDARY is really needed */
989 alcor_write8(priv, 0, AU6601_DMA_BOUNDARY);
991 alcor_write8(priv, 0, AU6601_INTERFACE_MODE_CTRL);
992 /* not clear what we are doing here. */
993 alcor_write8(priv, 0x44, AU6601_PAD_DRIVE0);
994 alcor_write8(priv, 0x44, AU6601_PAD_DRIVE1);
995 alcor_write8(priv, 0x00, AU6601_PAD_DRIVE2);
997 /* for 6601 - dma_boundary; for 6621 - dma_page_cnt
998 * exact meaning of this register is not clear.
1000 alcor_write8(priv, cfg->dma, AU6601_DMA_BOUNDARY);
1002 /* make sure all pins are set to input and VDD is off */
1003 alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE);
1004 alcor_write8(priv, 0, AU6601_POWER_CONTROL);
1006 alcor_write8(priv, AU6601_DETECT_EN, AU6601_DETECT_STATUS);
1007 /* now we should be safe to enable IRQs */
1008 alcor_unmask_sd_irqs(host);
1011 static void alcor_hw_uninit(struct alcor_sdmmc_host *host)
1013 struct alcor_pci_priv *priv = host->alcor_pci;
1015 alcor_mask_sd_irqs(host);
1016 alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA);
1018 alcor_write8(priv, 0, AU6601_DETECT_STATUS);
1020 alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE);
1021 alcor_write8(priv, 0, AU6601_POWER_CONTROL);
1023 alcor_write8(priv, 0, AU6601_OPT);
1026 static void alcor_init_mmc(struct alcor_sdmmc_host *host)
1028 struct mmc_host *mmc = host->mmc;
1030 mmc->f_min = AU6601_MIN_CLOCK;
1031 mmc->f_max = AU6601_MAX_CLOCK;
1032 mmc->ocr_avail = MMC_VDD_33_34;
1033 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED
1034 | MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
1035 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50;
1036 mmc->caps2 = MMC_CAP2_NO_SDIO;
1037 mmc->ops = &alcor_sdc_ops;
1039 /* The hardware does DMA data transfer of 4096 bytes to/from a single
1040 * buffer address. Scatterlists are not supported, but upon DMA
1041 * completion (signalled via IRQ), the original vendor driver does
1042 * then immediately set up another DMA transfer of the next 4096
1045 * This means that we need to handle the I/O in 4096 byte chunks.
1046 * Lacking a way to limit the sglist entries to 4096 bytes, we instead
1047 * impose that only one segment is provided, with maximum size 4096,
1048 * which also happens to be the minimum size. This means that the
1049 * single-entry sglist handled by this driver can be handed directly
1050 * to the hardware, nice and simple.
1052 * Unfortunately though, that means we only do 4096 bytes I/O per
1053 * MMC command. A future improvement would be to make the driver
1054 * accept sg lists and entries of any size, and simply iterate
1055 * through them 4096 bytes at a time.
1057 mmc->max_segs = AU6601_MAX_DMA_SEGMENTS;
1058 mmc->max_seg_size = AU6601_MAX_DMA_BLOCK_SIZE;
1059 mmc->max_req_size = mmc->max_seg_size;
1062 static int alcor_pci_sdmmc_drv_probe(struct platform_device *pdev)
1064 struct alcor_pci_priv *priv = pdev->dev.platform_data;
1065 struct mmc_host *mmc;
1066 struct alcor_sdmmc_host *host;
1069 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1071 dev_err(&pdev->dev, "Can't allocate MMC\n");
1075 host = mmc_priv(mmc);
1077 host->dev = &pdev->dev;
1078 host->cur_power_mode = MMC_POWER_UNDEFINED;
1079 host->alcor_pci = priv;
1081 /* make sure irqs are disabled */
1082 alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
1083 alcor_write32(priv, 0, AU6601_MS_INT_ENABLE);
1085 ret = devm_request_threaded_irq(&pdev->dev, priv->irq,
1086 alcor_irq, alcor_irq_thread, IRQF_SHARED,
1087 DRV_NAME_ALCOR_PCI_SDMMC, host);
1090 dev_err(&pdev->dev, "Failed to get irq for data line\n");
1094 mutex_init(&host->cmd_mutex);
1095 INIT_DELAYED_WORK(&host->timeout_work, alcor_timeout_timer);
1097 alcor_init_mmc(host);
1098 alcor_hw_init(host);
1100 dev_set_drvdata(&pdev->dev, host);
1105 static int alcor_pci_sdmmc_drv_remove(struct platform_device *pdev)
1107 struct alcor_sdmmc_host *host = dev_get_drvdata(&pdev->dev);
1109 if (cancel_delayed_work_sync(&host->timeout_work))
1110 alcor_request_complete(host, 0);
1112 alcor_hw_uninit(host);
1113 mmc_remove_host(host->mmc);
1114 mmc_free_host(host->mmc);
1119 #ifdef CONFIG_PM_SLEEP
1120 static int alcor_pci_sdmmc_suspend(struct device *dev)
1122 struct alcor_sdmmc_host *host = dev_get_drvdata(dev);
1124 if (cancel_delayed_work_sync(&host->timeout_work))
1125 alcor_request_complete(host, 0);
1127 alcor_hw_uninit(host);
1132 static int alcor_pci_sdmmc_resume(struct device *dev)
1134 struct alcor_sdmmc_host *host = dev_get_drvdata(dev);
1136 alcor_hw_init(host);
1140 #endif /* CONFIG_PM_SLEEP */
1142 static SIMPLE_DEV_PM_OPS(alcor_mmc_pm_ops, alcor_pci_sdmmc_suspend,
1143 alcor_pci_sdmmc_resume);
1145 static const struct platform_device_id alcor_pci_sdmmc_ids[] = {
1147 .name = DRV_NAME_ALCOR_PCI_SDMMC,
1152 MODULE_DEVICE_TABLE(platform, alcor_pci_sdmmc_ids);
1154 static struct platform_driver alcor_pci_sdmmc_driver = {
1155 .probe = alcor_pci_sdmmc_drv_probe,
1156 .remove = alcor_pci_sdmmc_drv_remove,
1157 .id_table = alcor_pci_sdmmc_ids,
1159 .name = DRV_NAME_ALCOR_PCI_SDMMC,
1160 .pm = &alcor_mmc_pm_ops
1163 module_platform_driver(alcor_pci_sdmmc_driver);
1165 MODULE_AUTHOR("Oleksij Rempel <linux@rempel-privat.de>");
1166 MODULE_DESCRIPTION("PCI driver for Alcor Micro AU6601 Secure Digital Host Controller Interface");
1167 MODULE_LICENSE("GPL");