drivers/memory/omap-gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/ioport.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio/driver.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_device.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/omap-gpmc.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #include <linux/platform_data/mtd-nand-omap2.h>
  35
  36 #include <asm/mach-types.h>
  37
  38 #define DEVICE_NAME             "omap-gpmc"
  39
  40 /* GPMC register offsets */
  41 #define GPMC_REVISION           0x00
  42 #define GPMC_SYSCONFIG          0x10
  43 #define GPMC_SYSSTATUS          0x14
  44 #define GPMC_IRQSTATUS          0x18
  45 #define GPMC_IRQENABLE          0x1c
  46 #define GPMC_TIMEOUT_CONTROL    0x40
  47 #define GPMC_ERR_ADDRESS        0x44
  48 #define GPMC_ERR_TYPE           0x48
  49 #define GPMC_CONFIG             0x50
  50 #define GPMC_STATUS             0x54
  51 #define GPMC_PREFETCH_CONFIG1   0x1e0
  52 #define GPMC_PREFETCH_CONFIG2   0x1e4
  53 #define GPMC_PREFETCH_CONTROL   0x1ec
  54 #define GPMC_PREFETCH_STATUS    0x1f0
  55 #define GPMC_ECC_CONFIG         0x1f4
  56 #define GPMC_ECC_CONTROL        0x1f8
  57 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  58 #define GPMC_ECC1_RESULT        0x200
  59 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  60 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  61 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  66
  67 /* GPMC ECC control settings */
  68 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  69 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  70 #define GPMC_ECC_CTRL_ECCREG1           0x001
  71 #define GPMC_ECC_CTRL_ECCREG2           0x002
  72 #define GPMC_ECC_CTRL_ECCREG3           0x003
  73 #define GPMC_ECC_CTRL_ECCREG4           0x004
  74 #define GPMC_ECC_CTRL_ECCREG5           0x005
  75 #define GPMC_ECC_CTRL_ECCREG6           0x006
  76 #define GPMC_ECC_CTRL_ECCREG7           0x007
  77 #define GPMC_ECC_CTRL_ECCREG8           0x008
  78 #define GPMC_ECC_CTRL_ECCREG9           0x009
  79
  80 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  81
  82 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS      BIT(0)
  83
  84 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  85 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  86 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  87 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  88 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  89 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  90
  91 #define GPMC_CS0_OFFSET         0x60
  92 #define GPMC_CS_SIZE            0x30
  93 #define GPMC_BCH_SIZE           0x10
  94
  95 /*
  96  * The first 1MB of GPMC address space is typically mapped to
  97  * the internal ROM. Never allocate the first page, to
  98  * facilitate bug detection; even if we didn't boot from ROM.
  99  * As GPMC minimum partition size is 16MB we can only start from
 100  * there.
 101  */
 102 #define GPMC_MEM_START          0x1000000
 103 #define GPMC_MEM_END            0x3FFFFFFF
 104
 105 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 106 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 107
 108 #define CS_NUM_SHIFT            24
 109 #define ENABLE_PREFETCH         (0x1 << 7)
 110 #define DMA_MPU_MODE            2
 111
 112 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 113 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 114
 115 #define GPMC_HAS_WR_ACCESS              0x1
 116 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 117 #define GPMC_HAS_MUX_AAD                0x4
 118
 119 #define GPMC_NR_WAITPINS                4
 120
 121 #define GPMC_CS_CONFIG1         0x00
 122 #define GPMC_CS_CONFIG2         0x04
 123 #define GPMC_CS_CONFIG3         0x08
 124 #define GPMC_CS_CONFIG4         0x0c
 125 #define GPMC_CS_CONFIG5         0x10
 126 #define GPMC_CS_CONFIG6         0x14
 127 #define GPMC_CS_CONFIG7         0x18
 128 #define GPMC_CS_NAND_COMMAND    0x1c
 129 #define GPMC_CS_NAND_ADDRESS    0x20
 130 #define GPMC_CS_NAND_DATA       0x24
 131
 132 /* Control Commands */
 133 #define GPMC_CONFIG_RDY_BSY     0x00000001
 134 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 135 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 136
 137 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 138 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 139 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 140 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 141 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 142 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 143 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 144 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
 145 /** CLKACTIVATIONTIME Max Ticks */
 146 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 147 #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
 148 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 149 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 150 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 151 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 152 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
 153 /** WAITMONITORINGTIME Max Ticks */
 154 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 155 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
 156 #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
 157 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 158 /** DEVICESIZE Max Value */
 159 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 160 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 161 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 162 #define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 163 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 164 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 165 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 166 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 167 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 168 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 169
 170 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 171 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 172 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 173 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 174 /* All CONFIG7 bits except reserved bits */
 175 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 176                                          GPMC_CONFIG7_CSVALID_MASK |     \
 177                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 178
 179 #define GPMC_DEVICETYPE_NOR             0
 180 #define GPMC_DEVICETYPE_NAND            2
 181 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 182 #define WR_RD_PIN_MONITORING            0x00600000
 183
 184 /* ECC commands */
 185 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 186 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 187 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 188
 189 #define GPMC_NR_NAND_IRQS       2 /* number of NAND specific IRQs */
 190
 191 enum gpmc_clk_domain {
 192         GPMC_CD_FCLK,
 193         GPMC_CD_CLK
 194 };
 195
 196 struct gpmc_cs_data {
 197         const char *name;
 198
 199 #define GPMC_CS_RESERVED        (1 << 0)
 200         u32 flags;
 201
 202         struct resource mem;
 203 };
 204
 205 /* Structure to save gpmc cs context */
 206 struct gpmc_cs_config {
 207         u32 config1;
 208         u32 config2;
 209         u32 config3;
 210         u32 config4;
 211         u32 config5;
 212         u32 config6;
 213         u32 config7;
 214         int is_valid;
 215 };
 216
 217 /*
 218  * Structure to save/restore gpmc context
 219  * to support core off on OMAP3
 220  */
 221 struct omap3_gpmc_regs {
 222         u32 sysconfig;
 223         u32 irqenable;
 224         u32 timeout_ctrl;
 225         u32 config;
 226         u32 prefetch_config1;
 227         u32 prefetch_config2;
 228         u32 prefetch_control;
 229         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 230 };
 231
 232 struct gpmc_device {
 233         struct device *dev;
 234         int irq;
 235         struct irq_chip irq_chip;
 236         struct gpio_chip gpio_chip;
 237         int nirqs;
 238 };
 239
 240 static struct irq_domain *gpmc_irq_domain;
 241
 242 static struct resource  gpmc_mem_root;
 243 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 244 static DEFINE_SPINLOCK(gpmc_mem_lock);
 245 /* Define chip-selects as reserved by default until probe completes */
 246 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 247 static unsigned int gpmc_nr_waitpins;
 248 static resource_size_t phys_base, mem_size;
 249 static unsigned gpmc_capability;
 250 static void __iomem *gpmc_base;
 251
 252 static struct clk *gpmc_l3_clk;
 253
 254 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 255
 256 static void gpmc_write_reg(int idx, u32 val)
 257 {
 258         writel_relaxed(val, gpmc_base + idx);
 259 }
 260
 261 static u32 gpmc_read_reg(int idx)
 262 {
 263         return readl_relaxed(gpmc_base + idx);
 264 }
 265
 266 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 267 {
 268         void __iomem *reg_addr;
 269
 270         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 271         writel_relaxed(val, reg_addr);
 272 }
 273
 274 static u32 gpmc_cs_read_reg(int cs, int idx)
 275 {
 276         void __iomem *reg_addr;
 277
 278         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 279         return readl_relaxed(reg_addr);
 280 }
 281
 282 /* TODO: Add support for gpmc_fck to clock framework and use it */
 283 static unsigned long gpmc_get_fclk_period(void)
 284 {
 285         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 286
 287         rate /= 1000;
 288         rate = 1000000000 / rate;       /* In picoseconds */
 289
 290         return rate;
 291 }
 292
 293 /**
 294  * gpmc_get_clk_period - get period of selected clock domain in ps
 295  * @cs Chip Select Region.
 296  * @cd Clock Domain.
 297  *
 298  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 299  * prior to calling this function with GPMC_CD_CLK.
 300  */
 301 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 302 {
 303
 304         unsigned long tick_ps = gpmc_get_fclk_period();
 305         u32 l;
 306         int div;
 307
 308         switch (cd) {
 309         case GPMC_CD_CLK:
 310                 /* get current clk divider */
 311                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 312                 div = (l & 0x03) + 1;
 313                 /* get GPMC_CLK period */
 314                 tick_ps *= div;
 315                 break;
 316         case GPMC_CD_FCLK:
 317                 /* FALL-THROUGH */
 318         default:
 319                 break;
 320         }
 321
 322         return tick_ps;
 323
 324 }
 325
 326 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 327                                          enum gpmc_clk_domain cd)
 328 {
 329         unsigned long tick_ps;
 330
 331         /* Calculate in picosecs to yield more exact results */
 332         tick_ps = gpmc_get_clk_period(cs, cd);
 333
 334         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 335 }
 336
 337 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 338 {
 339         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 340 }
 341
 342 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 343 {
 344         unsigned long tick_ps;
 345
 346         /* Calculate in picosecs to yield more exact results */
 347         tick_ps = gpmc_get_fclk_period();
 348
 349         return (time_ps + tick_ps - 1) / tick_ps;
 350 }
 351
 352 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
 353                                          enum gpmc_clk_domain cd)
 354 {
 355         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 356 }
 357
 358 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 359 {
 360         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 361 }
 362
 363 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 364 {
 365         return ticks * gpmc_get_fclk_period();
 366 }
 367
 368 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 369 {
 370         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 371
 372         return ticks * gpmc_get_fclk_period();
 373 }
 374
 375 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 376 {
 377         u32 l;
 378
 379         l = gpmc_cs_read_reg(cs, reg);
 380         if (value)
 381                 l |= mask;
 382         else
 383                 l &= ~mask;
 384         gpmc_cs_write_reg(cs, reg, l);
 385 }
 386
 387 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 388 {
 389         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 390                            GPMC_CONFIG1_TIME_PARA_GRAN,
 391                            p->time_para_granularity);
 392         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 393                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 394         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 395                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 396         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 397                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 398         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 399                            GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
 400         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 401                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 402                            p->cycle2cyclesamecsen);
 403         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 404                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 405                            p->cycle2cyclediffcsen);
 406 }
 407
 408 #ifdef CONFIG_OMAP_GPMC_DEBUG
 409 /**
 410  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 411  * @cs:      Chip Select Region
 412  * @reg:     GPMC_CS_CONFIGn register offset.
 413  * @st_bit:  Start Bit
 414  * @end_bit: End Bit. Must be >= @st_bit.
 415  * @ma:x     Maximum parameter value (before optional @shift).
 416  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 417  * @name:    DTS node name, w/o "gpmc,"
 418  * @cd:      Clock Domain of timing parameter.
 419  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 420  * @raw:     Raw Format Option.
 421  *           raw format:  gpmc,name = <value>
 422  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 423  *           Where x ns -- y ns result in the same tick value.
 424  *           When @max is exceeded, "invalid" is printed inside comment.
 425  * @noval:   Parameter values equal to 0 are not printed.
 426  * @return:  Specified timing parameter (after optional @shift).
 427  *
 428  */
 429 static int get_gpmc_timing_reg(
 430         /* timing specifiers */
 431         int cs, int reg, int st_bit, int end_bit, int max,
 432         const char *name, const enum gpmc_clk_domain cd,
 433         /* value transform */
 434         int shift,
 435         /* format specifiers */
 436         bool raw, bool noval)
 437 {
 438         u32 l;
 439         int nr_bits;
 440         int mask;
 441         bool invalid;
 442
 443         l = gpmc_cs_read_reg(cs, reg);
 444         nr_bits = end_bit - st_bit + 1;
 445         mask = (1 << nr_bits) - 1;
 446         l = (l >> st_bit) & mask;
 447         if (!max)
 448                 max = mask;
 449         invalid = l > max;
 450         if (shift)
 451                 l = (shift << l);
 452         if (noval && (l == 0))
 453                 return 0;
 454         if (!raw) {
 455                 /* DTS tick format for timings in ns */
 456                 unsigned int time_ns;
 457                 unsigned int time_ns_min = 0;
 458
 459                 if (l)
 460                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 461                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 462                 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
 463                         name, time_ns, time_ns_min, time_ns, l,
 464                         invalid ? "; invalid " : " ");
 465         } else {
 466                 /* raw format */
 467                 pr_info("gpmc,%s = <%u>;%s\n", name, l,
 468                         invalid ? " /* invalid */" : "");
 469         }
 470
 471         return l;
 472 }
 473
 474 #define GPMC_PRINT_CONFIG(cs, config) \
 475         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 476                 gpmc_cs_read_reg(cs, config))
 477 #define GPMC_GET_RAW(reg, st, end, field) \
 478         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 479 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 480         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 481 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 482         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 483 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 484         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 485 #define GPMC_GET_TICKS(reg, st, end, field) \
 486         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 487 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 488         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 489 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 490         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 491
 492 static void gpmc_show_regs(int cs, const char *desc)
 493 {
 494         pr_info("gpmc cs%i %s:\n", cs, desc);
 495         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 496         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 497         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 498         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 499         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 500         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 501 }
 502
 503 /*
 504  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 505  * see commit c9fb809.
 506  */
 507 static void gpmc_cs_show_timings(int cs, const char *desc)
 508 {
 509         gpmc_show_regs(cs, desc);
 510
 511         pr_info("gpmc cs%i access configuration:\n", cs);
 512         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 513         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 514         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
 515                          GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 516         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 517         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 518         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 519         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 520                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 521                                "burst-length");
 522         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 523         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 524         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 525         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 526         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 527
 528         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 529
 530         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 531
 532         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 533         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 534
 535         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 536         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 537
 538         pr_info("gpmc cs%i timings configuration:\n", cs);
 539         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 540         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 541         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 542
 543         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 544         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 545         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 546         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 547                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 548                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 549                                 "adv-aad-mux-rd-off-ns");
 550                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 551                                 "adv-aad-mux-wr-off-ns");
 552         }
 553
 554         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 555         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 556         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 557                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 558                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 559         }
 560         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 561         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 562
 563         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 564         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 565         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 566
 567         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 568
 569         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 570         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 571
 572         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 573                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 574                               "wait-monitoring-ns", GPMC_CD_CLK);
 575         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 576                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 577                               "clk-activation-ns", GPMC_CD_FCLK);
 578
 579         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 580         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 581 }
 582 #else
 583 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 584 {
 585 }
 586 #endif
 587
 588 /**
 589  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 590  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 591  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 592  *
 593  * @cs:      Chip Select Region.
 594  * @reg:     GPMC_CS_CONFIGn register offset.
 595  * @st_bit:  Start Bit
 596  * @end_bit: End Bit. Must be >= @st_bit.
 597  * @max:     Maximum parameter value.
 598  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 599  * @time:    Timing parameter in ns.
 600  * @cd:      Timing parameter clock domain.
 601  * @name:    Timing parameter name.
 602  * @return:  0 on success, -1 on error.
 603  */
 604 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 605                                int time, enum gpmc_clk_domain cd, const char *name)
 606 {
 607         u32 l;
 608         int ticks, mask, nr_bits;
 609
 610         if (time == 0)
 611                 ticks = 0;
 612         else
 613                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 614         nr_bits = end_bit - st_bit + 1;
 615         mask = (1 << nr_bits) - 1;
 616
 617         if (!max)
 618                 max = mask;
 619
 620         if (ticks > max) {
 621                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 622                        __func__, cs, name, time, ticks, max);
 623
 624                 return -1;
 625         }
 626
 627         l = gpmc_cs_read_reg(cs, reg);
 628 #ifdef CONFIG_OMAP_GPMC_DEBUG
 629         pr_info(
 630                 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 631                cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 632                         (l >> st_bit) & mask, time);
 633 #endif
 634         l &= ~(mask << st_bit);
 635         l |= ticks << st_bit;
 636         gpmc_cs_write_reg(cs, reg, l);
 637
 638         return 0;
 639 }
 640
 641 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd)  \
 642         if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
 643             t->field, (cd), #field) < 0)                       \
 644                 return -1
 645
 646 #define GPMC_SET_ONE(reg, st, end, field) \
 647         GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
 648
 649 /**
 650  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 651  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 652  * read  --> don't sample bus too early
 653  * write --> data is longer on bus
 654  *
 655  * Formula:
 656  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 657  *                    / waitmonitoring_ticks)
 658  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 659  * div <= 0 check.
 660  *
 661  * @wait_monitoring: WAITMONITORINGTIME in ns.
 662  * @return:          -1 on failure to scale, else proper divider > 0.
 663  */
 664 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 665 {
 666
 667         int div = gpmc_ns_to_ticks(wait_monitoring);
 668
 669         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 670         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 671
 672         if (div > 4)
 673                 return -1;
 674         if (div <= 0)
 675                 div = 1;
 676
 677         return div;
 678
 679 }
 680
 681 /**
 682  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 683  * @sync_clk: GPMC_CLK period in ps.
 684  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 685  *            Else, returns -1.
 686  */
 687 int gpmc_calc_divider(unsigned int sync_clk)
 688 {
 689         int div = gpmc_ps_to_ticks(sync_clk);
 690
 691         if (div > 4)
 692                 return -1;
 693         if (div <= 0)
 694                 div = 1;
 695
 696         return div;
 697 }
 698
 699 /**
 700  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 701  * @cs:     Chip Select Region.
 702  * @t:      GPMC timing parameters.
 703  * @s:      GPMC timing settings.
 704  * @return: 0 on success, -1 on error.
 705  */
 706 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 707                         const struct gpmc_settings *s)
 708 {
 709         int div;
 710         u32 l;
 711
 712         div = gpmc_calc_divider(t->sync_clk);
 713         if (div < 0)
 714                 return div;
 715
 716         /*
 717          * See if we need to change the divider for waitmonitoringtime.
 718          *
 719          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 720          * pure asynchronous accesses, i.e. both read and write asynchronous.
 721          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 722          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 723          *
 724          * This statement must not change div to scale async WAITMONITORINGTIME
 725          * to protect mixed synchronous and asynchronous accesses.
 726          *
 727          * We raise an error later if WAITMONITORINGTIME does not fit.
 728          */
 729         if (!s->sync_read && !s->sync_write &&
 730             (s->wait_on_read || s->wait_on_write)
 731            ) {
 732
 733                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 734                 if (div < 0) {
 735                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 736                                __func__,
 737                                t->wait_monitoring
 738                                );
 739                         return -1;
 740                 }
 741         }
 742
 743         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 744         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 745         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 746
 747         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 748         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 749         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 750         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 751                 GPMC_SET_ONE(GPMC_CS_CONFIG3,  4,  6, adv_aad_mux_on);
 752                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
 753                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
 754         }
 755
 756         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 757         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 758         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 759                 GPMC_SET_ONE(GPMC_CS_CONFIG4,  4,  6, oe_aad_mux_on);
 760                 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
 761         }
 762         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 763         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 764
 765         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 766         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 767         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 768
 769         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 770
 771         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 772         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 773
 774         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 775                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 776         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 777                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 778
 779         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 780         l &= ~0x03;
 781         l |= (div - 1);
 782         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 783
 784         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 785                             GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 786                             wait_monitoring, GPMC_CD_CLK);
 787         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 788                             GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 789                             clk_activation, GPMC_CD_FCLK);
 790
 791 #ifdef CONFIG_OMAP_GPMC_DEBUG
 792         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 793                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 794 #endif
 795
 796         gpmc_cs_bool_timings(cs, &t->bool_timings);
 797         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 798
 799         return 0;
 800 }
 801
 802 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 803 {
 804         u32 l;
 805         u32 mask;
 806
 807         /*
 808          * Ensure that base address is aligned on a
 809          * boundary equal to or greater than size.
 810          */
 811         if (base & (size - 1))
 812                 return -EINVAL;
 813
 814         base >>= GPMC_CHUNK_SHIFT;
 815         mask = (1 << GPMC_SECTION_SHIFT) - size;
 816         mask >>= GPMC_CHUNK_SHIFT;
 817         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 818
 819         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 820         l &= ~GPMC_CONFIG7_MASK;
 821         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 822         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 823         l |= GPMC_CONFIG7_CSVALID;
 824         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 825
 826         return 0;
 827 }
 828
 829 static void gpmc_cs_enable_mem(int cs)
 830 {
 831         u32 l;
 832
 833         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 834         l |= GPMC_CONFIG7_CSVALID;
 835         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 836 }
 837
 838 static void gpmc_cs_disable_mem(int cs)
 839 {
 840         u32 l;
 841
 842         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 843         l &= ~GPMC_CONFIG7_CSVALID;
 844         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 845 }
 846
 847 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 848 {
 849         u32 l;
 850         u32 mask;
 851
 852         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 853         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 854         mask = (l >> 8) & 0x0f;
 855         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 856 }
 857
 858 static int gpmc_cs_mem_enabled(int cs)
 859 {
 860         u32 l;
 861
 862         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 863         return l & GPMC_CONFIG7_CSVALID;
 864 }
 865
 866 static void gpmc_cs_set_reserved(int cs, int reserved)
 867 {
 868         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 869
 870         gpmc->flags |= GPMC_CS_RESERVED;
 871 }
 872
 873 static bool gpmc_cs_reserved(int cs)
 874 {
 875         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 876
 877         return gpmc->flags & GPMC_CS_RESERVED;
 878 }
 879
 880 static void gpmc_cs_set_name(int cs, const char *name)
 881 {
 882         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 883
 884         gpmc->name = name;
 885 }
 886
 887 static const char *gpmc_cs_get_name(int cs)
 888 {
 889         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 890
 891         return gpmc->name;
 892 }
 893
 894 static unsigned long gpmc_mem_align(unsigned long size)
 895 {
 896         int order;
 897
 898         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 899         order = GPMC_CHUNK_SHIFT - 1;
 900         do {
 901                 size >>= 1;
 902                 order++;
 903         } while (size);
 904         size = 1 << order;
 905         return size;
 906 }
 907
 908 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 909 {
 910         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 911         struct resource *res = &gpmc->mem;
 912         int r;
 913
 914         size = gpmc_mem_align(size);
 915         spin_lock(&gpmc_mem_lock);
 916         res->start = base;
 917         res->end = base + size - 1;
 918         r = request_resource(&gpmc_mem_root, res);
 919         spin_unlock(&gpmc_mem_lock);
 920
 921         return r;
 922 }
 923
 924 static int gpmc_cs_delete_mem(int cs)
 925 {
 926         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 927         struct resource *res = &gpmc->mem;
 928         int r;
 929
 930         spin_lock(&gpmc_mem_lock);
 931         r = release_resource(res);
 932         res->start = 0;
 933         res->end = 0;
 934         spin_unlock(&gpmc_mem_lock);
 935
 936         return r;
 937 }
 938
 939 /**
 940  * gpmc_cs_remap - remaps a chip-select physical base address
 941  * @cs:         chip-select to remap
 942  * @base:       physical base address to re-map chip-select to
 943  *
 944  * Re-maps a chip-select to a new physical base address specified by
 945  * "base". Returns 0 on success and appropriate negative error code
 946  * on failure.
 947  */
 948 static int gpmc_cs_remap(int cs, u32 base)
 949 {
 950         int ret;
 951         u32 old_base, size;
 952
 953         if (cs > gpmc_cs_num) {
 954                 pr_err("%s: requested chip-select is disabled\n", __func__);
 955                 return -ENODEV;
 956         }
 957
 958         /*
 959          * Make sure we ignore any device offsets from the GPMC partition
 960          * allocated for the chip select and that the new base confirms
 961          * to the GPMC 16MB minimum granularity.
 962          */
 963         base &= ~(SZ_16M - 1);
 964
 965         gpmc_cs_get_memconf(cs, &old_base, &size);
 966         if (base == old_base)
 967                 return 0;
 968
 969         ret = gpmc_cs_delete_mem(cs);
 970         if (ret < 0)
 971                 return ret;
 972
 973         ret = gpmc_cs_insert_mem(cs, base, size);
 974         if (ret < 0)
 975                 return ret;
 976
 977         ret = gpmc_cs_set_memconf(cs, base, size);
 978
 979         return ret;
 980 }
 981
 982 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 983 {
 984         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 985         struct resource *res = &gpmc->mem;
 986         int r = -1;
 987
 988         if (cs > gpmc_cs_num) {
 989                 pr_err("%s: requested chip-select is disabled\n", __func__);
 990                 return -ENODEV;
 991         }
 992         size = gpmc_mem_align(size);
 993         if (size > (1 << GPMC_SECTION_SHIFT))
 994                 return -ENOMEM;
 995
 996         spin_lock(&gpmc_mem_lock);
 997         if (gpmc_cs_reserved(cs)) {
 998                 r = -EBUSY;
 999                 goto out;
1000         }
1001         if (gpmc_cs_mem_enabled(cs))
1002                 r = adjust_resource(res, res->start & ~(size - 1), size);
1003         if (r < 0)
1004                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1005                                       size, NULL, NULL);
1006         if (r < 0)
1007                 goto out;
1008
1009         /* Disable CS while changing base address and size mask */
1010         gpmc_cs_disable_mem(cs);
1011
1012         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1013         if (r < 0) {
1014                 release_resource(res);
1015                 goto out;
1016         }
1017
1018         /* Enable CS */
1019         gpmc_cs_enable_mem(cs);
1020         *base = res->start;
1021         gpmc_cs_set_reserved(cs, 1);
1022 out:
1023         spin_unlock(&gpmc_mem_lock);
1024         return r;
1025 }
1026 EXPORT_SYMBOL(gpmc_cs_request);
1027
1028 void gpmc_cs_free(int cs)
1029 {
1030         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1031         struct resource *res = &gpmc->mem;
1032
1033         spin_lock(&gpmc_mem_lock);
1034         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1035                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1036                 BUG();
1037                 spin_unlock(&gpmc_mem_lock);
1038                 return;
1039         }
1040         gpmc_cs_disable_mem(cs);
1041         if (res->flags)
1042                 release_resource(res);
1043         gpmc_cs_set_reserved(cs, 0);
1044         spin_unlock(&gpmc_mem_lock);
1045 }
1046 EXPORT_SYMBOL(gpmc_cs_free);
1047
1048 /**
1049  * gpmc_configure - write request to configure gpmc
1050  * @cmd: command type
1051  * @wval: value to write
1052  * @return status of the operation
1053  */
1054 int gpmc_configure(int cmd, int wval)
1055 {
1056         u32 regval;
1057
1058         switch (cmd) {
1059         case GPMC_CONFIG_WP:
1060                 regval = gpmc_read_reg(GPMC_CONFIG);
1061                 if (wval)
1062                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1063                 else
1064                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1065                 gpmc_write_reg(GPMC_CONFIG, regval);
1066                 break;
1067
1068         default:
1069                 pr_err("%s: command not supported\n", __func__);
1070                 return -EINVAL;
1071         }
1072
1073         return 0;
1074 }
1075 EXPORT_SYMBOL(gpmc_configure);
1076
1077 static bool gpmc_nand_writebuffer_empty(void)
1078 {
1079         if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1080                 return true;
1081
1082         return false;
1083 }
1084
1085 static struct gpmc_nand_ops nand_ops = {
1086         .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1087 };
1088
1089 /**
1090  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1091  * @regs: the GPMC NAND register map exclusive for NAND use.
1092  * @cs: GPMC chip select number on which the NAND sits. The
1093  *      register map returned will be specific to this chip select.
1094  *
1095  * Returns NULL on error e.g. invalid cs.
1096  */
1097 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1098 {
1099         int i;
1100
1101         if (cs >= gpmc_cs_num)
1102                 return NULL;
1103
1104         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1105                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1106         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1107                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1108         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1109                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1110         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1111         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1112         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1113         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1114         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1115         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1116         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1117         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1118
1119         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1120                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1121                                            GPMC_BCH_SIZE * i;
1122                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1123                                            GPMC_BCH_SIZE * i;
1124                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1125                                            GPMC_BCH_SIZE * i;
1126                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1127                                            GPMC_BCH_SIZE * i;
1128                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1129                                            i * GPMC_BCH_SIZE;
1130                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1131                                            i * GPMC_BCH_SIZE;
1132                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1133                                            i * GPMC_BCH_SIZE;
1134         }
1135
1136         return &nand_ops;
1137 }
1138 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1139
1140 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1141                                                 struct gpmc_settings *s,
1142                                                 int freq, int latency)
1143 {
1144         struct gpmc_device_timings dev_t;
1145         const int t_cer  = 15;
1146         const int t_avdp = 12;
1147         const int t_cez  = 20; /* max of t_cez, t_oez */
1148         const int t_wpl  = 40;
1149         const int t_wph  = 30;
1150         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1151
1152         switch (freq) {
1153         case 104:
1154                 min_gpmc_clk_period = 9600; /* 104 MHz */
1155                 t_ces   = 3;
1156                 t_avds  = 4;
1157                 t_avdh  = 2;
1158                 t_ach   = 3;
1159                 t_aavdh = 6;
1160                 t_rdyo  = 6;
1161                 break;
1162         case 83:
1163                 min_gpmc_clk_period = 12000; /* 83 MHz */
1164                 t_ces   = 5;
1165                 t_avds  = 4;
1166                 t_avdh  = 2;
1167                 t_ach   = 6;
1168                 t_aavdh = 6;
1169                 t_rdyo  = 9;
1170                 break;
1171         case 66:
1172                 min_gpmc_clk_period = 15000; /* 66 MHz */
1173                 t_ces   = 6;
1174                 t_avds  = 5;
1175                 t_avdh  = 2;
1176                 t_ach   = 6;
1177                 t_aavdh = 6;
1178                 t_rdyo  = 11;
1179                 break;
1180         default:
1181                 min_gpmc_clk_period = 18500; /* 54 MHz */
1182                 t_ces   = 7;
1183                 t_avds  = 7;
1184                 t_avdh  = 7;
1185                 t_ach   = 9;
1186                 t_aavdh = 7;
1187                 t_rdyo  = 15;
1188                 break;
1189         }
1190
1191         /* Set synchronous read timings */
1192         memset(&dev_t, 0, sizeof(dev_t));
1193
1194         if (!s->sync_write) {
1195                 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1196                 dev_t.t_wpl = t_wpl * 1000;
1197                 dev_t.t_wph = t_wph * 1000;
1198                 dev_t.t_aavdh = t_aavdh * 1000;
1199         }
1200         dev_t.ce_xdelay = true;
1201         dev_t.avd_xdelay = true;
1202         dev_t.oe_xdelay = true;
1203         dev_t.we_xdelay = true;
1204         dev_t.clk = min_gpmc_clk_period;
1205         dev_t.t_bacc = dev_t.clk;
1206         dev_t.t_ces = t_ces * 1000;
1207         dev_t.t_avds = t_avds * 1000;
1208         dev_t.t_avdh = t_avdh * 1000;
1209         dev_t.t_ach = t_ach * 1000;
1210         dev_t.cyc_iaa = (latency + 1);
1211         dev_t.t_cez_r = t_cez * 1000;
1212         dev_t.t_cez_w = dev_t.t_cez_r;
1213         dev_t.cyc_aavdh_oe = 1;
1214         dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1215
1216         gpmc_calc_timings(t, s, &dev_t);
1217 }
1218
1219 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1220                                   int latency,
1221                                   struct gpmc_onenand_info *info)
1222 {
1223         int ret;
1224         struct gpmc_timings gpmc_t;
1225         struct gpmc_settings gpmc_s;
1226
1227         gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1228
1229         info->sync_read = gpmc_s.sync_read;
1230         info->sync_write = gpmc_s.sync_write;
1231         info->burst_len = gpmc_s.burst_len;
1232
1233         if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1234                 return 0;
1235
1236         gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1237
1238         ret = gpmc_cs_program_settings(cs, &gpmc_s);
1239         if (ret < 0)
1240                 return ret;
1241
1242         return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1243 }
1244 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1245
1246 int gpmc_get_client_irq(unsigned irq_config)
1247 {
1248         if (!gpmc_irq_domain) {
1249                 pr_warn("%s called before GPMC IRQ domain available\n",
1250                         __func__);
1251                 return 0;
1252         }
1253
1254         /* we restrict this to NAND IRQs only */
1255         if (irq_config >= GPMC_NR_NAND_IRQS)
1256                 return 0;
1257
1258         return irq_create_mapping(gpmc_irq_domain, irq_config);
1259 }
1260
1261 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1262 {
1263         u32 regval;
1264
1265         /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1266         if (hwirq >= GPMC_NR_NAND_IRQS)
1267                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1268
1269         regval = gpmc_read_reg(GPMC_IRQENABLE);
1270         if (endis)
1271                 regval |= BIT(hwirq);
1272         else
1273                 regval &= ~BIT(hwirq);
1274         gpmc_write_reg(GPMC_IRQENABLE, regval);
1275
1276         return 0;
1277 }
1278
1279 static void gpmc_irq_disable(struct irq_data *p)
1280 {
1281         gpmc_irq_endis(p->hwirq, false);
1282 }
1283
1284 static void gpmc_irq_enable(struct irq_data *p)
1285 {
1286         gpmc_irq_endis(p->hwirq, true);
1287 }
1288
1289 static void gpmc_irq_mask(struct irq_data *d)
1290 {
1291         gpmc_irq_endis(d->hwirq, false);
1292 }
1293
1294 static void gpmc_irq_unmask(struct irq_data *d)
1295 {
1296         gpmc_irq_endis(d->hwirq, true);
1297 }
1298
1299 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1300 {
1301         u32 regval;
1302
1303         /* NAND IRQs polarity is not configurable */
1304         if (hwirq < GPMC_NR_NAND_IRQS)
1305                 return;
1306
1307         /* WAITPIN starts at BIT 8 */
1308         hwirq += 8 - GPMC_NR_NAND_IRQS;
1309
1310         regval = gpmc_read_reg(GPMC_CONFIG);
1311         if (rising_edge)
1312                 regval &= ~BIT(hwirq);
1313         else
1314                 regval |= BIT(hwirq);
1315
1316         gpmc_write_reg(GPMC_CONFIG, regval);
1317 }
1318
1319 static void gpmc_irq_ack(struct irq_data *d)
1320 {
1321         unsigned int hwirq = d->hwirq;
1322
1323         /* skip reserved bits */
1324         if (hwirq >= GPMC_NR_NAND_IRQS)
1325                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1326
1327         /* Setting bit to 1 clears (or Acks) the interrupt */
1328         gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1329 }
1330
1331 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1332 {
1333         /* can't set type for NAND IRQs */
1334         if (d->hwirq < GPMC_NR_NAND_IRQS)
1335                 return -EINVAL;
1336
1337         /* We can support either rising or falling edge at a time */
1338         if (trigger == IRQ_TYPE_EDGE_FALLING)
1339                 gpmc_irq_edge_config(d->hwirq, false);
1340         else if (trigger == IRQ_TYPE_EDGE_RISING)
1341                 gpmc_irq_edge_config(d->hwirq, true);
1342         else
1343                 return -EINVAL;
1344
1345         return 0;
1346 }
1347
1348 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1349                         irq_hw_number_t hw)
1350 {
1351         struct gpmc_device *gpmc = d->host_data;
1352
1353         irq_set_chip_data(virq, gpmc);
1354         if (hw < GPMC_NR_NAND_IRQS) {
1355                 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1356                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1357                                          handle_simple_irq);
1358         } else {
1359                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1360                                          handle_edge_irq);
1361         }
1362
1363         return 0;
1364 }
1365
1366 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1367         .map    = gpmc_irq_map,
1368         .xlate  = irq_domain_xlate_twocell,
1369 };
1370
1371 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1372 {
1373         int hwirq, virq;
1374         u32 regval, regvalx;
1375         struct gpmc_device *gpmc = data;
1376
1377         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1378         regvalx = regval;
1379
1380         if (!regval)
1381                 return IRQ_NONE;
1382
1383         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1384                 /* skip reserved status bits */
1385                 if (hwirq == GPMC_NR_NAND_IRQS)
1386                         regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1387
1388                 if (regvalx & BIT(hwirq)) {
1389                         virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1390                         if (!virq) {
1391                                 dev_warn(gpmc->dev,
1392                                          "spurious irq detected hwirq %d, virq %d\n",
1393                                          hwirq, virq);
1394                         }
1395
1396                         generic_handle_irq(virq);
1397                 }
1398         }
1399
1400         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1401
1402         return IRQ_HANDLED;
1403 }
1404
1405 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1406 {
1407         u32 regval;
1408         int rc;
1409
1410         /* Disable interrupts */
1411         gpmc_write_reg(GPMC_IRQENABLE, 0);
1412
1413         /* clear interrupts */
1414         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1415         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1416
1417         gpmc->irq_chip.name = "gpmc";
1418         gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1419         gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1420         gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1421         gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1422         gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1423         gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1424
1425         gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1426                                                 gpmc->nirqs,
1427                                                 &gpmc_irq_domain_ops,
1428                                                 gpmc);
1429         if (!gpmc_irq_domain) {
1430                 dev_err(gpmc->dev, "IRQ domain add failed\n");
1431                 return -ENODEV;
1432         }
1433
1434         rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1435         if (rc) {
1436                 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1437                         gpmc->irq, rc);
1438                 irq_domain_remove(gpmc_irq_domain);
1439                 gpmc_irq_domain = NULL;
1440         }
1441
1442         return rc;
1443 }
1444
1445 static int gpmc_free_irq(struct gpmc_device *gpmc)
1446 {
1447         int hwirq;
1448
1449         free_irq(gpmc->irq, gpmc);
1450
1451         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1452                 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1453
1454         irq_domain_remove(gpmc_irq_domain);
1455         gpmc_irq_domain = NULL;
1456
1457         return 0;
1458 }
1459
1460 static void gpmc_mem_exit(void)
1461 {
1462         int cs;
1463
1464         for (cs = 0; cs < gpmc_cs_num; cs++) {
1465                 if (!gpmc_cs_mem_enabled(cs))
1466                         continue;
1467                 gpmc_cs_delete_mem(cs);
1468         }
1469
1470 }
1471
1472 static void gpmc_mem_init(void)
1473 {
1474         int cs;
1475
1476         gpmc_mem_root.start = GPMC_MEM_START;
1477         gpmc_mem_root.end = GPMC_MEM_END;
1478
1479         /* Reserve all regions that has been set up by bootloader */
1480         for (cs = 0; cs < gpmc_cs_num; cs++) {
1481                 u32 base, size;
1482
1483                 if (!gpmc_cs_mem_enabled(cs))
1484                         continue;
1485                 gpmc_cs_get_memconf(cs, &base, &size);
1486                 if (gpmc_cs_insert_mem(cs, base, size)) {
1487                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1488                                 __func__, cs, base, base + size);
1489                         gpmc_cs_disable_mem(cs);
1490                 }
1491         }
1492 }
1493
1494 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1495 {
1496         u32 temp;
1497         int div;
1498
1499         div = gpmc_calc_divider(sync_clk);
1500         temp = gpmc_ps_to_ticks(time_ps);
1501         temp = (temp + div - 1) / div;
1502         return gpmc_ticks_to_ps(temp * div);
1503 }
1504
1505 /* XXX: can the cycles be avoided ? */
1506 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1507                                        struct gpmc_device_timings *dev_t,
1508                                        bool mux)
1509 {
1510         u32 temp;
1511
1512         /* adv_rd_off */
1513         temp = dev_t->t_avdp_r;
1514         /* XXX: mux check required ? */
1515         if (mux) {
1516                 /* XXX: t_avdp not to be required for sync, only added for tusb
1517                  * this indirectly necessitates requirement of t_avdp_r and
1518                  * t_avdp_w instead of having a single t_avdp
1519                  */
1520                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1521                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1522         }
1523         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1524
1525         /* oe_on */
1526         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1527         if (mux) {
1528                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1529                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1530                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1531         }
1532         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1533
1534         /* access */
1535         /* XXX: any scope for improvement ?, by combining oe_on
1536          * and clk_activation, need to check whether
1537          * access = clk_activation + round to sync clk ?
1538          */
1539         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1540         temp += gpmc_t->clk_activation;
1541         if (dev_t->cyc_oe)
1542                 temp = max_t(u32, temp, gpmc_t->oe_on +
1543                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1544         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1545
1546         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1547         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1548
1549         /* rd_cycle */
1550         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1551         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1552                                                         gpmc_t->access;
1553         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1554         if (dev_t->t_ce_rdyz)
1555                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1556         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1557
1558         return 0;
1559 }
1560
1561 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1562                                         struct gpmc_device_timings *dev_t,
1563                                         bool mux)
1564 {
1565         u32 temp;
1566
1567         /* adv_wr_off */
1568         temp = dev_t->t_avdp_w;
1569         if (mux) {
1570                 temp = max_t(u32, temp,
1571                         gpmc_t->clk_activation + dev_t->t_avdh);
1572                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1573         }
1574         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1575
1576         /* wr_data_mux_bus */
1577         temp = max_t(u32, dev_t->t_weasu,
1578                         gpmc_t->clk_activation + dev_t->t_rdyo);
1579         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1580          * and in that case remember to handle we_on properly
1581          */
1582         if (mux) {
1583                 temp = max_t(u32, temp,
1584                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1585                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1586                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1587         }
1588         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1589
1590         /* we_on */
1591         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1592                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1593         else
1594                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1595
1596         /* wr_access */
1597         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1598         gpmc_t->wr_access = gpmc_t->access;
1599
1600         /* we_off */
1601         temp = gpmc_t->we_on + dev_t->t_wpl;
1602         temp = max_t(u32, temp,
1603                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1604         temp = max_t(u32, temp,
1605                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1606         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1607
1608         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1609                                                         dev_t->t_wph);
1610
1611         /* wr_cycle */
1612         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1613         temp += gpmc_t->wr_access;
1614         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1615         if (dev_t->t_ce_rdyz)
1616                 temp = max_t(u32, temp,
1617                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1618         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1619
1620         return 0;
1621 }
1622
1623 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1624                                         struct gpmc_device_timings *dev_t,
1625                                         bool mux)
1626 {
1627         u32 temp;
1628
1629         /* adv_rd_off */
1630         temp = dev_t->t_avdp_r;
1631         if (mux)
1632                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1633         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1634
1635         /* oe_on */
1636         temp = dev_t->t_oeasu;
1637         if (mux)
1638                 temp = max_t(u32, temp,
1639                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
1640         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1641
1642         /* access */
1643         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1644                                 gpmc_t->oe_on + dev_t->t_oe);
1645         temp = max_t(u32, temp,
1646                                 gpmc_t->cs_on + dev_t->t_ce);
1647         temp = max_t(u32, temp,
1648                                 gpmc_t->adv_on + dev_t->t_aa);
1649         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1650
1651         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1652         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1653
1654         /* rd_cycle */
1655         temp = max_t(u32, dev_t->t_rd_cycle,
1656                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1657         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1658         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1659
1660         return 0;
1661 }
1662
1663 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1664                                          struct gpmc_device_timings *dev_t,
1665                                          bool mux)
1666 {
1667         u32 temp;
1668
1669         /* adv_wr_off */
1670         temp = dev_t->t_avdp_w;
1671         if (mux)
1672                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1673         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1674
1675         /* wr_data_mux_bus */
1676         temp = dev_t->t_weasu;
1677         if (mux) {
1678                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1679                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1680                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1681         }
1682         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1683
1684         /* we_on */
1685         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1686                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1687         else
1688                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1689
1690         /* we_off */
1691         temp = gpmc_t->we_on + dev_t->t_wpl;
1692         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1693
1694         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1695                                                         dev_t->t_wph);
1696
1697         /* wr_cycle */
1698         temp = max_t(u32, dev_t->t_wr_cycle,
1699                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1700         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1701
1702         return 0;
1703 }
1704
1705 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1706                         struct gpmc_device_timings *dev_t)
1707 {
1708         u32 temp;
1709
1710         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1711                                                 gpmc_get_fclk_period();
1712
1713         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1714                                         dev_t->t_bacc,
1715                                         gpmc_t->sync_clk);
1716
1717         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1718         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1719
1720         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1721                 return 0;
1722
1723         if (dev_t->ce_xdelay)
1724                 gpmc_t->bool_timings.cs_extra_delay = true;
1725         if (dev_t->avd_xdelay)
1726                 gpmc_t->bool_timings.adv_extra_delay = true;
1727         if (dev_t->oe_xdelay)
1728                 gpmc_t->bool_timings.oe_extra_delay = true;
1729         if (dev_t->we_xdelay)
1730                 gpmc_t->bool_timings.we_extra_delay = true;
1731
1732         return 0;
1733 }
1734
1735 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1736                                     struct gpmc_device_timings *dev_t,
1737                                     bool sync)
1738 {
1739         u32 temp;
1740
1741         /* cs_on */
1742         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1743
1744         /* adv_on */
1745         temp = dev_t->t_avdasu;
1746         if (dev_t->t_ce_avd)
1747                 temp = max_t(u32, temp,
1748                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1749         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1750
1751         if (sync)
1752                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1753
1754         return 0;
1755 }
1756
1757 /* TODO: remove this function once all peripherals are confirmed to
1758  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1759  * has to be modified to handle timings in ps instead of ns
1760 */
1761 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1762 {
1763         t->cs_on /= 1000;
1764         t->cs_rd_off /= 1000;
1765         t->cs_wr_off /= 1000;
1766         t->adv_on /= 1000;
1767         t->adv_rd_off /= 1000;
1768         t->adv_wr_off /= 1000;
1769         t->we_on /= 1000;
1770         t->we_off /= 1000;
1771         t->oe_on /= 1000;
1772         t->oe_off /= 1000;
1773         t->page_burst_access /= 1000;
1774         t->access /= 1000;
1775         t->rd_cycle /= 1000;
1776         t->wr_cycle /= 1000;
1777         t->bus_turnaround /= 1000;
1778         t->cycle2cycle_delay /= 1000;
1779         t->wait_monitoring /= 1000;
1780         t->clk_activation /= 1000;
1781         t->wr_access /= 1000;
1782         t->wr_data_mux_bus /= 1000;
1783 }
1784
1785 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1786                       struct gpmc_settings *gpmc_s,
1787                       struct gpmc_device_timings *dev_t)
1788 {
1789         bool mux = false, sync = false;
1790
1791         if (gpmc_s) {
1792                 mux = gpmc_s->mux_add_data ? true : false;
1793                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1794         }
1795
1796         memset(gpmc_t, 0, sizeof(*gpmc_t));
1797
1798         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1799
1800         if (gpmc_s && gpmc_s->sync_read)
1801                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1802         else
1803                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1804
1805         if (gpmc_s && gpmc_s->sync_write)
1806                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1807         else
1808                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1809
1810         /* TODO: remove, see function definition */
1811         gpmc_convert_ps_to_ns(gpmc_t);
1812
1813         return 0;
1814 }
1815
1816 /**
1817  * gpmc_cs_program_settings - programs non-timing related settings
1818  * @cs:         GPMC chip-select to program
1819  * @p:          pointer to GPMC settings structure
1820  *
1821  * Programs non-timing related settings for a GPMC chip-select, such as
1822  * bus-width, burst configuration, etc. Function should be called once
1823  * for each chip-select that is being used and must be called before
1824  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1825  * register will be initialised to zero by this function. Returns 0 on
1826  * success and appropriate negative error code on failure.
1827  */
1828 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1829 {
1830         u32 config1;
1831
1832         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1833                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1834                 return -EINVAL;
1835         }
1836
1837         /* Address-data multiplexing not supported for NAND devices */
1838         if (p->device_nand && p->mux_add_data) {
1839                 pr_err("%s: invalid configuration!\n", __func__);
1840                 return -EINVAL;
1841         }
1842
1843         if ((p->mux_add_data > GPMC_MUX_AD) ||
1844             ((p->mux_add_data == GPMC_MUX_AAD) &&
1845              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1846                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1847                 return -EINVAL;
1848         }
1849
1850         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1851         if (p->burst_read || p->burst_write) {
1852                 switch (p->burst_len) {
1853                 case GPMC_BURST_4:
1854                 case GPMC_BURST_8:
1855                 case GPMC_BURST_16:
1856                         break;
1857                 default:
1858                         pr_err("%s: invalid page/burst-length (%d)\n",
1859                                __func__, p->burst_len);
1860                         return -EINVAL;
1861                 }
1862         }
1863
1864         if (p->wait_pin > gpmc_nr_waitpins) {
1865                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1866                 return -EINVAL;
1867         }
1868
1869         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1870
1871         if (p->sync_read)
1872                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1873         if (p->sync_write)
1874                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1875         if (p->wait_on_read)
1876                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1877         if (p->wait_on_write)
1878                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1879         if (p->wait_on_read || p->wait_on_write)
1880                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1881         if (p->device_nand)
1882                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1883         if (p->mux_add_data)
1884                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1885         if (p->burst_read)
1886                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1887         if (p->burst_write)
1888                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1889         if (p->burst_read || p->burst_write) {
1890                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1891                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1892         }
1893
1894         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1895
1896         return 0;
1897 }
1898
1899 #ifdef CONFIG_OF
1900 static const struct of_device_id gpmc_dt_ids[] = {
1901         { .compatible = "ti,omap2420-gpmc" },
1902         { .compatible = "ti,omap2430-gpmc" },
1903         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1904         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1905         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1906         { }
1907 };
1908
1909 /**
1910  * gpmc_read_settings_dt - read gpmc settings from device-tree
1911  * @np:         pointer to device-tree node for a gpmc child device
1912  * @p:          pointer to gpmc settings structure
1913  *
1914  * Reads the GPMC settings for a GPMC child device from device-tree and
1915  * stores them in the GPMC settings structure passed. The GPMC settings
1916  * structure is initialised to zero by this function and so any
1917  * previously stored settings will be cleared.
1918  */
1919 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1920 {
1921         memset(p, 0, sizeof(struct gpmc_settings));
1922
1923         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1924         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1925         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1926         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1927
1928         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1929                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1930                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1931                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1932                 if (!p->burst_read && !p->burst_write)
1933                         pr_warn("%s: page/burst-length set but not used!\n",
1934                                 __func__);
1935         }
1936
1937         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1938                 p->wait_on_read = of_property_read_bool(np,
1939                                                         "gpmc,wait-on-read");
1940                 p->wait_on_write = of_property_read_bool(np,
1941                                                          "gpmc,wait-on-write");
1942                 if (!p->wait_on_read && !p->wait_on_write)
1943                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1944                                  __func__);
1945         }
1946 }
1947
1948 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1949                                                 struct gpmc_timings *gpmc_t)
1950 {
1951         struct gpmc_bool_timings *p;
1952
1953         if (!np || !gpmc_t)
1954                 return;
1955
1956         memset(gpmc_t, 0, sizeof(*gpmc_t));
1957
1958         /* minimum clock period for syncronous mode */
1959         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1960
1961         /* chip select timtings */
1962         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1963         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1964         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1965
1966         /* ADV signal timings */
1967         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1968         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1969         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1970         of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1971                              &gpmc_t->adv_aad_mux_on);
1972         of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1973                              &gpmc_t->adv_aad_mux_rd_off);
1974         of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1975                              &gpmc_t->adv_aad_mux_wr_off);
1976
1977         /* WE signal timings */
1978         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1979         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1980
1981         /* OE signal timings */
1982         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1983         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1984         of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1985                              &gpmc_t->oe_aad_mux_on);
1986         of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1987                              &gpmc_t->oe_aad_mux_off);
1988
1989         /* access and cycle timings */
1990         of_property_read_u32(np, "gpmc,page-burst-access-ns",
1991                              &gpmc_t->page_burst_access);
1992         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1993         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1994         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1995         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1996                              &gpmc_t->bus_turnaround);
1997         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1998                              &gpmc_t->cycle2cycle_delay);
1999         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
2000                              &gpmc_t->wait_monitoring);
2001         of_property_read_u32(np, "gpmc,clk-activation-ns",
2002                              &gpmc_t->clk_activation);
2003
2004         /* only applicable to OMAP3+ */
2005         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
2006         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
2007                              &gpmc_t->wr_data_mux_bus);
2008
2009         /* bool timing parameters */
2010         p = &gpmc_t->bool_timings;
2011
2012         p->cycle2cyclediffcsen =
2013                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2014         p->cycle2cyclesamecsen =
2015                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2016         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2017         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2018         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2019         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2020         p->time_para_granularity =
2021                 of_property_read_bool(np, "gpmc,time-para-granularity");
2022 }
2023
2024 /**
2025  * gpmc_probe_generic_child - configures the gpmc for a child device
2026  * @pdev:       pointer to gpmc platform device
2027  * @child:      pointer to device-tree node for child device
2028  *
2029  * Allocates and configures a GPMC chip-select for a child device.
2030  * Returns 0 on success and appropriate negative error code on failure.
2031  */
2032 static int gpmc_probe_generic_child(struct platform_device *pdev,
2033                                 struct device_node *child)
2034 {
2035         struct gpmc_settings gpmc_s;
2036         struct gpmc_timings gpmc_t;
2037         struct resource res;
2038         unsigned long base;
2039         const char *name;
2040         int ret, cs;
2041         u32 val;
2042         struct gpio_desc *waitpin_desc = NULL;
2043         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2044
2045         if (of_property_read_u32(child, "reg", &cs) < 0) {
2046                 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2047                         child);
2048                 return -ENODEV;
2049         }
2050
2051         if (of_address_to_resource(child, 0, &res) < 0) {
2052                 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2053                         child);
2054                 return -ENODEV;
2055         }
2056
2057         /*
2058          * Check if we have multiple instances of the same device
2059          * on a single chip select. If so, use the already initialized
2060          * timings.
2061          */
2062         name = gpmc_cs_get_name(cs);
2063         if (name && child->name && of_node_cmp(child->name, name) == 0)
2064                         goto no_timings;
2065
2066         ret = gpmc_cs_request(cs, resource_size(&res), &base);
2067         if (ret < 0) {
2068                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2069                 return ret;
2070         }
2071         gpmc_cs_set_name(cs, child->name);
2072
2073         gpmc_read_settings_dt(child, &gpmc_s);
2074         gpmc_read_timings_dt(child, &gpmc_t);
2075
2076         /*
2077          * For some GPMC devices we still need to rely on the bootloader
2078          * timings because the devices can be connected via FPGA.
2079          * REVISIT: Add timing support from slls644g.pdf.
2080          */
2081         if (!gpmc_t.cs_rd_off) {
2082                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2083                         cs);
2084                 gpmc_cs_show_timings(cs,
2085                                      "please add GPMC bootloader timings to .dts");
2086                 goto no_timings;
2087         }
2088
2089         /* CS must be disabled while making changes to gpmc configuration */
2090         gpmc_cs_disable_mem(cs);
2091
2092         /*
2093          * FIXME: gpmc_cs_request() will map the CS to an arbitary
2094          * location in the gpmc address space. When booting with
2095          * device-tree we want the NOR flash to be mapped to the
2096          * location specified in the device-tree blob. So remap the
2097          * CS to this location. Once DT migration is complete should
2098          * just make gpmc_cs_request() map a specific address.
2099          */
2100         ret = gpmc_cs_remap(cs, res.start);
2101         if (ret < 0) {
2102                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2103                         cs, &res.start);
2104                 if (res.start < GPMC_MEM_START) {
2105                         dev_info(&pdev->dev,
2106                                  "GPMC CS %d start cannot be lesser than 0x%x\n",
2107                                  cs, GPMC_MEM_START);
2108                 } else if (res.end > GPMC_MEM_END) {
2109                         dev_info(&pdev->dev,
2110                                  "GPMC CS %d end cannot be greater than 0x%x\n",
2111                                  cs, GPMC_MEM_END);
2112                 }
2113                 goto err;
2114         }
2115
2116         if (of_node_cmp(child->name, "nand") == 0) {
2117                 /* Warn about older DT blobs with no compatible property */
2118                 if (!of_property_read_bool(child, "compatible")) {
2119                         dev_warn(&pdev->dev,
2120                                  "Incompatible NAND node: missing compatible");
2121                         ret = -EINVAL;
2122                         goto err;
2123                 }
2124         }
2125
2126         if (of_node_cmp(child->name, "onenand") == 0) {
2127                 /* Warn about older DT blobs with no compatible property */
2128                 if (!of_property_read_bool(child, "compatible")) {
2129                         dev_warn(&pdev->dev,
2130                                  "Incompatible OneNAND node: missing compatible");
2131                         ret = -EINVAL;
2132                         goto err;
2133                 }
2134         }
2135
2136         if (of_device_is_compatible(child, "ti,omap2-nand")) {
2137                 /* NAND specific setup */
2138                 val = 8;
2139                 of_property_read_u32(child, "nand-bus-width", &val);
2140                 switch (val) {
2141                 case 8:
2142                         gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2143                         break;
2144                 case 16:
2145                         gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2146                         break;
2147                 default:
2148                         dev_err(&pdev->dev, "%s: invalid 'nand-bus-width'\n",
2149                                 child->name);
2150                         ret = -EINVAL;
2151                         goto err;
2152                 }
2153
2154                 /* disable write protect */
2155                 gpmc_configure(GPMC_CONFIG_WP, 0);
2156                 gpmc_s.device_nand = true;
2157         } else {
2158                 ret = of_property_read_u32(child, "bank-width",
2159                                            &gpmc_s.device_width);
2160                 if (ret < 0 && !gpmc_s.device_width) {
2161                         dev_err(&pdev->dev,
2162                                 "%pOF has no 'gpmc,device-width' property\n",
2163                                 child);
2164                         goto err;
2165                 }
2166         }
2167
2168         /* Reserve wait pin if it is required and valid */
2169         if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2170                 unsigned int wait_pin = gpmc_s.wait_pin;
2171
2172                 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2173                                                          wait_pin, "WAITPIN");
2174                 if (IS_ERR(waitpin_desc)) {
2175                         dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2176                         ret = PTR_ERR(waitpin_desc);
2177                         goto err;
2178                 }
2179         }
2180
2181         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2182
2183         ret = gpmc_cs_program_settings(cs, &gpmc_s);
2184         if (ret < 0)
2185                 goto err_cs;
2186
2187         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2188         if (ret) {
2189                 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2190                         child->name);
2191                 goto err_cs;
2192         }
2193
2194         /* Clear limited address i.e. enable A26-A11 */
2195         val = gpmc_read_reg(GPMC_CONFIG);
2196         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2197         gpmc_write_reg(GPMC_CONFIG, val);
2198
2199         /* Enable CS region */
2200         gpmc_cs_enable_mem(cs);
2201
2202 no_timings:
2203
2204         /* create platform device, NULL on error or when disabled */
2205         if (!of_platform_device_create(child, NULL, &pdev->dev))
2206                 goto err_child_fail;
2207
2208         /* is child a common bus? */
2209         if (of_match_node(of_default_bus_match_table, child))
2210                 /* create children and other common bus children */
2211                 if (of_platform_default_populate(child, NULL, &pdev->dev))
2212                         goto err_child_fail;
2213
2214         return 0;
2215
2216 err_child_fail:
2217
2218         dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2219         ret = -ENODEV;
2220
2221 err_cs:
2222         gpiochip_free_own_desc(waitpin_desc);
2223 err:
2224         gpmc_cs_free(cs);
2225
2226         return ret;
2227 }
2228
2229 static int gpmc_probe_dt(struct platform_device *pdev)
2230 {
2231         int ret;
2232         const struct of_device_id *of_id =
2233                 of_match_device(gpmc_dt_ids, &pdev->dev);
2234
2235         if (!of_id)
2236                 return 0;
2237
2238         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2239                                    &gpmc_cs_num);
2240         if (ret < 0) {
2241                 pr_err("%s: number of chip-selects not defined\n", __func__);
2242                 return ret;
2243         } else if (gpmc_cs_num < 1) {
2244                 pr_err("%s: all chip-selects are disabled\n", __func__);
2245                 return -EINVAL;
2246         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2247                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2248                                          __func__, GPMC_CS_NUM);
2249                 return -EINVAL;
2250         }
2251
2252         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2253                                    &gpmc_nr_waitpins);
2254         if (ret < 0) {
2255                 pr_err("%s: number of wait pins not found!\n", __func__);
2256                 return ret;
2257         }
2258
2259         return 0;
2260 }
2261
2262 static void gpmc_probe_dt_children(struct platform_device *pdev)
2263 {
2264         int ret;
2265         struct device_node *child;
2266
2267         for_each_available_child_of_node(pdev->dev.of_node, child) {
2268
2269                 if (!child->name)
2270                         continue;
2271
2272                 ret = gpmc_probe_generic_child(pdev, child);
2273                 if (ret) {
2274                         dev_err(&pdev->dev, "failed to probe DT child '%s': %d\n",
2275                                 child->name, ret);
2276                 }
2277         }
2278 }
2279 #else
2280 static int gpmc_probe_dt(struct platform_device *pdev)
2281 {
2282         return 0;
2283 }
2284
2285 static void gpmc_probe_dt_children(struct platform_device *pdev)
2286 {
2287 }
2288 #endif /* CONFIG_OF */
2289
2290 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2291 {
2292         return 1;       /* we're input only */
2293 }
2294
2295 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2296                                      unsigned int offset)
2297 {
2298         return 0;       /* we're input only */
2299 }
2300
2301 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2302                                       unsigned int offset, int value)
2303 {
2304         return -EINVAL; /* we're input only */
2305 }
2306
2307 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2308                           int value)
2309 {
2310 }
2311
2312 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2313 {
2314         u32 reg;
2315
2316         offset += 8;
2317
2318         reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2319
2320         return !!reg;
2321 }
2322
2323 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2324 {
2325         int ret;
2326
2327         gpmc->gpio_chip.parent = gpmc->dev;
2328         gpmc->gpio_chip.owner = THIS_MODULE;
2329         gpmc->gpio_chip.label = DEVICE_NAME;
2330         gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2331         gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2332         gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2333         gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2334         gpmc->gpio_chip.set = gpmc_gpio_set;
2335         gpmc->gpio_chip.get = gpmc_gpio_get;
2336         gpmc->gpio_chip.base = -1;
2337
2338         ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2339         if (ret < 0) {
2340                 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2341                 return ret;
2342         }
2343
2344         return 0;
2345 }
2346
2347 static int gpmc_probe(struct platform_device *pdev)
2348 {
2349         int rc;
2350         u32 l;
2351         struct resource *res;
2352         struct gpmc_device *gpmc;
2353
2354         gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2355         if (!gpmc)
2356                 return -ENOMEM;
2357
2358         gpmc->dev = &pdev->dev;
2359         platform_set_drvdata(pdev, gpmc);
2360
2361         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2362         if (res == NULL)
2363                 return -ENOENT;
2364
2365         phys_base = res->start;
2366         mem_size = resource_size(res);
2367
2368         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2369         if (IS_ERR(gpmc_base))
2370                 return PTR_ERR(gpmc_base);
2371
2372         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2373         if (!res) {
2374                 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2375                 return -ENOENT;
2376         }
2377
2378         gpmc->irq = res->start;
2379
2380         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2381         if (IS_ERR(gpmc_l3_clk)) {
2382                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2383                 return PTR_ERR(gpmc_l3_clk);
2384         }
2385
2386         if (!clk_get_rate(gpmc_l3_clk)) {
2387                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2388                 return -EINVAL;
2389         }
2390
2391         if (pdev->dev.of_node) {
2392                 rc = gpmc_probe_dt(pdev);
2393                 if (rc)
2394                         return rc;
2395         } else {
2396                 gpmc_cs_num = GPMC_CS_NUM;
2397                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2398         }
2399
2400         pm_runtime_enable(&pdev->dev);
2401         pm_runtime_get_sync(&pdev->dev);
2402
2403         l = gpmc_read_reg(GPMC_REVISION);
2404
2405         /*
2406          * FIXME: Once device-tree migration is complete the below flags
2407          * should be populated based upon the device-tree compatible
2408          * string. For now just use the IP revision. OMAP3+ devices have
2409          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2410          * devices support the addr-addr-data multiplex protocol.
2411          *
2412          * GPMC IP revisions:
2413          * - OMAP24xx                   = 2.0
2414          * - OMAP3xxx                   = 5.0
2415          * - OMAP44xx/54xx/AM335x       = 6.0
2416          */
2417         if (GPMC_REVISION_MAJOR(l) > 0x4)
2418                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2419         if (GPMC_REVISION_MAJOR(l) > 0x5)
2420                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2421         dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2422                  GPMC_REVISION_MINOR(l));
2423
2424         gpmc_mem_init();
2425         rc = gpmc_gpio_init(gpmc);
2426         if (rc)
2427                 goto gpio_init_failed;
2428
2429         gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2430         rc = gpmc_setup_irq(gpmc);
2431         if (rc) {
2432                 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2433                 goto gpio_init_failed;
2434         }
2435
2436         gpmc_probe_dt_children(pdev);
2437
2438         return 0;
2439
2440 gpio_init_failed:
2441         gpmc_mem_exit();
2442         pm_runtime_put_sync(&pdev->dev);
2443         pm_runtime_disable(&pdev->dev);
2444
2445         return rc;
2446 }
2447
2448 static int gpmc_remove(struct platform_device *pdev)
2449 {
2450         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2451
2452         gpmc_free_irq(gpmc);
2453         gpmc_mem_exit();
2454         pm_runtime_put_sync(&pdev->dev);
2455         pm_runtime_disable(&pdev->dev);
2456
2457         return 0;
2458 }
2459
2460 #ifdef CONFIG_PM_SLEEP
2461 static int gpmc_suspend(struct device *dev)
2462 {
2463         omap3_gpmc_save_context();
2464         pm_runtime_put_sync(dev);
2465         return 0;
2466 }
2467
2468 static int gpmc_resume(struct device *dev)
2469 {
2470         pm_runtime_get_sync(dev);
2471         omap3_gpmc_restore_context();
2472         return 0;
2473 }
2474 #endif
2475
2476 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2477
2478 static struct platform_driver gpmc_driver = {
2479         .probe          = gpmc_probe,
2480         .remove         = gpmc_remove,
2481         .driver         = {
2482                 .name   = DEVICE_NAME,
2483                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2484                 .pm     = &gpmc_pm_ops,
2485         },
2486 };
2487
2488 static __init int gpmc_init(void)
2489 {
2490         return platform_driver_register(&gpmc_driver);
2491 }
2492 postcore_initcall(gpmc_init);
2493
2494 static struct omap3_gpmc_regs gpmc_context;
2495
2496 void omap3_gpmc_save_context(void)
2497 {
2498         int i;
2499
2500         if (!gpmc_base)
2501                 return;
2502
2503         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2504         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2505         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2506         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2507         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2508         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2509         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2510         for (i = 0; i < gpmc_cs_num; i++) {
2511                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2512                 if (gpmc_context.cs_context[i].is_valid) {
2513                         gpmc_context.cs_context[i].config1 =
2514                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2515                         gpmc_context.cs_context[i].config2 =
2516                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2517                         gpmc_context.cs_context[i].config3 =
2518                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2519                         gpmc_context.cs_context[i].config4 =
2520                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2521                         gpmc_context.cs_context[i].config5 =
2522                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2523                         gpmc_context.cs_context[i].config6 =
2524                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2525                         gpmc_context.cs_context[i].config7 =
2526                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2527                 }
2528         }
2529 }
2530
2531 void omap3_gpmc_restore_context(void)
2532 {
2533         int i;
2534
2535         if (!gpmc_base)
2536                 return;
2537
2538         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2539         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2540         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2541         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2542         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2543         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2544         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2545         for (i = 0; i < gpmc_cs_num; i++) {
2546                 if (gpmc_context.cs_context[i].is_valid) {
2547                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2548                                 gpmc_context.cs_context[i].config1);
2549                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2550                                 gpmc_context.cs_context[i].config2);
2551                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2552                                 gpmc_context.cs_context[i].config3);
2553                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2554                                 gpmc_context.cs_context[i].config4);
2555                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2556                                 gpmc_context.cs_context[i].config5);
2557                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2558                                 gpmc_context.cs_context[i].config6);
2559                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2560                                 gpmc_context.cs_context[i].config7);
2561                 }
2562         }
2563 }