drivers/memory/omap-gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/ioport.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio/driver.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_device.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/omap-gpmc.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #include <linux/platform_data/mtd-nand-omap2.h>
  35 #include <linux/platform_data/mtd-onenand-omap2.h>
  36
  37 #include <asm/mach-types.h>
  38
  39 #define DEVICE_NAME             "omap-gpmc"
  40
  41 /* GPMC register offsets */
  42 #define GPMC_REVISION           0x00
  43 #define GPMC_SYSCONFIG          0x10
  44 #define GPMC_SYSSTATUS          0x14
  45 #define GPMC_IRQSTATUS          0x18
  46 #define GPMC_IRQENABLE          0x1c
  47 #define GPMC_TIMEOUT_CONTROL    0x40
  48 #define GPMC_ERR_ADDRESS        0x44
  49 #define GPMC_ERR_TYPE           0x48
  50 #define GPMC_CONFIG             0x50
  51 #define GPMC_STATUS             0x54
  52 #define GPMC_PREFETCH_CONFIG1   0x1e0
  53 #define GPMC_PREFETCH_CONFIG2   0x1e4
  54 #define GPMC_PREFETCH_CONTROL   0x1ec
  55 #define GPMC_PREFETCH_STATUS    0x1f0
  56 #define GPMC_ECC_CONFIG         0x1f4
  57 #define GPMC_ECC_CONTROL        0x1f8
  58 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  59 #define GPMC_ECC1_RESULT        0x200
  60 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  61 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  66 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  67
  68 /* GPMC ECC control settings */
  69 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  70 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  71 #define GPMC_ECC_CTRL_ECCREG1           0x001
  72 #define GPMC_ECC_CTRL_ECCREG2           0x002
  73 #define GPMC_ECC_CTRL_ECCREG3           0x003
  74 #define GPMC_ECC_CTRL_ECCREG4           0x004
  75 #define GPMC_ECC_CTRL_ECCREG5           0x005
  76 #define GPMC_ECC_CTRL_ECCREG6           0x006
  77 #define GPMC_ECC_CTRL_ECCREG7           0x007
  78 #define GPMC_ECC_CTRL_ECCREG8           0x008
  79 #define GPMC_ECC_CTRL_ECCREG9           0x009
  80
  81 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  82
  83 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS      BIT(0)
  84
  85 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  86 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  87 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  88 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  89 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  90 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  91
  92 #define GPMC_CS0_OFFSET         0x60
  93 #define GPMC_CS_SIZE            0x30
  94 #define GPMC_BCH_SIZE           0x10
  95
  96 /*
  97  * The first 1MB of GPMC address space is typically mapped to
  98  * the internal ROM. Never allocate the first page, to
  99  * facilitate bug detection; even if we didn't boot from ROM.
 100  * As GPMC minimum partition size is 16MB we can only start from
 101  * there.
 102  */
 103 #define GPMC_MEM_START          0x1000000
 104 #define GPMC_MEM_END            0x3FFFFFFF
 105
 106 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 107 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 108
 109 #define CS_NUM_SHIFT            24
 110 #define ENABLE_PREFETCH         (0x1 << 7)
 111 #define DMA_MPU_MODE            2
 112
 113 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 114 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 115
 116 #define GPMC_HAS_WR_ACCESS              0x1
 117 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 118 #define GPMC_HAS_MUX_AAD                0x4
 119
 120 #define GPMC_NR_WAITPINS                4
 121
 122 #define GPMC_CS_CONFIG1         0x00
 123 #define GPMC_CS_CONFIG2         0x04
 124 #define GPMC_CS_CONFIG3         0x08
 125 #define GPMC_CS_CONFIG4         0x0c
 126 #define GPMC_CS_CONFIG5         0x10
 127 #define GPMC_CS_CONFIG6         0x14
 128 #define GPMC_CS_CONFIG7         0x18
 129 #define GPMC_CS_NAND_COMMAND    0x1c
 130 #define GPMC_CS_NAND_ADDRESS    0x20
 131 #define GPMC_CS_NAND_DATA       0x24
 132
 133 /* Control Commands */
 134 #define GPMC_CONFIG_RDY_BSY     0x00000001
 135 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 136 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 137
 138 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 139 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 140 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 141 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 142 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 143 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 144 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 145 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
 146 /** CLKACTIVATIONTIME Max Ticks */
 147 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 148 #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
 149 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 150 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 151 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 152 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 153 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
 154 /** WAITMONITORINGTIME Max Ticks */
 155 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 156 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
 157 #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
 158 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 159 /** DEVICESIZE Max Value */
 160 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 161 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 162 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 163 #define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 164 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 165 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 166 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 167 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 168 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 169 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 170
 171 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 172 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 173 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 174 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 175 /* All CONFIG7 bits except reserved bits */
 176 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 177                                          GPMC_CONFIG7_CSVALID_MASK |     \
 178                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 179
 180 #define GPMC_DEVICETYPE_NOR             0
 181 #define GPMC_DEVICETYPE_NAND            2
 182 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 183 #define WR_RD_PIN_MONITORING            0x00600000
 184
 185 /* ECC commands */
 186 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 187 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 188 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 189
 190 #define GPMC_NR_NAND_IRQS       2 /* number of NAND specific IRQs */
 191
 192 enum gpmc_clk_domain {
 193         GPMC_CD_FCLK,
 194         GPMC_CD_CLK
 195 };
 196
 197 struct gpmc_cs_data {
 198         const char *name;
 199
 200 #define GPMC_CS_RESERVED        (1 << 0)
 201         u32 flags;
 202
 203         struct resource mem;
 204 };
 205
 206 /* Structure to save gpmc cs context */
 207 struct gpmc_cs_config {
 208         u32 config1;
 209         u32 config2;
 210         u32 config3;
 211         u32 config4;
 212         u32 config5;
 213         u32 config6;
 214         u32 config7;
 215         int is_valid;
 216 };
 217
 218 /*
 219  * Structure to save/restore gpmc context
 220  * to support core off on OMAP3
 221  */
 222 struct omap3_gpmc_regs {
 223         u32 sysconfig;
 224         u32 irqenable;
 225         u32 timeout_ctrl;
 226         u32 config;
 227         u32 prefetch_config1;
 228         u32 prefetch_config2;
 229         u32 prefetch_control;
 230         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 231 };
 232
 233 struct gpmc_device {
 234         struct device *dev;
 235         int irq;
 236         struct irq_chip irq_chip;
 237         struct gpio_chip gpio_chip;
 238         int nirqs;
 239 };
 240
 241 static struct irq_domain *gpmc_irq_domain;
 242
 243 static struct resource  gpmc_mem_root;
 244 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 245 static DEFINE_SPINLOCK(gpmc_mem_lock);
 246 /* Define chip-selects as reserved by default until probe completes */
 247 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 248 static unsigned int gpmc_nr_waitpins;
 249 static resource_size_t phys_base, mem_size;
 250 static unsigned gpmc_capability;
 251 static void __iomem *gpmc_base;
 252
 253 static struct clk *gpmc_l3_clk;
 254
 255 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 256
 257 static void gpmc_write_reg(int idx, u32 val)
 258 {
 259         writel_relaxed(val, gpmc_base + idx);
 260 }
 261
 262 static u32 gpmc_read_reg(int idx)
 263 {
 264         return readl_relaxed(gpmc_base + idx);
 265 }
 266
 267 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 268 {
 269         void __iomem *reg_addr;
 270
 271         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 272         writel_relaxed(val, reg_addr);
 273 }
 274
 275 static u32 gpmc_cs_read_reg(int cs, int idx)
 276 {
 277         void __iomem *reg_addr;
 278
 279         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 280         return readl_relaxed(reg_addr);
 281 }
 282
 283 /* TODO: Add support for gpmc_fck to clock framework and use it */
 284 static unsigned long gpmc_get_fclk_period(void)
 285 {
 286         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 287
 288         rate /= 1000;
 289         rate = 1000000000 / rate;       /* In picoseconds */
 290
 291         return rate;
 292 }
 293
 294 /**
 295  * gpmc_get_clk_period - get period of selected clock domain in ps
 296  * @cs Chip Select Region.
 297  * @cd Clock Domain.
 298  *
 299  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 300  * prior to calling this function with GPMC_CD_CLK.
 301  */
 302 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 303 {
 304
 305         unsigned long tick_ps = gpmc_get_fclk_period();
 306         u32 l;
 307         int div;
 308
 309         switch (cd) {
 310         case GPMC_CD_CLK:
 311                 /* get current clk divider */
 312                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 313                 div = (l & 0x03) + 1;
 314                 /* get GPMC_CLK period */
 315                 tick_ps *= div;
 316                 break;
 317         case GPMC_CD_FCLK:
 318                 /* FALL-THROUGH */
 319         default:
 320                 break;
 321         }
 322
 323         return tick_ps;
 324
 325 }
 326
 327 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 328                                          enum gpmc_clk_domain cd)
 329 {
 330         unsigned long tick_ps;
 331
 332         /* Calculate in picosecs to yield more exact results */
 333         tick_ps = gpmc_get_clk_period(cs, cd);
 334
 335         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 336 }
 337
 338 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 339 {
 340         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 341 }
 342
 343 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 344 {
 345         unsigned long tick_ps;
 346
 347         /* Calculate in picosecs to yield more exact results */
 348         tick_ps = gpmc_get_fclk_period();
 349
 350         return (time_ps + tick_ps - 1) / tick_ps;
 351 }
 352
 353 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
 354                                          enum gpmc_clk_domain cd)
 355 {
 356         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 357 }
 358
 359 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 360 {
 361         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 362 }
 363
 364 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 365 {
 366         return ticks * gpmc_get_fclk_period();
 367 }
 368
 369 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 370 {
 371         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 372
 373         return ticks * gpmc_get_fclk_period();
 374 }
 375
 376 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 377 {
 378         u32 l;
 379
 380         l = gpmc_cs_read_reg(cs, reg);
 381         if (value)
 382                 l |= mask;
 383         else
 384                 l &= ~mask;
 385         gpmc_cs_write_reg(cs, reg, l);
 386 }
 387
 388 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 389 {
 390         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 391                            GPMC_CONFIG1_TIME_PARA_GRAN,
 392                            p->time_para_granularity);
 393         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 394                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 395         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 396                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 397         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 398                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 399         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 400                            GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
 401         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 402                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 403                            p->cycle2cyclesamecsen);
 404         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 405                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 406                            p->cycle2cyclediffcsen);
 407 }
 408
 409 #ifdef CONFIG_OMAP_GPMC_DEBUG
 410 /**
 411  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 412  * @cs:      Chip Select Region
 413  * @reg:     GPMC_CS_CONFIGn register offset.
 414  * @st_bit:  Start Bit
 415  * @end_bit: End Bit. Must be >= @st_bit.
 416  * @ma:x     Maximum parameter value (before optional @shift).
 417  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 418  * @name:    DTS node name, w/o "gpmc,"
 419  * @cd:      Clock Domain of timing parameter.
 420  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 421  * @raw:     Raw Format Option.
 422  *           raw format:  gpmc,name = <value>
 423  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 424  *           Where x ns -- y ns result in the same tick value.
 425  *           When @max is exceeded, "invalid" is printed inside comment.
 426  * @noval:   Parameter values equal to 0 are not printed.
 427  * @return:  Specified timing parameter (after optional @shift).
 428  *
 429  */
 430 static int get_gpmc_timing_reg(
 431         /* timing specifiers */
 432         int cs, int reg, int st_bit, int end_bit, int max,
 433         const char *name, const enum gpmc_clk_domain cd,
 434         /* value transform */
 435         int shift,
 436         /* format specifiers */
 437         bool raw, bool noval)
 438 {
 439         u32 l;
 440         int nr_bits;
 441         int mask;
 442         bool invalid;
 443
 444         l = gpmc_cs_read_reg(cs, reg);
 445         nr_bits = end_bit - st_bit + 1;
 446         mask = (1 << nr_bits) - 1;
 447         l = (l >> st_bit) & mask;
 448         if (!max)
 449                 max = mask;
 450         invalid = l > max;
 451         if (shift)
 452                 l = (shift << l);
 453         if (noval && (l == 0))
 454                 return 0;
 455         if (!raw) {
 456                 /* DTS tick format for timings in ns */
 457                 unsigned int time_ns;
 458                 unsigned int time_ns_min = 0;
 459
 460                 if (l)
 461                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 462                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 463                 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
 464                         name, time_ns, time_ns_min, time_ns, l,
 465                         invalid ? "; invalid " : " ");
 466         } else {
 467                 /* raw format */
 468                 pr_info("gpmc,%s = <%u>;%s\n", name, l,
 469                         invalid ? " /* invalid */" : "");
 470         }
 471
 472         return l;
 473 }
 474
 475 #define GPMC_PRINT_CONFIG(cs, config) \
 476         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 477                 gpmc_cs_read_reg(cs, config))
 478 #define GPMC_GET_RAW(reg, st, end, field) \
 479         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 480 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 481         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 482 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 483         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 484 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 485         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 486 #define GPMC_GET_TICKS(reg, st, end, field) \
 487         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 488 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 489         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 490 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 491         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 492
 493 static void gpmc_show_regs(int cs, const char *desc)
 494 {
 495         pr_info("gpmc cs%i %s:\n", cs, desc);
 496         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 497         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 498         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 499         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 500         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 501         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 502 }
 503
 504 /*
 505  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 506  * see commit c9fb809.
 507  */
 508 static void gpmc_cs_show_timings(int cs, const char *desc)
 509 {
 510         gpmc_show_regs(cs, desc);
 511
 512         pr_info("gpmc cs%i access configuration:\n", cs);
 513         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 514         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 515         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
 516                          GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 517         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 518         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 519         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 520         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 521                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 522                                "burst-length");
 523         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 524         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 525         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 526         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 527         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 528
 529         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 530
 531         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 532
 533         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 534         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 535
 536         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 537         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 538
 539         pr_info("gpmc cs%i timings configuration:\n", cs);
 540         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 541         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 542         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 543
 544         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 545         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 546         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 547         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 548                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 549                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 550                                 "adv-aad-mux-rd-off-ns");
 551                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 552                                 "adv-aad-mux-wr-off-ns");
 553         }
 554
 555         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 556         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 557         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 558                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 559                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 560         }
 561         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 562         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 563
 564         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 565         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 566         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 567
 568         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 569
 570         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 571         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 572
 573         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 574                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 575                               "wait-monitoring-ns", GPMC_CD_CLK);
 576         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 577                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 578                               "clk-activation-ns", GPMC_CD_FCLK);
 579
 580         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 581         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 582 }
 583 #else
 584 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 585 {
 586 }
 587 #endif
 588
 589 /**
 590  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 591  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 592  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 593  *
 594  * @cs:      Chip Select Region.
 595  * @reg:     GPMC_CS_CONFIGn register offset.
 596  * @st_bit:  Start Bit
 597  * @end_bit: End Bit. Must be >= @st_bit.
 598  * @max:     Maximum parameter value.
 599  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 600  * @time:    Timing parameter in ns.
 601  * @cd:      Timing parameter clock domain.
 602  * @name:    Timing parameter name.
 603  * @return:  0 on success, -1 on error.
 604  */
 605 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 606                                int time, enum gpmc_clk_domain cd, const char *name)
 607 {
 608         u32 l;
 609         int ticks, mask, nr_bits;
 610
 611         if (time == 0)
 612                 ticks = 0;
 613         else
 614                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 615         nr_bits = end_bit - st_bit + 1;
 616         mask = (1 << nr_bits) - 1;
 617
 618         if (!max)
 619                 max = mask;
 620
 621         if (ticks > max) {
 622                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 623                        __func__, cs, name, time, ticks, max);
 624
 625                 return -1;
 626         }
 627
 628         l = gpmc_cs_read_reg(cs, reg);
 629 #ifdef CONFIG_OMAP_GPMC_DEBUG
 630         pr_info(
 631                 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 632                cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 633                         (l >> st_bit) & mask, time);
 634 #endif
 635         l &= ~(mask << st_bit);
 636         l |= ticks << st_bit;
 637         gpmc_cs_write_reg(cs, reg, l);
 638
 639         return 0;
 640 }
 641
 642 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd)  \
 643         if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
 644             t->field, (cd), #field) < 0)                       \
 645                 return -1
 646
 647 #define GPMC_SET_ONE(reg, st, end, field) \
 648         GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
 649
 650 /**
 651  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 652  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 653  * read  --> don't sample bus too early
 654  * write --> data is longer on bus
 655  *
 656  * Formula:
 657  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 658  *                    / waitmonitoring_ticks)
 659  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 660  * div <= 0 check.
 661  *
 662  * @wait_monitoring: WAITMONITORINGTIME in ns.
 663  * @return:          -1 on failure to scale, else proper divider > 0.
 664  */
 665 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 666 {
 667
 668         int div = gpmc_ns_to_ticks(wait_monitoring);
 669
 670         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 671         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 672
 673         if (div > 4)
 674                 return -1;
 675         if (div <= 0)
 676                 div = 1;
 677
 678         return div;
 679
 680 }
 681
 682 /**
 683  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 684  * @sync_clk: GPMC_CLK period in ps.
 685  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 686  *            Else, returns -1.
 687  */
 688 int gpmc_calc_divider(unsigned int sync_clk)
 689 {
 690         int div = gpmc_ps_to_ticks(sync_clk);
 691
 692         if (div > 4)
 693                 return -1;
 694         if (div <= 0)
 695                 div = 1;
 696
 697         return div;
 698 }
 699
 700 /**
 701  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 702  * @cs:     Chip Select Region.
 703  * @t:      GPMC timing parameters.
 704  * @s:      GPMC timing settings.
 705  * @return: 0 on success, -1 on error.
 706  */
 707 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 708                         const struct gpmc_settings *s)
 709 {
 710         int div;
 711         u32 l;
 712
 713         div = gpmc_calc_divider(t->sync_clk);
 714         if (div < 0)
 715                 return div;
 716
 717         /*
 718          * See if we need to change the divider for waitmonitoringtime.
 719          *
 720          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 721          * pure asynchronous accesses, i.e. both read and write asynchronous.
 722          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 723          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 724          *
 725          * This statement must not change div to scale async WAITMONITORINGTIME
 726          * to protect mixed synchronous and asynchronous accesses.
 727          *
 728          * We raise an error later if WAITMONITORINGTIME does not fit.
 729          */
 730         if (!s->sync_read && !s->sync_write &&
 731             (s->wait_on_read || s->wait_on_write)
 732            ) {
 733
 734                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 735                 if (div < 0) {
 736                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 737                                __func__,
 738                                t->wait_monitoring
 739                                );
 740                         return -1;
 741                 }
 742         }
 743
 744         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 745         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 746         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 747
 748         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 749         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 750         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 751         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 752                 GPMC_SET_ONE(GPMC_CS_CONFIG3,  4,  6, adv_aad_mux_on);
 753                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
 754                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
 755         }
 756
 757         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 758         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 759         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 760                 GPMC_SET_ONE(GPMC_CS_CONFIG4,  4,  6, oe_aad_mux_on);
 761                 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
 762         }
 763         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 764         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 765
 766         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 767         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 768         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 769
 770         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 771
 772         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 773         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 774
 775         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 776                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 777         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 778                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 779
 780         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 781         l &= ~0x03;
 782         l |= (div - 1);
 783         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 784
 785         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 786                             GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 787                             wait_monitoring, GPMC_CD_CLK);
 788         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 789                             GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 790                             clk_activation, GPMC_CD_FCLK);
 791
 792 #ifdef CONFIG_OMAP_GPMC_DEBUG
 793         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 794                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 795 #endif
 796
 797         gpmc_cs_bool_timings(cs, &t->bool_timings);
 798         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 799
 800         return 0;
 801 }
 802
 803 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 804 {
 805         u32 l;
 806         u32 mask;
 807
 808         /*
 809          * Ensure that base address is aligned on a
 810          * boundary equal to or greater than size.
 811          */
 812         if (base & (size - 1))
 813                 return -EINVAL;
 814
 815         base >>= GPMC_CHUNK_SHIFT;
 816         mask = (1 << GPMC_SECTION_SHIFT) - size;
 817         mask >>= GPMC_CHUNK_SHIFT;
 818         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 819
 820         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 821         l &= ~GPMC_CONFIG7_MASK;
 822         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 823         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 824         l |= GPMC_CONFIG7_CSVALID;
 825         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 826
 827         return 0;
 828 }
 829
 830 static void gpmc_cs_enable_mem(int cs)
 831 {
 832         u32 l;
 833
 834         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 835         l |= GPMC_CONFIG7_CSVALID;
 836         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 837 }
 838
 839 static void gpmc_cs_disable_mem(int cs)
 840 {
 841         u32 l;
 842
 843         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 844         l &= ~GPMC_CONFIG7_CSVALID;
 845         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 846 }
 847
 848 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 849 {
 850         u32 l;
 851         u32 mask;
 852
 853         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 854         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 855         mask = (l >> 8) & 0x0f;
 856         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 857 }
 858
 859 static int gpmc_cs_mem_enabled(int cs)
 860 {
 861         u32 l;
 862
 863         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 864         return l & GPMC_CONFIG7_CSVALID;
 865 }
 866
 867 static void gpmc_cs_set_reserved(int cs, int reserved)
 868 {
 869         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 870
 871         gpmc->flags |= GPMC_CS_RESERVED;
 872 }
 873
 874 static bool gpmc_cs_reserved(int cs)
 875 {
 876         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 877
 878         return gpmc->flags & GPMC_CS_RESERVED;
 879 }
 880
 881 static void gpmc_cs_set_name(int cs, const char *name)
 882 {
 883         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 884
 885         gpmc->name = name;
 886 }
 887
 888 static const char *gpmc_cs_get_name(int cs)
 889 {
 890         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 891
 892         return gpmc->name;
 893 }
 894
 895 static unsigned long gpmc_mem_align(unsigned long size)
 896 {
 897         int order;
 898
 899         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 900         order = GPMC_CHUNK_SHIFT - 1;
 901         do {
 902                 size >>= 1;
 903                 order++;
 904         } while (size);
 905         size = 1 << order;
 906         return size;
 907 }
 908
 909 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 910 {
 911         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 912         struct resource *res = &gpmc->mem;
 913         int r;
 914
 915         size = gpmc_mem_align(size);
 916         spin_lock(&gpmc_mem_lock);
 917         res->start = base;
 918         res->end = base + size - 1;
 919         r = request_resource(&gpmc_mem_root, res);
 920         spin_unlock(&gpmc_mem_lock);
 921
 922         return r;
 923 }
 924
 925 static int gpmc_cs_delete_mem(int cs)
 926 {
 927         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 928         struct resource *res = &gpmc->mem;
 929         int r;
 930
 931         spin_lock(&gpmc_mem_lock);
 932         r = release_resource(res);
 933         res->start = 0;
 934         res->end = 0;
 935         spin_unlock(&gpmc_mem_lock);
 936
 937         return r;
 938 }
 939
 940 /**
 941  * gpmc_cs_remap - remaps a chip-select physical base address
 942  * @cs:         chip-select to remap
 943  * @base:       physical base address to re-map chip-select to
 944  *
 945  * Re-maps a chip-select to a new physical base address specified by
 946  * "base". Returns 0 on success and appropriate negative error code
 947  * on failure.
 948  */
 949 static int gpmc_cs_remap(int cs, u32 base)
 950 {
 951         int ret;
 952         u32 old_base, size;
 953
 954         if (cs > gpmc_cs_num) {
 955                 pr_err("%s: requested chip-select is disabled\n", __func__);
 956                 return -ENODEV;
 957         }
 958
 959         /*
 960          * Make sure we ignore any device offsets from the GPMC partition
 961          * allocated for the chip select and that the new base confirms
 962          * to the GPMC 16MB minimum granularity.
 963          */
 964         base &= ~(SZ_16M - 1);
 965
 966         gpmc_cs_get_memconf(cs, &old_base, &size);
 967         if (base == old_base)
 968                 return 0;
 969
 970         ret = gpmc_cs_delete_mem(cs);
 971         if (ret < 0)
 972                 return ret;
 973
 974         ret = gpmc_cs_insert_mem(cs, base, size);
 975         if (ret < 0)
 976                 return ret;
 977
 978         ret = gpmc_cs_set_memconf(cs, base, size);
 979
 980         return ret;
 981 }
 982
 983 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 984 {
 985         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 986         struct resource *res = &gpmc->mem;
 987         int r = -1;
 988
 989         if (cs > gpmc_cs_num) {
 990                 pr_err("%s: requested chip-select is disabled\n", __func__);
 991                 return -ENODEV;
 992         }
 993         size = gpmc_mem_align(size);
 994         if (size > (1 << GPMC_SECTION_SHIFT))
 995                 return -ENOMEM;
 996
 997         spin_lock(&gpmc_mem_lock);
 998         if (gpmc_cs_reserved(cs)) {
 999                 r = -EBUSY;
1000                 goto out;
1001         }
1002         if (gpmc_cs_mem_enabled(cs))
1003                 r = adjust_resource(res, res->start & ~(size - 1), size);
1004         if (r < 0)
1005                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1006                                       size, NULL, NULL);
1007         if (r < 0)
1008                 goto out;
1009
1010         /* Disable CS while changing base address and size mask */
1011         gpmc_cs_disable_mem(cs);
1012
1013         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1014         if (r < 0) {
1015                 release_resource(res);
1016                 goto out;
1017         }
1018
1019         /* Enable CS */
1020         gpmc_cs_enable_mem(cs);
1021         *base = res->start;
1022         gpmc_cs_set_reserved(cs, 1);
1023 out:
1024         spin_unlock(&gpmc_mem_lock);
1025         return r;
1026 }
1027 EXPORT_SYMBOL(gpmc_cs_request);
1028
1029 void gpmc_cs_free(int cs)
1030 {
1031         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1032         struct resource *res = &gpmc->mem;
1033
1034         spin_lock(&gpmc_mem_lock);
1035         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1036                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1037                 BUG();
1038                 spin_unlock(&gpmc_mem_lock);
1039                 return;
1040         }
1041         gpmc_cs_disable_mem(cs);
1042         if (res->flags)
1043                 release_resource(res);
1044         gpmc_cs_set_reserved(cs, 0);
1045         spin_unlock(&gpmc_mem_lock);
1046 }
1047 EXPORT_SYMBOL(gpmc_cs_free);
1048
1049 /**
1050  * gpmc_configure - write request to configure gpmc
1051  * @cmd: command type
1052  * @wval: value to write
1053  * @return status of the operation
1054  */
1055 int gpmc_configure(int cmd, int wval)
1056 {
1057         u32 regval;
1058
1059         switch (cmd) {
1060         case GPMC_CONFIG_WP:
1061                 regval = gpmc_read_reg(GPMC_CONFIG);
1062                 if (wval)
1063                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1064                 else
1065                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1066                 gpmc_write_reg(GPMC_CONFIG, regval);
1067                 break;
1068
1069         default:
1070                 pr_err("%s: command not supported\n", __func__);
1071                 return -EINVAL;
1072         }
1073
1074         return 0;
1075 }
1076 EXPORT_SYMBOL(gpmc_configure);
1077
1078 static bool gpmc_nand_writebuffer_empty(void)
1079 {
1080         if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1081                 return true;
1082
1083         return false;
1084 }
1085
1086 static struct gpmc_nand_ops nand_ops = {
1087         .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1088 };
1089
1090 /**
1091  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1092  * @regs: the GPMC NAND register map exclusive for NAND use.
1093  * @cs: GPMC chip select number on which the NAND sits. The
1094  *      register map returned will be specific to this chip select.
1095  *
1096  * Returns NULL on error e.g. invalid cs.
1097  */
1098 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1099 {
1100         int i;
1101
1102         if (cs >= gpmc_cs_num)
1103                 return NULL;
1104
1105         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1106                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1107         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1108                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1109         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1110                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1111         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1112         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1113         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1114         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1115         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1116         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1117         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1118         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1119
1120         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1121                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1122                                            GPMC_BCH_SIZE * i;
1123                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1124                                            GPMC_BCH_SIZE * i;
1125                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1126                                            GPMC_BCH_SIZE * i;
1127                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1128                                            GPMC_BCH_SIZE * i;
1129                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1130                                            i * GPMC_BCH_SIZE;
1131                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1132                                            i * GPMC_BCH_SIZE;
1133                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1134                                            i * GPMC_BCH_SIZE;
1135         }
1136
1137         return &nand_ops;
1138 }
1139 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1140
1141 int gpmc_get_client_irq(unsigned irq_config)
1142 {
1143         if (!gpmc_irq_domain) {
1144                 pr_warn("%s called before GPMC IRQ domain available\n",
1145                         __func__);
1146                 return 0;
1147         }
1148
1149         /* we restrict this to NAND IRQs only */
1150         if (irq_config >= GPMC_NR_NAND_IRQS)
1151                 return 0;
1152
1153         return irq_create_mapping(gpmc_irq_domain, irq_config);
1154 }
1155
1156 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1157 {
1158         u32 regval;
1159
1160         /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1161         if (hwirq >= GPMC_NR_NAND_IRQS)
1162                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1163
1164         regval = gpmc_read_reg(GPMC_IRQENABLE);
1165         if (endis)
1166                 regval |= BIT(hwirq);
1167         else
1168                 regval &= ~BIT(hwirq);
1169         gpmc_write_reg(GPMC_IRQENABLE, regval);
1170
1171         return 0;
1172 }
1173
1174 static void gpmc_irq_disable(struct irq_data *p)
1175 {
1176         gpmc_irq_endis(p->hwirq, false);
1177 }
1178
1179 static void gpmc_irq_enable(struct irq_data *p)
1180 {
1181         gpmc_irq_endis(p->hwirq, true);
1182 }
1183
1184 static void gpmc_irq_mask(struct irq_data *d)
1185 {
1186         gpmc_irq_endis(d->hwirq, false);
1187 }
1188
1189 static void gpmc_irq_unmask(struct irq_data *d)
1190 {
1191         gpmc_irq_endis(d->hwirq, true);
1192 }
1193
1194 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1195 {
1196         u32 regval;
1197
1198         /* NAND IRQs polarity is not configurable */
1199         if (hwirq < GPMC_NR_NAND_IRQS)
1200                 return;
1201
1202         /* WAITPIN starts at BIT 8 */
1203         hwirq += 8 - GPMC_NR_NAND_IRQS;
1204
1205         regval = gpmc_read_reg(GPMC_CONFIG);
1206         if (rising_edge)
1207                 regval &= ~BIT(hwirq);
1208         else
1209                 regval |= BIT(hwirq);
1210
1211         gpmc_write_reg(GPMC_CONFIG, regval);
1212 }
1213
1214 static void gpmc_irq_ack(struct irq_data *d)
1215 {
1216         unsigned int hwirq = d->hwirq;
1217
1218         /* skip reserved bits */
1219         if (hwirq >= GPMC_NR_NAND_IRQS)
1220                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1221
1222         /* Setting bit to 1 clears (or Acks) the interrupt */
1223         gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1224 }
1225
1226 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1227 {
1228         /* can't set type for NAND IRQs */
1229         if (d->hwirq < GPMC_NR_NAND_IRQS)
1230                 return -EINVAL;
1231
1232         /* We can support either rising or falling edge at a time */
1233         if (trigger == IRQ_TYPE_EDGE_FALLING)
1234                 gpmc_irq_edge_config(d->hwirq, false);
1235         else if (trigger == IRQ_TYPE_EDGE_RISING)
1236                 gpmc_irq_edge_config(d->hwirq, true);
1237         else
1238                 return -EINVAL;
1239
1240         return 0;
1241 }
1242
1243 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1244                         irq_hw_number_t hw)
1245 {
1246         struct gpmc_device *gpmc = d->host_data;
1247
1248         irq_set_chip_data(virq, gpmc);
1249         if (hw < GPMC_NR_NAND_IRQS) {
1250                 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1251                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1252                                          handle_simple_irq);
1253         } else {
1254                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1255                                          handle_edge_irq);
1256         }
1257
1258         return 0;
1259 }
1260
1261 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1262         .map    = gpmc_irq_map,
1263         .xlate  = irq_domain_xlate_twocell,
1264 };
1265
1266 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1267 {
1268         int hwirq, virq;
1269         u32 regval, regvalx;
1270         struct gpmc_device *gpmc = data;
1271
1272         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1273         regvalx = regval;
1274
1275         if (!regval)
1276                 return IRQ_NONE;
1277
1278         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1279                 /* skip reserved status bits */
1280                 if (hwirq == GPMC_NR_NAND_IRQS)
1281                         regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1282
1283                 if (regvalx & BIT(hwirq)) {
1284                         virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1285                         if (!virq) {
1286                                 dev_warn(gpmc->dev,
1287                                          "spurious irq detected hwirq %d, virq %d\n",
1288                                          hwirq, virq);
1289                         }
1290
1291                         generic_handle_irq(virq);
1292                 }
1293         }
1294
1295         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1296
1297         return IRQ_HANDLED;
1298 }
1299
1300 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1301 {
1302         u32 regval;
1303         int rc;
1304
1305         /* Disable interrupts */
1306         gpmc_write_reg(GPMC_IRQENABLE, 0);
1307
1308         /* clear interrupts */
1309         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1310         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1311
1312         gpmc->irq_chip.name = "gpmc";
1313         gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1314         gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1315         gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1316         gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1317         gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1318         gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1319
1320         gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1321                                                 gpmc->nirqs,
1322                                                 &gpmc_irq_domain_ops,
1323                                                 gpmc);
1324         if (!gpmc_irq_domain) {
1325                 dev_err(gpmc->dev, "IRQ domain add failed\n");
1326                 return -ENODEV;
1327         }
1328
1329         rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1330         if (rc) {
1331                 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1332                         gpmc->irq, rc);
1333                 irq_domain_remove(gpmc_irq_domain);
1334                 gpmc_irq_domain = NULL;
1335         }
1336
1337         return rc;
1338 }
1339
1340 static int gpmc_free_irq(struct gpmc_device *gpmc)
1341 {
1342         int hwirq;
1343
1344         free_irq(gpmc->irq, gpmc);
1345
1346         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1347                 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1348
1349         irq_domain_remove(gpmc_irq_domain);
1350         gpmc_irq_domain = NULL;
1351
1352         return 0;
1353 }
1354
1355 static void gpmc_mem_exit(void)
1356 {
1357         int cs;
1358
1359         for (cs = 0; cs < gpmc_cs_num; cs++) {
1360                 if (!gpmc_cs_mem_enabled(cs))
1361                         continue;
1362                 gpmc_cs_delete_mem(cs);
1363         }
1364
1365 }
1366
1367 static void gpmc_mem_init(void)
1368 {
1369         int cs;
1370
1371         gpmc_mem_root.start = GPMC_MEM_START;
1372         gpmc_mem_root.end = GPMC_MEM_END;
1373
1374         /* Reserve all regions that has been set up by bootloader */
1375         for (cs = 0; cs < gpmc_cs_num; cs++) {
1376                 u32 base, size;
1377
1378                 if (!gpmc_cs_mem_enabled(cs))
1379                         continue;
1380                 gpmc_cs_get_memconf(cs, &base, &size);
1381                 if (gpmc_cs_insert_mem(cs, base, size)) {
1382                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1383                                 __func__, cs, base, base + size);
1384                         gpmc_cs_disable_mem(cs);
1385                 }
1386         }
1387 }
1388
1389 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1390 {
1391         u32 temp;
1392         int div;
1393
1394         div = gpmc_calc_divider(sync_clk);
1395         temp = gpmc_ps_to_ticks(time_ps);
1396         temp = (temp + div - 1) / div;
1397         return gpmc_ticks_to_ps(temp * div);
1398 }
1399
1400 /* XXX: can the cycles be avoided ? */
1401 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1402                                        struct gpmc_device_timings *dev_t,
1403                                        bool mux)
1404 {
1405         u32 temp;
1406
1407         /* adv_rd_off */
1408         temp = dev_t->t_avdp_r;
1409         /* XXX: mux check required ? */
1410         if (mux) {
1411                 /* XXX: t_avdp not to be required for sync, only added for tusb
1412                  * this indirectly necessitates requirement of t_avdp_r and
1413                  * t_avdp_w instead of having a single t_avdp
1414                  */
1415                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1416                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1417         }
1418         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1419
1420         /* oe_on */
1421         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1422         if (mux) {
1423                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1424                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1425                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1426         }
1427         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1428
1429         /* access */
1430         /* XXX: any scope for improvement ?, by combining oe_on
1431          * and clk_activation, need to check whether
1432          * access = clk_activation + round to sync clk ?
1433          */
1434         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1435         temp += gpmc_t->clk_activation;
1436         if (dev_t->cyc_oe)
1437                 temp = max_t(u32, temp, gpmc_t->oe_on +
1438                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1439         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1440
1441         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1442         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1443
1444         /* rd_cycle */
1445         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1446         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1447                                                         gpmc_t->access;
1448         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1449         if (dev_t->t_ce_rdyz)
1450                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1451         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1452
1453         return 0;
1454 }
1455
1456 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1457                                         struct gpmc_device_timings *dev_t,
1458                                         bool mux)
1459 {
1460         u32 temp;
1461
1462         /* adv_wr_off */
1463         temp = dev_t->t_avdp_w;
1464         if (mux) {
1465                 temp = max_t(u32, temp,
1466                         gpmc_t->clk_activation + dev_t->t_avdh);
1467                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1468         }
1469         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1470
1471         /* wr_data_mux_bus */
1472         temp = max_t(u32, dev_t->t_weasu,
1473                         gpmc_t->clk_activation + dev_t->t_rdyo);
1474         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1475          * and in that case remember to handle we_on properly
1476          */
1477         if (mux) {
1478                 temp = max_t(u32, temp,
1479                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1480                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1481                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1482         }
1483         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1484
1485         /* we_on */
1486         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1487                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1488         else
1489                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1490
1491         /* wr_access */
1492         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1493         gpmc_t->wr_access = gpmc_t->access;
1494
1495         /* we_off */
1496         temp = gpmc_t->we_on + dev_t->t_wpl;
1497         temp = max_t(u32, temp,
1498                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1499         temp = max_t(u32, temp,
1500                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1501         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1502
1503         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1504                                                         dev_t->t_wph);
1505
1506         /* wr_cycle */
1507         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1508         temp += gpmc_t->wr_access;
1509         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1510         if (dev_t->t_ce_rdyz)
1511                 temp = max_t(u32, temp,
1512                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1513         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1514
1515         return 0;
1516 }
1517
1518 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1519                                         struct gpmc_device_timings *dev_t,
1520                                         bool mux)
1521 {
1522         u32 temp;
1523
1524         /* adv_rd_off */
1525         temp = dev_t->t_avdp_r;
1526         if (mux)
1527                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1528         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1529
1530         /* oe_on */
1531         temp = dev_t->t_oeasu;
1532         if (mux)
1533                 temp = max_t(u32, temp,
1534                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
1535         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1536
1537         /* access */
1538         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1539                                 gpmc_t->oe_on + dev_t->t_oe);
1540         temp = max_t(u32, temp,
1541                                 gpmc_t->cs_on + dev_t->t_ce);
1542         temp = max_t(u32, temp,
1543                                 gpmc_t->adv_on + dev_t->t_aa);
1544         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1545
1546         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1547         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1548
1549         /* rd_cycle */
1550         temp = max_t(u32, dev_t->t_rd_cycle,
1551                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1552         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1553         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1554
1555         return 0;
1556 }
1557
1558 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1559                                          struct gpmc_device_timings *dev_t,
1560                                          bool mux)
1561 {
1562         u32 temp;
1563
1564         /* adv_wr_off */
1565         temp = dev_t->t_avdp_w;
1566         if (mux)
1567                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1568         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1569
1570         /* wr_data_mux_bus */
1571         temp = dev_t->t_weasu;
1572         if (mux) {
1573                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1574                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1575                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1576         }
1577         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1578
1579         /* we_on */
1580         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1581                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1582         else
1583                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1584
1585         /* we_off */
1586         temp = gpmc_t->we_on + dev_t->t_wpl;
1587         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1588
1589         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1590                                                         dev_t->t_wph);
1591
1592         /* wr_cycle */
1593         temp = max_t(u32, dev_t->t_wr_cycle,
1594                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1595         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1596
1597         return 0;
1598 }
1599
1600 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1601                         struct gpmc_device_timings *dev_t)
1602 {
1603         u32 temp;
1604
1605         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1606                                                 gpmc_get_fclk_period();
1607
1608         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1609                                         dev_t->t_bacc,
1610                                         gpmc_t->sync_clk);
1611
1612         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1613         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1614
1615         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1616                 return 0;
1617
1618         if (dev_t->ce_xdelay)
1619                 gpmc_t->bool_timings.cs_extra_delay = true;
1620         if (dev_t->avd_xdelay)
1621                 gpmc_t->bool_timings.adv_extra_delay = true;
1622         if (dev_t->oe_xdelay)
1623                 gpmc_t->bool_timings.oe_extra_delay = true;
1624         if (dev_t->we_xdelay)
1625                 gpmc_t->bool_timings.we_extra_delay = true;
1626
1627         return 0;
1628 }
1629
1630 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1631                                     struct gpmc_device_timings *dev_t,
1632                                     bool sync)
1633 {
1634         u32 temp;
1635
1636         /* cs_on */
1637         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1638
1639         /* adv_on */
1640         temp = dev_t->t_avdasu;
1641         if (dev_t->t_ce_avd)
1642                 temp = max_t(u32, temp,
1643                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1644         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1645
1646         if (sync)
1647                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1648
1649         return 0;
1650 }
1651
1652 /* TODO: remove this function once all peripherals are confirmed to
1653  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1654  * has to be modified to handle timings in ps instead of ns
1655 */
1656 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1657 {
1658         t->cs_on /= 1000;
1659         t->cs_rd_off /= 1000;
1660         t->cs_wr_off /= 1000;
1661         t->adv_on /= 1000;
1662         t->adv_rd_off /= 1000;
1663         t->adv_wr_off /= 1000;
1664         t->we_on /= 1000;
1665         t->we_off /= 1000;
1666         t->oe_on /= 1000;
1667         t->oe_off /= 1000;
1668         t->page_burst_access /= 1000;
1669         t->access /= 1000;
1670         t->rd_cycle /= 1000;
1671         t->wr_cycle /= 1000;
1672         t->bus_turnaround /= 1000;
1673         t->cycle2cycle_delay /= 1000;
1674         t->wait_monitoring /= 1000;
1675         t->clk_activation /= 1000;
1676         t->wr_access /= 1000;
1677         t->wr_data_mux_bus /= 1000;
1678 }
1679
1680 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1681                       struct gpmc_settings *gpmc_s,
1682                       struct gpmc_device_timings *dev_t)
1683 {
1684         bool mux = false, sync = false;
1685
1686         if (gpmc_s) {
1687                 mux = gpmc_s->mux_add_data ? true : false;
1688                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1689         }
1690
1691         memset(gpmc_t, 0, sizeof(*gpmc_t));
1692
1693         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1694
1695         if (gpmc_s && gpmc_s->sync_read)
1696                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1697         else
1698                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1699
1700         if (gpmc_s && gpmc_s->sync_write)
1701                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1702         else
1703                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1704
1705         /* TODO: remove, see function definition */
1706         gpmc_convert_ps_to_ns(gpmc_t);
1707
1708         return 0;
1709 }
1710
1711 /**
1712  * gpmc_cs_program_settings - programs non-timing related settings
1713  * @cs:         GPMC chip-select to program
1714  * @p:          pointer to GPMC settings structure
1715  *
1716  * Programs non-timing related settings for a GPMC chip-select, such as
1717  * bus-width, burst configuration, etc. Function should be called once
1718  * for each chip-select that is being used and must be called before
1719  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1720  * register will be initialised to zero by this function. Returns 0 on
1721  * success and appropriate negative error code on failure.
1722  */
1723 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1724 {
1725         u32 config1;
1726
1727         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1728                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1729                 return -EINVAL;
1730         }
1731
1732         /* Address-data multiplexing not supported for NAND devices */
1733         if (p->device_nand && p->mux_add_data) {
1734                 pr_err("%s: invalid configuration!\n", __func__);
1735                 return -EINVAL;
1736         }
1737
1738         if ((p->mux_add_data > GPMC_MUX_AD) ||
1739             ((p->mux_add_data == GPMC_MUX_AAD) &&
1740              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1741                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1742                 return -EINVAL;
1743         }
1744
1745         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1746         if (p->burst_read || p->burst_write) {
1747                 switch (p->burst_len) {
1748                 case GPMC_BURST_4:
1749                 case GPMC_BURST_8:
1750                 case GPMC_BURST_16:
1751                         break;
1752                 default:
1753                         pr_err("%s: invalid page/burst-length (%d)\n",
1754                                __func__, p->burst_len);
1755                         return -EINVAL;
1756                 }
1757         }
1758
1759         if (p->wait_pin > gpmc_nr_waitpins) {
1760                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1761                 return -EINVAL;
1762         }
1763
1764         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1765
1766         if (p->sync_read)
1767                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1768         if (p->sync_write)
1769                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1770         if (p->wait_on_read)
1771                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1772         if (p->wait_on_write)
1773                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1774         if (p->wait_on_read || p->wait_on_write)
1775                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1776         if (p->device_nand)
1777                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1778         if (p->mux_add_data)
1779                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1780         if (p->burst_read)
1781                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1782         if (p->burst_write)
1783                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1784         if (p->burst_read || p->burst_write) {
1785                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1786                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1787         }
1788
1789         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1790
1791         return 0;
1792 }
1793
1794 #ifdef CONFIG_OF
1795 static const struct of_device_id gpmc_dt_ids[] = {
1796         { .compatible = "ti,omap2420-gpmc" },
1797         { .compatible = "ti,omap2430-gpmc" },
1798         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1799         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1800         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1801         { }
1802 };
1803
1804 /**
1805  * gpmc_read_settings_dt - read gpmc settings from device-tree
1806  * @np:         pointer to device-tree node for a gpmc child device
1807  * @p:          pointer to gpmc settings structure
1808  *
1809  * Reads the GPMC settings for a GPMC child device from device-tree and
1810  * stores them in the GPMC settings structure passed. The GPMC settings
1811  * structure is initialised to zero by this function and so any
1812  * previously stored settings will be cleared.
1813  */
1814 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1815 {
1816         memset(p, 0, sizeof(struct gpmc_settings));
1817
1818         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1819         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1820         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1821         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1822
1823         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1824                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1825                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1826                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1827                 if (!p->burst_read && !p->burst_write)
1828                         pr_warn("%s: page/burst-length set but not used!\n",
1829                                 __func__);
1830         }
1831
1832         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1833                 p->wait_on_read = of_property_read_bool(np,
1834                                                         "gpmc,wait-on-read");
1835                 p->wait_on_write = of_property_read_bool(np,
1836                                                          "gpmc,wait-on-write");
1837                 if (!p->wait_on_read && !p->wait_on_write)
1838                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1839                                  __func__);
1840         }
1841 }
1842
1843 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1844                                                 struct gpmc_timings *gpmc_t)
1845 {
1846         struct gpmc_bool_timings *p;
1847
1848         if (!np || !gpmc_t)
1849                 return;
1850
1851         memset(gpmc_t, 0, sizeof(*gpmc_t));
1852
1853         /* minimum clock period for syncronous mode */
1854         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1855
1856         /* chip select timtings */
1857         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1858         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1859         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1860
1861         /* ADV signal timings */
1862         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1863         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1864         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1865         of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1866                              &gpmc_t->adv_aad_mux_on);
1867         of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1868                              &gpmc_t->adv_aad_mux_rd_off);
1869         of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1870                              &gpmc_t->adv_aad_mux_wr_off);
1871
1872         /* WE signal timings */
1873         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1874         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1875
1876         /* OE signal timings */
1877         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1878         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1879         of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1880                              &gpmc_t->oe_aad_mux_on);
1881         of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1882                              &gpmc_t->oe_aad_mux_off);
1883
1884         /* access and cycle timings */
1885         of_property_read_u32(np, "gpmc,page-burst-access-ns",
1886                              &gpmc_t->page_burst_access);
1887         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1888         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1889         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1890         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1891                              &gpmc_t->bus_turnaround);
1892         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1893                              &gpmc_t->cycle2cycle_delay);
1894         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1895                              &gpmc_t->wait_monitoring);
1896         of_property_read_u32(np, "gpmc,clk-activation-ns",
1897                              &gpmc_t->clk_activation);
1898
1899         /* only applicable to OMAP3+ */
1900         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1901         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1902                              &gpmc_t->wr_data_mux_bus);
1903
1904         /* bool timing parameters */
1905         p = &gpmc_t->bool_timings;
1906
1907         p->cycle2cyclediffcsen =
1908                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1909         p->cycle2cyclesamecsen =
1910                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1911         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1912         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1913         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1914         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1915         p->time_para_granularity =
1916                 of_property_read_bool(np, "gpmc,time-para-granularity");
1917 }
1918
1919 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1920 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1921                                  struct device_node *child)
1922 {
1923         u32 val;
1924         struct omap_onenand_platform_data *gpmc_onenand_data;
1925
1926         if (of_property_read_u32(child, "reg", &val) < 0) {
1927                 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
1928                         child);
1929                 return -ENODEV;
1930         }
1931
1932         gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1933                                          GFP_KERNEL);
1934         if (!gpmc_onenand_data)
1935                 return -ENOMEM;
1936
1937         gpmc_onenand_data->cs = val;
1938         gpmc_onenand_data->of_node = child;
1939         gpmc_onenand_data->dma_channel = -1;
1940
1941         if (!of_property_read_u32(child, "dma-channel", &val))
1942                 gpmc_onenand_data->dma_channel = val;
1943
1944         return gpmc_onenand_init(gpmc_onenand_data);
1945 }
1946 #else
1947 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1948                                     struct device_node *child)
1949 {
1950         return 0;
1951 }
1952 #endif
1953
1954 /**
1955  * gpmc_probe_generic_child - configures the gpmc for a child device
1956  * @pdev:       pointer to gpmc platform device
1957  * @child:      pointer to device-tree node for child device
1958  *
1959  * Allocates and configures a GPMC chip-select for a child device.
1960  * Returns 0 on success and appropriate negative error code on failure.
1961  */
1962 static int gpmc_probe_generic_child(struct platform_device *pdev,
1963                                 struct device_node *child)
1964 {
1965         struct gpmc_settings gpmc_s;
1966         struct gpmc_timings gpmc_t;
1967         struct resource res;
1968         unsigned long base;
1969         const char *name;
1970         int ret, cs;
1971         u32 val;
1972         struct gpio_desc *waitpin_desc = NULL;
1973         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
1974
1975         if (of_property_read_u32(child, "reg", &cs) < 0) {
1976                 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
1977                         child);
1978                 return -ENODEV;
1979         }
1980
1981         if (of_address_to_resource(child, 0, &res) < 0) {
1982                 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
1983                         child);
1984                 return -ENODEV;
1985         }
1986
1987         /*
1988          * Check if we have multiple instances of the same device
1989          * on a single chip select. If so, use the already initialized
1990          * timings.
1991          */
1992         name = gpmc_cs_get_name(cs);
1993         if (name && child->name && of_node_cmp(child->name, name) == 0)
1994                         goto no_timings;
1995
1996         ret = gpmc_cs_request(cs, resource_size(&res), &base);
1997         if (ret < 0) {
1998                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1999                 return ret;
2000         }
2001         gpmc_cs_set_name(cs, child->name);
2002
2003         gpmc_read_settings_dt(child, &gpmc_s);
2004         gpmc_read_timings_dt(child, &gpmc_t);
2005
2006         /*
2007          * For some GPMC devices we still need to rely on the bootloader
2008          * timings because the devices can be connected via FPGA.
2009          * REVISIT: Add timing support from slls644g.pdf.
2010          */
2011         if (!gpmc_t.cs_rd_off) {
2012                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2013                         cs);
2014                 gpmc_cs_show_timings(cs,
2015                                      "please add GPMC bootloader timings to .dts");
2016                 goto no_timings;
2017         }
2018
2019         /* CS must be disabled while making changes to gpmc configuration */
2020         gpmc_cs_disable_mem(cs);
2021
2022         /*
2023          * FIXME: gpmc_cs_request() will map the CS to an arbitary
2024          * location in the gpmc address space. When booting with
2025          * device-tree we want the NOR flash to be mapped to the
2026          * location specified in the device-tree blob. So remap the
2027          * CS to this location. Once DT migration is complete should
2028          * just make gpmc_cs_request() map a specific address.
2029          */
2030         ret = gpmc_cs_remap(cs, res.start);
2031         if (ret < 0) {
2032                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2033                         cs, &res.start);
2034                 if (res.start < GPMC_MEM_START) {
2035                         dev_info(&pdev->dev,
2036                                  "GPMC CS %d start cannot be lesser than 0x%x\n",
2037                                  cs, GPMC_MEM_START);
2038                 } else if (res.end > GPMC_MEM_END) {
2039                         dev_info(&pdev->dev,
2040                                  "GPMC CS %d end cannot be greater than 0x%x\n",
2041                                  cs, GPMC_MEM_END);
2042                 }
2043                 goto err;
2044         }
2045
2046         if (of_node_cmp(child->name, "nand") == 0) {
2047                 /* Warn about older DT blobs with no compatible property */
2048                 if (!of_property_read_bool(child, "compatible")) {
2049                         dev_warn(&pdev->dev,
2050                                  "Incompatible NAND node: missing compatible");
2051                         ret = -EINVAL;
2052                         goto err;
2053                 }
2054         }
2055
2056         if (of_device_is_compatible(child, "ti,omap2-nand")) {
2057                 /* NAND specific setup */
2058                 val = 8;
2059                 of_property_read_u32(child, "nand-bus-width", &val);
2060                 switch (val) {
2061                 case 8:
2062                         gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2063                         break;
2064                 case 16:
2065                         gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2066                         break;
2067                 default:
2068                         dev_err(&pdev->dev, "%s: invalid 'nand-bus-width'\n",
2069                                 child->name);
2070                         ret = -EINVAL;
2071                         goto err;
2072                 }
2073
2074                 /* disable write protect */
2075                 gpmc_configure(GPMC_CONFIG_WP, 0);
2076                 gpmc_s.device_nand = true;
2077         } else {
2078                 ret = of_property_read_u32(child, "bank-width",
2079                                            &gpmc_s.device_width);
2080                 if (ret < 0) {
2081                         dev_err(&pdev->dev, "%pOF has no 'bank-width' property\n",
2082                                 child);
2083                         goto err;
2084                 }
2085         }
2086
2087         /* Reserve wait pin if it is required and valid */
2088         if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2089                 unsigned int wait_pin = gpmc_s.wait_pin;
2090
2091                 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2092                                                          wait_pin, "WAITPIN");
2093                 if (IS_ERR(waitpin_desc)) {
2094                         dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2095                         ret = PTR_ERR(waitpin_desc);
2096                         goto err;
2097                 }
2098         }
2099
2100         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2101
2102         ret = gpmc_cs_program_settings(cs, &gpmc_s);
2103         if (ret < 0)
2104                 goto err_cs;
2105
2106         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2107         if (ret) {
2108                 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2109                         child->name);
2110                 goto err_cs;
2111         }
2112
2113         /* Clear limited address i.e. enable A26-A11 */
2114         val = gpmc_read_reg(GPMC_CONFIG);
2115         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2116         gpmc_write_reg(GPMC_CONFIG, val);
2117
2118         /* Enable CS region */
2119         gpmc_cs_enable_mem(cs);
2120
2121 no_timings:
2122
2123         /* create platform device, NULL on error or when disabled */
2124         if (!of_platform_device_create(child, NULL, &pdev->dev))
2125                 goto err_child_fail;
2126
2127         /* is child a common bus? */
2128         if (of_match_node(of_default_bus_match_table, child))
2129                 /* create children and other common bus children */
2130                 if (of_platform_default_populate(child, NULL, &pdev->dev))
2131                         goto err_child_fail;
2132
2133         return 0;
2134
2135 err_child_fail:
2136
2137         dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2138         ret = -ENODEV;
2139
2140 err_cs:
2141         gpiochip_free_own_desc(waitpin_desc);
2142 err:
2143         gpmc_cs_free(cs);
2144
2145         return ret;
2146 }
2147
2148 static int gpmc_probe_dt(struct platform_device *pdev)
2149 {
2150         int ret;
2151         const struct of_device_id *of_id =
2152                 of_match_device(gpmc_dt_ids, &pdev->dev);
2153
2154         if (!of_id)
2155                 return 0;
2156
2157         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2158                                    &gpmc_cs_num);
2159         if (ret < 0) {
2160                 pr_err("%s: number of chip-selects not defined\n", __func__);
2161                 return ret;
2162         } else if (gpmc_cs_num < 1) {
2163                 pr_err("%s: all chip-selects are disabled\n", __func__);
2164                 return -EINVAL;
2165         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2166                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2167                                          __func__, GPMC_CS_NUM);
2168                 return -EINVAL;
2169         }
2170
2171         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2172                                    &gpmc_nr_waitpins);
2173         if (ret < 0) {
2174                 pr_err("%s: number of wait pins not found!\n", __func__);
2175                 return ret;
2176         }
2177
2178         return 0;
2179 }
2180
2181 static void gpmc_probe_dt_children(struct platform_device *pdev)
2182 {
2183         int ret;
2184         struct device_node *child;
2185
2186         for_each_available_child_of_node(pdev->dev.of_node, child) {
2187
2188                 if (!child->name)
2189                         continue;
2190
2191                 if (of_node_cmp(child->name, "onenand") == 0)
2192                         ret = gpmc_probe_onenand_child(pdev, child);
2193                 else
2194                         ret = gpmc_probe_generic_child(pdev, child);
2195
2196                 if (ret) {
2197                         dev_err(&pdev->dev, "failed to probe DT child '%s': %d\n",
2198                                 child->name, ret);
2199                 }
2200         }
2201 }
2202 #else
2203 static int gpmc_probe_dt(struct platform_device *pdev)
2204 {
2205         return 0;
2206 }
2207
2208 static void gpmc_probe_dt_children(struct platform_device *pdev)
2209 {
2210 }
2211 #endif /* CONFIG_OF */
2212
2213 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2214 {
2215         return 1;       /* we're input only */
2216 }
2217
2218 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2219                                      unsigned int offset)
2220 {
2221         return 0;       /* we're input only */
2222 }
2223
2224 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2225                                       unsigned int offset, int value)
2226 {
2227         return -EINVAL; /* we're input only */
2228 }
2229
2230 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2231                           int value)
2232 {
2233 }
2234
2235 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2236 {
2237         u32 reg;
2238
2239         offset += 8;
2240
2241         reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2242
2243         return !!reg;
2244 }
2245
2246 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2247 {
2248         int ret;
2249
2250         gpmc->gpio_chip.parent = gpmc->dev;
2251         gpmc->gpio_chip.owner = THIS_MODULE;
2252         gpmc->gpio_chip.label = DEVICE_NAME;
2253         gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2254         gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2255         gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2256         gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2257         gpmc->gpio_chip.set = gpmc_gpio_set;
2258         gpmc->gpio_chip.get = gpmc_gpio_get;
2259         gpmc->gpio_chip.base = -1;
2260
2261         ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2262         if (ret < 0) {
2263                 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2264                 return ret;
2265         }
2266
2267         return 0;
2268 }
2269
2270 static int gpmc_probe(struct platform_device *pdev)
2271 {
2272         int rc;
2273         u32 l;
2274         struct resource *res;
2275         struct gpmc_device *gpmc;
2276
2277         gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2278         if (!gpmc)
2279                 return -ENOMEM;
2280
2281         gpmc->dev = &pdev->dev;
2282         platform_set_drvdata(pdev, gpmc);
2283
2284         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2285         if (res == NULL)
2286                 return -ENOENT;
2287
2288         phys_base = res->start;
2289         mem_size = resource_size(res);
2290
2291         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2292         if (IS_ERR(gpmc_base))
2293                 return PTR_ERR(gpmc_base);
2294
2295         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2296         if (!res) {
2297                 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2298                 return -ENOENT;
2299         }
2300
2301         gpmc->irq = res->start;
2302
2303         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2304         if (IS_ERR(gpmc_l3_clk)) {
2305                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2306                 return PTR_ERR(gpmc_l3_clk);
2307         }
2308
2309         if (!clk_get_rate(gpmc_l3_clk)) {
2310                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2311                 return -EINVAL;
2312         }
2313
2314         if (pdev->dev.of_node) {
2315                 rc = gpmc_probe_dt(pdev);
2316                 if (rc)
2317                         return rc;
2318         } else {
2319                 gpmc_cs_num = GPMC_CS_NUM;
2320                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2321         }
2322
2323         pm_runtime_enable(&pdev->dev);
2324         pm_runtime_get_sync(&pdev->dev);
2325
2326         l = gpmc_read_reg(GPMC_REVISION);
2327
2328         /*
2329          * FIXME: Once device-tree migration is complete the below flags
2330          * should be populated based upon the device-tree compatible
2331          * string. For now just use the IP revision. OMAP3+ devices have
2332          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2333          * devices support the addr-addr-data multiplex protocol.
2334          *
2335          * GPMC IP revisions:
2336          * - OMAP24xx                   = 2.0
2337          * - OMAP3xxx                   = 5.0
2338          * - OMAP44xx/54xx/AM335x       = 6.0
2339          */
2340         if (GPMC_REVISION_MAJOR(l) > 0x4)
2341                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2342         if (GPMC_REVISION_MAJOR(l) > 0x5)
2343                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2344         dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2345                  GPMC_REVISION_MINOR(l));
2346
2347         gpmc_mem_init();
2348         rc = gpmc_gpio_init(gpmc);
2349         if (rc)
2350                 goto gpio_init_failed;
2351
2352         gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2353         rc = gpmc_setup_irq(gpmc);
2354         if (rc) {
2355                 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2356                 goto gpio_init_failed;
2357         }
2358
2359         gpmc_probe_dt_children(pdev);
2360
2361         return 0;
2362
2363 gpio_init_failed:
2364         gpmc_mem_exit();
2365         pm_runtime_put_sync(&pdev->dev);
2366         pm_runtime_disable(&pdev->dev);
2367
2368         return rc;
2369 }
2370
2371 static int gpmc_remove(struct platform_device *pdev)
2372 {
2373         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2374
2375         gpmc_free_irq(gpmc);
2376         gpmc_mem_exit();
2377         pm_runtime_put_sync(&pdev->dev);
2378         pm_runtime_disable(&pdev->dev);
2379
2380         return 0;
2381 }
2382
2383 #ifdef CONFIG_PM_SLEEP
2384 static int gpmc_suspend(struct device *dev)
2385 {
2386         omap3_gpmc_save_context();
2387         pm_runtime_put_sync(dev);
2388         return 0;
2389 }
2390
2391 static int gpmc_resume(struct device *dev)
2392 {
2393         pm_runtime_get_sync(dev);
2394         omap3_gpmc_restore_context();
2395         return 0;
2396 }
2397 #endif
2398
2399 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2400
2401 static struct platform_driver gpmc_driver = {
2402         .probe          = gpmc_probe,
2403         .remove         = gpmc_remove,
2404         .driver         = {
2405                 .name   = DEVICE_NAME,
2406                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2407                 .pm     = &gpmc_pm_ops,
2408         },
2409 };
2410
2411 static __init int gpmc_init(void)
2412 {
2413         return platform_driver_register(&gpmc_driver);
2414 }
2415 postcore_initcall(gpmc_init);
2416
2417 static struct omap3_gpmc_regs gpmc_context;
2418
2419 void omap3_gpmc_save_context(void)
2420 {
2421         int i;
2422
2423         if (!gpmc_base)
2424                 return;
2425
2426         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2427         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2428         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2429         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2430         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2431         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2432         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2433         for (i = 0; i < gpmc_cs_num; i++) {
2434                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2435                 if (gpmc_context.cs_context[i].is_valid) {
2436                         gpmc_context.cs_context[i].config1 =
2437                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2438                         gpmc_context.cs_context[i].config2 =
2439                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2440                         gpmc_context.cs_context[i].config3 =
2441                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2442                         gpmc_context.cs_context[i].config4 =
2443                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2444                         gpmc_context.cs_context[i].config5 =
2445                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2446                         gpmc_context.cs_context[i].config6 =
2447                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2448                         gpmc_context.cs_context[i].config7 =
2449                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2450                 }
2451         }
2452 }
2453
2454 void omap3_gpmc_restore_context(void)
2455 {
2456         int i;
2457
2458         if (!gpmc_base)
2459                 return;
2460
2461         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2462         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2463         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2464         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2465         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2466         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2467         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2468         for (i = 0; i < gpmc_cs_num; i++) {
2469                 if (gpmc_context.cs_context[i].is_valid) {
2470                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2471                                 gpmc_context.cs_context[i].config1);
2472                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2473                                 gpmc_context.cs_context[i].config2);
2474                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2475                                 gpmc_context.cs_context[i].config3);
2476                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2477                                 gpmc_context.cs_context[i].config4);
2478                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2479                                 gpmc_context.cs_context[i].config5);
2480                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2481                                 gpmc_context.cs_context[i].config6);
2482                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2483                                 gpmc_context.cs_context[i].config7);
2484                 }
2485         }
2486 }