drivers/media/video/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kmod.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <asm/div64.h>
  32
  33 #include "cx23885.h"
  34
  35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
  37 MODULE_LICENSE("GPL");
  38
  39 static unsigned int debug = 0;
  40 module_param(debug,int,0644);
  41 MODULE_PARM_DESC(debug,"enable debug messages");
  42
  43 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  44 module_param_array(card,  int, NULL, 0444);
  45 MODULE_PARM_DESC(card,"card type");
  46
  47 #define dprintk(level,fmt, arg...)      if (debug >= level) \
  48         printk(KERN_DEBUG "%s/0: " fmt, dev->name , ## arg)
  49
  50 static unsigned int cx23885_devcount;
  51
  52 static DEFINE_MUTEX(devlist);
  53 static LIST_HEAD(cx23885_devlist);
  54
  55 #define NO_SYNC_LINE (-1U)
  56
  57 /*
  58  * CX23885 Assumptions
  59  * 1 line = 16 bytes of CDT
  60  * cmds size = 80
  61  * cdt size = 16 * linesize
  62  * iqsize = 64
  63  * maxlines = 6
  64  *
  65  * Address Space:
  66  * 0x00000000 0x00008fff FIFO clusters
  67  * 0x00010000 0x000104af Channel Management Data Structures
  68  * 0x000104b0 0x000104ff Free
  69  * 0x00010500 0x000108bf 15 channels * iqsize
  70  * 0x000108c0 0x000108ff Free
  71  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  72  *                       15 channels * (iqsize + (maxlines * linesize))
  73  * 0x00010ea0 0x00010xxx Free
  74  */
  75
  76 struct sram_channel cx23885_sram_channels[] = {
  77         [SRAM_CH01] = {
  78                 .name           = "test ch1",
  79                 .cmds_start     = 0x10000,
  80                 .ctrl_start     = 0x10500,
  81                 .cdt            = 0x10900,
  82                 .fifo_start     = 0x3000,
  83                 .fifo_size      = 0x1000,
  84                 .ptr1_reg       = DMA1_PTR1,
  85                 .ptr2_reg       = DMA1_PTR2,
  86                 .cnt1_reg       = DMA1_CNT1,
  87                 .cnt2_reg       = DMA1_CNT2,
  88                 .jumponly       = 1,
  89         },
  90         [SRAM_CH02] = {
  91                 .name           = "ch2",
  92                 .cmds_start     = 0x0,
  93                 .ctrl_start     = 0x0,
  94                 .cdt            = 0x0,
  95                 .fifo_start     = 0x0,
  96                 .fifo_size      = 0x0,
  97                 .ptr1_reg       = DMA2_PTR1,
  98                 .ptr2_reg       = DMA2_PTR2,
  99                 .cnt1_reg       = DMA2_CNT1,
 100                 .cnt2_reg       = DMA2_CNT2,
 101         },
 102         [SRAM_CH03] = {
 103                 .name           = "ch3",
 104                 .cmds_start     = 0x0,
 105                 .ctrl_start     = 0x0,
 106                 .cdt            = 0x0,
 107                 .fifo_start     = 0x0,
 108                 .fifo_size      = 0x0,
 109                 .ptr1_reg       = DMA3_PTR1,
 110                 .ptr2_reg       = DMA3_PTR2,
 111                 .cnt1_reg       = DMA3_CNT1,
 112                 .cnt2_reg       = DMA3_CNT2,
 113         },
 114         [SRAM_CH04] = {
 115                 .name           = "ch4",
 116                 .cmds_start     = 0x0,
 117                 .ctrl_start     = 0x0,
 118                 .cdt            = 0x0,
 119                 .fifo_start     = 0x0,
 120                 .fifo_size      = 0x0,
 121                 .ptr1_reg       = DMA4_PTR1,
 122                 .ptr2_reg       = DMA4_PTR2,
 123                 .cnt1_reg       = DMA4_CNT1,
 124                 .cnt2_reg       = DMA4_CNT2,
 125         },
 126         [SRAM_CH05] = {
 127                 .name           = "ch5",
 128                 .cmds_start     = 0x0,
 129                 .ctrl_start     = 0x0,
 130                 .cdt            = 0x0,
 131                 .fifo_start     = 0x0,
 132                 .fifo_size      = 0x0,
 133                 .ptr1_reg       = DMA5_PTR1,
 134                 .ptr2_reg       = DMA5_PTR2,
 135                 .cnt1_reg       = DMA5_CNT1,
 136                 .cnt2_reg       = DMA5_CNT2,
 137         },
 138         [SRAM_CH06] = {
 139                 .name           = "TS2 C",
 140                 .cmds_start     = 0x10140,
 141                 .ctrl_start     = 0x10680,
 142                 .cdt            = 0x10480,
 143                 .fifo_start     = 0x6000,
 144                 .fifo_size      = 0x1000,
 145                 .ptr1_reg       = DMA5_PTR1,
 146                 .ptr2_reg       = DMA5_PTR2,
 147                 .cnt1_reg       = DMA5_CNT1,
 148                 .cnt2_reg       = DMA5_CNT2,
 149         },
 150         [SRAM_CH07] = {
 151                 .name           = "ch7",
 152                 .cmds_start     = 0x0,
 153                 .ctrl_start     = 0x0,
 154                 .cdt            = 0x0,
 155                 .fifo_start     = 0x0,
 156                 .fifo_size      = 0x0,
 157                 .ptr1_reg       = DMA6_PTR1,
 158                 .ptr2_reg       = DMA6_PTR2,
 159                 .cnt1_reg       = DMA6_CNT1,
 160                 .cnt2_reg       = DMA6_CNT2,
 161         },
 162         [SRAM_CH08] = {
 163                 .name           = "ch8",
 164                 .cmds_start     = 0x0,
 165                 .ctrl_start     = 0x0,
 166                 .cdt            = 0x0,
 167                 .fifo_start     = 0x0,
 168                 .fifo_size      = 0x0,
 169                 .ptr1_reg       = DMA7_PTR1,
 170                 .ptr2_reg       = DMA7_PTR2,
 171                 .cnt1_reg       = DMA7_CNT1,
 172                 .cnt2_reg       = DMA7_CNT2,
 173         },
 174         [SRAM_CH09] = {
 175                 .name           = "ch9",
 176                 .cmds_start     = 0x0,
 177                 .ctrl_start     = 0x0,
 178                 .cdt            = 0x0,
 179                 .fifo_start     = 0x0,
 180                 .fifo_size      = 0x0,
 181                 .ptr1_reg       = DMA8_PTR1,
 182                 .ptr2_reg       = DMA8_PTR2,
 183                 .cnt1_reg       = DMA8_CNT1,
 184                 .cnt2_reg       = DMA8_CNT2,
 185         },
 186 };
 187
 188 /* FIXME, these allocations will change when
 189  * analog arrives. The be reviewed.
 190  * CX23887 Assumptions
 191  * 1 line = 16 bytes of CDT
 192  * cmds size = 80
 193  * cdt size = 16 * linesize
 194  * iqsize = 64
 195  * maxlines = 6
 196  *
 197  * Address Space:
 198  * 0x00000000 0x00008fff FIFO clusters
 199  * 0x00010000 0x000104af Channel Management Data Structures
 200  * 0x000104b0 0x000104ff Free
 201  * 0x00010500 0x000108bf 15 channels * iqsize
 202  * 0x000108c0 0x000108ff Free
 203  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
 204  *                       15 channels * (iqsize + (maxlines * linesize))
 205  * 0x00010ea0 0x00010xxx Free
 206  */
 207
 208 struct sram_channel cx23887_sram_channels[] = {
 209         [SRAM_CH01] = {
 210                 .name           = "test ch1",
 211                 .cmds_start     = 0x0,
 212                 .ctrl_start     = 0x0,
 213                 .cdt            = 0x0,
 214                 .fifo_start     = 0x0,
 215                 .fifo_size      = 0x0,
 216                 .ptr1_reg       = DMA1_PTR1,
 217                 .ptr2_reg       = DMA1_PTR2,
 218                 .cnt1_reg       = DMA1_CNT1,
 219                 .cnt2_reg       = DMA1_CNT2,
 220         },
 221         [SRAM_CH02] = {
 222                 .name           = "ch2",
 223                 .cmds_start     = 0x0,
 224                 .ctrl_start     = 0x0,
 225                 .cdt            = 0x0,
 226                 .fifo_start     = 0x0,
 227                 .fifo_size      = 0x0,
 228                 .ptr1_reg       = DMA2_PTR1,
 229                 .ptr2_reg       = DMA2_PTR2,
 230                 .cnt1_reg       = DMA2_CNT1,
 231                 .cnt2_reg       = DMA2_CNT2,
 232         },
 233         [SRAM_CH03] = {
 234                 .name           = "ch3",
 235                 .cmds_start     = 0x0,
 236                 .ctrl_start     = 0x0,
 237                 .cdt            = 0x0,
 238                 .fifo_start     = 0x0,
 239                 .fifo_size      = 0x0,
 240                 .ptr1_reg       = DMA3_PTR1,
 241                 .ptr2_reg       = DMA3_PTR2,
 242                 .cnt1_reg       = DMA3_CNT1,
 243                 .cnt2_reg       = DMA3_CNT2,
 244         },
 245         [SRAM_CH04] = {
 246                 .name           = "ch4",
 247                 .cmds_start     = 0x0,
 248                 .ctrl_start     = 0x0,
 249                 .cdt            = 0x0,
 250                 .fifo_start     = 0x0,
 251                 .fifo_size      = 0x0,
 252                 .ptr1_reg       = DMA4_PTR1,
 253                 .ptr2_reg       = DMA4_PTR2,
 254                 .cnt1_reg       = DMA4_CNT1,
 255                 .cnt2_reg       = DMA4_CNT2,
 256         },
 257         [SRAM_CH05] = {
 258                 .name           = "ch5",
 259                 .cmds_start     = 0x0,
 260                 .ctrl_start     = 0x0,
 261                 .cdt            = 0x0,
 262                 .fifo_start     = 0x0,
 263                 .fifo_size      = 0x0,
 264                 .ptr1_reg       = DMA5_PTR1,
 265                 .ptr2_reg       = DMA5_PTR2,
 266                 .cnt1_reg       = DMA5_CNT1,
 267                 .cnt2_reg       = DMA5_CNT2,
 268         },
 269         [SRAM_CH06] = {
 270                 .name           = "TS2 C",
 271                 .cmds_start     = 0x10140,
 272                 .ctrl_start     = 0x10680,
 273                 .cdt            = 0x108d0,
 274                 .fifo_start     = 0x6000,
 275                 .fifo_size      = 0x1000,
 276                 .ptr1_reg       = DMA5_PTR1,
 277                 .ptr2_reg       = DMA5_PTR2,
 278                 .cnt1_reg       = DMA5_CNT1,
 279                 .cnt2_reg       = DMA5_CNT2,
 280         },
 281         [SRAM_CH07] = {
 282                 .name           = "ch7",
 283                 .cmds_start     = 0x0,
 284                 .ctrl_start     = 0x0,
 285                 .cdt            = 0x0,
 286                 .fifo_start     = 0x0,
 287                 .fifo_size      = 0x0,
 288                 .ptr1_reg       = DMA6_PTR1,
 289                 .ptr2_reg       = DMA6_PTR2,
 290                 .cnt1_reg       = DMA6_CNT1,
 291                 .cnt2_reg       = DMA6_CNT2,
 292         },
 293         [SRAM_CH08] = {
 294                 .name           = "ch8",
 295                 .cmds_start     = 0x0,
 296                 .ctrl_start     = 0x0,
 297                 .cdt            = 0x0,
 298                 .fifo_start     = 0x0,
 299                 .fifo_size      = 0x0,
 300                 .ptr1_reg       = DMA7_PTR1,
 301                 .ptr2_reg       = DMA7_PTR2,
 302                 .cnt1_reg       = DMA7_CNT1,
 303                 .cnt2_reg       = DMA7_CNT2,
 304         },
 305         [SRAM_CH09] = {
 306                 .name           = "ch9",
 307                 .cmds_start     = 0x0,
 308                 .ctrl_start     = 0x0,
 309                 .cdt            = 0x0,
 310                 .fifo_start     = 0x0,
 311                 .fifo_size      = 0x0,
 312                 .ptr1_reg       = DMA8_PTR1,
 313                 .ptr2_reg       = DMA8_PTR2,
 314                 .cnt1_reg       = DMA8_CNT1,
 315                 .cnt2_reg       = DMA8_CNT2,
 316         },
 317 };
 318
 319 static int cx23885_risc_decode(u32 risc)
 320 {
 321         static char *instr[16] = {
 322                 [ RISC_SYNC    >> 28 ] = "sync",
 323                 [ RISC_WRITE   >> 28 ] = "write",
 324                 [ RISC_WRITEC  >> 28 ] = "writec",
 325                 [ RISC_READ    >> 28 ] = "read",
 326                 [ RISC_READC   >> 28 ] = "readc",
 327                 [ RISC_JUMP    >> 28 ] = "jump",
 328                 [ RISC_SKIP    >> 28 ] = "skip",
 329                 [ RISC_WRITERM >> 28 ] = "writerm",
 330                 [ RISC_WRITECM >> 28 ] = "writecm",
 331                 [ RISC_WRITECR >> 28 ] = "writecr",
 332         };
 333         static int incr[16] = {
 334                 [ RISC_WRITE   >> 28 ] = 3, // 2
 335                 [ RISC_JUMP    >> 28 ] = 3, // 2
 336                 [ RISC_SKIP    >> 28 ] = 1,
 337                 [ RISC_SYNC    >> 28 ] = 1,
 338                 [ RISC_WRITERM >> 28 ] = 3,
 339                 [ RISC_WRITECM >> 28 ] = 3,
 340                 [ RISC_WRITECR >> 28 ] = 4,
 341         };
 342         static char *bits[] = {
 343                 "12",   "13",   "14",   "resync",
 344                 "cnt0", "cnt1", "18",   "19",
 345                 "20",   "21",   "22",   "23",
 346                 "irq1", "irq2", "eol",  "sol",
 347         };
 348         int i;
 349
 350         printk("0x%08x [ %s", risc,
 351                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 352         for (i = ARRAY_SIZE(bits)-1; i >= 0; i--)
 353                 if (risc & (1 << (i + 12)))
 354                         printk(" %s",bits[i]);
 355         printk(" count=%d ]\n", risc & 0xfff);
 356         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 357 }
 358
 359 void cx23885_wakeup(struct cx23885_tsport *port,
 360                  struct cx23885_dmaqueue *q, u32 count)
 361 {
 362         struct cx23885_dev *dev = port->dev;
 363         struct cx23885_buffer *buf;
 364         int bc;
 365
 366         for (bc = 0;; bc++) {
 367                 if (list_empty(&q->active))
 368                         break;
 369                 buf = list_entry(q->active.next,
 370                                  struct cx23885_buffer, vb.queue);
 371                 /* count comes from the hw and is is 16bit wide --
 372                  * this trick handles wrap-arounds correctly for
 373                  * up to 32767 buffers in flight... */
 374                 if ((s16) (count - buf->count) < 0)
 375                         break;
 376                 do_gettimeofday(&buf->vb.ts);
 377                 dprintk(2,"[%p/%d] wakeup reg=%d buf=%d\n",buf,buf->vb.i,
 378                         count, buf->count);
 379                 buf->vb.state = STATE_DONE;
 380                 list_del(&buf->vb.queue);
 381                 wake_up(&buf->vb.done);
 382         }
 383         if (list_empty(&q->active)) {
 384                 del_timer(&q->timeout);
 385         } else {
 386                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
 387         }
 388         if (bc != 1)
 389                 printk("%s: %d buffers handled (should be 1)\n",__FUNCTION__,bc);
 390 }
 391 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 392                             struct sram_channel *ch);
 393
 394 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 395                             struct sram_channel *ch,
 396                             unsigned int bpl, u32 risc)
 397 {
 398         unsigned int i,lines;
 399         u32 cdt;
 400
 401         if (ch->cmds_start == 0)
 402         {
 403                 dprintk(1, "%s() Erasing channel [%s]\n",__FUNCTION__, ch->name);
 404                 cx_write(ch->ptr1_reg, 0);
 405                 cx_write(ch->ptr2_reg, 0);
 406                 cx_write(ch->cnt2_reg, 0);
 407                 cx_write(ch->cnt1_reg, 0);
 408                 return 0;
 409         } else {
 410                 dprintk(1, "%s() Configuring channel [%s]\n",__FUNCTION__, ch->name);
 411         }
 412
 413         bpl   = (bpl + 7) & ~7; /* alignment */
 414         cdt   = ch->cdt;
 415         lines = ch->fifo_size / bpl;
 416         if (lines > 6)
 417                 lines = 6;
 418         BUG_ON(lines < 2);
 419
 420         cx_write(8+0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
 421         cx_write(8+4, cpu_to_le32(8) );
 422         cx_write(8+8, cpu_to_le32(0) );
 423
 424         /* write CDT */
 425         for (i = 0; i < lines; i++) {
 426                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __FUNCTION__, cdt + 16*i, ch->fifo_start + bpl*i);
 427                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 428                 cx_write(cdt + 16*i +  4, 0);
 429                 cx_write(cdt + 16*i +  8, 0);
 430                 cx_write(cdt + 16*i + 12, 0);
 431         }
 432
 433         /* write CMDS */
 434         if (ch->jumponly)
 435                 cx_write(ch->cmds_start +  0, 8);
 436         else
 437                 cx_write(ch->cmds_start +  0, risc);
 438         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 439         cx_write(ch->cmds_start +  8, cdt);
 440         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 441         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 442         if (ch->jumponly)
 443                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
 444         else
 445                 cx_write(ch->cmds_start + 20, 64 >> 2);
 446         for (i = 24; i < 80; i += 4)
 447                 cx_write(ch->cmds_start + i, 0);
 448
 449         /* fill registers */
 450         cx_write(ch->ptr1_reg, ch->fifo_start);
 451         cx_write(ch->ptr2_reg, cdt);
 452         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 453         cx_write(ch->cnt1_reg, (bpl >> 3) -1);
 454
 455         dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 456                 dev->bridge,
 457                 ch->name,
 458                 bpl,
 459                 lines);
 460
 461         return 0;
 462 }
 463
 464 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 465                             struct sram_channel *ch)
 466 {
 467         static char *name[] = {
 468                 "init risc lo",
 469                 "init risc hi",
 470                 "cdt base",
 471                 "cdt size",
 472                 "iq base",
 473                 "iq size",
 474                 "risc pc lo",
 475                 "risc pc hi",
 476                 "iq wr ptr",
 477                 "iq rd ptr",
 478                 "cdt current",
 479                 "pci target lo",
 480                 "pci target hi",
 481                 "line / byte",
 482         };
 483         u32 risc;
 484         unsigned int i,j,n;
 485
 486         printk("%s: %s - dma channel status dump\n",
 487                dev->name, ch->name);
 488         for (i = 0; i < ARRAY_SIZE(name); i++)
 489                 printk("%s:   cmds: %-15s: 0x%08x\n",
 490                        dev->name, name[i],
 491                        cx_read(ch->cmds_start + 4*i));
 492
 493         for (i = 0; i < 4; i++) {
 494                 risc = cx_read(ch->cmds_start + 4 * (i+14));
 495                 printk("%s:   risc%d: ", dev->name, i);
 496                 cx23885_risc_decode(risc);
 497         }
 498         for (i = 0; i < (64 >> 2); i += n) {
 499                 risc = cx_read(ch->ctrl_start + 4 * i); /* No consideration for bits 63-32 */
 500                 printk("%s:   (0x%08x) iq %x: ", dev->name, ch->ctrl_start + 4 * i, i);
 501                 n = cx23885_risc_decode(risc);
 502                 for (j = 1; j < n; j++) {
 503                         risc = cx_read(ch->ctrl_start + 4 * (i+j));
 504                         printk("%s:   iq %x: 0x%08x [ arg #%d ]\n",
 505                                dev->name, i+j, risc, j);
 506                 }
 507         }
 508
 509         printk("%s: fifo: 0x%08x -> 0x%x\n",
 510                dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 511         printk("%s: ctrl: 0x%08x -> 0x%x\n",
 512                dev->name, ch->ctrl_start, ch->ctrl_start+6*16);
 513         printk("%s:   ptr1_reg: 0x%08x\n",
 514                dev->name, cx_read(ch->ptr1_reg));
 515         printk("%s:   ptr2_reg: 0x%08x\n",
 516                dev->name, cx_read(ch->ptr2_reg));
 517         printk("%s:   cnt1_reg: 0x%08x\n",
 518                dev->name, cx_read(ch->cnt1_reg));
 519         printk("%s:   cnt2_reg: 0x%08x\n",
 520                dev->name, cx_read(ch->cnt2_reg));
 521 }
 522
 523 void cx23885_risc_disasm(struct cx23885_tsport *port, struct btcx_riscmem *risc)
 524 {
 525         struct cx23885_dev *dev = port->dev;
 526         unsigned int i,j,n;
 527
 528         printk("%s: risc disasm: %p [dma=0x%08lx]\n",
 529                dev->name, risc->cpu, (unsigned long)risc->dma);
 530         for (i = 0; i < (risc->size >> 2); i += n) {
 531                 printk("%s:   %04d: ", dev->name, i);
 532                 n = cx23885_risc_decode(risc->cpu[i]);
 533                 for (j = 1; j < n; j++)
 534                         printk("%s:   %04d: 0x%08x [ arg #%d ]\n",
 535                                dev->name, i+j, risc->cpu[i+j], j);
 536                 if (risc->cpu[i] == RISC_JUMP)
 537                         break;
 538         }
 539 }
 540
 541 void cx23885_shutdown(struct cx23885_dev *dev)
 542 {
 543         /* disable RISC controller */
 544         cx_write(DEV_CNTRL2, 0);
 545
 546         /* Disable all IR activity */
 547         cx_write(IR_CNTRL_REG, 0);
 548
 549         /* Disable Video A/B activity */
 550         cx_write(VID_A_DMA_CTL, 0);
 551         cx_write(VID_B_DMA_CTL, 0);
 552         cx_write(VID_C_DMA_CTL, 0);
 553
 554         /* Disable Audio activity */
 555         cx_write(AUD_INT_DMA_CTL, 0);
 556         cx_write(AUD_EXT_DMA_CTL, 0);
 557
 558         /* Disable Serial port */
 559         cx_write(UART_CTL, 0);
 560
 561         /* Disable Interrupts */
 562         cx_write(PCI_INT_MSK, 0);
 563         cx_write(VID_A_INT_MSK, 0);
 564         cx_write(VID_B_INT_MSK, 0);
 565         cx_write(VID_C_INT_MSK, 0);
 566         cx_write(AUDIO_INT_INT_MSK, 0);
 567         cx_write(AUDIO_EXT_INT_MSK, 0);
 568
 569 }
 570
 571 void cx23885_reset(struct cx23885_dev *dev)
 572 {
 573         dprintk(1, "%s()\n", __FUNCTION__);
 574
 575         cx23885_shutdown(dev);
 576
 577         cx_write(PCI_INT_STAT, 0xffffffff);
 578         cx_write(VID_A_INT_STAT, 0xffffffff);
 579         cx_write(VID_B_INT_STAT, 0xffffffff);
 580         cx_write(VID_C_INT_STAT, 0xffffffff);
 581         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 582         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 583         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 584
 585         mdelay(100);
 586
 587         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH01 ], 188*4, 0);
 588         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH02 ], 128, 0);
 589         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH03 ], 128, 0);
 590         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH04 ], 128, 0);
 591         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH05 ], 128, 0);
 592         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH06 ], 188*4, 0);
 593         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH07 ], 128, 0);
 594         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH08 ], 128, 0);
 595         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH09 ], 128, 0);
 596
 597         switch(dev->board) {
 598         case CX23885_BOARD_HAUPPAUGE_HVR1800:
 599                 /* GPIO-0 656_CLK */
 600                 /* GPIO-1 656_D0 */
 601                 /* GPIO-2 8295A Reset */
 602                 /* GPIO-3-10 cx23417 data0-7 */
 603                 /* GPIO-11-14 cx23417 addr0-3 */
 604                 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
 605                 /* GPIO-19 IR_RX */
 606                 dprintk( 1, "%s() Configuring HVR1800 GPIO's\n", __FUNCTION__);
 607                 // FIXME: Analog requires the tuner is brought out of reset
 608                 break;
 609         }
 610 }
 611
 612
 613 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 614 {
 615         dprintk(1, "%s()\n", __FUNCTION__);
 616
 617         switch(dev->board) {
 618         case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
 619                 cx_clear(RDR_TLCTL0, 1 << 4);
 620                 break;
 621         }
 622         return 0;
 623 }
 624
 625 static int get_resources(struct cx23885_dev *dev)
 626 {
 627         if (request_mem_region(pci_resource_start(dev->pci,0),
 628                                 pci_resource_len(dev->pci,0),
 629                                 dev->name))
 630                 return 0;
 631
 632         printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
 633                 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
 634
 635         return -EBUSY;
 636 }
 637
 638 static void cx23885_timeout(unsigned long data);
 639 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 640                       u32 reg, u32 mask, u32 value);
 641
 642 static int cx23885_ir_init(struct cx23885_dev *dev)
 643 {
 644         dprintk(1, "%s()\n", __FUNCTION__);
 645
 646         switch (dev->board) {
 647         case CX23885_BOARD_HAUPPAUGE_HVR1800:
 648                 dprintk(1, "%s() FIXME - Implement IR support\n", __FUNCTION__);
 649                 break;
 650         }
 651
 652         return 0;
 653 }
 654
 655 static int cx23885_dev_setup(struct cx23885_dev *dev)
 656 {
 657         int i;
 658
 659         mutex_init(&dev->lock);
 660
 661         atomic_inc(&dev->refcount);
 662
 663         dev->nr = cx23885_devcount++;
 664         dev->pci_bus  = dev->pci->bus->number;
 665         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 666         dev->pci_irqmask = 0x001f00;
 667
 668         /* External Master 1 Bus */
 669         dev->i2c_bus[0].nr = 0;
 670         dev->i2c_bus[0].dev = dev;
 671         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 672         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 673         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 674         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 675         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 676         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 677
 678         /* External Master 2 Bus */
 679         dev->i2c_bus[1].nr = 1;
 680         dev->i2c_bus[1].dev = dev;
 681         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 682         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 683         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 684         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 685         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 686         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 687
 688         /* Internal Master 3 Bus */
 689         dev->i2c_bus[2].nr = 2;
 690         dev->i2c_bus[2].dev = dev;
 691         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 692         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 693         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 694         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 695         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 696         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 697
 698         /* Transport bus init dma queue */
 699         spin_lock_init(&dev->ts2.slock);
 700         dev->ts2.dev = dev;
 701         dev->ts2.nr = 2;
 702         dev->ts2.sram_chno = SRAM_CH06;
 703         INIT_LIST_HEAD(&dev->ts2.mpegq.active);
 704         INIT_LIST_HEAD(&dev->ts2.mpegq.queued);
 705         dev->ts2.mpegq.timeout.function = cx23885_timeout;
 706         dev->ts2.mpegq.timeout.data     = (unsigned long)&dev->ts2;
 707         init_timer(&dev->ts2.mpegq.timeout);
 708
 709         dev->ts2.reg_gpcnt = VID_C_GPCNT;
 710         dev->ts2.reg_gpcnt_ctl = VID_C_GPCNT_CTL;
 711         dev->ts2.reg_dma_ctl = VID_C_DMA_CTL;
 712         dev->ts2.reg_lngth = VID_C_LNGTH;
 713         dev->ts2.reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
 714         dev->ts2.reg_gen_ctrl = VID_C_GEN_CTL;
 715         dev->ts2.reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
 716         dev->ts2.reg_sop_status = VID_C_SOP_STATUS;
 717         dev->ts2.reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 718         dev->ts2.reg_vld_misc = VID_C_VLD_MISC;
 719         dev->ts2.reg_ts_clk_en = VID_C_TS_CLK_EN;
 720         dev->ts2.reg_ts_int_msk = VID_C_INT_MSK;
 721
 722         // FIXME: Make this board specific
 723         dev->ts2.pci_irqmask = 0x04; /* TS Port 2 bit */
 724         dev->ts2.dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
 725         dev->ts2.ts_int_msk_val = 0x1111; /* TS port bits for RISC */
 726         dev->ts2.gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
 727         dev->ts2.ts_clk_en_val = 0x1; /* Enable TS_CLK */
 728
 729         cx23885_risc_stopper(dev->pci, &dev->ts2.mpegq.stopper, dev->ts2.reg_dma_ctl, dev->ts2.dma_ctl_val, 0x00);
 730
 731         sprintf(dev->name,"cx23885[%d]", dev->nr);
 732
 733         if (get_resources(dev) < 0) {
 734                 printk(KERN_ERR "CORE %s No more PCIe resources for "
 735                         "subsystem: %04x:%04x\n",
 736                         dev->name, dev->pci->subsystem_vendor,
 737                         dev->pci->subsystem_device);
 738
 739                 cx23885_devcount--;
 740                 goto fail_free;
 741         }
 742
 743         mutex_lock(&devlist);
 744         list_add_tail(&dev->devlist, &cx23885_devlist);
 745         mutex_unlock(&devlist);
 746
 747         /* PCIe stuff */
 748         dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
 749                               pci_resource_len(dev->pci,0));
 750
 751         dev->bmmio = (u8 __iomem *)dev->lmmio;
 752
 753         cx23885_pci_quirks(dev);
 754
 755         /* board config */
 756         dev->board = UNSET;
 757         if (card[dev->nr] < cx23885_bcount)
 758                 dev->board = card[dev->nr];
 759         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 760                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 761                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 762                         dev->board = cx23885_subids[i].card;
 763         if (UNSET == dev->board) {
 764                 dev->board = CX23885_BOARD_UNKNOWN;
 765                 cx23885_card_list(dev);
 766         }
 767         printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 768                 dev->name, dev->pci->subsystem_vendor,
 769                 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 770                 dev->board, card[dev->nr] == dev->board ?
 771                 "insmod option" : "autodetected");
 772
 773         /* Configure the internal memory */
 774         if(dev->pci->device == 0x8880) {
 775                 dev->bridge = CX23885_BRIDGE_887;
 776                 dev->sram_channels = cx23887_sram_channels;
 777         } else
 778         if(dev->pci->device == 0x8852) {
 779                 dev->bridge = CX23885_BRIDGE_885;
 780                 dev->sram_channels = cx23885_sram_channels;
 781         }
 782         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n", __FUNCTION__, dev->bridge);
 783
 784         /* init hardware */
 785         cx23885_reset(dev);
 786
 787         cx23885_i2c_register(&dev->i2c_bus[0]);
 788         cx23885_i2c_register(&dev->i2c_bus[1]);
 789         cx23885_i2c_register(&dev->i2c_bus[2]);
 790         cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
 791
 792         cx23885_card_setup(dev);
 793         cx23885_ir_init(dev);
 794
 795         if (cx23885_dvb_register(&dev->ts2) < 0) {
 796                 printk(KERN_ERR "%s() Failed to register dvb adapters\n", __FUNCTION__);
 797         }
 798
 799         return 0;
 800
 801 fail_free:
 802         kfree(dev);
 803         return -ENODEV;
 804 }
 805
 806 void cx23885_dev_unregister(struct cx23885_dev *dev)
 807 {
 808         release_mem_region(pci_resource_start(dev->pci,0),
 809                            pci_resource_len(dev->pci,0));
 810
 811         if (!atomic_dec_and_test(&dev->refcount))
 812                 return;
 813
 814         cx23885_dvb_unregister(&dev->ts2);
 815         cx23885_i2c_unregister(&dev->i2c_bus[2]);
 816         cx23885_i2c_unregister(&dev->i2c_bus[1]);
 817         cx23885_i2c_unregister(&dev->i2c_bus[0]);
 818
 819         iounmap(dev->lmmio);
 820 }
 821
 822 static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
 823                             unsigned int offset, u32 sync_line,
 824                             unsigned int bpl, unsigned int padding,
 825                             unsigned int lines)
 826 {
 827         struct scatterlist *sg;
 828         unsigned int line,todo;
 829
 830         /* sync instruction */
 831         if (sync_line != NO_SYNC_LINE)
 832                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
 833
 834         /* scan lines */
 835         sg = sglist;
 836         for (line = 0; line < lines; line++) {
 837                 while (offset && offset >= sg_dma_len(sg)) {
 838                         offset -= sg_dma_len(sg);
 839                         sg++;
 840                 }
 841                 if (bpl <= sg_dma_len(sg)-offset) {
 842                         /* fits into current chunk */
 843                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
 844                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 845                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 846                         offset+=bpl;
 847                 } else {
 848                         /* scanline needs to be split */
 849                         todo = bpl;
 850                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
 851                                             (sg_dma_len(sg)-offset));
 852                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 853                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 854                         todo -= (sg_dma_len(sg)-offset);
 855                         offset = 0;
 856                         sg++;
 857                         while (todo > sg_dma_len(sg)) {
 858                                 *(rp++)=cpu_to_le32(RISC_WRITE|
 859                                                     sg_dma_len(sg));
 860                                 *(rp++)=cpu_to_le32(sg_dma_address(sg));
 861                                 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 862                                 todo -= sg_dma_len(sg);
 863                                 sg++;
 864                         }
 865                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
 866                         *(rp++)=cpu_to_le32(sg_dma_address(sg));
 867                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 868                         offset += todo;
 869                 }
 870                 offset += padding;
 871         }
 872
 873         return rp;
 874 }
 875
 876 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 877                      struct scatterlist *sglist,
 878                      unsigned int top_offset, unsigned int bottom_offset,
 879                      unsigned int bpl, unsigned int padding, unsigned int lines)
 880 {
 881         u32 instructions,fields;
 882         u32 *rp;
 883         int rc;
 884
 885         fields = 0;
 886         if (UNSET != top_offset)
 887                 fields++;
 888         if (UNSET != bottom_offset)
 889                 fields++;
 890
 891         /* estimate risc mem: worst case is one write per page border +
 892            one write per scan line + syncs + jump (all 2 dwords).  Padding
 893            can cause next bpl to start close to a page border.  First DMA
 894            region may be smaller than PAGE_SIZE */
 895         /* write and jump need and extra dword */
 896         instructions  = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
 897         instructions += 2;
 898         //if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
 899         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
 900                 return rc;
 901
 902         /* write risc instructions */
 903         rp = risc->cpu;
 904         if (UNSET != top_offset)
 905                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
 906                                      bpl, padding, lines);
 907         if (UNSET != bottom_offset)
 908                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
 909                                      bpl, padding, lines);
 910
 911         /* save pointer to jmp instruction address */
 912         risc->jmp = rp;
 913         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
 914         return 0;
 915 }
 916
 917 int cx23885_risc_databuffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 918                          struct scatterlist *sglist, unsigned int bpl,
 919                          unsigned int lines)
 920 {
 921         u32 instructions;
 922         u32 *rp;
 923         int rc;
 924
 925         /* estimate risc mem: worst case is one write per page border +
 926            one write per scan line + syncs + jump (all 2 dwords).  Here
 927            there is no padding and no sync.  First DMA region may be smaller
 928            than PAGE_SIZE */
 929         /* Jump and write need an extra dword */
 930         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
 931         instructions += 1;
 932
 933         //if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
 934         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
 935                 return rc;
 936
 937         /* write risc instructions */
 938         rp = risc->cpu;
 939         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
 940
 941         /* save pointer to jmp instruction address */
 942         risc->jmp = rp;
 943         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
 944         return 0;
 945 }
 946
 947 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 948                       u32 reg, u32 mask, u32 value)
 949 {
 950         u32 *rp;
 951         int rc;
 952
 953         if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
 954                 return rc;
 955
 956         /* write risc instructions */
 957         rp = risc->cpu;
 958         //*(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2 | RISC_IMM);
 959         *(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2);
 960         *(rp++) = cpu_to_le32(reg);
 961         *(rp++) = cpu_to_le32(value);
 962         *(rp++) = cpu_to_le32(mask);
 963         *(rp++) = cpu_to_le32(RISC_JUMP);
 964         *(rp++) = cpu_to_le32(risc->dma);
 965         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
 966         return 0;
 967 }
 968
 969 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
 970 {
 971         BUG_ON(in_interrupt());
 972         videobuf_waiton(&buf->vb,0,0);
 973         videobuf_dma_unmap(q, &buf->vb.dma);
 974         videobuf_dma_free(&buf->vb.dma);
 975         btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc);
 976         buf->vb.state = STATE_NEEDS_INIT;
 977 }
 978
 979 static int cx23885_start_dma(struct cx23885_tsport *port,
 980                             struct cx23885_dmaqueue *q,
 981                             struct cx23885_buffer   *buf)
 982 {
 983         struct cx23885_dev *dev = port->dev;
 984
 985         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __FUNCTION__,
 986                         buf->vb.width, buf->vb.height, buf->vb.field);
 987
 988         /* setup fifo + format */
 989         cx23885_sram_channel_setup(dev,
 990                 &dev->sram_channels[ port->sram_chno ],
 991                 port->ts_packet_size, buf->risc.dma);
 992         if(debug > 5) {
 993                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
 994                 cx23885_risc_disasm(port, &buf->risc);
 995         }
 996
 997         /* write TS length to chip */
 998         cx_write(port->reg_lngth, buf->vb.width);
 999
1000         if (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) {
1001                 printk( "%s() Failed. Unsupported value in .portc (0x%08x)\n", __FUNCTION__,
1002                         cx23885_boards[dev->board].portc );
1003                 return -EINVAL;
1004         }
1005
1006         // FIXME: review the need for these two lines
1007         dprintk( 1, "%s() doing .dvb\n", __FUNCTION__);
1008         udelay(100);
1009
1010         cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
1011         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1012
1013         // FIXME: review the need for this
1014         cx_write(GPIO2, 0x00);
1015
1016         switch (dev->board) {
1017         case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1018         case CX23885_BOARD_HAUPPAUGE_HVR1800:
1019                 cx_write(port->reg_vld_misc, 0x00);
1020                 dprintk(1, "%s() Configuring HVR1800/lp/1500 board\n", __FUNCTION__);
1021                 break;
1022         default:
1023                 // FIXME
1024                 printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
1025         }
1026
1027         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1028         udelay(100);
1029
1030         /* reset counter to zero */
1031         cx_write(port->reg_gpcnt_ctl, 3);
1032         q->count = 1;
1033
1034         /* A bug in the current 887 implementation, causes an NMI assert during
1035          * starting or stopping interrupts or dma. Avoid the bug for the time being,
1036          * enabling the developer to work on the demod/tuner locking work.
1037          */
1038         switch(dev->bridge) {
1039         case CX23885_BRIDGE_885:
1040         case CX23885_BRIDGE_887:
1041                 /* enable irqs */
1042                 dprintk(1, "%s() enabling TS int's and DMA\n", __FUNCTION__ );
1043                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1044                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1045                 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1046                 break;
1047         default:
1048                 // FIXME: generate a sensible switch-default message
1049                 printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
1050         }
1051
1052         dprintk(1, "%s() Register Dump\n", __FUNCTION__);
1053         dprintk(1, "%s() set port ts_int_msk, now %x\n", __FUNCTION__, cx_read(port->reg_ts_int_msk) );
1054         dprintk(1, "%s() DEV_CNTRL2      0x%08x\n", __FUNCTION__, cx_read(DEV_CNTRL2) );
1055         dprintk(1, "%s() PCI_INT_MSK     0x%08x\n", __FUNCTION__, cx_read(PCI_INT_MSK) );
1056         dprintk(1, "%s() VID_A_INT_MSK   0x%08x\n", __FUNCTION__, cx_read(VID_A_INT_MSK) );
1057         dprintk(1, "%s() VID_B_INT_MSK   0x%08x\n", __FUNCTION__, cx_read(VID_B_INT_MSK) );
1058         dprintk(1, "%s() VID_C_INT_MSK   0x%08x\n", __FUNCTION__, cx_read(VID_C_INT_MSK) );
1059         dprintk(1, "%s() VID_A_DMA_CTL   0x%08x\n", __FUNCTION__, cx_read(VID_A_DMA_CTL) );
1060         dprintk(1, "%s() VID_B_DMA_CTL   0x%08x\n", __FUNCTION__, cx_read(VID_B_DMA_CTL) );
1061         dprintk(1, "%s() VID_C_DMA_CTL   0x%08x\n", __FUNCTION__, cx_read(VID_C_DMA_CTL) );
1062         dprintk(1, "%s() AUD_INT_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(AUDIO_INT_INT_MSK) );
1063         dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(AUD_INT_DMA_CTL) );
1064         dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(AUDIO_EXT_INT_MSK) );
1065         dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(AUD_EXT_DMA_CTL) );
1066
1067         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1068
1069         dprintk(1, "%s() set dev_cntrl2, now %x\n", __FUNCTION__, cx_read(DEV_CNTRL2) );
1070         dprintk(1, "%s() VID_C_DMA_CTL   , now %x\n", __FUNCTION__, cx_read(port->reg_dma_ctl) );
1071         dprintk(1, "%s() VID_C_DMA_CTL   , now %x\n", __FUNCTION__, cx_read(VID_C_DMA_CTL) );
1072         dprintk(1, "%s() PAD_CTRL %x\n", __FUNCTION__, cx_read(PAD_CTRL) );
1073         dprintk(1, "%s() GPIO2 %x\n", __FUNCTION__, cx_read(GPIO2) );
1074         dprintk(1, "%s() VID_C_LN_LNGTH  , now %x\n", __FUNCTION__, cx_read(port->reg_lngth) );
1075         dprintk(1, "%s() VID_C_HW_SOP_CTL, now %x\n", __FUNCTION__, cx_read(port->reg_hw_sop_ctrl) );
1076         dprintk(1, "%s() VID_C_GEN_CTL   , now %x\n", __FUNCTION__, cx_read(port->reg_gen_ctrl) );
1077         dprintk(1, "%s() VID_C_SOP_STATUS, now %x\n", __FUNCTION__, cx_read(VID_C_SOP_STATUS) );
1078         dprintk(1, "%s() VID_C_TS_CLK_EN , now %x\n", __FUNCTION__, cx_read(VID_C_TS_CLK_EN) );
1079         dprintk(1, "%s() VID_C_FIFO_OVLST, now %x\n", __FUNCTION__, cx_read(VID_C_FIFO_OVFL_STAT) );
1080         dprintk(1, "%s() VID_C_INT_MSTAT , now 0x%08x\n", __FUNCTION__, cx_read(VID_C_INT_MSTAT) );
1081         return 0;
1082 }
1083
1084 static int cx23885_stop_dma(struct cx23885_tsport *port)
1085 {
1086         struct cx23885_dev *dev = port->dev;
1087         dprintk(1, "%s()\n", __FUNCTION__);
1088
1089         /* Stop interrupts and DMA */
1090         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1091         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1092
1093         return 0;
1094 }
1095
1096 static int cx23885_restart_queue(struct cx23885_tsport *port,
1097                                 struct cx23885_dmaqueue *q)
1098 {
1099         struct cx23885_dev *dev = port->dev;
1100         struct cx23885_buffer *buf;
1101         struct list_head *item;
1102
1103         dprintk(5, "%s()\n", __FUNCTION__);
1104         if (list_empty(&q->active))
1105         {
1106                struct cx23885_buffer *prev;
1107                prev = NULL;
1108
1109                 dprintk(5, "%s() queue is empty\n", __FUNCTION__);
1110
1111                for (;;) {
1112                        if (list_empty(&q->queued))
1113                                return 0;
1114                        buf = list_entry(q->queued.next, struct cx23885_buffer, vb.queue);
1115                        if (NULL == prev) {
1116                                list_del(&buf->vb.queue);
1117                                list_add_tail(&buf->vb.queue,&q->active);
1118                                cx23885_start_dma(port, q, buf);
1119                                buf->vb.state = STATE_ACTIVE;
1120                                buf->count    = q->count++;
1121                                mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1122                                dprintk(5,"[%p/%d] restart_queue - first active\n",
1123                                        buf,buf->vb.i);
1124
1125                        } else if (prev->vb.width  == buf->vb.width  &&
1126                                   prev->vb.height == buf->vb.height &&
1127                                   prev->fmt       == buf->fmt) {
1128                                list_del(&buf->vb.queue);
1129                                list_add_tail(&buf->vb.queue,&q->active);
1130                                buf->vb.state = STATE_ACTIVE;
1131                                buf->count    = q->count++;
1132                                prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1133                                prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1134                                dprintk(5,"[%p/%d] restart_queue - move to active\n",
1135                                        buf,buf->vb.i);
1136                        } else {
1137                                return 0;
1138                        }
1139                        prev = buf;
1140                }
1141                 return 0;
1142         }
1143
1144         buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1145         dprintk(2,"restart_queue [%p/%d]: restart dma\n",
1146                 buf, buf->vb.i);
1147         cx23885_start_dma(port, q, buf);
1148         list_for_each(item,&q->active) {
1149                 buf = list_entry(item, struct cx23885_buffer, vb.queue);
1150                 buf->count = q->count++;
1151         }
1152         mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1153         return 0;
1154 }
1155
1156 /* ------------------------------------------------------------------ */
1157
1158 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1159                         struct cx23885_buffer *buf, enum v4l2_field field)
1160 {
1161         struct cx23885_dev *dev = port->dev;
1162         int size = port->ts_packet_size * port->ts_packet_count;
1163         int rc;
1164
1165         dprintk(1, "%s: %p\n", __FUNCTION__, buf);
1166         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1167                 return -EINVAL;
1168
1169         if (STATE_NEEDS_INIT == buf->vb.state) {
1170                 buf->vb.width  = port->ts_packet_size;
1171                 buf->vb.height = port->ts_packet_count;
1172                 buf->vb.size   = size;
1173                 buf->vb.field  = field /*V4L2_FIELD_TOP*/;
1174
1175                 if (0 != (rc = videobuf_iolock(q,&buf->vb,NULL)))
1176                         goto fail;
1177                 cx23885_risc_databuffer(dev->pci, &buf->risc,
1178                                      buf->vb.dma.sglist,
1179                                      buf->vb.width, buf->vb.height);
1180         }
1181         buf->vb.state = STATE_PREPARED;
1182         return 0;
1183
1184  fail:
1185         cx23885_free_buffer(q,buf);
1186         return rc;
1187 }
1188
1189 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1190 {
1191         struct cx23885_buffer    *prev;
1192         struct cx23885_dev *dev = port->dev;
1193         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1194
1195         /* add jump to stopper */
1196         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1197         buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1198         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1199
1200         if (list_empty(&cx88q->active)) {
1201                 dprintk( 1, "queue is empty - first active\n" );
1202                 list_add_tail(&buf->vb.queue,&cx88q->active);
1203                 cx23885_start_dma(port, cx88q, buf);
1204                 buf->vb.state = STATE_ACTIVE;
1205                 buf->count    = cx88q->count++;
1206                 mod_timer(&cx88q->timeout, jiffies+BUFFER_TIMEOUT);
1207                 dprintk(1,"[%p/%d] %s - first active\n",
1208                         buf, buf->vb.i, __FUNCTION__);
1209
1210         } else {
1211                 dprintk( 1, "queue is not empty - append to active\n" );
1212                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer, vb.queue);
1213                 list_add_tail(&buf->vb.queue,&cx88q->active);
1214                 buf->vb.state = STATE_ACTIVE;
1215                 buf->count    = cx88q->count++;
1216                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1217                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1218                 dprintk( 1, "[%p/%d] %s - append to active\n",
1219                         buf, buf->vb.i, __FUNCTION__);
1220         }
1221 }
1222
1223 /* ----------------------------------------------------------- */
1224
1225 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason, int restart)
1226 {
1227         struct cx23885_dev *dev = port->dev;
1228         struct cx23885_dmaqueue *q = &port->mpegq;
1229         struct cx23885_buffer *buf;
1230         unsigned long flags;
1231
1232         spin_lock_irqsave(&port->slock,flags);
1233         while (!list_empty(&q->active)) {
1234                 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1235                 list_del(&buf->vb.queue);
1236                 buf->vb.state = STATE_ERROR;
1237                 wake_up(&buf->vb.done);
1238                 dprintk(1,"[%p/%d] %s - dma=0x%08lx\n",
1239                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1240         }
1241         if (restart)
1242         {
1243                 dprintk(1, "restarting queue\n" );
1244                 cx23885_restart_queue(port, q);
1245         }
1246         spin_unlock_irqrestore(&port->slock,flags);
1247 }
1248
1249 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1250 {
1251         struct cx23885_dev *dev = port->dev;
1252         struct cx23885_dmaqueue *q = &port->mpegq;
1253
1254         dprintk(1, "%s()\n", __FUNCTION__ );
1255         del_timer_sync(&q->timeout);
1256         cx23885_stop_dma(port);
1257         do_cancel_buffers(port, "cancel", 0);
1258 }
1259
1260 static void cx23885_timeout(unsigned long data)
1261 {
1262         struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1263         struct cx23885_dev *dev = port->dev;
1264
1265         dprintk(1, "%s()\n",__FUNCTION__);
1266
1267         if (debug > 5)
1268                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1269
1270         cx23885_stop_dma(port);
1271         do_cancel_buffers(port, "timeout", 1);
1272 }
1273
1274 #define PCI_MSK_APB_DMA   (1 << 12)
1275 #define PCI_MSK_AL_WR     (1 << 11)
1276 #define PCI_MSK_AL_RD     (1 << 10)
1277 #define PCI_MSK_RISC_WR   (1 <<  9)
1278 #define PCI_MSK_RISC_RD   (1 <<  8)
1279
1280 #define PCI_MSK_AUD_EXT   (1 <<  4)
1281 #define PCI_MSK_AUD_INT   (1 <<  3)
1282 #define PCI_MSK_VID_C     (1 <<  2)
1283 #define PCI_MSK_VID_B     (1 <<  1)
1284 #define PCI_MSK_VID_A      1
1285
1286 #define VID_C_MSK_BAD_PKT (1 << 20)
1287 #define VID_C_MSK_OPC_ERR (1 << 16)
1288 #define VID_C_MSK_SYNC    (1 << 12)
1289 #define VID_C_MSK_OF      (1 <<  8)
1290 #define VID_C_MSK_RISCI2  (1 <<  4)
1291 #define VID_C_MSK_RISCI1   1
1292
1293 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1294 {
1295         struct cx23885_dev *dev = dev_id;
1296         struct cx23885_tsport *port = &dev->ts2;
1297         u32 pci_status, pci_mask;
1298         u32 ts2_status, ts2_mask;
1299         int count = 0, handled = 0;
1300
1301         pci_status = cx_read(PCI_INT_STAT);
1302         pci_mask = cx_read(PCI_INT_MSK);
1303
1304         ts2_status = cx_read(VID_C_INT_STAT);
1305         ts2_mask = cx_read(VID_C_INT_MSK);
1306
1307         if ( (pci_status == 0) && (ts2_status == 0) )
1308                 goto out;
1309
1310         count = cx_read(port->reg_gpcnt);
1311         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n", pci_status, pci_mask );
1312         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n", ts2_status, ts2_mask, count );
1313
1314         if ( (pci_status & PCI_MSK_RISC_RD) ||
1315                 (pci_status & PCI_MSK_RISC_WR) ||
1316                 (pci_status & PCI_MSK_AL_RD) ||
1317                 (pci_status & PCI_MSK_AL_WR) ||
1318                 (pci_status & PCI_MSK_APB_DMA) ||
1319                 (pci_status & PCI_MSK_VID_C) ||
1320                 (pci_status & PCI_MSK_VID_B) ||
1321                 (pci_status & PCI_MSK_VID_A) ||
1322                 (pci_status & PCI_MSK_AUD_INT) ||
1323                 (pci_status & PCI_MSK_AUD_EXT) )
1324         {
1325
1326                 if (pci_status & PCI_MSK_RISC_RD)
1327                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n", PCI_MSK_RISC_RD);
1328                 if (pci_status & PCI_MSK_RISC_WR)
1329                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n", PCI_MSK_RISC_WR);
1330                 if (pci_status & PCI_MSK_AL_RD)
1331                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n", PCI_MSK_AL_RD);
1332                 if (pci_status & PCI_MSK_AL_WR)
1333                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n", PCI_MSK_AL_WR);
1334                 if (pci_status & PCI_MSK_APB_DMA)
1335                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n", PCI_MSK_APB_DMA);
1336                 if (pci_status & PCI_MSK_VID_C)
1337                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n", PCI_MSK_VID_C);
1338                 if (pci_status & PCI_MSK_VID_B)
1339                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n", PCI_MSK_VID_B);
1340                 if (pci_status & PCI_MSK_VID_A)
1341                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n", PCI_MSK_VID_A);
1342                 if (pci_status & PCI_MSK_AUD_INT)
1343                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n", PCI_MSK_AUD_INT);
1344                 if (pci_status & PCI_MSK_AUD_EXT)
1345                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n", PCI_MSK_AUD_EXT);
1346
1347         }
1348
1349         if ( (ts2_status & VID_C_MSK_OPC_ERR) ||
1350                 (ts2_status & VID_C_MSK_BAD_PKT) ||
1351                 (ts2_status & VID_C_MSK_SYNC) ||
1352                 (ts2_status & VID_C_MSK_OF))
1353         {
1354                 if (ts2_status & VID_C_MSK_OPC_ERR)
1355                         dprintk(7, " (VID_C_MSK_OPC_ERR 0x%08x)\n", VID_C_MSK_OPC_ERR);
1356                 if (ts2_status & VID_C_MSK_BAD_PKT)
1357                         dprintk(7, " (VID_C_MSK_BAD_PKT 0x%08x)\n", VID_C_MSK_BAD_PKT);
1358                 if (ts2_status & VID_C_MSK_SYNC)
1359                         dprintk(7, " (VID_C_MSK_SYNC    0x%08x)\n", VID_C_MSK_SYNC);
1360                 if (ts2_status & VID_C_MSK_OF)
1361                         dprintk(7, " (VID_C_MSK_OF      0x%08x)\n", VID_C_MSK_OF);
1362
1363                 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1364
1365                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1366                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1367
1368         } else if (ts2_status & VID_C_MSK_RISCI1) {
1369
1370                 dprintk(7, " (RISCI1            0x%08x)\n", VID_C_MSK_RISCI1);
1371
1372                 spin_lock(&port->slock);
1373                 count = cx_read(port->reg_gpcnt);
1374                 cx23885_wakeup(port, &port->mpegq, count);
1375                 spin_unlock(&port->slock);
1376
1377         } else if (ts2_status & VID_C_MSK_RISCI2) {
1378
1379                 dprintk(7, " (RISCI2            0x%08x)\n", VID_C_MSK_RISCI2);
1380
1381                 spin_lock(&port->slock);
1382                 cx23885_restart_queue(port, &port->mpegq);
1383                 spin_unlock(&port->slock);
1384
1385         }
1386
1387         cx_write(VID_C_INT_STAT, ts2_status);
1388         cx_write(PCI_INT_STAT, pci_status);
1389         handled = 1;
1390 out:
1391         return IRQ_RETVAL(handled);
1392 }
1393
1394 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1395                                     const struct pci_device_id *pci_id)
1396 {
1397         struct cx23885_dev *dev;
1398         int err;
1399
1400         dev = kzalloc(sizeof(*dev),GFP_KERNEL);
1401         if (NULL == dev)
1402                 return -ENOMEM;
1403
1404         /* pci init */
1405         dev->pci = pci_dev;
1406         if (pci_enable_device(pci_dev)) {
1407                 err = -EIO;
1408                 goto fail_free;
1409         }
1410
1411         if (cx23885_dev_setup(dev) < 0) {
1412                 err = -EINVAL;
1413                 goto fail_free;
1414         }
1415
1416         /* print pci info */
1417         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1418         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
1419         printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1420                "latency: %d, mmio: 0x%llx\n", dev->name,
1421                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1422                dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0));
1423
1424         pci_set_master(pci_dev);
1425         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1426                 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1427                 err = -EIO;
1428                 goto fail_irq;
1429         }
1430
1431         err = request_irq(pci_dev->irq, cx23885_irq
1432                         , IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1433         if (err < 0) {
1434                 printk(KERN_ERR "%s: can't get IRQ %d\n",
1435                        dev->name, pci_dev->irq);
1436                 goto fail_irq;
1437         }
1438
1439         pci_set_drvdata(pci_dev, dev);
1440         return 0;
1441
1442 fail_irq:
1443         cx23885_dev_unregister(dev);
1444 fail_free:
1445         kfree(dev);
1446         return err;
1447 }
1448
1449 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1450 {
1451         struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1452
1453         cx23885_shutdown(dev);
1454
1455         pci_disable_device(pci_dev);
1456
1457         /* unregister stuff */
1458         free_irq(pci_dev->irq, dev);
1459         pci_set_drvdata(pci_dev, NULL);
1460
1461         mutex_lock(&devlist);
1462         list_del(&dev->devlist);
1463         mutex_unlock(&devlist);
1464
1465         cx23885_dev_unregister(dev);
1466         kfree(dev);
1467 }
1468
1469 static struct pci_device_id cx23885_pci_tbl[] = {
1470         {
1471                 /* CX23885 */
1472                 .vendor       = 0x14f1,
1473                 .device       = 0x8852,
1474                 .subvendor    = PCI_ANY_ID,
1475                 .subdevice    = PCI_ANY_ID,
1476         },{
1477                 /* CX23887 Rev 2 */
1478                 .vendor       = 0x14f1,
1479                 .device       = 0x8880,
1480                 .subvendor    = PCI_ANY_ID,
1481                 .subdevice    = PCI_ANY_ID,
1482         },{
1483                 /* --- end of list --- */
1484         }
1485 };
1486 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1487
1488 static struct pci_driver cx23885_pci_driver = {
1489         .name     = "cx23885",
1490         .id_table = cx23885_pci_tbl,
1491         .probe    = cx23885_initdev,
1492         .remove   = __devexit_p(cx23885_finidev),
1493         /* TODO */
1494         .suspend  = NULL,
1495         .resume   = NULL,
1496 };
1497
1498 static int cx23885_init(void)
1499 {
1500         printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1501                (CX23885_VERSION_CODE >> 16) & 0xff,
1502                (CX23885_VERSION_CODE >>  8) & 0xff,
1503                CX23885_VERSION_CODE & 0xff);
1504 #ifdef SNAPSHOT
1505         printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1506                SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1507 #endif
1508         return pci_register_driver(&cx23885_pci_driver);
1509 }
1510
1511 static void cx23885_fini(void)
1512 {
1513         pci_unregister_driver(&cx23885_pci_driver);
1514 }
1515
1516 module_init(cx23885_init);
1517 module_exit(cx23885_fini);
1518
1519 /* ----------------------------------------------------------- */
1520 /*
1521  * Local variables:
1522  * c-basic-offset: 8
1523  * End:
1524  * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1525  */