drivers/isdn/hisax/hfc4s8s_l1.c

   1 /*************************************************************************/
   2 /* $Id: hfc4s8s_l1.c,v 1.10 2005/02/09 16:31:09 martinb1 Exp $           */
   3 /* HFC-4S/8S low layer interface for Cologne Chip HFC-4S/8S isdn chips   */
   4 /* The low layer (L1) is implemented as a loadable module for usage with */
   5 /* the HiSax isdn driver for passive cards.                              */
   6 /*                                                                       */
   7 /* Author: Werner Cornelius                                              */
   8 /* (C) 2003 Cornelius Consult (werner@cornelius-consult.de)              */
   9 /*                                                                       */
  10 /* Driver maintained by Cologne Chip                                     */
  11 /*   - Martin Bachem, support@colognechip.com                            */
  12 /*                                                                       */
  13 /* This driver only works with chip revisions >= 1, older revision 0     */
  14 /* engineering samples (only first manufacturer sample cards) will not   */
  15 /* work and are rejected by the driver.                                  */
  16 /*                                                                       */
  17 /* This file distributed under the GNU GPL.                              */
  18 /*                                                                       */
  19 /* See Version History at the end of this file                           */
  20 /*                                                                       */
  21 /*************************************************************************/
  22
  23 #include <linux/module.h>
  24 #include <linux/init.h>
  25 #include <linux/config.h>
  26 #include <linux/pci.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <linux/timer.h>
  30 #include <linux/skbuff.h>
  31 #include <linux/wait.h>
  32 #include <asm/io.h>
  33 #include "hisax_if.h"
  34 #include "hfc4s8s_l1.h"
  35
  36 static const char hfc4s8s_rev[] = "Revision: 1.10";
  37
  38 /***************************************************************/
  39 /* adjustable transparent mode fifo threshold                  */
  40 /* The value defines the used fifo threshold with the equation */
  41 /*                                                             */
  42 /* notify number of bytes = 2 * 2 ^ TRANS_FIFO_THRES           */
  43 /*                                                             */
  44 /* The default value is 5 which results in a buffer size of 64 */
  45 /* and an interrupt rate of 8ms.                               */
  46 /* The maximum value is 7 due to fifo size restrictions.       */
  47 /* Values below 3-4 are not recommended due to high interrupt  */
  48 /* load of the processor. For non critical applications the    */
  49 /* value should be raised to 7 to reduce any interrupt overhead*/
  50 /***************************************************************/
  51 #define TRANS_FIFO_THRES 5
  52
  53 /*************/
  54 /* constants */
  55 /*************/
  56 #define CLOCKMODE_0     0       /* ext. 24.576 MhZ clk freq, int. single clock mode */
  57 #define CLOCKMODE_1     1       /* ext. 49.576 MhZ clk freq, int. single clock mode */
  58 #define CHIP_ID_SHIFT   4
  59 #define HFC_MAX_ST 8
  60 #define MAX_D_FRAME_SIZE 270
  61 #define MAX_B_FRAME_SIZE 1536
  62 #define TRANS_TIMER_MODE (TRANS_FIFO_THRES & 0xf)
  63 #define TRANS_FIFO_BYTES (2 << TRANS_FIFO_THRES)
  64 #define MAX_F_CNT 0x0f
  65
  66 #define CLKDEL_NT 0x6c
  67 #define CLKDEL_TE 0xf
  68 #define CTRL0_NT  4
  69 #define CTRL0_TE  0
  70
  71 #define L1_TIMER_T4 2           /* minimum in jiffies */
  72 #define L1_TIMER_T3 (7 * HZ)    /* activation timeout */
  73 #define L1_TIMER_T1 ((120 * HZ) / 1000) /* NT mode deactivation timeout */
  74
  75
  76 /******************/
  77 /* types and vars */
  78 /******************/
  79 static int card_cnt;
  80
  81 /* private driver_data */
  82 typedef struct {
  83         int chip_id;
  84         int clock_mode;
  85         int max_st_ports;
  86         char *device_name;
  87 } hfc4s8s_param;
  88
  89 static struct pci_device_id hfc4s8s_ids[] = {
  90         {.vendor = PCI_VENDOR_ID_CCD,
  91          .device = PCI_DEVICE_ID_4S,
  92          .subvendor = 0x1397,
  93          .subdevice = 0x08b4,
  94          .driver_data =
  95          (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_0, 4,
  96                                             "HFC-4S Evaluation Board"}),
  97          },
  98         {.vendor = PCI_VENDOR_ID_CCD,
  99          .device = PCI_DEVICE_ID_8S,
 100          .subvendor = 0x1397,
 101          .subdevice = 0x16b8,
 102          .driver_data =
 103          (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_0, 8,
 104                                             "HFC-8S Evaluation Board"}),
 105          },
 106         {.vendor = PCI_VENDOR_ID_CCD,
 107          .device = PCI_DEVICE_ID_4S,
 108          .subvendor = 0x1397,
 109          .subdevice = 0xb520,
 110          .driver_data =
 111          (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_1, 4,
 112                                             "IOB4ST"}),
 113          },
 114         {.vendor = PCI_VENDOR_ID_CCD,
 115          .device = PCI_DEVICE_ID_8S,
 116          .subvendor = 0x1397,
 117          .subdevice = 0xb522,
 118          .driver_data =
 119          (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_1, 8,
 120                                             "IOB8ST"}),
 121          },
 122         {}
 123 };
 124
 125 MODULE_DEVICE_TABLE(pci, hfc4s8s_ids);
 126
 127 MODULE_AUTHOR("Werner Cornelius, werner@cornelius-consult.de");
 128 MODULE_DESCRIPTION("ISDN layer 1 for Cologne Chip HFC-4S/8S chips");
 129 MODULE_LICENSE("GPL");
 130
 131 /***********/
 132 /* layer 1 */
 133 /***********/
 134 struct hfc4s8s_btype {
 135         spinlock_t lock;
 136         struct hisax_b_if b_if;
 137         struct hfc4s8s_l1 *l1p;
 138         struct sk_buff_head tx_queue;
 139         struct sk_buff *tx_skb;
 140         struct sk_buff *rx_skb;
 141         __u8 *rx_ptr;
 142         int tx_cnt;
 143         int bchan;
 144         int mode;
 145 };
 146
 147 struct _hfc4s8s_hw;
 148
 149 struct hfc4s8s_l1 {
 150         spinlock_t lock;
 151         struct _hfc4s8s_hw *hw; /* pointer to hardware area */
 152         int l1_state;           /* actual l1 state */
 153         struct timer_list l1_timer;     /* layer 1 timer structure */
 154         int nt_mode;            /* set to nt mode */
 155         int st_num;             /* own index */
 156         int enabled;            /* interface is enabled */
 157         struct sk_buff_head d_tx_queue; /* send queue */
 158         int tx_cnt;             /* bytes to send */
 159         struct hisax_d_if d_if; /* D-channel interface */
 160         struct hfc4s8s_btype b_ch[2];   /* B-channel data */
 161         struct hisax_b_if *b_table[2];
 162 };
 163
 164 /**********************/
 165 /* hardware structure */
 166 /**********************/
 167 typedef struct _hfc4s8s_hw {
 168         spinlock_t lock;
 169
 170         int cardnum;
 171         int ifnum;
 172         int iobase;
 173         int nt_mode;
 174         u_char *membase;
 175         u_char *hw_membase;
 176         void *pdev;
 177         int max_fifo;
 178         hfc4s8s_param driver_data;
 179         int irq;
 180         int fifo_sched_cnt;
 181         struct work_struct tqueue;
 182         struct hfc4s8s_l1 l1[HFC_MAX_ST];
 183         char card_name[60];
 184         struct {
 185                 u_char r_irq_ctrl;
 186                 u_char r_ctrl0;
 187                 volatile u_char r_irq_statech;  /* active isdn l1 status */
 188                 u_char r_irqmsk_statchg;        /* enabled isdn status ints */
 189                 u_char r_irq_fifo_blx[8];       /* fifo status registers */
 190                 u_char fifo_rx_trans_enables[8];        /* mask for enabled transparent rx fifos */
 191                 u_char fifo_slow_timer_service[8];      /* mask for fifos needing slower timer service */
 192                 volatile u_char r_irq_oview;    /* contents of overview register */
 193                 volatile u_char timer_irq;
 194                 int timer_usg_cnt;      /* number of channels using timer */
 195         } mr;
 196 } hfc4s8s_hw;
 197
 198
 199
 200 /***************************/
 201 /* inline function defines */
 202 /***************************/
 203 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM      /* inline functions mempry mapped */
 204
 205 /* memory write and dummy IO read to avoid PCI byte merge problems */
 206 #define Write_hfc8(a,b,c) {(*((volatile u_char *)(a->membase+b)) = c); inb(a->iobase+4);}
 207 /* memory write without dummy IO access for fifo data access */
 208 #define fWrite_hfc8(a,b,c) (*((volatile u_char *)(a->membase+b)) = c)
 209 #define Read_hfc8(a,b) (*((volatile u_char *)(a->membase+b)))
 210 #define Write_hfc16(a,b,c) (*((volatile unsigned short *)(a->membase+b)) = c)
 211 #define Read_hfc16(a,b) (*((volatile unsigned short *)(a->membase+b)))
 212 #define Write_hfc32(a,b,c) (*((volatile unsigned long *)(a->membase+b)) = c)
 213 #define Read_hfc32(a,b) (*((volatile unsigned long *)(a->membase+b)))
 214 #define wait_busy(a) {while ((Read_hfc8(a, R_STATUS) & M_BUSY));}
 215 #define PCI_ENA_MEMIO   0x03
 216
 217 #else
 218
 219 /* inline functions io mapped */
 220 static inline void
 221 SetRegAddr(hfc4s8s_hw * a, u_char b)
 222 {
 223         outb(b, (a->iobase) + 4);
 224 }
 225
 226 static inline u_char
 227 GetRegAddr(hfc4s8s_hw * a)
 228 {
 229         return (inb((volatile u_int) (a->iobase + 4)));
 230 }
 231
 232
 233 static inline void
 234 Write_hfc8(hfc4s8s_hw * a, u_char b, u_char c)
 235 {
 236         SetRegAddr(a, b);
 237         outb(c, a->iobase);
 238 }
 239
 240 static inline void
 241 fWrite_hfc8(hfc4s8s_hw * a, u_char c)
 242 {
 243         outb(c, a->iobase);
 244 }
 245
 246 static inline void
 247 Write_hfc16(hfc4s8s_hw * a, u_char b, u_short c)
 248 {
 249         SetRegAddr(a, b);
 250         outw(c, a->iobase);
 251 }
 252
 253 static inline void
 254 Write_hfc32(hfc4s8s_hw * a, u_char b, u_long c)
 255 {
 256         SetRegAddr(a, b);
 257         outl(c, a->iobase);
 258 }
 259
 260 static inline void
 261 fWrite_hfc32(hfc4s8s_hw * a, u_long c)
 262 {
 263         outl(c, a->iobase);
 264 }
 265
 266 static inline u_char
 267 Read_hfc8(hfc4s8s_hw * a, u_char b)
 268 {
 269         SetRegAddr(a, b);
 270         return (inb((volatile u_int) a->iobase));
 271 }
 272
 273 static inline u_char
 274 fRead_hfc8(hfc4s8s_hw * a)
 275 {
 276         return (inb((volatile u_int) a->iobase));
 277 }
 278
 279
 280 static inline u_short
 281 Read_hfc16(hfc4s8s_hw * a, u_char b)
 282 {
 283         SetRegAddr(a, b);
 284         return (inw((volatile u_int) a->iobase));
 285 }
 286
 287 static inline u_long
 288 Read_hfc32(hfc4s8s_hw * a, u_char b)
 289 {
 290         SetRegAddr(a, b);
 291         return (inl((volatile u_int) a->iobase));
 292 }
 293
 294 static inline u_long
 295 fRead_hfc32(hfc4s8s_hw * a)
 296 {
 297         return (inl((volatile u_int) a->iobase));
 298 }
 299
 300 static inline void
 301 wait_busy(hfc4s8s_hw * a)
 302 {
 303         SetRegAddr(a, R_STATUS);
 304         while (inb((volatile u_int) a->iobase) & M_BUSY);
 305 }
 306
 307 #define PCI_ENA_REGIO   0x01
 308
 309 #endif                          /* CONFIG_HISAX_HFC4S8S_PCIMEM */
 310
 311 /******************************************************/
 312 /* function to read critical counter registers that   */
 313 /* may be udpated by the chip during read             */
 314 /******************************************************/
 315 static u_char
 316 Read_hfc8_stable(hfc4s8s_hw * hw, int reg)
 317 {
 318         u_char ref8;
 319         u_char in8;
 320         ref8 = Read_hfc8(hw, reg);
 321         while (((in8 = Read_hfc8(hw, reg)) != ref8)) {
 322                 ref8 = in8;
 323         }
 324         return in8;
 325 }
 326
 327 static int
 328 Read_hfc16_stable(hfc4s8s_hw * hw, int reg)
 329 {
 330         int ref16;
 331         int in16;
 332
 333         ref16 = Read_hfc16(hw, reg);
 334         while (((in16 = Read_hfc16(hw, reg)) != ref16)) {
 335                 ref16 = in16;
 336         }
 337         return in16;
 338 }
 339
 340 /*****************************/
 341 /* D-channel call from HiSax */
 342 /*****************************/
 343 static void
 344 dch_l2l1(struct hisax_d_if *iface, int pr, void *arg)
 345 {
 346         struct hfc4s8s_l1 *l1 = iface->ifc.priv;
 347         struct sk_buff *skb = (struct sk_buff *) arg;
 348         u_long flags;
 349
 350         switch (pr) {
 351
 352                 case (PH_DATA | REQUEST):
 353                         if (!l1->enabled) {
 354                                 dev_kfree_skb(skb);
 355                                 break;
 356                         }
 357                         spin_lock_irqsave(&l1->lock, flags);
 358                         skb_queue_tail(&l1->d_tx_queue, skb);
 359                         if ((skb_queue_len(&l1->d_tx_queue) == 1) &&
 360                             (l1->tx_cnt <= 0)) {
 361                                 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
 362                                     0x10;
 363                                 spin_unlock_irqrestore(&l1->lock, flags);
 364                                 schedule_work(&l1->hw->tqueue);
 365                         } else
 366                                 spin_unlock_irqrestore(&l1->lock, flags);
 367                         break;
 368
 369                 case (PH_ACTIVATE | REQUEST):
 370                         if (!l1->enabled)
 371                                 break;
 372                         if (!l1->nt_mode) {
 373                                 if (l1->l1_state < 6) {
 374                                         spin_lock_irqsave(&l1->lock,
 375                                                           flags);
 376
 377                                         Write_hfc8(l1->hw, R_ST_SEL,
 378                                                    l1->st_num);
 379                                         Write_hfc8(l1->hw, A_ST_WR_STA,
 380                                                    0x60);
 381                                         mod_timer(&l1->l1_timer,
 382                                                   jiffies + L1_TIMER_T3);
 383                                         spin_unlock_irqrestore(&l1->lock,
 384                                                                flags);
 385                                 } else if (l1->l1_state == 7)
 386                                         l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 387                                                           PH_ACTIVATE |
 388                                                           INDICATION,
 389                                                           NULL);
 390                         } else {
 391                                 if (l1->l1_state != 3) {
 392                                         spin_lock_irqsave(&l1->lock,
 393                                                           flags);
 394                                         Write_hfc8(l1->hw, R_ST_SEL,
 395                                                    l1->st_num);
 396                                         Write_hfc8(l1->hw, A_ST_WR_STA,
 397                                                    0x60);
 398                                         spin_unlock_irqrestore(&l1->lock,
 399                                                                flags);
 400                                 } else if (l1->l1_state == 3)
 401                                         l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 402                                                           PH_ACTIVATE |
 403                                                           INDICATION,
 404                                                           NULL);
 405                         }
 406                         break;
 407
 408                 default:
 409                         printk(KERN_INFO
 410                                "HFC-4S/8S: Unknown D-chan cmd 0x%x received, ignored\n",
 411                                pr);
 412                         break;
 413         }
 414         if (!l1->enabled)
 415                 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 416                                   PH_DEACTIVATE | INDICATION, NULL);
 417 }                               /* dch_l2l1 */
 418
 419 /*****************************/
 420 /* B-channel call from HiSax */
 421 /*****************************/
 422 static void
 423 bch_l2l1(struct hisax_if *ifc, int pr, void *arg)
 424 {
 425         struct hfc4s8s_btype *bch = ifc->priv;
 426         struct hfc4s8s_l1 *l1 = bch->l1p;
 427         struct sk_buff *skb = (struct sk_buff *) arg;
 428         int mode = (int) arg;
 429         u_long flags;
 430
 431         switch (pr) {
 432
 433                 case (PH_DATA | REQUEST):
 434                         if (!l1->enabled || (bch->mode == L1_MODE_NULL)) {
 435                                 dev_kfree_skb(skb);
 436                                 break;
 437                         }
 438                         spin_lock_irqsave(&l1->lock, flags);
 439                         skb_queue_tail(&bch->tx_queue, skb);
 440                         if (!bch->tx_skb && (bch->tx_cnt <= 0)) {
 441                                 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
 442                                     ((bch->bchan == 1) ? 1 : 4);
 443                                 spin_unlock_irqrestore(&l1->lock, flags);
 444                                 schedule_work(&l1->hw->tqueue);
 445                         } else
 446                                 spin_unlock_irqrestore(&l1->lock, flags);
 447                         break;
 448
 449                 case (PH_ACTIVATE | REQUEST):
 450                 case (PH_DEACTIVATE | REQUEST):
 451                         if (!l1->enabled)
 452                                 break;
 453                         if (pr == (PH_DEACTIVATE | REQUEST))
 454                                 mode = L1_MODE_NULL;
 455
 456                         switch (mode) {
 457                                 case L1_MODE_HDLC:
 458                                         spin_lock_irqsave(&l1->lock,
 459                                                           flags);
 460                                         l1->hw->mr.timer_usg_cnt++;
 461                                         l1->hw->mr.
 462                                             fifo_slow_timer_service[l1->
 463                                                                     st_num]
 464                                             |=
 465                                             ((bch->bchan ==
 466                                               1) ? 0x2 : 0x8);
 467                                         Write_hfc8(l1->hw, R_FIFO,
 468                                                    (l1->st_num * 8 +
 469                                                     ((bch->bchan ==
 470                                                       1) ? 0 : 2)));
 471                                         wait_busy(l1->hw);
 472                                         Write_hfc8(l1->hw, A_CON_HDLC, 0xc);    /* HDLC mode, flag fill, connect ST */
 473                                         Write_hfc8(l1->hw, A_SUBCH_CFG, 0);     /* 8 bits */
 474                                         Write_hfc8(l1->hw, A_IRQ_MSK, 1);       /* enable TX interrupts for hdlc */
 475                                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 476                                         wait_busy(l1->hw);
 477
 478                                         Write_hfc8(l1->hw, R_FIFO,
 479                                                    (l1->st_num * 8 +
 480                                                     ((bch->bchan ==
 481                                                       1) ? 1 : 3)));
 482                                         wait_busy(l1->hw);
 483                                         Write_hfc8(l1->hw, A_CON_HDLC, 0xc);    /* HDLC mode, flag fill, connect ST */
 484                                         Write_hfc8(l1->hw, A_SUBCH_CFG, 0);     /* 8 bits */
 485                                         Write_hfc8(l1->hw, A_IRQ_MSK, 1);       /* enable RX interrupts for hdlc */
 486                                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 487
 488                                         Write_hfc8(l1->hw, R_ST_SEL,
 489                                                    l1->st_num);
 490                                         l1->hw->mr.r_ctrl0 |=
 491                                             (bch->bchan & 3);
 492                                         Write_hfc8(l1->hw, A_ST_CTRL0,
 493                                                    l1->hw->mr.r_ctrl0);
 494                                         bch->mode = L1_MODE_HDLC;
 495                                         spin_unlock_irqrestore(&l1->lock,
 496                                                                flags);
 497
 498                                         bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 499                                                            PH_ACTIVATE |
 500                                                            INDICATION,
 501                                                            NULL);
 502                                         break;
 503
 504                                 case L1_MODE_TRANS:
 505                                         spin_lock_irqsave(&l1->lock,
 506                                                           flags);
 507                                         l1->hw->mr.
 508                                             fifo_rx_trans_enables[l1->
 509                                                                   st_num]
 510                                             |=
 511                                             ((bch->bchan ==
 512                                               1) ? 0x2 : 0x8);
 513                                         l1->hw->mr.timer_usg_cnt++;
 514                                         Write_hfc8(l1->hw, R_FIFO,
 515                                                    (l1->st_num * 8 +
 516                                                     ((bch->bchan ==
 517                                                       1) ? 0 : 2)));
 518                                         wait_busy(l1->hw);
 519                                         Write_hfc8(l1->hw, A_CON_HDLC, 0xf);    /* Transparent mode, 1 fill, connect ST */
 520                                         Write_hfc8(l1->hw, A_SUBCH_CFG, 0);     /* 8 bits */
 521                                         Write_hfc8(l1->hw, A_IRQ_MSK, 0);       /* disable TX interrupts */
 522                                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 523                                         wait_busy(l1->hw);
 524
 525                                         Write_hfc8(l1->hw, R_FIFO,
 526                                                    (l1->st_num * 8 +
 527                                                     ((bch->bchan ==
 528                                                       1) ? 1 : 3)));
 529                                         wait_busy(l1->hw);
 530                                         Write_hfc8(l1->hw, A_CON_HDLC, 0xf);    /* Transparent mode, 1 fill, connect ST */
 531                                         Write_hfc8(l1->hw, A_SUBCH_CFG, 0);     /* 8 bits */
 532                                         Write_hfc8(l1->hw, A_IRQ_MSK, 0);       /* disable RX interrupts */
 533                                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 534
 535                                         Write_hfc8(l1->hw, R_ST_SEL,
 536                                                    l1->st_num);
 537                                         l1->hw->mr.r_ctrl0 |=
 538                                             (bch->bchan & 3);
 539                                         Write_hfc8(l1->hw, A_ST_CTRL0,
 540                                                    l1->hw->mr.r_ctrl0);
 541                                         bch->mode = L1_MODE_TRANS;
 542                                         spin_unlock_irqrestore(&l1->lock,
 543                                                                flags);
 544
 545                                         bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 546                                                            PH_ACTIVATE |
 547                                                            INDICATION,
 548                                                            NULL);
 549                                         break;
 550
 551                                 default:
 552                                         if (bch->mode == L1_MODE_NULL)
 553                                                 break;
 554                                         spin_lock_irqsave(&l1->lock,
 555                                                           flags);
 556                                         l1->hw->mr.
 557                                             fifo_slow_timer_service[l1->
 558                                                                     st_num]
 559                                             &=
 560                                             ~((bch->bchan ==
 561                                                1) ? 0x3 : 0xc);
 562                                         l1->hw->mr.
 563                                             fifo_rx_trans_enables[l1->
 564                                                                   st_num]
 565                                             &=
 566                                             ~((bch->bchan ==
 567                                                1) ? 0x3 : 0xc);
 568                                         l1->hw->mr.timer_usg_cnt--;
 569                                         Write_hfc8(l1->hw, R_FIFO,
 570                                                    (l1->st_num * 8 +
 571                                                     ((bch->bchan ==
 572                                                       1) ? 0 : 2)));
 573                                         wait_busy(l1->hw);
 574                                         Write_hfc8(l1->hw, A_IRQ_MSK, 0);       /* disable TX interrupts */
 575                                         wait_busy(l1->hw);
 576                                         Write_hfc8(l1->hw, R_FIFO,
 577                                                    (l1->st_num * 8 +
 578                                                     ((bch->bchan ==
 579                                                       1) ? 1 : 3)));
 580                                         wait_busy(l1->hw);
 581                                         Write_hfc8(l1->hw, A_IRQ_MSK, 0);       /* disable RX interrupts */
 582                                         Write_hfc8(l1->hw, R_ST_SEL,
 583                                                    l1->st_num);
 584                                         l1->hw->mr.r_ctrl0 &=
 585                                             ~(bch->bchan & 3);
 586                                         Write_hfc8(l1->hw, A_ST_CTRL0,
 587                                                    l1->hw->mr.r_ctrl0);
 588                                         spin_unlock_irqrestore(&l1->lock,
 589                                                                flags);
 590
 591                                         bch->mode = L1_MODE_NULL;
 592                                         bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 593                                                            PH_DEACTIVATE |
 594                                                            INDICATION,
 595                                                            NULL);
 596                                         if (bch->tx_skb) {
 597                                                 dev_kfree_skb(bch->tx_skb);
 598                                                 bch->tx_skb = NULL;
 599                                         }
 600                                         if (bch->rx_skb) {
 601                                                 dev_kfree_skb(bch->rx_skb);
 602                                                 bch->rx_skb = NULL;
 603                                         }
 604                                         skb_queue_purge(&bch->tx_queue);
 605                                         bch->tx_cnt = 0;
 606                                         bch->rx_ptr = NULL;
 607                                         break;
 608                         }
 609
 610                         /* timer is only used when at least one b channel */
 611                         /* is set up to transparent mode */
 612                         if (l1->hw->mr.timer_usg_cnt) {
 613                                 Write_hfc8(l1->hw, R_IRQMSK_MISC,
 614                                            M_TI_IRQMSK);
 615                         } else {
 616                                 Write_hfc8(l1->hw, R_IRQMSK_MISC, 0);
 617                         }
 618
 619                         break;
 620
 621                 default:
 622                         printk(KERN_INFO
 623                                "HFC-4S/8S: Unknown B-chan cmd 0x%x received, ignored\n",
 624                                pr);
 625                         break;
 626         }
 627         if (!l1->enabled)
 628                 bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 629                                    PH_DEACTIVATE | INDICATION, NULL);
 630 }                               /* bch_l2l1 */
 631
 632 /**************************/
 633 /* layer 1 timer function */
 634 /**************************/
 635 static void
 636 hfc_l1_timer(struct hfc4s8s_l1 *l1)
 637 {
 638         u_long flags;
 639
 640         if (!l1->enabled)
 641                 return;
 642
 643         spin_lock_irqsave(&l1->lock, flags);
 644         if (l1->nt_mode) {
 645                 l1->l1_state = 1;
 646                 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
 647                 Write_hfc8(l1->hw, A_ST_WR_STA, 0x11);
 648                 spin_unlock_irqrestore(&l1->lock, flags);
 649                 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 650                                   PH_DEACTIVATE | INDICATION, NULL);
 651                 spin_lock_irqsave(&l1->lock, flags);
 652                 l1->l1_state = 1;
 653                 Write_hfc8(l1->hw, A_ST_WR_STA, 0x1);
 654                 spin_unlock_irqrestore(&l1->lock, flags);
 655         } else {
 656                 /* activation timed out */
 657                 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
 658                 Write_hfc8(l1->hw, A_ST_WR_STA, 0x13);
 659                 spin_unlock_irqrestore(&l1->lock, flags);
 660                 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 661                                   PH_DEACTIVATE | INDICATION, NULL);
 662                 spin_lock_irqsave(&l1->lock, flags);
 663                 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
 664                 Write_hfc8(l1->hw, A_ST_WR_STA, 0x3);
 665                 spin_unlock_irqrestore(&l1->lock, flags);
 666         }
 667 }                               /* hfc_l1_timer */
 668
 669 /****************************************/
 670 /* a complete D-frame has been received */
 671 /****************************************/
 672 static void
 673 rx_d_frame(struct hfc4s8s_l1 *l1p, int ech)
 674 {
 675         int z1, z2;
 676         u_char f1, f2, df;
 677         struct sk_buff *skb;
 678         u_char *cp;
 679
 680
 681         if (!l1p->enabled)
 682                 return;
 683         do {
 684                 /* E/D RX fifo */
 685                 Write_hfc8(l1p->hw, R_FIFO,
 686                            (l1p->st_num * 8 + ((ech) ? 7 : 5)));
 687                 wait_busy(l1p->hw);
 688
 689                 f1 = Read_hfc8_stable(l1p->hw, A_F1);
 690                 f2 = Read_hfc8(l1p->hw, A_F2);
 691                 df = f1 - f2;
 692                 if ((f1 - f2) < 0)
 693                         df = f1 - f2 + MAX_F_CNT + 1;
 694
 695
 696                 if (!df) {
 697                         return; /* no complete frame in fifo */
 698                 }
 699
 700                 z1 = Read_hfc16_stable(l1p->hw, A_Z1);
 701                 z2 = Read_hfc16(l1p->hw, A_Z2);
 702
 703                 z1 = z1 - z2 + 1;
 704                 if (z1 < 0)
 705                         z1 += 384;
 706
 707                 if (!(skb = dev_alloc_skb(MAX_D_FRAME_SIZE))) {
 708                         printk(KERN_INFO
 709                                "HFC-4S/8S: Could not allocate D/E "
 710                                "channel receive buffer");
 711                         Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2);
 712                         wait_busy(l1p->hw);
 713                         return;
 714                 }
 715
 716                 if (((z1 < 4) || (z1 > MAX_D_FRAME_SIZE))) {
 717                         if (skb)
 718                                 dev_kfree_skb(skb);
 719                         /* remove errornous D frame */
 720                         if (df == 1) {
 721                                 /* reset fifo */
 722                                 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2);
 723                                 wait_busy(l1p->hw);
 724                                 return;
 725                         } else {
 726                                 /* read errornous D frame */
 727
 728 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
 729                                 SetRegAddr(l1p->hw, A_FIFO_DATA0);
 730 #endif
 731
 732                                 while (z1 >= 4) {
 733 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
 734                                         Read_hfc32(l1p->hw, A_FIFO_DATA0);
 735 #else
 736                                         fRead_hfc32(l1p->hw);
 737 #endif
 738                                         z1 -= 4;
 739                                 }
 740
 741                                 while (z1--)
 742 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
 743                                         Read_hfc8(l1p->hw, A_FIFO_DATA0);
 744 #else
 745                                         fRead_hfc8(l1p->hw);
 746 #endif
 747
 748                                 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1);
 749                                 wait_busy(l1p->hw);
 750                                 return;
 751                         }
 752                 }
 753
 754                 cp = skb->data;
 755
 756 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
 757                 SetRegAddr(l1p->hw, A_FIFO_DATA0);
 758 #endif
 759
 760                 while (z1 >= 4) {
 761 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
 762                         *((unsigned long *) cp) =
 763                             Read_hfc32(l1p->hw, A_FIFO_DATA0);
 764 #else
 765                         *((unsigned long *) cp) = fRead_hfc32(l1p->hw);
 766 #endif
 767                         cp += 4;
 768                         z1 -= 4;
 769                 }
 770
 771                 while (z1--)
 772 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
 773                         *cp++ = Read_hfc8(l1p->hw, A_FIFO_DATA0);
 774 #else
 775                         *cp++ = fRead_hfc8(l1p->hw);
 776 #endif
 777
 778                 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */
 779                 wait_busy(l1p->hw);
 780
 781                 if (*(--cp)) {
 782                         dev_kfree_skb(skb);
 783                 } else {
 784                         skb->len = (cp - skb->data) - 2;
 785                         if (ech)
 786                                 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc,
 787                                                    PH_DATA_E | INDICATION,
 788                                                    skb);
 789                         else
 790                                 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc,
 791                                                    PH_DATA | INDICATION,
 792                                                    skb);
 793                 }
 794         } while (1);
 795 }                               /* rx_d_frame */
 796
 797 /*************************************************************/
 798 /* a B-frame has been received (perhaps not fully completed) */
 799 /*************************************************************/
 800 static void
 801 rx_b_frame(struct hfc4s8s_btype *bch)
 802 {
 803         int z1, z2, hdlc_complete;
 804         u_char f1, f2;
 805         struct hfc4s8s_l1 *l1 = bch->l1p;
 806         struct sk_buff *skb;
 807
 808         if (!l1->enabled || (bch->mode == L1_MODE_NULL))
 809                 return;
 810
 811         do {
 812                 /* RX Fifo */
 813                 Write_hfc8(l1->hw, R_FIFO,
 814                            (l1->st_num * 8 + ((bch->bchan == 1) ? 1 : 3)));
 815                 wait_busy(l1->hw);
 816
 817                 if (bch->mode == L1_MODE_HDLC) {
 818                         f1 = Read_hfc8_stable(l1->hw, A_F1);
 819                         f2 = Read_hfc8(l1->hw, A_F2);
 820                         hdlc_complete = ((f1 ^ f2) & MAX_F_CNT);
 821                 } else
 822                         hdlc_complete = 0;
 823                 z1 = Read_hfc16_stable(l1->hw, A_Z1);
 824                 z2 = Read_hfc16(l1->hw, A_Z2);
 825                 z1 = (z1 - z2);
 826                 if (hdlc_complete)
 827                         z1++;
 828                 if (z1 < 0)
 829                         z1 += 384;
 830
 831                 if (!z1)
 832                         break;
 833
 834                 if (!(skb = bch->rx_skb)) {
 835                         if (!
 836                             (skb =
 837                              dev_alloc_skb((bch->mode ==
 838                                             L1_MODE_TRANS) ? z1
 839                                            : (MAX_B_FRAME_SIZE + 3)))) {
 840                                 printk(KERN_ERR
 841                                        "HFC-4S/8S: Could not allocate B "
 842                                        "channel receive buffer");
 843                                 return;
 844                         }
 845                         bch->rx_ptr = skb->data;
 846                         bch->rx_skb = skb;
 847                 }
 848
 849                 skb->len = (bch->rx_ptr - skb->data) + z1;
 850
 851                 /* HDLC length check */
 852                 if ((bch->mode == L1_MODE_HDLC) &&
 853                     ((hdlc_complete && (skb->len < 4)) ||
 854                      (skb->len > (MAX_B_FRAME_SIZE + 3)))) {
 855
 856                         skb->len = 0;
 857                         bch->rx_ptr = skb->data;
 858                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 859                         wait_busy(l1->hw);
 860                         return;
 861                 }
 862 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
 863                 SetRegAddr(l1->hw, A_FIFO_DATA0);
 864 #endif
 865
 866                 while (z1 >= 4) {
 867 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
 868                         *((unsigned long *) bch->rx_ptr) =
 869                             Read_hfc32(l1->hw, A_FIFO_DATA0);
 870 #else
 871                         *((unsigned long *) bch->rx_ptr) =
 872                             fRead_hfc32(l1->hw);
 873 #endif
 874                         bch->rx_ptr += 4;
 875                         z1 -= 4;
 876                 }
 877
 878                 while (z1--)
 879 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
 880                         *(bch->rx_ptr++) = Read_hfc8(l1->hw, A_FIFO_DATA0);
 881 #else
 882                         *(bch->rx_ptr++) = fRead_hfc8(l1->hw);
 883 #endif
 884
 885                 if (hdlc_complete) {
 886                         /* increment f counter */
 887                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 1);
 888                         wait_busy(l1->hw);
 889
 890                         /* hdlc crc check */
 891                         bch->rx_ptr--;
 892                         if (*bch->rx_ptr) {
 893                                 skb->len = 0;
 894                                 bch->rx_ptr = skb->data;
 895                                 continue;
 896                         }
 897                         skb->len -= 3;
 898                 }
 899                 if (hdlc_complete || (bch->mode == L1_MODE_TRANS)) {
 900                         bch->rx_skb = NULL;
 901                         bch->rx_ptr = NULL;
 902                         bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 903                                            PH_DATA | INDICATION, skb);
 904                 }
 905
 906         } while (1);
 907 }                               /* rx_b_frame */
 908
 909 /********************************************/
 910 /* a D-frame has been/should be transmitted */
 911 /********************************************/
 912 static void
 913 tx_d_frame(struct hfc4s8s_l1 *l1p)
 914 {
 915         struct sk_buff *skb;
 916         u_char f1, f2;
 917         u_char *cp;
 918         int cnt;
 919
 920         if (l1p->l1_state != 7)
 921                 return;
 922
 923         /* TX fifo */
 924         Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + 4));
 925         wait_busy(l1p->hw);
 926
 927         f1 = Read_hfc8(l1p->hw, A_F1);
 928         f2 = Read_hfc8_stable(l1p->hw, A_F2);
 929
 930         if ((f1 ^ f2) & MAX_F_CNT)
 931                 return;         /* fifo is still filled */
 932
 933         if (l1p->tx_cnt > 0) {
 934                 cnt = l1p->tx_cnt;
 935                 l1p->tx_cnt = 0;
 936                 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_DATA | CONFIRM,
 937                                    (void *) cnt);
 938         }
 939
 940         if ((skb = skb_dequeue(&l1p->d_tx_queue))) {
 941                 cp = skb->data;
 942                 cnt = skb->len;
 943 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
 944                 SetRegAddr(l1p->hw, A_FIFO_DATA0);
 945 #endif
 946
 947                 while (cnt >= 4) {
 948 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
 949                         fWrite_hfc32(l1p->hw, A_FIFO_DATA0,
 950                                      *(unsigned long *) cp);
 951 #else
 952                         SetRegAddr(l1p->hw, A_FIFO_DATA0);
 953                         fWrite_hfc32(l1p->hw, *(unsigned long *) cp);
 954 #endif
 955                         cp += 4;
 956                         cnt -= 4;
 957                 }
 958
 959 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
 960                 while (cnt--)
 961                         fWrite_hfc8(l1p->hw, A_FIFO_DATA0, *cp++);
 962 #else
 963                 while (cnt--)
 964                         fWrite_hfc8(l1p->hw, *cp++);
 965 #endif
 966
 967                 l1p->tx_cnt = skb->truesize;
 968                 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */
 969                 wait_busy(l1p->hw);
 970
 971                 dev_kfree_skb(skb);
 972         }
 973 }                               /* tx_d_frame */
 974
 975 /******************************************************/
 976 /* a B-frame may be transmitted (or is not completed) */
 977 /******************************************************/
 978 static void
 979 tx_b_frame(struct hfc4s8s_btype *bch)
 980 {
 981         struct sk_buff *skb;
 982         struct hfc4s8s_l1 *l1 = bch->l1p;
 983         u_char *cp;
 984         int cnt, max, hdlc_num, ack_len = 0;
 985
 986         if (!l1->enabled || (bch->mode == L1_MODE_NULL))
 987                 return;
 988
 989         /* TX fifo */
 990         Write_hfc8(l1->hw, R_FIFO,
 991                    (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2)));
 992         wait_busy(l1->hw);
 993         do {
 994
 995                 if (bch->mode == L1_MODE_HDLC) {
 996                         hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT;
 997                         hdlc_num -=
 998                             (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT);
 999                         if (hdlc_num < 0)
1000                                 hdlc_num += 16;
1001                         if (hdlc_num >= 15)
1002                                 break;  /* fifo still filled up with hdlc frames */
1003                 } else
1004                         hdlc_num = 0;
1005
1006                 if (!(skb = bch->tx_skb)) {
1007                         if (!(skb = skb_dequeue(&bch->tx_queue))) {
1008                                 l1->hw->mr.fifo_slow_timer_service[l1->
1009                                                                    st_num]
1010                                     &= ~((bch->bchan == 1) ? 1 : 4);
1011                                 break;  /* list empty */
1012                         }
1013                         bch->tx_skb = skb;
1014                         bch->tx_cnt = 0;
1015                 }
1016
1017                 if (!hdlc_num)
1018                         l1->hw->mr.fifo_slow_timer_service[l1->st_num] |=
1019                             ((bch->bchan == 1) ? 1 : 4);
1020                 else
1021                         l1->hw->mr.fifo_slow_timer_service[l1->st_num] &=
1022                             ~((bch->bchan == 1) ? 1 : 4);
1023
1024                 max = Read_hfc16_stable(l1->hw, A_Z2);
1025                 max -= Read_hfc16(l1->hw, A_Z1);
1026                 if (max <= 0)
1027                         max += 384;
1028                 max--;
1029
1030                 if (max < 16)
1031                         break;  /* don't write to small amounts of bytes */
1032
1033                 cnt = skb->len - bch->tx_cnt;
1034                 if (cnt > max)
1035                         cnt = max;
1036                 cp = skb->data + bch->tx_cnt;
1037                 bch->tx_cnt += cnt;
1038
1039 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
1040                 SetRegAddr(l1->hw, A_FIFO_DATA0);
1041 #endif
1042                 while (cnt >= 4) {
1043 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
1044                         fWrite_hfc32(l1->hw, A_FIFO_DATA0,
1045                                      *(unsigned long *) cp);
1046 #else
1047                         fWrite_hfc32(l1->hw, *(unsigned long *) cp);
1048 #endif
1049                         cp += 4;
1050                         cnt -= 4;
1051                 }
1052
1053                 while (cnt--)
1054 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
1055                         fWrite_hfc8(l1->hw, A_FIFO_DATA0, *cp++);
1056 #else
1057                         fWrite_hfc8(l1->hw, *cp++);
1058 #endif
1059
1060                 if (bch->tx_cnt >= skb->len) {
1061                         if (bch->mode == L1_MODE_HDLC) {
1062                                 /* increment f counter */
1063                                 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1);
1064                         }
1065                         ack_len += skb->truesize;
1066                         bch->tx_skb = NULL;
1067                         bch->tx_cnt = 0;
1068                         dev_kfree_skb(skb);
1069                 } else
1070                         /* Re-Select */
1071                         Write_hfc8(l1->hw, R_FIFO,
1072                                    (l1->st_num * 8 +
1073                                     ((bch->bchan == 1) ? 0 : 2)));
1074                 wait_busy(l1->hw);
1075         } while (1);
1076
1077         if (ack_len)
1078                 bch->b_if.ifc.l1l2((struct hisax_if *) &bch->b_if,
1079                                    PH_DATA | CONFIRM, (void *) ack_len);
1080 }                               /* tx_b_frame */
1081
1082 /*************************************/
1083 /* bottom half handler for interrupt */
1084 /*************************************/
1085 static void
1086 hfc4s8s_bh(hfc4s8s_hw * hw)
1087 {
1088         u_char b;
1089         struct hfc4s8s_l1 *l1p;
1090         volatile u_char *fifo_stat;
1091         int idx;
1092
1093         /* handle layer 1 state changes */
1094         b = 1;
1095         l1p = hw->l1;
1096         while (b) {
1097                 if ((b & hw->mr.r_irq_statech)) {
1098                         /* reset l1 event */
1099                         hw->mr.r_irq_statech &= ~b;
1100                         if (l1p->enabled) {
1101                                 if (l1p->nt_mode) {
1102                                         u_char oldstate = l1p->l1_state;
1103
1104                                         Write_hfc8(l1p->hw, R_ST_SEL,
1105                                                    l1p->st_num);
1106                                         l1p->l1_state =
1107                                             Read_hfc8(l1p->hw,
1108                                                       A_ST_RD_STA) & 0xf;
1109
1110                                         if ((oldstate == 3)
1111                                             && (l1p->l1_state != 3))
1112                                                 l1p->d_if.ifc.l1l2(&l1p->
1113                                                                    d_if.
1114                                                                    ifc,
1115                                                                    PH_DEACTIVATE
1116                                                                    |
1117                                                                    INDICATION,
1118                                                                    NULL);
1119
1120                                         if (l1p->l1_state != 2) {
1121                                                 del_timer(&l1p->l1_timer);
1122                                                 if (l1p->l1_state == 3) {
1123                                                         l1p->d_if.ifc.
1124                                                             l1l2(&l1p->
1125                                                                  d_if.ifc,
1126                                                                  PH_ACTIVATE
1127                                                                  |
1128                                                                  INDICATION,
1129                                                                  NULL);
1130                                                 }
1131                                         } else {
1132                                                 /* allow transition */
1133                                                 Write_hfc8(hw, A_ST_WR_STA,
1134                                                            M_SET_G2_G3);
1135                                                 mod_timer(&l1p->l1_timer,
1136                                                           jiffies +
1137                                                           L1_TIMER_T1);
1138                                         }
1139                                         printk(KERN_INFO
1140                                                "HFC-4S/8S: NT ch %d l1 state %d -> %d\n",
1141                                                l1p->st_num, oldstate,
1142                                                l1p->l1_state);
1143                                 } else {
1144                                         u_char oldstate = l1p->l1_state;
1145
1146                                         Write_hfc8(l1p->hw, R_ST_SEL,
1147                                                    l1p->st_num);
1148                                         l1p->l1_state =
1149                                             Read_hfc8(l1p->hw,
1150                                                       A_ST_RD_STA) & 0xf;
1151
1152                                         if (((l1p->l1_state == 3) &&
1153                                              ((oldstate == 7) ||
1154                                               (oldstate == 8))) ||
1155                                             ((timer_pending
1156                                               (&l1p->l1_timer))
1157                                              && (l1p->l1_state == 8))) {
1158                                                 mod_timer(&l1p->l1_timer,
1159                                                           L1_TIMER_T4 +
1160                                                           jiffies);
1161                                         } else {
1162                                                 if (l1p->l1_state == 7) {
1163                                                         del_timer(&l1p->
1164                                                                   l1_timer);
1165                                                         l1p->d_if.ifc.
1166                                                             l1l2(&l1p->
1167                                                                  d_if.ifc,
1168                                                                  PH_ACTIVATE
1169                                                                  |
1170                                                                  INDICATION,
1171                                                                  NULL);
1172                                                         tx_d_frame(l1p);
1173                                                 }
1174                                                 if (l1p->l1_state == 3) {
1175                                                         if (oldstate != 3)
1176                                                                 l1p->d_if.
1177                                                                     ifc.
1178                                                                     l1l2
1179                                                                     (&l1p->
1180                                                                      d_if.
1181                                                                      ifc,
1182                                                                      PH_DEACTIVATE
1183                                                                      |
1184                                                                      INDICATION,
1185                                                                      NULL);
1186                                                 }
1187                                         }
1188                                         printk(KERN_INFO
1189                                                "HFC-4S/8S: TE %d ch %d l1 state %d -> %d\n",
1190                                                l1p->hw->cardnum,
1191                                                l1p->st_num, oldstate,
1192                                                l1p->l1_state);
1193                                 }
1194                         }
1195                 }
1196                 b <<= 1;
1197                 l1p++;
1198         }
1199
1200         /* now handle the fifos */
1201         idx = 0;
1202         fifo_stat = hw->mr.r_irq_fifo_blx;
1203         l1p = hw->l1;
1204         while (idx < hw->driver_data.max_st_ports) {
1205
1206                 if (hw->mr.timer_irq) {
1207                         *fifo_stat |= hw->mr.fifo_rx_trans_enables[idx];
1208                         if (hw->fifo_sched_cnt <= 0) {
1209                                 *fifo_stat |=
1210                                     hw->mr.fifo_slow_timer_service[l1p->
1211                                                                    st_num];
1212                         }
1213                 }
1214                 /* ignore fifo 6 (TX E fifo) */
1215                 *fifo_stat &= 0xff - 0x40;
1216
1217                 while (*fifo_stat) {
1218
1219                         if (!l1p->nt_mode) {
1220                                 /* RX Fifo has data to read */
1221                                 if ((*fifo_stat & 0x20)) {
1222                                         *fifo_stat &= ~0x20;
1223                                         rx_d_frame(l1p, 0);
1224                                 }
1225                                 /* E Fifo has data to read */
1226                                 if ((*fifo_stat & 0x80)) {
1227                                         *fifo_stat &= ~0x80;
1228                                         rx_d_frame(l1p, 1);
1229                                 }
1230                                 /* TX Fifo completed send */
1231                                 if ((*fifo_stat & 0x10)) {
1232                                         *fifo_stat &= ~0x10;
1233                                         tx_d_frame(l1p);
1234                                 }
1235                         }
1236                         /* B1 RX Fifo has data to read */
1237                         if ((*fifo_stat & 0x2)) {
1238                                 *fifo_stat &= ~0x2;
1239                                 rx_b_frame(l1p->b_ch);
1240                         }
1241                         /* B1 TX Fifo has send completed */
1242                         if ((*fifo_stat & 0x1)) {
1243                                 *fifo_stat &= ~0x1;
1244                                 tx_b_frame(l1p->b_ch);
1245                         }
1246                         /* B2 RX Fifo has data to read */
1247                         if ((*fifo_stat & 0x8)) {
1248                                 *fifo_stat &= ~0x8;
1249                                 rx_b_frame(l1p->b_ch + 1);
1250                         }
1251                         /* B2 TX Fifo has send completed */
1252                         if ((*fifo_stat & 0x4)) {
1253                                 *fifo_stat &= ~0x4;
1254                                 tx_b_frame(l1p->b_ch + 1);
1255                         }
1256                 }
1257                 fifo_stat++;
1258                 l1p++;
1259                 idx++;
1260         }
1261
1262         if (hw->fifo_sched_cnt <= 0)
1263                 hw->fifo_sched_cnt += (1 << (7 - TRANS_TIMER_MODE));
1264         hw->mr.timer_irq = 0;   /* clear requested timer irq */
1265 }                               /* hfc4s8s_bh */
1266
1267 /*********************/
1268 /* interrupt handler */
1269 /*********************/
1270 static irqreturn_t
1271 hfc4s8s_interrupt(int intno, void *dev_id, struct pt_regs *regs)
1272 {
1273         hfc4s8s_hw *hw = dev_id;
1274         u_char b, ovr;
1275         volatile u_char *ovp;
1276         int idx;
1277         u_char old_ioreg;
1278
1279         if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN))
1280                 return IRQ_NONE;
1281
1282 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
1283         /* read current selected regsister */
1284         old_ioreg = GetRegAddr(hw);
1285 #endif
1286
1287         /* Layer 1 State change */
1288         hw->mr.r_irq_statech |=
1289             (Read_hfc8(hw, R_SCI) & hw->mr.r_irqmsk_statchg);
1290         if (!
1291             (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA)))
1292 && !hw->mr.r_irq_statech) {
1293 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
1294                 SetRegAddr(hw, old_ioreg);
1295 #endif
1296                 return IRQ_NONE;
1297         }
1298
1299         /* timer event */
1300         if (Read_hfc8(hw, R_IRQ_MISC) & M_TI_IRQ) {
1301                 hw->mr.timer_irq = 1;
1302                 hw->fifo_sched_cnt--;
1303         }
1304
1305         /* FIFO event */
1306         if ((ovr = Read_hfc8(hw, R_IRQ_OVIEW))) {
1307                 hw->mr.r_irq_oview |= ovr;
1308                 idx = R_IRQ_FIFO_BL0;
1309                 ovp = hw->mr.r_irq_fifo_blx;
1310                 while (ovr) {
1311                         if ((ovr & 1)) {
1312                                 *ovp |= Read_hfc8(hw, idx);
1313                         }
1314                         ovp++;
1315                         idx++;
1316                         ovr >>= 1;
1317                 }
1318         }
1319
1320         /* queue the request to allow other cards to interrupt */
1321         schedule_work(&hw->tqueue);
1322
1323 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
1324         SetRegAddr(hw, old_ioreg);
1325 #endif
1326         return IRQ_HANDLED;
1327 }                               /* hfc4s8s_interrupt */
1328
1329 /***********************************************************************/
1330 /* reset the complete chip, don't release the chips irq but disable it */
1331 /***********************************************************************/
1332 static void
1333 chipreset(hfc4s8s_hw * hw)
1334 {
1335         u_long flags;
1336
1337         spin_lock_irqsave(&hw->lock, flags);
1338         Write_hfc8(hw, R_CTRL, 0);      /* use internal RAM */
1339         Write_hfc8(hw, R_RAM_MISC, 0);  /* 32k*8 RAM */
1340         Write_hfc8(hw, R_FIFO_MD, 0);   /* fifo mode 386 byte/fifo simple mode */
1341         Write_hfc8(hw, R_CIRM, M_SRES); /* reset chip */
1342         hw->mr.r_irq_ctrl = 0;  /* interrupt is inactive */
1343         spin_unlock_irqrestore(&hw->lock, flags);
1344
1345         udelay(3);
1346         Write_hfc8(hw, R_CIRM, 0);      /* disable reset */
1347         wait_busy(hw);
1348
1349         Write_hfc8(hw, R_PCM_MD0, M_PCM_MD);    /* master mode */
1350         Write_hfc8(hw, R_RAM_MISC, M_FZ_MD);    /* transmit fifo option */
1351         if (hw->driver_data.clock_mode == 1)
1352                 Write_hfc8(hw, R_BRG_PCM_CFG, M_PCM_CLK);       /* PCM clk / 2 */
1353         Write_hfc8(hw, R_TI_WD, TRANS_TIMER_MODE);      /* timer interval */
1354
1355         memset(&hw->mr, 0, sizeof(hw->mr));
1356 }                               /* chipreset */
1357
1358 /********************************************/
1359 /* disable/enable hardware in nt or te mode */
1360 /********************************************/
1361 static void
1362 hfc_hardware_enable(hfc4s8s_hw * hw, int enable, int nt_mode)
1363 {
1364         u_long flags;
1365         char if_name[40];
1366         int i;
1367
1368         if (enable) {
1369                 /* save system vars */
1370                 hw->nt_mode = nt_mode;
1371
1372                 /* enable fifo and state irqs, but not global irq enable */
1373                 hw->mr.r_irq_ctrl = M_FIFO_IRQ;
1374                 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1375                 hw->mr.r_irqmsk_statchg = 0;
1376                 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg);
1377                 Write_hfc8(hw, R_PWM_MD, 0x80);
1378                 Write_hfc8(hw, R_PWM1, 26);
1379                 if (!nt_mode)
1380                         Write_hfc8(hw, R_ST_SYNC, M_AUTO_SYNC);
1381
1382                 /* enable the line interfaces and fifos */
1383                 for (i = 0; i < hw->driver_data.max_st_ports; i++) {
1384                         hw->mr.r_irqmsk_statchg |= (1 << i);
1385                         Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg);
1386                         Write_hfc8(hw, R_ST_SEL, i);
1387                         Write_hfc8(hw, A_ST_CLK_DLY,
1388                                    ((nt_mode) ? CLKDEL_NT : CLKDEL_TE));
1389                         hw->mr.r_ctrl0 = ((nt_mode) ? CTRL0_NT : CTRL0_TE);
1390                         Write_hfc8(hw, A_ST_CTRL0, hw->mr.r_ctrl0);
1391                         Write_hfc8(hw, A_ST_CTRL2, 3);
1392                         Write_hfc8(hw, A_ST_WR_STA, 0); /* enable state machine */
1393
1394                         hw->l1[i].enabled = 1;
1395                         hw->l1[i].nt_mode = nt_mode;
1396
1397                         if (!nt_mode) {
1398                                 /* setup E-fifo */
1399                                 Write_hfc8(hw, R_FIFO, i * 8 + 7);      /* E fifo */
1400                                 wait_busy(hw);
1401                                 Write_hfc8(hw, A_CON_HDLC, 0x11);       /* HDLC mode, 1 fill, connect ST */
1402                                 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1403                                 Write_hfc8(hw, A_IRQ_MSK, 1);   /* enable interrupt */
1404                                 Write_hfc8(hw, A_INC_RES_FIFO, 2);      /* reset fifo */
1405                                 wait_busy(hw);
1406
1407                                 /* setup D RX-fifo */
1408                                 Write_hfc8(hw, R_FIFO, i * 8 + 5);      /* RX fifo */
1409                                 wait_busy(hw);
1410                                 Write_hfc8(hw, A_CON_HDLC, 0x11);       /* HDLC mode, 1 fill, connect ST */
1411                                 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1412                                 Write_hfc8(hw, A_IRQ_MSK, 1);   /* enable interrupt */
1413                                 Write_hfc8(hw, A_INC_RES_FIFO, 2);      /* reset fifo */
1414                                 wait_busy(hw);
1415
1416                                 /* setup D TX-fifo */
1417                                 Write_hfc8(hw, R_FIFO, i * 8 + 4);      /* TX fifo */
1418                                 wait_busy(hw);
1419                                 Write_hfc8(hw, A_CON_HDLC, 0x11);       /* HDLC mode, 1 fill, connect ST */
1420                                 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1421                                 Write_hfc8(hw, A_IRQ_MSK, 1);   /* enable interrupt */
1422                                 Write_hfc8(hw, A_INC_RES_FIFO, 2);      /* reset fifo */
1423                                 wait_busy(hw);
1424                         }
1425
1426                         sprintf(if_name, "hfc4s8s_%d%d_", hw->cardnum, i);
1427
1428                         if (hisax_register
1429                             (&hw->l1[i].d_if, hw->l1[i].b_table, if_name,
1430                              ((nt_mode) ? 3 : 2))) {
1431
1432                                 hw->l1[i].enabled = 0;
1433                                 hw->mr.r_irqmsk_statchg &= ~(1 << i);
1434                                 Write_hfc8(hw, R_SCI_MSK,
1435                                            hw->mr.r_irqmsk_statchg);
1436                                 printk(KERN_INFO
1437                                        "HFC-4S/8S: Unable to register S/T device %s, break\n",
1438                                        if_name);
1439                                 break;
1440                         }
1441                 }
1442                 spin_lock_irqsave(&hw->lock, flags);
1443                 hw->mr.r_irq_ctrl |= M_GLOB_IRQ_EN;
1444                 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1445                 spin_unlock_irqrestore(&hw->lock, flags);
1446         } else {
1447                 /* disable hardware */
1448                 spin_lock_irqsave(&hw->lock, flags);
1449                 hw->mr.r_irq_ctrl &= ~M_GLOB_IRQ_EN;
1450                 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1451                 spin_unlock_irqrestore(&hw->lock, flags);
1452
1453                 for (i = hw->driver_data.max_st_ports - 1; i >= 0; i--) {
1454                         hw->l1[i].enabled = 0;
1455                         hisax_unregister(&hw->l1[i].d_if);
1456                         del_timer(&hw->l1[i].l1_timer);
1457                         skb_queue_purge(&hw->l1[i].d_tx_queue);
1458                         skb_queue_purge(&hw->l1[i].b_ch[0].tx_queue);
1459                         skb_queue_purge(&hw->l1[i].b_ch[1].tx_queue);
1460                 }
1461                 chipreset(hw);
1462         }
1463 }                               /* hfc_hardware_enable */
1464
1465 /******************************************/
1466 /* disable memory mapped ports / io ports */
1467 /******************************************/
1468 static void
1469 release_pci_ports(hfc4s8s_hw * hw)
1470 {
1471         pci_write_config_word(hw->pdev, PCI_COMMAND, 0);
1472 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
1473         if (hw->membase)
1474                 iounmap((void *) hw->membase);
1475 #else
1476         if (hw->iobase)
1477                 release_region(hw->iobase, 8);
1478 #endif
1479 }
1480
1481 /*****************************************/
1482 /* enable memory mapped ports / io ports */
1483 /*****************************************/
1484 static void
1485 enable_pci_ports(hfc4s8s_hw * hw)
1486 {
1487 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
1488         pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
1489 #else
1490         pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_REGIO);
1491 #endif
1492 }
1493
1494 /*************************************/
1495 /* initialise the HFC-4s/8s hardware */
1496 /* return 0 on success.              */
1497 /*************************************/
1498 static int __devinit
1499 setup_instance(hfc4s8s_hw * hw)
1500 {
1501         int err = -EIO;
1502         int i;
1503
1504         for (i = 0; i < HFC_MAX_ST; i++) {
1505                 struct hfc4s8s_l1 *l1p;
1506
1507                 l1p = hw->l1 + i;
1508                 spin_lock_init(&l1p->lock);
1509                 l1p->hw = hw;
1510                 l1p->l1_timer.function = (void *) hfc_l1_timer;
1511                 l1p->l1_timer.data = (long) (l1p);
1512                 init_timer(&l1p->l1_timer);
1513                 l1p->st_num = i;
1514                 skb_queue_head_init(&l1p->d_tx_queue);
1515                 l1p->d_if.ifc.priv = hw->l1 + i;
1516                 l1p->d_if.ifc.l2l1 = (void *) dch_l2l1;
1517
1518                 spin_lock_init(&l1p->b_ch[0].lock);
1519                 l1p->b_ch[0].b_if.ifc.l2l1 = (void *) bch_l2l1;
1520                 l1p->b_ch[0].b_if.ifc.priv = (void *) &l1p->b_ch[0];
1521                 l1p->b_ch[0].l1p = hw->l1 + i;
1522                 l1p->b_ch[0].bchan = 1;
1523                 l1p->b_table[0] = &l1p->b_ch[0].b_if;
1524                 skb_queue_head_init(&l1p->b_ch[0].tx_queue);
1525
1526                 spin_lock_init(&l1p->b_ch[1].lock);
1527                 l1p->b_ch[1].b_if.ifc.l2l1 = (void *) bch_l2l1;
1528                 l1p->b_ch[1].b_if.ifc.priv = (void *) &l1p->b_ch[1];
1529                 l1p->b_ch[1].l1p = hw->l1 + i;
1530                 l1p->b_ch[1].bchan = 2;
1531                 l1p->b_table[1] = &l1p->b_ch[1].b_if;
1532                 skb_queue_head_init(&l1p->b_ch[1].tx_queue);
1533         }
1534
1535         enable_pci_ports(hw);
1536         chipreset(hw);
1537
1538         i = Read_hfc8(hw, R_CHIP_ID) >> CHIP_ID_SHIFT;
1539         if (i != hw->driver_data.chip_id) {
1540                 printk(KERN_INFO
1541                        "HFC-4S/8S: invalid chip id 0x%x instead of 0x%x, card ignored\n",
1542                        i, hw->driver_data.chip_id);
1543                 goto out;
1544         }
1545
1546         i = Read_hfc8(hw, R_CHIP_RV) & 0xf;
1547         if (!i) {
1548                 printk(KERN_INFO
1549                        "HFC-4S/8S: chip revision 0 not supported, card ignored\n");
1550                 goto out;
1551         }
1552
1553         INIT_WORK(&hw->tqueue, (void *) (void *) hfc4s8s_bh, hw);
1554
1555         if (request_irq
1556             (hw->irq, hfc4s8s_interrupt, SA_SHIRQ, hw->card_name, hw)) {
1557                 printk(KERN_INFO
1558                        "HFC-4S/8S: unable to alloc irq %d, card ignored\n",
1559                        hw->irq);
1560                 goto out;
1561         }
1562 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
1563         printk(KERN_INFO
1564                "HFC-4S/8S: found PCI card at membase 0x%p, irq %d\n",
1565                hw->hw_membase, hw->irq);
1566 #else
1567         printk(KERN_INFO
1568                "HFC-4S/8S: found PCI card at iobase 0x%x, irq %d\n",
1569                hw->iobase, hw->irq);
1570 #endif
1571
1572         hfc_hardware_enable(hw, 1, 0);
1573
1574         return (0);
1575
1576       out:
1577         hw->irq = 0;
1578         release_pci_ports(hw);
1579         kfree(hw);
1580         return (err);
1581 }
1582
1583 /*****************************************/
1584 /* PCI hotplug interface: probe new card */
1585 /*****************************************/
1586 static int __devinit
1587 hfc4s8s_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1588 {
1589         int err = -ENOMEM;
1590         hfc4s8s_param *driver_data = (hfc4s8s_param *) ent->driver_data;
1591         hfc4s8s_hw *hw;
1592
1593         if (!(hw = kmalloc(sizeof(hfc4s8s_hw), GFP_ATOMIC))) {
1594                 printk(KERN_ERR "No kmem for HFC-4S/8S card\n");
1595                 return (err);
1596         }
1597         memset(hw, 0, sizeof(hfc4s8s_hw));
1598
1599         hw->pdev = pdev;
1600         err = pci_enable_device(pdev);
1601
1602         if (err)
1603                 goto out;
1604
1605         hw->cardnum = card_cnt;
1606         sprintf(hw->card_name, "hfc4s8s_%d", hw->cardnum);
1607         printk(KERN_INFO "HFC-4S/8S: found adapter %s (%s) at %s\n",
1608                driver_data->device_name, hw->card_name, pci_name(pdev));
1609
1610         spin_lock_init(&hw->lock);
1611
1612         hw->driver_data = *driver_data;
1613         hw->irq = pdev->irq;
1614         hw->iobase = pci_resource_start(pdev, 0);
1615
1616 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
1617         hw->hw_membase = (u_char *) pci_resource_start(pdev, 1);
1618         hw->membase = ioremap((ulong) hw->hw_membase, 256);
1619 #else
1620         if (!request_region(hw->iobase, 8, hw->card_name)) {
1621                 printk(KERN_INFO
1622                        "HFC-4S/8S: failed to rquest address space at 0x%04x\n",
1623                        hw->iobase);
1624                 goto out;
1625         }
1626 #endif
1627
1628         pci_set_drvdata(pdev, hw);
1629         err = setup_instance(hw);
1630         if (!err)
1631                 card_cnt++;
1632         return (err);
1633
1634       out:
1635         kfree(hw);
1636         return (err);
1637 }
1638
1639 /**************************************/
1640 /* PCI hotplug interface: remove card */
1641 /**************************************/
1642 static void __devexit
1643 hfc4s8s_remove(struct pci_dev *pdev)
1644 {
1645         hfc4s8s_hw *hw = pci_get_drvdata(pdev);
1646
1647         printk(KERN_INFO "HFC-4S/8S: removing card %d\n", hw->cardnum);
1648         hfc_hardware_enable(hw, 0, 0);
1649
1650         if (hw->irq)
1651                 free_irq(hw->irq, hw);
1652         hw->irq = 0;
1653         release_pci_ports(hw);
1654
1655         card_cnt--;
1656         pci_disable_device(pdev);
1657         kfree(hw);
1658         return;
1659 }
1660
1661 static struct pci_driver hfc4s8s_driver = {
1662       .name     = "hfc4s8s_l1",
1663       .probe    = hfc4s8s_probe,
1664       .remove   = __devexit_p(hfc4s8s_remove),
1665       .id_table = hfc4s8s_ids,
1666 };
1667
1668 /**********************/
1669 /* driver Module init */
1670 /**********************/
1671 static int __init
1672 hfc4s8s_module_init(void)
1673 {
1674         int err;
1675
1676         printk(KERN_INFO
1677                "HFC-4S/8S: Layer 1 driver module for HFC-4S/8S isdn chips, %s\n",
1678                hfc4s8s_rev);
1679         printk(KERN_INFO
1680                "HFC-4S/8S: (C) 2003 Cornelius Consult, www.cornelius-consult.de\n");
1681
1682         card_cnt = 0;
1683
1684         err = pci_register_driver(&hfc4s8s_driver);
1685         if (err < 0) {
1686                 goto out;
1687         }
1688         printk(KERN_INFO "HFC-4S/8S: found %d cards\n", card_cnt);
1689
1690 #if !defined(CONFIG_HOTPLUG)
1691         if (err == 0) {
1692                 err = -ENODEV;
1693                 pci_unregister_driver(&hfc4s8s_driver);
1694                 goto out;
1695         }
1696 #endif
1697
1698         return 0;
1699       out:
1700         return (err);
1701 }                               /* hfc4s8s_init_hw */
1702
1703 /*************************************/
1704 /* driver module exit :              */
1705 /* release the HFC-4s/8s hardware    */
1706 /*************************************/
1707 static void
1708 hfc4s8s_module_exit(void)
1709 {
1710         pci_unregister_driver(&hfc4s8s_driver);
1711         printk(KERN_INFO "HFC-4S/8S: module removed\n");
1712 }                               /* hfc4s8s_release_hw */
1713
1714 module_init(hfc4s8s_module_init);
1715 module_exit(hfc4s8s_module_exit);