drivers/iommu/intel-svm.c

   1 /*
   2  * Copyright © 2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * Authors: David Woodhouse <dwmw2@infradead.org>
  14  */
  15
  16 #include <linux/intel-iommu.h>
  17 #include <linux/mmu_notifier.h>
  18 #include <linux/sched.h>
  19 #include <linux/sched/mm.h>
  20 #include <linux/slab.h>
  21 #include <linux/intel-svm.h>
  22 #include <linux/rculist.h>
  23 #include <linux/pci.h>
  24 #include <linux/pci-ats.h>
  25 #include <linux/dmar.h>
  26 #include <linux/interrupt.h>
  27 #include <asm/page.h>
  28
  29 static irqreturn_t prq_event_thread(int irq, void *d);
  30
  31 struct pasid_entry {
  32         u64 val;
  33 };
  34
  35 struct pasid_state_entry {
  36         u64 val;
  37 };
  38
  39 int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
  40 {
  41         struct page *pages;
  42         int order;
  43
  44         /* Start at 2 because it's defined as 2^(1+PSS) */
  45         iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
  46
  47         /* Eventually I'm promised we will get a multi-level PASID table
  48          * and it won't have to be physically contiguous. Until then,
  49          * limit the size because 8MiB contiguous allocations can be hard
  50          * to come by. The limit of 0x20000, which is 1MiB for each of
  51          * the PASID and PASID-state tables, is somewhat arbitrary. */
  52         if (iommu->pasid_max > 0x20000)
  53                 iommu->pasid_max = 0x20000;
  54
  55         order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
  56         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
  57         if (!pages) {
  58                 pr_warn("IOMMU: %s: Failed to allocate PASID table\n",
  59                         iommu->name);
  60                 return -ENOMEM;
  61         }
  62         iommu->pasid_table = page_address(pages);
  63         pr_info("%s: Allocated order %d PASID table.\n", iommu->name, order);
  64
  65         if (ecap_dis(iommu->ecap)) {
  66                 /* Just making it explicit... */
  67                 BUILD_BUG_ON(sizeof(struct pasid_entry) != sizeof(struct pasid_state_entry));
  68                 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
  69                 if (pages)
  70                         iommu->pasid_state_table = page_address(pages);
  71                 else
  72                         pr_warn("IOMMU: %s: Failed to allocate PASID state table\n",
  73                                 iommu->name);
  74         }
  75
  76         idr_init(&iommu->pasid_idr);
  77
  78         return 0;
  79 }
  80
  81 int intel_svm_free_pasid_tables(struct intel_iommu *iommu)
  82 {
  83         int order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
  84
  85         if (iommu->pasid_table) {
  86                 free_pages((unsigned long)iommu->pasid_table, order);
  87                 iommu->pasid_table = NULL;
  88         }
  89         if (iommu->pasid_state_table) {
  90                 free_pages((unsigned long)iommu->pasid_state_table, order);
  91                 iommu->pasid_state_table = NULL;
  92         }
  93         idr_destroy(&iommu->pasid_idr);
  94         return 0;
  95 }
  96
  97 #define PRQ_ORDER 0
  98
  99 int intel_svm_enable_prq(struct intel_iommu *iommu)
 100 {
 101         struct page *pages;
 102         int irq, ret;
 103
 104         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
 105         if (!pages) {
 106                 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
 107                         iommu->name);
 108                 return -ENOMEM;
 109         }
 110         iommu->prq = page_address(pages);
 111
 112         irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
 113         if (irq <= 0) {
 114                 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
 115                        iommu->name);
 116                 ret = -EINVAL;
 117         err:
 118                 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
 119                 iommu->prq = NULL;
 120                 return ret;
 121         }
 122         iommu->pr_irq = irq;
 123
 124         snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
 125
 126         ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
 127                                    iommu->prq_name, iommu);
 128         if (ret) {
 129                 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
 130                        iommu->name);
 131                 dmar_free_hwirq(irq);
 132                 goto err;
 133         }
 134         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
 135         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
 136         dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
 137
 138         return 0;
 139 }
 140
 141 int intel_svm_finish_prq(struct intel_iommu *iommu)
 142 {
 143         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
 144         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
 145         dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
 146
 147         free_irq(iommu->pr_irq, iommu);
 148         dmar_free_hwirq(iommu->pr_irq);
 149         iommu->pr_irq = 0;
 150
 151         free_pages((unsigned long)iommu->prq, PRQ_ORDER);
 152         iommu->prq = NULL;
 153
 154         return 0;
 155 }
 156
 157 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
 158                                        unsigned long address, unsigned long pages, int ih, int gl)
 159 {
 160         struct qi_desc desc;
 161
 162         if (pages == -1) {
 163                 /* For global kernel pages we have to flush them in *all* PASIDs
 164                  * because that's the only option the hardware gives us. Despite
 165                  * the fact that they are actually only accessible through one. */
 166                 if (gl)
 167                         desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 168                                 QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) | QI_EIOTLB_TYPE;
 169                 else
 170                         desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 171                                 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
 172                 desc.high = 0;
 173         } else {
 174                 int mask = ilog2(__roundup_pow_of_two(pages));
 175
 176                 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 177                         QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
 178                 desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(gl) |
 179                         QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask);
 180         }
 181         qi_submit_sync(&desc, svm->iommu);
 182
 183         if (sdev->dev_iotlb) {
 184                 desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) |
 185                         QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE;
 186                 if (pages == -1) {
 187                         desc.high = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) | QI_DEV_EIOTLB_SIZE;
 188                 } else if (pages > 1) {
 189                         /* The least significant zero bit indicates the size. So,
 190                          * for example, an "address" value of 0x12345f000 will
 191                          * flush from 0x123440000 to 0x12347ffff (256KiB). */
 192                         unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
 193                         unsigned long mask = __rounddown_pow_of_two(address ^ last);;
 194
 195                         desc.high = QI_DEV_EIOTLB_ADDR((address & ~mask) | (mask - 1)) | QI_DEV_EIOTLB_SIZE;
 196                 } else {
 197                         desc.high = QI_DEV_EIOTLB_ADDR(address);
 198                 }
 199                 qi_submit_sync(&desc, svm->iommu);
 200         }
 201 }
 202
 203 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
 204                                   unsigned long pages, int ih, int gl)
 205 {
 206         struct intel_svm_dev *sdev;
 207
 208         /* Try deferred invalidate if available */
 209         if (svm->iommu->pasid_state_table &&
 210             !cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
 211                 return;
 212
 213         rcu_read_lock();
 214         list_for_each_entry_rcu(sdev, &svm->devs, list)
 215                 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
 216         rcu_read_unlock();
 217 }
 218
 219 static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm,
 220                              unsigned long address, pte_t pte)
 221 {
 222         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 223
 224         intel_flush_svm_range(svm, address, 1, 1, 0);
 225 }
 226
 227 /* Pages have been freed at this point */
 228 static void intel_invalidate_range(struct mmu_notifier *mn,
 229                                    struct mm_struct *mm,
 230                                    unsigned long start, unsigned long end)
 231 {
 232         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 233
 234         intel_flush_svm_range(svm, start,
 235                               (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0);
 236 }
 237
 238
 239 static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev, int pasid)
 240 {
 241         struct qi_desc desc;
 242
 243         desc.high = 0;
 244         desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
 245
 246         qi_submit_sync(&desc, svm->iommu);
 247 }
 248
 249 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
 250 {
 251         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 252         struct intel_svm_dev *sdev;
 253
 254         /* This might end up being called from exit_mmap(), *before* the page
 255          * tables are cleared. And __mmu_notifier_release() will delete us from
 256          * the list of notifiers so that our invalidate_range() callback doesn't
 257          * get called when the page tables are cleared. So we need to protect
 258          * against hardware accessing those page tables.
 259          *
 260          * We do it by clearing the entry in the PASID table and then flushing
 261          * the IOTLB and the PASID table caches. This might upset hardware;
 262          * perhaps we'll want to point the PASID to a dummy PGD (like the zero
 263          * page) so that we end up taking a fault that the hardware really
 264          * *has* to handle gracefully without affecting other processes.
 265          */
 266         svm->iommu->pasid_table[svm->pasid].val = 0;
 267         wmb();
 268
 269         rcu_read_lock();
 270         list_for_each_entry_rcu(sdev, &svm->devs, list) {
 271                 intel_flush_pasid_dev(svm, sdev, svm->pasid);
 272                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 273         }
 274         rcu_read_unlock();
 275
 276 }
 277
 278 static const struct mmu_notifier_ops intel_mmuops = {
 279         .release = intel_mm_release,
 280         .change_pte = intel_change_pte,
 281         .invalidate_range = intel_invalidate_range,
 282 };
 283
 284 static DEFINE_MUTEX(pasid_mutex);
 285
 286 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
 287 {
 288         struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
 289         struct intel_svm_dev *sdev;
 290         struct intel_svm *svm = NULL;
 291         struct mm_struct *mm = NULL;
 292         int pasid_max;
 293         int ret;
 294
 295         if (WARN_ON(!iommu || !iommu->pasid_table))
 296                 return -EINVAL;
 297
 298         if (dev_is_pci(dev)) {
 299                 pasid_max = pci_max_pasids(to_pci_dev(dev));
 300                 if (pasid_max < 0)
 301                         return -EINVAL;
 302         } else
 303                 pasid_max = 1 << 20;
 304
 305         if ((flags & SVM_FLAG_SUPERVISOR_MODE)) {
 306                 if (!ecap_srs(iommu->ecap))
 307                         return -EINVAL;
 308         } else if (pasid) {
 309                 mm = get_task_mm(current);
 310                 BUG_ON(!mm);
 311         }
 312
 313         mutex_lock(&pasid_mutex);
 314         if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
 315                 int i;
 316
 317                 idr_for_each_entry(&iommu->pasid_idr, svm, i) {
 318                         if (svm->mm != mm ||
 319                             (svm->flags & SVM_FLAG_PRIVATE_PASID))
 320                                 continue;
 321
 322                         if (svm->pasid >= pasid_max) {
 323                                 dev_warn(dev,
 324                                          "Limited PASID width. Cannot use existing PASID %d\n",
 325                                          svm->pasid);
 326                                 ret = -ENOSPC;
 327                                 goto out;
 328                         }
 329
 330                         list_for_each_entry(sdev, &svm->devs, list) {
 331                                 if (dev == sdev->dev) {
 332                                         if (sdev->ops != ops) {
 333                                                 ret = -EBUSY;
 334                                                 goto out;
 335                                         }
 336                                         sdev->users++;
 337                                         goto success;
 338                                 }
 339                         }
 340
 341                         break;
 342                 }
 343         }
 344
 345         sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
 346         if (!sdev) {
 347                 ret = -ENOMEM;
 348                 goto out;
 349         }
 350         sdev->dev = dev;
 351
 352         ret = intel_iommu_enable_pasid(iommu, sdev);
 353         if (ret || !pasid) {
 354                 /* If they don't actually want to assign a PASID, this is
 355                  * just an enabling check/preparation. */
 356                 kfree(sdev);
 357                 goto out;
 358         }
 359         /* Finish the setup now we know we're keeping it */
 360         sdev->users = 1;
 361         sdev->ops = ops;
 362         init_rcu_head(&sdev->rcu);
 363
 364         if (!svm) {
 365                 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
 366                 if (!svm) {
 367                         ret = -ENOMEM;
 368                         kfree(sdev);
 369                         goto out;
 370                 }
 371                 svm->iommu = iommu;
 372
 373                 if (pasid_max > iommu->pasid_max)
 374                         pasid_max = iommu->pasid_max;
 375
 376                 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
 377                 ret = idr_alloc(&iommu->pasid_idr, svm,
 378                                 !!cap_caching_mode(iommu->cap),
 379                                 pasid_max - 1, GFP_KERNEL);
 380                 if (ret < 0) {
 381                         kfree(svm);
 382                         goto out;
 383                 }
 384                 svm->pasid = ret;
 385                 svm->notifier.ops = &intel_mmuops;
 386                 svm->mm = mm;
 387                 svm->flags = flags;
 388                 INIT_LIST_HEAD_RCU(&svm->devs);
 389                 ret = -ENOMEM;
 390                 if (mm) {
 391                         ret = mmu_notifier_register(&svm->notifier, mm);
 392                         if (ret) {
 393                                 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
 394                                 kfree(svm);
 395                                 kfree(sdev);
 396                                 goto out;
 397                         }
 398                         iommu->pasid_table[svm->pasid].val = (u64)__pa(mm->pgd) | 1;
 399                 } else
 400                         iommu->pasid_table[svm->pasid].val = (u64)__pa(init_mm.pgd) | 1 | (1ULL << 11);
 401                 wmb();
 402                 /* In caching mode, we still have to flush with PASID 0 when
 403                  * a PASID table entry becomes present. Not entirely clear
 404                  * *why* that would be the case — surely we could just issue
 405                  * a flush with the PASID value that we've changed? The PASID
 406                  * is the index into the table, after all. It's not like domain
 407                  * IDs in the case of the equivalent context-entry change in
 408                  * caching mode. And for that matter it's not entirely clear why
 409                  * a VMM would be in the business of caching the PASID table
 410                  * anyway. Surely that can be left entirely to the guest? */
 411                 if (cap_caching_mode(iommu->cap))
 412                         intel_flush_pasid_dev(svm, sdev, 0);
 413         }
 414         list_add_rcu(&sdev->list, &svm->devs);
 415
 416  success:
 417         *pasid = svm->pasid;
 418         ret = 0;
 419  out:
 420         mutex_unlock(&pasid_mutex);
 421         if (mm)
 422                 mmput(mm);
 423         return ret;
 424 }
 425 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
 426
 427 int intel_svm_unbind_mm(struct device *dev, int pasid)
 428 {
 429         struct intel_svm_dev *sdev;
 430         struct intel_iommu *iommu;
 431         struct intel_svm *svm;
 432         int ret = -EINVAL;
 433
 434         mutex_lock(&pasid_mutex);
 435         iommu = intel_svm_device_to_iommu(dev);
 436         if (!iommu || !iommu->pasid_table)
 437                 goto out;
 438
 439         svm = idr_find(&iommu->pasid_idr, pasid);
 440         if (!svm)
 441                 goto out;
 442
 443         list_for_each_entry(sdev, &svm->devs, list) {
 444                 if (dev == sdev->dev) {
 445                         ret = 0;
 446                         sdev->users--;
 447                         if (!sdev->users) {
 448                                 list_del_rcu(&sdev->list);
 449                                 /* Flush the PASID cache and IOTLB for this device.
 450                                  * Note that we do depend on the hardware *not* using
 451                                  * the PASID any more. Just as we depend on other
 452                                  * devices never using PASIDs that they have no right
 453                                  * to use. We have a *shared* PASID table, because it's
 454                                  * large and has to be physically contiguous. So it's
 455                                  * hard to be as defensive as we might like. */
 456                                 intel_flush_pasid_dev(svm, sdev, svm->pasid);
 457                                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 458                                 kfree_rcu(sdev, rcu);
 459
 460                                 if (list_empty(&svm->devs)) {
 461                                         svm->iommu->pasid_table[svm->pasid].val = 0;
 462                                         wmb();
 463
 464                                         idr_remove(&svm->iommu->pasid_idr, svm->pasid);
 465                                         if (svm->mm)
 466                                                 mmu_notifier_unregister(&svm->notifier, svm->mm);
 467
 468                                         /* We mandate that no page faults may be outstanding
 469                                          * for the PASID when intel_svm_unbind_mm() is called.
 470                                          * If that is not obeyed, subtle errors will happen.
 471                                          * Let's make them less subtle... */
 472                                         memset(svm, 0x6b, sizeof(*svm));
 473                                         kfree(svm);
 474                                 }
 475                         }
 476                         break;
 477                 }
 478         }
 479  out:
 480         mutex_unlock(&pasid_mutex);
 481
 482         return ret;
 483 }
 484 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
 485
 486 int intel_svm_is_pasid_valid(struct device *dev, int pasid)
 487 {
 488         struct intel_iommu *iommu;
 489         struct intel_svm *svm;
 490         int ret = -EINVAL;
 491
 492         mutex_lock(&pasid_mutex);
 493         iommu = intel_svm_device_to_iommu(dev);
 494         if (!iommu || !iommu->pasid_table)
 495                 goto out;
 496
 497         svm = idr_find(&iommu->pasid_idr, pasid);
 498         if (!svm)
 499                 goto out;
 500
 501         /* init_mm is used in this case */
 502         if (!svm->mm)
 503                 ret = 1;
 504         else if (atomic_read(&svm->mm->mm_users) > 0)
 505                 ret = 1;
 506         else
 507                 ret = 0;
 508
 509  out:
 510         mutex_unlock(&pasid_mutex);
 511
 512         return ret;
 513 }
 514 EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
 515
 516 /* Page request queue descriptor */
 517 struct page_req_dsc {
 518         u64 srr:1;
 519         u64 bof:1;
 520         u64 pasid_present:1;
 521         u64 lpig:1;
 522         u64 pasid:20;
 523         u64 bus:8;
 524         u64 private:23;
 525         u64 prg_index:9;
 526         u64 rd_req:1;
 527         u64 wr_req:1;
 528         u64 exe_req:1;
 529         u64 priv_req:1;
 530         u64 devfn:8;
 531         u64 addr:52;
 532 };
 533
 534 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
 535
 536 static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
 537 {
 538         unsigned long requested = 0;
 539
 540         if (req->exe_req)
 541                 requested |= VM_EXEC;
 542
 543         if (req->rd_req)
 544                 requested |= VM_READ;
 545
 546         if (req->wr_req)
 547                 requested |= VM_WRITE;
 548
 549         return (requested & ~vma->vm_flags) != 0;
 550 }
 551
 552 static bool is_canonical_address(u64 addr)
 553 {
 554         int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
 555         long saddr = (long) addr;
 556
 557         return (((saddr << shift) >> shift) == saddr);
 558 }
 559
 560 static irqreturn_t prq_event_thread(int irq, void *d)
 561 {
 562         struct intel_iommu *iommu = d;
 563         struct intel_svm *svm = NULL;
 564         int head, tail, handled = 0;
 565
 566         /* Clear PPR bit before reading head/tail registers, to
 567          * ensure that we get a new interrupt if needed. */
 568         writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
 569
 570         tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
 571         head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
 572         while (head != tail) {
 573                 struct intel_svm_dev *sdev;
 574                 struct vm_area_struct *vma;
 575                 struct page_req_dsc *req;
 576                 struct qi_desc resp;
 577                 int ret, result;
 578                 u64 address;
 579
 580                 handled = 1;
 581
 582                 req = &iommu->prq[head / sizeof(*req)];
 583
 584                 result = QI_RESP_FAILURE;
 585                 address = (u64)req->addr << VTD_PAGE_SHIFT;
 586                 if (!req->pasid_present) {
 587                         pr_err("%s: Page request without PASID: %08llx %08llx\n",
 588                                iommu->name, ((unsigned long long *)req)[0],
 589                                ((unsigned long long *)req)[1]);
 590                         goto bad_req;
 591                 }
 592
 593                 if (!svm || svm->pasid != req->pasid) {
 594                         rcu_read_lock();
 595                         svm = idr_find(&iommu->pasid_idr, req->pasid);
 596                         /* It *can't* go away, because the driver is not permitted
 597                          * to unbind the mm while any page faults are outstanding.
 598                          * So we only need RCU to protect the internal idr code. */
 599                         rcu_read_unlock();
 600
 601                         if (!svm) {
 602                                 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
 603                                        iommu->name, req->pasid, ((unsigned long long *)req)[0],
 604                                        ((unsigned long long *)req)[1]);
 605                                 goto no_pasid;
 606                         }
 607                 }
 608
 609                 result = QI_RESP_INVALID;
 610                 /* Since we're using init_mm.pgd directly, we should never take
 611                  * any faults on kernel addresses. */
 612                 if (!svm->mm)
 613                         goto bad_req;
 614                 /* If the mm is already defunct, don't handle faults. */
 615                 if (!mmget_not_zero(svm->mm))
 616                         goto bad_req;
 617
 618                 /* If address is not canonical, return invalid response */
 619                 if (!is_canonical_address(address))
 620                         goto bad_req;
 621
 622                 down_read(&svm->mm->mmap_sem);
 623                 vma = find_extend_vma(svm->mm, address);
 624                 if (!vma || address < vma->vm_start)
 625                         goto invalid;
 626
 627                 if (access_error(vma, req))
 628                         goto invalid;
 629
 630                 ret = handle_mm_fault(vma, address,
 631                                       req->wr_req ? FAULT_FLAG_WRITE : 0);
 632                 if (ret & VM_FAULT_ERROR)
 633                         goto invalid;
 634
 635                 result = QI_RESP_SUCCESS;
 636         invalid:
 637                 up_read(&svm->mm->mmap_sem);
 638                 mmput(svm->mm);
 639         bad_req:
 640                 /* Accounting for major/minor faults? */
 641                 rcu_read_lock();
 642                 list_for_each_entry_rcu(sdev, &svm->devs, list) {
 643                         if (sdev->sid == PCI_DEVID(req->bus, req->devfn))
 644                                 break;
 645                 }
 646                 /* Other devices can go away, but the drivers are not permitted
 647                  * to unbind while any page faults might be in flight. So it's
 648                  * OK to drop the 'lock' here now we have it. */
 649                 rcu_read_unlock();
 650
 651                 if (WARN_ON(&sdev->list == &svm->devs))
 652                         sdev = NULL;
 653
 654                 if (sdev && sdev->ops && sdev->ops->fault_cb) {
 655                         int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
 656                                 (req->exe_req << 1) | (req->priv_req);
 657                         sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result);
 658                 }
 659                 /* We get here in the error case where the PASID lookup failed,
 660                    and these can be NULL. Do not use them below this point! */
 661                 sdev = NULL;
 662                 svm = NULL;
 663         no_pasid:
 664                 if (req->lpig) {
 665                         /* Page Group Response */
 666                         resp.low = QI_PGRP_PASID(req->pasid) |
 667                                 QI_PGRP_DID((req->bus << 8) | req->devfn) |
 668                                 QI_PGRP_PASID_P(req->pasid_present) |
 669                                 QI_PGRP_RESP_TYPE;
 670                         resp.high = QI_PGRP_IDX(req->prg_index) |
 671                                 QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result);
 672
 673                         qi_submit_sync(&resp, iommu);
 674                 } else if (req->srr) {
 675                         /* Page Stream Response */
 676                         resp.low = QI_PSTRM_IDX(req->prg_index) |
 677                                 QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) |
 678                                 QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
 679                         resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) |
 680                                 QI_PSTRM_RESP_CODE(result);
 681
 682                         qi_submit_sync(&resp, iommu);
 683                 }
 684
 685                 head = (head + sizeof(*req)) & PRQ_RING_MASK;
 686         }
 687
 688         dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
 689
 690         return IRQ_RETVAL(handled);
 691 }