drivers/infiniband/hw/usnic/usnic_uiom.c

   1 /*
   2  * Copyright (c) 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2013 Cisco Systems.  All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/mm.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/sched/signal.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/hugetlb.h>
  40 #include <linux/iommu.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/list.h>
  43 #include <linux/pci.h>
  44 #include <rdma/ib_verbs.h>
  45
  46 #include "usnic_log.h"
  47 #include "usnic_uiom.h"
  48 #include "usnic_uiom_interval_tree.h"
  49
  50 #define USNIC_UIOM_PAGE_CHUNK                                           \
  51         ((PAGE_SIZE - offsetof(struct usnic_uiom_chunk, page_list))     /\
  52         ((void *) &((struct usnic_uiom_chunk *) 0)->page_list[1] -      \
  53         (void *) &((struct usnic_uiom_chunk *) 0)->page_list[0]))
  54
  55 static int usnic_uiom_dma_fault(struct iommu_domain *domain,
  56                                 struct device *dev,
  57                                 unsigned long iova, int flags,
  58                                 void *token)
  59 {
  60         usnic_err("Device %s iommu fault domain 0x%pK va 0x%lx flags 0x%x\n",
  61                 dev_name(dev),
  62                 domain, iova, flags);
  63         return -ENOSYS;
  64 }
  65
  66 static void usnic_uiom_put_pages(struct list_head *chunk_list, int dirty)
  67 {
  68         struct usnic_uiom_chunk *chunk, *tmp;
  69         struct page *page;
  70         struct scatterlist *sg;
  71         int i;
  72         dma_addr_t pa;
  73
  74         list_for_each_entry_safe(chunk, tmp, chunk_list, list) {
  75                 for_each_sg(chunk->page_list, sg, chunk->nents, i) {
  76                         page = sg_page(sg);
  77                         pa = sg_phys(sg);
  78                         if (dirty)
  79                                 put_user_pages_dirty_lock(&page, 1);
  80                         else
  81                                 put_user_page(page);
  82                         usnic_dbg("pa: %pa\n", &pa);
  83                 }
  84                 kfree(chunk);
  85         }
  86 }
  87
  88 static int usnic_uiom_get_pages(unsigned long addr, size_t size, int writable,
  89                                 int dmasync, struct usnic_uiom_reg *uiomr)
  90 {
  91         struct list_head *chunk_list = &uiomr->chunk_list;
  92         struct page **page_list;
  93         struct scatterlist *sg;
  94         struct usnic_uiom_chunk *chunk;
  95         unsigned long locked;
  96         unsigned long lock_limit;
  97         unsigned long cur_base;
  98         unsigned long npages;
  99         int ret;
 100         int off;
 101         int i;
 102         int flags;
 103         dma_addr_t pa;
 104         unsigned int gup_flags;
 105         struct mm_struct *mm;
 106
 107         /*
 108          * If the combination of the addr and size requested for this memory
 109          * region causes an integer overflow, return error.
 110          */
 111         if (((addr + size) < addr) || PAGE_ALIGN(addr + size) < (addr + size))
 112                 return -EINVAL;
 113
 114         if (!size)
 115                 return -EINVAL;
 116
 117         if (!can_do_mlock())
 118                 return -EPERM;
 119
 120         INIT_LIST_HEAD(chunk_list);
 121
 122         page_list = (struct page **) __get_free_page(GFP_KERNEL);
 123         if (!page_list)
 124                 return -ENOMEM;
 125
 126         npages = PAGE_ALIGN(size + (addr & ~PAGE_MASK)) >> PAGE_SHIFT;
 127
 128         uiomr->owning_mm = mm = current->mm;
 129         down_read(&mm->mmap_sem);
 130
 131         locked = atomic64_add_return(npages, &current->mm->pinned_vm);
 132         lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
 133
 134         if ((locked > lock_limit) && !capable(CAP_IPC_LOCK)) {
 135                 ret = -ENOMEM;
 136                 goto out;
 137         }
 138
 139         flags = IOMMU_READ | IOMMU_CACHE;
 140         flags |= (writable) ? IOMMU_WRITE : 0;
 141         gup_flags = FOLL_WRITE;
 142         gup_flags |= (writable) ? 0 : FOLL_FORCE;
 143         cur_base = addr & PAGE_MASK;
 144         ret = 0;
 145
 146         while (npages) {
 147                 ret = get_user_pages(cur_base,
 148                                      min_t(unsigned long, npages,
 149                                      PAGE_SIZE / sizeof(struct page *)),
 150                                      gup_flags | FOLL_LONGTERM,
 151                                      page_list, NULL);
 152
 153                 if (ret < 0)
 154                         goto out;
 155
 156                 npages -= ret;
 157                 off = 0;
 158
 159                 while (ret) {
 160                         chunk = kmalloc(struct_size(chunk, page_list,
 161                                         min_t(int, ret, USNIC_UIOM_PAGE_CHUNK)),
 162                                         GFP_KERNEL);
 163                         if (!chunk) {
 164                                 ret = -ENOMEM;
 165                                 goto out;
 166                         }
 167
 168                         chunk->nents = min_t(int, ret, USNIC_UIOM_PAGE_CHUNK);
 169                         sg_init_table(chunk->page_list, chunk->nents);
 170                         for_each_sg(chunk->page_list, sg, chunk->nents, i) {
 171                                 sg_set_page(sg, page_list[i + off],
 172                                                 PAGE_SIZE, 0);
 173                                 pa = sg_phys(sg);
 174                                 usnic_dbg("va: 0x%lx pa: %pa\n",
 175                                                 cur_base + i*PAGE_SIZE, &pa);
 176                         }
 177                         cur_base += chunk->nents * PAGE_SIZE;
 178                         ret -= chunk->nents;
 179                         off += chunk->nents;
 180                         list_add_tail(&chunk->list, chunk_list);
 181                 }
 182
 183                 ret = 0;
 184         }
 185
 186 out:
 187         if (ret < 0) {
 188                 usnic_uiom_put_pages(chunk_list, 0);
 189                 atomic64_sub(npages, &current->mm->pinned_vm);
 190         } else
 191                 mmgrab(uiomr->owning_mm);
 192
 193         up_read(&mm->mmap_sem);
 194         free_page((unsigned long) page_list);
 195         return ret;
 196 }
 197
 198 static void usnic_uiom_unmap_sorted_intervals(struct list_head *intervals,
 199                                                 struct usnic_uiom_pd *pd)
 200 {
 201         struct usnic_uiom_interval_node *interval, *tmp;
 202         long unsigned va, size;
 203
 204         list_for_each_entry_safe(interval, tmp, intervals, link) {
 205                 va = interval->start << PAGE_SHIFT;
 206                 size = ((interval->last - interval->start) + 1) << PAGE_SHIFT;
 207                 while (size > 0) {
 208                         /* Workaround for RH 970401 */
 209                         usnic_dbg("va 0x%lx size 0x%lx", va, PAGE_SIZE);
 210                         iommu_unmap(pd->domain, va, PAGE_SIZE);
 211                         va += PAGE_SIZE;
 212                         size -= PAGE_SIZE;
 213                 }
 214         }
 215 }
 216
 217 static void __usnic_uiom_reg_release(struct usnic_uiom_pd *pd,
 218                                         struct usnic_uiom_reg *uiomr,
 219                                         int dirty)
 220 {
 221         int npages;
 222         unsigned long vpn_start, vpn_last;
 223         struct usnic_uiom_interval_node *interval, *tmp;
 224         int writable = 0;
 225         LIST_HEAD(rm_intervals);
 226
 227         npages = PAGE_ALIGN(uiomr->length + uiomr->offset) >> PAGE_SHIFT;
 228         vpn_start = (uiomr->va & PAGE_MASK) >> PAGE_SHIFT;
 229         vpn_last = vpn_start + npages - 1;
 230
 231         spin_lock(&pd->lock);
 232         usnic_uiom_remove_interval(&pd->root, vpn_start,
 233                                         vpn_last, &rm_intervals);
 234         usnic_uiom_unmap_sorted_intervals(&rm_intervals, pd);
 235
 236         list_for_each_entry_safe(interval, tmp, &rm_intervals, link) {
 237                 if (interval->flags & IOMMU_WRITE)
 238                         writable = 1;
 239                 list_del(&interval->link);
 240                 kfree(interval);
 241         }
 242
 243         usnic_uiom_put_pages(&uiomr->chunk_list, dirty & writable);
 244         spin_unlock(&pd->lock);
 245 }
 246
 247 static int usnic_uiom_map_sorted_intervals(struct list_head *intervals,
 248                                                 struct usnic_uiom_reg *uiomr)
 249 {
 250         int i, err;
 251         size_t size;
 252         struct usnic_uiom_chunk *chunk;
 253         struct usnic_uiom_interval_node *interval_node;
 254         dma_addr_t pa;
 255         dma_addr_t pa_start = 0;
 256         dma_addr_t pa_end = 0;
 257         long int va_start = -EINVAL;
 258         struct usnic_uiom_pd *pd = uiomr->pd;
 259         long int va = uiomr->va & PAGE_MASK;
 260         int flags = IOMMU_READ | IOMMU_CACHE;
 261
 262         flags |= (uiomr->writable) ? IOMMU_WRITE : 0;
 263         chunk = list_first_entry(&uiomr->chunk_list, struct usnic_uiom_chunk,
 264                                                                         list);
 265         list_for_each_entry(interval_node, intervals, link) {
 266 iter_chunk:
 267                 for (i = 0; i < chunk->nents; i++, va += PAGE_SIZE) {
 268                         pa = sg_phys(&chunk->page_list[i]);
 269                         if ((va >> PAGE_SHIFT) < interval_node->start)
 270                                 continue;
 271
 272                         if ((va >> PAGE_SHIFT) == interval_node->start) {
 273                                 /* First page of the interval */
 274                                 va_start = va;
 275                                 pa_start = pa;
 276                                 pa_end = pa;
 277                         }
 278
 279                         WARN_ON(va_start == -EINVAL);
 280
 281                         if ((pa_end + PAGE_SIZE != pa) &&
 282                                         (pa != pa_start)) {
 283                                 /* PAs are not contiguous */
 284                                 size = pa_end - pa_start + PAGE_SIZE;
 285                                 usnic_dbg("va 0x%lx pa %pa size 0x%zx flags 0x%x",
 286                                         va_start, &pa_start, size, flags);
 287                                 err = iommu_map(pd->domain, va_start, pa_start,
 288                                                         size, flags);
 289                                 if (err) {
 290                                         usnic_err("Failed to map va 0x%lx pa %pa size 0x%zx with err %d\n",
 291                                                 va_start, &pa_start, size, err);
 292                                         goto err_out;
 293                                 }
 294                                 va_start = va;
 295                                 pa_start = pa;
 296                                 pa_end = pa;
 297                         }
 298
 299                         if ((va >> PAGE_SHIFT) == interval_node->last) {
 300                                 /* Last page of the interval */
 301                                 size = pa - pa_start + PAGE_SIZE;
 302                                 usnic_dbg("va 0x%lx pa %pa size 0x%zx flags 0x%x\n",
 303                                         va_start, &pa_start, size, flags);
 304                                 err = iommu_map(pd->domain, va_start, pa_start,
 305                                                 size, flags);
 306                                 if (err) {
 307                                         usnic_err("Failed to map va 0x%lx pa %pa size 0x%zx with err %d\n",
 308                                                 va_start, &pa_start, size, err);
 309                                         goto err_out;
 310                                 }
 311                                 break;
 312                         }
 313
 314                         if (pa != pa_start)
 315                                 pa_end += PAGE_SIZE;
 316                 }
 317
 318                 if (i == chunk->nents) {
 319                         /*
 320                          * Hit last entry of the chunk,
 321                          * hence advance to next chunk
 322                          */
 323                         chunk = list_first_entry(&chunk->list,
 324                                                         struct usnic_uiom_chunk,
 325                                                         list);
 326                         goto iter_chunk;
 327                 }
 328         }
 329
 330         return 0;
 331
 332 err_out:
 333         usnic_uiom_unmap_sorted_intervals(intervals, pd);
 334         return err;
 335 }
 336
 337 struct usnic_uiom_reg *usnic_uiom_reg_get(struct usnic_uiom_pd *pd,
 338                                                 unsigned long addr, size_t size,
 339                                                 int writable, int dmasync)
 340 {
 341         struct usnic_uiom_reg *uiomr;
 342         unsigned long va_base, vpn_start, vpn_last;
 343         unsigned long npages;
 344         int offset, err;
 345         LIST_HEAD(sorted_diff_intervals);
 346
 347         /*
 348          * Intel IOMMU map throws an error if a translation entry is
 349          * changed from read to write.  This module may not unmap
 350          * and then remap the entry after fixing the permission
 351          * b/c this open up a small windows where hw DMA may page fault
 352          * Hence, make all entries to be writable.
 353          */
 354         writable = 1;
 355
 356         va_base = addr & PAGE_MASK;
 357         offset = addr & ~PAGE_MASK;
 358         npages = PAGE_ALIGN(size + offset) >> PAGE_SHIFT;
 359         vpn_start = (addr & PAGE_MASK) >> PAGE_SHIFT;
 360         vpn_last = vpn_start + npages - 1;
 361
 362         uiomr = kmalloc(sizeof(*uiomr), GFP_KERNEL);
 363         if (!uiomr)
 364                 return ERR_PTR(-ENOMEM);
 365
 366         uiomr->va = va_base;
 367         uiomr->offset = offset;
 368         uiomr->length = size;
 369         uiomr->writable = writable;
 370         uiomr->pd = pd;
 371
 372         err = usnic_uiom_get_pages(addr, size, writable, dmasync,
 373                                    uiomr);
 374         if (err) {
 375                 usnic_err("Failed get_pages vpn [0x%lx,0x%lx] err %d\n",
 376                                 vpn_start, vpn_last, err);
 377                 goto out_free_uiomr;
 378         }
 379
 380         spin_lock(&pd->lock);
 381         err = usnic_uiom_get_intervals_diff(vpn_start, vpn_last,
 382                                                 (writable) ? IOMMU_WRITE : 0,
 383                                                 IOMMU_WRITE,
 384                                                 &pd->root,
 385                                                 &sorted_diff_intervals);
 386         if (err) {
 387                 usnic_err("Failed disjoint interval vpn [0x%lx,0x%lx] err %d\n",
 388                                                 vpn_start, vpn_last, err);
 389                 goto out_put_pages;
 390         }
 391
 392         err = usnic_uiom_map_sorted_intervals(&sorted_diff_intervals, uiomr);
 393         if (err) {
 394                 usnic_err("Failed map interval vpn [0x%lx,0x%lx] err %d\n",
 395                                                 vpn_start, vpn_last, err);
 396                 goto out_put_intervals;
 397
 398         }
 399
 400         err = usnic_uiom_insert_interval(&pd->root, vpn_start, vpn_last,
 401                                         (writable) ? IOMMU_WRITE : 0);
 402         if (err) {
 403                 usnic_err("Failed insert interval vpn [0x%lx,0x%lx] err %d\n",
 404                                                 vpn_start, vpn_last, err);
 405                 goto out_unmap_intervals;
 406         }
 407
 408         usnic_uiom_put_interval_set(&sorted_diff_intervals);
 409         spin_unlock(&pd->lock);
 410
 411         return uiomr;
 412
 413 out_unmap_intervals:
 414         usnic_uiom_unmap_sorted_intervals(&sorted_diff_intervals, pd);
 415 out_put_intervals:
 416         usnic_uiom_put_interval_set(&sorted_diff_intervals);
 417 out_put_pages:
 418         usnic_uiom_put_pages(&uiomr->chunk_list, 0);
 419         spin_unlock(&pd->lock);
 420         mmdrop(uiomr->owning_mm);
 421 out_free_uiomr:
 422         kfree(uiomr);
 423         return ERR_PTR(err);
 424 }
 425
 426 static void __usnic_uiom_release_tail(struct usnic_uiom_reg *uiomr)
 427 {
 428         mmdrop(uiomr->owning_mm);
 429         kfree(uiomr);
 430 }
 431
 432 static inline size_t usnic_uiom_num_pages(struct usnic_uiom_reg *uiomr)
 433 {
 434         return PAGE_ALIGN(uiomr->length + uiomr->offset) >> PAGE_SHIFT;
 435 }
 436
 437 void usnic_uiom_reg_release(struct usnic_uiom_reg *uiomr)
 438 {
 439         __usnic_uiom_reg_release(uiomr->pd, uiomr, 1);
 440
 441         atomic64_sub(usnic_uiom_num_pages(uiomr), &uiomr->owning_mm->pinned_vm);
 442         __usnic_uiom_release_tail(uiomr);
 443 }
 444
 445 struct usnic_uiom_pd *usnic_uiom_alloc_pd(void)
 446 {
 447         struct usnic_uiom_pd *pd;
 448         void *domain;
 449
 450         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 451         if (!pd)
 452                 return ERR_PTR(-ENOMEM);
 453
 454         pd->domain = domain = iommu_domain_alloc(&pci_bus_type);
 455         if (!domain) {
 456                 usnic_err("Failed to allocate IOMMU domain");
 457                 kfree(pd);
 458                 return ERR_PTR(-ENOMEM);
 459         }
 460
 461         iommu_set_fault_handler(pd->domain, usnic_uiom_dma_fault, NULL);
 462
 463         spin_lock_init(&pd->lock);
 464         INIT_LIST_HEAD(&pd->devs);
 465
 466         return pd;
 467 }
 468
 469 void usnic_uiom_dealloc_pd(struct usnic_uiom_pd *pd)
 470 {
 471         iommu_domain_free(pd->domain);
 472         kfree(pd);
 473 }
 474
 475 int usnic_uiom_attach_dev_to_pd(struct usnic_uiom_pd *pd, struct device *dev)
 476 {
 477         struct usnic_uiom_dev *uiom_dev;
 478         int err;
 479
 480         uiom_dev = kzalloc(sizeof(*uiom_dev), GFP_ATOMIC);
 481         if (!uiom_dev)
 482                 return -ENOMEM;
 483         uiom_dev->dev = dev;
 484
 485         err = iommu_attach_device(pd->domain, dev);
 486         if (err)
 487                 goto out_free_dev;
 488
 489         if (!iommu_capable(dev->bus, IOMMU_CAP_CACHE_COHERENCY)) {
 490                 usnic_err("IOMMU of %s does not support cache coherency\n",
 491                                 dev_name(dev));
 492                 err = -EINVAL;
 493                 goto out_detach_device;
 494         }
 495
 496         spin_lock(&pd->lock);
 497         list_add_tail(&uiom_dev->link, &pd->devs);
 498         pd->dev_cnt++;
 499         spin_unlock(&pd->lock);
 500
 501         return 0;
 502
 503 out_detach_device:
 504         iommu_detach_device(pd->domain, dev);
 505 out_free_dev:
 506         kfree(uiom_dev);
 507         return err;
 508 }
 509
 510 void usnic_uiom_detach_dev_from_pd(struct usnic_uiom_pd *pd, struct device *dev)
 511 {
 512         struct usnic_uiom_dev *uiom_dev;
 513         int found = 0;
 514
 515         spin_lock(&pd->lock);
 516         list_for_each_entry(uiom_dev, &pd->devs, link) {
 517                 if (uiom_dev->dev == dev) {
 518                         found = 1;
 519                         break;
 520                 }
 521         }
 522
 523         if (!found) {
 524                 usnic_err("Unable to free dev %s - not found\n",
 525                                 dev_name(dev));
 526                 spin_unlock(&pd->lock);
 527                 return;
 528         }
 529
 530         list_del(&uiom_dev->link);
 531         pd->dev_cnt--;
 532         spin_unlock(&pd->lock);
 533
 534         return iommu_detach_device(pd->domain, dev);
 535 }
 536
 537 struct device **usnic_uiom_get_dev_list(struct usnic_uiom_pd *pd)
 538 {
 539         struct usnic_uiom_dev *uiom_dev;
 540         struct device **devs;
 541         int i = 0;
 542
 543         spin_lock(&pd->lock);
 544         devs = kcalloc(pd->dev_cnt + 1, sizeof(*devs), GFP_ATOMIC);
 545         if (!devs) {
 546                 devs = ERR_PTR(-ENOMEM);
 547                 goto out;
 548         }
 549
 550         list_for_each_entry(uiom_dev, &pd->devs, link) {
 551                 devs[i++] = uiom_dev->dev;
 552         }
 553 out:
 554         spin_unlock(&pd->lock);
 555         return devs;
 556 }
 557
 558 void usnic_uiom_free_dev_list(struct device **devs)
 559 {
 560         kfree(devs);
 561 }
 562
 563 int usnic_uiom_init(char *drv_name)
 564 {
 565         if (!iommu_present(&pci_bus_type)) {
 566                 usnic_err("IOMMU required but not present or enabled.  USNIC QPs will not function w/o enabling IOMMU\n");
 567                 return -EPERM;
 568         }
 569
 570         return 0;
 571 }