drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include "mlx5_ib.h"
  38
  39 /* not supported currently */
  40 static int wq_signature;
  41
  42 enum {
  43         MLX5_IB_ACK_REQ_FREQ    = 8,
  44 };
  45
  46 enum {
  47         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  48         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  49         MLX5_IB_LINK_TYPE_IB            = 0,
  50         MLX5_IB_LINK_TYPE_ETH           = 1
  51 };
  52
  53 enum {
  54         MLX5_IB_SQ_STRIDE       = 6,
  55 };
  56
  57 static const u32 mlx5_ib_opcode[] = {
  58         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  59         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  60         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  61         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  62         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  63         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  64         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  65         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  66         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  67         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  68         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  69         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  70         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  71         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  72 };
  73
  74 struct mlx5_wqe_eth_pad {
  75         u8 rsvd0[16];
  76 };
  77
  78 enum raw_qp_set_mask_map {
  79         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  80         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  81 };
  82
  83 struct mlx5_modify_raw_qp_param {
  84         u16 operation;
  85
  86         u32 set_mask; /* raw_qp_set_mask_map */
  87         u32 rate_limit;
  88         u8 rq_q_ctr_id;
  89 };
  90
  91 static void get_cqs(enum ib_qp_type qp_type,
  92                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  93                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
  94
  95 static int is_qp0(enum ib_qp_type qp_type)
  96 {
  97         return qp_type == IB_QPT_SMI;
  98 }
  99
 100 static int is_sqp(enum ib_qp_type qp_type)
 101 {
 102         return is_qp0(qp_type) || is_qp1(qp_type);
 103 }
 104
 105 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
 106 {
 107         return mlx5_buf_offset(&qp->buf, offset);
 108 }
 109
 110 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 111 {
 112         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 113 }
 114
 115 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 116 {
 117         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 118 }
 119
 120 /**
 121  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 122  *
 123  * @qp: QP to copy from.
 124  * @send: copy from the send queue when non-zero, use the receive queue
 125  *        otherwise.
 126  * @wqe_index:  index to start copying from. For send work queues, the
 127  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 128  *              For receive work queue, it is the number of work queue
 129  *              element in the queue.
 130  * @buffer: destination buffer.
 131  * @length: maximum number of bytes to copy.
 132  *
 133  * Copies at least a single WQE, but may copy more data.
 134  *
 135  * Return: the number of bytes copied, or an error code.
 136  */
 137 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 138                           void *buffer, u32 length,
 139                           struct mlx5_ib_qp_base *base)
 140 {
 141         struct ib_device *ibdev = qp->ibqp.device;
 142         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 143         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 144         size_t offset;
 145         size_t wq_end;
 146         struct ib_umem *umem = base->ubuffer.umem;
 147         u32 first_copy_length;
 148         int wqe_length;
 149         int ret;
 150
 151         if (wq->wqe_cnt == 0) {
 152                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 153                             qp->ibqp.qp_type);
 154                 return -EINVAL;
 155         }
 156
 157         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 158         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 159
 160         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 161                 return -EINVAL;
 162
 163         if (offset > umem->length ||
 164             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 165                 return -EINVAL;
 166
 167         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 168         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 169         if (ret)
 170                 return ret;
 171
 172         if (send) {
 173                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 174                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 175
 176                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 177         } else {
 178                 wqe_length = 1 << wq->wqe_shift;
 179         }
 180
 181         if (wqe_length <= first_copy_length)
 182                 return first_copy_length;
 183
 184         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 185                                 wqe_length - first_copy_length);
 186         if (ret)
 187                 return ret;
 188
 189         return wqe_length;
 190 }
 191
 192 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 193 {
 194         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 195         struct ib_event event;
 196
 197         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 198                 /* This event is only valid for trans_qps */
 199                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 200         }
 201
 202         if (ibqp->event_handler) {
 203                 event.device     = ibqp->device;
 204                 event.element.qp = ibqp;
 205                 switch (type) {
 206                 case MLX5_EVENT_TYPE_PATH_MIG:
 207                         event.event = IB_EVENT_PATH_MIG;
 208                         break;
 209                 case MLX5_EVENT_TYPE_COMM_EST:
 210                         event.event = IB_EVENT_COMM_EST;
 211                         break;
 212                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 213                         event.event = IB_EVENT_SQ_DRAINED;
 214                         break;
 215                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 216                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 217                         break;
 218                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 219                         event.event = IB_EVENT_QP_FATAL;
 220                         break;
 221                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 222                         event.event = IB_EVENT_PATH_MIG_ERR;
 223                         break;
 224                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 225                         event.event = IB_EVENT_QP_REQ_ERR;
 226                         break;
 227                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 228                         event.event = IB_EVENT_QP_ACCESS_ERR;
 229                         break;
 230                 default:
 231                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 232                         return;
 233                 }
 234
 235                 ibqp->event_handler(&event, ibqp->qp_context);
 236         }
 237 }
 238
 239 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 240                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 241 {
 242         int wqe_size;
 243         int wq_size;
 244
 245         /* Sanity check RQ size before proceeding */
 246         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 247                 return -EINVAL;
 248
 249         if (!has_rq) {
 250                 qp->rq.max_gs = 0;
 251                 qp->rq.wqe_cnt = 0;
 252                 qp->rq.wqe_shift = 0;
 253                 cap->max_recv_wr = 0;
 254                 cap->max_recv_sge = 0;
 255         } else {
 256                 if (ucmd) {
 257                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 258                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 259                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 260                         qp->rq.max_post = qp->rq.wqe_cnt;
 261                 } else {
 262                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 263                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 264                         wqe_size = roundup_pow_of_two(wqe_size);
 265                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 266                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 267                         qp->rq.wqe_cnt = wq_size / wqe_size;
 268                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 269                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 270                                             wqe_size,
 271                                             MLX5_CAP_GEN(dev->mdev,
 272                                                          max_wqe_sz_rq));
 273                                 return -EINVAL;
 274                         }
 275                         qp->rq.wqe_shift = ilog2(wqe_size);
 276                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 277                         qp->rq.max_post = qp->rq.wqe_cnt;
 278                 }
 279         }
 280
 281         return 0;
 282 }
 283
 284 static int sq_overhead(struct ib_qp_init_attr *attr)
 285 {
 286         int size = 0;
 287
 288         switch (attr->qp_type) {
 289         case IB_QPT_XRC_INI:
 290                 size += sizeof(struct mlx5_wqe_xrc_seg);
 291                 /* fall through */
 292         case IB_QPT_RC:
 293                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 294                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 295                             sizeof(struct mlx5_wqe_raddr_seg),
 296                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 297                             sizeof(struct mlx5_mkey_seg));
 298                 break;
 299
 300         case IB_QPT_XRC_TGT:
 301                 return 0;
 302
 303         case IB_QPT_UC:
 304                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 305                         max(sizeof(struct mlx5_wqe_raddr_seg),
 306                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 307                             sizeof(struct mlx5_mkey_seg));
 308                 break;
 309
 310         case IB_QPT_UD:
 311                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 312                         size += sizeof(struct mlx5_wqe_eth_pad) +
 313                                 sizeof(struct mlx5_wqe_eth_seg);
 314                 /* fall through */
 315         case IB_QPT_SMI:
 316         case MLX5_IB_QPT_HW_GSI:
 317                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 318                         sizeof(struct mlx5_wqe_datagram_seg);
 319                 break;
 320
 321         case MLX5_IB_QPT_REG_UMR:
 322                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 323                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 324                         sizeof(struct mlx5_mkey_seg);
 325                 break;
 326
 327         default:
 328                 return -EINVAL;
 329         }
 330
 331         return size;
 332 }
 333
 334 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 335 {
 336         int inl_size = 0;
 337         int size;
 338
 339         size = sq_overhead(attr);
 340         if (size < 0)
 341                 return size;
 342
 343         if (attr->cap.max_inline_data) {
 344                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 345                         attr->cap.max_inline_data;
 346         }
 347
 348         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 349         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 350             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 351                         return MLX5_SIG_WQE_SIZE;
 352         else
 353                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 354 }
 355
 356 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 357 {
 358         int max_sge;
 359
 360         if (attr->qp_type == IB_QPT_RC)
 361                 max_sge = (min_t(int, wqe_size, 512) -
 362                            sizeof(struct mlx5_wqe_ctrl_seg) -
 363                            sizeof(struct mlx5_wqe_raddr_seg)) /
 364                         sizeof(struct mlx5_wqe_data_seg);
 365         else if (attr->qp_type == IB_QPT_XRC_INI)
 366                 max_sge = (min_t(int, wqe_size, 512) -
 367                            sizeof(struct mlx5_wqe_ctrl_seg) -
 368                            sizeof(struct mlx5_wqe_xrc_seg) -
 369                            sizeof(struct mlx5_wqe_raddr_seg)) /
 370                         sizeof(struct mlx5_wqe_data_seg);
 371         else
 372                 max_sge = (wqe_size - sq_overhead(attr)) /
 373                         sizeof(struct mlx5_wqe_data_seg);
 374
 375         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 376                      sizeof(struct mlx5_wqe_data_seg));
 377 }
 378
 379 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 380                         struct mlx5_ib_qp *qp)
 381 {
 382         int wqe_size;
 383         int wq_size;
 384
 385         if (!attr->cap.max_send_wr)
 386                 return 0;
 387
 388         wqe_size = calc_send_wqe(attr);
 389         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 390         if (wqe_size < 0)
 391                 return wqe_size;
 392
 393         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 394                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 395                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 396                 return -EINVAL;
 397         }
 398
 399         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 400                               sizeof(struct mlx5_wqe_inline_seg);
 401         attr->cap.max_inline_data = qp->max_inline_data;
 402
 403         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 404                 qp->signature_en = true;
 405
 406         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 407         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 408         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 409                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 410                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 411                             qp->sq.wqe_cnt,
 412                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 413                 return -ENOMEM;
 414         }
 415         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 416         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 417         if (qp->sq.max_gs < attr->cap.max_send_sge)
 418                 return -ENOMEM;
 419
 420         attr->cap.max_send_sge = qp->sq.max_gs;
 421         qp->sq.max_post = wq_size / wqe_size;
 422         attr->cap.max_send_wr = qp->sq.max_post;
 423
 424         return wq_size;
 425 }
 426
 427 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 428                             struct mlx5_ib_qp *qp,
 429                             struct mlx5_ib_create_qp *ucmd,
 430                             struct mlx5_ib_qp_base *base,
 431                             struct ib_qp_init_attr *attr)
 432 {
 433         int desc_sz = 1 << qp->sq.wqe_shift;
 434
 435         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 436                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 437                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 438                 return -EINVAL;
 439         }
 440
 441         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 442                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 443                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 444                 return -EINVAL;
 445         }
 446
 447         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 448
 449         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 450                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 451                              qp->sq.wqe_cnt,
 452                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 453                 return -EINVAL;
 454         }
 455
 456         if (attr->qp_type == IB_QPT_RAW_PACKET) {
 457                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 458                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 459         } else {
 460                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 461                                          (qp->sq.wqe_cnt << 6);
 462         }
 463
 464         return 0;
 465 }
 466
 467 static int qp_has_rq(struct ib_qp_init_attr *attr)
 468 {
 469         if (attr->qp_type == IB_QPT_XRC_INI ||
 470             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 471             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 472             !attr->cap.max_recv_wr)
 473                 return 0;
 474
 475         return 1;
 476 }
 477
 478 static int first_med_uuar(void)
 479 {
 480         return 1;
 481 }
 482
 483 static int next_uuar(int n)
 484 {
 485         n++;
 486
 487         while (((n % 4) & 2))
 488                 n++;
 489
 490         return n;
 491 }
 492
 493 static int num_med_uuar(struct mlx5_uuar_info *uuari)
 494 {
 495         int n;
 496
 497         n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
 498                 uuari->num_low_latency_uuars - 1;
 499
 500         return n >= 0 ? n : 0;
 501 }
 502
 503 static int max_uuari(struct mlx5_uuar_info *uuari)
 504 {
 505         return uuari->num_uars * 4;
 506 }
 507
 508 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
 509 {
 510         int med;
 511         int i;
 512         int t;
 513
 514         med = num_med_uuar(uuari);
 515         for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
 516                 t++;
 517                 if (t == med)
 518                         return next_uuar(i);
 519         }
 520
 521         return 0;
 522 }
 523
 524 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
 525 {
 526         int i;
 527
 528         for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
 529                 if (!test_bit(i, uuari->bitmap)) {
 530                         set_bit(i, uuari->bitmap);
 531                         uuari->count[i]++;
 532                         return i;
 533                 }
 534         }
 535
 536         return -ENOMEM;
 537 }
 538
 539 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
 540 {
 541         int minidx = first_med_uuar();
 542         int i;
 543
 544         for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
 545                 if (uuari->count[i] < uuari->count[minidx])
 546                         minidx = i;
 547         }
 548
 549         uuari->count[minidx]++;
 550         return minidx;
 551 }
 552
 553 static int alloc_uuar(struct mlx5_uuar_info *uuari,
 554                       enum mlx5_ib_latency_class lat)
 555 {
 556         int uuarn = -EINVAL;
 557
 558         mutex_lock(&uuari->lock);
 559         switch (lat) {
 560         case MLX5_IB_LATENCY_CLASS_LOW:
 561                 uuarn = 0;
 562                 uuari->count[uuarn]++;
 563                 break;
 564
 565         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 566                 if (uuari->ver < 2)
 567                         uuarn = -ENOMEM;
 568                 else
 569                         uuarn = alloc_med_class_uuar(uuari);
 570                 break;
 571
 572         case MLX5_IB_LATENCY_CLASS_HIGH:
 573                 if (uuari->ver < 2)
 574                         uuarn = -ENOMEM;
 575                 else
 576                         uuarn = alloc_high_class_uuar(uuari);
 577                 break;
 578
 579         case MLX5_IB_LATENCY_CLASS_FAST_PATH:
 580                 uuarn = 2;
 581                 break;
 582         }
 583         mutex_unlock(&uuari->lock);
 584
 585         return uuarn;
 586 }
 587
 588 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 589 {
 590         clear_bit(uuarn, uuari->bitmap);
 591         --uuari->count[uuarn];
 592 }
 593
 594 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 595 {
 596         clear_bit(uuarn, uuari->bitmap);
 597         --uuari->count[uuarn];
 598 }
 599
 600 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 601 {
 602         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 603         int high_uuar = nuuars - uuari->num_low_latency_uuars;
 604
 605         mutex_lock(&uuari->lock);
 606         if (uuarn == 0) {
 607                 --uuari->count[uuarn];
 608                 goto out;
 609         }
 610
 611         if (uuarn < high_uuar) {
 612                 free_med_class_uuar(uuari, uuarn);
 613                 goto out;
 614         }
 615
 616         free_high_class_uuar(uuari, uuarn);
 617
 618 out:
 619         mutex_unlock(&uuari->lock);
 620 }
 621
 622 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 623 {
 624         switch (state) {
 625         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 626         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 627         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 628         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 629         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 630         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 631         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 632         default:                return -1;
 633         }
 634 }
 635
 636 static int to_mlx5_st(enum ib_qp_type type)
 637 {
 638         switch (type) {
 639         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 640         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 641         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 642         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 643         case IB_QPT_XRC_INI:
 644         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 645         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 646         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 647         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 648         case IB_QPT_RAW_PACKET:
 649         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 650         case IB_QPT_MAX:
 651         default:                return -EINVAL;
 652         }
 653 }
 654
 655 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 656                              struct mlx5_ib_cq *recv_cq);
 657 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 658                                struct mlx5_ib_cq *recv_cq);
 659
 660 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
 661 {
 662         return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
 663 }
 664
 665 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 666                             struct ib_pd *pd,
 667                             unsigned long addr, size_t size,
 668                             struct ib_umem **umem,
 669                             int *npages, int *page_shift, int *ncont,
 670                             u32 *offset)
 671 {
 672         int err;
 673
 674         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 675         if (IS_ERR(*umem)) {
 676                 mlx5_ib_dbg(dev, "umem_get failed\n");
 677                 return PTR_ERR(*umem);
 678         }
 679
 680         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 681
 682         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 683         if (err) {
 684                 mlx5_ib_warn(dev, "bad offset\n");
 685                 goto err_umem;
 686         }
 687
 688         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 689                     addr, size, *npages, *page_shift, *ncont, *offset);
 690
 691         return 0;
 692
 693 err_umem:
 694         ib_umem_release(*umem);
 695         *umem = NULL;
 696
 697         return err;
 698 }
 699
 700 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
 701 {
 702         struct mlx5_ib_ucontext *context;
 703
 704         context = to_mucontext(pd->uobject->context);
 705         mlx5_ib_db_unmap_user(context, &rwq->db);
 706         if (rwq->umem)
 707                 ib_umem_release(rwq->umem);
 708 }
 709
 710 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 711                           struct mlx5_ib_rwq *rwq,
 712                           struct mlx5_ib_create_wq *ucmd)
 713 {
 714         struct mlx5_ib_ucontext *context;
 715         int page_shift = 0;
 716         int npages;
 717         u32 offset = 0;
 718         int ncont = 0;
 719         int err;
 720
 721         if (!ucmd->buf_addr)
 722                 return -EINVAL;
 723
 724         context = to_mucontext(pd->uobject->context);
 725         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 726                                rwq->buf_size, 0, 0);
 727         if (IS_ERR(rwq->umem)) {
 728                 mlx5_ib_dbg(dev, "umem_get failed\n");
 729                 err = PTR_ERR(rwq->umem);
 730                 return err;
 731         }
 732
 733         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 734                            &ncont, NULL);
 735         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 736                                      &rwq->rq_page_offset);
 737         if (err) {
 738                 mlx5_ib_warn(dev, "bad offset\n");
 739                 goto err_umem;
 740         }
 741
 742         rwq->rq_num_pas = ncont;
 743         rwq->page_shift = page_shift;
 744         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 745         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 746
 747         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 748                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 749                     npages, page_shift, ncont, offset);
 750
 751         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 752         if (err) {
 753                 mlx5_ib_dbg(dev, "map failed\n");
 754                 goto err_umem;
 755         }
 756
 757         rwq->create_type = MLX5_WQ_USER;
 758         return 0;
 759
 760 err_umem:
 761         ib_umem_release(rwq->umem);
 762         return err;
 763 }
 764
 765 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 766                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 767                           struct ib_qp_init_attr *attr,
 768                           u32 **in,
 769                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 770                           struct mlx5_ib_qp_base *base)
 771 {
 772         struct mlx5_ib_ucontext *context;
 773         struct mlx5_ib_create_qp ucmd;
 774         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 775         int page_shift = 0;
 776         int uar_index;
 777         int npages;
 778         u32 offset = 0;
 779         int uuarn;
 780         int ncont = 0;
 781         __be64 *pas;
 782         void *qpc;
 783         int err;
 784
 785         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 786         if (err) {
 787                 mlx5_ib_dbg(dev, "copy failed\n");
 788                 return err;
 789         }
 790
 791         context = to_mucontext(pd->uobject->context);
 792         /*
 793          * TBD: should come from the verbs when we have the API
 794          */
 795         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
 796                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 797                 uuarn = MLX5_CROSS_CHANNEL_UUAR;
 798         else {
 799                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
 800                 if (uuarn < 0) {
 801                         mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
 802                         mlx5_ib_dbg(dev, "reverting to medium latency\n");
 803                         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
 804                         if (uuarn < 0) {
 805                                 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
 806                                 mlx5_ib_dbg(dev, "reverting to high latency\n");
 807                                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
 808                                 if (uuarn < 0) {
 809                                         mlx5_ib_warn(dev, "uuar allocation failed\n");
 810                                         return uuarn;
 811                                 }
 812                         }
 813                 }
 814         }
 815
 816         uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
 817         mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
 818
 819         qp->rq.offset = 0;
 820         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 821         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 822
 823         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 824         if (err)
 825                 goto err_uuar;
 826
 827         if (ucmd.buf_addr && ubuffer->buf_size) {
 828                 ubuffer->buf_addr = ucmd.buf_addr;
 829                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 830                                        ubuffer->buf_size,
 831                                        &ubuffer->umem, &npages, &page_shift,
 832                                        &ncont, &offset);
 833                 if (err)
 834                         goto err_uuar;
 835         } else {
 836                 ubuffer->umem = NULL;
 837         }
 838
 839         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 840                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 841         *in = mlx5_vzalloc(*inlen);
 842         if (!*in) {
 843                 err = -ENOMEM;
 844                 goto err_umem;
 845         }
 846
 847         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 848         if (ubuffer->umem)
 849                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 850
 851         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 852
 853         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 854         MLX5_SET(qpc, qpc, page_offset, offset);
 855
 856         MLX5_SET(qpc, qpc, uar_page, uar_index);
 857         resp->uuar_index = uuarn;
 858         qp->uuarn = uuarn;
 859
 860         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 861         if (err) {
 862                 mlx5_ib_dbg(dev, "map failed\n");
 863                 goto err_free;
 864         }
 865
 866         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 867         if (err) {
 868                 mlx5_ib_dbg(dev, "copy failed\n");
 869                 goto err_unmap;
 870         }
 871         qp->create_type = MLX5_QP_USER;
 872
 873         return 0;
 874
 875 err_unmap:
 876         mlx5_ib_db_unmap_user(context, &qp->db);
 877
 878 err_free:
 879         kvfree(*in);
 880
 881 err_umem:
 882         if (ubuffer->umem)
 883                 ib_umem_release(ubuffer->umem);
 884
 885 err_uuar:
 886         free_uuar(&context->uuari, uuarn);
 887         return err;
 888 }
 889
 890 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
 891                             struct mlx5_ib_qp_base *base)
 892 {
 893         struct mlx5_ib_ucontext *context;
 894
 895         context = to_mucontext(pd->uobject->context);
 896         mlx5_ib_db_unmap_user(context, &qp->db);
 897         if (base->ubuffer.umem)
 898                 ib_umem_release(base->ubuffer.umem);
 899         free_uuar(&context->uuari, qp->uuarn);
 900 }
 901
 902 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 903                             struct ib_qp_init_attr *init_attr,
 904                             struct mlx5_ib_qp *qp,
 905                             u32 **in, int *inlen,
 906                             struct mlx5_ib_qp_base *base)
 907 {
 908         enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
 909         struct mlx5_uuar_info *uuari;
 910         int uar_index;
 911         void *qpc;
 912         int uuarn;
 913         int err;
 914
 915         uuari = &dev->mdev->priv.uuari;
 916         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 917                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 918                                         IB_QP_CREATE_IPOIB_UD_LSO |
 919                                         mlx5_ib_create_qp_sqpn_qp1()))
 920                 return -EINVAL;
 921
 922         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 923                 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
 924
 925         uuarn = alloc_uuar(uuari, lc);
 926         if (uuarn < 0) {
 927                 mlx5_ib_dbg(dev, "\n");
 928                 return -ENOMEM;
 929         }
 930
 931         qp->bf = &uuari->bfs[uuarn];
 932         uar_index = qp->bf->uar->index;
 933
 934         err = calc_sq_size(dev, init_attr, qp);
 935         if (err < 0) {
 936                 mlx5_ib_dbg(dev, "err %d\n", err);
 937                 goto err_uuar;
 938         }
 939
 940         qp->rq.offset = 0;
 941         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 942         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 943
 944         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
 945         if (err) {
 946                 mlx5_ib_dbg(dev, "err %d\n", err);
 947                 goto err_uuar;
 948         }
 949
 950         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 951         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 952                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
 953         *in = mlx5_vzalloc(*inlen);
 954         if (!*in) {
 955                 err = -ENOMEM;
 956                 goto err_buf;
 957         }
 958
 959         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 960         MLX5_SET(qpc, qpc, uar_page, uar_index);
 961         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 962
 963         /* Set "fast registration enabled" for all kernel QPs */
 964         MLX5_SET(qpc, qpc, fre, 1);
 965         MLX5_SET(qpc, qpc, rlky, 1);
 966
 967         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
 968                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
 969                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
 970         }
 971
 972         mlx5_fill_page_array(&qp->buf,
 973                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
 974
 975         err = mlx5_db_alloc(dev->mdev, &qp->db);
 976         if (err) {
 977                 mlx5_ib_dbg(dev, "err %d\n", err);
 978                 goto err_free;
 979         }
 980
 981         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
 982         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
 983         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
 984         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
 985         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 986
 987         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 988             !qp->sq.w_list || !qp->sq.wqe_head) {
 989                 err = -ENOMEM;
 990                 goto err_wrid;
 991         }
 992         qp->create_type = MLX5_QP_KERNEL;
 993
 994         return 0;
 995
 996 err_wrid:
 997         mlx5_db_free(dev->mdev, &qp->db);
 998         kfree(qp->sq.wqe_head);
 999         kfree(qp->sq.w_list);
1000         kfree(qp->sq.wrid);
1001         kfree(qp->sq.wr_data);
1002         kfree(qp->rq.wrid);
1003
1004 err_free:
1005         kvfree(*in);
1006
1007 err_buf:
1008         mlx5_buf_free(dev->mdev, &qp->buf);
1009
1010 err_uuar:
1011         free_uuar(&dev->mdev->priv.uuari, uuarn);
1012         return err;
1013 }
1014
1015 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1016 {
1017         mlx5_db_free(dev->mdev, &qp->db);
1018         kfree(qp->sq.wqe_head);
1019         kfree(qp->sq.w_list);
1020         kfree(qp->sq.wrid);
1021         kfree(qp->sq.wr_data);
1022         kfree(qp->rq.wrid);
1023         mlx5_buf_free(dev->mdev, &qp->buf);
1024         free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
1025 }
1026
1027 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1028 {
1029         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1030             (attr->qp_type == IB_QPT_XRC_INI))
1031                 return MLX5_SRQ_RQ;
1032         else if (!qp->has_rq)
1033                 return MLX5_ZERO_LEN_RQ;
1034         else
1035                 return MLX5_NON_ZERO_RQ;
1036 }
1037
1038 static int is_connected(enum ib_qp_type qp_type)
1039 {
1040         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1041                 return 1;
1042
1043         return 0;
1044 }
1045
1046 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1047                                     struct mlx5_ib_sq *sq, u32 tdn)
1048 {
1049         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1050         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1051
1052         MLX5_SET(tisc, tisc, transport_domain, tdn);
1053         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1054 }
1055
1056 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1057                                       struct mlx5_ib_sq *sq)
1058 {
1059         mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1060 }
1061
1062 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1063                                    struct mlx5_ib_sq *sq, void *qpin,
1064                                    struct ib_pd *pd)
1065 {
1066         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1067         __be64 *pas;
1068         void *in;
1069         void *sqc;
1070         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1071         void *wq;
1072         int inlen;
1073         int err;
1074         int page_shift = 0;
1075         int npages;
1076         int ncont = 0;
1077         u32 offset = 0;
1078
1079         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1080                                &sq->ubuffer.umem, &npages, &page_shift,
1081                                &ncont, &offset);
1082         if (err)
1083                 return err;
1084
1085         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1086         in = mlx5_vzalloc(inlen);
1087         if (!in) {
1088                 err = -ENOMEM;
1089                 goto err_umem;
1090         }
1091
1092         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1093         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1094         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1095         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1096         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1097         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1098         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1099
1100         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1101         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1102         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1103         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1104         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1105         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1106         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1107         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1108         MLX5_SET(wq, wq, page_offset, offset);
1109
1110         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1111         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1112
1113         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1114
1115         kvfree(in);
1116
1117         if (err)
1118                 goto err_umem;
1119
1120         return 0;
1121
1122 err_umem:
1123         ib_umem_release(sq->ubuffer.umem);
1124         sq->ubuffer.umem = NULL;
1125
1126         return err;
1127 }
1128
1129 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1130                                      struct mlx5_ib_sq *sq)
1131 {
1132         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1133         ib_umem_release(sq->ubuffer.umem);
1134 }
1135
1136 static int get_rq_pas_size(void *qpc)
1137 {
1138         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1139         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1140         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1141         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1142         u32 po_quanta     = 1 << (log_page_size - 6);
1143         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1144         u32 page_size     = 1 << log_page_size;
1145         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1146         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1147
1148         return rq_num_pas * sizeof(u64);
1149 }
1150
1151 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1152                                    struct mlx5_ib_rq *rq, void *qpin)
1153 {
1154         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1155         __be64 *pas;
1156         __be64 *qp_pas;
1157         void *in;
1158         void *rqc;
1159         void *wq;
1160         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1161         int inlen;
1162         int err;
1163         u32 rq_pas_size = get_rq_pas_size(qpc);
1164
1165         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1166         in = mlx5_vzalloc(inlen);
1167         if (!in)
1168                 return -ENOMEM;
1169
1170         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1171         MLX5_SET(rqc, rqc, vsd, 1);
1172         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1173         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1174         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1175         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1176         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1177
1178         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1179                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1180
1181         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1182         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1183         MLX5_SET(wq, wq, end_padding_mode,
1184                  MLX5_GET(qpc, qpc, end_padding_mode));
1185         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1186         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1187         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1188         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1189         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1190         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1191
1192         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1193         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1194         memcpy(pas, qp_pas, rq_pas_size);
1195
1196         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1197
1198         kvfree(in);
1199
1200         return err;
1201 }
1202
1203 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1204                                      struct mlx5_ib_rq *rq)
1205 {
1206         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1207 }
1208
1209 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1210                                     struct mlx5_ib_rq *rq, u32 tdn)
1211 {
1212         u32 *in;
1213         void *tirc;
1214         int inlen;
1215         int err;
1216
1217         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1218         in = mlx5_vzalloc(inlen);
1219         if (!in)
1220                 return -ENOMEM;
1221
1222         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1223         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1224         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1225         MLX5_SET(tirc, tirc, transport_domain, tdn);
1226
1227         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1228
1229         kvfree(in);
1230
1231         return err;
1232 }
1233
1234 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1235                                       struct mlx5_ib_rq *rq)
1236 {
1237         mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1238 }
1239
1240 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1241                                 u32 *in,
1242                                 struct ib_pd *pd)
1243 {
1244         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1245         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1246         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1247         struct ib_uobject *uobj = pd->uobject;
1248         struct ib_ucontext *ucontext = uobj->context;
1249         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1250         int err;
1251         u32 tdn = mucontext->tdn;
1252
1253         if (qp->sq.wqe_cnt) {
1254                 err = create_raw_packet_qp_tis(dev, sq, tdn);
1255                 if (err)
1256                         return err;
1257
1258                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1259                 if (err)
1260                         goto err_destroy_tis;
1261
1262                 sq->base.container_mibqp = qp;
1263         }
1264
1265         if (qp->rq.wqe_cnt) {
1266                 rq->base.container_mibqp = qp;
1267
1268                 err = create_raw_packet_qp_rq(dev, rq, in);
1269                 if (err)
1270                         goto err_destroy_sq;
1271
1272
1273                 err = create_raw_packet_qp_tir(dev, rq, tdn);
1274                 if (err)
1275                         goto err_destroy_rq;
1276         }
1277
1278         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1279                                                      rq->base.mqp.qpn;
1280
1281         return 0;
1282
1283 err_destroy_rq:
1284         destroy_raw_packet_qp_rq(dev, rq);
1285 err_destroy_sq:
1286         if (!qp->sq.wqe_cnt)
1287                 return err;
1288         destroy_raw_packet_qp_sq(dev, sq);
1289 err_destroy_tis:
1290         destroy_raw_packet_qp_tis(dev, sq);
1291
1292         return err;
1293 }
1294
1295 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1296                                   struct mlx5_ib_qp *qp)
1297 {
1298         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1299         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1300         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1301
1302         if (qp->rq.wqe_cnt) {
1303                 destroy_raw_packet_qp_tir(dev, rq);
1304                 destroy_raw_packet_qp_rq(dev, rq);
1305         }
1306
1307         if (qp->sq.wqe_cnt) {
1308                 destroy_raw_packet_qp_sq(dev, sq);
1309                 destroy_raw_packet_qp_tis(dev, sq);
1310         }
1311 }
1312
1313 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1314                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1315 {
1316         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1317         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1318
1319         sq->sq = &qp->sq;
1320         rq->rq = &qp->rq;
1321         sq->doorbell = &qp->db;
1322         rq->doorbell = &qp->db;
1323 }
1324
1325 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1326 {
1327         mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1328 }
1329
1330 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1331                                  struct ib_pd *pd,
1332                                  struct ib_qp_init_attr *init_attr,
1333                                  struct ib_udata *udata)
1334 {
1335         struct ib_uobject *uobj = pd->uobject;
1336         struct ib_ucontext *ucontext = uobj->context;
1337         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1338         struct mlx5_ib_create_qp_resp resp = {};
1339         int inlen;
1340         int err;
1341         u32 *in;
1342         void *tirc;
1343         void *hfso;
1344         u32 selected_fields = 0;
1345         size_t min_resp_len;
1346         u32 tdn = mucontext->tdn;
1347         struct mlx5_ib_create_qp_rss ucmd = {};
1348         size_t required_cmd_sz;
1349
1350         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1351                 return -EOPNOTSUPP;
1352
1353         if (init_attr->create_flags || init_attr->send_cq)
1354                 return -EINVAL;
1355
1356         min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1357         if (udata->outlen < min_resp_len)
1358                 return -EINVAL;
1359
1360         required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1361         if (udata->inlen < required_cmd_sz) {
1362                 mlx5_ib_dbg(dev, "invalid inlen\n");
1363                 return -EINVAL;
1364         }
1365
1366         if (udata->inlen > sizeof(ucmd) &&
1367             !ib_is_udata_cleared(udata, sizeof(ucmd),
1368                                  udata->inlen - sizeof(ucmd))) {
1369                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1370                 return -EOPNOTSUPP;
1371         }
1372
1373         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1374                 mlx5_ib_dbg(dev, "copy failed\n");
1375                 return -EFAULT;
1376         }
1377
1378         if (ucmd.comp_mask) {
1379                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1380                 return -EOPNOTSUPP;
1381         }
1382
1383         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1384                 mlx5_ib_dbg(dev, "invalid reserved\n");
1385                 return -EOPNOTSUPP;
1386         }
1387
1388         err = ib_copy_to_udata(udata, &resp, min_resp_len);
1389         if (err) {
1390                 mlx5_ib_dbg(dev, "copy failed\n");
1391                 return -EINVAL;
1392         }
1393
1394         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1395         in = mlx5_vzalloc(inlen);
1396         if (!in)
1397                 return -ENOMEM;
1398
1399         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1400         MLX5_SET(tirc, tirc, disp_type,
1401                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1402         MLX5_SET(tirc, tirc, indirect_table,
1403                  init_attr->rwq_ind_tbl->ind_tbl_num);
1404         MLX5_SET(tirc, tirc, transport_domain, tdn);
1405
1406         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1407         switch (ucmd.rx_hash_function) {
1408         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1409         {
1410                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1411                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1412
1413                 if (len != ucmd.rx_key_len) {
1414                         err = -EINVAL;
1415                         goto err;
1416                 }
1417
1418                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1419                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1420                 memcpy(rss_key, ucmd.rx_hash_key, len);
1421                 break;
1422         }
1423         default:
1424                 err = -EOPNOTSUPP;
1425                 goto err;
1426         }
1427
1428         if (!ucmd.rx_hash_fields_mask) {
1429                 /* special case when this TIR serves as steering entry without hashing */
1430                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1431                         goto create_tir;
1432                 err = -EINVAL;
1433                 goto err;
1434         }
1435
1436         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1437              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1438              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1439              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1440                 err = -EINVAL;
1441                 goto err;
1442         }
1443
1444         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1445         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1446             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1447                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1448                          MLX5_L3_PROT_TYPE_IPV4);
1449         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1450                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1451                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1452                          MLX5_L3_PROT_TYPE_IPV6);
1453
1454         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1455              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1456              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1457              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1458                 err = -EINVAL;
1459                 goto err;
1460         }
1461
1462         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1463         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1464             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1465                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1466                          MLX5_L4_PROT_TYPE_TCP);
1467         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1468                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1469                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1470                          MLX5_L4_PROT_TYPE_UDP);
1471
1472         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1473             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1474                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1475
1476         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1477             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1478                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1479
1480         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1481             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1482                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1483
1484         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1485             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1486                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1487
1488         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1489
1490 create_tir:
1491         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1492
1493         if (err)
1494                 goto err;
1495
1496         kvfree(in);
1497         /* qpn is reserved for that QP */
1498         qp->trans_qp.base.mqp.qpn = 0;
1499         qp->flags |= MLX5_IB_QP_RSS;
1500         return 0;
1501
1502 err:
1503         kvfree(in);
1504         return err;
1505 }
1506
1507 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1508                             struct ib_qp_init_attr *init_attr,
1509                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1510 {
1511         struct mlx5_ib_resources *devr = &dev->devr;
1512         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1513         struct mlx5_core_dev *mdev = dev->mdev;
1514         struct mlx5_ib_create_qp_resp resp;
1515         struct mlx5_ib_cq *send_cq;
1516         struct mlx5_ib_cq *recv_cq;
1517         unsigned long flags;
1518         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1519         struct mlx5_ib_create_qp ucmd;
1520         struct mlx5_ib_qp_base *base;
1521         void *qpc;
1522         u32 *in;
1523         int err;
1524
1525         base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1526                &qp->raw_packet_qp.rq.base :
1527                &qp->trans_qp.base;
1528
1529         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1530                 mlx5_ib_odp_create_qp(qp);
1531
1532         mutex_init(&qp->mutex);
1533         spin_lock_init(&qp->sq.lock);
1534         spin_lock_init(&qp->rq.lock);
1535
1536         if (init_attr->rwq_ind_tbl) {
1537                 if (!udata)
1538                         return -ENOSYS;
1539
1540                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1541                 return err;
1542         }
1543
1544         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1545                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1546                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1547                         return -EINVAL;
1548                 } else {
1549                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1550                 }
1551         }
1552
1553         if (init_attr->create_flags &
1554                         (IB_QP_CREATE_CROSS_CHANNEL |
1555                          IB_QP_CREATE_MANAGED_SEND |
1556                          IB_QP_CREATE_MANAGED_RECV)) {
1557                 if (!MLX5_CAP_GEN(mdev, cd)) {
1558                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1559                         return -EINVAL;
1560                 }
1561                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1562                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1563                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1564                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1565                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1566                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1567         }
1568
1569         if (init_attr->qp_type == IB_QPT_UD &&
1570             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1571                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1572                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1573                         return -EOPNOTSUPP;
1574                 }
1575
1576         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1577                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1578                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1579                         return -EOPNOTSUPP;
1580                 }
1581                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1582                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1583                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1584                         return -EOPNOTSUPP;
1585                 }
1586                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1587         }
1588
1589         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1590                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1591
1592         if (pd && pd->uobject) {
1593                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1594                         mlx5_ib_dbg(dev, "copy failed\n");
1595                         return -EFAULT;
1596                 }
1597
1598                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1599                                         &ucmd, udata->inlen, &uidx);
1600                 if (err)
1601                         return err;
1602
1603                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1604                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1605         } else {
1606                 qp->wq_sig = !!wq_signature;
1607         }
1608
1609         qp->has_rq = qp_has_rq(init_attr);
1610         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1611                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1612         if (err) {
1613                 mlx5_ib_dbg(dev, "err %d\n", err);
1614                 return err;
1615         }
1616
1617         if (pd) {
1618                 if (pd->uobject) {
1619                         __u32 max_wqes =
1620                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1621                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1622                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1623                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1624                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1625                                 return -EINVAL;
1626                         }
1627                         if (ucmd.sq_wqe_count > max_wqes) {
1628                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1629                                             ucmd.sq_wqe_count, max_wqes);
1630                                 return -EINVAL;
1631                         }
1632                         if (init_attr->create_flags &
1633                             mlx5_ib_create_qp_sqpn_qp1()) {
1634                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1635                                 return -EINVAL;
1636                         }
1637                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1638                                              &resp, &inlen, base);
1639                         if (err)
1640                                 mlx5_ib_dbg(dev, "err %d\n", err);
1641                 } else {
1642                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1643                                                base);
1644                         if (err)
1645                                 mlx5_ib_dbg(dev, "err %d\n", err);
1646                 }
1647
1648                 if (err)
1649                         return err;
1650         } else {
1651                 in = mlx5_vzalloc(inlen);
1652                 if (!in)
1653                         return -ENOMEM;
1654
1655                 qp->create_type = MLX5_QP_EMPTY;
1656         }
1657
1658         if (is_sqp(init_attr->qp_type))
1659                 qp->port = init_attr->port_num;
1660
1661         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1662
1663         MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1664         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1665
1666         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1667                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1668         else
1669                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1670
1671
1672         if (qp->wq_sig)
1673                 MLX5_SET(qpc, qpc, wq_signature, 1);
1674
1675         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1676                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1677
1678         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1679                 MLX5_SET(qpc, qpc, cd_master, 1);
1680         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1681                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1682         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1683                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1684
1685         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1686                 int rcqe_sz;
1687                 int scqe_sz;
1688
1689                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1690                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1691
1692                 if (rcqe_sz == 128)
1693                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1694                 else
1695                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1696
1697                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1698                         if (scqe_sz == 128)
1699                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1700                         else
1701                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1702                 }
1703         }
1704
1705         if (qp->rq.wqe_cnt) {
1706                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1707                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1708         }
1709
1710         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1711
1712         if (qp->sq.wqe_cnt)
1713                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1714         else
1715                 MLX5_SET(qpc, qpc, no_sq, 1);
1716
1717         /* Set default resources */
1718         switch (init_attr->qp_type) {
1719         case IB_QPT_XRC_TGT:
1720                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1721                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1722                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1723                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1724                 break;
1725         case IB_QPT_XRC_INI:
1726                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1727                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1728                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1729                 break;
1730         default:
1731                 if (init_attr->srq) {
1732                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1733                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1734                 } else {
1735                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1736                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1737                 }
1738         }
1739
1740         if (init_attr->send_cq)
1741                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1742
1743         if (init_attr->recv_cq)
1744                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1745
1746         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1747
1748         /* 0xffffff means we ask to work with cqe version 0 */
1749         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1750                 MLX5_SET(qpc, qpc, user_index, uidx);
1751
1752         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1753         if (init_attr->qp_type == IB_QPT_UD &&
1754             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1755                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1756                 qp->flags |= MLX5_IB_QP_LSO;
1757         }
1758
1759         if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1760                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1761                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1762                 err = create_raw_packet_qp(dev, qp, in, pd);
1763         } else {
1764                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1765         }
1766
1767         if (err) {
1768                 mlx5_ib_dbg(dev, "create qp failed\n");
1769                 goto err_create;
1770         }
1771
1772         kvfree(in);
1773
1774         base->container_mibqp = qp;
1775         base->mqp.event = mlx5_ib_qp_event;
1776
1777         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1778                 &send_cq, &recv_cq);
1779         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1780         mlx5_ib_lock_cqs(send_cq, recv_cq);
1781         /* Maintain device to QPs access, needed for further handling via reset
1782          * flow
1783          */
1784         list_add_tail(&qp->qps_list, &dev->qp_list);
1785         /* Maintain CQ to QPs access, needed for further handling via reset flow
1786          */
1787         if (send_cq)
1788                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1789         if (recv_cq)
1790                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1791         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1792         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1793
1794         return 0;
1795
1796 err_create:
1797         if (qp->create_type == MLX5_QP_USER)
1798                 destroy_qp_user(pd, qp, base);
1799         else if (qp->create_type == MLX5_QP_KERNEL)
1800                 destroy_qp_kernel(dev, qp);
1801
1802         kvfree(in);
1803         return err;
1804 }
1805
1806 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1807         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1808 {
1809         if (send_cq) {
1810                 if (recv_cq) {
1811                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1812                                 spin_lock(&send_cq->lock);
1813                                 spin_lock_nested(&recv_cq->lock,
1814                                                  SINGLE_DEPTH_NESTING);
1815                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1816                                 spin_lock(&send_cq->lock);
1817                                 __acquire(&recv_cq->lock);
1818                         } else {
1819                                 spin_lock(&recv_cq->lock);
1820                                 spin_lock_nested(&send_cq->lock,
1821                                                  SINGLE_DEPTH_NESTING);
1822                         }
1823                 } else {
1824                         spin_lock(&send_cq->lock);
1825                         __acquire(&recv_cq->lock);
1826                 }
1827         } else if (recv_cq) {
1828                 spin_lock(&recv_cq->lock);
1829                 __acquire(&send_cq->lock);
1830         } else {
1831                 __acquire(&send_cq->lock);
1832                 __acquire(&recv_cq->lock);
1833         }
1834 }
1835
1836 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1837         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1838 {
1839         if (send_cq) {
1840                 if (recv_cq) {
1841                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1842                                 spin_unlock(&recv_cq->lock);
1843                                 spin_unlock(&send_cq->lock);
1844                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1845                                 __release(&recv_cq->lock);
1846                                 spin_unlock(&send_cq->lock);
1847                         } else {
1848                                 spin_unlock(&send_cq->lock);
1849                                 spin_unlock(&recv_cq->lock);
1850                         }
1851                 } else {
1852                         __release(&recv_cq->lock);
1853                         spin_unlock(&send_cq->lock);
1854                 }
1855         } else if (recv_cq) {
1856                 __release(&send_cq->lock);
1857                 spin_unlock(&recv_cq->lock);
1858         } else {
1859                 __release(&recv_cq->lock);
1860                 __release(&send_cq->lock);
1861         }
1862 }
1863
1864 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1865 {
1866         return to_mpd(qp->ibqp.pd);
1867 }
1868
1869 static void get_cqs(enum ib_qp_type qp_type,
1870                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1871                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1872 {
1873         switch (qp_type) {
1874         case IB_QPT_XRC_TGT:
1875                 *send_cq = NULL;
1876                 *recv_cq = NULL;
1877                 break;
1878         case MLX5_IB_QPT_REG_UMR:
1879         case IB_QPT_XRC_INI:
1880                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1881                 *recv_cq = NULL;
1882                 break;
1883
1884         case IB_QPT_SMI:
1885         case MLX5_IB_QPT_HW_GSI:
1886         case IB_QPT_RC:
1887         case IB_QPT_UC:
1888         case IB_QPT_UD:
1889         case IB_QPT_RAW_IPV6:
1890         case IB_QPT_RAW_ETHERTYPE:
1891         case IB_QPT_RAW_PACKET:
1892                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1893                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1894                 break;
1895
1896         case IB_QPT_MAX:
1897         default:
1898                 *send_cq = NULL;
1899                 *recv_cq = NULL;
1900                 break;
1901         }
1902 }
1903
1904 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1905                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1906                                 u8 lag_tx_affinity);
1907
1908 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1909 {
1910         struct mlx5_ib_cq *send_cq, *recv_cq;
1911         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1912         unsigned long flags;
1913         int err;
1914
1915         if (qp->ibqp.rwq_ind_tbl) {
1916                 destroy_rss_raw_qp_tir(dev, qp);
1917                 return;
1918         }
1919
1920         base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1921                &qp->raw_packet_qp.rq.base :
1922                &qp->trans_qp.base;
1923
1924         if (qp->state != IB_QPS_RESET) {
1925                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1926                         mlx5_ib_qp_disable_pagefaults(qp);
1927                         err = mlx5_core_qp_modify(dev->mdev,
1928                                                   MLX5_CMD_OP_2RST_QP, 0,
1929                                                   NULL, &base->mqp);
1930                 } else {
1931                         struct mlx5_modify_raw_qp_param raw_qp_param = {
1932                                 .operation = MLX5_CMD_OP_2RST_QP
1933                         };
1934
1935                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1936                 }
1937                 if (err)
1938                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1939                                      base->mqp.qpn);
1940         }
1941
1942         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1943                 &send_cq, &recv_cq);
1944
1945         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1946         mlx5_ib_lock_cqs(send_cq, recv_cq);
1947         /* del from lists under both locks above to protect reset flow paths */
1948         list_del(&qp->qps_list);
1949         if (send_cq)
1950                 list_del(&qp->cq_send_list);
1951
1952         if (recv_cq)
1953                 list_del(&qp->cq_recv_list);
1954
1955         if (qp->create_type == MLX5_QP_KERNEL) {
1956                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1957                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1958                 if (send_cq != recv_cq)
1959                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1960                                            NULL);
1961         }
1962         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1963         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1964
1965         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1966                 destroy_raw_packet_qp(dev, qp);
1967         } else {
1968                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1969                 if (err)
1970                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1971                                      base->mqp.qpn);
1972         }
1973
1974         if (qp->create_type == MLX5_QP_KERNEL)
1975                 destroy_qp_kernel(dev, qp);
1976         else if (qp->create_type == MLX5_QP_USER)
1977                 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
1978 }
1979
1980 static const char *ib_qp_type_str(enum ib_qp_type type)
1981 {
1982         switch (type) {
1983         case IB_QPT_SMI:
1984                 return "IB_QPT_SMI";
1985         case IB_QPT_GSI:
1986                 return "IB_QPT_GSI";
1987         case IB_QPT_RC:
1988                 return "IB_QPT_RC";
1989         case IB_QPT_UC:
1990                 return "IB_QPT_UC";
1991         case IB_QPT_UD:
1992                 return "IB_QPT_UD";
1993         case IB_QPT_RAW_IPV6:
1994                 return "IB_QPT_RAW_IPV6";
1995         case IB_QPT_RAW_ETHERTYPE:
1996                 return "IB_QPT_RAW_ETHERTYPE";
1997         case IB_QPT_XRC_INI:
1998                 return "IB_QPT_XRC_INI";
1999         case IB_QPT_XRC_TGT:
2000                 return "IB_QPT_XRC_TGT";
2001         case IB_QPT_RAW_PACKET:
2002                 return "IB_QPT_RAW_PACKET";
2003         case MLX5_IB_QPT_REG_UMR:
2004                 return "MLX5_IB_QPT_REG_UMR";
2005         case IB_QPT_MAX:
2006         default:
2007                 return "Invalid QP type";
2008         }
2009 }
2010
2011 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2012                                 struct ib_qp_init_attr *init_attr,
2013                                 struct ib_udata *udata)
2014 {
2015         struct mlx5_ib_dev *dev;
2016         struct mlx5_ib_qp *qp;
2017         u16 xrcdn = 0;
2018         int err;
2019
2020         if (pd) {
2021                 dev = to_mdev(pd->device);
2022
2023                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2024                         if (!pd->uobject) {
2025                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2026                                 return ERR_PTR(-EINVAL);
2027                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2028                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2029                                 return ERR_PTR(-EINVAL);
2030                         }
2031                 }
2032         } else {
2033                 /* being cautious here */
2034                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2035                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2036                         pr_warn("%s: no PD for transport %s\n", __func__,
2037                                 ib_qp_type_str(init_attr->qp_type));
2038                         return ERR_PTR(-EINVAL);
2039                 }
2040                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2041         }
2042
2043         switch (init_attr->qp_type) {
2044         case IB_QPT_XRC_TGT:
2045         case IB_QPT_XRC_INI:
2046                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2047                         mlx5_ib_dbg(dev, "XRC not supported\n");
2048                         return ERR_PTR(-ENOSYS);
2049                 }
2050                 init_attr->recv_cq = NULL;
2051                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2052                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2053                         init_attr->send_cq = NULL;
2054                 }
2055
2056                 /* fall through */
2057         case IB_QPT_RAW_PACKET:
2058         case IB_QPT_RC:
2059         case IB_QPT_UC:
2060         case IB_QPT_UD:
2061         case IB_QPT_SMI:
2062         case MLX5_IB_QPT_HW_GSI:
2063         case MLX5_IB_QPT_REG_UMR:
2064                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2065                 if (!qp)
2066                         return ERR_PTR(-ENOMEM);
2067
2068                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2069                 if (err) {
2070                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2071                         kfree(qp);
2072                         return ERR_PTR(err);
2073                 }
2074
2075                 if (is_qp0(init_attr->qp_type))
2076                         qp->ibqp.qp_num = 0;
2077                 else if (is_qp1(init_attr->qp_type))
2078                         qp->ibqp.qp_num = 1;
2079                 else
2080                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2081
2082                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2083                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2084                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2085                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2086
2087                 qp->trans_qp.xrcdn = xrcdn;
2088
2089                 break;
2090
2091         case IB_QPT_GSI:
2092                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2093
2094         case IB_QPT_RAW_IPV6:
2095         case IB_QPT_RAW_ETHERTYPE:
2096         case IB_QPT_MAX:
2097         default:
2098                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2099                             init_attr->qp_type);
2100                 /* Don't support raw QPs */
2101                 return ERR_PTR(-EINVAL);
2102         }
2103
2104         return &qp->ibqp;
2105 }
2106
2107 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2108 {
2109         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2110         struct mlx5_ib_qp *mqp = to_mqp(qp);
2111
2112         if (unlikely(qp->qp_type == IB_QPT_GSI))
2113                 return mlx5_ib_gsi_destroy_qp(qp);
2114
2115         destroy_qp_common(dev, mqp);
2116
2117         kfree(mqp);
2118
2119         return 0;
2120 }
2121
2122 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2123                                    int attr_mask)
2124 {
2125         u32 hw_access_flags = 0;
2126         u8 dest_rd_atomic;
2127         u32 access_flags;
2128
2129         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2130                 dest_rd_atomic = attr->max_dest_rd_atomic;
2131         else
2132                 dest_rd_atomic = qp->trans_qp.resp_depth;
2133
2134         if (attr_mask & IB_QP_ACCESS_FLAGS)
2135                 access_flags = attr->qp_access_flags;
2136         else
2137                 access_flags = qp->trans_qp.atomic_rd_en;
2138
2139         if (!dest_rd_atomic)
2140                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2141
2142         if (access_flags & IB_ACCESS_REMOTE_READ)
2143                 hw_access_flags |= MLX5_QP_BIT_RRE;
2144         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2145                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2146         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2147                 hw_access_flags |= MLX5_QP_BIT_RWE;
2148
2149         return cpu_to_be32(hw_access_flags);
2150 }
2151
2152 enum {
2153         MLX5_PATH_FLAG_FL       = 1 << 0,
2154         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2155         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2156 };
2157
2158 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2159 {
2160         if (rate == IB_RATE_PORT_CURRENT) {
2161                 return 0;
2162         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2163                 return -EINVAL;
2164         } else {
2165                 while (rate != IB_RATE_2_5_GBPS &&
2166                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2167                          MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2168                         --rate;
2169         }
2170
2171         return rate + MLX5_STAT_RATE_OFFSET;
2172 }
2173
2174 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2175                                       struct mlx5_ib_sq *sq, u8 sl)
2176 {
2177         void *in;
2178         void *tisc;
2179         int inlen;
2180         int err;
2181
2182         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2183         in = mlx5_vzalloc(inlen);
2184         if (!in)
2185                 return -ENOMEM;
2186
2187         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2188
2189         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2190         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2191
2192         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2193
2194         kvfree(in);
2195
2196         return err;
2197 }
2198
2199 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2200                                          struct mlx5_ib_sq *sq, u8 tx_affinity)
2201 {
2202         void *in;
2203         void *tisc;
2204         int inlen;
2205         int err;
2206
2207         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2208         in = mlx5_vzalloc(inlen);
2209         if (!in)
2210                 return -ENOMEM;
2211
2212         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2213
2214         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2215         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2216
2217         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2218
2219         kvfree(in);
2220
2221         return err;
2222 }
2223
2224 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2225                          const struct ib_ah_attr *ah,
2226                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2227                          u32 path_flags, const struct ib_qp_attr *attr,
2228                          bool alt)
2229 {
2230         enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2231         int err;
2232
2233         if (attr_mask & IB_QP_PKEY_INDEX)
2234                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2235                                                      attr->pkey_index);
2236
2237         if (ah->ah_flags & IB_AH_GRH) {
2238                 if (ah->grh.sgid_index >=
2239                     dev->mdev->port_caps[port - 1].gid_table_len) {
2240                         pr_err("sgid_index (%u) too large. max is %d\n",
2241                                ah->grh.sgid_index,
2242                                dev->mdev->port_caps[port - 1].gid_table_len);
2243                         return -EINVAL;
2244                 }
2245         }
2246
2247         if (ll == IB_LINK_LAYER_ETHERNET) {
2248                 if (!(ah->ah_flags & IB_AH_GRH))
2249                         return -EINVAL;
2250                 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2251                 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2252                                                           ah->grh.sgid_index);
2253                 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2254         } else {
2255                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2256                 path->fl_free_ar |=
2257                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2258                 path->rlid = cpu_to_be16(ah->dlid);
2259                 path->grh_mlid = ah->src_path_bits & 0x7f;
2260                 if (ah->ah_flags & IB_AH_GRH)
2261                         path->grh_mlid  |= 1 << 7;
2262                 path->dci_cfi_prio_sl = ah->sl & 0xf;
2263         }
2264
2265         if (ah->ah_flags & IB_AH_GRH) {
2266                 path->mgid_index = ah->grh.sgid_index;
2267                 path->hop_limit  = ah->grh.hop_limit;
2268                 path->tclass_flowlabel =
2269                         cpu_to_be32((ah->grh.traffic_class << 20) |
2270                                     (ah->grh.flow_label));
2271                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2272         }
2273
2274         err = ib_rate_to_mlx5(dev, ah->static_rate);
2275         if (err < 0)
2276                 return err;
2277         path->static_rate = err;
2278         path->port = port;
2279
2280         if (attr_mask & IB_QP_TIMEOUT)
2281                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2282
2283         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2284                 return modify_raw_packet_eth_prio(dev->mdev,
2285                                                   &qp->raw_packet_qp.sq,
2286                                                   ah->sl & 0xf);
2287
2288         return 0;
2289 }
2290
2291 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2292         [MLX5_QP_STATE_INIT] = {
2293                 [MLX5_QP_STATE_INIT] = {
2294                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2295                                           MLX5_QP_OPTPAR_RAE            |
2296                                           MLX5_QP_OPTPAR_RWE            |
2297                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2298                                           MLX5_QP_OPTPAR_PRI_PORT,
2299                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2300                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2301                                           MLX5_QP_OPTPAR_PRI_PORT,
2302                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2303                                           MLX5_QP_OPTPAR_Q_KEY          |
2304                                           MLX5_QP_OPTPAR_PRI_PORT,
2305                 },
2306                 [MLX5_QP_STATE_RTR] = {
2307                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2308                                           MLX5_QP_OPTPAR_RRE            |
2309                                           MLX5_QP_OPTPAR_RAE            |
2310                                           MLX5_QP_OPTPAR_RWE            |
2311                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2312                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2313                                           MLX5_QP_OPTPAR_RWE            |
2314                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2315                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2316                                           MLX5_QP_OPTPAR_Q_KEY,
2317                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2318                                            MLX5_QP_OPTPAR_Q_KEY,
2319                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2320                                           MLX5_QP_OPTPAR_RRE            |
2321                                           MLX5_QP_OPTPAR_RAE            |
2322                                           MLX5_QP_OPTPAR_RWE            |
2323                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2324                 },
2325         },
2326         [MLX5_QP_STATE_RTR] = {
2327                 [MLX5_QP_STATE_RTS] = {
2328                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2329                                           MLX5_QP_OPTPAR_RRE            |
2330                                           MLX5_QP_OPTPAR_RAE            |
2331                                           MLX5_QP_OPTPAR_RWE            |
2332                                           MLX5_QP_OPTPAR_PM_STATE       |
2333                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2334                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2335                                           MLX5_QP_OPTPAR_RWE            |
2336                                           MLX5_QP_OPTPAR_PM_STATE,
2337                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2338                 },
2339         },
2340         [MLX5_QP_STATE_RTS] = {
2341                 [MLX5_QP_STATE_RTS] = {
2342                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2343                                           MLX5_QP_OPTPAR_RAE            |
2344                                           MLX5_QP_OPTPAR_RWE            |
2345                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2346                                           MLX5_QP_OPTPAR_PM_STATE       |
2347                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2348                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2349                                           MLX5_QP_OPTPAR_PM_STATE       |
2350                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2351                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2352                                           MLX5_QP_OPTPAR_SRQN           |
2353                                           MLX5_QP_OPTPAR_CQN_RCV,
2354                 },
2355         },
2356         [MLX5_QP_STATE_SQER] = {
2357                 [MLX5_QP_STATE_RTS] = {
2358                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2359                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2360                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2361                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2362                                            MLX5_QP_OPTPAR_RWE           |
2363                                            MLX5_QP_OPTPAR_RAE           |
2364                                            MLX5_QP_OPTPAR_RRE,
2365                 },
2366         },
2367 };
2368
2369 static int ib_nr_to_mlx5_nr(int ib_mask)
2370 {
2371         switch (ib_mask) {
2372         case IB_QP_STATE:
2373                 return 0;
2374         case IB_QP_CUR_STATE:
2375                 return 0;
2376         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2377                 return 0;
2378         case IB_QP_ACCESS_FLAGS:
2379                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2380                         MLX5_QP_OPTPAR_RAE;
2381         case IB_QP_PKEY_INDEX:
2382                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2383         case IB_QP_PORT:
2384                 return MLX5_QP_OPTPAR_PRI_PORT;
2385         case IB_QP_QKEY:
2386                 return MLX5_QP_OPTPAR_Q_KEY;
2387         case IB_QP_AV:
2388                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2389                         MLX5_QP_OPTPAR_PRI_PORT;
2390         case IB_QP_PATH_MTU:
2391                 return 0;
2392         case IB_QP_TIMEOUT:
2393                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2394         case IB_QP_RETRY_CNT:
2395                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2396         case IB_QP_RNR_RETRY:
2397                 return MLX5_QP_OPTPAR_RNR_RETRY;
2398         case IB_QP_RQ_PSN:
2399                 return 0;
2400         case IB_QP_MAX_QP_RD_ATOMIC:
2401                 return MLX5_QP_OPTPAR_SRA_MAX;
2402         case IB_QP_ALT_PATH:
2403                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2404         case IB_QP_MIN_RNR_TIMER:
2405                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2406         case IB_QP_SQ_PSN:
2407                 return 0;
2408         case IB_QP_MAX_DEST_RD_ATOMIC:
2409                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2410                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2411         case IB_QP_PATH_MIG_STATE:
2412                 return MLX5_QP_OPTPAR_PM_STATE;
2413         case IB_QP_CAP:
2414                 return 0;
2415         case IB_QP_DEST_QPN:
2416                 return 0;
2417         }
2418         return 0;
2419 }
2420
2421 static int ib_mask_to_mlx5_opt(int ib_mask)
2422 {
2423         int result = 0;
2424         int i;
2425
2426         for (i = 0; i < 8 * sizeof(int); i++) {
2427                 if ((1 << i) & ib_mask)
2428                         result |= ib_nr_to_mlx5_nr(1 << i);
2429         }
2430
2431         return result;
2432 }
2433
2434 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2435                                    struct mlx5_ib_rq *rq, int new_state,
2436                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2437 {
2438         void *in;
2439         void *rqc;
2440         int inlen;
2441         int err;
2442
2443         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2444         in = mlx5_vzalloc(inlen);
2445         if (!in)
2446                 return -ENOMEM;
2447
2448         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2449
2450         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2451         MLX5_SET(rqc, rqc, state, new_state);
2452
2453         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2454                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2455                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
2456                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID);
2457                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2458                 } else
2459                         pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2460                                      dev->ib_dev.name);
2461         }
2462
2463         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2464         if (err)
2465                 goto out;
2466
2467         rq->state = new_state;
2468
2469 out:
2470         kvfree(in);
2471         return err;
2472 }
2473
2474 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2475                                    struct mlx5_ib_sq *sq,
2476                                    int new_state,
2477                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2478 {
2479         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2480         u32 old_rate = ibqp->rate_limit;
2481         u32 new_rate = old_rate;
2482         u16 rl_index = 0;
2483         void *in;
2484         void *sqc;
2485         int inlen;
2486         int err;
2487
2488         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2489         in = mlx5_vzalloc(inlen);
2490         if (!in)
2491                 return -ENOMEM;
2492
2493         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2494
2495         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2496         MLX5_SET(sqc, sqc, state, new_state);
2497
2498         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2499                 if (new_state != MLX5_SQC_STATE_RDY)
2500                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2501                                 __func__);
2502                 else
2503                         new_rate = raw_qp_param->rate_limit;
2504         }
2505
2506         if (old_rate != new_rate) {
2507                 if (new_rate) {
2508                         err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2509                         if (err) {
2510                                 pr_err("Failed configuring rate %u: %d\n",
2511                                        new_rate, err);
2512                                 goto out;
2513                         }
2514                 }
2515
2516                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2517                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2518         }
2519
2520         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2521         if (err) {
2522                 /* Remove new rate from table if failed */
2523                 if (new_rate &&
2524                     old_rate != new_rate)
2525                         mlx5_rl_remove_rate(dev, new_rate);
2526                 goto out;
2527         }
2528
2529         /* Only remove the old rate after new rate was set */
2530         if ((old_rate &&
2531             (old_rate != new_rate)) ||
2532             (new_state != MLX5_SQC_STATE_RDY))
2533                 mlx5_rl_remove_rate(dev, old_rate);
2534
2535         ibqp->rate_limit = new_rate;
2536         sq->state = new_state;
2537
2538 out:
2539         kvfree(in);
2540         return err;
2541 }
2542
2543 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2544                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2545                                 u8 tx_affinity)
2546 {
2547         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2548         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2549         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2550         int modify_rq = !!qp->rq.wqe_cnt;
2551         int modify_sq = !!qp->sq.wqe_cnt;
2552         int rq_state;
2553         int sq_state;
2554         int err;
2555
2556         switch (raw_qp_param->operation) {
2557         case MLX5_CMD_OP_RST2INIT_QP:
2558                 rq_state = MLX5_RQC_STATE_RDY;
2559                 sq_state = MLX5_SQC_STATE_RDY;
2560                 break;
2561         case MLX5_CMD_OP_2ERR_QP:
2562                 rq_state = MLX5_RQC_STATE_ERR;
2563                 sq_state = MLX5_SQC_STATE_ERR;
2564                 break;
2565         case MLX5_CMD_OP_2RST_QP:
2566                 rq_state = MLX5_RQC_STATE_RST;
2567                 sq_state = MLX5_SQC_STATE_RST;
2568                 break;
2569         case MLX5_CMD_OP_RTR2RTS_QP:
2570         case MLX5_CMD_OP_RTS2RTS_QP:
2571                 if (raw_qp_param->set_mask ==
2572                     MLX5_RAW_QP_RATE_LIMIT) {
2573                         modify_rq = 0;
2574                         sq_state = sq->state;
2575                 } else {
2576                         return raw_qp_param->set_mask ? -EINVAL : 0;
2577                 }
2578                 break;
2579         case MLX5_CMD_OP_INIT2INIT_QP:
2580         case MLX5_CMD_OP_INIT2RTR_QP:
2581                 if (raw_qp_param->set_mask)
2582                         return -EINVAL;
2583                 else
2584                         return 0;
2585         default:
2586                 WARN_ON(1);
2587                 return -EINVAL;
2588         }
2589
2590         if (modify_rq) {
2591                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2592                 if (err)
2593                         return err;
2594         }
2595
2596         if (modify_sq) {
2597                 if (tx_affinity) {
2598                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2599                                                             tx_affinity);
2600                         if (err)
2601                                 return err;
2602                 }
2603
2604                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2605         }
2606
2607         return 0;
2608 }
2609
2610 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2611                                const struct ib_qp_attr *attr, int attr_mask,
2612                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2613 {
2614         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2615                 [MLX5_QP_STATE_RST] = {
2616                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2617                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2618                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
2619                 },
2620                 [MLX5_QP_STATE_INIT]  = {
2621                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2622                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2623                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
2624                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
2625                 },
2626                 [MLX5_QP_STATE_RTR]   = {
2627                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2628                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2629                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
2630                 },
2631                 [MLX5_QP_STATE_RTS]   = {
2632                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2633                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2634                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
2635                 },
2636                 [MLX5_QP_STATE_SQD] = {
2637                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2638                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2639                 },
2640                 [MLX5_QP_STATE_SQER] = {
2641                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2642                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2643                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
2644                 },
2645                 [MLX5_QP_STATE_ERR] = {
2646                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2647                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2648                 }
2649         };
2650
2651         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2652         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2653         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2654         struct mlx5_ib_cq *send_cq, *recv_cq;
2655         struct mlx5_qp_context *context;
2656         struct mlx5_ib_pd *pd;
2657         struct mlx5_ib_port *mibport = NULL;
2658         enum mlx5_qp_state mlx5_cur, mlx5_new;
2659         enum mlx5_qp_optpar optpar;
2660         int mlx5_st;
2661         int err;
2662         u16 op;
2663         u8 tx_affinity = 0;
2664
2665         context = kzalloc(sizeof(*context), GFP_KERNEL);
2666         if (!context)
2667                 return -ENOMEM;
2668
2669         err = to_mlx5_st(ibqp->qp_type);
2670         if (err < 0) {
2671                 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2672                 goto out;
2673         }
2674
2675         context->flags = cpu_to_be32(err << 16);
2676
2677         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2678                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2679         } else {
2680                 switch (attr->path_mig_state) {
2681                 case IB_MIG_MIGRATED:
2682                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2683                         break;
2684                 case IB_MIG_REARM:
2685                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2686                         break;
2687                 case IB_MIG_ARMED:
2688                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2689                         break;
2690                 }
2691         }
2692
2693         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2694                 if ((ibqp->qp_type == IB_QPT_RC) ||
2695                     (ibqp->qp_type == IB_QPT_UD &&
2696                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2697                     (ibqp->qp_type == IB_QPT_UC) ||
2698                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2699                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
2700                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2701                         if (mlx5_lag_is_active(dev->mdev)) {
2702                                 tx_affinity = (unsigned int)atomic_add_return(1,
2703                                                 &dev->roce.next_port) %
2704                                                 MLX5_MAX_PORTS + 1;
2705                                 context->flags |= cpu_to_be32(tx_affinity << 24);
2706                         }
2707                 }
2708         }
2709
2710         if (is_sqp(ibqp->qp_type)) {
2711                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2712         } else if (ibqp->qp_type == IB_QPT_UD ||
2713                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2714                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2715         } else if (attr_mask & IB_QP_PATH_MTU) {
2716                 if (attr->path_mtu < IB_MTU_256 ||
2717                     attr->path_mtu > IB_MTU_4096) {
2718                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2719                         err = -EINVAL;
2720                         goto out;
2721                 }
2722                 context->mtu_msgmax = (attr->path_mtu << 5) |
2723                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2724         }
2725
2726         if (attr_mask & IB_QP_DEST_QPN)
2727                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2728
2729         if (attr_mask & IB_QP_PKEY_INDEX)
2730                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2731
2732         /* todo implement counter_index functionality */
2733
2734         if (is_sqp(ibqp->qp_type))
2735                 context->pri_path.port = qp->port;
2736
2737         if (attr_mask & IB_QP_PORT)
2738                 context->pri_path.port = attr->port_num;
2739
2740         if (attr_mask & IB_QP_AV) {
2741                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2742                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2743                                     attr_mask, 0, attr, false);
2744                 if (err)
2745                         goto out;
2746         }
2747
2748         if (attr_mask & IB_QP_TIMEOUT)
2749                 context->pri_path.ackto_lt |= attr->timeout << 3;
2750
2751         if (attr_mask & IB_QP_ALT_PATH) {
2752                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2753                                     &context->alt_path,
2754                                     attr->alt_port_num,
2755                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2756                                     0, attr, true);
2757                 if (err)
2758                         goto out;
2759         }
2760
2761         pd = get_pd(qp);
2762         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2763                 &send_cq, &recv_cq);
2764
2765         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2766         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2767         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2768         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2769
2770         if (attr_mask & IB_QP_RNR_RETRY)
2771                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2772
2773         if (attr_mask & IB_QP_RETRY_CNT)
2774                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2775
2776         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2777                 if (attr->max_rd_atomic)
2778                         context->params1 |=
2779                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2780         }
2781
2782         if (attr_mask & IB_QP_SQ_PSN)
2783                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2784
2785         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2786                 if (attr->max_dest_rd_atomic)
2787                         context->params2 |=
2788                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2789         }
2790
2791         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2792                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2793
2794         if (attr_mask & IB_QP_MIN_RNR_TIMER)
2795                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2796
2797         if (attr_mask & IB_QP_RQ_PSN)
2798                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2799
2800         if (attr_mask & IB_QP_QKEY)
2801                 context->qkey = cpu_to_be32(attr->qkey);
2802
2803         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2804                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2805
2806         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2807                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2808                                qp->port) - 1;
2809                 mibport = &dev->port[port_num];
2810                 context->qp_counter_set_usr_page |=
2811                         cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2812         }
2813
2814         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2815                 context->sq_crq_size |= cpu_to_be16(1 << 4);
2816
2817         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2818                 context->deth_sqpn = cpu_to_be32(1);
2819
2820         mlx5_cur = to_mlx5_state(cur_state);
2821         mlx5_new = to_mlx5_state(new_state);
2822         mlx5_st = to_mlx5_st(ibqp->qp_type);
2823         if (mlx5_st < 0)
2824                 goto out;
2825
2826         /* If moving to a reset or error state, we must disable page faults on
2827          * this QP and flush all current page faults. Otherwise a stale page
2828          * fault may attempt to work on this QP after it is reset and moved
2829          * again to RTS, and may cause the driver and the device to get out of
2830          * sync. */
2831         if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2832             (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2833             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2834                 mlx5_ib_qp_disable_pagefaults(qp);
2835
2836         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2837             !optab[mlx5_cur][mlx5_new])
2838                 goto out;
2839
2840         op = optab[mlx5_cur][mlx5_new];
2841         optpar = ib_mask_to_mlx5_opt(attr_mask);
2842         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2843
2844         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2845                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2846
2847                 raw_qp_param.operation = op;
2848                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2849                         raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id;
2850                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2851                 }
2852
2853                 if (attr_mask & IB_QP_RATE_LIMIT) {
2854                         raw_qp_param.rate_limit = attr->rate_limit;
2855                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2856                 }
2857
2858                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
2859         } else {
2860                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2861                                           &base->mqp);
2862         }
2863
2864         if (err)
2865                 goto out;
2866
2867         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2868             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2869                 mlx5_ib_qp_enable_pagefaults(qp);
2870
2871         qp->state = new_state;
2872
2873         if (attr_mask & IB_QP_ACCESS_FLAGS)
2874                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2875         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2876                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2877         if (attr_mask & IB_QP_PORT)
2878                 qp->port = attr->port_num;
2879         if (attr_mask & IB_QP_ALT_PATH)
2880                 qp->trans_qp.alt_port = attr->alt_port_num;
2881
2882         /*
2883          * If we moved a kernel QP to RESET, clean up all old CQ
2884          * entries and reinitialize the QP.
2885          */
2886         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2887                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2888                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2889                 if (send_cq != recv_cq)
2890                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2891
2892                 qp->rq.head = 0;
2893                 qp->rq.tail = 0;
2894                 qp->sq.head = 0;
2895                 qp->sq.tail = 0;
2896                 qp->sq.cur_post = 0;
2897                 qp->sq.last_poll = 0;
2898                 qp->db.db[MLX5_RCV_DBR] = 0;
2899                 qp->db.db[MLX5_SND_DBR] = 0;
2900         }
2901
2902 out:
2903         kfree(context);
2904         return err;
2905 }
2906
2907 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2908                       int attr_mask, struct ib_udata *udata)
2909 {
2910         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2911         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2912         enum ib_qp_type qp_type;
2913         enum ib_qp_state cur_state, new_state;
2914         int err = -EINVAL;
2915         int port;
2916         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2917
2918         if (ibqp->rwq_ind_tbl)
2919                 return -ENOSYS;
2920
2921         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2922                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2923
2924         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2925                 IB_QPT_GSI : ibqp->qp_type;
2926
2927         mutex_lock(&qp->mutex);
2928
2929         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2930         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2931
2932         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2933                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2934                 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2935         }
2936
2937         if (qp_type != MLX5_IB_QPT_REG_UMR &&
2938             !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2939                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2940                             cur_state, new_state, ibqp->qp_type, attr_mask);
2941                 goto out;
2942         }
2943
2944         if ((attr_mask & IB_QP_PORT) &&
2945             (attr->port_num == 0 ||
2946              attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2947                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2948                             attr->port_num, dev->num_ports);
2949                 goto out;
2950         }
2951
2952         if (attr_mask & IB_QP_PKEY_INDEX) {
2953                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2954                 if (attr->pkey_index >=
2955                     dev->mdev->port_caps[port - 1].pkey_table_len) {
2956                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2957                                     attr->pkey_index);
2958                         goto out;
2959                 }
2960         }
2961
2962         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2963             attr->max_rd_atomic >
2964             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2965                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2966                             attr->max_rd_atomic);
2967                 goto out;
2968         }
2969
2970         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2971             attr->max_dest_rd_atomic >
2972             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2973                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2974                             attr->max_dest_rd_atomic);
2975                 goto out;
2976         }
2977
2978         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2979                 err = 0;
2980                 goto out;
2981         }
2982
2983         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2984
2985 out:
2986         mutex_unlock(&qp->mutex);
2987         return err;
2988 }
2989
2990 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2991 {
2992         struct mlx5_ib_cq *cq;
2993         unsigned cur;
2994
2995         cur = wq->head - wq->tail;
2996         if (likely(cur + nreq < wq->max_post))
2997                 return 0;
2998
2999         cq = to_mcq(ib_cq);
3000         spin_lock(&cq->lock);
3001         cur = wq->head - wq->tail;
3002         spin_unlock(&cq->lock);
3003
3004         return cur + nreq >= wq->max_post;
3005 }
3006
3007 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3008                                           u64 remote_addr, u32 rkey)
3009 {
3010         rseg->raddr    = cpu_to_be64(remote_addr);
3011         rseg->rkey     = cpu_to_be32(rkey);
3012         rseg->reserved = 0;
3013 }
3014
3015 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3016                          struct ib_send_wr *wr, void *qend,
3017                          struct mlx5_ib_qp *qp, int *size)
3018 {
3019         void *seg = eseg;
3020
3021         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3022
3023         if (wr->send_flags & IB_SEND_IP_CSUM)
3024                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3025                                  MLX5_ETH_WQE_L4_CSUM;
3026
3027         seg += sizeof(struct mlx5_wqe_eth_seg);
3028         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3029
3030         if (wr->opcode == IB_WR_LSO) {
3031                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3032                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
3033                 u64 left, leftlen, copysz;
3034                 void *pdata = ud_wr->header;
3035
3036                 left = ud_wr->hlen;
3037                 eseg->mss = cpu_to_be16(ud_wr->mss);
3038                 eseg->inline_hdr_sz = cpu_to_be16(left);
3039
3040                 /*
3041                  * check if there is space till the end of queue, if yes,
3042                  * copy all in one shot, otherwise copy till the end of queue,
3043                  * rollback and than the copy the left
3044                  */
3045                 leftlen = qend - (void *)eseg->inline_hdr_start;
3046                 copysz = min_t(u64, leftlen, left);
3047
3048                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3049
3050                 if (likely(copysz > size_of_inl_hdr_start)) {
3051                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3052                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3053                 }
3054
3055                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3056                         seg = mlx5_get_send_wqe(qp, 0);
3057                         left -= copysz;
3058                         pdata += copysz;
3059                         memcpy(seg, pdata, left);
3060                         seg += ALIGN(left, 16);
3061                         *size += ALIGN(left, 16) / 16;
3062                 }
3063         }
3064
3065         return seg;
3066 }
3067
3068 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3069                              struct ib_send_wr *wr)
3070 {
3071         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3072         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3073         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3074 }
3075
3076 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3077 {
3078         dseg->byte_count = cpu_to_be32(sg->length);
3079         dseg->lkey       = cpu_to_be32(sg->lkey);
3080         dseg->addr       = cpu_to_be64(sg->addr);
3081 }
3082
3083 static u64 get_xlt_octo(u64 bytes)
3084 {
3085         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3086                MLX5_IB_UMR_OCTOWORD;
3087 }
3088
3089 static __be64 frwr_mkey_mask(void)
3090 {
3091         u64 result;
3092
3093         result = MLX5_MKEY_MASK_LEN             |
3094                 MLX5_MKEY_MASK_PAGE_SIZE        |
3095                 MLX5_MKEY_MASK_START_ADDR       |
3096                 MLX5_MKEY_MASK_EN_RINVAL        |
3097                 MLX5_MKEY_MASK_KEY              |
3098                 MLX5_MKEY_MASK_LR               |
3099                 MLX5_MKEY_MASK_LW               |
3100                 MLX5_MKEY_MASK_RR               |
3101                 MLX5_MKEY_MASK_RW               |
3102                 MLX5_MKEY_MASK_A                |
3103                 MLX5_MKEY_MASK_SMALL_FENCE      |
3104                 MLX5_MKEY_MASK_FREE;
3105
3106         return cpu_to_be64(result);
3107 }
3108
3109 static __be64 sig_mkey_mask(void)
3110 {
3111         u64 result;
3112
3113         result = MLX5_MKEY_MASK_LEN             |
3114                 MLX5_MKEY_MASK_PAGE_SIZE        |
3115                 MLX5_MKEY_MASK_START_ADDR       |
3116                 MLX5_MKEY_MASK_EN_SIGERR        |
3117                 MLX5_MKEY_MASK_EN_RINVAL        |
3118                 MLX5_MKEY_MASK_KEY              |
3119                 MLX5_MKEY_MASK_LR               |
3120                 MLX5_MKEY_MASK_LW               |
3121                 MLX5_MKEY_MASK_RR               |
3122                 MLX5_MKEY_MASK_RW               |
3123                 MLX5_MKEY_MASK_SMALL_FENCE      |
3124                 MLX5_MKEY_MASK_FREE             |
3125                 MLX5_MKEY_MASK_BSF_EN;
3126
3127         return cpu_to_be64(result);
3128 }
3129
3130 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3131                             struct mlx5_ib_mr *mr)
3132 {
3133         int size = mr->ndescs * mr->desc_size;
3134
3135         memset(umr, 0, sizeof(*umr));
3136
3137         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3138         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3139         umr->mkey_mask = frwr_mkey_mask();
3140 }
3141
3142 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3143 {
3144         memset(umr, 0, sizeof(*umr));
3145         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3146         umr->flags = MLX5_UMR_INLINE;
3147 }
3148
3149 static __be64 get_umr_enable_mr_mask(void)
3150 {
3151         u64 result;
3152
3153         result = MLX5_MKEY_MASK_KEY |
3154                  MLX5_MKEY_MASK_FREE;
3155
3156         return cpu_to_be64(result);
3157 }
3158
3159 static __be64 get_umr_disable_mr_mask(void)
3160 {
3161         u64 result;
3162
3163         result = MLX5_MKEY_MASK_FREE;
3164
3165         return cpu_to_be64(result);
3166 }
3167
3168 static __be64 get_umr_update_translation_mask(void)
3169 {
3170         u64 result;
3171
3172         result = MLX5_MKEY_MASK_LEN |
3173                  MLX5_MKEY_MASK_PAGE_SIZE |
3174                  MLX5_MKEY_MASK_START_ADDR;
3175
3176         return cpu_to_be64(result);
3177 }
3178
3179 static __be64 get_umr_update_access_mask(int atomic)
3180 {
3181         u64 result;
3182
3183         result = MLX5_MKEY_MASK_LR |
3184                  MLX5_MKEY_MASK_LW |
3185                  MLX5_MKEY_MASK_RR |
3186                  MLX5_MKEY_MASK_RW;
3187
3188         if (atomic)
3189                 result |= MLX5_MKEY_MASK_A;
3190
3191         return cpu_to_be64(result);
3192 }
3193
3194 static __be64 get_umr_update_pd_mask(void)
3195 {
3196         u64 result;
3197
3198         result = MLX5_MKEY_MASK_PD;
3199
3200         return cpu_to_be64(result);
3201 }
3202
3203 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3204                                 struct ib_send_wr *wr, int atomic)
3205 {
3206         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3207
3208         memset(umr, 0, sizeof(*umr));
3209
3210         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3211                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3212         else
3213                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3214
3215         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3216         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3217                 u64 offset = get_xlt_octo(umrwr->offset);
3218
3219                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3220                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3221                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3222         }
3223         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3224                 umr->mkey_mask |= get_umr_update_translation_mask();
3225         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3226                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3227                 umr->mkey_mask |= get_umr_update_pd_mask();
3228         }
3229         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3230                 umr->mkey_mask |= get_umr_enable_mr_mask();
3231         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3232                 umr->mkey_mask |= get_umr_disable_mr_mask();
3233
3234         if (!wr->num_sge)
3235                 umr->flags |= MLX5_UMR_INLINE;
3236 }
3237
3238 static u8 get_umr_flags(int acc)
3239 {
3240         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3241                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3242                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3243                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3244                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3245 }
3246
3247 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3248                              struct mlx5_ib_mr *mr,
3249                              u32 key, int access)
3250 {
3251         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3252
3253         memset(seg, 0, sizeof(*seg));
3254
3255         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3256                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3257         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3258                 /* KLMs take twice the size of MTTs */
3259                 ndescs *= 2;
3260
3261         seg->flags = get_umr_flags(access) | mr->access_mode;
3262         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3263         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3264         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3265         seg->len = cpu_to_be64(mr->ibmr.length);
3266         seg->xlt_oct_size = cpu_to_be32(ndescs);
3267 }
3268
3269 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3270 {
3271         memset(seg, 0, sizeof(*seg));
3272         seg->status = MLX5_MKEY_STATUS_FREE;
3273 }
3274
3275 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3276 {
3277         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3278
3279         memset(seg, 0, sizeof(*seg));
3280         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3281                 seg->status = MLX5_MKEY_STATUS_FREE;
3282
3283         seg->flags = convert_access(umrwr->access_flags);
3284         if (umrwr->pd)
3285                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3286         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3287             !umrwr->length)
3288                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3289
3290         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3291         seg->len = cpu_to_be64(umrwr->length);
3292         seg->log2_page_size = umrwr->page_shift;
3293         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3294                                        mlx5_mkey_variant(umrwr->mkey));
3295 }
3296
3297 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3298                              struct mlx5_ib_mr *mr,
3299                              struct mlx5_ib_pd *pd)
3300 {
3301         int bcount = mr->desc_size * mr->ndescs;
3302
3303         dseg->addr = cpu_to_be64(mr->desc_map);
3304         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3305         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3306 }
3307
3308 static __be32 send_ieth(struct ib_send_wr *wr)
3309 {
3310         switch (wr->opcode) {
3311         case IB_WR_SEND_WITH_IMM:
3312         case IB_WR_RDMA_WRITE_WITH_IMM:
3313                 return wr->ex.imm_data;
3314
3315         case IB_WR_SEND_WITH_INV:
3316                 return cpu_to_be32(wr->ex.invalidate_rkey);
3317
3318         default:
3319                 return 0;
3320         }
3321 }
3322
3323 static u8 calc_sig(void *wqe, int size)
3324 {
3325         u8 *p = wqe;
3326         u8 res = 0;
3327         int i;
3328
3329         for (i = 0; i < size; i++)
3330                 res ^= p[i];
3331
3332         return ~res;
3333 }
3334
3335 static u8 wq_sig(void *wqe)
3336 {
3337         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3338 }
3339
3340 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3341                             void *wqe, int *sz)
3342 {
3343         struct mlx5_wqe_inline_seg *seg;
3344         void *qend = qp->sq.qend;
3345         void *addr;
3346         int inl = 0;
3347         int copy;
3348         int len;
3349         int i;
3350
3351         seg = wqe;
3352         wqe += sizeof(*seg);
3353         for (i = 0; i < wr->num_sge; i++) {
3354                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3355                 len  = wr->sg_list[i].length;
3356                 inl += len;
3357
3358                 if (unlikely(inl > qp->max_inline_data))
3359                         return -ENOMEM;
3360
3361                 if (unlikely(wqe + len > qend)) {
3362                         copy = qend - wqe;
3363                         memcpy(wqe, addr, copy);
3364                         addr += copy;
3365                         len -= copy;
3366                         wqe = mlx5_get_send_wqe(qp, 0);
3367                 }
3368                 memcpy(wqe, addr, len);
3369                 wqe += len;
3370         }
3371
3372         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3373
3374         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3375
3376         return 0;
3377 }
3378
3379 static u16 prot_field_size(enum ib_signature_type type)
3380 {
3381         switch (type) {
3382         case IB_SIG_TYPE_T10_DIF:
3383                 return MLX5_DIF_SIZE;
3384         default:
3385                 return 0;
3386         }
3387 }
3388
3389 static u8 bs_selector(int block_size)
3390 {
3391         switch (block_size) {
3392         case 512:           return 0x1;
3393         case 520:           return 0x2;
3394         case 4096:          return 0x3;
3395         case 4160:          return 0x4;
3396         case 1073741824:    return 0x5;
3397         default:            return 0;
3398         }
3399 }
3400
3401 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3402                               struct mlx5_bsf_inl *inl)
3403 {
3404         /* Valid inline section and allow BSF refresh */
3405         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3406                                        MLX5_BSF_REFRESH_DIF);
3407         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3408         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3409         /* repeating block */
3410         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3411         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3412                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
3413
3414         if (domain->sig.dif.ref_remap)
3415                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3416
3417         if (domain->sig.dif.app_escape) {
3418                 if (domain->sig.dif.ref_escape)
3419                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3420                 else
3421                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3422         }
3423
3424         inl->dif_app_bitmask_check =
3425                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3426 }
3427
3428 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3429                         struct ib_sig_attrs *sig_attrs,
3430                         struct mlx5_bsf *bsf, u32 data_size)
3431 {
3432         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3433         struct mlx5_bsf_basic *basic = &bsf->basic;
3434         struct ib_sig_domain *mem = &sig_attrs->mem;
3435         struct ib_sig_domain *wire = &sig_attrs->wire;
3436
3437         memset(bsf, 0, sizeof(*bsf));
3438
3439         /* Basic + Extended + Inline */
3440         basic->bsf_size_sbs = 1 << 7;
3441         /* Input domain check byte mask */
3442         basic->check_byte_mask = sig_attrs->check_mask;
3443         basic->raw_data_size = cpu_to_be32(data_size);
3444
3445         /* Memory domain */
3446         switch (sig_attrs->mem.sig_type) {
3447         case IB_SIG_TYPE_NONE:
3448                 break;
3449         case IB_SIG_TYPE_T10_DIF:
3450                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3451                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3452                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3453                 break;
3454         default:
3455                 return -EINVAL;
3456         }
3457
3458         /* Wire domain */
3459         switch (sig_attrs->wire.sig_type) {
3460         case IB_SIG_TYPE_NONE:
3461                 break;
3462         case IB_SIG_TYPE_T10_DIF:
3463                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3464                     mem->sig_type == wire->sig_type) {
3465                         /* Same block structure */
3466                         basic->bsf_size_sbs |= 1 << 4;
3467                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3468                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3469                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3470                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3471                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3472                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3473                 } else
3474                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3475
3476                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3477                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3478                 break;
3479         default:
3480                 return -EINVAL;
3481         }
3482
3483         return 0;
3484 }
3485
3486 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3487                                 struct mlx5_ib_qp *qp, void **seg, int *size)
3488 {
3489         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3490         struct ib_mr *sig_mr = wr->sig_mr;
3491         struct mlx5_bsf *bsf;
3492         u32 data_len = wr->wr.sg_list->length;
3493         u32 data_key = wr->wr.sg_list->lkey;
3494         u64 data_va = wr->wr.sg_list->addr;
3495         int ret;
3496         int wqe_size;
3497
3498         if (!wr->prot ||
3499             (data_key == wr->prot->lkey &&
3500              data_va == wr->prot->addr &&
3501              data_len == wr->prot->length)) {
3502                 /**
3503                  * Source domain doesn't contain signature information
3504                  * or data and protection are interleaved in memory.
3505                  * So need construct:
3506                  *                  ------------------
3507                  *                 |     data_klm     |
3508                  *                  ------------------
3509                  *                 |       BSF        |
3510                  *                  ------------------
3511                  **/
3512                 struct mlx5_klm *data_klm = *seg;
3513
3514                 data_klm->bcount = cpu_to_be32(data_len);
3515                 data_klm->key = cpu_to_be32(data_key);
3516                 data_klm->va = cpu_to_be64(data_va);
3517                 wqe_size = ALIGN(sizeof(*data_klm), 64);
3518         } else {
3519                 /**
3520                  * Source domain contains signature information
3521                  * So need construct a strided block format:
3522                  *               ---------------------------
3523                  *              |     stride_block_ctrl     |
3524                  *               ---------------------------
3525                  *              |          data_klm         |
3526                  *               ---------------------------
3527                  *              |          prot_klm         |
3528                  *               ---------------------------
3529                  *              |             BSF           |
3530                  *               ---------------------------
3531                  **/
3532                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3533                 struct mlx5_stride_block_entry *data_sentry;
3534                 struct mlx5_stride_block_entry *prot_sentry;
3535                 u32 prot_key = wr->prot->lkey;
3536                 u64 prot_va = wr->prot->addr;
3537                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3538                 int prot_size;
3539
3540                 sblock_ctrl = *seg;
3541                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3542                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3543
3544                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3545                 if (!prot_size) {
3546                         pr_err("Bad block size given: %u\n", block_size);
3547                         return -EINVAL;
3548                 }
3549                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3550                                                             prot_size);
3551                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3552                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3553                 sblock_ctrl->num_entries = cpu_to_be16(2);
3554
3555                 data_sentry->bcount = cpu_to_be16(block_size);
3556                 data_sentry->key = cpu_to_be32(data_key);
3557                 data_sentry->va = cpu_to_be64(data_va);
3558                 data_sentry->stride = cpu_to_be16(block_size);
3559
3560                 prot_sentry->bcount = cpu_to_be16(prot_size);
3561                 prot_sentry->key = cpu_to_be32(prot_key);
3562                 prot_sentry->va = cpu_to_be64(prot_va);
3563                 prot_sentry->stride = cpu_to_be16(prot_size);
3564
3565                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3566                                  sizeof(*prot_sentry), 64);
3567         }
3568
3569         *seg += wqe_size;
3570         *size += wqe_size / 16;
3571         if (unlikely((*seg == qp->sq.qend)))
3572                 *seg = mlx5_get_send_wqe(qp, 0);
3573
3574         bsf = *seg;
3575         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3576         if (ret)
3577                 return -EINVAL;
3578
3579         *seg += sizeof(*bsf);
3580         *size += sizeof(*bsf) / 16;
3581         if (unlikely((*seg == qp->sq.qend)))
3582                 *seg = mlx5_get_send_wqe(qp, 0);
3583
3584         return 0;
3585 }
3586
3587 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3588                                  struct ib_sig_handover_wr *wr, u32 size,
3589                                  u32 length, u32 pdn)
3590 {
3591         struct ib_mr *sig_mr = wr->sig_mr;
3592         u32 sig_key = sig_mr->rkey;
3593         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3594
3595         memset(seg, 0, sizeof(*seg));
3596
3597         seg->flags = get_umr_flags(wr->access_flags) |
3598                                    MLX5_MKC_ACCESS_MODE_KLMS;
3599         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3600         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3601                                     MLX5_MKEY_BSF_EN | pdn);
3602         seg->len = cpu_to_be64(length);
3603         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
3604         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3605 }
3606
3607 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3608                                 u32 size)
3609 {
3610         memset(umr, 0, sizeof(*umr));
3611
3612         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3613         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3614         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3615         umr->mkey_mask = sig_mkey_mask();
3616 }
3617
3618
3619 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3620                           void **seg, int *size)
3621 {
3622         struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3623         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3624         u32 pdn = get_pd(qp)->pdn;
3625         u32 xlt_size;
3626         int region_len, ret;
3627
3628         if (unlikely(wr->wr.num_sge != 1) ||
3629             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3630             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3631             unlikely(!sig_mr->sig->sig_status_checked))
3632                 return -EINVAL;
3633
3634         /* length of the protected region, data + protection */
3635         region_len = wr->wr.sg_list->length;
3636         if (wr->prot &&
3637             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
3638              wr->prot->addr != wr->wr.sg_list->addr  ||
3639              wr->prot->length != wr->wr.sg_list->length))
3640                 region_len += wr->prot->length;
3641
3642         /**
3643          * KLM octoword size - if protection was provided
3644          * then we use strided block format (3 octowords),
3645          * else we use single KLM (1 octoword)
3646          **/
3647         xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
3648
3649         set_sig_umr_segment(*seg, xlt_size);
3650         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3651         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3652         if (unlikely((*seg == qp->sq.qend)))
3653                 *seg = mlx5_get_send_wqe(qp, 0);
3654
3655         set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
3656         *seg += sizeof(struct mlx5_mkey_seg);
3657         *size += sizeof(struct mlx5_mkey_seg) / 16;
3658         if (unlikely((*seg == qp->sq.qend)))
3659                 *seg = mlx5_get_send_wqe(qp, 0);
3660
3661         ret = set_sig_data_segment(wr, qp, seg, size);
3662         if (ret)
3663                 return ret;
3664
3665         sig_mr->sig->sig_status_checked = false;
3666         return 0;
3667 }
3668
3669 static int set_psv_wr(struct ib_sig_domain *domain,
3670                       u32 psv_idx, void **seg, int *size)
3671 {
3672         struct mlx5_seg_set_psv *psv_seg = *seg;
3673
3674         memset(psv_seg, 0, sizeof(*psv_seg));
3675         psv_seg->psv_num = cpu_to_be32(psv_idx);
3676         switch (domain->sig_type) {
3677         case IB_SIG_TYPE_NONE:
3678                 break;
3679         case IB_SIG_TYPE_T10_DIF:
3680                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3681                                                      domain->sig.dif.app_tag);
3682                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3683                 break;
3684         default:
3685                 pr_err("Bad signature type given.\n");
3686                 return 1;
3687         }
3688
3689         *seg += sizeof(*psv_seg);
3690         *size += sizeof(*psv_seg) / 16;
3691
3692         return 0;
3693 }
3694
3695 static int set_reg_wr(struct mlx5_ib_qp *qp,
3696                       struct ib_reg_wr *wr,
3697                       void **seg, int *size)
3698 {
3699         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3700         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3701
3702         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3703                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3704                              "Invalid IB_SEND_INLINE send flag\n");
3705                 return -EINVAL;
3706         }
3707
3708         set_reg_umr_seg(*seg, mr);
3709         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3710         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3711         if (unlikely((*seg == qp->sq.qend)))
3712                 *seg = mlx5_get_send_wqe(qp, 0);
3713
3714         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3715         *seg += sizeof(struct mlx5_mkey_seg);
3716         *size += sizeof(struct mlx5_mkey_seg) / 16;
3717         if (unlikely((*seg == qp->sq.qend)))
3718                 *seg = mlx5_get_send_wqe(qp, 0);
3719
3720         set_reg_data_seg(*seg, mr, pd);
3721         *seg += sizeof(struct mlx5_wqe_data_seg);
3722         *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3723
3724         return 0;
3725 }
3726
3727 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3728 {
3729         set_linv_umr_seg(*seg);
3730         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3731         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3732         if (unlikely((*seg == qp->sq.qend)))
3733                 *seg = mlx5_get_send_wqe(qp, 0);
3734         set_linv_mkey_seg(*seg);
3735         *seg += sizeof(struct mlx5_mkey_seg);
3736         *size += sizeof(struct mlx5_mkey_seg) / 16;
3737         if (unlikely((*seg == qp->sq.qend)))
3738                 *seg = mlx5_get_send_wqe(qp, 0);
3739 }
3740
3741 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3742 {
3743         __be32 *p = NULL;
3744         int tidx = idx;
3745         int i, j;
3746
3747         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3748         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3749                 if ((i & 0xf) == 0) {
3750                         void *buf = mlx5_get_send_wqe(qp, tidx);
3751                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3752                         p = buf;
3753                         j = 0;
3754                 }
3755                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3756                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3757                          be32_to_cpu(p[j + 3]));
3758         }
3759 }
3760
3761 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3762                          unsigned bytecnt, struct mlx5_ib_qp *qp)
3763 {
3764         while (bytecnt > 0) {
3765                 __iowrite64_copy(dst++, src++, 8);
3766                 __iowrite64_copy(dst++, src++, 8);
3767                 __iowrite64_copy(dst++, src++, 8);
3768                 __iowrite64_copy(dst++, src++, 8);
3769                 __iowrite64_copy(dst++, src++, 8);
3770                 __iowrite64_copy(dst++, src++, 8);
3771                 __iowrite64_copy(dst++, src++, 8);
3772                 __iowrite64_copy(dst++, src++, 8);
3773                 bytecnt -= 64;
3774                 if (unlikely(src == qp->sq.qend))
3775                         src = mlx5_get_send_wqe(qp, 0);
3776         }
3777 }
3778
3779 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3780 {
3781         if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3782                      wr->send_flags & IB_SEND_FENCE))
3783                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3784
3785         if (unlikely(fence)) {
3786                 if (wr->send_flags & IB_SEND_FENCE)
3787                         return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3788                 else
3789                         return fence;
3790         } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3791                 return MLX5_FENCE_MODE_FENCE;
3792         }
3793
3794         return 0;
3795 }
3796
3797 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3798                      struct mlx5_wqe_ctrl_seg **ctrl,
3799                      struct ib_send_wr *wr, unsigned *idx,
3800                      int *size, int nreq)
3801 {
3802         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3803                 return -ENOMEM;
3804
3805         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3806         *seg = mlx5_get_send_wqe(qp, *idx);
3807         *ctrl = *seg;
3808         *(uint32_t *)(*seg + 8) = 0;
3809         (*ctrl)->imm = send_ieth(wr);
3810         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3811                 (wr->send_flags & IB_SEND_SIGNALED ?
3812                  MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3813                 (wr->send_flags & IB_SEND_SOLICITED ?
3814                  MLX5_WQE_CTRL_SOLICITED : 0);
3815
3816         *seg += sizeof(**ctrl);
3817         *size = sizeof(**ctrl) / 16;
3818
3819         return 0;
3820 }
3821
3822 static void finish_wqe(struct mlx5_ib_qp *qp,
3823                        struct mlx5_wqe_ctrl_seg *ctrl,
3824                        u8 size, unsigned idx, u64 wr_id,
3825                        int nreq, u8 fence, u8 next_fence,
3826                        u32 mlx5_opcode)
3827 {
3828         u8 opmod = 0;
3829
3830         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3831                                              mlx5_opcode | ((u32)opmod << 24));
3832         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3833         ctrl->fm_ce_se |= fence;
3834         qp->fm_cache = next_fence;
3835         if (unlikely(qp->wq_sig))
3836                 ctrl->signature = wq_sig(ctrl);
3837
3838         qp->sq.wrid[idx] = wr_id;
3839         qp->sq.w_list[idx].opcode = mlx5_opcode;
3840         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3841         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3842         qp->sq.w_list[idx].next = qp->sq.cur_post;
3843 }
3844
3845
3846 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3847                       struct ib_send_wr **bad_wr)
3848 {
3849         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
3850         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3851         struct mlx5_core_dev *mdev = dev->mdev;
3852         struct mlx5_ib_qp *qp;
3853         struct mlx5_ib_mr *mr;
3854         struct mlx5_wqe_data_seg *dpseg;
3855         struct mlx5_wqe_xrc_seg *xrc;
3856         struct mlx5_bf *bf;
3857         int uninitialized_var(size);
3858         void *qend;
3859         unsigned long flags;
3860         unsigned idx;
3861         int err = 0;
3862         int inl = 0;
3863         int num_sge;
3864         void *seg;
3865         int nreq;
3866         int i;
3867         u8 next_fence = 0;
3868         u8 fence;
3869
3870         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3871                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3872
3873         qp = to_mqp(ibqp);
3874         bf = qp->bf;
3875         qend = qp->sq.qend;
3876
3877         spin_lock_irqsave(&qp->sq.lock, flags);
3878
3879         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3880                 err = -EIO;
3881                 *bad_wr = wr;
3882                 nreq = 0;
3883                 goto out;
3884         }
3885
3886         for (nreq = 0; wr; nreq++, wr = wr->next) {
3887                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3888                         mlx5_ib_warn(dev, "\n");
3889                         err = -EINVAL;
3890                         *bad_wr = wr;
3891                         goto out;
3892                 }
3893
3894                 fence = qp->fm_cache;
3895                 num_sge = wr->num_sge;
3896                 if (unlikely(num_sge > qp->sq.max_gs)) {
3897                         mlx5_ib_warn(dev, "\n");
3898                         err = -EINVAL;
3899                         *bad_wr = wr;
3900                         goto out;
3901                 }
3902
3903                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3904                 if (err) {
3905                         mlx5_ib_warn(dev, "\n");
3906                         err = -ENOMEM;
3907                         *bad_wr = wr;
3908                         goto out;
3909                 }
3910
3911                 switch (ibqp->qp_type) {
3912                 case IB_QPT_XRC_INI:
3913                         xrc = seg;
3914                         seg += sizeof(*xrc);
3915                         size += sizeof(*xrc) / 16;
3916                         /* fall through */
3917                 case IB_QPT_RC:
3918                         switch (wr->opcode) {
3919                         case IB_WR_RDMA_READ:
3920                         case IB_WR_RDMA_WRITE:
3921                         case IB_WR_RDMA_WRITE_WITH_IMM:
3922                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3923                                               rdma_wr(wr)->rkey);
3924                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
3925                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3926                                 break;
3927
3928                         case IB_WR_ATOMIC_CMP_AND_SWP:
3929                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3930                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3931                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3932                                 err = -ENOSYS;
3933                                 *bad_wr = wr;
3934                                 goto out;
3935
3936                         case IB_WR_LOCAL_INV:
3937                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3938                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3939                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3940                                 set_linv_wr(qp, &seg, &size);
3941                                 num_sge = 0;
3942                                 break;
3943
3944                         case IB_WR_REG_MR:
3945                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3946                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3947                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3948                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3949                                 if (err) {
3950                                         *bad_wr = wr;
3951                                         goto out;
3952                                 }
3953                                 num_sge = 0;
3954                                 break;
3955
3956                         case IB_WR_REG_SIG_MR:
3957                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3958                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3959
3960                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3961                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
3962                                 if (err) {
3963                                         mlx5_ib_warn(dev, "\n");
3964                                         *bad_wr = wr;
3965                                         goto out;
3966                                 }
3967
3968                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3969                                            nreq, get_fence(fence, wr),
3970                                            next_fence, MLX5_OPCODE_UMR);
3971                                 /*
3972                                  * SET_PSV WQEs are not signaled and solicited
3973                                  * on error
3974                                  */
3975                                 wr->send_flags &= ~IB_SEND_SIGNALED;
3976                                 wr->send_flags |= IB_SEND_SOLICITED;
3977                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3978                                                 &idx, &size, nreq);
3979                                 if (err) {
3980                                         mlx5_ib_warn(dev, "\n");
3981                                         err = -ENOMEM;
3982                                         *bad_wr = wr;
3983                                         goto out;
3984                                 }
3985
3986                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3987                                                  mr->sig->psv_memory.psv_idx, &seg,
3988                                                  &size);
3989                                 if (err) {
3990                                         mlx5_ib_warn(dev, "\n");
3991                                         *bad_wr = wr;
3992                                         goto out;
3993                                 }
3994
3995                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3996                                            nreq, get_fence(fence, wr),
3997                                            next_fence, MLX5_OPCODE_SET_PSV);
3998                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3999                                                 &idx, &size, nreq);
4000                                 if (err) {
4001                                         mlx5_ib_warn(dev, "\n");
4002                                         err = -ENOMEM;
4003                                         *bad_wr = wr;
4004                                         goto out;
4005                                 }
4006
4007                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4008                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4009                                                  mr->sig->psv_wire.psv_idx, &seg,
4010                                                  &size);
4011                                 if (err) {
4012                                         mlx5_ib_warn(dev, "\n");
4013                                         *bad_wr = wr;
4014                                         goto out;
4015                                 }
4016
4017                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
4018                                            nreq, get_fence(fence, wr),
4019                                            next_fence, MLX5_OPCODE_SET_PSV);
4020                                 num_sge = 0;
4021                                 goto skip_psv;
4022
4023                         default:
4024                                 break;
4025                         }
4026                         break;
4027
4028                 case IB_QPT_UC:
4029                         switch (wr->opcode) {
4030                         case IB_WR_RDMA_WRITE:
4031                         case IB_WR_RDMA_WRITE_WITH_IMM:
4032                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4033                                               rdma_wr(wr)->rkey);
4034                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
4035                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4036                                 break;
4037
4038                         default:
4039                                 break;
4040                         }
4041                         break;
4042
4043                 case IB_QPT_SMI:
4044                 case MLX5_IB_QPT_HW_GSI:
4045                         set_datagram_seg(seg, wr);
4046                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4047                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4048                         if (unlikely((seg == qend)))
4049                                 seg = mlx5_get_send_wqe(qp, 0);
4050                         break;
4051                 case IB_QPT_UD:
4052                         set_datagram_seg(seg, wr);
4053                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4054                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4055
4056                         if (unlikely((seg == qend)))
4057                                 seg = mlx5_get_send_wqe(qp, 0);
4058
4059                         /* handle qp that supports ud offload */
4060                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4061                                 struct mlx5_wqe_eth_pad *pad;
4062
4063                                 pad = seg;
4064                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4065                                 seg += sizeof(struct mlx5_wqe_eth_pad);
4066                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4067
4068                                 seg = set_eth_seg(seg, wr, qend, qp, &size);
4069
4070                                 if (unlikely((seg == qend)))
4071                                         seg = mlx5_get_send_wqe(qp, 0);
4072                         }
4073                         break;
4074                 case MLX5_IB_QPT_REG_UMR:
4075                         if (wr->opcode != MLX5_IB_WR_UMR) {
4076                                 err = -EINVAL;
4077                                 mlx5_ib_warn(dev, "bad opcode\n");
4078                                 goto out;
4079                         }
4080                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4081                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4082                         set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4083                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4084                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4085                         if (unlikely((seg == qend)))
4086                                 seg = mlx5_get_send_wqe(qp, 0);
4087                         set_reg_mkey_segment(seg, wr);
4088                         seg += sizeof(struct mlx5_mkey_seg);
4089                         size += sizeof(struct mlx5_mkey_seg) / 16;
4090                         if (unlikely((seg == qend)))
4091                                 seg = mlx5_get_send_wqe(qp, 0);
4092                         break;
4093
4094                 default:
4095                         break;
4096                 }
4097
4098                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4099                         int uninitialized_var(sz);
4100
4101                         err = set_data_inl_seg(qp, wr, seg, &sz);
4102                         if (unlikely(err)) {
4103                                 mlx5_ib_warn(dev, "\n");
4104                                 *bad_wr = wr;
4105                                 goto out;
4106                         }
4107                         inl = 1;
4108                         size += sz;
4109                 } else {
4110                         dpseg = seg;
4111                         for (i = 0; i < num_sge; i++) {
4112                                 if (unlikely(dpseg == qend)) {
4113                                         seg = mlx5_get_send_wqe(qp, 0);
4114                                         dpseg = seg;
4115                                 }
4116                                 if (likely(wr->sg_list[i].length)) {
4117                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
4118                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
4119                                         dpseg++;
4120                                 }
4121                         }
4122                 }
4123
4124                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4125                            get_fence(fence, wr), next_fence,
4126                            mlx5_ib_opcode[wr->opcode]);
4127 skip_psv:
4128                 if (0)
4129                         dump_wqe(qp, idx, size);
4130         }
4131
4132 out:
4133         if (likely(nreq)) {
4134                 qp->sq.head += nreq;
4135
4136                 /* Make sure that descriptors are written before
4137                  * updating doorbell record and ringing the doorbell
4138                  */
4139                 wmb();
4140
4141                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4142
4143                 /* Make sure doorbell record is visible to the HCA before
4144                  * we hit doorbell */
4145                 wmb();
4146
4147                 if (bf->need_lock)
4148                         spin_lock(&bf->lock);
4149                 else
4150                         __acquire(&bf->lock);
4151
4152                 /* TBD enable WC */
4153                 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
4154                         mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
4155                         /* wc_wmb(); */
4156                 } else {
4157                         mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
4158                                      MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4159                         /* Make sure doorbells don't leak out of SQ spinlock
4160                          * and reach the HCA out of order.
4161                          */
4162                         mmiowb();
4163                 }
4164                 bf->offset ^= bf->buf_size;
4165                 if (bf->need_lock)
4166                         spin_unlock(&bf->lock);
4167                 else
4168                         __release(&bf->lock);
4169         }
4170
4171         spin_unlock_irqrestore(&qp->sq.lock, flags);
4172
4173         return err;
4174 }
4175
4176 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4177 {
4178         sig->signature = calc_sig(sig, size);
4179 }
4180
4181 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4182                       struct ib_recv_wr **bad_wr)
4183 {
4184         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4185         struct mlx5_wqe_data_seg *scat;
4186         struct mlx5_rwqe_sig *sig;
4187         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4188         struct mlx5_core_dev *mdev = dev->mdev;
4189         unsigned long flags;
4190         int err = 0;
4191         int nreq;
4192         int ind;
4193         int i;
4194
4195         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4196                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4197
4198         spin_lock_irqsave(&qp->rq.lock, flags);
4199
4200         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4201                 err = -EIO;
4202                 *bad_wr = wr;
4203                 nreq = 0;
4204                 goto out;
4205         }
4206
4207         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4208
4209         for (nreq = 0; wr; nreq++, wr = wr->next) {
4210                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4211                         err = -ENOMEM;
4212                         *bad_wr = wr;
4213                         goto out;
4214                 }
4215
4216                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4217                         err = -EINVAL;
4218                         *bad_wr = wr;
4219                         goto out;
4220                 }
4221
4222                 scat = get_recv_wqe(qp, ind);
4223                 if (qp->wq_sig)
4224                         scat++;
4225
4226                 for (i = 0; i < wr->num_sge; i++)
4227                         set_data_ptr_seg(scat + i, wr->sg_list + i);
4228
4229                 if (i < qp->rq.max_gs) {
4230                         scat[i].byte_count = 0;
4231                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4232                         scat[i].addr       = 0;
4233                 }
4234
4235                 if (qp->wq_sig) {
4236                         sig = (struct mlx5_rwqe_sig *)scat;
4237                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4238                 }
4239
4240                 qp->rq.wrid[ind] = wr->wr_id;
4241
4242                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4243         }
4244
4245 out:
4246         if (likely(nreq)) {
4247                 qp->rq.head += nreq;
4248
4249                 /* Make sure that descriptors are written before
4250                  * doorbell record.
4251                  */
4252                 wmb();
4253
4254                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4255         }
4256
4257         spin_unlock_irqrestore(&qp->rq.lock, flags);
4258
4259         return err;
4260 }
4261
4262 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4263 {
4264         switch (mlx5_state) {
4265         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4266         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4267         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4268         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4269         case MLX5_QP_STATE_SQ_DRAINING:
4270         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4271         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4272         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4273         default:                     return -1;
4274         }
4275 }
4276
4277 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4278 {
4279         switch (mlx5_mig_state) {
4280         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4281         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4282         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4283         default: return -1;
4284         }
4285 }
4286
4287 static int to_ib_qp_access_flags(int mlx5_flags)
4288 {
4289         int ib_flags = 0;
4290
4291         if (mlx5_flags & MLX5_QP_BIT_RRE)
4292                 ib_flags |= IB_ACCESS_REMOTE_READ;
4293         if (mlx5_flags & MLX5_QP_BIT_RWE)
4294                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4295         if (mlx5_flags & MLX5_QP_BIT_RAE)
4296                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4297
4298         return ib_flags;
4299 }
4300
4301 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4302                                 struct mlx5_qp_path *path)
4303 {
4304         struct mlx5_core_dev *dev = ibdev->mdev;
4305
4306         memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4307         ib_ah_attr->port_num      = path->port;
4308
4309         if (ib_ah_attr->port_num == 0 ||
4310             ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
4311                 return;
4312
4313         ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
4314
4315         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
4316         ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4317         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
4318         ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4319         if (ib_ah_attr->ah_flags) {
4320                 ib_ah_attr->grh.sgid_index = path->mgid_index;
4321                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
4322                 ib_ah_attr->grh.traffic_class =
4323                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4324                 ib_ah_attr->grh.flow_label =
4325                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4326                 memcpy(ib_ah_attr->grh.dgid.raw,
4327                        path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4328         }
4329 }
4330
4331 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4332                                         struct mlx5_ib_sq *sq,
4333                                         u8 *sq_state)
4334 {
4335         void *out;
4336         void *sqc;
4337         int inlen;
4338         int err;
4339
4340         inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4341         out = mlx5_vzalloc(inlen);
4342         if (!out)
4343                 return -ENOMEM;
4344
4345         err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4346         if (err)
4347                 goto out;
4348
4349         sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4350         *sq_state = MLX5_GET(sqc, sqc, state);
4351         sq->state = *sq_state;
4352
4353 out:
4354         kvfree(out);
4355         return err;
4356 }
4357
4358 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4359                                         struct mlx5_ib_rq *rq,
4360                                         u8 *rq_state)
4361 {
4362         void *out;
4363         void *rqc;
4364         int inlen;
4365         int err;
4366
4367         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4368         out = mlx5_vzalloc(inlen);
4369         if (!out)
4370                 return -ENOMEM;
4371
4372         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4373         if (err)
4374                 goto out;
4375
4376         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4377         *rq_state = MLX5_GET(rqc, rqc, state);
4378         rq->state = *rq_state;
4379
4380 out:
4381         kvfree(out);
4382         return err;
4383 }
4384
4385 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4386                                   struct mlx5_ib_qp *qp, u8 *qp_state)
4387 {
4388         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4389                 [MLX5_RQC_STATE_RST] = {
4390                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4391                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4392                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
4393                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
4394                 },
4395                 [MLX5_RQC_STATE_RDY] = {
4396                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4397                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4398                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
4399                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
4400                 },
4401                 [MLX5_RQC_STATE_ERR] = {
4402                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4403                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4404                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
4405                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
4406                 },
4407                 [MLX5_RQ_STATE_NA] = {
4408                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4409                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4410                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
4411                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
4412                 },
4413         };
4414
4415         *qp_state = sqrq_trans[rq_state][sq_state];
4416
4417         if (*qp_state == MLX5_QP_STATE_BAD) {
4418                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4419                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4420                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4421                 return -EINVAL;
4422         }
4423
4424         if (*qp_state == MLX5_QP_STATE)
4425                 *qp_state = qp->state;
4426
4427         return 0;
4428 }
4429
4430 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4431                                      struct mlx5_ib_qp *qp,
4432                                      u8 *raw_packet_qp_state)
4433 {
4434         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4435         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4436         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4437         int err;
4438         u8 sq_state = MLX5_SQ_STATE_NA;
4439         u8 rq_state = MLX5_RQ_STATE_NA;
4440
4441         if (qp->sq.wqe_cnt) {
4442                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4443                 if (err)
4444                         return err;
4445         }
4446
4447         if (qp->rq.wqe_cnt) {
4448                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4449                 if (err)
4450                         return err;
4451         }
4452
4453         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4454                                       raw_packet_qp_state);
4455 }
4456
4457 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4458                          struct ib_qp_attr *qp_attr)
4459 {
4460         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4461         struct mlx5_qp_context *context;
4462         int mlx5_state;
4463         u32 *outb;
4464         int err = 0;
4465
4466         outb = kzalloc(outlen, GFP_KERNEL);
4467         if (!outb)
4468                 return -ENOMEM;
4469
4470         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4471                                  outlen);
4472         if (err)
4473                 goto out;
4474
4475         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4476         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4477
4478         mlx5_state = be32_to_cpu(context->flags) >> 28;
4479
4480         qp->state                    = to_ib_qp_state(mlx5_state);
4481         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
4482         qp_attr->path_mig_state      =
4483                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4484         qp_attr->qkey                = be32_to_cpu(context->qkey);
4485         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4486         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
4487         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4488         qp_attr->qp_access_flags     =
4489                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4490
4491         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4492                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4493                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4494                 qp_attr->alt_pkey_index =
4495                         be16_to_cpu(context->alt_path.pkey_index);
4496                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
4497         }
4498
4499         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4500         qp_attr->port_num = context->pri_path.port;
4501
4502         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4503         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4504
4505         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4506
4507         qp_attr->max_dest_rd_atomic =
4508                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4509         qp_attr->min_rnr_timer      =
4510                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4511         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
4512         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
4513         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
4514         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
4515
4516 out:
4517         kfree(outb);
4518         return err;
4519 }
4520
4521 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4522                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4523 {
4524         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4525         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4526         int err = 0;
4527         u8 raw_packet_qp_state;
4528
4529         if (ibqp->rwq_ind_tbl)
4530                 return -ENOSYS;
4531
4532         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4533                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4534                                             qp_init_attr);
4535
4536 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4537         /*
4538          * Wait for any outstanding page faults, in case the user frees memory
4539          * based upon this query's result.
4540          */
4541         flush_workqueue(mlx5_ib_page_fault_wq);
4542 #endif
4543
4544         mutex_lock(&qp->mutex);
4545
4546         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4547                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4548                 if (err)
4549                         goto out;
4550                 qp->state = raw_packet_qp_state;
4551                 qp_attr->port_num = 1;
4552         } else {
4553                 err = query_qp_attr(dev, qp, qp_attr);
4554                 if (err)
4555                         goto out;
4556         }
4557
4558         qp_attr->qp_state            = qp->state;
4559         qp_attr->cur_qp_state        = qp_attr->qp_state;
4560         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4561         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4562
4563         if (!ibqp->uobject) {
4564                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
4565                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4566                 qp_init_attr->qp_context = ibqp->qp_context;
4567         } else {
4568                 qp_attr->cap.max_send_wr  = 0;
4569                 qp_attr->cap.max_send_sge = 0;
4570         }
4571
4572         qp_init_attr->qp_type = ibqp->qp_type;
4573         qp_init_attr->recv_cq = ibqp->recv_cq;
4574         qp_init_attr->send_cq = ibqp->send_cq;
4575         qp_init_attr->srq = ibqp->srq;
4576         qp_attr->cap.max_inline_data = qp->max_inline_data;
4577
4578         qp_init_attr->cap            = qp_attr->cap;
4579
4580         qp_init_attr->create_flags = 0;
4581         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4582                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4583
4584         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4585                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4586         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4587                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4588         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4589                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4590         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4591                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4592
4593         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4594                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4595
4596 out:
4597         mutex_unlock(&qp->mutex);
4598         return err;
4599 }
4600
4601 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4602                                           struct ib_ucontext *context,
4603                                           struct ib_udata *udata)
4604 {
4605         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4606         struct mlx5_ib_xrcd *xrcd;
4607         int err;
4608
4609         if (!MLX5_CAP_GEN(dev->mdev, xrc))
4610                 return ERR_PTR(-ENOSYS);
4611
4612         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4613         if (!xrcd)
4614                 return ERR_PTR(-ENOMEM);
4615
4616         err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4617         if (err) {
4618                 kfree(xrcd);
4619                 return ERR_PTR(-ENOMEM);
4620         }
4621
4622         return &xrcd->ibxrcd;
4623 }
4624
4625 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4626 {
4627         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4628         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4629         int err;
4630
4631         err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4632         if (err) {
4633                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4634                 return err;
4635         }
4636
4637         kfree(xrcd);
4638
4639         return 0;
4640 }
4641
4642 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4643 {
4644         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4645         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4646         struct ib_event event;
4647
4648         if (rwq->ibwq.event_handler) {
4649                 event.device     = rwq->ibwq.device;
4650                 event.element.wq = &rwq->ibwq;
4651                 switch (type) {
4652                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4653                         event.event = IB_EVENT_WQ_FATAL;
4654                         break;
4655                 default:
4656                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4657                         return;
4658                 }
4659
4660                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4661         }
4662 }
4663
4664 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4665                       struct ib_wq_init_attr *init_attr)
4666 {
4667         struct mlx5_ib_dev *dev;
4668         __be64 *rq_pas0;
4669         void *in;
4670         void *rqc;
4671         void *wq;
4672         int inlen;
4673         int err;
4674
4675         dev = to_mdev(pd->device);
4676
4677         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4678         in = mlx5_vzalloc(inlen);
4679         if (!in)
4680                 return -ENOMEM;
4681
4682         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4683         MLX5_SET(rqc,  rqc, mem_rq_type,
4684                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4685         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4686         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4687         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4688         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4689         wq = MLX5_ADDR_OF(rqc, rqc, wq);
4690         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4691         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4692         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4693         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4694         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4695         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4696         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4697         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4698         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4699         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4700         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4701         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4702         kvfree(in);
4703         return err;
4704 }
4705
4706 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4707                             struct ib_wq_init_attr *wq_init_attr,
4708                             struct mlx5_ib_create_wq *ucmd,
4709                             struct mlx5_ib_rwq *rwq)
4710 {
4711         /* Sanity check RQ size before proceeding */
4712         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4713                 return -EINVAL;
4714
4715         if (!ucmd->rq_wqe_count)
4716                 return -EINVAL;
4717
4718         rwq->wqe_count = ucmd->rq_wqe_count;
4719         rwq->wqe_shift = ucmd->rq_wqe_shift;
4720         rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4721         rwq->log_rq_stride = rwq->wqe_shift;
4722         rwq->log_rq_size = ilog2(rwq->wqe_count);
4723         return 0;
4724 }
4725
4726 static int prepare_user_rq(struct ib_pd *pd,
4727                            struct ib_wq_init_attr *init_attr,
4728                            struct ib_udata *udata,
4729                            struct mlx5_ib_rwq *rwq)
4730 {
4731         struct mlx5_ib_dev *dev = to_mdev(pd->device);
4732         struct mlx5_ib_create_wq ucmd = {};
4733         int err;
4734         size_t required_cmd_sz;
4735
4736         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4737         if (udata->inlen < required_cmd_sz) {
4738                 mlx5_ib_dbg(dev, "invalid inlen\n");
4739                 return -EINVAL;
4740         }
4741
4742         if (udata->inlen > sizeof(ucmd) &&
4743             !ib_is_udata_cleared(udata, sizeof(ucmd),
4744                                  udata->inlen - sizeof(ucmd))) {
4745                 mlx5_ib_dbg(dev, "inlen is not supported\n");
4746                 return -EOPNOTSUPP;
4747         }
4748
4749         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4750                 mlx5_ib_dbg(dev, "copy failed\n");
4751                 return -EFAULT;
4752         }
4753
4754         if (ucmd.comp_mask) {
4755                 mlx5_ib_dbg(dev, "invalid comp mask\n");
4756                 return -EOPNOTSUPP;
4757         }
4758
4759         if (ucmd.reserved) {
4760                 mlx5_ib_dbg(dev, "invalid reserved\n");
4761                 return -EOPNOTSUPP;
4762         }
4763
4764         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4765         if (err) {
4766                 mlx5_ib_dbg(dev, "err %d\n", err);
4767                 return err;
4768         }
4769
4770         err = create_user_rq(dev, pd, rwq, &ucmd);
4771         if (err) {
4772                 mlx5_ib_dbg(dev, "err %d\n", err);
4773                 if (err)
4774                         return err;
4775         }
4776
4777         rwq->user_index = ucmd.user_index;
4778         return 0;
4779 }
4780
4781 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4782                                 struct ib_wq_init_attr *init_attr,
4783                                 struct ib_udata *udata)
4784 {
4785         struct mlx5_ib_dev *dev;
4786         struct mlx5_ib_rwq *rwq;
4787         struct mlx5_ib_create_wq_resp resp = {};
4788         size_t min_resp_len;
4789         int err;
4790
4791         if (!udata)
4792                 return ERR_PTR(-ENOSYS);
4793
4794         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4795         if (udata->outlen && udata->outlen < min_resp_len)
4796                 return ERR_PTR(-EINVAL);
4797
4798         dev = to_mdev(pd->device);
4799         switch (init_attr->wq_type) {
4800         case IB_WQT_RQ:
4801                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4802                 if (!rwq)
4803                         return ERR_PTR(-ENOMEM);
4804                 err = prepare_user_rq(pd, init_attr, udata, rwq);
4805                 if (err)
4806                         goto err;
4807                 err = create_rq(rwq, pd, init_attr);
4808                 if (err)
4809                         goto err_user_rq;
4810                 break;
4811         default:
4812                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4813                             init_attr->wq_type);
4814                 return ERR_PTR(-EINVAL);
4815         }
4816
4817         rwq->ibwq.wq_num = rwq->core_qp.qpn;
4818         rwq->ibwq.state = IB_WQS_RESET;
4819         if (udata->outlen) {
4820                 resp.response_length = offsetof(typeof(resp), response_length) +
4821                                 sizeof(resp.response_length);
4822                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4823                 if (err)
4824                         goto err_copy;
4825         }
4826
4827         rwq->core_qp.event = mlx5_ib_wq_event;
4828         rwq->ibwq.event_handler = init_attr->event_handler;
4829         return &rwq->ibwq;
4830
4831 err_copy:
4832         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4833 err_user_rq:
4834         destroy_user_rq(pd, rwq);
4835 err:
4836         kfree(rwq);
4837         return ERR_PTR(err);
4838 }
4839
4840 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4841 {
4842         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4843         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4844
4845         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4846         destroy_user_rq(wq->pd, rwq);
4847         kfree(rwq);
4848
4849         return 0;
4850 }
4851
4852 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4853                                                       struct ib_rwq_ind_table_init_attr *init_attr,
4854                                                       struct ib_udata *udata)
4855 {
4856         struct mlx5_ib_dev *dev = to_mdev(device);
4857         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4858         int sz = 1 << init_attr->log_ind_tbl_size;
4859         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4860         size_t min_resp_len;
4861         int inlen;
4862         int err;
4863         int i;
4864         u32 *in;
4865         void *rqtc;
4866
4867         if (udata->inlen > 0 &&
4868             !ib_is_udata_cleared(udata, 0,
4869                                  udata->inlen))
4870                 return ERR_PTR(-EOPNOTSUPP);
4871
4872         if (init_attr->log_ind_tbl_size >
4873             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4874                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4875                             init_attr->log_ind_tbl_size,
4876                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4877                 return ERR_PTR(-EINVAL);
4878         }
4879
4880         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4881         if (udata->outlen && udata->outlen < min_resp_len)
4882                 return ERR_PTR(-EINVAL);
4883
4884         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4885         if (!rwq_ind_tbl)
4886                 return ERR_PTR(-ENOMEM);
4887
4888         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4889         in = mlx5_vzalloc(inlen);
4890         if (!in) {
4891                 err = -ENOMEM;
4892                 goto err;
4893         }
4894
4895         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4896
4897         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4898         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4899
4900         for (i = 0; i < sz; i++)
4901                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4902
4903         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4904         kvfree(in);
4905
4906         if (err)
4907                 goto err;
4908
4909         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4910         if (udata->outlen) {
4911                 resp.response_length = offsetof(typeof(resp), response_length) +
4912                                         sizeof(resp.response_length);
4913                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4914                 if (err)
4915                         goto err_copy;
4916         }
4917
4918         return &rwq_ind_tbl->ib_rwq_ind_tbl;
4919
4920 err_copy:
4921         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4922 err:
4923         kfree(rwq_ind_tbl);
4924         return ERR_PTR(err);
4925 }
4926
4927 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4928 {
4929         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4930         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4931
4932         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4933
4934         kfree(rwq_ind_tbl);
4935         return 0;
4936 }
4937
4938 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4939                       u32 wq_attr_mask, struct ib_udata *udata)
4940 {
4941         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4942         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4943         struct mlx5_ib_modify_wq ucmd = {};
4944         size_t required_cmd_sz;
4945         int curr_wq_state;
4946         int wq_state;
4947         int inlen;
4948         int err;
4949         void *rqc;
4950         void *in;
4951
4952         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4953         if (udata->inlen < required_cmd_sz)
4954                 return -EINVAL;
4955
4956         if (udata->inlen > sizeof(ucmd) &&
4957             !ib_is_udata_cleared(udata, sizeof(ucmd),
4958                                  udata->inlen - sizeof(ucmd)))
4959                 return -EOPNOTSUPP;
4960
4961         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4962                 return -EFAULT;
4963
4964         if (ucmd.comp_mask || ucmd.reserved)
4965                 return -EOPNOTSUPP;
4966
4967         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4968         in = mlx5_vzalloc(inlen);
4969         if (!in)
4970                 return -ENOMEM;
4971
4972         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4973
4974         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4975                 wq_attr->curr_wq_state : wq->state;
4976         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4977                 wq_attr->wq_state : curr_wq_state;
4978         if (curr_wq_state == IB_WQS_ERR)
4979                 curr_wq_state = MLX5_RQC_STATE_ERR;
4980         if (wq_state == IB_WQS_ERR)
4981                 wq_state = MLX5_RQC_STATE_ERR;
4982         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4983         MLX5_SET(rqc, rqc, state, wq_state);
4984
4985         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
4986         kvfree(in);
4987         if (!err)
4988                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4989
4990         return err;
4991 }