drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include "mlx5_ib.h"
  38
  39 /* not supported currently */
  40 static int wq_signature;
  41
  42 enum {
  43         MLX5_IB_ACK_REQ_FREQ    = 8,
  44 };
  45
  46 enum {
  47         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  48         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  49         MLX5_IB_LINK_TYPE_IB            = 0,
  50         MLX5_IB_LINK_TYPE_ETH           = 1
  51 };
  52
  53 enum {
  54         MLX5_IB_SQ_STRIDE       = 6,
  55 };
  56
  57 static const u32 mlx5_ib_opcode[] = {
  58         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  59         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  60         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  61         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  62         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  63         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  64         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  65         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  66         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  67         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  68         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  69         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  70         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  71         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  72 };
  73
  74 struct mlx5_wqe_eth_pad {
  75         u8 rsvd0[16];
  76 };
  77
  78 enum raw_qp_set_mask_map {
  79         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  80         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  81 };
  82
  83 struct mlx5_modify_raw_qp_param {
  84         u16 operation;
  85
  86         u32 set_mask; /* raw_qp_set_mask_map */
  87         u32 rate_limit;
  88         u8 rq_q_ctr_id;
  89 };
  90
  91 static void get_cqs(enum ib_qp_type qp_type,
  92                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  93                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
  94
  95 static int is_qp0(enum ib_qp_type qp_type)
  96 {
  97         return qp_type == IB_QPT_SMI;
  98 }
  99
 100 static int is_sqp(enum ib_qp_type qp_type)
 101 {
 102         return is_qp0(qp_type) || is_qp1(qp_type);
 103 }
 104
 105 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
 106 {
 107         return mlx5_buf_offset(&qp->buf, offset);
 108 }
 109
 110 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 111 {
 112         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 113 }
 114
 115 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 116 {
 117         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 118 }
 119
 120 /**
 121  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 122  *
 123  * @qp: QP to copy from.
 124  * @send: copy from the send queue when non-zero, use the receive queue
 125  *        otherwise.
 126  * @wqe_index:  index to start copying from. For send work queues, the
 127  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 128  *              For receive work queue, it is the number of work queue
 129  *              element in the queue.
 130  * @buffer: destination buffer.
 131  * @length: maximum number of bytes to copy.
 132  *
 133  * Copies at least a single WQE, but may copy more data.
 134  *
 135  * Return: the number of bytes copied, or an error code.
 136  */
 137 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 138                           void *buffer, u32 length,
 139                           struct mlx5_ib_qp_base *base)
 140 {
 141         struct ib_device *ibdev = qp->ibqp.device;
 142         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 143         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 144         size_t offset;
 145         size_t wq_end;
 146         struct ib_umem *umem = base->ubuffer.umem;
 147         u32 first_copy_length;
 148         int wqe_length;
 149         int ret;
 150
 151         if (wq->wqe_cnt == 0) {
 152                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 153                             qp->ibqp.qp_type);
 154                 return -EINVAL;
 155         }
 156
 157         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 158         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 159
 160         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 161                 return -EINVAL;
 162
 163         if (offset > umem->length ||
 164             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 165                 return -EINVAL;
 166
 167         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 168         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 169         if (ret)
 170                 return ret;
 171
 172         if (send) {
 173                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 174                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 175
 176                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 177         } else {
 178                 wqe_length = 1 << wq->wqe_shift;
 179         }
 180
 181         if (wqe_length <= first_copy_length)
 182                 return first_copy_length;
 183
 184         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 185                                 wqe_length - first_copy_length);
 186         if (ret)
 187                 return ret;
 188
 189         return wqe_length;
 190 }
 191
 192 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 193 {
 194         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 195         struct ib_event event;
 196
 197         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 198                 /* This event is only valid for trans_qps */
 199                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 200         }
 201
 202         if (ibqp->event_handler) {
 203                 event.device     = ibqp->device;
 204                 event.element.qp = ibqp;
 205                 switch (type) {
 206                 case MLX5_EVENT_TYPE_PATH_MIG:
 207                         event.event = IB_EVENT_PATH_MIG;
 208                         break;
 209                 case MLX5_EVENT_TYPE_COMM_EST:
 210                         event.event = IB_EVENT_COMM_EST;
 211                         break;
 212                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 213                         event.event = IB_EVENT_SQ_DRAINED;
 214                         break;
 215                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 216                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 217                         break;
 218                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 219                         event.event = IB_EVENT_QP_FATAL;
 220                         break;
 221                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 222                         event.event = IB_EVENT_PATH_MIG_ERR;
 223                         break;
 224                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 225                         event.event = IB_EVENT_QP_REQ_ERR;
 226                         break;
 227                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 228                         event.event = IB_EVENT_QP_ACCESS_ERR;
 229                         break;
 230                 default:
 231                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 232                         return;
 233                 }
 234
 235                 ibqp->event_handler(&event, ibqp->qp_context);
 236         }
 237 }
 238
 239 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 240                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 241 {
 242         int wqe_size;
 243         int wq_size;
 244
 245         /* Sanity check RQ size before proceeding */
 246         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 247                 return -EINVAL;
 248
 249         if (!has_rq) {
 250                 qp->rq.max_gs = 0;
 251                 qp->rq.wqe_cnt = 0;
 252                 qp->rq.wqe_shift = 0;
 253                 cap->max_recv_wr = 0;
 254                 cap->max_recv_sge = 0;
 255         } else {
 256                 if (ucmd) {
 257                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 258                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 259                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 260                         qp->rq.max_post = qp->rq.wqe_cnt;
 261                 } else {
 262                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 263                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 264                         wqe_size = roundup_pow_of_two(wqe_size);
 265                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 266                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 267                         qp->rq.wqe_cnt = wq_size / wqe_size;
 268                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 269                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 270                                             wqe_size,
 271                                             MLX5_CAP_GEN(dev->mdev,
 272                                                          max_wqe_sz_rq));
 273                                 return -EINVAL;
 274                         }
 275                         qp->rq.wqe_shift = ilog2(wqe_size);
 276                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 277                         qp->rq.max_post = qp->rq.wqe_cnt;
 278                 }
 279         }
 280
 281         return 0;
 282 }
 283
 284 static int sq_overhead(struct ib_qp_init_attr *attr)
 285 {
 286         int size = 0;
 287
 288         switch (attr->qp_type) {
 289         case IB_QPT_XRC_INI:
 290                 size += sizeof(struct mlx5_wqe_xrc_seg);
 291                 /* fall through */
 292         case IB_QPT_RC:
 293                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 294                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 295                             sizeof(struct mlx5_wqe_raddr_seg),
 296                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 297                             sizeof(struct mlx5_mkey_seg));
 298                 break;
 299
 300         case IB_QPT_XRC_TGT:
 301                 return 0;
 302
 303         case IB_QPT_UC:
 304                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 305                         max(sizeof(struct mlx5_wqe_raddr_seg),
 306                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 307                             sizeof(struct mlx5_mkey_seg));
 308                 break;
 309
 310         case IB_QPT_UD:
 311                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 312                         size += sizeof(struct mlx5_wqe_eth_pad) +
 313                                 sizeof(struct mlx5_wqe_eth_seg);
 314                 /* fall through */
 315         case IB_QPT_SMI:
 316         case MLX5_IB_QPT_HW_GSI:
 317                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 318                         sizeof(struct mlx5_wqe_datagram_seg);
 319                 break;
 320
 321         case MLX5_IB_QPT_REG_UMR:
 322                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 323                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 324                         sizeof(struct mlx5_mkey_seg);
 325                 break;
 326
 327         default:
 328                 return -EINVAL;
 329         }
 330
 331         return size;
 332 }
 333
 334 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 335 {
 336         int inl_size = 0;
 337         int size;
 338
 339         size = sq_overhead(attr);
 340         if (size < 0)
 341                 return size;
 342
 343         if (attr->cap.max_inline_data) {
 344                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 345                         attr->cap.max_inline_data;
 346         }
 347
 348         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 349         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 350             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 351                         return MLX5_SIG_WQE_SIZE;
 352         else
 353                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 354 }
 355
 356 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 357 {
 358         int max_sge;
 359
 360         if (attr->qp_type == IB_QPT_RC)
 361                 max_sge = (min_t(int, wqe_size, 512) -
 362                            sizeof(struct mlx5_wqe_ctrl_seg) -
 363                            sizeof(struct mlx5_wqe_raddr_seg)) /
 364                         sizeof(struct mlx5_wqe_data_seg);
 365         else if (attr->qp_type == IB_QPT_XRC_INI)
 366                 max_sge = (min_t(int, wqe_size, 512) -
 367                            sizeof(struct mlx5_wqe_ctrl_seg) -
 368                            sizeof(struct mlx5_wqe_xrc_seg) -
 369                            sizeof(struct mlx5_wqe_raddr_seg)) /
 370                         sizeof(struct mlx5_wqe_data_seg);
 371         else
 372                 max_sge = (wqe_size - sq_overhead(attr)) /
 373                         sizeof(struct mlx5_wqe_data_seg);
 374
 375         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 376                      sizeof(struct mlx5_wqe_data_seg));
 377 }
 378
 379 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 380                         struct mlx5_ib_qp *qp)
 381 {
 382         int wqe_size;
 383         int wq_size;
 384
 385         if (!attr->cap.max_send_wr)
 386                 return 0;
 387
 388         wqe_size = calc_send_wqe(attr);
 389         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 390         if (wqe_size < 0)
 391                 return wqe_size;
 392
 393         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 394                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 395                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 396                 return -EINVAL;
 397         }
 398
 399         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 400                               sizeof(struct mlx5_wqe_inline_seg);
 401         attr->cap.max_inline_data = qp->max_inline_data;
 402
 403         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 404                 qp->signature_en = true;
 405
 406         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 407         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 408         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 409                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 410                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 411                             qp->sq.wqe_cnt,
 412                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 413                 return -ENOMEM;
 414         }
 415         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 416         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 417         if (qp->sq.max_gs < attr->cap.max_send_sge)
 418                 return -ENOMEM;
 419
 420         attr->cap.max_send_sge = qp->sq.max_gs;
 421         qp->sq.max_post = wq_size / wqe_size;
 422         attr->cap.max_send_wr = qp->sq.max_post;
 423
 424         return wq_size;
 425 }
 426
 427 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 428                             struct mlx5_ib_qp *qp,
 429                             struct mlx5_ib_create_qp *ucmd,
 430                             struct mlx5_ib_qp_base *base,
 431                             struct ib_qp_init_attr *attr)
 432 {
 433         int desc_sz = 1 << qp->sq.wqe_shift;
 434
 435         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 436                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 437                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 438                 return -EINVAL;
 439         }
 440
 441         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 442                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 443                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 444                 return -EINVAL;
 445         }
 446
 447         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 448
 449         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 450                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 451                              qp->sq.wqe_cnt,
 452                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 453                 return -EINVAL;
 454         }
 455
 456         if (attr->qp_type == IB_QPT_RAW_PACKET) {
 457                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 458                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 459         } else {
 460                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 461                                          (qp->sq.wqe_cnt << 6);
 462         }
 463
 464         return 0;
 465 }
 466
 467 static int qp_has_rq(struct ib_qp_init_attr *attr)
 468 {
 469         if (attr->qp_type == IB_QPT_XRC_INI ||
 470             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 471             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 472             !attr->cap.max_recv_wr)
 473                 return 0;
 474
 475         return 1;
 476 }
 477
 478 static int first_med_bfreg(void)
 479 {
 480         return 1;
 481 }
 482
 483 enum {
 484         /* this is the first blue flame register in the array of bfregs assigned
 485          * to a processes. Since we do not use it for blue flame but rather
 486          * regular 64 bit doorbells, we do not need a lock for maintaiing
 487          * "odd/even" order
 488          */
 489         NUM_NON_BLUE_FLAME_BFREGS = 1,
 490 };
 491
 492 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 493 {
 494         return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 495 }
 496
 497 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 498                          struct mlx5_bfreg_info *bfregi)
 499 {
 500         int n;
 501
 502         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 503             NUM_NON_BLUE_FLAME_BFREGS;
 504
 505         return n >= 0 ? n : 0;
 506 }
 507
 508 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 509                           struct mlx5_bfreg_info *bfregi)
 510 {
 511         int med;
 512
 513         med = num_med_bfreg(dev, bfregi);
 514         return ++med;
 515 }
 516
 517 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 518                                   struct mlx5_bfreg_info *bfregi)
 519 {
 520         int i;
 521
 522         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 523                 if (!bfregi->count[i]) {
 524                         bfregi->count[i]++;
 525                         return i;
 526                 }
 527         }
 528
 529         return -ENOMEM;
 530 }
 531
 532 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 533                                  struct mlx5_bfreg_info *bfregi)
 534 {
 535         int minidx = first_med_bfreg();
 536         int i;
 537
 538         for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
 539                 if (bfregi->count[i] < bfregi->count[minidx])
 540                         minidx = i;
 541                 if (!bfregi->count[minidx])
 542                         break;
 543         }
 544
 545         bfregi->count[minidx]++;
 546         return minidx;
 547 }
 548
 549 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 550                        struct mlx5_bfreg_info *bfregi,
 551                        enum mlx5_ib_latency_class lat)
 552 {
 553         int bfregn = -EINVAL;
 554
 555         mutex_lock(&bfregi->lock);
 556         switch (lat) {
 557         case MLX5_IB_LATENCY_CLASS_LOW:
 558                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 559                 bfregn = 0;
 560                 bfregi->count[bfregn]++;
 561                 break;
 562
 563         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 564                 if (bfregi->ver < 2)
 565                         bfregn = -ENOMEM;
 566                 else
 567                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 568                 break;
 569
 570         case MLX5_IB_LATENCY_CLASS_HIGH:
 571                 if (bfregi->ver < 2)
 572                         bfregn = -ENOMEM;
 573                 else
 574                         bfregn = alloc_high_class_bfreg(dev, bfregi);
 575                 break;
 576         }
 577         mutex_unlock(&bfregi->lock);
 578
 579         return bfregn;
 580 }
 581
 582 static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 583 {
 584         mutex_lock(&bfregi->lock);
 585         bfregi->count[bfregn]--;
 586         mutex_unlock(&bfregi->lock);
 587 }
 588
 589 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 590 {
 591         switch (state) {
 592         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 593         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 594         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 595         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 596         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 597         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 598         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 599         default:                return -1;
 600         }
 601 }
 602
 603 static int to_mlx5_st(enum ib_qp_type type)
 604 {
 605         switch (type) {
 606         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 607         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 608         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 609         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 610         case IB_QPT_XRC_INI:
 611         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 612         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 613         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 614         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 615         case IB_QPT_RAW_PACKET:
 616         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 617         case IB_QPT_MAX:
 618         default:                return -EINVAL;
 619         }
 620 }
 621
 622 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 623                              struct mlx5_ib_cq *recv_cq);
 624 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 625                                struct mlx5_ib_cq *recv_cq);
 626
 627 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 628                                struct mlx5_bfreg_info *bfregi, int bfregn)
 629 {
 630         int bfregs_per_sys_page;
 631         int index_of_sys_page;
 632         int offset;
 633
 634         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 635                                 MLX5_NON_FP_BFREGS_PER_UAR;
 636         index_of_sys_page = bfregn / bfregs_per_sys_page;
 637
 638         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 639
 640         return bfregi->sys_pages[index_of_sys_page] + offset;
 641 }
 642
 643 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 644                             struct ib_pd *pd,
 645                             unsigned long addr, size_t size,
 646                             struct ib_umem **umem,
 647                             int *npages, int *page_shift, int *ncont,
 648                             u32 *offset)
 649 {
 650         int err;
 651
 652         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 653         if (IS_ERR(*umem)) {
 654                 mlx5_ib_dbg(dev, "umem_get failed\n");
 655                 return PTR_ERR(*umem);
 656         }
 657
 658         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 659
 660         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 661         if (err) {
 662                 mlx5_ib_warn(dev, "bad offset\n");
 663                 goto err_umem;
 664         }
 665
 666         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 667                     addr, size, *npages, *page_shift, *ncont, *offset);
 668
 669         return 0;
 670
 671 err_umem:
 672         ib_umem_release(*umem);
 673         *umem = NULL;
 674
 675         return err;
 676 }
 677
 678 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
 679 {
 680         struct mlx5_ib_ucontext *context;
 681
 682         context = to_mucontext(pd->uobject->context);
 683         mlx5_ib_db_unmap_user(context, &rwq->db);
 684         if (rwq->umem)
 685                 ib_umem_release(rwq->umem);
 686 }
 687
 688 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 689                           struct mlx5_ib_rwq *rwq,
 690                           struct mlx5_ib_create_wq *ucmd)
 691 {
 692         struct mlx5_ib_ucontext *context;
 693         int page_shift = 0;
 694         int npages;
 695         u32 offset = 0;
 696         int ncont = 0;
 697         int err;
 698
 699         if (!ucmd->buf_addr)
 700                 return -EINVAL;
 701
 702         context = to_mucontext(pd->uobject->context);
 703         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 704                                rwq->buf_size, 0, 0);
 705         if (IS_ERR(rwq->umem)) {
 706                 mlx5_ib_dbg(dev, "umem_get failed\n");
 707                 err = PTR_ERR(rwq->umem);
 708                 return err;
 709         }
 710
 711         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 712                            &ncont, NULL);
 713         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 714                                      &rwq->rq_page_offset);
 715         if (err) {
 716                 mlx5_ib_warn(dev, "bad offset\n");
 717                 goto err_umem;
 718         }
 719
 720         rwq->rq_num_pas = ncont;
 721         rwq->page_shift = page_shift;
 722         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 723         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 724
 725         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 726                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 727                     npages, page_shift, ncont, offset);
 728
 729         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 730         if (err) {
 731                 mlx5_ib_dbg(dev, "map failed\n");
 732                 goto err_umem;
 733         }
 734
 735         rwq->create_type = MLX5_WQ_USER;
 736         return 0;
 737
 738 err_umem:
 739         ib_umem_release(rwq->umem);
 740         return err;
 741 }
 742
 743 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 744                          struct mlx5_bfreg_info *bfregi, int bfregn)
 745 {
 746         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 747                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 748 }
 749
 750 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 751                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 752                           struct ib_qp_init_attr *attr,
 753                           u32 **in,
 754                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 755                           struct mlx5_ib_qp_base *base)
 756 {
 757         struct mlx5_ib_ucontext *context;
 758         struct mlx5_ib_create_qp ucmd;
 759         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 760         int page_shift = 0;
 761         int uar_index;
 762         int npages;
 763         u32 offset = 0;
 764         int bfregn;
 765         int ncont = 0;
 766         __be64 *pas;
 767         void *qpc;
 768         int err;
 769
 770         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 771         if (err) {
 772                 mlx5_ib_dbg(dev, "copy failed\n");
 773                 return err;
 774         }
 775
 776         context = to_mucontext(pd->uobject->context);
 777         /*
 778          * TBD: should come from the verbs when we have the API
 779          */
 780         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
 781                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 782                 bfregn = MLX5_CROSS_CHANNEL_BFREG;
 783         else {
 784                 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
 785                 if (bfregn < 0) {
 786                         mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
 787                         mlx5_ib_dbg(dev, "reverting to medium latency\n");
 788                         bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
 789                         if (bfregn < 0) {
 790                                 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
 791                                 mlx5_ib_dbg(dev, "reverting to high latency\n");
 792                                 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
 793                                 if (bfregn < 0) {
 794                                         mlx5_ib_warn(dev, "bfreg allocation failed\n");
 795                                         return bfregn;
 796                                 }
 797                         }
 798                 }
 799         }
 800
 801         uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn);
 802         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 803
 804         qp->rq.offset = 0;
 805         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 806         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 807
 808         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 809         if (err)
 810                 goto err_bfreg;
 811
 812         if (ucmd.buf_addr && ubuffer->buf_size) {
 813                 ubuffer->buf_addr = ucmd.buf_addr;
 814                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 815                                        ubuffer->buf_size,
 816                                        &ubuffer->umem, &npages, &page_shift,
 817                                        &ncont, &offset);
 818                 if (err)
 819                         goto err_bfreg;
 820         } else {
 821                 ubuffer->umem = NULL;
 822         }
 823
 824         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 825                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 826         *in = mlx5_vzalloc(*inlen);
 827         if (!*in) {
 828                 err = -ENOMEM;
 829                 goto err_umem;
 830         }
 831
 832         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 833         if (ubuffer->umem)
 834                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 835
 836         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 837
 838         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 839         MLX5_SET(qpc, qpc, page_offset, offset);
 840
 841         MLX5_SET(qpc, qpc, uar_page, uar_index);
 842         resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
 843         qp->bfregn = bfregn;
 844
 845         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 846         if (err) {
 847                 mlx5_ib_dbg(dev, "map failed\n");
 848                 goto err_free;
 849         }
 850
 851         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 852         if (err) {
 853                 mlx5_ib_dbg(dev, "copy failed\n");
 854                 goto err_unmap;
 855         }
 856         qp->create_type = MLX5_QP_USER;
 857
 858         return 0;
 859
 860 err_unmap:
 861         mlx5_ib_db_unmap_user(context, &qp->db);
 862
 863 err_free:
 864         kvfree(*in);
 865
 866 err_umem:
 867         if (ubuffer->umem)
 868                 ib_umem_release(ubuffer->umem);
 869
 870 err_bfreg:
 871         free_bfreg(dev, &context->bfregi, bfregn);
 872         return err;
 873 }
 874
 875 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 876                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
 877 {
 878         struct mlx5_ib_ucontext *context;
 879
 880         context = to_mucontext(pd->uobject->context);
 881         mlx5_ib_db_unmap_user(context, &qp->db);
 882         if (base->ubuffer.umem)
 883                 ib_umem_release(base->ubuffer.umem);
 884         free_bfreg(dev, &context->bfregi, qp->bfregn);
 885 }
 886
 887 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 888                             struct ib_qp_init_attr *init_attr,
 889                             struct mlx5_ib_qp *qp,
 890                             u32 **in, int *inlen,
 891                             struct mlx5_ib_qp_base *base)
 892 {
 893         int uar_index;
 894         void *qpc;
 895         int err;
 896
 897         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 898                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 899                                         IB_QP_CREATE_IPOIB_UD_LSO |
 900                                         IB_QP_CREATE_NETIF_QP |
 901                                         mlx5_ib_create_qp_sqpn_qp1()))
 902                 return -EINVAL;
 903
 904         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 905                 qp->bf.bfreg = &dev->fp_bfreg;
 906         else
 907                 qp->bf.bfreg = &dev->bfreg;
 908
 909         /* We need to divide by two since each register is comprised of
 910          * two buffers of identical size, namely odd and even
 911          */
 912         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
 913         uar_index = qp->bf.bfreg->index;
 914
 915         err = calc_sq_size(dev, init_attr, qp);
 916         if (err < 0) {
 917                 mlx5_ib_dbg(dev, "err %d\n", err);
 918                 return err;
 919         }
 920
 921         qp->rq.offset = 0;
 922         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 923         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 924
 925         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
 926         if (err) {
 927                 mlx5_ib_dbg(dev, "err %d\n", err);
 928                 return err;
 929         }
 930
 931         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 932         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 933                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
 934         *in = mlx5_vzalloc(*inlen);
 935         if (!*in) {
 936                 err = -ENOMEM;
 937                 goto err_buf;
 938         }
 939
 940         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 941         MLX5_SET(qpc, qpc, uar_page, uar_index);
 942         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 943
 944         /* Set "fast registration enabled" for all kernel QPs */
 945         MLX5_SET(qpc, qpc, fre, 1);
 946         MLX5_SET(qpc, qpc, rlky, 1);
 947
 948         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
 949                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
 950                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
 951         }
 952
 953         mlx5_fill_page_array(&qp->buf,
 954                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
 955
 956         err = mlx5_db_alloc(dev->mdev, &qp->db);
 957         if (err) {
 958                 mlx5_ib_dbg(dev, "err %d\n", err);
 959                 goto err_free;
 960         }
 961
 962         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
 963         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
 964         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
 965         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
 966         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 967
 968         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 969             !qp->sq.w_list || !qp->sq.wqe_head) {
 970                 err = -ENOMEM;
 971                 goto err_wrid;
 972         }
 973         qp->create_type = MLX5_QP_KERNEL;
 974
 975         return 0;
 976
 977 err_wrid:
 978         kfree(qp->sq.wqe_head);
 979         kfree(qp->sq.w_list);
 980         kfree(qp->sq.wrid);
 981         kfree(qp->sq.wr_data);
 982         kfree(qp->rq.wrid);
 983         mlx5_db_free(dev->mdev, &qp->db);
 984
 985 err_free:
 986         kvfree(*in);
 987
 988 err_buf:
 989         mlx5_buf_free(dev->mdev, &qp->buf);
 990         return err;
 991 }
 992
 993 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
 994 {
 995         kfree(qp->sq.wqe_head);
 996         kfree(qp->sq.w_list);
 997         kfree(qp->sq.wrid);
 998         kfree(qp->sq.wr_data);
 999         kfree(qp->rq.wrid);
1000         mlx5_db_free(dev->mdev, &qp->db);
1001         mlx5_buf_free(dev->mdev, &qp->buf);
1002 }
1003
1004 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1005 {
1006         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1007             (attr->qp_type == IB_QPT_XRC_INI))
1008                 return MLX5_SRQ_RQ;
1009         else if (!qp->has_rq)
1010                 return MLX5_ZERO_LEN_RQ;
1011         else
1012                 return MLX5_NON_ZERO_RQ;
1013 }
1014
1015 static int is_connected(enum ib_qp_type qp_type)
1016 {
1017         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1018                 return 1;
1019
1020         return 0;
1021 }
1022
1023 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1024                                     struct mlx5_ib_sq *sq, u32 tdn)
1025 {
1026         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1027         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1028
1029         MLX5_SET(tisc, tisc, transport_domain, tdn);
1030         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1031 }
1032
1033 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1034                                       struct mlx5_ib_sq *sq)
1035 {
1036         mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1037 }
1038
1039 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1040                                    struct mlx5_ib_sq *sq, void *qpin,
1041                                    struct ib_pd *pd)
1042 {
1043         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1044         __be64 *pas;
1045         void *in;
1046         void *sqc;
1047         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1048         void *wq;
1049         int inlen;
1050         int err;
1051         int page_shift = 0;
1052         int npages;
1053         int ncont = 0;
1054         u32 offset = 0;
1055
1056         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1057                                &sq->ubuffer.umem, &npages, &page_shift,
1058                                &ncont, &offset);
1059         if (err)
1060                 return err;
1061
1062         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1063         in = mlx5_vzalloc(inlen);
1064         if (!in) {
1065                 err = -ENOMEM;
1066                 goto err_umem;
1067         }
1068
1069         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1070         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1071         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1072         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1073         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1074         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1075         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1076
1077         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1078         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1079         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1080         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1081         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1082         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1083         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1084         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1085         MLX5_SET(wq, wq, page_offset, offset);
1086
1087         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1088         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1089
1090         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1091
1092         kvfree(in);
1093
1094         if (err)
1095                 goto err_umem;
1096
1097         return 0;
1098
1099 err_umem:
1100         ib_umem_release(sq->ubuffer.umem);
1101         sq->ubuffer.umem = NULL;
1102
1103         return err;
1104 }
1105
1106 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1107                                      struct mlx5_ib_sq *sq)
1108 {
1109         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1110         ib_umem_release(sq->ubuffer.umem);
1111 }
1112
1113 static int get_rq_pas_size(void *qpc)
1114 {
1115         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1116         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1117         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1118         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1119         u32 po_quanta     = 1 << (log_page_size - 6);
1120         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1121         u32 page_size     = 1 << log_page_size;
1122         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1123         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1124
1125         return rq_num_pas * sizeof(u64);
1126 }
1127
1128 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1129                                    struct mlx5_ib_rq *rq, void *qpin)
1130 {
1131         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1132         __be64 *pas;
1133         __be64 *qp_pas;
1134         void *in;
1135         void *rqc;
1136         void *wq;
1137         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1138         int inlen;
1139         int err;
1140         u32 rq_pas_size = get_rq_pas_size(qpc);
1141
1142         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1143         in = mlx5_vzalloc(inlen);
1144         if (!in)
1145                 return -ENOMEM;
1146
1147         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1148         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1149                 MLX5_SET(rqc, rqc, vsd, 1);
1150         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1151         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1152         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1153         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1154         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1155
1156         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1157                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1158
1159         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1160         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1161         MLX5_SET(wq, wq, end_padding_mode,
1162                  MLX5_GET(qpc, qpc, end_padding_mode));
1163         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1164         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1165         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1166         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1167         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1168         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1169
1170         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1171         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1172         memcpy(pas, qp_pas, rq_pas_size);
1173
1174         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1175
1176         kvfree(in);
1177
1178         return err;
1179 }
1180
1181 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1182                                      struct mlx5_ib_rq *rq)
1183 {
1184         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1185 }
1186
1187 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1188                                     struct mlx5_ib_rq *rq, u32 tdn)
1189 {
1190         u32 *in;
1191         void *tirc;
1192         int inlen;
1193         int err;
1194
1195         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1196         in = mlx5_vzalloc(inlen);
1197         if (!in)
1198                 return -ENOMEM;
1199
1200         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1201         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1202         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1203         MLX5_SET(tirc, tirc, transport_domain, tdn);
1204
1205         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1206
1207         kvfree(in);
1208
1209         return err;
1210 }
1211
1212 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1213                                       struct mlx5_ib_rq *rq)
1214 {
1215         mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1216 }
1217
1218 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1219                                 u32 *in,
1220                                 struct ib_pd *pd)
1221 {
1222         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1223         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1224         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1225         struct ib_uobject *uobj = pd->uobject;
1226         struct ib_ucontext *ucontext = uobj->context;
1227         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1228         int err;
1229         u32 tdn = mucontext->tdn;
1230
1231         if (qp->sq.wqe_cnt) {
1232                 err = create_raw_packet_qp_tis(dev, sq, tdn);
1233                 if (err)
1234                         return err;
1235
1236                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1237                 if (err)
1238                         goto err_destroy_tis;
1239
1240                 sq->base.container_mibqp = qp;
1241         }
1242
1243         if (qp->rq.wqe_cnt) {
1244                 rq->base.container_mibqp = qp;
1245
1246                 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1247                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1248                 err = create_raw_packet_qp_rq(dev, rq, in);
1249                 if (err)
1250                         goto err_destroy_sq;
1251
1252
1253                 err = create_raw_packet_qp_tir(dev, rq, tdn);
1254                 if (err)
1255                         goto err_destroy_rq;
1256         }
1257
1258         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1259                                                      rq->base.mqp.qpn;
1260
1261         return 0;
1262
1263 err_destroy_rq:
1264         destroy_raw_packet_qp_rq(dev, rq);
1265 err_destroy_sq:
1266         if (!qp->sq.wqe_cnt)
1267                 return err;
1268         destroy_raw_packet_qp_sq(dev, sq);
1269 err_destroy_tis:
1270         destroy_raw_packet_qp_tis(dev, sq);
1271
1272         return err;
1273 }
1274
1275 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1276                                   struct mlx5_ib_qp *qp)
1277 {
1278         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1279         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1280         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1281
1282         if (qp->rq.wqe_cnt) {
1283                 destroy_raw_packet_qp_tir(dev, rq);
1284                 destroy_raw_packet_qp_rq(dev, rq);
1285         }
1286
1287         if (qp->sq.wqe_cnt) {
1288                 destroy_raw_packet_qp_sq(dev, sq);
1289                 destroy_raw_packet_qp_tis(dev, sq);
1290         }
1291 }
1292
1293 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1294                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1295 {
1296         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1297         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1298
1299         sq->sq = &qp->sq;
1300         rq->rq = &qp->rq;
1301         sq->doorbell = &qp->db;
1302         rq->doorbell = &qp->db;
1303 }
1304
1305 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1306 {
1307         mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1308 }
1309
1310 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1311                                  struct ib_pd *pd,
1312                                  struct ib_qp_init_attr *init_attr,
1313                                  struct ib_udata *udata)
1314 {
1315         struct ib_uobject *uobj = pd->uobject;
1316         struct ib_ucontext *ucontext = uobj->context;
1317         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1318         struct mlx5_ib_create_qp_resp resp = {};
1319         int inlen;
1320         int err;
1321         u32 *in;
1322         void *tirc;
1323         void *hfso;
1324         u32 selected_fields = 0;
1325         size_t min_resp_len;
1326         u32 tdn = mucontext->tdn;
1327         struct mlx5_ib_create_qp_rss ucmd = {};
1328         size_t required_cmd_sz;
1329
1330         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1331                 return -EOPNOTSUPP;
1332
1333         if (init_attr->create_flags || init_attr->send_cq)
1334                 return -EINVAL;
1335
1336         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1337         if (udata->outlen < min_resp_len)
1338                 return -EINVAL;
1339
1340         required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1341         if (udata->inlen < required_cmd_sz) {
1342                 mlx5_ib_dbg(dev, "invalid inlen\n");
1343                 return -EINVAL;
1344         }
1345
1346         if (udata->inlen > sizeof(ucmd) &&
1347             !ib_is_udata_cleared(udata, sizeof(ucmd),
1348                                  udata->inlen - sizeof(ucmd))) {
1349                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1350                 return -EOPNOTSUPP;
1351         }
1352
1353         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1354                 mlx5_ib_dbg(dev, "copy failed\n");
1355                 return -EFAULT;
1356         }
1357
1358         if (ucmd.comp_mask) {
1359                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1360                 return -EOPNOTSUPP;
1361         }
1362
1363         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1364                 mlx5_ib_dbg(dev, "invalid reserved\n");
1365                 return -EOPNOTSUPP;
1366         }
1367
1368         err = ib_copy_to_udata(udata, &resp, min_resp_len);
1369         if (err) {
1370                 mlx5_ib_dbg(dev, "copy failed\n");
1371                 return -EINVAL;
1372         }
1373
1374         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1375         in = mlx5_vzalloc(inlen);
1376         if (!in)
1377                 return -ENOMEM;
1378
1379         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1380         MLX5_SET(tirc, tirc, disp_type,
1381                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1382         MLX5_SET(tirc, tirc, indirect_table,
1383                  init_attr->rwq_ind_tbl->ind_tbl_num);
1384         MLX5_SET(tirc, tirc, transport_domain, tdn);
1385
1386         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1387         switch (ucmd.rx_hash_function) {
1388         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1389         {
1390                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1391                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1392
1393                 if (len != ucmd.rx_key_len) {
1394                         err = -EINVAL;
1395                         goto err;
1396                 }
1397
1398                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1399                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1400                 memcpy(rss_key, ucmd.rx_hash_key, len);
1401                 break;
1402         }
1403         default:
1404                 err = -EOPNOTSUPP;
1405                 goto err;
1406         }
1407
1408         if (!ucmd.rx_hash_fields_mask) {
1409                 /* special case when this TIR serves as steering entry without hashing */
1410                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1411                         goto create_tir;
1412                 err = -EINVAL;
1413                 goto err;
1414         }
1415
1416         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1417              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1418              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1419              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1420                 err = -EINVAL;
1421                 goto err;
1422         }
1423
1424         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1425         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1426             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1427                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1428                          MLX5_L3_PROT_TYPE_IPV4);
1429         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1430                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1431                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1432                          MLX5_L3_PROT_TYPE_IPV6);
1433
1434         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1435              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1436              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1437              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1438                 err = -EINVAL;
1439                 goto err;
1440         }
1441
1442         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1443         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1444             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1445                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1446                          MLX5_L4_PROT_TYPE_TCP);
1447         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1448                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1449                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1450                          MLX5_L4_PROT_TYPE_UDP);
1451
1452         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1453             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1454                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1455
1456         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1457             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1458                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1459
1460         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1461             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1462                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1463
1464         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1465             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1466                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1467
1468         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1469
1470 create_tir:
1471         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1472
1473         if (err)
1474                 goto err;
1475
1476         kvfree(in);
1477         /* qpn is reserved for that QP */
1478         qp->trans_qp.base.mqp.qpn = 0;
1479         qp->flags |= MLX5_IB_QP_RSS;
1480         return 0;
1481
1482 err:
1483         kvfree(in);
1484         return err;
1485 }
1486
1487 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1488                             struct ib_qp_init_attr *init_attr,
1489                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1490 {
1491         struct mlx5_ib_resources *devr = &dev->devr;
1492         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1493         struct mlx5_core_dev *mdev = dev->mdev;
1494         struct mlx5_ib_create_qp_resp resp;
1495         struct mlx5_ib_cq *send_cq;
1496         struct mlx5_ib_cq *recv_cq;
1497         unsigned long flags;
1498         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1499         struct mlx5_ib_create_qp ucmd;
1500         struct mlx5_ib_qp_base *base;
1501         void *qpc;
1502         u32 *in;
1503         int err;
1504
1505         base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1506                &qp->raw_packet_qp.rq.base :
1507                &qp->trans_qp.base;
1508
1509         mutex_init(&qp->mutex);
1510         spin_lock_init(&qp->sq.lock);
1511         spin_lock_init(&qp->rq.lock);
1512
1513         if (init_attr->rwq_ind_tbl) {
1514                 if (!udata)
1515                         return -ENOSYS;
1516
1517                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1518                 return err;
1519         }
1520
1521         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1522                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1523                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1524                         return -EINVAL;
1525                 } else {
1526                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1527                 }
1528         }
1529
1530         if (init_attr->create_flags &
1531                         (IB_QP_CREATE_CROSS_CHANNEL |
1532                          IB_QP_CREATE_MANAGED_SEND |
1533                          IB_QP_CREATE_MANAGED_RECV)) {
1534                 if (!MLX5_CAP_GEN(mdev, cd)) {
1535                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1536                         return -EINVAL;
1537                 }
1538                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1539                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1540                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1541                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1542                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1543                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1544         }
1545
1546         if (init_attr->qp_type == IB_QPT_UD &&
1547             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1548                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1549                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1550                         return -EOPNOTSUPP;
1551                 }
1552
1553         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1554                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1555                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1556                         return -EOPNOTSUPP;
1557                 }
1558                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1559                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1560                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1561                         return -EOPNOTSUPP;
1562                 }
1563                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1564         }
1565
1566         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1567                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1568
1569         if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1570                 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1571                       MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1572                     (init_attr->qp_type != IB_QPT_RAW_PACKET))
1573                         return -EOPNOTSUPP;
1574                 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1575         }
1576
1577         if (pd && pd->uobject) {
1578                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1579                         mlx5_ib_dbg(dev, "copy failed\n");
1580                         return -EFAULT;
1581                 }
1582
1583                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1584                                         &ucmd, udata->inlen, &uidx);
1585                 if (err)
1586                         return err;
1587
1588                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1589                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1590         } else {
1591                 qp->wq_sig = !!wq_signature;
1592         }
1593
1594         qp->has_rq = qp_has_rq(init_attr);
1595         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1596                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1597         if (err) {
1598                 mlx5_ib_dbg(dev, "err %d\n", err);
1599                 return err;
1600         }
1601
1602         if (pd) {
1603                 if (pd->uobject) {
1604                         __u32 max_wqes =
1605                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1606                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1607                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1608                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1609                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1610                                 return -EINVAL;
1611                         }
1612                         if (ucmd.sq_wqe_count > max_wqes) {
1613                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1614                                             ucmd.sq_wqe_count, max_wqes);
1615                                 return -EINVAL;
1616                         }
1617                         if (init_attr->create_flags &
1618                             mlx5_ib_create_qp_sqpn_qp1()) {
1619                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1620                                 return -EINVAL;
1621                         }
1622                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1623                                              &resp, &inlen, base);
1624                         if (err)
1625                                 mlx5_ib_dbg(dev, "err %d\n", err);
1626                 } else {
1627                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1628                                                base);
1629                         if (err)
1630                                 mlx5_ib_dbg(dev, "err %d\n", err);
1631                 }
1632
1633                 if (err)
1634                         return err;
1635         } else {
1636                 in = mlx5_vzalloc(inlen);
1637                 if (!in)
1638                         return -ENOMEM;
1639
1640                 qp->create_type = MLX5_QP_EMPTY;
1641         }
1642
1643         if (is_sqp(init_attr->qp_type))
1644                 qp->port = init_attr->port_num;
1645
1646         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1647
1648         MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1649         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1650
1651         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1652                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1653         else
1654                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1655
1656
1657         if (qp->wq_sig)
1658                 MLX5_SET(qpc, qpc, wq_signature, 1);
1659
1660         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1661                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1662
1663         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1664                 MLX5_SET(qpc, qpc, cd_master, 1);
1665         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1666                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1667         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1668                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1669
1670         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1671                 int rcqe_sz;
1672                 int scqe_sz;
1673
1674                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1675                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1676
1677                 if (rcqe_sz == 128)
1678                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1679                 else
1680                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1681
1682                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1683                         if (scqe_sz == 128)
1684                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1685                         else
1686                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1687                 }
1688         }
1689
1690         if (qp->rq.wqe_cnt) {
1691                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1692                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1693         }
1694
1695         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1696
1697         if (qp->sq.wqe_cnt)
1698                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1699         else
1700                 MLX5_SET(qpc, qpc, no_sq, 1);
1701
1702         /* Set default resources */
1703         switch (init_attr->qp_type) {
1704         case IB_QPT_XRC_TGT:
1705                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1706                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1707                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1708                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1709                 break;
1710         case IB_QPT_XRC_INI:
1711                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1712                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1713                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1714                 break;
1715         default:
1716                 if (init_attr->srq) {
1717                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1718                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1719                 } else {
1720                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1721                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1722                 }
1723         }
1724
1725         if (init_attr->send_cq)
1726                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1727
1728         if (init_attr->recv_cq)
1729                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1730
1731         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1732
1733         /* 0xffffff means we ask to work with cqe version 0 */
1734         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1735                 MLX5_SET(qpc, qpc, user_index, uidx);
1736
1737         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1738         if (init_attr->qp_type == IB_QPT_UD &&
1739             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1740                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1741                 qp->flags |= MLX5_IB_QP_LSO;
1742         }
1743
1744         if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1745                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1746                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1747                 err = create_raw_packet_qp(dev, qp, in, pd);
1748         } else {
1749                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1750         }
1751
1752         if (err) {
1753                 mlx5_ib_dbg(dev, "create qp failed\n");
1754                 goto err_create;
1755         }
1756
1757         kvfree(in);
1758
1759         base->container_mibqp = qp;
1760         base->mqp.event = mlx5_ib_qp_event;
1761
1762         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1763                 &send_cq, &recv_cq);
1764         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1765         mlx5_ib_lock_cqs(send_cq, recv_cq);
1766         /* Maintain device to QPs access, needed for further handling via reset
1767          * flow
1768          */
1769         list_add_tail(&qp->qps_list, &dev->qp_list);
1770         /* Maintain CQ to QPs access, needed for further handling via reset flow
1771          */
1772         if (send_cq)
1773                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1774         if (recv_cq)
1775                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1776         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1777         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1778
1779         return 0;
1780
1781 err_create:
1782         if (qp->create_type == MLX5_QP_USER)
1783                 destroy_qp_user(dev, pd, qp, base);
1784         else if (qp->create_type == MLX5_QP_KERNEL)
1785                 destroy_qp_kernel(dev, qp);
1786
1787         kvfree(in);
1788         return err;
1789 }
1790
1791 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1792         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1793 {
1794         if (send_cq) {
1795                 if (recv_cq) {
1796                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1797                                 spin_lock(&send_cq->lock);
1798                                 spin_lock_nested(&recv_cq->lock,
1799                                                  SINGLE_DEPTH_NESTING);
1800                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1801                                 spin_lock(&send_cq->lock);
1802                                 __acquire(&recv_cq->lock);
1803                         } else {
1804                                 spin_lock(&recv_cq->lock);
1805                                 spin_lock_nested(&send_cq->lock,
1806                                                  SINGLE_DEPTH_NESTING);
1807                         }
1808                 } else {
1809                         spin_lock(&send_cq->lock);
1810                         __acquire(&recv_cq->lock);
1811                 }
1812         } else if (recv_cq) {
1813                 spin_lock(&recv_cq->lock);
1814                 __acquire(&send_cq->lock);
1815         } else {
1816                 __acquire(&send_cq->lock);
1817                 __acquire(&recv_cq->lock);
1818         }
1819 }
1820
1821 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1822         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1823 {
1824         if (send_cq) {
1825                 if (recv_cq) {
1826                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1827                                 spin_unlock(&recv_cq->lock);
1828                                 spin_unlock(&send_cq->lock);
1829                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1830                                 __release(&recv_cq->lock);
1831                                 spin_unlock(&send_cq->lock);
1832                         } else {
1833                                 spin_unlock(&send_cq->lock);
1834                                 spin_unlock(&recv_cq->lock);
1835                         }
1836                 } else {
1837                         __release(&recv_cq->lock);
1838                         spin_unlock(&send_cq->lock);
1839                 }
1840         } else if (recv_cq) {
1841                 __release(&send_cq->lock);
1842                 spin_unlock(&recv_cq->lock);
1843         } else {
1844                 __release(&recv_cq->lock);
1845                 __release(&send_cq->lock);
1846         }
1847 }
1848
1849 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1850 {
1851         return to_mpd(qp->ibqp.pd);
1852 }
1853
1854 static void get_cqs(enum ib_qp_type qp_type,
1855                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1856                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1857 {
1858         switch (qp_type) {
1859         case IB_QPT_XRC_TGT:
1860                 *send_cq = NULL;
1861                 *recv_cq = NULL;
1862                 break;
1863         case MLX5_IB_QPT_REG_UMR:
1864         case IB_QPT_XRC_INI:
1865                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1866                 *recv_cq = NULL;
1867                 break;
1868
1869         case IB_QPT_SMI:
1870         case MLX5_IB_QPT_HW_GSI:
1871         case IB_QPT_RC:
1872         case IB_QPT_UC:
1873         case IB_QPT_UD:
1874         case IB_QPT_RAW_IPV6:
1875         case IB_QPT_RAW_ETHERTYPE:
1876         case IB_QPT_RAW_PACKET:
1877                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1878                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1879                 break;
1880
1881         case IB_QPT_MAX:
1882         default:
1883                 *send_cq = NULL;
1884                 *recv_cq = NULL;
1885                 break;
1886         }
1887 }
1888
1889 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1890                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1891                                 u8 lag_tx_affinity);
1892
1893 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1894 {
1895         struct mlx5_ib_cq *send_cq, *recv_cq;
1896         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1897         unsigned long flags;
1898         int err;
1899
1900         if (qp->ibqp.rwq_ind_tbl) {
1901                 destroy_rss_raw_qp_tir(dev, qp);
1902                 return;
1903         }
1904
1905         base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1906                &qp->raw_packet_qp.rq.base :
1907                &qp->trans_qp.base;
1908
1909         if (qp->state != IB_QPS_RESET) {
1910                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1911                         err = mlx5_core_qp_modify(dev->mdev,
1912                                                   MLX5_CMD_OP_2RST_QP, 0,
1913                                                   NULL, &base->mqp);
1914                 } else {
1915                         struct mlx5_modify_raw_qp_param raw_qp_param = {
1916                                 .operation = MLX5_CMD_OP_2RST_QP
1917                         };
1918
1919                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1920                 }
1921                 if (err)
1922                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1923                                      base->mqp.qpn);
1924         }
1925
1926         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1927                 &send_cq, &recv_cq);
1928
1929         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1930         mlx5_ib_lock_cqs(send_cq, recv_cq);
1931         /* del from lists under both locks above to protect reset flow paths */
1932         list_del(&qp->qps_list);
1933         if (send_cq)
1934                 list_del(&qp->cq_send_list);
1935
1936         if (recv_cq)
1937                 list_del(&qp->cq_recv_list);
1938
1939         if (qp->create_type == MLX5_QP_KERNEL) {
1940                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1941                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1942                 if (send_cq != recv_cq)
1943                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1944                                            NULL);
1945         }
1946         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1947         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1948
1949         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1950                 destroy_raw_packet_qp(dev, qp);
1951         } else {
1952                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1953                 if (err)
1954                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1955                                      base->mqp.qpn);
1956         }
1957
1958         if (qp->create_type == MLX5_QP_KERNEL)
1959                 destroy_qp_kernel(dev, qp);
1960         else if (qp->create_type == MLX5_QP_USER)
1961                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
1962 }
1963
1964 static const char *ib_qp_type_str(enum ib_qp_type type)
1965 {
1966         switch (type) {
1967         case IB_QPT_SMI:
1968                 return "IB_QPT_SMI";
1969         case IB_QPT_GSI:
1970                 return "IB_QPT_GSI";
1971         case IB_QPT_RC:
1972                 return "IB_QPT_RC";
1973         case IB_QPT_UC:
1974                 return "IB_QPT_UC";
1975         case IB_QPT_UD:
1976                 return "IB_QPT_UD";
1977         case IB_QPT_RAW_IPV6:
1978                 return "IB_QPT_RAW_IPV6";
1979         case IB_QPT_RAW_ETHERTYPE:
1980                 return "IB_QPT_RAW_ETHERTYPE";
1981         case IB_QPT_XRC_INI:
1982                 return "IB_QPT_XRC_INI";
1983         case IB_QPT_XRC_TGT:
1984                 return "IB_QPT_XRC_TGT";
1985         case IB_QPT_RAW_PACKET:
1986                 return "IB_QPT_RAW_PACKET";
1987         case MLX5_IB_QPT_REG_UMR:
1988                 return "MLX5_IB_QPT_REG_UMR";
1989         case IB_QPT_MAX:
1990         default:
1991                 return "Invalid QP type";
1992         }
1993 }
1994
1995 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1996                                 struct ib_qp_init_attr *init_attr,
1997                                 struct ib_udata *udata)
1998 {
1999         struct mlx5_ib_dev *dev;
2000         struct mlx5_ib_qp *qp;
2001         u16 xrcdn = 0;
2002         int err;
2003
2004         if (pd) {
2005                 dev = to_mdev(pd->device);
2006
2007                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2008                         if (!pd->uobject) {
2009                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2010                                 return ERR_PTR(-EINVAL);
2011                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2012                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2013                                 return ERR_PTR(-EINVAL);
2014                         }
2015                 }
2016         } else {
2017                 /* being cautious here */
2018                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2019                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2020                         pr_warn("%s: no PD for transport %s\n", __func__,
2021                                 ib_qp_type_str(init_attr->qp_type));
2022                         return ERR_PTR(-EINVAL);
2023                 }
2024                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2025         }
2026
2027         switch (init_attr->qp_type) {
2028         case IB_QPT_XRC_TGT:
2029         case IB_QPT_XRC_INI:
2030                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2031                         mlx5_ib_dbg(dev, "XRC not supported\n");
2032                         return ERR_PTR(-ENOSYS);
2033                 }
2034                 init_attr->recv_cq = NULL;
2035                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2036                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2037                         init_attr->send_cq = NULL;
2038                 }
2039
2040                 /* fall through */
2041         case IB_QPT_RAW_PACKET:
2042         case IB_QPT_RC:
2043         case IB_QPT_UC:
2044         case IB_QPT_UD:
2045         case IB_QPT_SMI:
2046         case MLX5_IB_QPT_HW_GSI:
2047         case MLX5_IB_QPT_REG_UMR:
2048                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2049                 if (!qp)
2050                         return ERR_PTR(-ENOMEM);
2051
2052                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2053                 if (err) {
2054                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2055                         kfree(qp);
2056                         return ERR_PTR(err);
2057                 }
2058
2059                 if (is_qp0(init_attr->qp_type))
2060                         qp->ibqp.qp_num = 0;
2061                 else if (is_qp1(init_attr->qp_type))
2062                         qp->ibqp.qp_num = 1;
2063                 else
2064                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2065
2066                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2067                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2068                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2069                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2070
2071                 qp->trans_qp.xrcdn = xrcdn;
2072
2073                 break;
2074
2075         case IB_QPT_GSI:
2076                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2077
2078         case IB_QPT_RAW_IPV6:
2079         case IB_QPT_RAW_ETHERTYPE:
2080         case IB_QPT_MAX:
2081         default:
2082                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2083                             init_attr->qp_type);
2084                 /* Don't support raw QPs */
2085                 return ERR_PTR(-EINVAL);
2086         }
2087
2088         return &qp->ibqp;
2089 }
2090
2091 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2092 {
2093         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2094         struct mlx5_ib_qp *mqp = to_mqp(qp);
2095
2096         if (unlikely(qp->qp_type == IB_QPT_GSI))
2097                 return mlx5_ib_gsi_destroy_qp(qp);
2098
2099         destroy_qp_common(dev, mqp);
2100
2101         kfree(mqp);
2102
2103         return 0;
2104 }
2105
2106 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2107                                    int attr_mask)
2108 {
2109         u32 hw_access_flags = 0;
2110         u8 dest_rd_atomic;
2111         u32 access_flags;
2112
2113         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2114                 dest_rd_atomic = attr->max_dest_rd_atomic;
2115         else
2116                 dest_rd_atomic = qp->trans_qp.resp_depth;
2117
2118         if (attr_mask & IB_QP_ACCESS_FLAGS)
2119                 access_flags = attr->qp_access_flags;
2120         else
2121                 access_flags = qp->trans_qp.atomic_rd_en;
2122
2123         if (!dest_rd_atomic)
2124                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2125
2126         if (access_flags & IB_ACCESS_REMOTE_READ)
2127                 hw_access_flags |= MLX5_QP_BIT_RRE;
2128         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2129                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2130         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2131                 hw_access_flags |= MLX5_QP_BIT_RWE;
2132
2133         return cpu_to_be32(hw_access_flags);
2134 }
2135
2136 enum {
2137         MLX5_PATH_FLAG_FL       = 1 << 0,
2138         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2139         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2140 };
2141
2142 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2143 {
2144         if (rate == IB_RATE_PORT_CURRENT) {
2145                 return 0;
2146         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2147                 return -EINVAL;
2148         } else {
2149                 while (rate != IB_RATE_2_5_GBPS &&
2150                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2151                          MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2152                         --rate;
2153         }
2154
2155         return rate + MLX5_STAT_RATE_OFFSET;
2156 }
2157
2158 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2159                                       struct mlx5_ib_sq *sq, u8 sl)
2160 {
2161         void *in;
2162         void *tisc;
2163         int inlen;
2164         int err;
2165
2166         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2167         in = mlx5_vzalloc(inlen);
2168         if (!in)
2169                 return -ENOMEM;
2170
2171         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2172
2173         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2174         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2175
2176         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2177
2178         kvfree(in);
2179
2180         return err;
2181 }
2182
2183 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2184                                          struct mlx5_ib_sq *sq, u8 tx_affinity)
2185 {
2186         void *in;
2187         void *tisc;
2188         int inlen;
2189         int err;
2190
2191         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2192         in = mlx5_vzalloc(inlen);
2193         if (!in)
2194                 return -ENOMEM;
2195
2196         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2197
2198         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2199         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2200
2201         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2202
2203         kvfree(in);
2204
2205         return err;
2206 }
2207
2208 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2209                          const struct rdma_ah_attr *ah,
2210                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2211                          u32 path_flags, const struct ib_qp_attr *attr,
2212                          bool alt)
2213 {
2214         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2215         int err;
2216         enum ib_gid_type gid_type;
2217         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2218         u8 sl = rdma_ah_get_sl(ah);
2219
2220         if (attr_mask & IB_QP_PKEY_INDEX)
2221                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2222                                                      attr->pkey_index);
2223
2224         if (ah_flags & IB_AH_GRH) {
2225                 if (grh->sgid_index >=
2226                     dev->mdev->port_caps[port - 1].gid_table_len) {
2227                         pr_err("sgid_index (%u) too large. max is %d\n",
2228                                grh->sgid_index,
2229                                dev->mdev->port_caps[port - 1].gid_table_len);
2230                         return -EINVAL;
2231                 }
2232         }
2233
2234         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2235                 if (!(ah_flags & IB_AH_GRH))
2236                         return -EINVAL;
2237                 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
2238                                              &gid_type);
2239                 if (err)
2240                         return err;
2241                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2242                 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2243                                                           grh->sgid_index);
2244                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2245                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2246                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2247         } else {
2248                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2249                 path->fl_free_ar |=
2250                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2251                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2252                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2253                 if (ah_flags & IB_AH_GRH)
2254                         path->grh_mlid  |= 1 << 7;
2255                 path->dci_cfi_prio_sl = sl & 0xf;
2256         }
2257
2258         if (ah_flags & IB_AH_GRH) {
2259                 path->mgid_index = grh->sgid_index;
2260                 path->hop_limit  = grh->hop_limit;
2261                 path->tclass_flowlabel =
2262                         cpu_to_be32((grh->traffic_class << 20) |
2263                                     (grh->flow_label));
2264                 memcpy(path->rgid, grh->dgid.raw, 16);
2265         }
2266
2267         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2268         if (err < 0)
2269                 return err;
2270         path->static_rate = err;
2271         path->port = port;
2272
2273         if (attr_mask & IB_QP_TIMEOUT)
2274                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2275
2276         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2277                 return modify_raw_packet_eth_prio(dev->mdev,
2278                                                   &qp->raw_packet_qp.sq,
2279                                                   sl & 0xf);
2280
2281         return 0;
2282 }
2283
2284 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2285         [MLX5_QP_STATE_INIT] = {
2286                 [MLX5_QP_STATE_INIT] = {
2287                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2288                                           MLX5_QP_OPTPAR_RAE            |
2289                                           MLX5_QP_OPTPAR_RWE            |
2290                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2291                                           MLX5_QP_OPTPAR_PRI_PORT,
2292                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2293                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2294                                           MLX5_QP_OPTPAR_PRI_PORT,
2295                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2296                                           MLX5_QP_OPTPAR_Q_KEY          |
2297                                           MLX5_QP_OPTPAR_PRI_PORT,
2298                 },
2299                 [MLX5_QP_STATE_RTR] = {
2300                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2301                                           MLX5_QP_OPTPAR_RRE            |
2302                                           MLX5_QP_OPTPAR_RAE            |
2303                                           MLX5_QP_OPTPAR_RWE            |
2304                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2305                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2306                                           MLX5_QP_OPTPAR_RWE            |
2307                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2308                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2309                                           MLX5_QP_OPTPAR_Q_KEY,
2310                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2311                                            MLX5_QP_OPTPAR_Q_KEY,
2312                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2313                                           MLX5_QP_OPTPAR_RRE            |
2314                                           MLX5_QP_OPTPAR_RAE            |
2315                                           MLX5_QP_OPTPAR_RWE            |
2316                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2317                 },
2318         },
2319         [MLX5_QP_STATE_RTR] = {
2320                 [MLX5_QP_STATE_RTS] = {
2321                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2322                                           MLX5_QP_OPTPAR_RRE            |
2323                                           MLX5_QP_OPTPAR_RAE            |
2324                                           MLX5_QP_OPTPAR_RWE            |
2325                                           MLX5_QP_OPTPAR_PM_STATE       |
2326                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2327                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2328                                           MLX5_QP_OPTPAR_RWE            |
2329                                           MLX5_QP_OPTPAR_PM_STATE,
2330                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2331                 },
2332         },
2333         [MLX5_QP_STATE_RTS] = {
2334                 [MLX5_QP_STATE_RTS] = {
2335                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2336                                           MLX5_QP_OPTPAR_RAE            |
2337                                           MLX5_QP_OPTPAR_RWE            |
2338                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2339                                           MLX5_QP_OPTPAR_PM_STATE       |
2340                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2341                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2342                                           MLX5_QP_OPTPAR_PM_STATE       |
2343                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2344                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2345                                           MLX5_QP_OPTPAR_SRQN           |
2346                                           MLX5_QP_OPTPAR_CQN_RCV,
2347                 },
2348         },
2349         [MLX5_QP_STATE_SQER] = {
2350                 [MLX5_QP_STATE_RTS] = {
2351                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2352                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2353                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2354                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2355                                            MLX5_QP_OPTPAR_RWE           |
2356                                            MLX5_QP_OPTPAR_RAE           |
2357                                            MLX5_QP_OPTPAR_RRE,
2358                 },
2359         },
2360 };
2361
2362 static int ib_nr_to_mlx5_nr(int ib_mask)
2363 {
2364         switch (ib_mask) {
2365         case IB_QP_STATE:
2366                 return 0;
2367         case IB_QP_CUR_STATE:
2368                 return 0;
2369         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2370                 return 0;
2371         case IB_QP_ACCESS_FLAGS:
2372                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2373                         MLX5_QP_OPTPAR_RAE;
2374         case IB_QP_PKEY_INDEX:
2375                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2376         case IB_QP_PORT:
2377                 return MLX5_QP_OPTPAR_PRI_PORT;
2378         case IB_QP_QKEY:
2379                 return MLX5_QP_OPTPAR_Q_KEY;
2380         case IB_QP_AV:
2381                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2382                         MLX5_QP_OPTPAR_PRI_PORT;
2383         case IB_QP_PATH_MTU:
2384                 return 0;
2385         case IB_QP_TIMEOUT:
2386                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2387         case IB_QP_RETRY_CNT:
2388                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2389         case IB_QP_RNR_RETRY:
2390                 return MLX5_QP_OPTPAR_RNR_RETRY;
2391         case IB_QP_RQ_PSN:
2392                 return 0;
2393         case IB_QP_MAX_QP_RD_ATOMIC:
2394                 return MLX5_QP_OPTPAR_SRA_MAX;
2395         case IB_QP_ALT_PATH:
2396                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2397         case IB_QP_MIN_RNR_TIMER:
2398                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2399         case IB_QP_SQ_PSN:
2400                 return 0;
2401         case IB_QP_MAX_DEST_RD_ATOMIC:
2402                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2403                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2404         case IB_QP_PATH_MIG_STATE:
2405                 return MLX5_QP_OPTPAR_PM_STATE;
2406         case IB_QP_CAP:
2407                 return 0;
2408         case IB_QP_DEST_QPN:
2409                 return 0;
2410         }
2411         return 0;
2412 }
2413
2414 static int ib_mask_to_mlx5_opt(int ib_mask)
2415 {
2416         int result = 0;
2417         int i;
2418
2419         for (i = 0; i < 8 * sizeof(int); i++) {
2420                 if ((1 << i) & ib_mask)
2421                         result |= ib_nr_to_mlx5_nr(1 << i);
2422         }
2423
2424         return result;
2425 }
2426
2427 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2428                                    struct mlx5_ib_rq *rq, int new_state,
2429                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2430 {
2431         void *in;
2432         void *rqc;
2433         int inlen;
2434         int err;
2435
2436         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2437         in = mlx5_vzalloc(inlen);
2438         if (!in)
2439                 return -ENOMEM;
2440
2441         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2442
2443         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2444         MLX5_SET(rqc, rqc, state, new_state);
2445
2446         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2447                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2448                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
2449                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2450                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2451                 } else
2452                         pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2453                                      dev->ib_dev.name);
2454         }
2455
2456         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2457         if (err)
2458                 goto out;
2459
2460         rq->state = new_state;
2461
2462 out:
2463         kvfree(in);
2464         return err;
2465 }
2466
2467 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2468                                    struct mlx5_ib_sq *sq,
2469                                    int new_state,
2470                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2471 {
2472         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2473         u32 old_rate = ibqp->rate_limit;
2474         u32 new_rate = old_rate;
2475         u16 rl_index = 0;
2476         void *in;
2477         void *sqc;
2478         int inlen;
2479         int err;
2480
2481         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2482         in = mlx5_vzalloc(inlen);
2483         if (!in)
2484                 return -ENOMEM;
2485
2486         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2487
2488         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2489         MLX5_SET(sqc, sqc, state, new_state);
2490
2491         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2492                 if (new_state != MLX5_SQC_STATE_RDY)
2493                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2494                                 __func__);
2495                 else
2496                         new_rate = raw_qp_param->rate_limit;
2497         }
2498
2499         if (old_rate != new_rate) {
2500                 if (new_rate) {
2501                         err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2502                         if (err) {
2503                                 pr_err("Failed configuring rate %u: %d\n",
2504                                        new_rate, err);
2505                                 goto out;
2506                         }
2507                 }
2508
2509                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2510                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2511         }
2512
2513         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2514         if (err) {
2515                 /* Remove new rate from table if failed */
2516                 if (new_rate &&
2517                     old_rate != new_rate)
2518                         mlx5_rl_remove_rate(dev, new_rate);
2519                 goto out;
2520         }
2521
2522         /* Only remove the old rate after new rate was set */
2523         if ((old_rate &&
2524             (old_rate != new_rate)) ||
2525             (new_state != MLX5_SQC_STATE_RDY))
2526                 mlx5_rl_remove_rate(dev, old_rate);
2527
2528         ibqp->rate_limit = new_rate;
2529         sq->state = new_state;
2530
2531 out:
2532         kvfree(in);
2533         return err;
2534 }
2535
2536 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2537                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2538                                 u8 tx_affinity)
2539 {
2540         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2541         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2542         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2543         int modify_rq = !!qp->rq.wqe_cnt;
2544         int modify_sq = !!qp->sq.wqe_cnt;
2545         int rq_state;
2546         int sq_state;
2547         int err;
2548
2549         switch (raw_qp_param->operation) {
2550         case MLX5_CMD_OP_RST2INIT_QP:
2551                 rq_state = MLX5_RQC_STATE_RDY;
2552                 sq_state = MLX5_SQC_STATE_RDY;
2553                 break;
2554         case MLX5_CMD_OP_2ERR_QP:
2555                 rq_state = MLX5_RQC_STATE_ERR;
2556                 sq_state = MLX5_SQC_STATE_ERR;
2557                 break;
2558         case MLX5_CMD_OP_2RST_QP:
2559                 rq_state = MLX5_RQC_STATE_RST;
2560                 sq_state = MLX5_SQC_STATE_RST;
2561                 break;
2562         case MLX5_CMD_OP_RTR2RTS_QP:
2563         case MLX5_CMD_OP_RTS2RTS_QP:
2564                 if (raw_qp_param->set_mask ==
2565                     MLX5_RAW_QP_RATE_LIMIT) {
2566                         modify_rq = 0;
2567                         sq_state = sq->state;
2568                 } else {
2569                         return raw_qp_param->set_mask ? -EINVAL : 0;
2570                 }
2571                 break;
2572         case MLX5_CMD_OP_INIT2INIT_QP:
2573         case MLX5_CMD_OP_INIT2RTR_QP:
2574                 if (raw_qp_param->set_mask)
2575                         return -EINVAL;
2576                 else
2577                         return 0;
2578         default:
2579                 WARN_ON(1);
2580                 return -EINVAL;
2581         }
2582
2583         if (modify_rq) {
2584                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2585                 if (err)
2586                         return err;
2587         }
2588
2589         if (modify_sq) {
2590                 if (tx_affinity) {
2591                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2592                                                             tx_affinity);
2593                         if (err)
2594                                 return err;
2595                 }
2596
2597                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2598         }
2599
2600         return 0;
2601 }
2602
2603 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2604                                const struct ib_qp_attr *attr, int attr_mask,
2605                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2606 {
2607         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2608                 [MLX5_QP_STATE_RST] = {
2609                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2610                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2611                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
2612                 },
2613                 [MLX5_QP_STATE_INIT]  = {
2614                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2615                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2616                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
2617                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
2618                 },
2619                 [MLX5_QP_STATE_RTR]   = {
2620                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2621                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2622                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
2623                 },
2624                 [MLX5_QP_STATE_RTS]   = {
2625                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2626                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2627                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
2628                 },
2629                 [MLX5_QP_STATE_SQD] = {
2630                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2631                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2632                 },
2633                 [MLX5_QP_STATE_SQER] = {
2634                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2635                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2636                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
2637                 },
2638                 [MLX5_QP_STATE_ERR] = {
2639                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2640                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2641                 }
2642         };
2643
2644         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2645         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2646         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2647         struct mlx5_ib_cq *send_cq, *recv_cq;
2648         struct mlx5_qp_context *context;
2649         struct mlx5_ib_pd *pd;
2650         struct mlx5_ib_port *mibport = NULL;
2651         enum mlx5_qp_state mlx5_cur, mlx5_new;
2652         enum mlx5_qp_optpar optpar;
2653         int mlx5_st;
2654         int err;
2655         u16 op;
2656         u8 tx_affinity = 0;
2657
2658         context = kzalloc(sizeof(*context), GFP_KERNEL);
2659         if (!context)
2660                 return -ENOMEM;
2661
2662         err = to_mlx5_st(ibqp->qp_type);
2663         if (err < 0) {
2664                 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2665                 goto out;
2666         }
2667
2668         context->flags = cpu_to_be32(err << 16);
2669
2670         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2671                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2672         } else {
2673                 switch (attr->path_mig_state) {
2674                 case IB_MIG_MIGRATED:
2675                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2676                         break;
2677                 case IB_MIG_REARM:
2678                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2679                         break;
2680                 case IB_MIG_ARMED:
2681                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2682                         break;
2683                 }
2684         }
2685
2686         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2687                 if ((ibqp->qp_type == IB_QPT_RC) ||
2688                     (ibqp->qp_type == IB_QPT_UD &&
2689                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2690                     (ibqp->qp_type == IB_QPT_UC) ||
2691                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2692                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
2693                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2694                         if (mlx5_lag_is_active(dev->mdev)) {
2695                                 tx_affinity = (unsigned int)atomic_add_return(1,
2696                                                 &dev->roce.next_port) %
2697                                                 MLX5_MAX_PORTS + 1;
2698                                 context->flags |= cpu_to_be32(tx_affinity << 24);
2699                         }
2700                 }
2701         }
2702
2703         if (is_sqp(ibqp->qp_type)) {
2704                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2705         } else if (ibqp->qp_type == IB_QPT_UD ||
2706                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2707                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2708         } else if (attr_mask & IB_QP_PATH_MTU) {
2709                 if (attr->path_mtu < IB_MTU_256 ||
2710                     attr->path_mtu > IB_MTU_4096) {
2711                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2712                         err = -EINVAL;
2713                         goto out;
2714                 }
2715                 context->mtu_msgmax = (attr->path_mtu << 5) |
2716                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2717         }
2718
2719         if (attr_mask & IB_QP_DEST_QPN)
2720                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2721
2722         if (attr_mask & IB_QP_PKEY_INDEX)
2723                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2724
2725         /* todo implement counter_index functionality */
2726
2727         if (is_sqp(ibqp->qp_type))
2728                 context->pri_path.port = qp->port;
2729
2730         if (attr_mask & IB_QP_PORT)
2731                 context->pri_path.port = attr->port_num;
2732
2733         if (attr_mask & IB_QP_AV) {
2734                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2735                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2736                                     attr_mask, 0, attr, false);
2737                 if (err)
2738                         goto out;
2739         }
2740
2741         if (attr_mask & IB_QP_TIMEOUT)
2742                 context->pri_path.ackto_lt |= attr->timeout << 3;
2743
2744         if (attr_mask & IB_QP_ALT_PATH) {
2745                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2746                                     &context->alt_path,
2747                                     attr->alt_port_num,
2748                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2749                                     0, attr, true);
2750                 if (err)
2751                         goto out;
2752         }
2753
2754         pd = get_pd(qp);
2755         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2756                 &send_cq, &recv_cq);
2757
2758         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2759         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2760         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2761         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2762
2763         if (attr_mask & IB_QP_RNR_RETRY)
2764                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2765
2766         if (attr_mask & IB_QP_RETRY_CNT)
2767                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2768
2769         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2770                 if (attr->max_rd_atomic)
2771                         context->params1 |=
2772                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2773         }
2774
2775         if (attr_mask & IB_QP_SQ_PSN)
2776                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2777
2778         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2779                 if (attr->max_dest_rd_atomic)
2780                         context->params2 |=
2781                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2782         }
2783
2784         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2785                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2786
2787         if (attr_mask & IB_QP_MIN_RNR_TIMER)
2788                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2789
2790         if (attr_mask & IB_QP_RQ_PSN)
2791                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2792
2793         if (attr_mask & IB_QP_QKEY)
2794                 context->qkey = cpu_to_be32(attr->qkey);
2795
2796         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2797                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2798
2799         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2800                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2801                                qp->port) - 1;
2802                 mibport = &dev->port[port_num];
2803                 context->qp_counter_set_usr_page |=
2804                         cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
2805         }
2806
2807         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2808                 context->sq_crq_size |= cpu_to_be16(1 << 4);
2809
2810         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2811                 context->deth_sqpn = cpu_to_be32(1);
2812
2813         mlx5_cur = to_mlx5_state(cur_state);
2814         mlx5_new = to_mlx5_state(new_state);
2815         mlx5_st = to_mlx5_st(ibqp->qp_type);
2816         if (mlx5_st < 0)
2817                 goto out;
2818
2819         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2820             !optab[mlx5_cur][mlx5_new])
2821                 goto out;
2822
2823         op = optab[mlx5_cur][mlx5_new];
2824         optpar = ib_mask_to_mlx5_opt(attr_mask);
2825         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2826
2827         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2828                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2829
2830                 raw_qp_param.operation = op;
2831                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2832                         raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
2833                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2834                 }
2835
2836                 if (attr_mask & IB_QP_RATE_LIMIT) {
2837                         raw_qp_param.rate_limit = attr->rate_limit;
2838                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2839                 }
2840
2841                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
2842         } else {
2843                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2844                                           &base->mqp);
2845         }
2846
2847         if (err)
2848                 goto out;
2849
2850         qp->state = new_state;
2851
2852         if (attr_mask & IB_QP_ACCESS_FLAGS)
2853                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2854         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2855                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2856         if (attr_mask & IB_QP_PORT)
2857                 qp->port = attr->port_num;
2858         if (attr_mask & IB_QP_ALT_PATH)
2859                 qp->trans_qp.alt_port = attr->alt_port_num;
2860
2861         /*
2862          * If we moved a kernel QP to RESET, clean up all old CQ
2863          * entries and reinitialize the QP.
2864          */
2865         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2866                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2867                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2868                 if (send_cq != recv_cq)
2869                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2870
2871                 qp->rq.head = 0;
2872                 qp->rq.tail = 0;
2873                 qp->sq.head = 0;
2874                 qp->sq.tail = 0;
2875                 qp->sq.cur_post = 0;
2876                 qp->sq.last_poll = 0;
2877                 qp->db.db[MLX5_RCV_DBR] = 0;
2878                 qp->db.db[MLX5_SND_DBR] = 0;
2879         }
2880
2881 out:
2882         kfree(context);
2883         return err;
2884 }
2885
2886 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2887                       int attr_mask, struct ib_udata *udata)
2888 {
2889         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2890         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2891         enum ib_qp_type qp_type;
2892         enum ib_qp_state cur_state, new_state;
2893         int err = -EINVAL;
2894         int port;
2895         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2896
2897         if (ibqp->rwq_ind_tbl)
2898                 return -ENOSYS;
2899
2900         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2901                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2902
2903         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2904                 IB_QPT_GSI : ibqp->qp_type;
2905
2906         mutex_lock(&qp->mutex);
2907
2908         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2909         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2910
2911         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2912                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2913                 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2914         }
2915
2916         if (qp_type != MLX5_IB_QPT_REG_UMR &&
2917             !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2918                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2919                             cur_state, new_state, ibqp->qp_type, attr_mask);
2920                 goto out;
2921         }
2922
2923         if ((attr_mask & IB_QP_PORT) &&
2924             (attr->port_num == 0 ||
2925              attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2926                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2927                             attr->port_num, dev->num_ports);
2928                 goto out;
2929         }
2930
2931         if (attr_mask & IB_QP_PKEY_INDEX) {
2932                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2933                 if (attr->pkey_index >=
2934                     dev->mdev->port_caps[port - 1].pkey_table_len) {
2935                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2936                                     attr->pkey_index);
2937                         goto out;
2938                 }
2939         }
2940
2941         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2942             attr->max_rd_atomic >
2943             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2944                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2945                             attr->max_rd_atomic);
2946                 goto out;
2947         }
2948
2949         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2950             attr->max_dest_rd_atomic >
2951             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2952                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2953                             attr->max_dest_rd_atomic);
2954                 goto out;
2955         }
2956
2957         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2958                 err = 0;
2959                 goto out;
2960         }
2961
2962         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2963
2964 out:
2965         mutex_unlock(&qp->mutex);
2966         return err;
2967 }
2968
2969 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2970 {
2971         struct mlx5_ib_cq *cq;
2972         unsigned cur;
2973
2974         cur = wq->head - wq->tail;
2975         if (likely(cur + nreq < wq->max_post))
2976                 return 0;
2977
2978         cq = to_mcq(ib_cq);
2979         spin_lock(&cq->lock);
2980         cur = wq->head - wq->tail;
2981         spin_unlock(&cq->lock);
2982
2983         return cur + nreq >= wq->max_post;
2984 }
2985
2986 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2987                                           u64 remote_addr, u32 rkey)
2988 {
2989         rseg->raddr    = cpu_to_be64(remote_addr);
2990         rseg->rkey     = cpu_to_be32(rkey);
2991         rseg->reserved = 0;
2992 }
2993
2994 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2995                          struct ib_send_wr *wr, void *qend,
2996                          struct mlx5_ib_qp *qp, int *size)
2997 {
2998         void *seg = eseg;
2999
3000         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3001
3002         if (wr->send_flags & IB_SEND_IP_CSUM)
3003                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3004                                  MLX5_ETH_WQE_L4_CSUM;
3005
3006         seg += sizeof(struct mlx5_wqe_eth_seg);
3007         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3008
3009         if (wr->opcode == IB_WR_LSO) {
3010                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3011                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3012                 u64 left, leftlen, copysz;
3013                 void *pdata = ud_wr->header;
3014
3015                 left = ud_wr->hlen;
3016                 eseg->mss = cpu_to_be16(ud_wr->mss);
3017                 eseg->inline_hdr.sz = cpu_to_be16(left);
3018
3019                 /*
3020                  * check if there is space till the end of queue, if yes,
3021                  * copy all in one shot, otherwise copy till the end of queue,
3022                  * rollback and than the copy the left
3023                  */
3024                 leftlen = qend - (void *)eseg->inline_hdr.start;
3025                 copysz = min_t(u64, leftlen, left);
3026
3027                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3028
3029                 if (likely(copysz > size_of_inl_hdr_start)) {
3030                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3031                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3032                 }
3033
3034                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3035                         seg = mlx5_get_send_wqe(qp, 0);
3036                         left -= copysz;
3037                         pdata += copysz;
3038                         memcpy(seg, pdata, left);
3039                         seg += ALIGN(left, 16);
3040                         *size += ALIGN(left, 16) / 16;
3041                 }
3042         }
3043
3044         return seg;
3045 }
3046
3047 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3048                              struct ib_send_wr *wr)
3049 {
3050         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3051         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3052         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3053 }
3054
3055 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3056 {
3057         dseg->byte_count = cpu_to_be32(sg->length);
3058         dseg->lkey       = cpu_to_be32(sg->lkey);
3059         dseg->addr       = cpu_to_be64(sg->addr);
3060 }
3061
3062 static u64 get_xlt_octo(u64 bytes)
3063 {
3064         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3065                MLX5_IB_UMR_OCTOWORD;
3066 }
3067
3068 static __be64 frwr_mkey_mask(void)
3069 {
3070         u64 result;
3071
3072         result = MLX5_MKEY_MASK_LEN             |
3073                 MLX5_MKEY_MASK_PAGE_SIZE        |
3074                 MLX5_MKEY_MASK_START_ADDR       |
3075                 MLX5_MKEY_MASK_EN_RINVAL        |
3076                 MLX5_MKEY_MASK_KEY              |
3077                 MLX5_MKEY_MASK_LR               |
3078                 MLX5_MKEY_MASK_LW               |
3079                 MLX5_MKEY_MASK_RR               |
3080                 MLX5_MKEY_MASK_RW               |
3081                 MLX5_MKEY_MASK_A                |
3082                 MLX5_MKEY_MASK_SMALL_FENCE      |
3083                 MLX5_MKEY_MASK_FREE;
3084
3085         return cpu_to_be64(result);
3086 }
3087
3088 static __be64 sig_mkey_mask(void)
3089 {
3090         u64 result;
3091
3092         result = MLX5_MKEY_MASK_LEN             |
3093                 MLX5_MKEY_MASK_PAGE_SIZE        |
3094                 MLX5_MKEY_MASK_START_ADDR       |
3095                 MLX5_MKEY_MASK_EN_SIGERR        |
3096                 MLX5_MKEY_MASK_EN_RINVAL        |
3097                 MLX5_MKEY_MASK_KEY              |
3098                 MLX5_MKEY_MASK_LR               |
3099                 MLX5_MKEY_MASK_LW               |
3100                 MLX5_MKEY_MASK_RR               |
3101                 MLX5_MKEY_MASK_RW               |
3102                 MLX5_MKEY_MASK_SMALL_FENCE      |
3103                 MLX5_MKEY_MASK_FREE             |
3104                 MLX5_MKEY_MASK_BSF_EN;
3105
3106         return cpu_to_be64(result);
3107 }
3108
3109 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3110                             struct mlx5_ib_mr *mr)
3111 {
3112         int size = mr->ndescs * mr->desc_size;
3113
3114         memset(umr, 0, sizeof(*umr));
3115
3116         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3117         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3118         umr->mkey_mask = frwr_mkey_mask();
3119 }
3120
3121 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3122 {
3123         memset(umr, 0, sizeof(*umr));
3124         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3125         umr->flags = MLX5_UMR_INLINE;
3126 }
3127
3128 static __be64 get_umr_enable_mr_mask(void)
3129 {
3130         u64 result;
3131
3132         result = MLX5_MKEY_MASK_KEY |
3133                  MLX5_MKEY_MASK_FREE;
3134
3135         return cpu_to_be64(result);
3136 }
3137
3138 static __be64 get_umr_disable_mr_mask(void)
3139 {
3140         u64 result;
3141
3142         result = MLX5_MKEY_MASK_FREE;
3143
3144         return cpu_to_be64(result);
3145 }
3146
3147 static __be64 get_umr_update_translation_mask(void)
3148 {
3149         u64 result;
3150
3151         result = MLX5_MKEY_MASK_LEN |
3152                  MLX5_MKEY_MASK_PAGE_SIZE |
3153                  MLX5_MKEY_MASK_START_ADDR;
3154
3155         return cpu_to_be64(result);
3156 }
3157
3158 static __be64 get_umr_update_access_mask(int atomic)
3159 {
3160         u64 result;
3161
3162         result = MLX5_MKEY_MASK_LR |
3163                  MLX5_MKEY_MASK_LW |
3164                  MLX5_MKEY_MASK_RR |
3165                  MLX5_MKEY_MASK_RW;
3166
3167         if (atomic)
3168                 result |= MLX5_MKEY_MASK_A;
3169
3170         return cpu_to_be64(result);
3171 }
3172
3173 static __be64 get_umr_update_pd_mask(void)
3174 {
3175         u64 result;
3176
3177         result = MLX5_MKEY_MASK_PD;
3178
3179         return cpu_to_be64(result);
3180 }
3181
3182 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3183                                 struct ib_send_wr *wr, int atomic)
3184 {
3185         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3186
3187         memset(umr, 0, sizeof(*umr));
3188
3189         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3190                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3191         else
3192                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3193
3194         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3195         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3196                 u64 offset = get_xlt_octo(umrwr->offset);
3197
3198                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3199                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3200                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3201         }
3202         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3203                 umr->mkey_mask |= get_umr_update_translation_mask();
3204         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3205                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3206                 umr->mkey_mask |= get_umr_update_pd_mask();
3207         }
3208         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3209                 umr->mkey_mask |= get_umr_enable_mr_mask();
3210         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3211                 umr->mkey_mask |= get_umr_disable_mr_mask();
3212
3213         if (!wr->num_sge)
3214                 umr->flags |= MLX5_UMR_INLINE;
3215 }
3216
3217 static u8 get_umr_flags(int acc)
3218 {
3219         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3220                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3221                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3222                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3223                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3224 }
3225
3226 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3227                              struct mlx5_ib_mr *mr,
3228                              u32 key, int access)
3229 {
3230         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3231
3232         memset(seg, 0, sizeof(*seg));
3233
3234         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3235                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3236         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3237                 /* KLMs take twice the size of MTTs */
3238                 ndescs *= 2;
3239
3240         seg->flags = get_umr_flags(access) | mr->access_mode;
3241         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3242         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3243         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3244         seg->len = cpu_to_be64(mr->ibmr.length);
3245         seg->xlt_oct_size = cpu_to_be32(ndescs);
3246 }
3247
3248 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3249 {
3250         memset(seg, 0, sizeof(*seg));
3251         seg->status = MLX5_MKEY_STATUS_FREE;
3252 }
3253
3254 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3255 {
3256         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3257
3258         memset(seg, 0, sizeof(*seg));
3259         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3260                 seg->status = MLX5_MKEY_STATUS_FREE;
3261
3262         seg->flags = convert_access(umrwr->access_flags);
3263         if (umrwr->pd)
3264                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3265         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3266             !umrwr->length)
3267                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3268
3269         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3270         seg->len = cpu_to_be64(umrwr->length);
3271         seg->log2_page_size = umrwr->page_shift;
3272         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3273                                        mlx5_mkey_variant(umrwr->mkey));
3274 }
3275
3276 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3277                              struct mlx5_ib_mr *mr,
3278                              struct mlx5_ib_pd *pd)
3279 {
3280         int bcount = mr->desc_size * mr->ndescs;
3281
3282         dseg->addr = cpu_to_be64(mr->desc_map);
3283         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3284         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3285 }
3286
3287 static __be32 send_ieth(struct ib_send_wr *wr)
3288 {
3289         switch (wr->opcode) {
3290         case IB_WR_SEND_WITH_IMM:
3291         case IB_WR_RDMA_WRITE_WITH_IMM:
3292                 return wr->ex.imm_data;
3293
3294         case IB_WR_SEND_WITH_INV:
3295                 return cpu_to_be32(wr->ex.invalidate_rkey);
3296
3297         default:
3298                 return 0;
3299         }
3300 }
3301
3302 static u8 calc_sig(void *wqe, int size)
3303 {
3304         u8 *p = wqe;
3305         u8 res = 0;
3306         int i;
3307
3308         for (i = 0; i < size; i++)
3309                 res ^= p[i];
3310
3311         return ~res;
3312 }
3313
3314 static u8 wq_sig(void *wqe)
3315 {
3316         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3317 }
3318
3319 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3320                             void *wqe, int *sz)
3321 {
3322         struct mlx5_wqe_inline_seg *seg;
3323         void *qend = qp->sq.qend;
3324         void *addr;
3325         int inl = 0;
3326         int copy;
3327         int len;
3328         int i;
3329
3330         seg = wqe;
3331         wqe += sizeof(*seg);
3332         for (i = 0; i < wr->num_sge; i++) {
3333                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3334                 len  = wr->sg_list[i].length;
3335                 inl += len;
3336
3337                 if (unlikely(inl > qp->max_inline_data))
3338                         return -ENOMEM;
3339
3340                 if (unlikely(wqe + len > qend)) {
3341                         copy = qend - wqe;
3342                         memcpy(wqe, addr, copy);
3343                         addr += copy;
3344                         len -= copy;
3345                         wqe = mlx5_get_send_wqe(qp, 0);
3346                 }
3347                 memcpy(wqe, addr, len);
3348                 wqe += len;
3349         }
3350
3351         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3352
3353         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3354
3355         return 0;
3356 }
3357
3358 static u16 prot_field_size(enum ib_signature_type type)
3359 {
3360         switch (type) {
3361         case IB_SIG_TYPE_T10_DIF:
3362                 return MLX5_DIF_SIZE;
3363         default:
3364                 return 0;
3365         }
3366 }
3367
3368 static u8 bs_selector(int block_size)
3369 {
3370         switch (block_size) {
3371         case 512:           return 0x1;
3372         case 520:           return 0x2;
3373         case 4096:          return 0x3;
3374         case 4160:          return 0x4;
3375         case 1073741824:    return 0x5;
3376         default:            return 0;
3377         }
3378 }
3379
3380 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3381                               struct mlx5_bsf_inl *inl)
3382 {
3383         /* Valid inline section and allow BSF refresh */
3384         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3385                                        MLX5_BSF_REFRESH_DIF);
3386         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3387         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3388         /* repeating block */
3389         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3390         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3391                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
3392
3393         if (domain->sig.dif.ref_remap)
3394                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3395
3396         if (domain->sig.dif.app_escape) {
3397                 if (domain->sig.dif.ref_escape)
3398                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3399                 else
3400                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3401         }
3402
3403         inl->dif_app_bitmask_check =
3404                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3405 }
3406
3407 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3408                         struct ib_sig_attrs *sig_attrs,
3409                         struct mlx5_bsf *bsf, u32 data_size)
3410 {
3411         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3412         struct mlx5_bsf_basic *basic = &bsf->basic;
3413         struct ib_sig_domain *mem = &sig_attrs->mem;
3414         struct ib_sig_domain *wire = &sig_attrs->wire;
3415
3416         memset(bsf, 0, sizeof(*bsf));
3417
3418         /* Basic + Extended + Inline */
3419         basic->bsf_size_sbs = 1 << 7;
3420         /* Input domain check byte mask */
3421         basic->check_byte_mask = sig_attrs->check_mask;
3422         basic->raw_data_size = cpu_to_be32(data_size);
3423
3424         /* Memory domain */
3425         switch (sig_attrs->mem.sig_type) {
3426         case IB_SIG_TYPE_NONE:
3427                 break;
3428         case IB_SIG_TYPE_T10_DIF:
3429                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3430                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3431                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3432                 break;
3433         default:
3434                 return -EINVAL;
3435         }
3436
3437         /* Wire domain */
3438         switch (sig_attrs->wire.sig_type) {
3439         case IB_SIG_TYPE_NONE:
3440                 break;
3441         case IB_SIG_TYPE_T10_DIF:
3442                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3443                     mem->sig_type == wire->sig_type) {
3444                         /* Same block structure */
3445                         basic->bsf_size_sbs |= 1 << 4;
3446                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3447                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3448                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3449                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3450                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3451                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3452                 } else
3453                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3454
3455                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3456                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3457                 break;
3458         default:
3459                 return -EINVAL;
3460         }
3461
3462         return 0;
3463 }
3464
3465 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3466                                 struct mlx5_ib_qp *qp, void **seg, int *size)
3467 {
3468         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3469         struct ib_mr *sig_mr = wr->sig_mr;
3470         struct mlx5_bsf *bsf;
3471         u32 data_len = wr->wr.sg_list->length;
3472         u32 data_key = wr->wr.sg_list->lkey;
3473         u64 data_va = wr->wr.sg_list->addr;
3474         int ret;
3475         int wqe_size;
3476
3477         if (!wr->prot ||
3478             (data_key == wr->prot->lkey &&
3479              data_va == wr->prot->addr &&
3480              data_len == wr->prot->length)) {
3481                 /**
3482                  * Source domain doesn't contain signature information
3483                  * or data and protection are interleaved in memory.
3484                  * So need construct:
3485                  *                  ------------------
3486                  *                 |     data_klm     |
3487                  *                  ------------------
3488                  *                 |       BSF        |
3489                  *                  ------------------
3490                  **/
3491                 struct mlx5_klm *data_klm = *seg;
3492
3493                 data_klm->bcount = cpu_to_be32(data_len);
3494                 data_klm->key = cpu_to_be32(data_key);
3495                 data_klm->va = cpu_to_be64(data_va);
3496                 wqe_size = ALIGN(sizeof(*data_klm), 64);
3497         } else {
3498                 /**
3499                  * Source domain contains signature information
3500                  * So need construct a strided block format:
3501                  *               ---------------------------
3502                  *              |     stride_block_ctrl     |
3503                  *               ---------------------------
3504                  *              |          data_klm         |
3505                  *               ---------------------------
3506                  *              |          prot_klm         |
3507                  *               ---------------------------
3508                  *              |             BSF           |
3509                  *               ---------------------------
3510                  **/
3511                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3512                 struct mlx5_stride_block_entry *data_sentry;
3513                 struct mlx5_stride_block_entry *prot_sentry;
3514                 u32 prot_key = wr->prot->lkey;
3515                 u64 prot_va = wr->prot->addr;
3516                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3517                 int prot_size;
3518
3519                 sblock_ctrl = *seg;
3520                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3521                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3522
3523                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3524                 if (!prot_size) {
3525                         pr_err("Bad block size given: %u\n", block_size);
3526                         return -EINVAL;
3527                 }
3528                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3529                                                             prot_size);
3530                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3531                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3532                 sblock_ctrl->num_entries = cpu_to_be16(2);
3533
3534                 data_sentry->bcount = cpu_to_be16(block_size);
3535                 data_sentry->key = cpu_to_be32(data_key);
3536                 data_sentry->va = cpu_to_be64(data_va);
3537                 data_sentry->stride = cpu_to_be16(block_size);
3538
3539                 prot_sentry->bcount = cpu_to_be16(prot_size);
3540                 prot_sentry->key = cpu_to_be32(prot_key);
3541                 prot_sentry->va = cpu_to_be64(prot_va);
3542                 prot_sentry->stride = cpu_to_be16(prot_size);
3543
3544                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3545                                  sizeof(*prot_sentry), 64);
3546         }
3547
3548         *seg += wqe_size;
3549         *size += wqe_size / 16;
3550         if (unlikely((*seg == qp->sq.qend)))
3551                 *seg = mlx5_get_send_wqe(qp, 0);
3552
3553         bsf = *seg;
3554         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3555         if (ret)
3556                 return -EINVAL;
3557
3558         *seg += sizeof(*bsf);
3559         *size += sizeof(*bsf) / 16;
3560         if (unlikely((*seg == qp->sq.qend)))
3561                 *seg = mlx5_get_send_wqe(qp, 0);
3562
3563         return 0;
3564 }
3565
3566 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3567                                  struct ib_sig_handover_wr *wr, u32 size,
3568                                  u32 length, u32 pdn)
3569 {
3570         struct ib_mr *sig_mr = wr->sig_mr;
3571         u32 sig_key = sig_mr->rkey;
3572         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3573
3574         memset(seg, 0, sizeof(*seg));
3575
3576         seg->flags = get_umr_flags(wr->access_flags) |
3577                                    MLX5_MKC_ACCESS_MODE_KLMS;
3578         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3579         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3580                                     MLX5_MKEY_BSF_EN | pdn);
3581         seg->len = cpu_to_be64(length);
3582         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
3583         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3584 }
3585
3586 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3587                                 u32 size)
3588 {
3589         memset(umr, 0, sizeof(*umr));
3590
3591         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3592         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3593         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3594         umr->mkey_mask = sig_mkey_mask();
3595 }
3596
3597
3598 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3599                           void **seg, int *size)
3600 {
3601         struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3602         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3603         u32 pdn = get_pd(qp)->pdn;
3604         u32 xlt_size;
3605         int region_len, ret;
3606
3607         if (unlikely(wr->wr.num_sge != 1) ||
3608             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3609             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3610             unlikely(!sig_mr->sig->sig_status_checked))
3611                 return -EINVAL;
3612
3613         /* length of the protected region, data + protection */
3614         region_len = wr->wr.sg_list->length;
3615         if (wr->prot &&
3616             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
3617              wr->prot->addr != wr->wr.sg_list->addr  ||
3618              wr->prot->length != wr->wr.sg_list->length))
3619                 region_len += wr->prot->length;
3620
3621         /**
3622          * KLM octoword size - if protection was provided
3623          * then we use strided block format (3 octowords),
3624          * else we use single KLM (1 octoword)
3625          **/
3626         xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
3627
3628         set_sig_umr_segment(*seg, xlt_size);
3629         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3630         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3631         if (unlikely((*seg == qp->sq.qend)))
3632                 *seg = mlx5_get_send_wqe(qp, 0);
3633
3634         set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
3635         *seg += sizeof(struct mlx5_mkey_seg);
3636         *size += sizeof(struct mlx5_mkey_seg) / 16;
3637         if (unlikely((*seg == qp->sq.qend)))
3638                 *seg = mlx5_get_send_wqe(qp, 0);
3639
3640         ret = set_sig_data_segment(wr, qp, seg, size);
3641         if (ret)
3642                 return ret;
3643
3644         sig_mr->sig->sig_status_checked = false;
3645         return 0;
3646 }
3647
3648 static int set_psv_wr(struct ib_sig_domain *domain,
3649                       u32 psv_idx, void **seg, int *size)
3650 {
3651         struct mlx5_seg_set_psv *psv_seg = *seg;
3652
3653         memset(psv_seg, 0, sizeof(*psv_seg));
3654         psv_seg->psv_num = cpu_to_be32(psv_idx);
3655         switch (domain->sig_type) {
3656         case IB_SIG_TYPE_NONE:
3657                 break;
3658         case IB_SIG_TYPE_T10_DIF:
3659                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3660                                                      domain->sig.dif.app_tag);
3661                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3662                 break;
3663         default:
3664                 pr_err("Bad signature type (%d) is given.\n",
3665                        domain->sig_type);
3666                 return -EINVAL;
3667         }
3668
3669         *seg += sizeof(*psv_seg);
3670         *size += sizeof(*psv_seg) / 16;
3671
3672         return 0;
3673 }
3674
3675 static int set_reg_wr(struct mlx5_ib_qp *qp,
3676                       struct ib_reg_wr *wr,
3677                       void **seg, int *size)
3678 {
3679         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3680         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3681
3682         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3683                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3684                              "Invalid IB_SEND_INLINE send flag\n");
3685                 return -EINVAL;
3686         }
3687
3688         set_reg_umr_seg(*seg, mr);
3689         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3690         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3691         if (unlikely((*seg == qp->sq.qend)))
3692                 *seg = mlx5_get_send_wqe(qp, 0);
3693
3694         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3695         *seg += sizeof(struct mlx5_mkey_seg);
3696         *size += sizeof(struct mlx5_mkey_seg) / 16;
3697         if (unlikely((*seg == qp->sq.qend)))
3698                 *seg = mlx5_get_send_wqe(qp, 0);
3699
3700         set_reg_data_seg(*seg, mr, pd);
3701         *seg += sizeof(struct mlx5_wqe_data_seg);
3702         *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3703
3704         return 0;
3705 }
3706
3707 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3708 {
3709         set_linv_umr_seg(*seg);
3710         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3711         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3712         if (unlikely((*seg == qp->sq.qend)))
3713                 *seg = mlx5_get_send_wqe(qp, 0);
3714         set_linv_mkey_seg(*seg);
3715         *seg += sizeof(struct mlx5_mkey_seg);
3716         *size += sizeof(struct mlx5_mkey_seg) / 16;
3717         if (unlikely((*seg == qp->sq.qend)))
3718                 *seg = mlx5_get_send_wqe(qp, 0);
3719 }
3720
3721 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3722 {
3723         __be32 *p = NULL;
3724         int tidx = idx;
3725         int i, j;
3726
3727         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3728         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3729                 if ((i & 0xf) == 0) {
3730                         void *buf = mlx5_get_send_wqe(qp, tidx);
3731                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3732                         p = buf;
3733                         j = 0;
3734                 }
3735                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3736                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3737                          be32_to_cpu(p[j + 3]));
3738         }
3739 }
3740
3741 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3742 {
3743         if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3744                      wr->send_flags & IB_SEND_FENCE))
3745                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3746
3747         if (unlikely(fence)) {
3748                 if (wr->send_flags & IB_SEND_FENCE)
3749                         return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3750                 else
3751                         return fence;
3752         } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3753                 return MLX5_FENCE_MODE_FENCE;
3754         }
3755
3756         return 0;
3757 }
3758
3759 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3760                      struct mlx5_wqe_ctrl_seg **ctrl,
3761                      struct ib_send_wr *wr, unsigned *idx,
3762                      int *size, int nreq)
3763 {
3764         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3765                 return -ENOMEM;
3766
3767         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3768         *seg = mlx5_get_send_wqe(qp, *idx);
3769         *ctrl = *seg;
3770         *(uint32_t *)(*seg + 8) = 0;
3771         (*ctrl)->imm = send_ieth(wr);
3772         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3773                 (wr->send_flags & IB_SEND_SIGNALED ?
3774                  MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3775                 (wr->send_flags & IB_SEND_SOLICITED ?
3776                  MLX5_WQE_CTRL_SOLICITED : 0);
3777
3778         *seg += sizeof(**ctrl);
3779         *size = sizeof(**ctrl) / 16;
3780
3781         return 0;
3782 }
3783
3784 static void finish_wqe(struct mlx5_ib_qp *qp,
3785                        struct mlx5_wqe_ctrl_seg *ctrl,
3786                        u8 size, unsigned idx, u64 wr_id,
3787                        int nreq, u8 fence, u8 next_fence,
3788                        u32 mlx5_opcode)
3789 {
3790         u8 opmod = 0;
3791
3792         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3793                                              mlx5_opcode | ((u32)opmod << 24));
3794         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3795         ctrl->fm_ce_se |= fence;
3796         qp->fm_cache = next_fence;
3797         if (unlikely(qp->wq_sig))
3798                 ctrl->signature = wq_sig(ctrl);
3799
3800         qp->sq.wrid[idx] = wr_id;
3801         qp->sq.w_list[idx].opcode = mlx5_opcode;
3802         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3803         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3804         qp->sq.w_list[idx].next = qp->sq.cur_post;
3805 }
3806
3807
3808 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3809                       struct ib_send_wr **bad_wr)
3810 {
3811         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
3812         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3813         struct mlx5_core_dev *mdev = dev->mdev;
3814         struct mlx5_ib_qp *qp;
3815         struct mlx5_ib_mr *mr;
3816         struct mlx5_wqe_data_seg *dpseg;
3817         struct mlx5_wqe_xrc_seg *xrc;
3818         struct mlx5_bf *bf;
3819         int uninitialized_var(size);
3820         void *qend;
3821         unsigned long flags;
3822         unsigned idx;
3823         int err = 0;
3824         int inl = 0;
3825         int num_sge;
3826         void *seg;
3827         int nreq;
3828         int i;
3829         u8 next_fence = 0;
3830         u8 fence;
3831
3832         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3833                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3834
3835         qp = to_mqp(ibqp);
3836         bf = &qp->bf;
3837         qend = qp->sq.qend;
3838
3839         spin_lock_irqsave(&qp->sq.lock, flags);
3840
3841         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3842                 err = -EIO;
3843                 *bad_wr = wr;
3844                 nreq = 0;
3845                 goto out;
3846         }
3847
3848         for (nreq = 0; wr; nreq++, wr = wr->next) {
3849                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3850                         mlx5_ib_warn(dev, "\n");
3851                         err = -EINVAL;
3852                         *bad_wr = wr;
3853                         goto out;
3854                 }
3855
3856                 fence = qp->fm_cache;
3857                 num_sge = wr->num_sge;
3858                 if (unlikely(num_sge > qp->sq.max_gs)) {
3859                         mlx5_ib_warn(dev, "\n");
3860                         err = -EINVAL;
3861                         *bad_wr = wr;
3862                         goto out;
3863                 }
3864
3865                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3866                 if (err) {
3867                         mlx5_ib_warn(dev, "\n");
3868                         err = -ENOMEM;
3869                         *bad_wr = wr;
3870                         goto out;
3871                 }
3872
3873                 switch (ibqp->qp_type) {
3874                 case IB_QPT_XRC_INI:
3875                         xrc = seg;
3876                         seg += sizeof(*xrc);
3877                         size += sizeof(*xrc) / 16;
3878                         /* fall through */
3879                 case IB_QPT_RC:
3880                         switch (wr->opcode) {
3881                         case IB_WR_RDMA_READ:
3882                         case IB_WR_RDMA_WRITE:
3883                         case IB_WR_RDMA_WRITE_WITH_IMM:
3884                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3885                                               rdma_wr(wr)->rkey);
3886                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
3887                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3888                                 break;
3889
3890                         case IB_WR_ATOMIC_CMP_AND_SWP:
3891                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3892                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3893                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3894                                 err = -ENOSYS;
3895                                 *bad_wr = wr;
3896                                 goto out;
3897
3898                         case IB_WR_LOCAL_INV:
3899                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3900                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3901                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3902                                 set_linv_wr(qp, &seg, &size);
3903                                 num_sge = 0;
3904                                 break;
3905
3906                         case IB_WR_REG_MR:
3907                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3908                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3909                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3910                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3911                                 if (err) {
3912                                         *bad_wr = wr;
3913                                         goto out;
3914                                 }
3915                                 num_sge = 0;
3916                                 break;
3917
3918                         case IB_WR_REG_SIG_MR:
3919                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3920                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3921
3922                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3923                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
3924                                 if (err) {
3925                                         mlx5_ib_warn(dev, "\n");
3926                                         *bad_wr = wr;
3927                                         goto out;
3928                                 }
3929
3930                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3931                                            nreq, get_fence(fence, wr),
3932                                            next_fence, MLX5_OPCODE_UMR);
3933                                 /*
3934                                  * SET_PSV WQEs are not signaled and solicited
3935                                  * on error
3936                                  */
3937                                 wr->send_flags &= ~IB_SEND_SIGNALED;
3938                                 wr->send_flags |= IB_SEND_SOLICITED;
3939                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3940                                                 &idx, &size, nreq);
3941                                 if (err) {
3942                                         mlx5_ib_warn(dev, "\n");
3943                                         err = -ENOMEM;
3944                                         *bad_wr = wr;
3945                                         goto out;
3946                                 }
3947
3948                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3949                                                  mr->sig->psv_memory.psv_idx, &seg,
3950                                                  &size);
3951                                 if (err) {
3952                                         mlx5_ib_warn(dev, "\n");
3953                                         *bad_wr = wr;
3954                                         goto out;
3955                                 }
3956
3957                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3958                                            nreq, get_fence(fence, wr),
3959                                            next_fence, MLX5_OPCODE_SET_PSV);
3960                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3961                                                 &idx, &size, nreq);
3962                                 if (err) {
3963                                         mlx5_ib_warn(dev, "\n");
3964                                         err = -ENOMEM;
3965                                         *bad_wr = wr;
3966                                         goto out;
3967                                 }
3968
3969                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3970                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
3971                                                  mr->sig->psv_wire.psv_idx, &seg,
3972                                                  &size);
3973                                 if (err) {
3974                                         mlx5_ib_warn(dev, "\n");
3975                                         *bad_wr = wr;
3976                                         goto out;
3977                                 }
3978
3979                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3980                                            nreq, get_fence(fence, wr),
3981                                            next_fence, MLX5_OPCODE_SET_PSV);
3982                                 num_sge = 0;
3983                                 goto skip_psv;
3984
3985                         default:
3986                                 break;
3987                         }
3988                         break;
3989
3990                 case IB_QPT_UC:
3991                         switch (wr->opcode) {
3992                         case IB_WR_RDMA_WRITE:
3993                         case IB_WR_RDMA_WRITE_WITH_IMM:
3994                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3995                                               rdma_wr(wr)->rkey);
3996                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
3997                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3998                                 break;
3999
4000                         default:
4001                                 break;
4002                         }
4003                         break;
4004
4005                 case IB_QPT_SMI:
4006                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4007                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4008                                 err = -EPERM;
4009                                 *bad_wr = wr;
4010                                 goto out;
4011                         }
4012                 case MLX5_IB_QPT_HW_GSI:
4013                         set_datagram_seg(seg, wr);
4014                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4015                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4016                         if (unlikely((seg == qend)))
4017                                 seg = mlx5_get_send_wqe(qp, 0);
4018                         break;
4019                 case IB_QPT_UD:
4020                         set_datagram_seg(seg, wr);
4021                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4022                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4023
4024                         if (unlikely((seg == qend)))
4025                                 seg = mlx5_get_send_wqe(qp, 0);
4026
4027                         /* handle qp that supports ud offload */
4028                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4029                                 struct mlx5_wqe_eth_pad *pad;
4030
4031                                 pad = seg;
4032                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4033                                 seg += sizeof(struct mlx5_wqe_eth_pad);
4034                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4035
4036                                 seg = set_eth_seg(seg, wr, qend, qp, &size);
4037
4038                                 if (unlikely((seg == qend)))
4039                                         seg = mlx5_get_send_wqe(qp, 0);
4040                         }
4041                         break;
4042                 case MLX5_IB_QPT_REG_UMR:
4043                         if (wr->opcode != MLX5_IB_WR_UMR) {
4044                                 err = -EINVAL;
4045                                 mlx5_ib_warn(dev, "bad opcode\n");
4046                                 goto out;
4047                         }
4048                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4049                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4050                         set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4051                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4052                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4053                         if (unlikely((seg == qend)))
4054                                 seg = mlx5_get_send_wqe(qp, 0);
4055                         set_reg_mkey_segment(seg, wr);
4056                         seg += sizeof(struct mlx5_mkey_seg);
4057                         size += sizeof(struct mlx5_mkey_seg) / 16;
4058                         if (unlikely((seg == qend)))
4059                                 seg = mlx5_get_send_wqe(qp, 0);
4060                         break;
4061
4062                 default:
4063                         break;
4064                 }
4065
4066                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4067                         int uninitialized_var(sz);
4068
4069                         err = set_data_inl_seg(qp, wr, seg, &sz);
4070                         if (unlikely(err)) {
4071                                 mlx5_ib_warn(dev, "\n");
4072                                 *bad_wr = wr;
4073                                 goto out;
4074                         }
4075                         inl = 1;
4076                         size += sz;
4077                 } else {
4078                         dpseg = seg;
4079                         for (i = 0; i < num_sge; i++) {
4080                                 if (unlikely(dpseg == qend)) {
4081                                         seg = mlx5_get_send_wqe(qp, 0);
4082                                         dpseg = seg;
4083                                 }
4084                                 if (likely(wr->sg_list[i].length)) {
4085                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
4086                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
4087                                         dpseg++;
4088                                 }
4089                         }
4090                 }
4091
4092                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4093                            get_fence(fence, wr), next_fence,
4094                            mlx5_ib_opcode[wr->opcode]);
4095 skip_psv:
4096                 if (0)
4097                         dump_wqe(qp, idx, size);
4098         }
4099
4100 out:
4101         if (likely(nreq)) {
4102                 qp->sq.head += nreq;
4103
4104                 /* Make sure that descriptors are written before
4105                  * updating doorbell record and ringing the doorbell
4106                  */
4107                 wmb();
4108
4109                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4110
4111                 /* Make sure doorbell record is visible to the HCA before
4112                  * we hit doorbell */
4113                 wmb();
4114
4115                 /* currently we support only regular doorbells */
4116                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4117                 /* Make sure doorbells don't leak out of SQ spinlock
4118                  * and reach the HCA out of order.
4119                  */
4120                 mmiowb();
4121                 bf->offset ^= bf->buf_size;
4122         }
4123
4124         spin_unlock_irqrestore(&qp->sq.lock, flags);
4125
4126         return err;
4127 }
4128
4129 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4130 {
4131         sig->signature = calc_sig(sig, size);
4132 }
4133
4134 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4135                       struct ib_recv_wr **bad_wr)
4136 {
4137         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4138         struct mlx5_wqe_data_seg *scat;
4139         struct mlx5_rwqe_sig *sig;
4140         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4141         struct mlx5_core_dev *mdev = dev->mdev;
4142         unsigned long flags;
4143         int err = 0;
4144         int nreq;
4145         int ind;
4146         int i;
4147
4148         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4149                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4150
4151         spin_lock_irqsave(&qp->rq.lock, flags);
4152
4153         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4154                 err = -EIO;
4155                 *bad_wr = wr;
4156                 nreq = 0;
4157                 goto out;
4158         }
4159
4160         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4161
4162         for (nreq = 0; wr; nreq++, wr = wr->next) {
4163                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4164                         err = -ENOMEM;
4165                         *bad_wr = wr;
4166                         goto out;
4167                 }
4168
4169                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4170                         err = -EINVAL;
4171                         *bad_wr = wr;
4172                         goto out;
4173                 }
4174
4175                 scat = get_recv_wqe(qp, ind);
4176                 if (qp->wq_sig)
4177                         scat++;
4178
4179                 for (i = 0; i < wr->num_sge; i++)
4180                         set_data_ptr_seg(scat + i, wr->sg_list + i);
4181
4182                 if (i < qp->rq.max_gs) {
4183                         scat[i].byte_count = 0;
4184                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4185                         scat[i].addr       = 0;
4186                 }
4187
4188                 if (qp->wq_sig) {
4189                         sig = (struct mlx5_rwqe_sig *)scat;
4190                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4191                 }
4192
4193                 qp->rq.wrid[ind] = wr->wr_id;
4194
4195                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4196         }
4197
4198 out:
4199         if (likely(nreq)) {
4200                 qp->rq.head += nreq;
4201
4202                 /* Make sure that descriptors are written before
4203                  * doorbell record.
4204                  */
4205                 wmb();
4206
4207                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4208         }
4209
4210         spin_unlock_irqrestore(&qp->rq.lock, flags);
4211
4212         return err;
4213 }
4214
4215 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4216 {
4217         switch (mlx5_state) {
4218         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4219         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4220         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4221         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4222         case MLX5_QP_STATE_SQ_DRAINING:
4223         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4224         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4225         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4226         default:                     return -1;
4227         }
4228 }
4229
4230 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4231 {
4232         switch (mlx5_mig_state) {
4233         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4234         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4235         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4236         default: return -1;
4237         }
4238 }
4239
4240 static int to_ib_qp_access_flags(int mlx5_flags)
4241 {
4242         int ib_flags = 0;
4243
4244         if (mlx5_flags & MLX5_QP_BIT_RRE)
4245                 ib_flags |= IB_ACCESS_REMOTE_READ;
4246         if (mlx5_flags & MLX5_QP_BIT_RWE)
4247                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4248         if (mlx5_flags & MLX5_QP_BIT_RAE)
4249                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4250
4251         return ib_flags;
4252 }
4253
4254 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4255                             struct rdma_ah_attr *ah_attr,
4256                             struct mlx5_qp_path *path)
4257 {
4258         struct mlx5_core_dev *dev = ibdev->mdev;
4259
4260         memset(ah_attr, 0, sizeof(*ah_attr));
4261
4262         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4263         rdma_ah_set_port_num(ah_attr, path->port);
4264         if (rdma_ah_get_port_num(ah_attr) == 0 ||
4265             rdma_ah_get_port_num(ah_attr) > MLX5_CAP_GEN(dev, num_ports))
4266                 return;
4267
4268         rdma_ah_set_port_num(ah_attr, path->port);
4269         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4270
4271         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4272         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4273         rdma_ah_set_static_rate(ah_attr,
4274                                 path->static_rate ? path->static_rate - 5 : 0);
4275         if (path->grh_mlid & (1 << 7)) {
4276                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4277
4278                 rdma_ah_set_grh(ah_attr, NULL,
4279                                 tc_fl & 0xfffff,
4280                                 path->mgid_index,
4281                                 path->hop_limit,
4282                                 (tc_fl >> 20) & 0xff);
4283                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4284         }
4285 }
4286
4287 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4288                                         struct mlx5_ib_sq *sq,
4289                                         u8 *sq_state)
4290 {
4291         void *out;
4292         void *sqc;
4293         int inlen;
4294         int err;
4295
4296         inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4297         out = mlx5_vzalloc(inlen);
4298         if (!out)
4299                 return -ENOMEM;
4300
4301         err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4302         if (err)
4303                 goto out;
4304
4305         sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4306         *sq_state = MLX5_GET(sqc, sqc, state);
4307         sq->state = *sq_state;
4308
4309 out:
4310         kvfree(out);
4311         return err;
4312 }
4313
4314 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4315                                         struct mlx5_ib_rq *rq,
4316                                         u8 *rq_state)
4317 {
4318         void *out;
4319         void *rqc;
4320         int inlen;
4321         int err;
4322
4323         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4324         out = mlx5_vzalloc(inlen);
4325         if (!out)
4326                 return -ENOMEM;
4327
4328         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4329         if (err)
4330                 goto out;
4331
4332         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4333         *rq_state = MLX5_GET(rqc, rqc, state);
4334         rq->state = *rq_state;
4335
4336 out:
4337         kvfree(out);
4338         return err;
4339 }
4340
4341 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4342                                   struct mlx5_ib_qp *qp, u8 *qp_state)
4343 {
4344         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4345                 [MLX5_RQC_STATE_RST] = {
4346                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4347                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4348                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
4349                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
4350                 },
4351                 [MLX5_RQC_STATE_RDY] = {
4352                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4353                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4354                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
4355                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
4356                 },
4357                 [MLX5_RQC_STATE_ERR] = {
4358                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4359                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4360                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
4361                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
4362                 },
4363                 [MLX5_RQ_STATE_NA] = {
4364                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4365                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4366                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
4367                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
4368                 },
4369         };
4370
4371         *qp_state = sqrq_trans[rq_state][sq_state];
4372
4373         if (*qp_state == MLX5_QP_STATE_BAD) {
4374                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4375                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4376                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4377                 return -EINVAL;
4378         }
4379
4380         if (*qp_state == MLX5_QP_STATE)
4381                 *qp_state = qp->state;
4382
4383         return 0;
4384 }
4385
4386 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4387                                      struct mlx5_ib_qp *qp,
4388                                      u8 *raw_packet_qp_state)
4389 {
4390         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4391         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4392         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4393         int err;
4394         u8 sq_state = MLX5_SQ_STATE_NA;
4395         u8 rq_state = MLX5_RQ_STATE_NA;
4396
4397         if (qp->sq.wqe_cnt) {
4398                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4399                 if (err)
4400                         return err;
4401         }
4402
4403         if (qp->rq.wqe_cnt) {
4404                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4405                 if (err)
4406                         return err;
4407         }
4408
4409         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4410                                       raw_packet_qp_state);
4411 }
4412
4413 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4414                          struct ib_qp_attr *qp_attr)
4415 {
4416         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4417         struct mlx5_qp_context *context;
4418         int mlx5_state;
4419         u32 *outb;
4420         int err = 0;
4421
4422         outb = kzalloc(outlen, GFP_KERNEL);
4423         if (!outb)
4424                 return -ENOMEM;
4425
4426         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4427                                  outlen);
4428         if (err)
4429                 goto out;
4430
4431         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4432         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4433
4434         mlx5_state = be32_to_cpu(context->flags) >> 28;
4435
4436         qp->state                    = to_ib_qp_state(mlx5_state);
4437         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
4438         qp_attr->path_mig_state      =
4439                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4440         qp_attr->qkey                = be32_to_cpu(context->qkey);
4441         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4442         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
4443         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4444         qp_attr->qp_access_flags     =
4445                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4446
4447         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4448                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4449                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4450                 qp_attr->alt_pkey_index =
4451                         be16_to_cpu(context->alt_path.pkey_index);
4452                 qp_attr->alt_port_num   =
4453                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4454         }
4455
4456         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4457         qp_attr->port_num = context->pri_path.port;
4458
4459         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4460         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4461
4462         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4463
4464         qp_attr->max_dest_rd_atomic =
4465                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4466         qp_attr->min_rnr_timer      =
4467                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4468         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
4469         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
4470         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
4471         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
4472
4473 out:
4474         kfree(outb);
4475         return err;
4476 }
4477
4478 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4479                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4480 {
4481         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4482         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4483         int err = 0;
4484         u8 raw_packet_qp_state;
4485
4486         if (ibqp->rwq_ind_tbl)
4487                 return -ENOSYS;
4488
4489         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4490                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4491                                             qp_init_attr);
4492
4493         mutex_lock(&qp->mutex);
4494
4495         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4496                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4497                 if (err)
4498                         goto out;
4499                 qp->state = raw_packet_qp_state;
4500                 qp_attr->port_num = 1;
4501         } else {
4502                 err = query_qp_attr(dev, qp, qp_attr);
4503                 if (err)
4504                         goto out;
4505         }
4506
4507         qp_attr->qp_state            = qp->state;
4508         qp_attr->cur_qp_state        = qp_attr->qp_state;
4509         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4510         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4511
4512         if (!ibqp->uobject) {
4513                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
4514                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4515                 qp_init_attr->qp_context = ibqp->qp_context;
4516         } else {
4517                 qp_attr->cap.max_send_wr  = 0;
4518                 qp_attr->cap.max_send_sge = 0;
4519         }
4520
4521         qp_init_attr->qp_type = ibqp->qp_type;
4522         qp_init_attr->recv_cq = ibqp->recv_cq;
4523         qp_init_attr->send_cq = ibqp->send_cq;
4524         qp_init_attr->srq = ibqp->srq;
4525         qp_attr->cap.max_inline_data = qp->max_inline_data;
4526
4527         qp_init_attr->cap            = qp_attr->cap;
4528
4529         qp_init_attr->create_flags = 0;
4530         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4531                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4532
4533         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4534                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4535         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4536                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4537         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4538                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4539         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4540                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4541
4542         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4543                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4544
4545 out:
4546         mutex_unlock(&qp->mutex);
4547         return err;
4548 }
4549
4550 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4551                                           struct ib_ucontext *context,
4552                                           struct ib_udata *udata)
4553 {
4554         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4555         struct mlx5_ib_xrcd *xrcd;
4556         int err;
4557
4558         if (!MLX5_CAP_GEN(dev->mdev, xrc))
4559                 return ERR_PTR(-ENOSYS);
4560
4561         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4562         if (!xrcd)
4563                 return ERR_PTR(-ENOMEM);
4564
4565         err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4566         if (err) {
4567                 kfree(xrcd);
4568                 return ERR_PTR(-ENOMEM);
4569         }
4570
4571         return &xrcd->ibxrcd;
4572 }
4573
4574 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4575 {
4576         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4577         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4578         int err;
4579
4580         err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4581         if (err) {
4582                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4583                 return err;
4584         }
4585
4586         kfree(xrcd);
4587
4588         return 0;
4589 }
4590
4591 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4592 {
4593         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4594         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4595         struct ib_event event;
4596
4597         if (rwq->ibwq.event_handler) {
4598                 event.device     = rwq->ibwq.device;
4599                 event.element.wq = &rwq->ibwq;
4600                 switch (type) {
4601                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4602                         event.event = IB_EVENT_WQ_FATAL;
4603                         break;
4604                 default:
4605                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4606                         return;
4607                 }
4608
4609                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4610         }
4611 }
4612
4613 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4614                       struct ib_wq_init_attr *init_attr)
4615 {
4616         struct mlx5_ib_dev *dev;
4617         int has_net_offloads;
4618         __be64 *rq_pas0;
4619         void *in;
4620         void *rqc;
4621         void *wq;
4622         int inlen;
4623         int err;
4624
4625         dev = to_mdev(pd->device);
4626
4627         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4628         in = mlx5_vzalloc(inlen);
4629         if (!in)
4630                 return -ENOMEM;
4631
4632         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4633         MLX5_SET(rqc,  rqc, mem_rq_type,
4634                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4635         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4636         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4637         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4638         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4639         wq = MLX5_ADDR_OF(rqc, rqc, wq);
4640         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4641         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4642         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4643         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4644         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4645         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4646         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4647         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4648         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4649         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
4650         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4651                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4652                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4653                         err = -EOPNOTSUPP;
4654                         goto out;
4655                 }
4656         } else {
4657                 MLX5_SET(rqc, rqc, vsd, 1);
4658         }
4659         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4660                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4661                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4662                         err = -EOPNOTSUPP;
4663                         goto out;
4664                 }
4665                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4666         }
4667         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4668         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4669         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4670 out:
4671         kvfree(in);
4672         return err;
4673 }
4674
4675 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4676                             struct ib_wq_init_attr *wq_init_attr,
4677                             struct mlx5_ib_create_wq *ucmd,
4678                             struct mlx5_ib_rwq *rwq)
4679 {
4680         /* Sanity check RQ size before proceeding */
4681         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4682                 return -EINVAL;
4683
4684         if (!ucmd->rq_wqe_count)
4685                 return -EINVAL;
4686
4687         rwq->wqe_count = ucmd->rq_wqe_count;
4688         rwq->wqe_shift = ucmd->rq_wqe_shift;
4689         rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4690         rwq->log_rq_stride = rwq->wqe_shift;
4691         rwq->log_rq_size = ilog2(rwq->wqe_count);
4692         return 0;
4693 }
4694
4695 static int prepare_user_rq(struct ib_pd *pd,
4696                            struct ib_wq_init_attr *init_attr,
4697                            struct ib_udata *udata,
4698                            struct mlx5_ib_rwq *rwq)
4699 {
4700         struct mlx5_ib_dev *dev = to_mdev(pd->device);
4701         struct mlx5_ib_create_wq ucmd = {};
4702         int err;
4703         size_t required_cmd_sz;
4704
4705         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4706         if (udata->inlen < required_cmd_sz) {
4707                 mlx5_ib_dbg(dev, "invalid inlen\n");
4708                 return -EINVAL;
4709         }
4710
4711         if (udata->inlen > sizeof(ucmd) &&
4712             !ib_is_udata_cleared(udata, sizeof(ucmd),
4713                                  udata->inlen - sizeof(ucmd))) {
4714                 mlx5_ib_dbg(dev, "inlen is not supported\n");
4715                 return -EOPNOTSUPP;
4716         }
4717
4718         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4719                 mlx5_ib_dbg(dev, "copy failed\n");
4720                 return -EFAULT;
4721         }
4722
4723         if (ucmd.comp_mask) {
4724                 mlx5_ib_dbg(dev, "invalid comp mask\n");
4725                 return -EOPNOTSUPP;
4726         }
4727
4728         if (ucmd.reserved) {
4729                 mlx5_ib_dbg(dev, "invalid reserved\n");
4730                 return -EOPNOTSUPP;
4731         }
4732
4733         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4734         if (err) {
4735                 mlx5_ib_dbg(dev, "err %d\n", err);
4736                 return err;
4737         }
4738
4739         err = create_user_rq(dev, pd, rwq, &ucmd);
4740         if (err) {
4741                 mlx5_ib_dbg(dev, "err %d\n", err);
4742                 if (err)
4743                         return err;
4744         }
4745
4746         rwq->user_index = ucmd.user_index;
4747         return 0;
4748 }
4749
4750 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4751                                 struct ib_wq_init_attr *init_attr,
4752                                 struct ib_udata *udata)
4753 {
4754         struct mlx5_ib_dev *dev;
4755         struct mlx5_ib_rwq *rwq;
4756         struct mlx5_ib_create_wq_resp resp = {};
4757         size_t min_resp_len;
4758         int err;
4759
4760         if (!udata)
4761                 return ERR_PTR(-ENOSYS);
4762
4763         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4764         if (udata->outlen && udata->outlen < min_resp_len)
4765                 return ERR_PTR(-EINVAL);
4766
4767         dev = to_mdev(pd->device);
4768         switch (init_attr->wq_type) {
4769         case IB_WQT_RQ:
4770                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4771                 if (!rwq)
4772                         return ERR_PTR(-ENOMEM);
4773                 err = prepare_user_rq(pd, init_attr, udata, rwq);
4774                 if (err)
4775                         goto err;
4776                 err = create_rq(rwq, pd, init_attr);
4777                 if (err)
4778                         goto err_user_rq;
4779                 break;
4780         default:
4781                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4782                             init_attr->wq_type);
4783                 return ERR_PTR(-EINVAL);
4784         }
4785
4786         rwq->ibwq.wq_num = rwq->core_qp.qpn;
4787         rwq->ibwq.state = IB_WQS_RESET;
4788         if (udata->outlen) {
4789                 resp.response_length = offsetof(typeof(resp), response_length) +
4790                                 sizeof(resp.response_length);
4791                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4792                 if (err)
4793                         goto err_copy;
4794         }
4795
4796         rwq->core_qp.event = mlx5_ib_wq_event;
4797         rwq->ibwq.event_handler = init_attr->event_handler;
4798         return &rwq->ibwq;
4799
4800 err_copy:
4801         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4802 err_user_rq:
4803         destroy_user_rq(pd, rwq);
4804 err:
4805         kfree(rwq);
4806         return ERR_PTR(err);
4807 }
4808
4809 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4810 {
4811         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4812         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4813
4814         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4815         destroy_user_rq(wq->pd, rwq);
4816         kfree(rwq);
4817
4818         return 0;
4819 }
4820
4821 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4822                                                       struct ib_rwq_ind_table_init_attr *init_attr,
4823                                                       struct ib_udata *udata)
4824 {
4825         struct mlx5_ib_dev *dev = to_mdev(device);
4826         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4827         int sz = 1 << init_attr->log_ind_tbl_size;
4828         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4829         size_t min_resp_len;
4830         int inlen;
4831         int err;
4832         int i;
4833         u32 *in;
4834         void *rqtc;
4835
4836         if (udata->inlen > 0 &&
4837             !ib_is_udata_cleared(udata, 0,
4838                                  udata->inlen))
4839                 return ERR_PTR(-EOPNOTSUPP);
4840
4841         if (init_attr->log_ind_tbl_size >
4842             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4843                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4844                             init_attr->log_ind_tbl_size,
4845                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4846                 return ERR_PTR(-EINVAL);
4847         }
4848
4849         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4850         if (udata->outlen && udata->outlen < min_resp_len)
4851                 return ERR_PTR(-EINVAL);
4852
4853         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4854         if (!rwq_ind_tbl)
4855                 return ERR_PTR(-ENOMEM);
4856
4857         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4858         in = mlx5_vzalloc(inlen);
4859         if (!in) {
4860                 err = -ENOMEM;
4861                 goto err;
4862         }
4863
4864         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4865
4866         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4867         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4868
4869         for (i = 0; i < sz; i++)
4870                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4871
4872         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4873         kvfree(in);
4874
4875         if (err)
4876                 goto err;
4877
4878         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4879         if (udata->outlen) {
4880                 resp.response_length = offsetof(typeof(resp), response_length) +
4881                                         sizeof(resp.response_length);
4882                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4883                 if (err)
4884                         goto err_copy;
4885         }
4886
4887         return &rwq_ind_tbl->ib_rwq_ind_tbl;
4888
4889 err_copy:
4890         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4891 err:
4892         kfree(rwq_ind_tbl);
4893         return ERR_PTR(err);
4894 }
4895
4896 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4897 {
4898         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4899         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4900
4901         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4902
4903         kfree(rwq_ind_tbl);
4904         return 0;
4905 }
4906
4907 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4908                       u32 wq_attr_mask, struct ib_udata *udata)
4909 {
4910         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4911         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4912         struct mlx5_ib_modify_wq ucmd = {};
4913         size_t required_cmd_sz;
4914         int curr_wq_state;
4915         int wq_state;
4916         int inlen;
4917         int err;
4918         void *rqc;
4919         void *in;
4920
4921         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4922         if (udata->inlen < required_cmd_sz)
4923                 return -EINVAL;
4924
4925         if (udata->inlen > sizeof(ucmd) &&
4926             !ib_is_udata_cleared(udata, sizeof(ucmd),
4927                                  udata->inlen - sizeof(ucmd)))
4928                 return -EOPNOTSUPP;
4929
4930         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4931                 return -EFAULT;
4932
4933         if (ucmd.comp_mask || ucmd.reserved)
4934                 return -EOPNOTSUPP;
4935
4936         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4937         in = mlx5_vzalloc(inlen);
4938         if (!in)
4939                 return -ENOMEM;
4940
4941         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4942
4943         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4944                 wq_attr->curr_wq_state : wq->state;
4945         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4946                 wq_attr->wq_state : curr_wq_state;
4947         if (curr_wq_state == IB_WQS_ERR)
4948                 curr_wq_state = MLX5_RQC_STATE_ERR;
4949         if (wq_state == IB_WQS_ERR)
4950                 wq_state = MLX5_RQC_STATE_ERR;
4951         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4952         MLX5_SET(rqc, rqc, state, wq_state);
4953
4954         if (wq_attr_mask & IB_WQ_FLAGS) {
4955                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4956                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
4957                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4958                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
4959                                             "supported\n");
4960                                 err = -EOPNOTSUPP;
4961                                 goto out;
4962                         }
4963                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
4964                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
4965                         MLX5_SET(rqc, rqc, vsd,
4966                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
4967                 }
4968         }
4969
4970         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
4971                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
4972                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
4973                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
4974                         MLX5_SET(rqc, rqc, counter_set_id,
4975                                  dev->port->cnts.set_id);
4976                 } else
4977                         pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
4978                                      dev->ib_dev.name);
4979         }
4980
4981         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
4982         if (!err)
4983                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4984
4985 out:
4986         kvfree(in);
4987         return err;
4988 }