drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <rdma/ib_cache.h>
  34 #include <rdma/ib_pack.h>
  35
  36 #include <linux/mlx4/qp.h>
  37
  38 #include "mlx4_ib.h"
  39 #include "user.h"
  40
  41 enum {
  42         MLX4_IB_ACK_REQ_FREQ    = 8,
  43 };
  44
  45 enum {
  46         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  47         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
  48 };
  49
  50 enum {
  51         /*
  52          * Largest possible UD header: send with GRH and immediate data.
  53          */
  54         MLX4_IB_UD_HEADER_SIZE          = 72
  55 };
  56
  57 struct mlx4_ib_sqp {
  58         struct mlx4_ib_qp       qp;
  59         int                     pkey_index;
  60         u32                     qkey;
  61         u32                     send_psn;
  62         struct ib_ud_header     ud_header;
  63         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  64 };
  65
  66 static const __be32 mlx4_ib_opcode[] = {
  67         [IB_WR_SEND]                    = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
  68         [IB_WR_SEND_WITH_IMM]           = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
  69         [IB_WR_RDMA_WRITE]              = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
  70         [IB_WR_RDMA_WRITE_WITH_IMM]     = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
  71         [IB_WR_RDMA_READ]               = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
  72         [IB_WR_ATOMIC_CMP_AND_SWP]      = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
  73         [IB_WR_ATOMIC_FETCH_AND_ADD]    = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
  74 };
  75
  76 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
  77 {
  78         return container_of(mqp, struct mlx4_ib_sqp, qp);
  79 }
  80
  81 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  82 {
  83         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  84                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
  85 }
  86
  87 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  88 {
  89         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  90                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
  91 }
  92
  93 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
  94 {
  95         if (qp->buf.nbufs == 1)
  96                 return qp->buf.u.direct.buf + offset;
  97         else
  98                 return qp->buf.u.page_list[offset >> PAGE_SHIFT].buf +
  99                         (offset & (PAGE_SIZE - 1));
 100 }
 101
 102 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 103 {
 104         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 105 }
 106
 107 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 108 {
 109         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 110 }
 111
 112 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 113 {
 114         struct ib_event event;
 115         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 116
 117         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 118                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 119
 120         if (ibqp->event_handler) {
 121                 event.device     = ibqp->device;
 122                 event.element.qp = ibqp;
 123                 switch (type) {
 124                 case MLX4_EVENT_TYPE_PATH_MIG:
 125                         event.event = IB_EVENT_PATH_MIG;
 126                         break;
 127                 case MLX4_EVENT_TYPE_COMM_EST:
 128                         event.event = IB_EVENT_COMM_EST;
 129                         break;
 130                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 131                         event.event = IB_EVENT_SQ_DRAINED;
 132                         break;
 133                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 134                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 135                         break;
 136                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 137                         event.event = IB_EVENT_QP_FATAL;
 138                         break;
 139                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 140                         event.event = IB_EVENT_PATH_MIG_ERR;
 141                         break;
 142                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 143                         event.event = IB_EVENT_QP_REQ_ERR;
 144                         break;
 145                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 146                         event.event = IB_EVENT_QP_ACCESS_ERR;
 147                         break;
 148                 default:
 149                         printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
 150                                "on QP %06x\n", type, qp->qpn);
 151                         return;
 152                 }
 153
 154                 ibqp->event_handler(&event, ibqp->qp_context);
 155         }
 156 }
 157
 158 static int send_wqe_overhead(enum ib_qp_type type)
 159 {
 160         /*
 161          * UD WQEs must have a datagram segment.
 162          * RC and UC WQEs might have a remote address segment.
 163          * MLX WQEs need two extra inline data segments (for the UD
 164          * header and space for the ICRC).
 165          */
 166         switch (type) {
 167         case IB_QPT_UD:
 168                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 169                         sizeof (struct mlx4_wqe_datagram_seg);
 170         case IB_QPT_UC:
 171                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 172                         sizeof (struct mlx4_wqe_raddr_seg);
 173         case IB_QPT_RC:
 174                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 175                         sizeof (struct mlx4_wqe_atomic_seg) +
 176                         sizeof (struct mlx4_wqe_raddr_seg);
 177         case IB_QPT_SMI:
 178         case IB_QPT_GSI:
 179                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 180                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 181                               sizeof (struct mlx4_wqe_inline_seg),
 182                               sizeof (struct mlx4_wqe_data_seg)) +
 183                         ALIGN(4 +
 184                               sizeof (struct mlx4_wqe_inline_seg),
 185                               sizeof (struct mlx4_wqe_data_seg));
 186         default:
 187                 return sizeof (struct mlx4_wqe_ctrl_seg);
 188         }
 189 }
 190
 191 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 192                        struct mlx4_ib_qp *qp)
 193 {
 194         /* Sanity check RQ size before proceeding */
 195         if (cap->max_recv_wr  > dev->dev->caps.max_wqes  ||
 196             cap->max_recv_sge > dev->dev->caps.max_rq_sg)
 197                 return -EINVAL;
 198
 199         qp->rq.max = cap->max_recv_wr ? roundup_pow_of_two(cap->max_recv_wr) : 0;
 200
 201         qp->rq.wqe_shift = ilog2(roundup_pow_of_two(cap->max_recv_sge *
 202                                                     sizeof (struct mlx4_wqe_data_seg)));
 203         qp->rq.max_gs    = (1 << qp->rq.wqe_shift) / sizeof (struct mlx4_wqe_data_seg);
 204
 205         cap->max_recv_wr  = qp->rq.max;
 206         cap->max_recv_sge = qp->rq.max_gs;
 207
 208         return 0;
 209 }
 210
 211 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 212                               enum ib_qp_type type, struct mlx4_ib_qp *qp)
 213 {
 214         /* Sanity check SQ size before proceeding */
 215         if (cap->max_send_wr     > dev->dev->caps.max_wqes  ||
 216             cap->max_send_sge    > dev->dev->caps.max_sq_sg ||
 217             cap->max_inline_data + send_wqe_overhead(type) +
 218             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 219                 return -EINVAL;
 220
 221         /*
 222          * For MLX transport we need 2 extra S/G entries:
 223          * one for the header and one for the checksum at the end
 224          */
 225         if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
 226             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 227                 return -EINVAL;
 228
 229         qp->sq.max = cap->max_send_wr ? roundup_pow_of_two(cap->max_send_wr) : 1;
 230
 231         qp->sq.wqe_shift = ilog2(roundup_pow_of_two(max(cap->max_send_sge *
 232                                                         sizeof (struct mlx4_wqe_data_seg),
 233                                                         cap->max_inline_data +
 234                                                         sizeof (struct mlx4_wqe_inline_seg)) +
 235                                                     send_wqe_overhead(type)));
 236         qp->sq.max_gs    = ((1 << qp->sq.wqe_shift) - send_wqe_overhead(type)) /
 237                 sizeof (struct mlx4_wqe_data_seg);
 238
 239         qp->buf_size = (qp->rq.max << qp->rq.wqe_shift) +
 240                 (qp->sq.max << qp->sq.wqe_shift);
 241         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 242                 qp->rq.offset = 0;
 243                 qp->sq.offset = qp->rq.max << qp->rq.wqe_shift;
 244         } else {
 245                 qp->rq.offset = qp->sq.max << qp->sq.wqe_shift;
 246                 qp->sq.offset = 0;
 247         }
 248
 249         cap->max_send_wr     = qp->sq.max;
 250         cap->max_send_sge    = qp->sq.max_gs;
 251         cap->max_inline_data = (1 << qp->sq.wqe_shift) - send_wqe_overhead(type) -
 252                 sizeof (struct mlx4_wqe_inline_seg);
 253
 254         return 0;
 255 }
 256
 257 static int set_user_sq_size(struct mlx4_ib_qp *qp,
 258                             struct mlx4_ib_create_qp *ucmd)
 259 {
 260         qp->sq.max       = 1 << ucmd->log_sq_bb_count;
 261         qp->sq.wqe_shift = ucmd->log_sq_stride;
 262
 263         qp->buf_size = (qp->rq.max << qp->rq.wqe_shift) +
 264                 (qp->sq.max << qp->sq.wqe_shift);
 265
 266         return 0;
 267 }
 268
 269 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 270                             struct ib_qp_init_attr *init_attr,
 271                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
 272 {
 273         struct mlx4_wqe_ctrl_seg *ctrl;
 274         int err;
 275         int i;
 276
 277         mutex_init(&qp->mutex);
 278         spin_lock_init(&qp->sq.lock);
 279         spin_lock_init(&qp->rq.lock);
 280
 281         qp->state        = IB_QPS_RESET;
 282         qp->atomic_rd_en = 0;
 283         qp->resp_depth   = 0;
 284
 285         qp->rq.head         = 0;
 286         qp->rq.tail         = 0;
 287         qp->sq.head         = 0;
 288         qp->sq.tail         = 0;
 289
 290         err = set_rq_size(dev, &init_attr->cap, qp);
 291         if (err)
 292                 goto err;
 293
 294         if (pd->uobject) {
 295                 struct mlx4_ib_create_qp ucmd;
 296
 297                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 298                         err = -EFAULT;
 299                         goto err;
 300                 }
 301
 302                 err = set_user_sq_size(qp, &ucmd);
 303                 if (err)
 304                         goto err;
 305
 306                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 307                                        qp->buf_size, 0);
 308                 if (IS_ERR(qp->umem)) {
 309                         err = PTR_ERR(qp->umem);
 310                         goto err;
 311                 }
 312
 313                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 314                                     ilog2(qp->umem->page_size), &qp->mtt);
 315                 if (err)
 316                         goto err_buf;
 317
 318                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 319                 if (err)
 320                         goto err_mtt;
 321
 322                 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 323                                           ucmd.db_addr, &qp->db);
 324                 if (err)
 325                         goto err_mtt;
 326         } else {
 327                 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
 328                 if (err)
 329                         goto err;
 330
 331                 err = mlx4_ib_db_alloc(dev, &qp->db, 0);
 332                 if (err)
 333                         goto err;
 334
 335                 *qp->db.db = 0;
 336
 337                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 338                         err = -ENOMEM;
 339                         goto err_db;
 340                 }
 341
 342                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 343                                     &qp->mtt);
 344                 if (err)
 345                         goto err_buf;
 346
 347                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 348                 if (err)
 349                         goto err_mtt;
 350
 351                 for (i = 0; i < qp->sq.max; ++i) {
 352                         ctrl = get_send_wqe(qp, i);
 353                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
 354                 }
 355
 356                 qp->sq.wrid  = kmalloc(qp->sq.max * sizeof (u64), GFP_KERNEL);
 357                 qp->rq.wrid  = kmalloc(qp->rq.max * sizeof (u64), GFP_KERNEL);
 358
 359                 if (!qp->sq.wrid || !qp->rq.wrid) {
 360                         err = -ENOMEM;
 361                         goto err_wrid;
 362                 }
 363
 364                 /* We don't support inline sends for kernel QPs (yet) */
 365                 init_attr->cap.max_inline_data = 0;
 366         }
 367
 368         err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
 369         if (err)
 370                 goto err_wrid;
 371
 372         /*
 373          * Hardware wants QPN written in big-endian order (after
 374          * shifting) for send doorbell.  Precompute this value to save
 375          * a little bit when posting sends.
 376          */
 377         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 378
 379         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 380                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 381         else
 382                 qp->sq_signal_bits = 0;
 383
 384         qp->mqp.event = mlx4_ib_qp_event;
 385
 386         return 0;
 387
 388 err_wrid:
 389         if (pd->uobject)
 390                 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 391         else {
 392                 kfree(qp->sq.wrid);
 393                 kfree(qp->rq.wrid);
 394         }
 395
 396 err_mtt:
 397         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 398
 399 err_buf:
 400         if (pd->uobject)
 401                 ib_umem_release(qp->umem);
 402         else
 403                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 404
 405 err_db:
 406         if (!pd->uobject)
 407                 mlx4_ib_db_free(dev, &qp->db);
 408
 409 err:
 410         return err;
 411 }
 412
 413 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 414 {
 415         switch (state) {
 416         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 417         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 418         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 419         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 420         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 421         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 422         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 423         default:                return -1;
 424         }
 425 }
 426
 427 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 428 {
 429         if (send_cq == recv_cq)
 430                 spin_lock_irq(&send_cq->lock);
 431         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 432                 spin_lock_irq(&send_cq->lock);
 433                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 434         } else {
 435                 spin_lock_irq(&recv_cq->lock);
 436                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 437         }
 438 }
 439
 440 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 441 {
 442         if (send_cq == recv_cq)
 443                 spin_unlock_irq(&send_cq->lock);
 444         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 445                 spin_unlock(&recv_cq->lock);
 446                 spin_unlock_irq(&send_cq->lock);
 447         } else {
 448                 spin_unlock(&send_cq->lock);
 449                 spin_unlock_irq(&recv_cq->lock);
 450         }
 451 }
 452
 453 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 454                               int is_user)
 455 {
 456         struct mlx4_ib_cq *send_cq, *recv_cq;
 457
 458         if (qp->state != IB_QPS_RESET)
 459                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 460                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 461                         printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
 462                                qp->mqp.qpn);
 463
 464         send_cq = to_mcq(qp->ibqp.send_cq);
 465         recv_cq = to_mcq(qp->ibqp.recv_cq);
 466
 467         mlx4_ib_lock_cqs(send_cq, recv_cq);
 468
 469         if (!is_user) {
 470                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 471                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 472                 if (send_cq != recv_cq)
 473                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 474         }
 475
 476         mlx4_qp_remove(dev->dev, &qp->mqp);
 477
 478         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 479
 480         mlx4_qp_free(dev->dev, &qp->mqp);
 481         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 482
 483         if (is_user) {
 484                 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
 485                                       &qp->db);
 486                 ib_umem_release(qp->umem);
 487         } else {
 488                 kfree(qp->sq.wrid);
 489                 kfree(qp->rq.wrid);
 490                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 491                 mlx4_ib_db_free(dev, &qp->db);
 492         }
 493 }
 494
 495 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
 496                                 struct ib_qp_init_attr *init_attr,
 497                                 struct ib_udata *udata)
 498 {
 499         struct mlx4_ib_dev *dev = to_mdev(pd->device);
 500         struct mlx4_ib_sqp *sqp;
 501         struct mlx4_ib_qp *qp;
 502         int err;
 503
 504         switch (init_attr->qp_type) {
 505         case IB_QPT_RC:
 506         case IB_QPT_UC:
 507         case IB_QPT_UD:
 508         {
 509                 qp = kmalloc(sizeof *qp, GFP_KERNEL);
 510                 if (!qp)
 511                         return ERR_PTR(-ENOMEM);
 512
 513                 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
 514                 if (err) {
 515                         kfree(qp);
 516                         return ERR_PTR(err);
 517                 }
 518
 519                 qp->ibqp.qp_num = qp->mqp.qpn;
 520
 521                 break;
 522         }
 523         case IB_QPT_SMI:
 524         case IB_QPT_GSI:
 525         {
 526                 /* Userspace is not allowed to create special QPs: */
 527                 if (pd->uobject)
 528                         return ERR_PTR(-EINVAL);
 529
 530                 sqp = kmalloc(sizeof *sqp, GFP_KERNEL);
 531                 if (!sqp)
 532                         return ERR_PTR(-ENOMEM);
 533
 534                 qp = &sqp->qp;
 535
 536                 err = create_qp_common(dev, pd, init_attr, udata,
 537                                        dev->dev->caps.sqp_start +
 538                                        (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
 539                                        init_attr->port_num - 1,
 540                                        qp);
 541                 if (err) {
 542                         kfree(sqp);
 543                         return ERR_PTR(err);
 544                 }
 545
 546                 qp->port        = init_attr->port_num;
 547                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
 548
 549                 break;
 550         }
 551         default:
 552                 /* Don't support raw QPs */
 553                 return ERR_PTR(-EINVAL);
 554         }
 555
 556         return &qp->ibqp;
 557 }
 558
 559 int mlx4_ib_destroy_qp(struct ib_qp *qp)
 560 {
 561         struct mlx4_ib_dev *dev = to_mdev(qp->device);
 562         struct mlx4_ib_qp *mqp = to_mqp(qp);
 563
 564         if (is_qp0(dev, mqp))
 565                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
 566
 567         destroy_qp_common(dev, mqp, !!qp->pd->uobject);
 568
 569         if (is_sqp(dev, mqp))
 570                 kfree(to_msqp(mqp));
 571         else
 572                 kfree(mqp);
 573
 574         return 0;
 575 }
 576
 577 static void init_port(struct mlx4_ib_dev *dev, int port)
 578 {
 579         struct mlx4_init_port_param param;
 580         int err;
 581
 582         memset(&param, 0, sizeof param);
 583
 584         param.port_width_cap = dev->dev->caps.port_width_cap;
 585         param.vl_cap         = dev->dev->caps.vl_cap;
 586         param.mtu            = ib_mtu_enum_to_int(dev->dev->caps.mtu_cap);
 587         param.max_gid        = dev->dev->caps.gid_table_len;
 588         param.max_pkey       = dev->dev->caps.pkey_table_len;
 589
 590         err = mlx4_INIT_PORT(dev->dev, &param, port);
 591         if (err)
 592                 printk(KERN_WARNING "INIT_PORT failed, return code %d.\n", err);
 593 }
 594
 595 static int to_mlx4_st(enum ib_qp_type type)
 596 {
 597         switch (type) {
 598         case IB_QPT_RC:         return MLX4_QP_ST_RC;
 599         case IB_QPT_UC:         return MLX4_QP_ST_UC;
 600         case IB_QPT_UD:         return MLX4_QP_ST_UD;
 601         case IB_QPT_SMI:
 602         case IB_QPT_GSI:        return MLX4_QP_ST_MLX;
 603         default:                return -1;
 604         }
 605 }
 606
 607 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
 608                                    int attr_mask)
 609 {
 610         u8 dest_rd_atomic;
 611         u32 access_flags;
 612         u32 hw_access_flags = 0;
 613
 614         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 615                 dest_rd_atomic = attr->max_dest_rd_atomic;
 616         else
 617                 dest_rd_atomic = qp->resp_depth;
 618
 619         if (attr_mask & IB_QP_ACCESS_FLAGS)
 620                 access_flags = attr->qp_access_flags;
 621         else
 622                 access_flags = qp->atomic_rd_en;
 623
 624         if (!dest_rd_atomic)
 625                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 626
 627         if (access_flags & IB_ACCESS_REMOTE_READ)
 628                 hw_access_flags |= MLX4_QP_BIT_RRE;
 629         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 630                 hw_access_flags |= MLX4_QP_BIT_RAE;
 631         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 632                 hw_access_flags |= MLX4_QP_BIT_RWE;
 633
 634         return cpu_to_be32(hw_access_flags);
 635 }
 636
 637 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
 638                             int attr_mask)
 639 {
 640         if (attr_mask & IB_QP_PKEY_INDEX)
 641                 sqp->pkey_index = attr->pkey_index;
 642         if (attr_mask & IB_QP_QKEY)
 643                 sqp->qkey = attr->qkey;
 644         if (attr_mask & IB_QP_SQ_PSN)
 645                 sqp->send_psn = attr->sq_psn;
 646 }
 647
 648 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
 649 {
 650         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
 651 }
 652
 653 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
 654                          struct mlx4_qp_path *path, u8 port)
 655 {
 656         path->grh_mylmc     = ah->src_path_bits & 0x7f;
 657         path->rlid          = cpu_to_be16(ah->dlid);
 658         if (ah->static_rate) {
 659                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
 660                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
 661                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
 662                         --path->static_rate;
 663         } else
 664                 path->static_rate = 0;
 665         path->counter_index = 0xff;
 666
 667         if (ah->ah_flags & IB_AH_GRH) {
 668                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len) {
 669                         printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
 670                                ah->grh.sgid_index, dev->dev->caps.gid_table_len - 1);
 671                         return -1;
 672                 }
 673
 674                 path->grh_mylmc |= 1 << 7;
 675                 path->mgid_index = ah->grh.sgid_index;
 676                 path->hop_limit  = ah->grh.hop_limit;
 677                 path->tclass_flowlabel =
 678                         cpu_to_be32((ah->grh.traffic_class << 20) |
 679                                     (ah->grh.flow_label));
 680                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 681         }
 682
 683         path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
 684                 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
 685
 686         return 0;
 687 }
 688
 689 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
 690                                const struct ib_qp_attr *attr, int attr_mask,
 691                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
 692 {
 693         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
 694         struct mlx4_ib_qp *qp = to_mqp(ibqp);
 695         struct mlx4_qp_context *context;
 696         enum mlx4_qp_optpar optpar = 0;
 697         int sqd_event;
 698         int err = -EINVAL;
 699
 700         context = kzalloc(sizeof *context, GFP_KERNEL);
 701         if (!context)
 702                 return -ENOMEM;
 703
 704         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
 705                                      (to_mlx4_st(ibqp->qp_type) << 16));
 706         context->flags     |= cpu_to_be32(1 << 8); /* DE? */
 707
 708         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 709                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 710         else {
 711                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
 712                 switch (attr->path_mig_state) {
 713                 case IB_MIG_MIGRATED:
 714                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 715                         break;
 716                 case IB_MIG_REARM:
 717                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
 718                         break;
 719                 case IB_MIG_ARMED:
 720                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
 721                         break;
 722                 }
 723         }
 724
 725         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
 726             ibqp->qp_type == IB_QPT_UD)
 727                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
 728         else if (attr_mask & IB_QP_PATH_MTU) {
 729                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
 730                         printk(KERN_ERR "path MTU (%u) is invalid\n",
 731                                attr->path_mtu);
 732                         return -EINVAL;
 733                 }
 734                 context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 735         }
 736
 737         if (qp->rq.max)
 738                 context->rq_size_stride = ilog2(qp->rq.max) << 3;
 739         context->rq_size_stride |= qp->rq.wqe_shift - 4;
 740
 741         if (qp->sq.max)
 742                 context->sq_size_stride = ilog2(qp->sq.max) << 3;
 743         context->sq_size_stride |= qp->sq.wqe_shift - 4;
 744
 745         if (qp->ibqp.uobject)
 746                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
 747         else
 748                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
 749
 750         if (attr_mask & IB_QP_DEST_QPN)
 751                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 752
 753         if (attr_mask & IB_QP_PORT) {
 754                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
 755                     !(attr_mask & IB_QP_AV)) {
 756                         mlx4_set_sched(&context->pri_path, attr->port_num);
 757                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
 758                 }
 759         }
 760
 761         if (attr_mask & IB_QP_PKEY_INDEX) {
 762                 context->pri_path.pkey_index = attr->pkey_index;
 763                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
 764         }
 765
 766         if (attr_mask & IB_QP_RNR_RETRY) {
 767                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
 768                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
 769         }
 770
 771         if (attr_mask & IB_QP_AV) {
 772                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
 773                                   attr_mask & IB_QP_PORT ? attr->port_num : qp->port)) {
 774                         err = -EINVAL;
 775                         goto out;
 776                 }
 777
 778                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
 779                            MLX4_QP_OPTPAR_SCHED_QUEUE);
 780         }
 781
 782         if (attr_mask & IB_QP_TIMEOUT) {
 783                 context->pri_path.ackto = attr->timeout << 3;
 784                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
 785         }
 786
 787         if (attr_mask & IB_QP_ALT_PATH) {
 788                 if (attr->alt_pkey_index >= dev->dev->caps.pkey_table_len)
 789                         return -EINVAL;
 790
 791                 if (attr->alt_port_num == 0 ||
 792                     attr->alt_port_num > dev->dev->caps.num_ports)
 793                         return -EINVAL;
 794
 795                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
 796                                   attr->alt_port_num))
 797                         return -EINVAL;
 798
 799                 context->alt_path.pkey_index = attr->alt_pkey_index;
 800                 context->alt_path.ackto = attr->alt_timeout << 3;
 801                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
 802         }
 803
 804         context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
 805         context->params1    = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
 806         if (attr_mask & IB_QP_RETRY_CNT) {
 807                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 808                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
 809         }
 810
 811         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 812                 if (attr->max_rd_atomic)
 813                         context->params1 |=
 814                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 815                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
 816         }
 817
 818         if (attr_mask & IB_QP_SQ_PSN)
 819                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
 820
 821         context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
 822
 823         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 824                 if (attr->max_dest_rd_atomic)
 825                         context->params2 |=
 826                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 827                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
 828         }
 829
 830         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 831                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
 832                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
 833         }
 834
 835         if (ibqp->srq)
 836                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
 837
 838         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 839                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 840                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
 841         }
 842         if (attr_mask & IB_QP_RQ_PSN)
 843                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 844
 845         context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
 846
 847         if (attr_mask & IB_QP_QKEY) {
 848                 context->qkey = cpu_to_be32(attr->qkey);
 849                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
 850         }
 851
 852         if (ibqp->srq)
 853                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
 854
 855         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
 856                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
 857
 858         if (cur_state == IB_QPS_INIT &&
 859             new_state == IB_QPS_RTR  &&
 860             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
 861              ibqp->qp_type == IB_QPT_UD)) {
 862                 context->pri_path.sched_queue = (qp->port - 1) << 6;
 863                 if (is_qp0(dev, qp))
 864                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
 865                 else
 866                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
 867         }
 868
 869         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 870             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
 871                 sqd_event = 1;
 872         else
 873                 sqd_event = 0;
 874
 875         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
 876                              to_mlx4_state(new_state), context, optpar,
 877                              sqd_event, &qp->mqp);
 878         if (err)
 879                 goto out;
 880
 881         qp->state = new_state;
 882
 883         if (attr_mask & IB_QP_ACCESS_FLAGS)
 884                 qp->atomic_rd_en = attr->qp_access_flags;
 885         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 886                 qp->resp_depth = attr->max_dest_rd_atomic;
 887         if (attr_mask & IB_QP_PORT)
 888                 qp->port = attr->port_num;
 889         if (attr_mask & IB_QP_ALT_PATH)
 890                 qp->alt_port = attr->alt_port_num;
 891
 892         if (is_sqp(dev, qp))
 893                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
 894
 895         /*
 896          * If we moved QP0 to RTR, bring the IB link up; if we moved
 897          * QP0 to RESET or ERROR, bring the link back down.
 898          */
 899         if (is_qp0(dev, qp)) {
 900                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
 901                         init_port(dev, qp->port);
 902
 903                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
 904                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
 905                         mlx4_CLOSE_PORT(dev->dev, qp->port);
 906         }
 907
 908         /*
 909          * If we moved a kernel QP to RESET, clean up all old CQ
 910          * entries and reinitialize the QP.
 911          */
 912         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
 913                 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
 914                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
 915                 if (ibqp->send_cq != ibqp->recv_cq)
 916                         mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
 917
 918                 qp->rq.head = 0;
 919                 qp->rq.tail = 0;
 920                 qp->sq.head = 0;
 921                 qp->sq.tail = 0;
 922                 *qp->db.db  = 0;
 923         }
 924
 925 out:
 926         kfree(context);
 927         return err;
 928 }
 929
 930 static const struct ib_qp_attr mlx4_ib_qp_attr = { .port_num = 1 };
 931 static const int mlx4_ib_qp_attr_mask_table[IB_QPT_UD + 1] = {
 932                 [IB_QPT_UD]  = (IB_QP_PKEY_INDEX                |
 933                                 IB_QP_PORT                      |
 934                                 IB_QP_QKEY),
 935                 [IB_QPT_UC]  = (IB_QP_PKEY_INDEX                |
 936                                 IB_QP_PORT                      |
 937                                 IB_QP_ACCESS_FLAGS),
 938                 [IB_QPT_RC]  = (IB_QP_PKEY_INDEX                |
 939                                 IB_QP_PORT                      |
 940                                 IB_QP_ACCESS_FLAGS),
 941                 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX                |
 942                                 IB_QP_QKEY),
 943                 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX                |
 944                                 IB_QP_QKEY),
 945 };
 946
 947 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 948                       int attr_mask, struct ib_udata *udata)
 949 {
 950         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
 951         struct mlx4_ib_qp *qp = to_mqp(ibqp);
 952         enum ib_qp_state cur_state, new_state;
 953         int err = -EINVAL;
 954
 955         mutex_lock(&qp->mutex);
 956
 957         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
 958         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
 959
 960         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
 961                 goto out;
 962
 963         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 964              attr->pkey_index >= dev->dev->caps.pkey_table_len) {
 965                 goto out;
 966         }
 967
 968         if ((attr_mask & IB_QP_PORT) &&
 969             (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
 970                 goto out;
 971         }
 972
 973         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 974             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
 975                 goto out;
 976         }
 977
 978         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 979             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
 980                 goto out;
 981         }
 982
 983         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
 984                 err = 0;
 985                 goto out;
 986         }
 987
 988         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
 989                 err = __mlx4_ib_modify_qp(ibqp, &mlx4_ib_qp_attr,
 990                                           mlx4_ib_qp_attr_mask_table[ibqp->qp_type],
 991                                           IB_QPS_RESET, IB_QPS_INIT);
 992                 if (err)
 993                         goto out;
 994                 cur_state = IB_QPS_INIT;
 995         }
 996
 997         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
 998
 999 out:
1000         mutex_unlock(&qp->mutex);
1001         return err;
1002 }
1003
1004 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1005                             void *wqe)
1006 {
1007         struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1008         struct mlx4_wqe_mlx_seg *mlx = wqe;
1009         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1010         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1011         u16 pkey;
1012         int send_size;
1013         int header_size;
1014         int i;
1015
1016         send_size = 0;
1017         for (i = 0; i < wr->num_sge; ++i)
1018                 send_size += wr->sg_list[i].length;
1019
1020         ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1021
1022         sqp->ud_header.lrh.service_level   =
1023                 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1024         sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1025         sqp->ud_header.lrh.source_lid      = cpu_to_be16(ah->av.g_slid & 0x7f);
1026         if (mlx4_ib_ah_grh_present(ah)) {
1027                 sqp->ud_header.grh.traffic_class =
1028                         (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1029                 sqp->ud_header.grh.flow_label    =
1030                         ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1031                 sqp->ud_header.grh.hop_limit     = ah->av.hop_limit;
1032                 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1033                                   ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1034                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1035                        ah->av.dgid, 16);
1036         }
1037
1038         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1039         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1040                                   (sqp->ud_header.lrh.destination_lid ==
1041                                    IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1042                                   (sqp->ud_header.lrh.service_level << 8));
1043         mlx->rlid   = sqp->ud_header.lrh.destination_lid;
1044
1045         switch (wr->opcode) {
1046         case IB_WR_SEND:
1047                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1048                 sqp->ud_header.immediate_present = 0;
1049                 break;
1050         case IB_WR_SEND_WITH_IMM:
1051                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1052                 sqp->ud_header.immediate_present = 1;
1053                 sqp->ud_header.immediate_data    = wr->imm_data;
1054                 break;
1055         default:
1056                 return -EINVAL;
1057         }
1058
1059         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1060         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1061                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1062         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1063         if (!sqp->qp.ibqp.qp_num)
1064                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1065         else
1066                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1067         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1068         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1069         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1070         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1071                                                sqp->qkey : wr->wr.ud.remote_qkey);
1072         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1073
1074         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1075
1076         if (0) {
1077                 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1078                 for (i = 0; i < header_size / 4; ++i) {
1079                         if (i % 8 == 0)
1080                                 printk("  [%02x] ", i * 4);
1081                         printk(" %08x",
1082                                be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1083                         if ((i + 1) % 8 == 0)
1084                                 printk("\n");
1085                 }
1086                 printk("\n");
1087         }
1088
1089         inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1090         memcpy(inl + 1, sqp->header_buf, header_size);
1091
1092         return ALIGN(sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1093 }
1094
1095 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1096 {
1097         unsigned cur;
1098         struct mlx4_ib_cq *cq;
1099
1100         cur = wq->head - wq->tail;
1101         if (likely(cur + nreq < wq->max))
1102                 return 0;
1103
1104         cq = to_mcq(ib_cq);
1105         spin_lock(&cq->lock);
1106         cur = wq->head - wq->tail;
1107         spin_unlock(&cq->lock);
1108
1109         return cur + nreq >= wq->max;
1110 }
1111
1112 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1113                       struct ib_send_wr **bad_wr)
1114 {
1115         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1116         void *wqe;
1117         struct mlx4_wqe_ctrl_seg *ctrl;
1118         unsigned long flags;
1119         int nreq;
1120         int err = 0;
1121         int ind;
1122         int size;
1123         int i;
1124
1125         spin_lock_irqsave(&qp->rq.lock, flags);
1126
1127         ind = qp->sq.head;
1128
1129         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1130                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1131                         err = -ENOMEM;
1132                         *bad_wr = wr;
1133                         goto out;
1134                 }
1135
1136                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1137                         err = -EINVAL;
1138                         *bad_wr = wr;
1139                         goto out;
1140                 }
1141
1142                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.max - 1));
1143                 qp->sq.wrid[ind & (qp->sq.max - 1)] = wr->wr_id;
1144
1145                 ctrl->srcrb_flags =
1146                         (wr->send_flags & IB_SEND_SIGNALED ?
1147                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1148                         (wr->send_flags & IB_SEND_SOLICITED ?
1149                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1150                         qp->sq_signal_bits;
1151
1152                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1153                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1154                         ctrl->imm = wr->imm_data;
1155                 else
1156                         ctrl->imm = 0;
1157
1158                 wqe += sizeof *ctrl;
1159                 size = sizeof *ctrl / 16;
1160
1161                 switch (ibqp->qp_type) {
1162                 case IB_QPT_RC:
1163                 case IB_QPT_UC:
1164                         switch (wr->opcode) {
1165                         case IB_WR_ATOMIC_CMP_AND_SWP:
1166                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1167                                 ((struct mlx4_wqe_raddr_seg *) wqe)->raddr =
1168                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1169                                 ((struct mlx4_wqe_raddr_seg *) wqe)->rkey =
1170                                         cpu_to_be32(wr->wr.atomic.rkey);
1171                                 ((struct mlx4_wqe_raddr_seg *) wqe)->reserved = 0;
1172
1173                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1174
1175                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1176                                         ((struct mlx4_wqe_atomic_seg *) wqe)->swap_add =
1177                                                 cpu_to_be64(wr->wr.atomic.swap);
1178                                         ((struct mlx4_wqe_atomic_seg *) wqe)->compare =
1179                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1180                                 } else {
1181                                         ((struct mlx4_wqe_atomic_seg *) wqe)->swap_add =
1182                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1183                                         ((struct mlx4_wqe_atomic_seg *) wqe)->compare = 0;
1184                                 }
1185
1186                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
1187                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1188                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1189
1190                                 break;
1191
1192                         case IB_WR_RDMA_READ:
1193                         case IB_WR_RDMA_WRITE:
1194                         case IB_WR_RDMA_WRITE_WITH_IMM:
1195                                 ((struct mlx4_wqe_raddr_seg *) wqe)->raddr =
1196                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1197                                 ((struct mlx4_wqe_raddr_seg *) wqe)->rkey =
1198                                         cpu_to_be32(wr->wr.rdma.rkey);
1199                                 ((struct mlx4_wqe_raddr_seg *) wqe)->reserved = 0;
1200
1201                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1202                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1203
1204                                 break;
1205
1206                         default:
1207                                 /* No extra segments required for sends */
1208                                 break;
1209                         }
1210                         break;
1211
1212                 case IB_QPT_UD:
1213                         memcpy(((struct mlx4_wqe_datagram_seg *) wqe)->av,
1214                                &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1215                         ((struct mlx4_wqe_datagram_seg *) wqe)->dqpn =
1216                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1217                         ((struct mlx4_wqe_datagram_seg *) wqe)->qkey =
1218                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1219
1220                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
1221                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1222                         break;
1223
1224                 case IB_QPT_SMI:
1225                 case IB_QPT_GSI:
1226                         err = build_mlx_header(to_msqp(qp), wr, ctrl);
1227                         if (err < 0) {
1228                                 *bad_wr = wr;
1229                                 goto out;
1230                         }
1231                         wqe  += err;
1232                         size += err / 16;
1233
1234                         err = 0;
1235                         break;
1236
1237                 default:
1238                         break;
1239                 }
1240
1241                 for (i = 0; i < wr->num_sge; ++i) {
1242                         ((struct mlx4_wqe_data_seg *) wqe)->byte_count =
1243                                 cpu_to_be32(wr->sg_list[i].length);
1244                         ((struct mlx4_wqe_data_seg *) wqe)->lkey =
1245                                 cpu_to_be32(wr->sg_list[i].lkey);
1246                         ((struct mlx4_wqe_data_seg *) wqe)->addr =
1247                                 cpu_to_be64(wr->sg_list[i].addr);
1248
1249                         wqe  += sizeof (struct mlx4_wqe_data_seg);
1250                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1251                 }
1252
1253                 /* Add one more inline data segment for ICRC for MLX sends */
1254                 if (qp->ibqp.qp_type == IB_QPT_SMI || qp->ibqp.qp_type == IB_QPT_GSI) {
1255                         ((struct mlx4_wqe_inline_seg *) wqe)->byte_count =
1256                                 cpu_to_be32((1 << 31) | 4);
1257                         ((u32 *) wqe)[1] = 0;
1258                         wqe  += sizeof (struct mlx4_wqe_data_seg);
1259                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1260                 }
1261
1262                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1263                                     MLX4_WQE_CTRL_FENCE : 0) | size;
1264
1265                 /*
1266                  * Make sure descriptor is fully written before
1267                  * setting ownership bit (because HW can start
1268                  * executing as soon as we do).
1269                  */
1270                 wmb();
1271
1272                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1273                         err = -EINVAL;
1274                         goto out;
1275                 }
1276
1277                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1278                         (ind & qp->sq.max ? cpu_to_be32(1 << 31) : 0);
1279
1280                 ++ind;
1281         }
1282
1283 out:
1284         if (likely(nreq)) {
1285                 qp->sq.head += nreq;
1286
1287                 /*
1288                  * Make sure that descriptors are written before
1289                  * doorbell record.
1290                  */
1291                 wmb();
1292
1293                 writel(qp->doorbell_qpn,
1294                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1295
1296                 /*
1297                  * Make sure doorbells don't leak out of SQ spinlock
1298                  * and reach the HCA out of order.
1299                  */
1300                 mmiowb();
1301         }
1302
1303         spin_unlock_irqrestore(&qp->rq.lock, flags);
1304
1305         return err;
1306 }
1307
1308 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1309                       struct ib_recv_wr **bad_wr)
1310 {
1311         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1312         struct mlx4_wqe_data_seg *scat;
1313         unsigned long flags;
1314         int err = 0;
1315         int nreq;
1316         int ind;
1317         int i;
1318
1319         spin_lock_irqsave(&qp->rq.lock, flags);
1320
1321         ind = qp->rq.head & (qp->rq.max - 1);
1322
1323         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1324                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1325                         err = -ENOMEM;
1326                         *bad_wr = wr;
1327                         goto out;
1328                 }
1329
1330                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1331                         err = -EINVAL;
1332                         *bad_wr = wr;
1333                         goto out;
1334                 }
1335
1336                 scat = get_recv_wqe(qp, ind);
1337
1338                 for (i = 0; i < wr->num_sge; ++i) {
1339                         scat[i].byte_count = cpu_to_be32(wr->sg_list[i].length);
1340                         scat[i].lkey       = cpu_to_be32(wr->sg_list[i].lkey);
1341                         scat[i].addr       = cpu_to_be64(wr->sg_list[i].addr);
1342                 }
1343
1344                 if (i < qp->rq.max_gs) {
1345                         scat[i].byte_count = 0;
1346                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
1347                         scat[i].addr       = 0;
1348                 }
1349
1350                 qp->rq.wrid[ind] = wr->wr_id;
1351
1352                 ind = (ind + 1) & (qp->rq.max - 1);
1353         }
1354
1355 out:
1356         if (likely(nreq)) {
1357                 qp->rq.head += nreq;
1358
1359                 /*
1360                  * Make sure that descriptors are written before
1361                  * doorbell record.
1362                  */
1363                 wmb();
1364
1365                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1366         }
1367
1368         spin_unlock_irqrestore(&qp->rq.lock, flags);
1369
1370         return err;
1371 }