drivers/infiniband/hw/i40iw/i40iw_type.h

   1 /*******************************************************************************
   2 *
   3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenFabrics.org BSD license below:
  10 *
  11 *   Redistribution and use in source and binary forms, with or
  12 *   without modification, are permitted provided that the following
  13 *   conditions are met:
  14 *
  15 *    - Redistributions of source code must retain the above
  16 *       copyright notice, this list of conditions and the following
  17 *       disclaimer.
  18 *
  19 *    - Redistributions in binary form must reproduce the above
  20 *       copyright notice, this list of conditions and the following
  21 *       disclaimer in the documentation and/or other materials
  22 *       provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 *
  33 *******************************************************************************/
  34
  35 #ifndef I40IW_TYPE_H
  36 #define I40IW_TYPE_H
  37 #include "i40iw_user.h"
  38 #include "i40iw_hmc.h"
  39 #include "i40iw_vf.h"
  40 #include "i40iw_virtchnl.h"
  41
  42 struct i40iw_cqp_sq_wqe {
  43         u64 buf[I40IW_CQP_WQE_SIZE];
  44 };
  45
  46 struct i40iw_sc_aeqe {
  47         u64 buf[I40IW_AEQE_SIZE];
  48 };
  49
  50 struct i40iw_ceqe {
  51         u64 buf[I40IW_CEQE_SIZE];
  52 };
  53
  54 struct i40iw_cqp_ctx {
  55         u64 buf[I40IW_CQP_CTX_SIZE];
  56 };
  57
  58 struct i40iw_cq_shadow_area {
  59         u64 buf[I40IW_SHADOW_AREA_SIZE];
  60 };
  61
  62 struct i40iw_sc_dev;
  63 struct i40iw_hmc_info;
  64 struct i40iw_vsi_pestat;
  65
  66 struct i40iw_cqp_ops;
  67 struct i40iw_ccq_ops;
  68 struct i40iw_ceq_ops;
  69 struct i40iw_aeq_ops;
  70 struct i40iw_mr_ops;
  71 struct i40iw_cqp_misc_ops;
  72 struct i40iw_pd_ops;
  73 struct i40iw_priv_qp_ops;
  74 struct i40iw_priv_cq_ops;
  75 struct i40iw_hmc_ops;
  76
  77 enum i40iw_page_size {
  78         I40IW_PAGE_SIZE_4K,
  79         I40IW_PAGE_SIZE_2M
  80 };
  81
  82 enum i40iw_resource_indicator_type {
  83         I40IW_RSRC_INDICATOR_TYPE_ADAPTER = 0,
  84         I40IW_RSRC_INDICATOR_TYPE_CQ,
  85         I40IW_RSRC_INDICATOR_TYPE_QP,
  86         I40IW_RSRC_INDICATOR_TYPE_SRQ
  87 };
  88
  89 enum i40iw_hdrct_flags {
  90         DDP_LEN_FLAG = 0x80,
  91         DDP_HDR_FLAG = 0x40,
  92         RDMA_HDR_FLAG = 0x20
  93 };
  94
  95 enum i40iw_term_layers {
  96         LAYER_RDMA = 0,
  97         LAYER_DDP = 1,
  98         LAYER_MPA = 2
  99 };
 100
 101 enum i40iw_term_error_types {
 102         RDMAP_REMOTE_PROT = 1,
 103         RDMAP_REMOTE_OP = 2,
 104         DDP_CATASTROPHIC = 0,
 105         DDP_TAGGED_BUFFER = 1,
 106         DDP_UNTAGGED_BUFFER = 2,
 107         DDP_LLP = 3
 108 };
 109
 110 enum i40iw_term_rdma_errors {
 111         RDMAP_INV_STAG = 0x00,
 112         RDMAP_INV_BOUNDS = 0x01,
 113         RDMAP_ACCESS = 0x02,
 114         RDMAP_UNASSOC_STAG = 0x03,
 115         RDMAP_TO_WRAP = 0x04,
 116         RDMAP_INV_RDMAP_VER = 0x05,
 117         RDMAP_UNEXPECTED_OP = 0x06,
 118         RDMAP_CATASTROPHIC_LOCAL = 0x07,
 119         RDMAP_CATASTROPHIC_GLOBAL = 0x08,
 120         RDMAP_CANT_INV_STAG = 0x09,
 121         RDMAP_UNSPECIFIED = 0xff
 122 };
 123
 124 enum i40iw_term_ddp_errors {
 125         DDP_CATASTROPHIC_LOCAL = 0x00,
 126         DDP_TAGGED_INV_STAG = 0x00,
 127         DDP_TAGGED_BOUNDS = 0x01,
 128         DDP_TAGGED_UNASSOC_STAG = 0x02,
 129         DDP_TAGGED_TO_WRAP = 0x03,
 130         DDP_TAGGED_INV_DDP_VER = 0x04,
 131         DDP_UNTAGGED_INV_QN = 0x01,
 132         DDP_UNTAGGED_INV_MSN_NO_BUF = 0x02,
 133         DDP_UNTAGGED_INV_MSN_RANGE = 0x03,
 134         DDP_UNTAGGED_INV_MO = 0x04,
 135         DDP_UNTAGGED_INV_TOO_LONG = 0x05,
 136         DDP_UNTAGGED_INV_DDP_VER = 0x06
 137 };
 138
 139 enum i40iw_term_mpa_errors {
 140         MPA_CLOSED = 0x01,
 141         MPA_CRC = 0x02,
 142         MPA_MARKER = 0x03,
 143         MPA_REQ_RSP = 0x04,
 144 };
 145
 146 enum i40iw_flush_opcode {
 147         FLUSH_INVALID = 0,
 148         FLUSH_PROT_ERR,
 149         FLUSH_REM_ACCESS_ERR,
 150         FLUSH_LOC_QP_OP_ERR,
 151         FLUSH_REM_OP_ERR,
 152         FLUSH_LOC_LEN_ERR,
 153         FLUSH_GENERAL_ERR,
 154         FLUSH_FATAL_ERR
 155 };
 156
 157 enum i40iw_term_eventtypes {
 158         TERM_EVENT_QP_FATAL,
 159         TERM_EVENT_QP_ACCESS_ERR
 160 };
 161
 162 struct i40iw_terminate_hdr {
 163         u8 layer_etype;
 164         u8 error_code;
 165         u8 hdrct;
 166         u8 rsvd;
 167 };
 168
 169 enum i40iw_debug_flag {
 170         I40IW_DEBUG_NONE        = 0x00000000,
 171         I40IW_DEBUG_ERR         = 0x00000001,
 172         I40IW_DEBUG_INIT        = 0x00000002,
 173         I40IW_DEBUG_DEV         = 0x00000004,
 174         I40IW_DEBUG_CM          = 0x00000008,
 175         I40IW_DEBUG_VERBS       = 0x00000010,
 176         I40IW_DEBUG_PUDA        = 0x00000020,
 177         I40IW_DEBUG_ILQ         = 0x00000040,
 178         I40IW_DEBUG_IEQ         = 0x00000080,
 179         I40IW_DEBUG_QP          = 0x00000100,
 180         I40IW_DEBUG_CQ          = 0x00000200,
 181         I40IW_DEBUG_MR          = 0x00000400,
 182         I40IW_DEBUG_PBLE        = 0x00000800,
 183         I40IW_DEBUG_WQE         = 0x00001000,
 184         I40IW_DEBUG_AEQ         = 0x00002000,
 185         I40IW_DEBUG_CQP         = 0x00004000,
 186         I40IW_DEBUG_HMC         = 0x00008000,
 187         I40IW_DEBUG_USER        = 0x00010000,
 188         I40IW_DEBUG_VIRT        = 0x00020000,
 189         I40IW_DEBUG_DCB         = 0x00040000,
 190         I40IW_DEBUG_CQE         = 0x00800000,
 191         I40IW_DEBUG_ALL         = 0xFFFFFFFF
 192 };
 193
 194 enum i40iw_hw_stats_index_32b {
 195         I40IW_HW_STAT_INDEX_IP4RXDISCARD = 0,
 196         I40IW_HW_STAT_INDEX_IP4RXTRUNC,
 197         I40IW_HW_STAT_INDEX_IP4TXNOROUTE,
 198         I40IW_HW_STAT_INDEX_IP6RXDISCARD,
 199         I40IW_HW_STAT_INDEX_IP6RXTRUNC,
 200         I40IW_HW_STAT_INDEX_IP6TXNOROUTE,
 201         I40IW_HW_STAT_INDEX_TCPRTXSEG,
 202         I40IW_HW_STAT_INDEX_TCPRXOPTERR,
 203         I40IW_HW_STAT_INDEX_TCPRXPROTOERR,
 204         I40IW_HW_STAT_INDEX_MAX_32
 205 };
 206
 207 enum i40iw_hw_stats_index_64b {
 208         I40IW_HW_STAT_INDEX_IP4RXOCTS = 0,
 209         I40IW_HW_STAT_INDEX_IP4RXPKTS,
 210         I40IW_HW_STAT_INDEX_IP4RXFRAGS,
 211         I40IW_HW_STAT_INDEX_IP4RXMCPKTS,
 212         I40IW_HW_STAT_INDEX_IP4TXOCTS,
 213         I40IW_HW_STAT_INDEX_IP4TXPKTS,
 214         I40IW_HW_STAT_INDEX_IP4TXFRAGS,
 215         I40IW_HW_STAT_INDEX_IP4TXMCPKTS,
 216         I40IW_HW_STAT_INDEX_IP6RXOCTS,
 217         I40IW_HW_STAT_INDEX_IP6RXPKTS,
 218         I40IW_HW_STAT_INDEX_IP6RXFRAGS,
 219         I40IW_HW_STAT_INDEX_IP6RXMCPKTS,
 220         I40IW_HW_STAT_INDEX_IP6TXOCTS,
 221         I40IW_HW_STAT_INDEX_IP6TXPKTS,
 222         I40IW_HW_STAT_INDEX_IP6TXFRAGS,
 223         I40IW_HW_STAT_INDEX_IP6TXMCPKTS,
 224         I40IW_HW_STAT_INDEX_TCPRXSEGS,
 225         I40IW_HW_STAT_INDEX_TCPTXSEG,
 226         I40IW_HW_STAT_INDEX_RDMARXRDS,
 227         I40IW_HW_STAT_INDEX_RDMARXSNDS,
 228         I40IW_HW_STAT_INDEX_RDMARXWRS,
 229         I40IW_HW_STAT_INDEX_RDMATXRDS,
 230         I40IW_HW_STAT_INDEX_RDMATXSNDS,
 231         I40IW_HW_STAT_INDEX_RDMATXWRS,
 232         I40IW_HW_STAT_INDEX_RDMAVBND,
 233         I40IW_HW_STAT_INDEX_RDMAVINV,
 234         I40IW_HW_STAT_INDEX_MAX_64
 235 };
 236
 237 struct i40iw_dev_hw_stats_offsets {
 238         u32 stats_offset_32[I40IW_HW_STAT_INDEX_MAX_32];
 239         u32 stats_offset_64[I40IW_HW_STAT_INDEX_MAX_64];
 240 };
 241
 242 struct i40iw_dev_hw_stats {
 243         u64 stats_value_32[I40IW_HW_STAT_INDEX_MAX_32];
 244         u64 stats_value_64[I40IW_HW_STAT_INDEX_MAX_64];
 245 };
 246
 247 struct i40iw_vsi_pestat {
 248         struct i40iw_hw *hw;
 249         struct i40iw_dev_hw_stats hw_stats;
 250         struct i40iw_dev_hw_stats last_read_hw_stats;
 251         struct i40iw_dev_hw_stats_offsets hw_stats_offsets;
 252         struct timer_list stats_timer;
 253         struct i40iw_sc_vsi *vsi;
 254         spinlock_t lock; /* rdma stats lock */
 255 };
 256
 257 struct i40iw_hw {
 258         u8 __iomem *hw_addr;
 259         void *dev_context;
 260         struct i40iw_hmc_info hmc;
 261 };
 262
 263 struct i40iw_pfpdu {
 264         struct list_head rxlist;
 265         u32 rcv_nxt;
 266         u32 fps;
 267         u32 max_fpdu_data;
 268         bool mode;
 269         bool mpa_crc_err;
 270         u64 total_ieq_bufs;
 271         u64 fpdu_processed;
 272         u64 bad_seq_num;
 273         u64 crc_err;
 274         u64 no_tx_bufs;
 275         u64 tx_err;
 276         u64 out_of_order;
 277         u64 pmode_count;
 278 };
 279
 280 struct i40iw_sc_pd {
 281         u32 size;
 282         struct i40iw_sc_dev *dev;
 283         u16 pd_id;
 284         int abi_ver;
 285 };
 286
 287 struct i40iw_cqp_quanta {
 288         u64 elem[I40IW_CQP_WQE_SIZE];
 289 };
 290
 291 struct i40iw_sc_cqp {
 292         u32 size;
 293         u64 sq_pa;
 294         u64 host_ctx_pa;
 295         void *back_cqp;
 296         struct i40iw_sc_dev *dev;
 297         enum i40iw_status_code (*process_cqp_sds)(struct i40iw_sc_dev *,
 298                                                   struct i40iw_update_sds_info *);
 299         struct i40iw_dma_mem sdbuf;
 300         struct i40iw_ring sq_ring;
 301         struct i40iw_cqp_quanta *sq_base;
 302         u64 *host_ctx;
 303         u64 *scratch_array;
 304         u32 cqp_id;
 305         u32 sq_size;
 306         u32 hw_sq_size;
 307         u8 struct_ver;
 308         u8 polarity;
 309         bool en_datacenter_tcp;
 310         u8 hmc_profile;
 311         u8 enabled_vf_count;
 312         u8 timeout_count;
 313 };
 314
 315 struct i40iw_sc_aeq {
 316         u32 size;
 317         u64 aeq_elem_pa;
 318         struct i40iw_sc_dev *dev;
 319         struct i40iw_sc_aeqe *aeqe_base;
 320         void *pbl_list;
 321         u32 elem_cnt;
 322         struct i40iw_ring aeq_ring;
 323         bool virtual_map;
 324         u8 pbl_chunk_size;
 325         u32 first_pm_pbl_idx;
 326         u8 polarity;
 327 };
 328
 329 struct i40iw_sc_ceq {
 330         u32 size;
 331         u64 ceq_elem_pa;
 332         struct i40iw_sc_dev *dev;
 333         struct i40iw_ceqe *ceqe_base;
 334         void *pbl_list;
 335         u32 ceq_id;
 336         u32 elem_cnt;
 337         struct i40iw_ring ceq_ring;
 338         bool virtual_map;
 339         u8 pbl_chunk_size;
 340         bool tph_en;
 341         u8 tph_val;
 342         u32 first_pm_pbl_idx;
 343         u8 polarity;
 344 };
 345
 346 struct i40iw_sc_cq {
 347         struct i40iw_cq_uk cq_uk;
 348         u64 cq_pa;
 349         u64 shadow_area_pa;
 350         struct i40iw_sc_dev *dev;
 351         struct i40iw_sc_vsi *vsi;
 352         void *pbl_list;
 353         void *back_cq;
 354         u32 ceq_id;
 355         u32 shadow_read_threshold;
 356         bool ceqe_mask;
 357         bool virtual_map;
 358         u8 pbl_chunk_size;
 359         u8 cq_type;
 360         bool ceq_id_valid;
 361         bool tph_en;
 362         u8 tph_val;
 363         u32 first_pm_pbl_idx;
 364         bool check_overflow;
 365 };
 366
 367 struct i40iw_sc_qp {
 368         struct i40iw_qp_uk qp_uk;
 369         u64 sq_pa;
 370         u64 rq_pa;
 371         u64 hw_host_ctx_pa;
 372         u64 shadow_area_pa;
 373         u64 q2_pa;
 374         struct i40iw_sc_dev *dev;
 375         struct i40iw_sc_vsi *vsi;
 376         struct i40iw_sc_pd *pd;
 377         u64 *hw_host_ctx;
 378         void *llp_stream_handle;
 379         void *back_qp;
 380         struct i40iw_pfpdu pfpdu;
 381         u8 *q2_buf;
 382         u64 qp_compl_ctx;
 383         u16 qs_handle;
 384         u16 push_idx;
 385         u8 sq_tph_val;
 386         u8 rq_tph_val;
 387         u8 qp_state;
 388         u8 qp_type;
 389         u8 hw_sq_size;
 390         u8 hw_rq_size;
 391         u8 src_mac_addr_idx;
 392         bool sq_tph_en;
 393         bool rq_tph_en;
 394         bool rcv_tph_en;
 395         bool xmit_tph_en;
 396         bool virtual_map;
 397         bool flush_sq;
 398         bool flush_rq;
 399         u8 user_pri;
 400         struct list_head list;
 401         bool on_qoslist;
 402         bool sq_flush;
 403         enum i40iw_flush_opcode flush_code;
 404         enum i40iw_term_eventtypes eventtype;
 405         u8 term_flags;
 406 };
 407
 408 struct i40iw_hmc_fpm_misc {
 409         u32 max_ceqs;
 410         u32 max_sds;
 411         u32 xf_block_size;
 412         u32 q1_block_size;
 413         u32 ht_multiplier;
 414         u32 timer_bucket;
 415 };
 416
 417 struct i40iw_vchnl_if {
 418         enum i40iw_status_code (*vchnl_recv)(struct i40iw_sc_dev *, u32, u8 *, u16);
 419         enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *dev, u32, u8 *, u16);
 420 };
 421
 422 #define I40IW_VCHNL_MAX_VF_MSG_SIZE 512
 423
 424 struct i40iw_vchnl_vf_msg_buffer {
 425         struct i40iw_virtchnl_op_buf vchnl_msg;
 426         char parm_buffer[I40IW_VCHNL_MAX_VF_MSG_SIZE - 1];
 427 };
 428
 429 struct i40iw_qos {
 430         struct list_head qplist;
 431         spinlock_t lock;        /* qos list */
 432         u16 qs_handle;
 433 };
 434
 435 struct i40iw_vfdev {
 436         struct i40iw_sc_dev *pf_dev;
 437         u8 *hmc_info_mem;
 438         struct i40iw_vsi_pestat pestat;
 439         struct i40iw_hmc_pble_info *pble_info;
 440         struct i40iw_hmc_info hmc_info;
 441         struct i40iw_vchnl_vf_msg_buffer vf_msg_buffer;
 442         u64 fpm_query_buf_pa;
 443         u64 *fpm_query_buf;
 444         u32 vf_id;
 445         u32 msg_count;
 446         bool pf_hmc_initialized;
 447         u16 pmf_index;
 448         u16 iw_vf_idx;          /* VF Device table index */
 449         bool stats_initialized;
 450 };
 451
 452 #define I40IW_INVALID_FCN_ID 0xff
 453 struct i40iw_sc_vsi {
 454         struct i40iw_sc_dev *dev;
 455         void *back_vsi; /* Owned by OS */
 456         u32 ilq_count;
 457         struct i40iw_virt_mem ilq_mem;
 458         struct i40iw_puda_rsrc *ilq;
 459         u32 ieq_count;
 460         struct i40iw_virt_mem ieq_mem;
 461         struct i40iw_puda_rsrc *ieq;
 462         u16 exception_lan_queue;
 463         u16 mtu;
 464         u8 fcn_id;
 465         bool stats_fcn_id_alloc;
 466         struct i40iw_qos qos[I40IW_MAX_USER_PRIORITY];
 467         struct i40iw_vsi_pestat *pestat;
 468 };
 469
 470 struct i40iw_sc_dev {
 471         struct list_head cqp_cmd_head;  /* head of the CQP command list */
 472         spinlock_t cqp_lock; /* cqp list sync */
 473         struct i40iw_dev_uk dev_uk;
 474         bool fcn_id_array[I40IW_MAX_STATS_COUNT];
 475         struct i40iw_dma_mem vf_fpm_query_buf[I40IW_MAX_PE_ENABLED_VF_COUNT];
 476         u64 fpm_query_buf_pa;
 477         u64 fpm_commit_buf_pa;
 478         u64 *fpm_query_buf;
 479         u64 *fpm_commit_buf;
 480         void *back_dev;
 481         struct i40iw_hw *hw;
 482         u8 __iomem *db_addr;
 483         struct i40iw_hmc_info *hmc_info;
 484         struct i40iw_hmc_pble_info *pble_info;
 485         struct i40iw_vfdev *vf_dev[I40IW_MAX_PE_ENABLED_VF_COUNT];
 486         struct i40iw_sc_cqp *cqp;
 487         struct i40iw_sc_aeq *aeq;
 488         struct i40iw_sc_ceq *ceq[I40IW_CEQ_MAX_COUNT];
 489         struct i40iw_sc_cq *ccq;
 490         struct i40iw_cqp_ops *cqp_ops;
 491         struct i40iw_ccq_ops *ccq_ops;
 492         struct i40iw_ceq_ops *ceq_ops;
 493         struct i40iw_aeq_ops *aeq_ops;
 494         struct i40iw_pd_ops *iw_pd_ops;
 495         struct i40iw_priv_qp_ops *iw_priv_qp_ops;
 496         struct i40iw_priv_cq_ops *iw_priv_cq_ops;
 497         struct i40iw_mr_ops *mr_ops;
 498         struct i40iw_cqp_misc_ops *cqp_misc_ops;
 499         struct i40iw_hmc_ops *hmc_ops;
 500         struct i40iw_vchnl_if vchnl_if;
 501         const struct i40iw_vf_cqp_ops *iw_vf_cqp_ops;
 502
 503         struct i40iw_hmc_fpm_misc hmc_fpm_misc;
 504         u32 debug_mask;
 505         u8 hmc_fn_id;
 506         bool is_pf;
 507         bool vchnl_up;
 508         bool ceq_valid;
 509         u8 vf_id;
 510         wait_queue_head_t vf_reqs;
 511         u64 cqp_cmd_stats[OP_SIZE_CQP_STAT_ARRAY];
 512         struct i40iw_vchnl_vf_msg_buffer vchnl_vf_msg_buf;
 513         u8 hw_rev;
 514 };
 515
 516 struct i40iw_modify_cq_info {
 517         u64 cq_pa;
 518         struct i40iw_cqe *cq_base;
 519         void *pbl_list;
 520         u32 ceq_id;
 521         u32 cq_size;
 522         u32 shadow_read_threshold;
 523         bool virtual_map;
 524         u8 pbl_chunk_size;
 525         bool check_overflow;
 526         bool cq_resize;
 527         bool ceq_change;
 528         bool check_overflow_change;
 529         u32 first_pm_pbl_idx;
 530         bool ceq_valid;
 531 };
 532
 533 struct i40iw_create_qp_info {
 534         u8 next_iwarp_state;
 535         bool ord_valid;
 536         bool tcp_ctx_valid;
 537         bool cq_num_valid;
 538         bool arp_cache_idx_valid;
 539 };
 540
 541 struct i40iw_modify_qp_info {
 542         u64 rx_win0;
 543         u64 rx_win1;
 544         u8 next_iwarp_state;
 545         u8 termlen;
 546         bool ord_valid;
 547         bool tcp_ctx_valid;
 548         bool cq_num_valid;
 549         bool arp_cache_idx_valid;
 550         bool reset_tcp_conn;
 551         bool remove_hash_idx;
 552         bool dont_send_term;
 553         bool dont_send_fin;
 554         bool cached_var_valid;
 555         bool force_loopback;
 556 };
 557
 558 struct i40iw_ccq_cqe_info {
 559         struct i40iw_sc_cqp *cqp;
 560         u64 scratch;
 561         u32 op_ret_val;
 562         u16 maj_err_code;
 563         u16 min_err_code;
 564         u8 op_code;
 565         bool error;
 566 };
 567
 568 struct i40iw_l2params {
 569         u16 qs_handle_list[I40IW_MAX_USER_PRIORITY];
 570         u16 mtu;
 571 };
 572
 573 struct i40iw_vsi_init_info {
 574         struct i40iw_sc_dev *dev;
 575         void  *back_vsi;
 576         struct i40iw_l2params *params;
 577         u16 exception_lan_queue;
 578 };
 579
 580 struct i40iw_vsi_stats_info {
 581         struct i40iw_vsi_pestat *pestat;
 582         u8 fcn_id;
 583         bool alloc_fcn_id;
 584         bool stats_initialize;
 585 };
 586
 587 struct i40iw_device_init_info {
 588         u64 fpm_query_buf_pa;
 589         u64 fpm_commit_buf_pa;
 590         u64 *fpm_query_buf;
 591         u64 *fpm_commit_buf;
 592         struct i40iw_hw *hw;
 593         void __iomem *bar0;
 594         enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *, u32, u8 *, u16);
 595         u8 hmc_fn_id;
 596         bool is_pf;
 597         u32 debug_mask;
 598 };
 599
 600 enum i40iw_cqp_hmc_profile {
 601         I40IW_HMC_PROFILE_DEFAULT = 1,
 602         I40IW_HMC_PROFILE_FAVOR_VF = 2,
 603         I40IW_HMC_PROFILE_EQUAL = 3,
 604 };
 605
 606 struct i40iw_cqp_init_info {
 607         u64 cqp_compl_ctx;
 608         u64 host_ctx_pa;
 609         u64 sq_pa;
 610         struct i40iw_sc_dev *dev;
 611         struct i40iw_cqp_quanta *sq;
 612         u64 *host_ctx;
 613         u64 *scratch_array;
 614         u32 sq_size;
 615         u8 struct_ver;
 616         bool en_datacenter_tcp;
 617         u8 hmc_profile;
 618         u8 enabled_vf_count;
 619 };
 620
 621 struct i40iw_ceq_init_info {
 622         u64 ceqe_pa;
 623         struct i40iw_sc_dev *dev;
 624         u64 *ceqe_base;
 625         void *pbl_list;
 626         u32 elem_cnt;
 627         u32 ceq_id;
 628         bool virtual_map;
 629         u8 pbl_chunk_size;
 630         bool tph_en;
 631         u8 tph_val;
 632         u32 first_pm_pbl_idx;
 633 };
 634
 635 struct i40iw_aeq_init_info {
 636         u64 aeq_elem_pa;
 637         struct i40iw_sc_dev *dev;
 638         u32 *aeqe_base;
 639         void *pbl_list;
 640         u32 elem_cnt;
 641         bool virtual_map;
 642         u8 pbl_chunk_size;
 643         u32 first_pm_pbl_idx;
 644 };
 645
 646 struct i40iw_ccq_init_info {
 647         u64 cq_pa;
 648         u64 shadow_area_pa;
 649         struct i40iw_sc_dev *dev;
 650         struct i40iw_cqe *cq_base;
 651         u64 *shadow_area;
 652         void *pbl_list;
 653         u32 num_elem;
 654         u32 ceq_id;
 655         u32 shadow_read_threshold;
 656         bool ceqe_mask;
 657         bool ceq_id_valid;
 658         bool tph_en;
 659         u8 tph_val;
 660         bool avoid_mem_cflct;
 661         bool virtual_map;
 662         u8 pbl_chunk_size;
 663         u32 first_pm_pbl_idx;
 664 };
 665
 666 struct i40iwarp_offload_info {
 667         u16 rcv_mark_offset;
 668         u16 snd_mark_offset;
 669         u16 pd_id;
 670         u8 ddp_ver;
 671         u8 rdmap_ver;
 672         u8 ord_size;
 673         u8 ird_size;
 674         bool wr_rdresp_en;
 675         bool rd_enable;
 676         bool snd_mark_en;
 677         bool rcv_mark_en;
 678         bool bind_en;
 679         bool fast_reg_en;
 680         bool priv_mode_en;
 681         bool lsmm_present;
 682         u8 iwarp_mode;
 683         bool align_hdrs;
 684         bool rcv_no_mpa_crc;
 685
 686         u8 last_byte_sent;
 687 };
 688
 689 struct i40iw_tcp_offload_info {
 690         bool ipv4;
 691         bool no_nagle;
 692         bool insert_vlan_tag;
 693         bool time_stamp;
 694         u8 cwnd_inc_limit;
 695         bool drop_ooo_seg;
 696         u8 dup_ack_thresh;
 697         u8 ttl;
 698         u8 src_mac_addr_idx;
 699         bool avoid_stretch_ack;
 700         u8 tos;
 701         u16 src_port;
 702         u16 dst_port;
 703         u32 dest_ip_addr0;
 704         u32 dest_ip_addr1;
 705         u32 dest_ip_addr2;
 706         u32 dest_ip_addr3;
 707         u32 snd_mss;
 708         u16 vlan_tag;
 709         u16 arp_idx;
 710         u32 flow_label;
 711         bool wscale;
 712         u8 tcp_state;
 713         u8 snd_wscale;
 714         u8 rcv_wscale;
 715         u32 time_stamp_recent;
 716         u32 time_stamp_age;
 717         u32 snd_nxt;
 718         u32 snd_wnd;
 719         u32 rcv_nxt;
 720         u32 rcv_wnd;
 721         u32 snd_max;
 722         u32 snd_una;
 723         u32 srtt;
 724         u32 rtt_var;
 725         u32 ss_thresh;
 726         u32 cwnd;
 727         u32 snd_wl1;
 728         u32 snd_wl2;
 729         u32 max_snd_window;
 730         u8 rexmit_thresh;
 731         u32 local_ipaddr0;
 732         u32 local_ipaddr1;
 733         u32 local_ipaddr2;
 734         u32 local_ipaddr3;
 735         bool ignore_tcp_opt;
 736         bool ignore_tcp_uns_opt;
 737 };
 738
 739 struct i40iw_qp_host_ctx_info {
 740         u64 qp_compl_ctx;
 741         struct i40iw_tcp_offload_info *tcp_info;
 742         struct i40iwarp_offload_info *iwarp_info;
 743         u32 send_cq_num;
 744         u32 rcv_cq_num;
 745         u16 push_idx;
 746         bool push_mode_en;
 747         bool tcp_info_valid;
 748         bool iwarp_info_valid;
 749         bool err_rq_idx_valid;
 750         u16 err_rq_idx;
 751         bool add_to_qoslist;
 752         u8 user_pri;
 753 };
 754
 755 struct i40iw_aeqe_info {
 756         u64 compl_ctx;
 757         u32 qp_cq_id;
 758         u16 ae_id;
 759         u16 wqe_idx;
 760         u8 tcp_state;
 761         u8 iwarp_state;
 762         bool qp;
 763         bool cq;
 764         bool sq;
 765         bool in_rdrsp_wr;
 766         bool out_rdrsp;
 767         u8 q2_data_written;
 768         bool aeqe_overflow;
 769 };
 770
 771 struct i40iw_allocate_stag_info {
 772         u64 total_len;
 773         u32 chunk_size;
 774         u32 stag_idx;
 775         u32 page_size;
 776         u16 pd_id;
 777         u16 access_rights;
 778         bool remote_access;
 779         bool use_hmc_fcn_index;
 780         u8 hmc_fcn_index;
 781         bool use_pf_rid;
 782 };
 783
 784 struct i40iw_reg_ns_stag_info {
 785         u64 reg_addr_pa;
 786         u64 fbo;
 787         void *va;
 788         u64 total_len;
 789         u32 page_size;
 790         u32 chunk_size;
 791         u32 first_pm_pbl_index;
 792         enum i40iw_addressing_type addr_type;
 793         i40iw_stag_index stag_idx;
 794         u16 access_rights;
 795         u16 pd_id;
 796         i40iw_stag_key stag_key;
 797         bool use_hmc_fcn_index;
 798         u8 hmc_fcn_index;
 799         bool use_pf_rid;
 800 };
 801
 802 struct i40iw_fast_reg_stag_info {
 803         u64 wr_id;
 804         u64 reg_addr_pa;
 805         u64 fbo;
 806         void *va;
 807         u64 total_len;
 808         u32 page_size;
 809         u32 chunk_size;
 810         u32 first_pm_pbl_index;
 811         enum i40iw_addressing_type addr_type;
 812         i40iw_stag_index stag_idx;
 813         u16 access_rights;
 814         u16 pd_id;
 815         i40iw_stag_key stag_key;
 816         bool local_fence;
 817         bool read_fence;
 818         bool signaled;
 819         bool use_hmc_fcn_index;
 820         u8 hmc_fcn_index;
 821         bool use_pf_rid;
 822         bool defer_flag;
 823 };
 824
 825 struct i40iw_dealloc_stag_info {
 826         u32 stag_idx;
 827         u16 pd_id;
 828         bool mr;
 829         bool dealloc_pbl;
 830 };
 831
 832 struct i40iw_register_shared_stag {
 833         void *va;
 834         enum i40iw_addressing_type addr_type;
 835         i40iw_stag_index new_stag_idx;
 836         i40iw_stag_index parent_stag_idx;
 837         u32 access_rights;
 838         u16 pd_id;
 839         i40iw_stag_key new_stag_key;
 840 };
 841
 842 struct i40iw_qp_init_info {
 843         struct i40iw_qp_uk_init_info qp_uk_init_info;
 844         struct i40iw_sc_pd *pd;
 845         struct i40iw_sc_vsi *vsi;
 846         u64 *host_ctx;
 847         u8 *q2;
 848         u64 sq_pa;
 849         u64 rq_pa;
 850         u64 host_ctx_pa;
 851         u64 q2_pa;
 852         u64 shadow_area_pa;
 853         int abi_ver;
 854         u8 sq_tph_val;
 855         u8 rq_tph_val;
 856         u8 type;
 857         bool sq_tph_en;
 858         bool rq_tph_en;
 859         bool rcv_tph_en;
 860         bool xmit_tph_en;
 861         bool virtual_map;
 862 };
 863
 864 struct i40iw_cq_init_info {
 865         struct i40iw_sc_dev *dev;
 866         u64 cq_base_pa;
 867         u64 shadow_area_pa;
 868         u32 ceq_id;
 869         u32 shadow_read_threshold;
 870         bool virtual_map;
 871         bool ceqe_mask;
 872         u8 pbl_chunk_size;
 873         u32 first_pm_pbl_idx;
 874         bool ceq_id_valid;
 875         bool tph_en;
 876         u8 tph_val;
 877         u8 type;
 878         struct i40iw_cq_uk_init_info cq_uk_init_info;
 879 };
 880
 881 struct i40iw_upload_context_info {
 882         u64 buf_pa;
 883         bool freeze_qp;
 884         bool raw_format;
 885         u32 qp_id;
 886         u8 qp_type;
 887 };
 888
 889 struct i40iw_add_arp_cache_entry_info {
 890         u8 mac_addr[6];
 891         u32 reach_max;
 892         u16 arp_index;
 893         bool permanent;
 894 };
 895
 896 struct i40iw_apbvt_info {
 897         u16 port;
 898         bool add;
 899 };
 900
 901 enum i40iw_quad_entry_type {
 902         I40IW_QHASH_TYPE_TCP_ESTABLISHED = 1,
 903         I40IW_QHASH_TYPE_TCP_SYN,
 904 };
 905
 906 enum i40iw_quad_hash_manage_type {
 907         I40IW_QHASH_MANAGE_TYPE_DELETE = 0,
 908         I40IW_QHASH_MANAGE_TYPE_ADD,
 909         I40IW_QHASH_MANAGE_TYPE_MODIFY
 910 };
 911
 912 struct i40iw_qhash_table_info {
 913         struct i40iw_sc_vsi *vsi;
 914         enum i40iw_quad_hash_manage_type manage;
 915         enum i40iw_quad_entry_type entry_type;
 916         bool vlan_valid;
 917         bool ipv4_valid;
 918         u8 mac_addr[6];
 919         u16 vlan_id;
 920         u8 user_pri;
 921         u32 qp_num;
 922         u32 dest_ip[4];
 923         u32 src_ip[4];
 924         u16 dest_port;
 925         u16 src_port;
 926 };
 927
 928 struct i40iw_local_mac_ipaddr_entry_info {
 929         u8 mac_addr[6];
 930         u8 entry_idx;
 931 };
 932
 933 struct i40iw_cqp_manage_push_page_info {
 934         u32 push_idx;
 935         u16 qs_handle;
 936         u8 free_page;
 937 };
 938
 939 struct i40iw_qp_flush_info {
 940         u16 sq_minor_code;
 941         u16 sq_major_code;
 942         u16 rq_minor_code;
 943         u16 rq_major_code;
 944         u16 ae_code;
 945         u8 ae_source;
 946         bool sq;
 947         bool rq;
 948         bool userflushcode;
 949         bool generate_ae;
 950 };
 951
 952 struct i40iw_cqp_commit_fpm_values {
 953         u64 qp_base;
 954         u64 cq_base;
 955         u32 hte_base;
 956         u32 arp_base;
 957         u32 apbvt_inuse_base;
 958         u32 mr_base;
 959         u32 xf_base;
 960         u32 xffl_base;
 961         u32 q1_base;
 962         u32 q1fl_base;
 963         u32 fsimc_base;
 964         u32 fsiav_base;
 965         u32 pbl_base;
 966
 967         u32 qp_cnt;
 968         u32 cq_cnt;
 969         u32 hte_cnt;
 970         u32 arp_cnt;
 971         u32 mr_cnt;
 972         u32 xf_cnt;
 973         u32 xffl_cnt;
 974         u32 q1_cnt;
 975         u32 q1fl_cnt;
 976         u32 fsimc_cnt;
 977         u32 fsiav_cnt;
 978         u32 pbl_cnt;
 979 };
 980
 981 struct i40iw_cqp_query_fpm_values {
 982         u16 first_pe_sd_index;
 983         u32 qp_objsize;
 984         u32 cq_objsize;
 985         u32 hte_objsize;
 986         u32 arp_objsize;
 987         u32 mr_objsize;
 988         u32 xf_objsize;
 989         u32 q1_objsize;
 990         u32 fsimc_objsize;
 991         u32 fsiav_objsize;
 992
 993         u32 qp_max;
 994         u32 cq_max;
 995         u32 hte_max;
 996         u32 arp_max;
 997         u32 mr_max;
 998         u32 xf_max;
 999         u32 xffl_max;
1000         u32 q1_max;
1001         u32 q1fl_max;
1002         u32 fsimc_max;
1003         u32 fsiav_max;
1004         u32 pbl_max;
1005 };
1006
1007 struct i40iw_gen_ae_info {
1008         u16 ae_code;
1009         u8 ae_source;
1010 };
1011
1012 struct i40iw_cqp_ops {
1013         enum i40iw_status_code (*cqp_init)(struct i40iw_sc_cqp *,
1014                                            struct i40iw_cqp_init_info *);
1015         enum i40iw_status_code (*cqp_create)(struct i40iw_sc_cqp *, u16 *, u16 *);
1016         void (*cqp_post_sq)(struct i40iw_sc_cqp *);
1017         u64 *(*cqp_get_next_send_wqe)(struct i40iw_sc_cqp *, u64 scratch);
1018         enum i40iw_status_code (*cqp_destroy)(struct i40iw_sc_cqp *);
1019         enum i40iw_status_code (*poll_for_cqp_op_done)(struct i40iw_sc_cqp *, u8,
1020                                                        struct i40iw_ccq_cqe_info *);
1021 };
1022
1023 struct i40iw_ccq_ops {
1024         enum i40iw_status_code (*ccq_init)(struct i40iw_sc_cq *,
1025                                            struct i40iw_ccq_init_info *);
1026         enum i40iw_status_code (*ccq_create)(struct i40iw_sc_cq *, u64, bool, bool);
1027         enum i40iw_status_code (*ccq_destroy)(struct i40iw_sc_cq *, u64, bool);
1028         enum i40iw_status_code (*ccq_create_done)(struct i40iw_sc_cq *);
1029         enum i40iw_status_code (*ccq_get_cqe_info)(struct i40iw_sc_cq *,
1030                                                    struct i40iw_ccq_cqe_info *);
1031         void (*ccq_arm)(struct i40iw_sc_cq *);
1032 };
1033
1034 struct i40iw_ceq_ops {
1035         enum i40iw_status_code (*ceq_init)(struct i40iw_sc_ceq *,
1036                                            struct i40iw_ceq_init_info *);
1037         enum i40iw_status_code (*ceq_create)(struct i40iw_sc_ceq *, u64, bool);
1038         enum i40iw_status_code (*cceq_create_done)(struct i40iw_sc_ceq *);
1039         enum i40iw_status_code (*cceq_destroy_done)(struct i40iw_sc_ceq *);
1040         enum i40iw_status_code (*cceq_create)(struct i40iw_sc_ceq *, u64);
1041         enum i40iw_status_code (*ceq_destroy)(struct i40iw_sc_ceq *, u64, bool);
1042         void *(*process_ceq)(struct i40iw_sc_dev *, struct i40iw_sc_ceq *);
1043 };
1044
1045 struct i40iw_aeq_ops {
1046         enum i40iw_status_code (*aeq_init)(struct i40iw_sc_aeq *,
1047                                            struct i40iw_aeq_init_info *);
1048         enum i40iw_status_code (*aeq_create)(struct i40iw_sc_aeq *, u64, bool);
1049         enum i40iw_status_code (*aeq_destroy)(struct i40iw_sc_aeq *, u64, bool);
1050         enum i40iw_status_code (*get_next_aeqe)(struct i40iw_sc_aeq *,
1051                                                 struct i40iw_aeqe_info *);
1052         enum i40iw_status_code (*repost_aeq_entries)(struct i40iw_sc_dev *, u32);
1053         enum i40iw_status_code (*aeq_create_done)(struct i40iw_sc_aeq *);
1054         enum i40iw_status_code (*aeq_destroy_done)(struct i40iw_sc_aeq *);
1055 };
1056
1057 struct i40iw_pd_ops {
1058         void (*pd_init)(struct i40iw_sc_dev *, struct i40iw_sc_pd *, u16, int);
1059 };
1060
1061 struct i40iw_priv_qp_ops {
1062         enum i40iw_status_code (*qp_init)(struct i40iw_sc_qp *, struct i40iw_qp_init_info *);
1063         enum i40iw_status_code (*qp_create)(struct i40iw_sc_qp *,
1064                                             struct i40iw_create_qp_info *, u64, bool);
1065         enum i40iw_status_code (*qp_modify)(struct i40iw_sc_qp *,
1066                                             struct i40iw_modify_qp_info *, u64, bool);
1067         enum i40iw_status_code (*qp_destroy)(struct i40iw_sc_qp *, u64, bool, bool, bool);
1068         enum i40iw_status_code (*qp_flush_wqes)(struct i40iw_sc_qp *,
1069                                                 struct i40iw_qp_flush_info *, u64, bool);
1070         enum i40iw_status_code (*qp_upload_context)(struct i40iw_sc_dev *,
1071                                                     struct i40iw_upload_context_info *,
1072                                                     u64, bool);
1073         enum i40iw_status_code (*qp_setctx)(struct i40iw_sc_qp *, u64 *,
1074                                             struct i40iw_qp_host_ctx_info *);
1075
1076         void (*qp_send_lsmm)(struct i40iw_sc_qp *, void *, u32, i40iw_stag);
1077         void (*qp_send_lsmm_nostag)(struct i40iw_sc_qp *, void *, u32);
1078         void (*qp_send_rtt)(struct i40iw_sc_qp *, bool);
1079         enum i40iw_status_code (*qp_post_wqe0)(struct i40iw_sc_qp *, u8);
1080         enum i40iw_status_code (*iw_mr_fast_register)(struct i40iw_sc_qp *,
1081                                                       struct i40iw_fast_reg_stag_info *,
1082                                                       bool);
1083 };
1084
1085 struct i40iw_priv_cq_ops {
1086         enum i40iw_status_code (*cq_init)(struct i40iw_sc_cq *, struct i40iw_cq_init_info *);
1087         enum i40iw_status_code (*cq_create)(struct i40iw_sc_cq *, u64, bool, bool);
1088         enum i40iw_status_code (*cq_destroy)(struct i40iw_sc_cq *, u64, bool);
1089         enum i40iw_status_code (*cq_modify)(struct i40iw_sc_cq *,
1090                                             struct i40iw_modify_cq_info *, u64, bool);
1091 };
1092
1093 struct i40iw_mr_ops {
1094         enum i40iw_status_code (*alloc_stag)(struct i40iw_sc_dev *,
1095                                              struct i40iw_allocate_stag_info *, u64, bool);
1096         enum i40iw_status_code (*mr_reg_non_shared)(struct i40iw_sc_dev *,
1097                                                     struct i40iw_reg_ns_stag_info *,
1098                                                     u64, bool);
1099         enum i40iw_status_code (*mr_reg_shared)(struct i40iw_sc_dev *,
1100                                                 struct i40iw_register_shared_stag *,
1101                                                 u64, bool);
1102         enum i40iw_status_code (*dealloc_stag)(struct i40iw_sc_dev *,
1103                                                struct i40iw_dealloc_stag_info *,
1104                                                u64, bool);
1105         enum i40iw_status_code (*query_stag)(struct i40iw_sc_dev *, u64, u32, bool);
1106         enum i40iw_status_code (*mw_alloc)(struct i40iw_sc_dev *, u64, u32, u16, bool);
1107 };
1108
1109 struct i40iw_cqp_misc_ops {
1110         enum i40iw_status_code (*manage_push_page)(struct i40iw_sc_cqp *,
1111                                                    struct i40iw_cqp_manage_push_page_info *,
1112                                                    u64, bool);
1113         enum i40iw_status_code (*manage_hmc_pm_func_table)(struct i40iw_sc_cqp *,
1114                                                            u64, u8, bool, bool);
1115         enum i40iw_status_code (*set_hmc_resource_profile)(struct i40iw_sc_cqp *,
1116                                                            u64, u8, u8, bool, bool);
1117         enum i40iw_status_code (*commit_fpm_values)(struct i40iw_sc_cqp *, u64, u8,
1118                                                     struct i40iw_dma_mem *, bool, u8);
1119         enum i40iw_status_code (*query_fpm_values)(struct i40iw_sc_cqp *, u64, u8,
1120                                                    struct i40iw_dma_mem *, bool, u8);
1121         enum i40iw_status_code (*static_hmc_pages_allocated)(struct i40iw_sc_cqp *,
1122                                                              u64, u8, bool, bool);
1123         enum i40iw_status_code (*add_arp_cache_entry)(struct i40iw_sc_cqp *,
1124                                                       struct i40iw_add_arp_cache_entry_info *,
1125                                                       u64, bool);
1126         enum i40iw_status_code (*del_arp_cache_entry)(struct i40iw_sc_cqp *, u64, u16, bool);
1127         enum i40iw_status_code (*query_arp_cache_entry)(struct i40iw_sc_cqp *, u64, u16, bool);
1128         enum i40iw_status_code (*manage_apbvt_entry)(struct i40iw_sc_cqp *,
1129                                                      struct i40iw_apbvt_info *, u64, bool);
1130         enum i40iw_status_code (*manage_qhash_table_entry)(struct i40iw_sc_cqp *,
1131                                                            struct i40iw_qhash_table_info *, u64, bool);
1132         enum i40iw_status_code (*alloc_local_mac_ipaddr_table_entry)(struct i40iw_sc_cqp *, u64, bool);
1133         enum i40iw_status_code (*add_local_mac_ipaddr_entry)(struct i40iw_sc_cqp *,
1134                                                              struct i40iw_local_mac_ipaddr_entry_info *,
1135                                                              u64, bool);
1136         enum i40iw_status_code (*del_local_mac_ipaddr_entry)(struct i40iw_sc_cqp *, u64, u8, u8, bool);
1137         enum i40iw_status_code (*cqp_nop)(struct i40iw_sc_cqp *, u64, bool);
1138         enum i40iw_status_code (*commit_fpm_values_done)(struct i40iw_sc_cqp
1139                                                           *);
1140         enum i40iw_status_code (*query_fpm_values_done)(struct i40iw_sc_cqp *);
1141         enum i40iw_status_code (*manage_hmc_pm_func_table_done)(struct i40iw_sc_cqp *);
1142         enum i40iw_status_code (*update_suspend_qp)(struct i40iw_sc_cqp *, struct i40iw_sc_qp *, u64);
1143         enum i40iw_status_code (*update_resume_qp)(struct i40iw_sc_cqp *, struct i40iw_sc_qp *, u64);
1144 };
1145
1146 struct i40iw_hmc_ops {
1147         enum i40iw_status_code (*init_iw_hmc)(struct i40iw_sc_dev *, u8);
1148         enum i40iw_status_code (*parse_fpm_query_buf)(u64 *, struct i40iw_hmc_info *,
1149                                                       struct i40iw_hmc_fpm_misc *);
1150         enum i40iw_status_code (*configure_iw_fpm)(struct i40iw_sc_dev *, u8);
1151         enum i40iw_status_code (*parse_fpm_commit_buf)(u64 *, struct i40iw_hmc_obj_info *, u32 *sd);
1152         enum i40iw_status_code (*create_hmc_object)(struct i40iw_sc_dev *dev,
1153                                                     struct i40iw_hmc_create_obj_info *);
1154         enum i40iw_status_code (*del_hmc_object)(struct i40iw_sc_dev *dev,
1155                                                  struct i40iw_hmc_del_obj_info *,
1156                                                  bool reset);
1157         enum i40iw_status_code (*pf_init_vfhmc)(struct i40iw_sc_dev *, u8, u32 *);
1158         enum i40iw_status_code (*vf_configure_vffpm)(struct i40iw_sc_dev *, u32 *);
1159 };
1160
1161 struct cqp_info {
1162         union {
1163                 struct {
1164                         struct i40iw_sc_qp *qp;
1165                         struct i40iw_create_qp_info info;
1166                         u64 scratch;
1167                 } qp_create;
1168
1169                 struct {
1170                         struct i40iw_sc_qp *qp;
1171                         struct i40iw_modify_qp_info info;
1172                         u64 scratch;
1173                 } qp_modify;
1174
1175                 struct {
1176                         struct i40iw_sc_qp *qp;
1177                         u64 scratch;
1178                         bool remove_hash_idx;
1179                         bool ignore_mw_bnd;
1180                 } qp_destroy;
1181
1182                 struct {
1183                         struct i40iw_sc_cq *cq;
1184                         u64 scratch;
1185                         bool check_overflow;
1186                 } cq_create;
1187
1188                 struct {
1189                         struct i40iw_sc_cq *cq;
1190                         u64 scratch;
1191                 } cq_destroy;
1192
1193                 struct {
1194                         struct i40iw_sc_dev *dev;
1195                         struct i40iw_allocate_stag_info info;
1196                         u64 scratch;
1197                 } alloc_stag;
1198
1199                 struct {
1200                         struct i40iw_sc_dev *dev;
1201                         u64 scratch;
1202                         u32 mw_stag_index;
1203                         u16 pd_id;
1204                 } mw_alloc;
1205
1206                 struct {
1207                         struct i40iw_sc_dev *dev;
1208                         struct i40iw_reg_ns_stag_info info;
1209                         u64 scratch;
1210                 } mr_reg_non_shared;
1211
1212                 struct {
1213                         struct i40iw_sc_dev *dev;
1214                         struct i40iw_dealloc_stag_info info;
1215                         u64 scratch;
1216                 } dealloc_stag;
1217
1218                 struct {
1219                         struct i40iw_sc_cqp *cqp;
1220                         struct i40iw_local_mac_ipaddr_entry_info info;
1221                         u64 scratch;
1222                 } add_local_mac_ipaddr_entry;
1223
1224                 struct {
1225                         struct i40iw_sc_cqp *cqp;
1226                         struct i40iw_add_arp_cache_entry_info info;
1227                         u64 scratch;
1228                 } add_arp_cache_entry;
1229
1230                 struct {
1231                         struct i40iw_sc_cqp *cqp;
1232                         u64 scratch;
1233                         u8 entry_idx;
1234                         u8 ignore_ref_count;
1235                 } del_local_mac_ipaddr_entry;
1236
1237                 struct {
1238                         struct i40iw_sc_cqp *cqp;
1239                         u64 scratch;
1240                         u16 arp_index;
1241                 } del_arp_cache_entry;
1242
1243                 struct {
1244                         struct i40iw_sc_cqp *cqp;
1245                         struct i40iw_manage_vf_pble_info info;
1246                         u64 scratch;
1247                 } manage_vf_pble_bp;
1248
1249                 struct {
1250                         struct i40iw_sc_cqp *cqp;
1251                         struct i40iw_cqp_manage_push_page_info info;
1252                         u64 scratch;
1253                 } manage_push_page;
1254
1255                 struct {
1256                         struct i40iw_sc_dev *dev;
1257                         struct i40iw_upload_context_info info;
1258                         u64 scratch;
1259                 } qp_upload_context;
1260
1261                 struct {
1262                         struct i40iw_sc_cqp *cqp;
1263                         u64 scratch;
1264                 } alloc_local_mac_ipaddr_entry;
1265
1266                 struct {
1267                         struct i40iw_sc_dev *dev;
1268                         struct i40iw_hmc_fcn_info info;
1269                         u64 scratch;
1270                 } manage_hmc_pm;
1271
1272                 struct {
1273                         struct i40iw_sc_ceq *ceq;
1274                         u64 scratch;
1275                 } ceq_create;
1276
1277                 struct {
1278                         struct i40iw_sc_ceq *ceq;
1279                         u64 scratch;
1280                 } ceq_destroy;
1281
1282                 struct {
1283                         struct i40iw_sc_aeq *aeq;
1284                         u64 scratch;
1285                 } aeq_create;
1286
1287                 struct {
1288                         struct i40iw_sc_aeq *aeq;
1289                         u64 scratch;
1290                 } aeq_destroy;
1291
1292                 struct {
1293                         struct i40iw_sc_qp *qp;
1294                         struct i40iw_qp_flush_info info;
1295                         u64 scratch;
1296                 } qp_flush_wqes;
1297
1298                 struct {
1299                         struct i40iw_sc_qp *qp;
1300                         struct i40iw_gen_ae_info info;
1301                         u64 scratch;
1302                 } gen_ae;
1303
1304                 struct {
1305                         struct i40iw_sc_cqp *cqp;
1306                         void *fpm_values_va;
1307                         u64 fpm_values_pa;
1308                         u8 hmc_fn_id;
1309                         u64 scratch;
1310                 } query_fpm_values;
1311
1312                 struct {
1313                         struct i40iw_sc_cqp *cqp;
1314                         void *fpm_values_va;
1315                         u64 fpm_values_pa;
1316                         u8 hmc_fn_id;
1317                         u64 scratch;
1318                 } commit_fpm_values;
1319
1320                 struct {
1321                         struct i40iw_sc_cqp *cqp;
1322                         struct i40iw_apbvt_info info;
1323                         u64 scratch;
1324                 } manage_apbvt_entry;
1325
1326                 struct {
1327                         struct i40iw_sc_cqp *cqp;
1328                         struct i40iw_qhash_table_info info;
1329                         u64 scratch;
1330                 } manage_qhash_table_entry;
1331
1332                 struct {
1333                         struct i40iw_sc_dev *dev;
1334                         struct i40iw_update_sds_info info;
1335                         u64 scratch;
1336                 } update_pe_sds;
1337
1338                 struct {
1339                         struct i40iw_sc_cqp *cqp;
1340                         struct i40iw_sc_qp *qp;
1341                         u64 scratch;
1342                 } suspend_resume;
1343         } u;
1344 };
1345
1346 struct cqp_commands_info {
1347         struct list_head cqp_cmd_entry;
1348         u8 cqp_cmd;
1349         u8 post_sq;
1350         struct cqp_info in;
1351 };
1352
1353 struct i40iw_virtchnl_work_info {
1354         void (*callback_fcn)(void *vf_dev);
1355         void *worker_vf_dev;
1356 };
1357
1358 struct i40iw_cqp_timeout {
1359         u64 compl_cqp_cmds;
1360         u8 count;
1361 };
1362
1363 #endif