drivers/infiniband/hw/cxgb3/cxio_hal.c

   1 /*
   2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
   3  * Copyright (c) 2006 Open Grid Computing, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 #include <asm/delay.h>
  34
  35 #include <linux/mutex.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/sched.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/pci.h>
  40
  41 #include "cxio_resource.h"
  42 #include "cxio_hal.h"
  43 #include "cxgb3_offload.h"
  44 #include "sge_defs.h"
  45
  46 static LIST_HEAD(rdev_list);
  47 static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL;
  48
  49 static inline struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name)
  50 {
  51         struct cxio_rdev *rdev;
  52
  53         list_for_each_entry(rdev, &rdev_list, entry)
  54                 if (!strcmp(rdev->dev_name, dev_name))
  55                         return rdev;
  56         return NULL;
  57 }
  58
  59 static inline struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev
  60                                                              *tdev)
  61 {
  62         struct cxio_rdev *rdev;
  63
  64         list_for_each_entry(rdev, &rdev_list, entry)
  65                 if (rdev->t3cdev_p == tdev)
  66                         return rdev;
  67         return NULL;
  68 }
  69
  70 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
  71                    enum t3_cq_opcode op, u32 credit)
  72 {
  73         int ret;
  74         struct t3_cqe *cqe;
  75         u32 rptr;
  76
  77         struct rdma_cq_op setup;
  78         setup.id = cq->cqid;
  79         setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0;
  80         setup.op = op;
  81         ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
  82
  83         if ((ret < 0) || (op == CQ_CREDIT_UPDATE))
  84                 return ret;
  85
  86         /*
  87          * If the rearm returned an index other than our current index,
  88          * then there might be CQE's in flight (being DMA'd).  We must wait
  89          * here for them to complete or the consumer can miss a notification.
  90          */
  91         if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) {
  92                 int i=0;
  93
  94                 rptr = cq->rptr;
  95
  96                 /*
  97                  * Keep the generation correct by bumping rptr until it
  98                  * matches the index returned by the rearm - 1.
  99                  */
 100                 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret)
 101                         rptr++;
 102
 103                 /*
 104                  * Now rptr is the index for the (last) cqe that was
 105                  * in-flight at the time the HW rearmed the CQ.  We
 106                  * spin until that CQE is valid.
 107                  */
 108                 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2);
 109                 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) {
 110                         udelay(1);
 111                         if (i++ > 1000000) {
 112                                 BUG_ON(1);
 113                                 printk(KERN_ERR "%s: stalled rnic\n",
 114                                        rdev_p->dev_name);
 115                                 return -EIO;
 116                         }
 117                 }
 118         }
 119         return 0;
 120 }
 121
 122 static inline int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
 123 {
 124         struct rdma_cq_setup setup;
 125         setup.id = cqid;
 126         setup.base_addr = 0;    /* NULL address */
 127         setup.size = 0;         /* disaable the CQ */
 128         setup.credits = 0;
 129         setup.credit_thres = 0;
 130         setup.ovfl_mode = 0;
 131         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 132 }
 133
 134 int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
 135 {
 136         u64 sge_cmd;
 137         struct t3_modify_qp_wr *wqe;
 138         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
 139         if (!skb) {
 140                 PDBG("%s alloc_skb failed\n", __FUNCTION__);
 141                 return -ENOMEM;
 142         }
 143         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
 144         memset(wqe, 0, sizeof(*wqe));
 145         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 3, 1, qpid, 7);
 146         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
 147         sge_cmd = qpid << 8 | 3;
 148         wqe->sge_cmd = cpu_to_be64(sge_cmd);
 149         skb->priority = CPL_PRIORITY_CONTROL;
 150         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
 151 }
 152
 153 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 154 {
 155         struct rdma_cq_setup setup;
 156         int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe);
 157
 158         cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
 159         if (!cq->cqid)
 160                 return -ENOMEM;
 161         cq->sw_queue = kzalloc(size, GFP_KERNEL);
 162         if (!cq->sw_queue)
 163                 return -ENOMEM;
 164         cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
 165                                              (1UL << (cq->size_log2)) *
 166                                              sizeof(struct t3_cqe),
 167                                              &(cq->dma_addr), GFP_KERNEL);
 168         if (!cq->queue) {
 169                 kfree(cq->sw_queue);
 170                 return -ENOMEM;
 171         }
 172         pci_unmap_addr_set(cq, mapping, cq->dma_addr);
 173         memset(cq->queue, 0, size);
 174         setup.id = cq->cqid;
 175         setup.base_addr = (u64) (cq->dma_addr);
 176         setup.size = 1UL << cq->size_log2;
 177         setup.credits = 65535;
 178         setup.credit_thres = 1;
 179         if (rdev_p->t3cdev_p->type == T3B)
 180                 setup.ovfl_mode = 0;
 181         else
 182                 setup.ovfl_mode = 1;
 183         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 184 }
 185
 186 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 187 {
 188         struct rdma_cq_setup setup;
 189         setup.id = cq->cqid;
 190         setup.base_addr = (u64) (cq->dma_addr);
 191         setup.size = 1UL << cq->size_log2;
 192         setup.credits = setup.size;
 193         setup.credit_thres = setup.size;        /* TBD: overflow recovery */
 194         setup.ovfl_mode = 1;
 195         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 196 }
 197
 198 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 199 {
 200         struct cxio_qpid_list *entry;
 201         u32 qpid;
 202         int i;
 203
 204         mutex_lock(&uctx->lock);
 205         if (!list_empty(&uctx->qpids)) {
 206                 entry = list_entry(uctx->qpids.next, struct cxio_qpid_list,
 207                                    entry);
 208                 list_del(&entry->entry);
 209                 qpid = entry->qpid;
 210                 kfree(entry);
 211         } else {
 212                 qpid = cxio_hal_get_qpid(rdev_p->rscp);
 213                 if (!qpid)
 214                         goto out;
 215                 for (i = qpid+1; i & rdev_p->qpmask; i++) {
 216                         entry = kmalloc(sizeof *entry, GFP_KERNEL);
 217                         if (!entry)
 218                                 break;
 219                         entry->qpid = i;
 220                         list_add_tail(&entry->entry, &uctx->qpids);
 221                 }
 222         }
 223 out:
 224         mutex_unlock(&uctx->lock);
 225         PDBG("%s qpid 0x%x\n", __FUNCTION__, qpid);
 226         return qpid;
 227 }
 228
 229 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
 230                      struct cxio_ucontext *uctx)
 231 {
 232         struct cxio_qpid_list *entry;
 233
 234         entry = kmalloc(sizeof *entry, GFP_KERNEL);
 235         if (!entry)
 236                 return;
 237         PDBG("%s qpid 0x%x\n", __FUNCTION__, qpid);
 238         entry->qpid = qpid;
 239         mutex_lock(&uctx->lock);
 240         list_add_tail(&entry->entry, &uctx->qpids);
 241         mutex_unlock(&uctx->lock);
 242 }
 243
 244 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 245 {
 246         struct list_head *pos, *nxt;
 247         struct cxio_qpid_list *entry;
 248
 249         mutex_lock(&uctx->lock);
 250         list_for_each_safe(pos, nxt, &uctx->qpids) {
 251                 entry = list_entry(pos, struct cxio_qpid_list, entry);
 252                 list_del_init(&entry->entry);
 253                 if (!(entry->qpid & rdev_p->qpmask))
 254                         cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
 255                 kfree(entry);
 256         }
 257         mutex_unlock(&uctx->lock);
 258 }
 259
 260 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 261 {
 262         INIT_LIST_HEAD(&uctx->qpids);
 263         mutex_init(&uctx->lock);
 264 }
 265
 266 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
 267                    struct t3_wq *wq, struct cxio_ucontext *uctx)
 268 {
 269         int depth = 1UL << wq->size_log2;
 270         int rqsize = 1UL << wq->rq_size_log2;
 271
 272         wq->qpid = get_qpid(rdev_p, uctx);
 273         if (!wq->qpid)
 274                 return -ENOMEM;
 275
 276         wq->rq = kzalloc(depth * sizeof(u64), GFP_KERNEL);
 277         if (!wq->rq)
 278                 goto err1;
 279
 280         wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
 281         if (!wq->rq_addr)
 282                 goto err2;
 283
 284         wq->sq = kzalloc(depth * sizeof(struct t3_swsq), GFP_KERNEL);
 285         if (!wq->sq)
 286                 goto err3;
 287
 288         wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
 289                                              depth * sizeof(union t3_wr),
 290                                              &(wq->dma_addr), GFP_KERNEL);
 291         if (!wq->queue)
 292                 goto err4;
 293
 294         memset(wq->queue, 0, depth * sizeof(union t3_wr));
 295         pci_unmap_addr_set(wq, mapping, wq->dma_addr);
 296         wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
 297         if (!kernel_domain)
 298                 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
 299                                         (wq->qpid << rdev_p->qpshift);
 300         PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __FUNCTION__,
 301              wq->qpid, wq->doorbell, (unsigned long long) wq->udb);
 302         return 0;
 303 err4:
 304         kfree(wq->sq);
 305 err3:
 306         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
 307 err2:
 308         kfree(wq->rq);
 309 err1:
 310         put_qpid(rdev_p, wq->qpid, uctx);
 311         return -ENOMEM;
 312 }
 313
 314 int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 315 {
 316         int err;
 317         err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
 318         kfree(cq->sw_queue);
 319         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 320                           (1UL << (cq->size_log2))
 321                           * sizeof(struct t3_cqe), cq->queue,
 322                           pci_unmap_addr(cq, mapping));
 323         cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
 324         return err;
 325 }
 326
 327 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
 328                     struct cxio_ucontext *uctx)
 329 {
 330         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 331                           (1UL << (wq->size_log2))
 332                           * sizeof(union t3_wr), wq->queue,
 333                           pci_unmap_addr(wq, mapping));
 334         kfree(wq->sq);
 335         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
 336         kfree(wq->rq);
 337         put_qpid(rdev_p, wq->qpid, uctx);
 338         return 0;
 339 }
 340
 341 static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq)
 342 {
 343         struct t3_cqe cqe;
 344
 345         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __FUNCTION__,
 346              wq, cq, cq->sw_rptr, cq->sw_wptr);
 347         memset(&cqe, 0, sizeof(cqe));
 348         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
 349                                  V_CQE_OPCODE(T3_SEND) |
 350                                  V_CQE_TYPE(0) |
 351                                  V_CQE_SWCQE(1) |
 352                                  V_CQE_QPID(wq->qpid) |
 353                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
 354                                                        cq->size_log2)));
 355         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
 356         cq->sw_wptr++;
 357 }
 358
 359 void cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count)
 360 {
 361         u32 ptr;
 362
 363         PDBG("%s wq %p cq %p\n", __FUNCTION__, wq, cq);
 364
 365         /* flush RQ */
 366         PDBG("%s rq_rptr %u rq_wptr %u skip count %u\n", __FUNCTION__,
 367             wq->rq_rptr, wq->rq_wptr, count);
 368         ptr = wq->rq_rptr + count;
 369         while (ptr++ != wq->rq_wptr)
 370                 insert_recv_cqe(wq, cq);
 371 }
 372
 373 static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
 374                           struct t3_swsq *sqp)
 375 {
 376         struct t3_cqe cqe;
 377
 378         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __FUNCTION__,
 379              wq, cq, cq->sw_rptr, cq->sw_wptr);
 380         memset(&cqe, 0, sizeof(cqe));
 381         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
 382                                  V_CQE_OPCODE(sqp->opcode) |
 383                                  V_CQE_TYPE(1) |
 384                                  V_CQE_SWCQE(1) |
 385                                  V_CQE_QPID(wq->qpid) |
 386                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
 387                                                        cq->size_log2)));
 388         cqe.u.scqe.wrid_hi = sqp->sq_wptr;
 389
 390         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
 391         cq->sw_wptr++;
 392 }
 393
 394 void cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
 395 {
 396         __u32 ptr;
 397         struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2);
 398
 399         ptr = wq->sq_rptr + count;
 400         sqp += count;
 401         while (ptr != wq->sq_wptr) {
 402                 insert_sq_cqe(wq, cq, sqp);
 403                 sqp++;
 404                 ptr++;
 405         }
 406 }
 407
 408 /*
 409  * Move all CQEs from the HWCQ into the SWCQ.
 410  */
 411 void cxio_flush_hw_cq(struct t3_cq *cq)
 412 {
 413         struct t3_cqe *cqe, *swcqe;
 414
 415         PDBG("%s cq %p cqid 0x%x\n", __FUNCTION__, cq, cq->cqid);
 416         cqe = cxio_next_hw_cqe(cq);
 417         while (cqe) {
 418                 PDBG("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
 419                      __FUNCTION__, cq->rptr, cq->sw_wptr);
 420                 swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2);
 421                 *swcqe = *cqe;
 422                 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
 423                 cq->sw_wptr++;
 424                 cq->rptr++;
 425                 cqe = cxio_next_hw_cqe(cq);
 426         }
 427 }
 428
 429 static inline int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq)
 430 {
 431         if (CQE_OPCODE(*cqe) == T3_TERMINATE)
 432                 return 0;
 433
 434         if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe))
 435                 return 0;
 436
 437         if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe))
 438                 return 0;
 439
 440         if ((CQE_OPCODE(*cqe) == T3_SEND) && RQ_TYPE(*cqe) &&
 441             Q_EMPTY(wq->rq_rptr, wq->rq_wptr))
 442                 return 0;
 443
 444         return 1;
 445 }
 446
 447 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
 448 {
 449         struct t3_cqe *cqe;
 450         u32 ptr;
 451
 452         *count = 0;
 453         ptr = cq->sw_rptr;
 454         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
 455                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
 456                 if ((SQ_TYPE(*cqe) || (CQE_OPCODE(*cqe) == T3_READ_RESP)) &&
 457                     (CQE_QPID(*cqe) == wq->qpid))
 458                         (*count)++;
 459                 ptr++;
 460         }
 461         PDBG("%s cq %p count %d\n", __FUNCTION__, cq, *count);
 462 }
 463
 464 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
 465 {
 466         struct t3_cqe *cqe;
 467         u32 ptr;
 468
 469         *count = 0;
 470         PDBG("%s count zero %d\n", __FUNCTION__, *count);
 471         ptr = cq->sw_rptr;
 472         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
 473                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
 474                 if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) &&
 475                     (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq))
 476                         (*count)++;
 477                 ptr++;
 478         }
 479         PDBG("%s cq %p count %d\n", __FUNCTION__, cq, *count);
 480 }
 481
 482 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
 483 {
 484         struct rdma_cq_setup setup;
 485         setup.id = 0;
 486         setup.base_addr = 0;    /* NULL address */
 487         setup.size = 1;         /* enable the CQ */
 488         setup.credits = 0;
 489
 490         /* force SGE to redirect to RspQ and interrupt */
 491         setup.credit_thres = 0;
 492         setup.ovfl_mode = 1;
 493         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 494 }
 495
 496 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
 497 {
 498         int err;
 499         u64 sge_cmd, ctx0, ctx1;
 500         u64 base_addr;
 501         struct t3_modify_qp_wr *wqe;
 502         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
 503
 504
 505         if (!skb) {
 506                 PDBG("%s alloc_skb failed\n", __FUNCTION__);
 507                 return -ENOMEM;
 508         }
 509         err = cxio_hal_init_ctrl_cq(rdev_p);
 510         if (err) {
 511                 PDBG("%s err %d initializing ctrl_cq\n", __FUNCTION__, err);
 512                 return err;
 513         }
 514         rdev_p->ctrl_qp.workq = dma_alloc_coherent(
 515                                         &(rdev_p->rnic_info.pdev->dev),
 516                                         (1 << T3_CTRL_QP_SIZE_LOG2) *
 517                                         sizeof(union t3_wr),
 518                                         &(rdev_p->ctrl_qp.dma_addr),
 519                                         GFP_KERNEL);
 520         if (!rdev_p->ctrl_qp.workq) {
 521                 PDBG("%s dma_alloc_coherent failed\n", __FUNCTION__);
 522                 return -ENOMEM;
 523         }
 524         pci_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
 525                            rdev_p->ctrl_qp.dma_addr);
 526         rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
 527         memset(rdev_p->ctrl_qp.workq, 0,
 528                (1 << T3_CTRL_QP_SIZE_LOG2) * sizeof(union t3_wr));
 529
 530         mutex_init(&rdev_p->ctrl_qp.lock);
 531         init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
 532
 533         /* update HW Ctrl QP context */
 534         base_addr = rdev_p->ctrl_qp.dma_addr;
 535         base_addr >>= 12;
 536         ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
 537                 V_EC_BASE_LO((u32) base_addr & 0xffff));
 538         ctx0 <<= 32;
 539         ctx0 |= V_EC_CREDITS(FW_WR_NUM);
 540         base_addr >>= 16;
 541         ctx1 = (u32) base_addr;
 542         base_addr >>= 32;
 543         ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) |
 544                         V_EC_TYPE(0) | V_EC_GEN(1) |
 545                         V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32;
 546         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
 547         memset(wqe, 0, sizeof(*wqe));
 548         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 1,
 549                        T3_CTL_QP_TID, 7);
 550         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
 551         sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
 552         wqe->sge_cmd = cpu_to_be64(sge_cmd);
 553         wqe->ctx1 = cpu_to_be64(ctx1);
 554         wqe->ctx0 = cpu_to_be64(ctx0);
 555         PDBG("CtrlQP dma_addr 0x%llx workq %p size %d\n",
 556              (unsigned long long) rdev_p->ctrl_qp.dma_addr,
 557              rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
 558         skb->priority = CPL_PRIORITY_CONTROL;
 559         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
 560 }
 561
 562 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
 563 {
 564         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 565                           (1UL << T3_CTRL_QP_SIZE_LOG2)
 566                           * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
 567                           pci_unmap_addr(&rdev_p->ctrl_qp, mapping));
 568         return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
 569 }
 570
 571 /* write len bytes of data into addr (32B aligned address)
 572  * If data is NULL, clear len byte of memory to zero.
 573  * caller aquires the ctrl_qp lock before the call
 574  */
 575 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
 576                                       u32 len, void *data, int completion)
 577 {
 578         u32 i, nr_wqe, copy_len;
 579         u8 *copy_data;
 580         u8 wr_len, utx_len;     /* lenght in 8 byte flit */
 581         enum t3_wr_flags flag;
 582         __be64 *wqe;
 583         u64 utx_cmd;
 584         addr &= 0x7FFFFFF;
 585         nr_wqe = len % 96 ? len / 96 + 1 : len / 96;    /* 96B max per WQE */
 586         PDBG("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
 587              __FUNCTION__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
 588              nr_wqe, data, addr);
 589         utx_len = 3;            /* in 32B unit */
 590         for (i = 0; i < nr_wqe; i++) {
 591                 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
 592                            T3_CTRL_QP_SIZE_LOG2)) {
 593                         PDBG("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, "
 594                              "wait for more space i %d\n", __FUNCTION__,
 595                              rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
 596                         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 597                                              !Q_FULL(rdev_p->ctrl_qp.rptr,
 598                                                      rdev_p->ctrl_qp.wptr,
 599                                                      T3_CTRL_QP_SIZE_LOG2))) {
 600                                 PDBG("%s ctrl_qp workq interrupted\n",
 601                                      __FUNCTION__);
 602                                 return -ERESTARTSYS;
 603                         }
 604                         PDBG("%s ctrl_qp wakeup, continue posting work request "
 605                              "i %d\n", __FUNCTION__, i);
 606                 }
 607                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
 608                                                 (1 << T3_CTRL_QP_SIZE_LOG2)));
 609                 flag = 0;
 610                 if (i == (nr_wqe - 1)) {
 611                         /* last WQE */
 612                         flag = completion ? T3_COMPLETION_FLAG : 0;
 613                         if (len % 32)
 614                                 utx_len = len / 32 + 1;
 615                         else
 616                                 utx_len = len / 32;
 617                 }
 618
 619                 /*
 620                  * Force a CQE to return the credit to the workq in case
 621                  * we posted more than half the max QP size of WRs
 622                  */
 623                 if ((i != 0) &&
 624                     (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) {
 625                         flag = T3_COMPLETION_FLAG;
 626                         PDBG("%s force completion at i %d\n", __FUNCTION__, i);
 627                 }
 628
 629                 /* build the utx mem command */
 630                 wqe += (sizeof(struct t3_bypass_wr) >> 3);
 631                 utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3);
 632                 utx_cmd <<= 32;
 633                 utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1);
 634                 *wqe = cpu_to_be64(utx_cmd);
 635                 wqe++;
 636                 copy_data = (u8 *) data + i * 96;
 637                 copy_len = len > 96 ? 96 : len;
 638
 639                 /* clear memory content if data is NULL */
 640                 if (data)
 641                         memcpy(wqe, copy_data, copy_len);
 642                 else
 643                         memset(wqe, 0, copy_len);
 644                 if (copy_len % 32)
 645                         memset(((u8 *) wqe) + copy_len, 0,
 646                                32 - (copy_len % 32));
 647                 wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 +
 648                          (utx_len << 2);
 649                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
 650                               (1 << T3_CTRL_QP_SIZE_LOG2)));
 651
 652                 /* wptr in the WRID[31:0] */
 653                 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
 654
 655                 /*
 656                  * This must be the last write with a memory barrier
 657                  * for the genbit
 658                  */
 659                 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
 660                                Q_GENBIT(rdev_p->ctrl_qp.wptr,
 661                                         T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
 662                                wr_len);
 663                 if (flag == T3_COMPLETION_FLAG)
 664                         ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
 665                 len -= 96;
 666                 rdev_p->ctrl_qp.wptr++;
 667         }
 668         return 0;
 669 }
 670
 671 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl, and pbl_size
 672  * OUT: stag index, actual pbl_size, pbl_addr allocated.
 673  * TBD: shared memory region support
 674  */
 675 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
 676                          u32 *stag, u8 stag_state, u32 pdid,
 677                          enum tpt_mem_type type, enum tpt_mem_perm perm,
 678                          u32 zbva, u64 to, u32 len, u8 page_size, __be64 *pbl,
 679                          u32 *pbl_size, u32 *pbl_addr)
 680 {
 681         int err;
 682         struct tpt_entry tpt;
 683         u32 stag_idx;
 684         u32 wptr;
 685         int rereg = (*stag != T3_STAG_UNSET);
 686
 687         stag_state = stag_state > 0;
 688         stag_idx = (*stag) >> 8;
 689
 690         if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) {
 691                 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
 692                 if (!stag_idx)
 693                         return -ENOMEM;
 694                 *stag = (stag_idx << 8) | ((*stag) & 0xFF);
 695         }
 696         PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
 697              __FUNCTION__, stag_state, type, pdid, stag_idx);
 698
 699         if (reset_tpt_entry)
 700                 cxio_hal_pblpool_free(rdev_p, *pbl_addr, *pbl_size << 3);
 701         else if (!rereg) {
 702                 *pbl_addr = cxio_hal_pblpool_alloc(rdev_p, *pbl_size << 3);
 703                 if (!*pbl_addr) {
 704                         return -ENOMEM;
 705                 }
 706         }
 707
 708         mutex_lock(&rdev_p->ctrl_qp.lock);
 709
 710         /* write PBL first if any - update pbl only if pbl list exist */
 711         if (pbl) {
 712
 713                 PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
 714                      __FUNCTION__, *pbl_addr, rdev_p->rnic_info.pbl_base,
 715                      *pbl_size);
 716                 err = cxio_hal_ctrl_qp_write_mem(rdev_p,
 717                                 (*pbl_addr >> 5),
 718                                 (*pbl_size << 3), pbl, 0);
 719                 if (err)
 720                         goto ret;
 721         }
 722
 723         /* write TPT entry */
 724         if (reset_tpt_entry)
 725                 memset(&tpt, 0, sizeof(tpt));
 726         else {
 727                 tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID |
 728                                 V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) |
 729                                 V_TPT_STAG_STATE(stag_state) |
 730                                 V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
 731                 BUG_ON(page_size >= 28);
 732                 tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
 733                                 F_TPT_MW_BIND_ENABLE |
 734                                 V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
 735                                 V_TPT_PAGE_SIZE(page_size));
 736                 tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 :
 737                                     cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, *pbl_addr)>>3));
 738                 tpt.len = cpu_to_be32(len);
 739                 tpt.va_hi = cpu_to_be32((u32) (to >> 32));
 740                 tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL));
 741                 tpt.rsvd_bind_cnt_or_pstag = 0;
 742                 tpt.rsvd_pbl_size = reset_tpt_entry ? 0 :
 743                                   cpu_to_be32(V_TPT_PBL_SIZE((*pbl_size) >> 2));
 744         }
 745         err = cxio_hal_ctrl_qp_write_mem(rdev_p,
 746                                        stag_idx +
 747                                        (rdev_p->rnic_info.tpt_base >> 5),
 748                                        sizeof(tpt), &tpt, 1);
 749
 750         /* release the stag index to free pool */
 751         if (reset_tpt_entry)
 752                 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
 753 ret:
 754         wptr = rdev_p->ctrl_qp.wptr;
 755         mutex_unlock(&rdev_p->ctrl_qp.lock);
 756         if (!err)
 757                 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 758                                              SEQ32_GE(rdev_p->ctrl_qp.rptr,
 759                                                       wptr)))
 760                         return -ERESTARTSYS;
 761         return err;
 762 }
 763
 764 /* IN : stag key, pdid, pbl_size
 765  * Out: stag index, actaul pbl_size, and pbl_addr allocated.
 766  */
 767 int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid,
 768                        enum tpt_mem_perm perm, u32 * pbl_size, u32 * pbl_addr)
 769 {
 770         *stag = T3_STAG_UNSET;
 771         return (__cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_NON_SHARED_MR,
 772                               perm, 0, 0ULL, 0, 0, NULL, pbl_size, pbl_addr));
 773 }
 774
 775 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
 776                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
 777                            u8 page_size, __be64 *pbl, u32 *pbl_size,
 778                            u32 *pbl_addr)
 779 {
 780         *stag = T3_STAG_UNSET;
 781         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
 782                              zbva, to, len, page_size, pbl, pbl_size, pbl_addr);
 783 }
 784
 785 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
 786                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
 787                            u8 page_size, __be64 *pbl, u32 *pbl_size,
 788                            u32 *pbl_addr)
 789 {
 790         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
 791                              zbva, to, len, page_size, pbl, pbl_size, pbl_addr);
 792 }
 793
 794 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
 795                    u32 pbl_addr)
 796 {
 797         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0, NULL,
 798                              &pbl_size, &pbl_addr);
 799 }
 800
 801 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
 802 {
 803         u32 pbl_size = 0;
 804         *stag = T3_STAG_UNSET;
 805         return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
 806                              NULL, &pbl_size, NULL);
 807 }
 808
 809 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
 810 {
 811         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0, NULL,
 812                              NULL, NULL);
 813 }
 814
 815 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
 816 {
 817         struct t3_rdma_init_wr *wqe;
 818         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC);
 819         if (!skb)
 820                 return -ENOMEM;
 821         PDBG("%s rdev_p %p\n", __FUNCTION__, rdev_p);
 822         wqe = (struct t3_rdma_init_wr *) __skb_put(skb, sizeof(*wqe));
 823         wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT));
 824         wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) |
 825                                            V_FW_RIWR_LEN(sizeof(*wqe) >> 3));
 826         wqe->wrid.id1 = 0;
 827         wqe->qpid = cpu_to_be32(attr->qpid);
 828         wqe->pdid = cpu_to_be32(attr->pdid);
 829         wqe->scqid = cpu_to_be32(attr->scqid);
 830         wqe->rcqid = cpu_to_be32(attr->rcqid);
 831         wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
 832         wqe->rq_size = cpu_to_be32(attr->rq_size);
 833         wqe->mpaattrs = attr->mpaattrs;
 834         wqe->qpcaps = attr->qpcaps;
 835         wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss);
 836         wqe->flags = cpu_to_be32(attr->flags);
 837         wqe->ord = cpu_to_be32(attr->ord);
 838         wqe->ird = cpu_to_be32(attr->ird);
 839         wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr);
 840         wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
 841         wqe->rsvd = 0;
 842         skb->priority = 0;      /* 0=>ToeQ; 1=>CtrlQ */
 843         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
 844 }
 845
 846 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
 847 {
 848         cxio_ev_cb = ev_cb;
 849 }
 850
 851 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
 852 {
 853         cxio_ev_cb = NULL;
 854 }
 855
 856 static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb)
 857 {
 858         static int cnt;
 859         struct cxio_rdev *rdev_p = NULL;
 860         struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data;
 861         PDBG("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x"
 862              " se %0x notify %0x cqbranch %0x creditth %0x\n",
 863              cnt, __FUNCTION__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg),
 864              RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg),
 865              RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg),
 866              RSPQ_CREDIT_THRESH(rsp_msg));
 867         PDBG("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d "
 868              "len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
 869              CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe),
 870              CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe),
 871              CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe),
 872              CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe));
 873         rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
 874         if (!rdev_p) {
 875                 PDBG("%s called by t3cdev %p with null ulp\n", __FUNCTION__,
 876                      t3cdev_p);
 877                 return 0;
 878         }
 879         if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) {
 880                 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
 881                 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
 882                 dev_kfree_skb_irq(skb);
 883         } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8)
 884                 dev_kfree_skb_irq(skb);
 885         else if (cxio_ev_cb)
 886                 (*cxio_ev_cb) (rdev_p, skb);
 887         else
 888                 dev_kfree_skb_irq(skb);
 889         cnt++;
 890         return 0;
 891 }
 892
 893 /* Caller takes care of locking if needed */
 894 int cxio_rdev_open(struct cxio_rdev *rdev_p)
 895 {
 896         struct net_device *netdev_p = NULL;
 897         int err = 0;
 898         if (strlen(rdev_p->dev_name)) {
 899                 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
 900                         return -EBUSY;
 901                 }
 902                 netdev_p = dev_get_by_name(rdev_p->dev_name);
 903                 if (!netdev_p) {
 904                         return -EINVAL;
 905                 }
 906                 dev_put(netdev_p);
 907         } else if (rdev_p->t3cdev_p) {
 908                 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
 909                         return -EBUSY;
 910                 }
 911                 netdev_p = rdev_p->t3cdev_p->lldev;
 912                 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
 913                         T3_MAX_DEV_NAME_LEN);
 914         } else {
 915                 PDBG("%s t3cdev_p or dev_name must be set\n", __FUNCTION__);
 916                 return -EINVAL;
 917         }
 918
 919         list_add_tail(&rdev_p->entry, &rdev_list);
 920
 921         PDBG("%s opening rnic dev %s\n", __FUNCTION__, rdev_p->dev_name);
 922         memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
 923         if (!rdev_p->t3cdev_p)
 924                 rdev_p->t3cdev_p = T3CDEV(netdev_p);
 925         rdev_p->t3cdev_p->ulp = (void *) rdev_p;
 926         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
 927                                          &(rdev_p->rnic_info));
 928         if (err) {
 929                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
 930                      __FUNCTION__, rdev_p->t3cdev_p, err);
 931                 goto err1;
 932         }
 933         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
 934                                     &(rdev_p->port_info));
 935         if (err) {
 936                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
 937                      __FUNCTION__, rdev_p->t3cdev_p, err);
 938                 goto err1;
 939         }
 940
 941         /*
 942          * qpshift is the number of bits to shift the qpid left in order
 943          * to get the correct address of the doorbell for that qp.
 944          */
 945         cxio_init_ucontext(rdev_p, &rdev_p->uctx);
 946         rdev_p->qpshift = PAGE_SHIFT -
 947                           ilog2(65536 >>
 948                                     ilog2(rdev_p->rnic_info.udbell_len >>
 949                                               PAGE_SHIFT));
 950         rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
 951         rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
 952         PDBG("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d "
 953              "pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
 954              __FUNCTION__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
 955              rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
 956              rdev_p->rnic_info.pbl_base,
 957              rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
 958              rdev_p->rnic_info.rqt_top);
 959         PDBG("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu "
 960              "qpnr %d qpmask 0x%x\n",
 961              rdev_p->rnic_info.udbell_len,
 962              rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
 963              rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
 964
 965         err = cxio_hal_init_ctrl_qp(rdev_p);
 966         if (err) {
 967                 printk(KERN_ERR "%s error %d initializing ctrl_qp.\n",
 968                        __FUNCTION__, err);
 969                 goto err1;
 970         }
 971         err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
 972                                      0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ,
 973                                      T3_MAX_NUM_PD);
 974         if (err) {
 975                 printk(KERN_ERR "%s error %d initializing hal resources.\n",
 976                        __FUNCTION__, err);
 977                 goto err2;
 978         }
 979         err = cxio_hal_pblpool_create(rdev_p);
 980         if (err) {
 981                 printk(KERN_ERR "%s error %d initializing pbl mem pool.\n",
 982                        __FUNCTION__, err);
 983                 goto err3;
 984         }
 985         err = cxio_hal_rqtpool_create(rdev_p);
 986         if (err) {
 987                 printk(KERN_ERR "%s error %d initializing rqt mem pool.\n",
 988                        __FUNCTION__, err);
 989                 goto err4;
 990         }
 991         return 0;
 992 err4:
 993         cxio_hal_pblpool_destroy(rdev_p);
 994 err3:
 995         cxio_hal_destroy_resource(rdev_p->rscp);
 996 err2:
 997         cxio_hal_destroy_ctrl_qp(rdev_p);
 998 err1:
 999         list_del(&rdev_p->entry);
1000         return err;
1001 }
1002
1003 void cxio_rdev_close(struct cxio_rdev *rdev_p)
1004 {
1005         if (rdev_p) {
1006                 cxio_hal_pblpool_destroy(rdev_p);
1007                 cxio_hal_rqtpool_destroy(rdev_p);
1008                 list_del(&rdev_p->entry);
1009                 rdev_p->t3cdev_p->ulp = NULL;
1010                 cxio_hal_destroy_ctrl_qp(rdev_p);
1011                 cxio_hal_destroy_resource(rdev_p->rscp);
1012         }
1013 }
1014
1015 int __init cxio_hal_init(void)
1016 {
1017         if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI))
1018                 return -ENOMEM;
1019         t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler);
1020         return 0;
1021 }
1022
1023 void __exit cxio_hal_exit(void)
1024 {
1025         struct cxio_rdev *rdev, *tmp;
1026
1027         t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL);
1028         list_for_each_entry_safe(rdev, tmp, &rdev_list, entry)
1029                 cxio_rdev_close(rdev);
1030         cxio_hal_destroy_rhdl_resource();
1031 }
1032
1033 static inline void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq)
1034 {
1035         struct t3_swsq *sqp;
1036         __u32 ptr = wq->sq_rptr;
1037         int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr);
1038
1039         sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1040         while (count--)
1041                 if (!sqp->signaled) {
1042                         ptr++;
1043                         sqp = wq->sq + Q_PTR2IDX(ptr,  wq->sq_size_log2);
1044                 } else if (sqp->complete) {
1045
1046                         /*
1047                          * Insert this completed cqe into the swcq.
1048                          */
1049                         PDBG("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1050                              __FUNCTION__, Q_PTR2IDX(ptr,  wq->sq_size_log2),
1051                              Q_PTR2IDX(cq->sw_wptr, cq->size_log2));
1052                         sqp->cqe.header |= htonl(V_CQE_SWCQE(1));
1053                         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2))
1054                                 = sqp->cqe;
1055                         cq->sw_wptr++;
1056                         sqp->signaled = 0;
1057                         break;
1058                 } else
1059                         break;
1060 }
1061
1062 static inline void create_read_req_cqe(struct t3_wq *wq,
1063                                        struct t3_cqe *hw_cqe,
1064                                        struct t3_cqe *read_cqe)
1065 {
1066         read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr;
1067         read_cqe->len = wq->oldest_read->read_len;
1068         read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) |
1069                                  V_CQE_SWCQE(SW_CQE(*hw_cqe)) |
1070                                  V_CQE_OPCODE(T3_READ_REQ) |
1071                                  V_CQE_TYPE(1));
1072 }
1073
1074 /*
1075  * Return a ptr to the next read wr in the SWSQ or NULL.
1076  */
1077 static inline void advance_oldest_read(struct t3_wq *wq)
1078 {
1079
1080         u32 rptr = wq->oldest_read - wq->sq + 1;
1081         u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2);
1082
1083         while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) {
1084                 wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2);
1085
1086                 if (wq->oldest_read->opcode == T3_READ_REQ)
1087                         return;
1088                 rptr++;
1089         }
1090         wq->oldest_read = NULL;
1091 }
1092
1093 /*
1094  * cxio_poll_cq
1095  *
1096  * Caller must:
1097  *     check the validity of the first CQE,
1098  *     supply the wq assicated with the qpid.
1099  *
1100  * credit: cq credit to return to sge.
1101  * cqe_flushed: 1 iff the CQE is flushed.
1102  * cqe: copy of the polled CQE.
1103  *
1104  * return value:
1105  *     0       CQE returned,
1106  *    -1       CQE skipped, try again.
1107  */
1108 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
1109                      u8 *cqe_flushed, u64 *cookie, u32 *credit)
1110 {
1111         int ret = 0;
1112         struct t3_cqe *hw_cqe, read_cqe;
1113
1114         *cqe_flushed = 0;
1115         *credit = 0;
1116         hw_cqe = cxio_next_cqe(cq);
1117
1118         PDBG("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x"
1119              " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1120              __FUNCTION__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe),
1121              CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe),
1122              CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe),
1123              CQE_WRID_LOW(*hw_cqe));
1124
1125         /*
1126          * skip cqe's not affiliated with a QP.
1127          */
1128         if (wq == NULL) {
1129                 ret = -1;
1130                 goto skip_cqe;
1131         }
1132
1133         /*
1134          * Gotta tweak READ completions:
1135          *      1) the cqe doesn't contain the sq_wptr from the wr.
1136          *      2) opcode not reflected from the wr.
1137          *      3) read_len not reflected from the wr.
1138          *      4) cq_type is RQ_TYPE not SQ_TYPE.
1139          */
1140         if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) {
1141
1142                 /*
1143                  * Don't write to the HWCQ, so create a new read req CQE
1144                  * in local memory.
1145                  */
1146                 create_read_req_cqe(wq, hw_cqe, &read_cqe);
1147                 hw_cqe = &read_cqe;
1148                 advance_oldest_read(wq);
1149         }
1150
1151         /*
1152          * T3A: Discard TERMINATE CQEs.
1153          */
1154         if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) {
1155                 ret = -1;
1156                 wq->error = 1;
1157                 goto skip_cqe;
1158         }
1159
1160         if (CQE_STATUS(*hw_cqe) || wq->error) {
1161                 *cqe_flushed = wq->error;
1162                 wq->error = 1;
1163
1164                 /*
1165                  * T3A inserts errors into the CQE.  We cannot return
1166                  * these as work completions.
1167                  */
1168                 /* incoming write failures */
1169                 if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE)
1170                      && RQ_TYPE(*hw_cqe)) {
1171                         ret = -1;
1172                         goto skip_cqe;
1173                 }
1174                 /* incoming read request failures */
1175                 if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) {
1176                         ret = -1;
1177                         goto skip_cqe;
1178                 }
1179
1180                 /* incoming SEND with no receive posted failures */
1181                 if ((CQE_OPCODE(*hw_cqe) == T3_SEND) && RQ_TYPE(*hw_cqe) &&
1182                     Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1183                         ret = -1;
1184                         goto skip_cqe;
1185                 }
1186                 goto proc_cqe;
1187         }
1188
1189         /*
1190          * RECV completion.
1191          */
1192         if (RQ_TYPE(*hw_cqe)) {
1193
1194                 /*
1195                  * HW only validates 4 bits of MSN.  So we must validate that
1196                  * the MSN in the SEND is the next expected MSN.  If its not,
1197                  * then we complete this with TPT_ERR_MSN and mark the wq in
1198                  * error.
1199                  */
1200                 if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) {
1201                         wq->error = 1;
1202                         hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN));
1203                         goto proc_cqe;
1204                 }
1205                 goto proc_cqe;
1206         }
1207
1208         /*
1209          * If we get here its a send completion.
1210          *
1211          * Handle out of order completion. These get stuffed
1212          * in the SW SQ. Then the SW SQ is walked to move any
1213          * now in-order completions into the SW CQ.  This handles
1214          * 2 cases:
1215          *      1) reaping unsignaled WRs when the first subsequent
1216          *         signaled WR is completed.
1217          *      2) out of order read completions.
1218          */
1219         if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) {
1220                 struct t3_swsq *sqp;
1221
1222                 PDBG("%s out of order completion going in swsq at idx %ld\n",
1223                      __FUNCTION__,
1224                      Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2));
1225                 sqp = wq->sq +
1226                       Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2);
1227                 sqp->cqe = *hw_cqe;
1228                 sqp->complete = 1;
1229                 ret = -1;
1230                 goto flush_wq;
1231         }
1232
1233 proc_cqe:
1234         *cqe = *hw_cqe;
1235
1236         /*
1237          * Reap the associated WR(s) that are freed up with this
1238          * completion.
1239          */
1240         if (SQ_TYPE(*hw_cqe)) {
1241                 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1242                 PDBG("%s completing sq idx %ld\n", __FUNCTION__,
1243                      Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1244                 *cookie = (wq->sq +
1245                            Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2))->wr_id;
1246                 wq->sq_rptr++;
1247         } else {
1248                 PDBG("%s completing rq idx %ld\n", __FUNCTION__,
1249                      Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1250                 *cookie = *(wq->rq + Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1251                 wq->rq_rptr++;
1252         }
1253
1254 flush_wq:
1255         /*
1256          * Flush any completed cqes that are now in-order.
1257          */
1258         flush_completed_wrs(wq, cq);
1259
1260 skip_cqe:
1261         if (SW_CQE(*hw_cqe)) {
1262                 PDBG("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1263                      __FUNCTION__, cq, cq->cqid, cq->sw_rptr);
1264                 ++cq->sw_rptr;
1265         } else {
1266                 PDBG("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1267                      __FUNCTION__, cq, cq->cqid, cq->rptr);
1268                 ++cq->rptr;
1269
1270                 /*
1271                  * T3A: compute credits.
1272                  */
1273                 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1)))
1274                     || ((cq->rptr - cq->wptr) >= 128)) {
1275                         *credit = cq->rptr - cq->wptr;
1276                         cq->wptr = cq->rptr;
1277                 }
1278         }
1279         return ret;
1280 }