drivers/i2c/busses/i2c-ocores.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
   4  * (https://opencores.org/project/i2c/overview)
   5  *
   6  * Peter Korsgaard <peter@korsgaard.com>
   7  *
   8  * Support for the GRLIB port of the controller by
   9  * Andreas Larsson <andreas@gaisler.com>
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/err.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/errno.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/i2c.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/wait.h>
  22 #include <linux/platform_data/i2c-ocores.h>
  23 #include <linux/slab.h>
  24 #include <linux/io.h>
  25 #include <linux/log2.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/jiffies.h>
  28
  29 /*
  30  * 'process_lock' exists because ocores_process() and ocores_process_timeout()
  31  * can't run in parallel.
  32  */
  33 struct ocores_i2c {
  34         void __iomem *base;
  35         int iobase;
  36         u32 reg_shift;
  37         u32 reg_io_width;
  38         wait_queue_head_t wait;
  39         struct i2c_adapter adap;
  40         struct i2c_msg *msg;
  41         int pos;
  42         int nmsgs;
  43         int state; /* see STATE_ */
  44         spinlock_t process_lock;
  45         struct clk *clk;
  46         int ip_clock_khz;
  47         int bus_clock_khz;
  48         void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
  49         u8 (*getreg)(struct ocores_i2c *i2c, int reg);
  50 };
  51
  52 /* registers */
  53 #define OCI2C_PRELOW            0
  54 #define OCI2C_PREHIGH           1
  55 #define OCI2C_CONTROL           2
  56 #define OCI2C_DATA              3
  57 #define OCI2C_CMD               4 /* write only */
  58 #define OCI2C_STATUS            4 /* read only, same address as OCI2C_CMD */
  59
  60 #define OCI2C_CTRL_IEN          0x40
  61 #define OCI2C_CTRL_EN           0x80
  62
  63 #define OCI2C_CMD_START         0x91
  64 #define OCI2C_CMD_STOP          0x41
  65 #define OCI2C_CMD_READ          0x21
  66 #define OCI2C_CMD_WRITE         0x11
  67 #define OCI2C_CMD_READ_ACK      0x21
  68 #define OCI2C_CMD_READ_NACK     0x29
  69 #define OCI2C_CMD_IACK          0x01
  70
  71 #define OCI2C_STAT_IF           0x01
  72 #define OCI2C_STAT_TIP          0x02
  73 #define OCI2C_STAT_ARBLOST      0x20
  74 #define OCI2C_STAT_BUSY         0x40
  75 #define OCI2C_STAT_NACK         0x80
  76
  77 #define STATE_DONE              0
  78 #define STATE_START             1
  79 #define STATE_WRITE             2
  80 #define STATE_READ              3
  81 #define STATE_ERROR             4
  82
  83 #define TYPE_OCORES             0
  84 #define TYPE_GRLIB              1
  85
  86 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
  87 {
  88         iowrite8(value, i2c->base + (reg << i2c->reg_shift));
  89 }
  90
  91 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
  92 {
  93         iowrite16(value, i2c->base + (reg << i2c->reg_shift));
  94 }
  95
  96 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
  97 {
  98         iowrite32(value, i2c->base + (reg << i2c->reg_shift));
  99 }
 100
 101 static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
 102 {
 103         iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
 104 }
 105
 106 static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
 107 {
 108         iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
 109 }
 110
 111 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
 112 {
 113         return ioread8(i2c->base + (reg << i2c->reg_shift));
 114 }
 115
 116 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
 117 {
 118         return ioread16(i2c->base + (reg << i2c->reg_shift));
 119 }
 120
 121 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
 122 {
 123         return ioread32(i2c->base + (reg << i2c->reg_shift));
 124 }
 125
 126 static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
 127 {
 128         return ioread16be(i2c->base + (reg << i2c->reg_shift));
 129 }
 130
 131 static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
 132 {
 133         return ioread32be(i2c->base + (reg << i2c->reg_shift));
 134 }
 135
 136 static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value)
 137 {
 138         outb(value, i2c->iobase + reg);
 139 }
 140
 141 static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg)
 142 {
 143         return inb(i2c->iobase + reg);
 144 }
 145
 146 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
 147 {
 148         i2c->setreg(i2c, reg, value);
 149 }
 150
 151 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
 152 {
 153         return i2c->getreg(i2c, reg);
 154 }
 155
 156 static void ocores_process(struct ocores_i2c *i2c, u8 stat)
 157 {
 158         struct i2c_msg *msg = i2c->msg;
 159         unsigned long flags;
 160
 161         /*
 162          * If we spin here is because we are in timeout, so we are going
 163          * to be in STATE_ERROR. See ocores_process_timeout()
 164          */
 165         spin_lock_irqsave(&i2c->process_lock, flags);
 166
 167         if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
 168                 /* stop has been sent */
 169                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
 170                 wake_up(&i2c->wait);
 171                 goto out;
 172         }
 173
 174         /* error? */
 175         if (stat & OCI2C_STAT_ARBLOST) {
 176                 i2c->state = STATE_ERROR;
 177                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 178                 goto out;
 179         }
 180
 181         if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
 182                 i2c->state =
 183                         (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
 184
 185                 if (stat & OCI2C_STAT_NACK) {
 186                         i2c->state = STATE_ERROR;
 187                         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 188                         goto out;
 189                 }
 190         } else {
 191                 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
 192         }
 193
 194         /* end of msg? */
 195         if (i2c->pos == msg->len) {
 196                 i2c->nmsgs--;
 197                 i2c->msg++;
 198                 i2c->pos = 0;
 199                 msg = i2c->msg;
 200
 201                 if (i2c->nmsgs) {       /* end? */
 202                         /* send start? */
 203                         if (!(msg->flags & I2C_M_NOSTART)) {
 204                                 u8 addr = i2c_8bit_addr_from_msg(msg);
 205
 206                                 i2c->state = STATE_START;
 207
 208                                 oc_setreg(i2c, OCI2C_DATA, addr);
 209                                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
 210                                 goto out;
 211                         }
 212                         i2c->state = (msg->flags & I2C_M_RD)
 213                                 ? STATE_READ : STATE_WRITE;
 214                 } else {
 215                         i2c->state = STATE_DONE;
 216                         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 217                         goto out;
 218                 }
 219         }
 220
 221         if (i2c->state == STATE_READ) {
 222                 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
 223                           OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
 224         } else {
 225                 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
 226                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
 227         }
 228
 229 out:
 230         spin_unlock_irqrestore(&i2c->process_lock, flags);
 231 }
 232
 233 static irqreturn_t ocores_isr(int irq, void *dev_id)
 234 {
 235         struct ocores_i2c *i2c = dev_id;
 236         u8 stat = oc_getreg(i2c, OCI2C_STATUS);
 237
 238         if (!(stat & OCI2C_STAT_IF))
 239                 return IRQ_NONE;
 240
 241         ocores_process(i2c, stat);
 242
 243         return IRQ_HANDLED;
 244 }
 245
 246 /**
 247  * Process timeout event
 248  * @i2c: ocores I2C device instance
 249  */
 250 static void ocores_process_timeout(struct ocores_i2c *i2c)
 251 {
 252         unsigned long flags;
 253
 254         spin_lock_irqsave(&i2c->process_lock, flags);
 255         i2c->state = STATE_ERROR;
 256         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 257         spin_unlock_irqrestore(&i2c->process_lock, flags);
 258 }
 259
 260 /**
 261  * Wait until something change in a given register
 262  * @i2c: ocores I2C device instance
 263  * @reg: register to query
 264  * @mask: bitmask to apply on register value
 265  * @val: expected result
 266  * @timeout: timeout in jiffies
 267  *
 268  * Timeout is necessary to avoid to stay here forever when the chip
 269  * does not answer correctly.
 270  *
 271  * Return: 0 on success, -ETIMEDOUT on timeout
 272  */
 273 static int ocores_wait(struct ocores_i2c *i2c,
 274                        int reg, u8 mask, u8 val,
 275                        const unsigned long timeout)
 276 {
 277         unsigned long j;
 278
 279         j = jiffies + timeout;
 280         while (1) {
 281                 u8 status = oc_getreg(i2c, reg);
 282
 283                 if ((status & mask) == val)
 284                         break;
 285
 286                 if (time_after(jiffies, j))
 287                         return -ETIMEDOUT;
 288         }
 289         return 0;
 290 }
 291
 292 /**
 293  * Wait until is possible to process some data
 294  * @i2c: ocores I2C device instance
 295  *
 296  * Used when the device is in polling mode (interrupts disabled).
 297  *
 298  * Return: 0 on success, -ETIMEDOUT on timeout
 299  */
 300 static int ocores_poll_wait(struct ocores_i2c *i2c)
 301 {
 302         u8 mask;
 303         int err;
 304
 305         if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
 306                 /* transfer is over */
 307                 mask = OCI2C_STAT_BUSY;
 308         } else {
 309                 /* on going transfer */
 310                 mask = OCI2C_STAT_TIP;
 311                 /*
 312                  * We wait for the data to be transferred (8bit),
 313                  * then we start polling on the ACK/NACK bit
 314                  */
 315                 udelay((8 * 1000) / i2c->bus_clock_khz);
 316         }
 317
 318         /*
 319          * once we are here we expect to get the expected result immediately
 320          * so if after 1ms we timeout then something is broken.
 321          */
 322         err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1));
 323         if (err)
 324                 dev_warn(i2c->adap.dev.parent,
 325                          "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
 326                          __func__, mask);
 327         return err;
 328 }
 329
 330 /**
 331  * It handles an IRQ-less transfer
 332  * @i2c: ocores I2C device instance
 333  *
 334  * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
 335  * (only that IRQ are not produced). This means that we can re-use entirely
 336  * ocores_isr(), we just add our polling code around it.
 337  *
 338  * It can run in atomic context
 339  */
 340 static void ocores_process_polling(struct ocores_i2c *i2c)
 341 {
 342         while (1) {
 343                 irqreturn_t ret;
 344                 int err;
 345
 346                 err = ocores_poll_wait(i2c);
 347                 if (err) {
 348                         i2c->state = STATE_ERROR;
 349                         break; /* timeout */
 350                 }
 351
 352                 ret = ocores_isr(-1, i2c);
 353                 if (ret == IRQ_NONE)
 354                         break; /* all messages have been transferred */
 355         }
 356 }
 357
 358 static int ocores_xfer_core(struct ocores_i2c *i2c,
 359                             struct i2c_msg *msgs, int num,
 360                             bool polling)
 361 {
 362         int ret;
 363         u8 ctrl;
 364
 365         ctrl = oc_getreg(i2c, OCI2C_CONTROL);
 366         if (polling)
 367                 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
 368         else
 369                 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN);
 370
 371         i2c->msg = msgs;
 372         i2c->pos = 0;
 373         i2c->nmsgs = num;
 374         i2c->state = STATE_START;
 375
 376         oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
 377         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
 378
 379         if (polling) {
 380                 ocores_process_polling(i2c);
 381         } else {
 382                 ret = wait_event_timeout(i2c->wait,
 383                                          (i2c->state == STATE_ERROR) ||
 384                                          (i2c->state == STATE_DONE), HZ);
 385                 if (ret == 0) {
 386                         ocores_process_timeout(i2c);
 387                         return -ETIMEDOUT;
 388                 }
 389         }
 390
 391         return (i2c->state == STATE_DONE) ? num : -EIO;
 392 }
 393
 394 static int ocores_xfer_polling(struct i2c_adapter *adap,
 395                                struct i2c_msg *msgs, int num)
 396 {
 397         return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true);
 398 }
 399
 400 static int ocores_xfer(struct i2c_adapter *adap,
 401                        struct i2c_msg *msgs, int num)
 402 {
 403         return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false);
 404 }
 405
 406 static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
 407 {
 408         int prescale;
 409         int diff;
 410         u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
 411
 412         /* make sure the device is disabled */
 413         ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
 414         oc_setreg(i2c, OCI2C_CONTROL, ctrl);
 415
 416         prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
 417         prescale = clamp(prescale, 0, 0xffff);
 418
 419         diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
 420         if (abs(diff) > i2c->bus_clock_khz / 10) {
 421                 dev_err(dev,
 422                         "Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
 423                         i2c->ip_clock_khz, i2c->bus_clock_khz);
 424                 return -EINVAL;
 425         }
 426
 427         oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
 428         oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
 429
 430         /* Init the device */
 431         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
 432         oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
 433
 434         return 0;
 435 }
 436
 437
 438 static u32 ocores_func(struct i2c_adapter *adap)
 439 {
 440         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 441 }
 442
 443 static struct i2c_algorithm ocores_algorithm = {
 444         .master_xfer = ocores_xfer,
 445         .master_xfer_atomic = ocores_xfer_polling,
 446         .functionality = ocores_func,
 447 };
 448
 449 static const struct i2c_adapter ocores_adapter = {
 450         .owner = THIS_MODULE,
 451         .name = "i2c-ocores",
 452         .class = I2C_CLASS_DEPRECATED,
 453         .algo = &ocores_algorithm,
 454 };
 455
 456 static const struct of_device_id ocores_i2c_match[] = {
 457         {
 458                 .compatible = "opencores,i2c-ocores",
 459                 .data = (void *)TYPE_OCORES,
 460         },
 461         {
 462                 .compatible = "aeroflexgaisler,i2cmst",
 463                 .data = (void *)TYPE_GRLIB,
 464         },
 465         {},
 466 };
 467 MODULE_DEVICE_TABLE(of, ocores_i2c_match);
 468
 469 #ifdef CONFIG_OF
 470 /*
 471  * Read and write functions for the GRLIB port of the controller. Registers are
 472  * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
 473  * register. The subsequent registers have their offsets decreased accordingly.
 474  */
 475 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
 476 {
 477         u32 rd;
 478         int rreg = reg;
 479
 480         if (reg != OCI2C_PRELOW)
 481                 rreg--;
 482         rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
 483         if (reg == OCI2C_PREHIGH)
 484                 return (u8)(rd >> 8);
 485         else
 486                 return (u8)rd;
 487 }
 488
 489 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
 490 {
 491         u32 curr, wr;
 492         int rreg = reg;
 493
 494         if (reg != OCI2C_PRELOW)
 495                 rreg--;
 496         if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
 497                 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
 498                 if (reg == OCI2C_PRELOW)
 499                         wr = (curr & 0xff00) | value;
 500                 else
 501                         wr = (((u32)value) << 8) | (curr & 0xff);
 502         } else {
 503                 wr = value;
 504         }
 505         iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
 506 }
 507
 508 static int ocores_i2c_of_probe(struct platform_device *pdev,
 509                                 struct ocores_i2c *i2c)
 510 {
 511         struct device_node *np = pdev->dev.of_node;
 512         const struct of_device_id *match;
 513         u32 val;
 514         u32 clock_frequency;
 515         bool clock_frequency_present;
 516
 517         if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
 518                 /* no 'reg-shift', check for deprecated 'regstep' */
 519                 if (!of_property_read_u32(np, "regstep", &val)) {
 520                         if (!is_power_of_2(val)) {
 521                                 dev_err(&pdev->dev, "invalid regstep %d\n",
 522                                         val);
 523                                 return -EINVAL;
 524                         }
 525                         i2c->reg_shift = ilog2(val);
 526                         dev_warn(&pdev->dev,
 527                                 "regstep property deprecated, use reg-shift\n");
 528                 }
 529         }
 530
 531         clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
 532                                                         &clock_frequency);
 533         i2c->bus_clock_khz = 100;
 534
 535         i2c->clk = devm_clk_get(&pdev->dev, NULL);
 536
 537         if (!IS_ERR(i2c->clk)) {
 538                 int ret = clk_prepare_enable(i2c->clk);
 539
 540                 if (ret) {
 541                         dev_err(&pdev->dev,
 542                                 "clk_prepare_enable failed: %d\n", ret);
 543                         return ret;
 544                 }
 545                 i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
 546                 if (clock_frequency_present)
 547                         i2c->bus_clock_khz = clock_frequency / 1000;
 548         }
 549
 550         if (i2c->ip_clock_khz == 0) {
 551                 if (of_property_read_u32(np, "opencores,ip-clock-frequency",
 552                                                 &val)) {
 553                         if (!clock_frequency_present) {
 554                                 dev_err(&pdev->dev,
 555                                         "Missing required parameter 'opencores,ip-clock-frequency'\n");
 556                                 clk_disable_unprepare(i2c->clk);
 557                                 return -ENODEV;
 558                         }
 559                         i2c->ip_clock_khz = clock_frequency / 1000;
 560                         dev_warn(&pdev->dev,
 561                                  "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
 562                 } else {
 563                         i2c->ip_clock_khz = val / 1000;
 564                         if (clock_frequency_present)
 565                                 i2c->bus_clock_khz = clock_frequency / 1000;
 566                 }
 567         }
 568
 569         of_property_read_u32(pdev->dev.of_node, "reg-io-width",
 570                                 &i2c->reg_io_width);
 571
 572         match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
 573         if (match && (long)match->data == TYPE_GRLIB) {
 574                 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
 575                 i2c->setreg = oc_setreg_grlib;
 576                 i2c->getreg = oc_getreg_grlib;
 577         }
 578
 579         return 0;
 580 }
 581 #else
 582 #define ocores_i2c_of_probe(pdev, i2c) -ENODEV
 583 #endif
 584
 585 static int ocores_i2c_probe(struct platform_device *pdev)
 586 {
 587         struct ocores_i2c *i2c;
 588         struct ocores_i2c_platform_data *pdata;
 589         struct resource *res;
 590         int irq;
 591         int ret;
 592         int i;
 593
 594         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 595         if (!i2c)
 596                 return -ENOMEM;
 597
 598         spin_lock_init(&i2c->process_lock);
 599
 600         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 601         if (res) {
 602                 i2c->base = devm_ioremap_resource(&pdev->dev, res);
 603                 if (IS_ERR(i2c->base))
 604                         return PTR_ERR(i2c->base);
 605         } else {
 606                 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
 607                 if (!res)
 608                         return -EINVAL;
 609                 i2c->iobase = res->start;
 610                 if (!devm_request_region(&pdev->dev, res->start,
 611                                          resource_size(res),
 612                                          pdev->name)) {
 613                         dev_err(&pdev->dev, "Can't get I/O resource.\n");
 614                         return -EBUSY;
 615                 }
 616                 i2c->setreg = oc_setreg_io_8;
 617                 i2c->getreg = oc_getreg_io_8;
 618         }
 619
 620         pdata = dev_get_platdata(&pdev->dev);
 621         if (pdata) {
 622                 i2c->reg_shift = pdata->reg_shift;
 623                 i2c->reg_io_width = pdata->reg_io_width;
 624                 i2c->ip_clock_khz = pdata->clock_khz;
 625                 if (pdata->bus_khz)
 626                         i2c->bus_clock_khz = pdata->bus_khz;
 627                 else
 628                         i2c->bus_clock_khz = 100;
 629         } else {
 630                 ret = ocores_i2c_of_probe(pdev, i2c);
 631                 if (ret)
 632                         return ret;
 633         }
 634
 635         if (i2c->reg_io_width == 0)
 636                 i2c->reg_io_width = 1; /* Set to default value */
 637
 638         if (!i2c->setreg || !i2c->getreg) {
 639                 bool be = pdata ? pdata->big_endian :
 640                         of_device_is_big_endian(pdev->dev.of_node);
 641
 642                 switch (i2c->reg_io_width) {
 643                 case 1:
 644                         i2c->setreg = oc_setreg_8;
 645                         i2c->getreg = oc_getreg_8;
 646                         break;
 647
 648                 case 2:
 649                         i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
 650                         i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
 651                         break;
 652
 653                 case 4:
 654                         i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
 655                         i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
 656                         break;
 657
 658                 default:
 659                         dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
 660                                 i2c->reg_io_width);
 661                         ret = -EINVAL;
 662                         goto err_clk;
 663                 }
 664         }
 665
 666         init_waitqueue_head(&i2c->wait);
 667
 668         irq = platform_get_irq(pdev, 0);
 669         if (irq == -ENXIO) {
 670                 ocores_algorithm.master_xfer = ocores_xfer_polling;
 671         } else {
 672                 if (irq < 0)
 673                         return irq;
 674         }
 675
 676         if (ocores_algorithm.master_xfer != ocores_xfer_polling) {
 677                 ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
 678                                        pdev->name, i2c);
 679                 if (ret) {
 680                         dev_err(&pdev->dev, "Cannot claim IRQ\n");
 681                         goto err_clk;
 682                 }
 683         }
 684
 685         ret = ocores_init(&pdev->dev, i2c);
 686         if (ret)
 687                 goto err_clk;
 688
 689         /* hook up driver to tree */
 690         platform_set_drvdata(pdev, i2c);
 691         i2c->adap = ocores_adapter;
 692         i2c_set_adapdata(&i2c->adap, i2c);
 693         i2c->adap.dev.parent = &pdev->dev;
 694         i2c->adap.dev.of_node = pdev->dev.of_node;
 695
 696         /* add i2c adapter to i2c tree */
 697         ret = i2c_add_adapter(&i2c->adap);
 698         if (ret)
 699                 goto err_clk;
 700
 701         /* add in known devices to the bus */
 702         if (pdata) {
 703                 for (i = 0; i < pdata->num_devices; i++)
 704                         i2c_new_device(&i2c->adap, pdata->devices + i);
 705         }
 706
 707         return 0;
 708
 709 err_clk:
 710         clk_disable_unprepare(i2c->clk);
 711         return ret;
 712 }
 713
 714 static int ocores_i2c_remove(struct platform_device *pdev)
 715 {
 716         struct ocores_i2c *i2c = platform_get_drvdata(pdev);
 717         u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
 718
 719         /* disable i2c logic */
 720         ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
 721         oc_setreg(i2c, OCI2C_CONTROL, ctrl);
 722
 723         /* remove adapter & data */
 724         i2c_del_adapter(&i2c->adap);
 725
 726         if (!IS_ERR(i2c->clk))
 727                 clk_disable_unprepare(i2c->clk);
 728
 729         return 0;
 730 }
 731
 732 #ifdef CONFIG_PM_SLEEP
 733 static int ocores_i2c_suspend(struct device *dev)
 734 {
 735         struct ocores_i2c *i2c = dev_get_drvdata(dev);
 736         u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
 737
 738         /* make sure the device is disabled */
 739         ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
 740         oc_setreg(i2c, OCI2C_CONTROL, ctrl);
 741
 742         if (!IS_ERR(i2c->clk))
 743                 clk_disable_unprepare(i2c->clk);
 744         return 0;
 745 }
 746
 747 static int ocores_i2c_resume(struct device *dev)
 748 {
 749         struct ocores_i2c *i2c = dev_get_drvdata(dev);
 750
 751         if (!IS_ERR(i2c->clk)) {
 752                 unsigned long rate;
 753                 int ret = clk_prepare_enable(i2c->clk);
 754
 755                 if (ret) {
 756                         dev_err(dev,
 757                                 "clk_prepare_enable failed: %d\n", ret);
 758                         return ret;
 759                 }
 760                 rate = clk_get_rate(i2c->clk) / 1000;
 761                 if (rate)
 762                         i2c->ip_clock_khz = rate;
 763         }
 764         return ocores_init(dev, i2c);
 765 }
 766
 767 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
 768 #define OCORES_I2C_PM   (&ocores_i2c_pm)
 769 #else
 770 #define OCORES_I2C_PM   NULL
 771 #endif
 772
 773 static struct platform_driver ocores_i2c_driver = {
 774         .probe   = ocores_i2c_probe,
 775         .remove  = ocores_i2c_remove,
 776         .driver  = {
 777                 .name = "ocores-i2c",
 778                 .of_match_table = ocores_i2c_match,
 779                 .pm = OCORES_I2C_PM,
 780         },
 781 };
 782
 783 module_platform_driver(ocores_i2c_driver);
 784
 785 MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>");
 786 MODULE_DESCRIPTION("OpenCores I2C bus driver");
 787 MODULE_LICENSE("GPL");
 788 MODULE_ALIAS("platform:ocores-i2c");