drivers/gpu/drm/vc4/vc4_crtc.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 CRTC module
  11  *
  12  * In VC4, the Pixel Valve is what most closely corresponds to the
  13  * DRM's concept of a CRTC.  The PV generates video timings from the
  14  * encoder's clock plus its configuration.  It pulls scaled pixels from
  15  * the HVS at that timing, and feeds it to the encoder.
  16  *
  17  * However, the DRM CRTC also collects the configuration of all the
  18  * DRM planes attached to it.  As a result, the CRTC is also
  19  * responsible for writing the display list for the HVS channel that
  20  * the CRTC will use.
  21  *
  22  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  23  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  24  * image domain can feed either HDMI or the SDTV controller.  The
  25  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  26  * SDTV, etc.) according to which output type is chosen in the mux.
  27  *
  28  * For power management, the pixel valve's registers are all clocked
  29  * by the AXI clock, while the timings and FIFOs make use of the
  30  * output-specific clock.  Since the encoders also directly consume
  31  * the CPRMAN clocks, and know what timings they need, they are the
  32  * ones that set the clock.
  33  */
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <linux/clk.h>
  39 #include <drm/drm_fb_cma_helper.h>
  40 #include <linux/component.h>
  41 #include <linux/of_device.h>
  42 #include "vc4_drv.h"
  43 #include "vc4_regs.h"
  44
  45 struct vc4_crtc {
  46         struct drm_crtc base;
  47         const struct vc4_crtc_data *data;
  48         void __iomem *regs;
  49
  50         /* Timestamp at start of vblank irq - unaffected by lock delays. */
  51         ktime_t t_vblank;
  52
  53         /* Which HVS channel we're using for our CRTC. */
  54         int channel;
  55
  56         u8 lut_r[256];
  57         u8 lut_g[256];
  58         u8 lut_b[256];
  59         /* Size in pixels of the COB memory allocated to this CRTC. */
  60         u32 cob_size;
  61
  62         struct drm_pending_vblank_event *event;
  63 };
  64
  65 struct vc4_crtc_state {
  66         struct drm_crtc_state base;
  67         /* Dlist area for this CRTC configuration. */
  68         struct drm_mm_node mm;
  69 };
  70
  71 static inline struct vc4_crtc *
  72 to_vc4_crtc(struct drm_crtc *crtc)
  73 {
  74         return (struct vc4_crtc *)crtc;
  75 }
  76
  77 static inline struct vc4_crtc_state *
  78 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  79 {
  80         return (struct vc4_crtc_state *)crtc_state;
  81 }
  82
  83 struct vc4_crtc_data {
  84         /* Which channel of the HVS this pixelvalve sources from. */
  85         int hvs_channel;
  86
  87         enum vc4_encoder_type encoder_types[4];
  88 };
  89
  90 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  91 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  92
  93 #define CRTC_REG(reg) { reg, #reg }
  94 static const struct {
  95         u32 reg;
  96         const char *name;
  97 } crtc_regs[] = {
  98         CRTC_REG(PV_CONTROL),
  99         CRTC_REG(PV_V_CONTROL),
 100         CRTC_REG(PV_VSYNCD_EVEN),
 101         CRTC_REG(PV_HORZA),
 102         CRTC_REG(PV_HORZB),
 103         CRTC_REG(PV_VERTA),
 104         CRTC_REG(PV_VERTB),
 105         CRTC_REG(PV_VERTA_EVEN),
 106         CRTC_REG(PV_VERTB_EVEN),
 107         CRTC_REG(PV_INTEN),
 108         CRTC_REG(PV_INTSTAT),
 109         CRTC_REG(PV_STAT),
 110         CRTC_REG(PV_HACT_ACT),
 111 };
 112
 113 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
 114 {
 115         int i;
 116
 117         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 118                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 119                          crtc_regs[i].reg, crtc_regs[i].name,
 120                          CRTC_READ(crtc_regs[i].reg));
 121         }
 122 }
 123
 124 #ifdef CONFIG_DEBUG_FS
 125 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
 126 {
 127         struct drm_info_node *node = (struct drm_info_node *)m->private;
 128         struct drm_device *dev = node->minor->dev;
 129         int crtc_index = (uintptr_t)node->info_ent->data;
 130         struct drm_crtc *crtc;
 131         struct vc4_crtc *vc4_crtc;
 132         int i;
 133
 134         i = 0;
 135         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 136                 if (i == crtc_index)
 137                         break;
 138                 i++;
 139         }
 140         if (!crtc)
 141                 return 0;
 142         vc4_crtc = to_vc4_crtc(crtc);
 143
 144         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 145                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 146                            crtc_regs[i].name, crtc_regs[i].reg,
 147                            CRTC_READ(crtc_regs[i].reg));
 148         }
 149
 150         return 0;
 151 }
 152 #endif
 153
 154 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
 155                              bool in_vblank_irq, int *vpos, int *hpos,
 156                              ktime_t *stime, ktime_t *etime,
 157                              const struct drm_display_mode *mode)
 158 {
 159         struct vc4_dev *vc4 = to_vc4_dev(dev);
 160         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
 161         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 162         u32 val;
 163         int fifo_lines;
 164         int vblank_lines;
 165         bool ret = false;
 166
 167         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 168
 169         /* Get optional system timestamp before query. */
 170         if (stime)
 171                 *stime = ktime_get();
 172
 173         /*
 174          * Read vertical scanline which is currently composed for our
 175          * pixelvalve by the HVS, and also the scaler status.
 176          */
 177         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
 178
 179         /* Get optional system timestamp after query. */
 180         if (etime)
 181                 *etime = ktime_get();
 182
 183         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 184
 185         /* Vertical position of hvs composed scanline. */
 186         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 187         *hpos = 0;
 188
 189         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 190                 *vpos /= 2;
 191
 192                 /* Use hpos to correct for field offset in interlaced mode. */
 193                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 194                         *hpos += mode->crtc_htotal / 2;
 195         }
 196
 197         /* This is the offset we need for translating hvs -> pv scanout pos. */
 198         fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
 199
 200         if (fifo_lines > 0)
 201                 ret = true;
 202
 203         /* HVS more than fifo_lines into frame for compositing? */
 204         if (*vpos > fifo_lines) {
 205                 /*
 206                  * We are in active scanout and can get some meaningful results
 207                  * from HVS. The actual PV scanout can not trail behind more
 208                  * than fifo_lines as that is the fifo's capacity. Assume that
 209                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 210                  * refilling the fifo and PV consuming from the fifo, ie.
 211                  * whenever the PV consumes and frees up a scanline in the
 212                  * fifo, the HVS will immediately refill it, therefore
 213                  * incrementing vpos. Therefore we choose HVS read position -
 214                  * fifo size in scanlines as a estimate of the real scanout
 215                  * position of the PV.
 216                  */
 217                 *vpos -= fifo_lines + 1;
 218
 219                 return ret;
 220         }
 221
 222         /*
 223          * Less: This happens when we are in vblank and the HVS, after getting
 224          * the VSTART restart signal from the PV, just started refilling its
 225          * fifo with new lines from the top-most lines of the new framebuffers.
 226          * The PV does not scan out in vblank, so does not remove lines from
 227          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 228          * We can't get meaningful readings wrt. scanline position of the PV
 229          * and need to make things up in a approximative but consistent way.
 230          */
 231         vblank_lines = mode->vtotal - mode->vdisplay;
 232
 233         if (in_vblank_irq) {
 234                 /*
 235                  * Assume the irq handler got called close to first
 236                  * line of vblank, so PV has about a full vblank
 237                  * scanlines to go, and as a base timestamp use the
 238                  * one taken at entry into vblank irq handler, so it
 239                  * is not affected by random delays due to lock
 240                  * contention on event_lock or vblank_time lock in
 241                  * the core.
 242                  */
 243                 *vpos = -vblank_lines;
 244
 245                 if (stime)
 246                         *stime = vc4_crtc->t_vblank;
 247                 if (etime)
 248                         *etime = vc4_crtc->t_vblank;
 249
 250                 /*
 251                  * If the HVS fifo is not yet full then we know for certain
 252                  * we are at the very beginning of vblank, as the hvs just
 253                  * started refilling, and the stime and etime timestamps
 254                  * truly correspond to start of vblank.
 255                  *
 256                  * Unfortunately there's no way to report this to upper levels
 257                  * and make it more useful.
 258                  */
 259         } else {
 260                 /*
 261                  * No clue where we are inside vblank. Return a vpos of zero,
 262                  * which will cause calling code to just return the etime
 263                  * timestamp uncorrected. At least this is no worse than the
 264                  * standard fallback.
 265                  */
 266                 *vpos = 0;
 267         }
 268
 269         return ret;
 270 }
 271
 272 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 273 {
 274         drm_crtc_cleanup(crtc);
 275 }
 276
 277 static void
 278 vc4_crtc_lut_load(struct drm_crtc *crtc)
 279 {
 280         struct drm_device *dev = crtc->dev;
 281         struct vc4_dev *vc4 = to_vc4_dev(dev);
 282         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 283         u32 i;
 284
 285         /* The LUT memory is laid out with each HVS channel in order,
 286          * each of which takes 256 writes for R, 256 for G, then 256
 287          * for B.
 288          */
 289         HVS_WRITE(SCALER_GAMADDR,
 290                   SCALER_GAMADDR_AUTOINC |
 291                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 292
 293         for (i = 0; i < crtc->gamma_size; i++)
 294                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 295         for (i = 0; i < crtc->gamma_size; i++)
 296                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 297         for (i = 0; i < crtc->gamma_size; i++)
 298                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 299 }
 300
 301 static int
 302 vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 303                    uint32_t size,
 304                    struct drm_modeset_acquire_ctx *ctx)
 305 {
 306         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 307         u32 i;
 308
 309         for (i = 0; i < size; i++) {
 310                 vc4_crtc->lut_r[i] = r[i] >> 8;
 311                 vc4_crtc->lut_g[i] = g[i] >> 8;
 312                 vc4_crtc->lut_b[i] = b[i] >> 8;
 313         }
 314
 315         vc4_crtc_lut_load(crtc);
 316
 317         return 0;
 318 }
 319
 320 static u32 vc4_get_fifo_full_level(u32 format)
 321 {
 322         static const u32 fifo_len_bytes = 64;
 323         static const u32 hvs_latency_pix = 6;
 324
 325         switch (format) {
 326         case PV_CONTROL_FORMAT_DSIV_16:
 327         case PV_CONTROL_FORMAT_DSIC_16:
 328                 return fifo_len_bytes - 2 * hvs_latency_pix;
 329         case PV_CONTROL_FORMAT_DSIV_18:
 330                 return fifo_len_bytes - 14;
 331         case PV_CONTROL_FORMAT_24:
 332         case PV_CONTROL_FORMAT_DSIV_24:
 333         default:
 334                 return fifo_len_bytes - 3 * hvs_latency_pix;
 335         }
 336 }
 337
 338 /*
 339  * Returns the encoder attached to the CRTC.
 340  *
 341  * VC4 can only scan out to one encoder at a time, while the DRM core
 342  * allows drivers to push pixels to more than one encoder from the
 343  * same CRTC.
 344  */
 345 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
 346 {
 347         struct drm_connector *connector;
 348         struct drm_connector_list_iter conn_iter;
 349
 350         drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 351         drm_for_each_connector_iter(connector, &conn_iter) {
 352                 if (connector->state->crtc == crtc) {
 353                         drm_connector_list_iter_end(&conn_iter);
 354                         return connector->encoder;
 355                 }
 356         }
 357         drm_connector_list_iter_end(&conn_iter);
 358
 359         return NULL;
 360 }
 361
 362 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 363 {
 364         struct drm_device *dev = crtc->dev;
 365         struct vc4_dev *vc4 = to_vc4_dev(dev);
 366         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
 367         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 368         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 369         struct drm_crtc_state *state = crtc->state;
 370         struct drm_display_mode *mode = &state->adjusted_mode;
 371         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 372         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 373         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 374                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 375         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 376         bool debug_dump_regs = false;
 377
 378         if (debug_dump_regs) {
 379                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
 380                 vc4_crtc_dump_regs(vc4_crtc);
 381         }
 382
 383         /* Reset the PV fifo. */
 384         CRTC_WRITE(PV_CONTROL, 0);
 385         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 386         CRTC_WRITE(PV_CONTROL, 0);
 387
 388         CRTC_WRITE(PV_HORZA,
 389                    VC4_SET_FIELD((mode->htotal -
 390                                   mode->hsync_end) * pixel_rep,
 391                                  PV_HORZA_HBP) |
 392                    VC4_SET_FIELD((mode->hsync_end -
 393                                   mode->hsync_start) * pixel_rep,
 394                                  PV_HORZA_HSYNC));
 395         CRTC_WRITE(PV_HORZB,
 396                    VC4_SET_FIELD((mode->hsync_start -
 397                                   mode->hdisplay) * pixel_rep,
 398                                  PV_HORZB_HFP) |
 399                    VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
 400
 401         CRTC_WRITE(PV_VERTA,
 402                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 403                                  PV_VERTA_VBP) |
 404                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 405                                  PV_VERTA_VSYNC));
 406         CRTC_WRITE(PV_VERTB,
 407                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 408                                  PV_VERTB_VFP) |
 409                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 410
 411         if (interlace) {
 412                 CRTC_WRITE(PV_VERTA_EVEN,
 413                            VC4_SET_FIELD(mode->crtc_vtotal -
 414                                          mode->crtc_vsync_end - 1,
 415                                          PV_VERTA_VBP) |
 416                            VC4_SET_FIELD(mode->crtc_vsync_end -
 417                                          mode->crtc_vsync_start,
 418                                          PV_VERTA_VSYNC));
 419                 CRTC_WRITE(PV_VERTB_EVEN,
 420                            VC4_SET_FIELD(mode->crtc_vsync_start -
 421                                          mode->crtc_vdisplay,
 422                                          PV_VERTB_VFP) |
 423                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 424
 425                 /* We set up first field even mode for HDMI.  VEC's
 426                  * NTSC mode would want first field odd instead, once
 427                  * we support it (to do so, set ODD_FIRST and put the
 428                  * delay in VSYNCD_EVEN instead).
 429                  */
 430                 CRTC_WRITE(PV_V_CONTROL,
 431                            PV_VCONTROL_CONTINUOUS |
 432                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 433                            PV_VCONTROL_INTERLACE |
 434                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 435                                          PV_VCONTROL_ODD_DELAY));
 436                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 437         } else {
 438                 CRTC_WRITE(PV_V_CONTROL,
 439                            PV_VCONTROL_CONTINUOUS |
 440                            (is_dsi ? PV_VCONTROL_DSI : 0));
 441         }
 442
 443         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 444
 445         CRTC_WRITE(PV_CONTROL,
 446                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 447                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 448                                  PV_CONTROL_FIFO_LEVEL) |
 449                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 450                    PV_CONTROL_CLR_AT_START |
 451                    PV_CONTROL_TRIGGER_UNDERFLOW |
 452                    PV_CONTROL_WAIT_HSTART |
 453                    VC4_SET_FIELD(vc4_encoder->clock_select,
 454                                  PV_CONTROL_CLK_SELECT) |
 455                    PV_CONTROL_FIFO_CLR |
 456                    PV_CONTROL_EN);
 457
 458         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 459                   SCALER_DISPBKGND_AUTOHS |
 460                   SCALER_DISPBKGND_GAMMA |
 461                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 462
 463         /* Reload the LUT, since the SRAMs would have been disabled if
 464          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 465          */
 466         vc4_crtc_lut_load(crtc);
 467
 468         if (debug_dump_regs) {
 469                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
 470                 vc4_crtc_dump_regs(vc4_crtc);
 471         }
 472 }
 473
 474 static void require_hvs_enabled(struct drm_device *dev)
 475 {
 476         struct vc4_dev *vc4 = to_vc4_dev(dev);
 477
 478         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 479                      SCALER_DISPCTRL_ENABLE);
 480 }
 481
 482 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
 483                                     struct drm_crtc_state *old_state)
 484 {
 485         struct drm_device *dev = crtc->dev;
 486         struct vc4_dev *vc4 = to_vc4_dev(dev);
 487         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 488         u32 chan = vc4_crtc->channel;
 489         int ret;
 490         require_hvs_enabled(dev);
 491
 492         /* Disable vblank irq handling before crtc is disabled. */
 493         drm_crtc_vblank_off(crtc);
 494
 495         CRTC_WRITE(PV_V_CONTROL,
 496                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 497         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 498         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 499
 500         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 501             SCALER_DISPCTRLX_ENABLE) {
 502                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 503                           SCALER_DISPCTRLX_RESET);
 504
 505                 /* While the docs say that reset is self-clearing, it
 506                  * seems it doesn't actually.
 507                  */
 508                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 509         }
 510
 511         /* Once we leave, the scaler should be disabled and its fifo empty. */
 512
 513         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 514
 515         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 516                                    SCALER_DISPSTATX_MODE) !=
 517                      SCALER_DISPSTATX_MODE_DISABLED);
 518
 519         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 520                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 521                      SCALER_DISPSTATX_EMPTY);
 522
 523         /*
 524          * Make sure we issue a vblank event after disabling the CRTC if
 525          * someone was waiting it.
 526          */
 527         if (crtc->state->event) {
 528                 unsigned long flags;
 529
 530                 spin_lock_irqsave(&dev->event_lock, flags);
 531                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 532                 crtc->state->event = NULL;
 533                 spin_unlock_irqrestore(&dev->event_lock, flags);
 534         }
 535 }
 536
 537 static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
 538 {
 539         struct drm_device *dev = crtc->dev;
 540         struct vc4_dev *vc4 = to_vc4_dev(dev);
 541         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 542         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 543
 544         if (crtc->state->event) {
 545                 unsigned long flags;
 546
 547                 crtc->state->event->pipe = drm_crtc_index(crtc);
 548
 549                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 550
 551                 spin_lock_irqsave(&dev->event_lock, flags);
 552                 vc4_crtc->event = crtc->state->event;
 553                 crtc->state->event = NULL;
 554
 555                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 556                           vc4_state->mm.start);
 557
 558                 spin_unlock_irqrestore(&dev->event_lock, flags);
 559         } else {
 560                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 561                           vc4_state->mm.start);
 562         }
 563 }
 564
 565 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 566                                    struct drm_crtc_state *old_state)
 567 {
 568         struct drm_device *dev = crtc->dev;
 569         struct vc4_dev *vc4 = to_vc4_dev(dev);
 570         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 571         struct drm_crtc_state *state = crtc->state;
 572         struct drm_display_mode *mode = &state->adjusted_mode;
 573
 574         require_hvs_enabled(dev);
 575
 576         /* Enable vblank irq handling before crtc is started otherwise
 577          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 578          */
 579         drm_crtc_vblank_on(crtc);
 580         vc4_crtc_update_dlist(crtc);
 581
 582         /* Turn on the scaler, which will wait for vstart to start
 583          * compositing.
 584          */
 585         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 586                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 587                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 588                   SCALER_DISPCTRLX_ENABLE);
 589
 590         /* Turn on the pixel valve, which will emit the vstart signal. */
 591         CRTC_WRITE(PV_V_CONTROL,
 592                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 593 }
 594
 595 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
 596                                                 const struct drm_display_mode *mode)
 597 {
 598         /* Do not allow doublescan modes from user space */
 599         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 600                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 601                               crtc->base.id);
 602                 return MODE_NO_DBLESCAN;
 603         }
 604
 605         return MODE_OK;
 606 }
 607
 608 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 609                                  struct drm_crtc_state *state)
 610 {
 611         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 612         struct drm_device *dev = crtc->dev;
 613         struct vc4_dev *vc4 = to_vc4_dev(dev);
 614         struct drm_plane *plane;
 615         unsigned long flags;
 616         const struct drm_plane_state *plane_state;
 617         u32 dlist_count = 0;
 618         int ret;
 619
 620         /* The pixelvalve can only feed one encoder (and encoders are
 621          * 1:1 with connectors.)
 622          */
 623         if (hweight32(state->connector_mask) > 1)
 624                 return -EINVAL;
 625
 626         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 627                 dlist_count += vc4_plane_dlist_size(plane_state);
 628
 629         dlist_count++; /* Account for SCALER_CTL0_END. */
 630
 631         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 632         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 633                                  dlist_count);
 634         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 635         if (ret)
 636                 return ret;
 637
 638         return 0;
 639 }
 640
 641 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 642                                   struct drm_crtc_state *old_state)
 643 {
 644         struct drm_device *dev = crtc->dev;
 645         struct vc4_dev *vc4 = to_vc4_dev(dev);
 646         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 647         struct drm_plane *plane;
 648         bool debug_dump_regs = false;
 649         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 650         u32 __iomem *dlist_next = dlist_start;
 651
 652         if (debug_dump_regs) {
 653                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 654                 vc4_hvs_dump_state(dev);
 655         }
 656
 657         /* Copy all the active planes' dlist contents to the hardware dlist. */
 658         drm_atomic_crtc_for_each_plane(plane, crtc) {
 659                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 660         }
 661
 662         writel(SCALER_CTL0_END, dlist_next);
 663         dlist_next++;
 664
 665         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 666
 667         /* Only update DISPLIST if the CRTC was already running and is not
 668          * being disabled.
 669          * vc4_crtc_enable() takes care of updating the dlist just after
 670          * re-enabling VBLANK interrupts and before enabling the engine.
 671          * If the CRTC is being disabled, there's no point in updating this
 672          * information.
 673          */
 674         if (crtc->state->active && old_state->active)
 675                 vc4_crtc_update_dlist(crtc);
 676
 677         if (debug_dump_regs) {
 678                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 679                 vc4_hvs_dump_state(dev);
 680         }
 681 }
 682
 683 static int vc4_enable_vblank(struct drm_crtc *crtc)
 684 {
 685         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 686
 687         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 688
 689         return 0;
 690 }
 691
 692 static void vc4_disable_vblank(struct drm_crtc *crtc)
 693 {
 694         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 695
 696         CRTC_WRITE(PV_INTEN, 0);
 697 }
 698
 699 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 700 {
 701         struct drm_crtc *crtc = &vc4_crtc->base;
 702         struct drm_device *dev = crtc->dev;
 703         struct vc4_dev *vc4 = to_vc4_dev(dev);
 704         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 705         u32 chan = vc4_crtc->channel;
 706         unsigned long flags;
 707
 708         spin_lock_irqsave(&dev->event_lock, flags);
 709         if (vc4_crtc->event &&
 710             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
 711                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 712                 vc4_crtc->event = NULL;
 713                 drm_crtc_vblank_put(crtc);
 714         }
 715         spin_unlock_irqrestore(&dev->event_lock, flags);
 716 }
 717
 718 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 719 {
 720         struct vc4_crtc *vc4_crtc = data;
 721         u32 stat = CRTC_READ(PV_INTSTAT);
 722         irqreturn_t ret = IRQ_NONE;
 723
 724         if (stat & PV_INT_VFP_START) {
 725                 vc4_crtc->t_vblank = ktime_get();
 726                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 727                 drm_crtc_handle_vblank(&vc4_crtc->base);
 728                 vc4_crtc_handle_page_flip(vc4_crtc);
 729                 ret = IRQ_HANDLED;
 730         }
 731
 732         return ret;
 733 }
 734
 735 struct vc4_async_flip_state {
 736         struct drm_crtc *crtc;
 737         struct drm_framebuffer *fb;
 738         struct drm_pending_vblank_event *event;
 739
 740         struct vc4_seqno_cb cb;
 741 };
 742
 743 /* Called when the V3D execution for the BO being flipped to is done, so that
 744  * we can actually update the plane's address to point to it.
 745  */
 746 static void
 747 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 748 {
 749         struct vc4_async_flip_state *flip_state =
 750                 container_of(cb, struct vc4_async_flip_state, cb);
 751         struct drm_crtc *crtc = flip_state->crtc;
 752         struct drm_device *dev = crtc->dev;
 753         struct vc4_dev *vc4 = to_vc4_dev(dev);
 754         struct drm_plane *plane = crtc->primary;
 755
 756         vc4_plane_async_set_fb(plane, flip_state->fb);
 757         if (flip_state->event) {
 758                 unsigned long flags;
 759
 760                 spin_lock_irqsave(&dev->event_lock, flags);
 761                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 762                 spin_unlock_irqrestore(&dev->event_lock, flags);
 763         }
 764
 765         drm_crtc_vblank_put(crtc);
 766         drm_framebuffer_put(flip_state->fb);
 767         kfree(flip_state);
 768
 769         up(&vc4->async_modeset);
 770 }
 771
 772 /* Implements async (non-vblank-synced) page flips.
 773  *
 774  * The page flip ioctl needs to return immediately, so we grab the
 775  * modeset semaphore on the pipe, and queue the address update for
 776  * when V3D is done with the BO being flipped to.
 777  */
 778 static int vc4_async_page_flip(struct drm_crtc *crtc,
 779                                struct drm_framebuffer *fb,
 780                                struct drm_pending_vblank_event *event,
 781                                uint32_t flags)
 782 {
 783         struct drm_device *dev = crtc->dev;
 784         struct vc4_dev *vc4 = to_vc4_dev(dev);
 785         struct drm_plane *plane = crtc->primary;
 786         int ret = 0;
 787         struct vc4_async_flip_state *flip_state;
 788         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 789         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 790
 791         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 792         if (!flip_state)
 793                 return -ENOMEM;
 794
 795         drm_framebuffer_get(fb);
 796         flip_state->fb = fb;
 797         flip_state->crtc = crtc;
 798         flip_state->event = event;
 799
 800         /* Make sure all other async modesetes have landed. */
 801         ret = down_interruptible(&vc4->async_modeset);
 802         if (ret) {
 803                 drm_framebuffer_put(fb);
 804                 kfree(flip_state);
 805                 return ret;
 806         }
 807
 808         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 809
 810         /* Immediately update the plane's legacy fb pointer, so that later
 811          * modeset prep sees the state that will be present when the semaphore
 812          * is released.
 813          */
 814         drm_atomic_set_fb_for_plane(plane->state, fb);
 815         plane->fb = fb;
 816
 817         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 818                            vc4_async_page_flip_complete);
 819
 820         /* Driver takes ownership of state on successful async commit. */
 821         return 0;
 822 }
 823
 824 static int vc4_page_flip(struct drm_crtc *crtc,
 825                          struct drm_framebuffer *fb,
 826                          struct drm_pending_vblank_event *event,
 827                          uint32_t flags,
 828                          struct drm_modeset_acquire_ctx *ctx)
 829 {
 830         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 831                 return vc4_async_page_flip(crtc, fb, event, flags);
 832         else
 833                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
 834 }
 835
 836 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 837 {
 838         struct vc4_crtc_state *vc4_state;
 839
 840         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 841         if (!vc4_state)
 842                 return NULL;
 843
 844         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 845         return &vc4_state->base;
 846 }
 847
 848 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 849                                    struct drm_crtc_state *state)
 850 {
 851         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 852         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 853
 854         if (vc4_state->mm.allocated) {
 855                 unsigned long flags;
 856
 857                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 858                 drm_mm_remove_node(&vc4_state->mm);
 859                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 860
 861         }
 862
 863         drm_atomic_helper_crtc_destroy_state(crtc, state);
 864 }
 865
 866 static void
 867 vc4_crtc_reset(struct drm_crtc *crtc)
 868 {
 869         if (crtc->state)
 870                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 871
 872         crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
 873         if (crtc->state)
 874                 crtc->state->crtc = crtc;
 875 }
 876
 877 static const struct drm_crtc_funcs vc4_crtc_funcs = {
 878         .set_config = drm_atomic_helper_set_config,
 879         .destroy = vc4_crtc_destroy,
 880         .page_flip = vc4_page_flip,
 881         .set_property = NULL,
 882         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
 883         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
 884         .reset = vc4_crtc_reset,
 885         .atomic_duplicate_state = vc4_crtc_duplicate_state,
 886         .atomic_destroy_state = vc4_crtc_destroy_state,
 887         .gamma_set = vc4_crtc_gamma_set,
 888         .enable_vblank = vc4_enable_vblank,
 889         .disable_vblank = vc4_disable_vblank,
 890 };
 891
 892 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
 893         .mode_set_nofb = vc4_crtc_mode_set_nofb,
 894         .mode_valid = vc4_crtc_mode_valid,
 895         .atomic_check = vc4_crtc_atomic_check,
 896         .atomic_flush = vc4_crtc_atomic_flush,
 897         .atomic_enable = vc4_crtc_atomic_enable,
 898         .atomic_disable = vc4_crtc_atomic_disable,
 899 };
 900
 901 static const struct vc4_crtc_data pv0_data = {
 902         .hvs_channel = 0,
 903         .encoder_types = {
 904                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
 905                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
 906         },
 907 };
 908
 909 static const struct vc4_crtc_data pv1_data = {
 910         .hvs_channel = 2,
 911         .encoder_types = {
 912                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
 913                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
 914         },
 915 };
 916
 917 static const struct vc4_crtc_data pv2_data = {
 918         .hvs_channel = 1,
 919         .encoder_types = {
 920                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
 921                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
 922         },
 923 };
 924
 925 static const struct of_device_id vc4_crtc_dt_match[] = {
 926         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
 927         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
 928         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
 929         {}
 930 };
 931
 932 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
 933                                         struct drm_crtc *crtc)
 934 {
 935         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 936         const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
 937         const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
 938         struct drm_encoder *encoder;
 939
 940         drm_for_each_encoder(encoder, drm) {
 941                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 942                 int i;
 943
 944                 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
 945                         if (vc4_encoder->type == encoder_types[i]) {
 946                                 vc4_encoder->clock_select = i;
 947                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
 948                                 break;
 949                         }
 950                 }
 951         }
 952 }
 953
 954 static void
 955 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
 956 {
 957         struct drm_device *drm = vc4_crtc->base.dev;
 958         struct vc4_dev *vc4 = to_vc4_dev(drm);
 959         u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
 960         /* Top/base are supposed to be 4-pixel aligned, but the
 961          * Raspberry Pi firmware fills the low bits (which are
 962          * presumably ignored).
 963          */
 964         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
 965         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
 966
 967         vc4_crtc->cob_size = top - base + 4;
 968 }
 969
 970 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
 971 {
 972         struct platform_device *pdev = to_platform_device(dev);
 973         struct drm_device *drm = dev_get_drvdata(master);
 974         struct vc4_crtc *vc4_crtc;
 975         struct drm_crtc *crtc;
 976         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
 977         const struct of_device_id *match;
 978         int ret, i;
 979
 980         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
 981         if (!vc4_crtc)
 982                 return -ENOMEM;
 983         crtc = &vc4_crtc->base;
 984
 985         match = of_match_device(vc4_crtc_dt_match, dev);
 986         if (!match)
 987                 return -ENODEV;
 988         vc4_crtc->data = match->data;
 989
 990         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
 991         if (IS_ERR(vc4_crtc->regs))
 992                 return PTR_ERR(vc4_crtc->regs);
 993
 994         /* For now, we create just the primary and the legacy cursor
 995          * planes.  We should be able to stack more planes on easily,
 996          * but to do that we would need to compute the bandwidth
 997          * requirement of the plane configuration, and reject ones
 998          * that will take too much.
 999          */
1000         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1001         if (IS_ERR(primary_plane)) {
1002                 dev_err(dev, "failed to construct primary plane\n");
1003                 ret = PTR_ERR(primary_plane);
1004                 goto err;
1005         }
1006
1007         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1008                                   &vc4_crtc_funcs, NULL);
1009         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1010         primary_plane->crtc = crtc;
1011         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1012         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1013
1014         /* Set up some arbitrary number of planes.  We're not limited
1015          * by a set number of physical registers, just the space in
1016          * the HVS (16k) and how small an plane can be (28 bytes).
1017          * However, each plane we set up takes up some memory, and
1018          * increases the cost of looping over planes, which atomic
1019          * modesetting does quite a bit.  As a result, we pick a
1020          * modest number of planes to expose, that should hopefully
1021          * still cover any sane usecase.
1022          */
1023         for (i = 0; i < 8; i++) {
1024                 struct drm_plane *plane =
1025                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1026
1027                 if (IS_ERR(plane))
1028                         continue;
1029
1030                 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1031         }
1032
1033         /* Set up the legacy cursor after overlay initialization,
1034          * since we overlay planes on the CRTC in the order they were
1035          * initialized.
1036          */
1037         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1038         if (!IS_ERR(cursor_plane)) {
1039                 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1040                 cursor_plane->crtc = crtc;
1041                 crtc->cursor = cursor_plane;
1042         }
1043
1044         vc4_crtc_get_cob_allocation(vc4_crtc);
1045
1046         CRTC_WRITE(PV_INTEN, 0);
1047         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1048         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1049                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1050         if (ret)
1051                 goto err_destroy_planes;
1052
1053         vc4_set_crtc_possible_masks(drm, crtc);
1054
1055         for (i = 0; i < crtc->gamma_size; i++) {
1056                 vc4_crtc->lut_r[i] = i;
1057                 vc4_crtc->lut_g[i] = i;
1058                 vc4_crtc->lut_b[i] = i;
1059         }
1060
1061         platform_set_drvdata(pdev, vc4_crtc);
1062
1063         return 0;
1064
1065 err_destroy_planes:
1066         list_for_each_entry_safe(destroy_plane, temp,
1067                                  &drm->mode_config.plane_list, head) {
1068                 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1069                     destroy_plane->funcs->destroy(destroy_plane);
1070         }
1071 err:
1072         return ret;
1073 }
1074
1075 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1076                             void *data)
1077 {
1078         struct platform_device *pdev = to_platform_device(dev);
1079         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1080
1081         vc4_crtc_destroy(&vc4_crtc->base);
1082
1083         CRTC_WRITE(PV_INTEN, 0);
1084
1085         platform_set_drvdata(pdev, NULL);
1086 }
1087
1088 static const struct component_ops vc4_crtc_ops = {
1089         .bind   = vc4_crtc_bind,
1090         .unbind = vc4_crtc_unbind,
1091 };
1092
1093 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1094 {
1095         return component_add(&pdev->dev, &vc4_crtc_ops);
1096 }
1097
1098 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1099 {
1100         component_del(&pdev->dev, &vc4_crtc_ops);
1101         return 0;
1102 }
1103
1104 struct platform_driver vc4_crtc_driver = {
1105         .probe = vc4_crtc_dev_probe,
1106         .remove = vc4_crtc_dev_remove,
1107         .driver = {
1108                 .name = "vc4_crtc",
1109                 .of_match_table = vc4_crtc_dt_match,
1110         },
1111 };