1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2015-2018 Broadcom */
4 #include <linux/reservation.h>
6 #include <drm/drm_encoder.h>
7 #include <drm/drm_gem.h>
8 #include <drm/gpu_scheduler.h>
10 #define GMP_GRANULARITY (128 * 1024)
12 /* Enum for each of the V3D queues. We maintain various queue
13 * tracking as an array because at some point we'll want to support
14 * the TFU (texture formatting unit) as another queue.
21 #define V3D_MAX_QUEUES (V3D_RENDER + 1)
23 struct v3d_queue_state {
24 struct drm_gpu_scheduler sched;
32 struct drm_device drm;
34 /* Short representation (e.g. 33, 41) of the V3D tech version
40 struct platform_device *pdev;
41 void __iomem *hub_regs;
42 void __iomem *core_regs[3];
43 void __iomem *bridge_regs;
44 void __iomem *gca_regs;
47 /* Virtual and DMA addresses of the single shared page table. */
51 /* Virtual and DMA addresses of the MMU's scratch page. When
52 * a read or write is invalid in the MMU, it will be
56 dma_addr_t mmu_scratch_paddr;
58 /* Number of V3D cores. */
61 /* Allocator managing the address space. All units are in
67 struct work_struct overflow_mem_work;
69 struct v3d_exec_info *bin_job;
70 struct v3d_exec_info *render_job;
72 struct v3d_queue_state queue[V3D_MAX_QUEUES];
74 /* Spinlock used to synchronize the overflow memory
75 * management against bin job submission.
79 /* Protects bo_stats */
82 /* Lock taken when resetting the GPU, to keep multiple
83 * processes from trying to park the scheduler threads and
86 struct mutex reset_lock;
94 static inline struct v3d_dev *
95 to_v3d_dev(struct drm_device *dev)
97 return (struct v3d_dev *)dev->dev_private;
100 /* The per-fd struct, which tracks the MMU mappings. */
101 struct v3d_file_priv {
104 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES];
107 /* Tracks a mapping of a BO into a per-fd address space */
109 struct v3d_page_table *pt;
110 struct list_head list; /* entry in v3d_bo.vmas */
114 struct drm_gem_object base;
118 struct drm_mm_node node;
122 struct sg_table *sgt;
125 struct list_head vmas; /* list of v3d_vma */
127 /* List entry for the BO's position in
128 * v3d_exec_info->unref_list
130 struct list_head unref_head;
132 /* normally (resv == &_resv) except for imported bo's */
133 struct reservation_object *resv;
134 struct reservation_object _resv;
137 static inline struct v3d_bo *
138 to_v3d_bo(struct drm_gem_object *bo)
140 return (struct v3d_bo *)bo;
144 struct dma_fence base;
145 struct drm_device *dev;
146 /* v3d seqno for signaled() test */
148 enum v3d_queue queue;
151 static inline struct v3d_fence *
152 to_v3d_fence(struct dma_fence *fence)
154 return (struct v3d_fence *)fence;
157 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
158 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
160 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
161 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
163 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
164 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
166 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
167 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
170 struct drm_sched_job base;
172 struct v3d_exec_info *exec;
174 /* An optional fence userspace can pass in for the job to depend on. */
175 struct dma_fence *in_fence;
177 /* v3d fence to be signaled by IRQ handler when the job is complete. */
178 struct dma_fence *done_fence;
180 /* GPU virtual addresses of the start/end of the CL job. */
184 struct v3d_exec_info {
187 struct v3d_job bin, render;
189 /* Fence for when the scheduler considers the binner to be
190 * done, for render to depend on.
192 struct dma_fence *bin_done_fence;
194 struct kref refcount;
196 /* This is the array of BOs that were looked up at the start of exec. */
200 /* List of overflow BOs used in the job that need to be
201 * released once the job is complete.
203 struct list_head unref_list;
205 /* Submitted tile memory allocation start/size, tile state. */
210 * _wait_for - magic (register) wait macro
212 * Does the right thing for modeset paths when run under kdgb or similar atomic
213 * contexts. Note that it's important that we check the condition again after
214 * having timed out, since the timeout could be due to preemption or similar and
215 * we've never had a chance to check the condition before the timeout.
217 #define wait_for(COND, MS) ({ \
218 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
221 if (time_after(jiffies, timeout__)) { \
223 ret__ = -ETIMEDOUT; \
231 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
233 /* nsecs_to_jiffies64() does not guard against overflow */
234 if (NSEC_PER_SEC % HZ &&
235 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
236 return MAX_JIFFY_OFFSET;
238 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
242 void v3d_free_object(struct drm_gem_object *gem_obj);
243 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv,
245 int v3d_create_bo_ioctl(struct drm_device *dev, void *data,
246 struct drm_file *file_priv);
247 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data,
248 struct drm_file *file_priv);
249 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data,
250 struct drm_file *file_priv);
251 int v3d_gem_fault(struct vm_fault *vmf);
252 int v3d_mmap(struct file *filp, struct vm_area_struct *vma);
253 struct reservation_object *v3d_prime_res_obj(struct drm_gem_object *obj);
254 int v3d_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
255 struct sg_table *v3d_prime_get_sg_table(struct drm_gem_object *obj);
256 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev,
257 struct dma_buf_attachment *attach,
258 struct sg_table *sgt);
261 int v3d_debugfs_init(struct drm_minor *minor);
264 extern const struct dma_fence_ops v3d_fence_ops;
265 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
268 int v3d_gem_init(struct drm_device *dev);
269 void v3d_gem_destroy(struct drm_device *dev);
270 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
271 struct drm_file *file_priv);
272 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
273 struct drm_file *file_priv);
274 void v3d_exec_put(struct v3d_exec_info *exec);
275 void v3d_reset(struct v3d_dev *v3d);
276 void v3d_invalidate_caches(struct v3d_dev *v3d);
277 void v3d_flush_caches(struct v3d_dev *v3d);
280 void v3d_irq_init(struct v3d_dev *v3d);
281 void v3d_irq_enable(struct v3d_dev *v3d);
282 void v3d_irq_disable(struct v3d_dev *v3d);
283 void v3d_irq_reset(struct v3d_dev *v3d);
286 int v3d_mmu_get_offset(struct drm_file *file_priv, struct v3d_bo *bo,
288 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
289 void v3d_mmu_insert_ptes(struct v3d_bo *bo);
290 void v3d_mmu_remove_ptes(struct v3d_bo *bo);
293 int v3d_sched_init(struct v3d_dev *v3d);
294 void v3d_sched_fini(struct v3d_dev *v3d);