drivers/gpu/drm/tegra/dc.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/iommu.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/reset.h>
  15
  16 #include <soc/tegra/pmc.h>
  17
  18 #include "dc.h"
  19 #include "drm.h"
  20 #include "gem.h"
  21
  22 #include <drm/drm_atomic.h>
  23 #include <drm/drm_atomic_helper.h>
  24 #include <drm/drm_plane_helper.h>
  25
  26 struct tegra_dc_soc_info {
  27         bool supports_border_color;
  28         bool supports_interlacing;
  29         bool supports_cursor;
  30         bool supports_block_linear;
  31         unsigned int pitch_align;
  32         bool has_powergate;
  33         bool broken_reset;
  34 };
  35
  36 struct tegra_plane {
  37         struct drm_plane base;
  38         unsigned int index;
  39 };
  40
  41 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
  42 {
  43         return container_of(plane, struct tegra_plane, base);
  44 }
  45
  46 struct tegra_dc_state {
  47         struct drm_crtc_state base;
  48
  49         struct clk *clk;
  50         unsigned long pclk;
  51         unsigned int div;
  52
  53         u32 planes;
  54 };
  55
  56 static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
  57 {
  58         if (state)
  59                 return container_of(state, struct tegra_dc_state, base);
  60
  61         return NULL;
  62 }
  63
  64 struct tegra_plane_state {
  65         struct drm_plane_state base;
  66
  67         struct tegra_bo_tiling tiling;
  68         u32 format;
  69         u32 swap;
  70 };
  71
  72 static inline struct tegra_plane_state *
  73 to_tegra_plane_state(struct drm_plane_state *state)
  74 {
  75         if (state)
  76                 return container_of(state, struct tegra_plane_state, base);
  77
  78         return NULL;
  79 }
  80
  81 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
  82 {
  83         stats->frames = 0;
  84         stats->vblank = 0;
  85         stats->underflow = 0;
  86         stats->overflow = 0;
  87 }
  88
  89 /*
  90  * Reads the active copy of a register. This takes the dc->lock spinlock to
  91  * prevent races with the VBLANK processing which also needs access to the
  92  * active copy of some registers.
  93  */
  94 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
  95 {
  96         unsigned long flags;
  97         u32 value;
  98
  99         spin_lock_irqsave(&dc->lock, flags);
 100
 101         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
 102         value = tegra_dc_readl(dc, offset);
 103         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
 104
 105         spin_unlock_irqrestore(&dc->lock, flags);
 106         return value;
 107 }
 108
 109 /*
 110  * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
 111  * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
 112  * Latching happens mmediately if the display controller is in STOP mode or
 113  * on the next frame boundary otherwise.
 114  *
 115  * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
 116  * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
 117  * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
 118  * into the ACTIVE copy, either immediately if the display controller is in
 119  * STOP mode, or at the next frame boundary otherwise.
 120  */
 121 void tegra_dc_commit(struct tegra_dc *dc)
 122 {
 123         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 124         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 125 }
 126
 127 static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
 128 {
 129         /* assume no swapping of fetched data */
 130         if (swap)
 131                 *swap = BYTE_SWAP_NOSWAP;
 132
 133         switch (fourcc) {
 134         case DRM_FORMAT_XBGR8888:
 135                 *format = WIN_COLOR_DEPTH_R8G8B8A8;
 136                 break;
 137
 138         case DRM_FORMAT_XRGB8888:
 139                 *format = WIN_COLOR_DEPTH_B8G8R8A8;
 140                 break;
 141
 142         case DRM_FORMAT_RGB565:
 143                 *format = WIN_COLOR_DEPTH_B5G6R5;
 144                 break;
 145
 146         case DRM_FORMAT_UYVY:
 147                 *format = WIN_COLOR_DEPTH_YCbCr422;
 148                 break;
 149
 150         case DRM_FORMAT_YUYV:
 151                 if (swap)
 152                         *swap = BYTE_SWAP_SWAP2;
 153
 154                 *format = WIN_COLOR_DEPTH_YCbCr422;
 155                 break;
 156
 157         case DRM_FORMAT_YUV420:
 158                 *format = WIN_COLOR_DEPTH_YCbCr420P;
 159                 break;
 160
 161         case DRM_FORMAT_YUV422:
 162                 *format = WIN_COLOR_DEPTH_YCbCr422P;
 163                 break;
 164
 165         default:
 166                 return -EINVAL;
 167         }
 168
 169         return 0;
 170 }
 171
 172 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
 173 {
 174         switch (format) {
 175         case WIN_COLOR_DEPTH_YCbCr422:
 176         case WIN_COLOR_DEPTH_YUV422:
 177                 if (planar)
 178                         *planar = false;
 179
 180                 return true;
 181
 182         case WIN_COLOR_DEPTH_YCbCr420P:
 183         case WIN_COLOR_DEPTH_YUV420P:
 184         case WIN_COLOR_DEPTH_YCbCr422P:
 185         case WIN_COLOR_DEPTH_YUV422P:
 186         case WIN_COLOR_DEPTH_YCbCr422R:
 187         case WIN_COLOR_DEPTH_YUV422R:
 188         case WIN_COLOR_DEPTH_YCbCr422RA:
 189         case WIN_COLOR_DEPTH_YUV422RA:
 190                 if (planar)
 191                         *planar = true;
 192
 193                 return true;
 194         }
 195
 196         if (planar)
 197                 *planar = false;
 198
 199         return false;
 200 }
 201
 202 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 203                                   unsigned int bpp)
 204 {
 205         fixed20_12 outf = dfixed_init(out);
 206         fixed20_12 inf = dfixed_init(in);
 207         u32 dda_inc;
 208         int max;
 209
 210         if (v)
 211                 max = 15;
 212         else {
 213                 switch (bpp) {
 214                 case 2:
 215                         max = 8;
 216                         break;
 217
 218                 default:
 219                         WARN_ON_ONCE(1);
 220                         /* fallthrough */
 221                 case 4:
 222                         max = 4;
 223                         break;
 224                 }
 225         }
 226
 227         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 228         inf.full -= dfixed_const(1);
 229
 230         dda_inc = dfixed_div(inf, outf);
 231         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 232
 233         return dda_inc;
 234 }
 235
 236 static inline u32 compute_initial_dda(unsigned int in)
 237 {
 238         fixed20_12 inf = dfixed_init(in);
 239         return dfixed_frac(inf);
 240 }
 241
 242 static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
 243                                   const struct tegra_dc_window *window)
 244 {
 245         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 246         unsigned long value, flags;
 247         bool yuv, planar;
 248
 249         /*
 250          * For YUV planar modes, the number of bytes per pixel takes into
 251          * account only the luma component and therefore is 1.
 252          */
 253         yuv = tegra_dc_format_is_yuv(window->format, &planar);
 254         if (!yuv)
 255                 bpp = window->bits_per_pixel / 8;
 256         else
 257                 bpp = planar ? 1 : 2;
 258
 259         spin_lock_irqsave(&dc->lock, flags);
 260
 261         value = WINDOW_A_SELECT << index;
 262         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 263
 264         tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
 265         tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
 266
 267         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 268         tegra_dc_writel(dc, value, DC_WIN_POSITION);
 269
 270         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 271         tegra_dc_writel(dc, value, DC_WIN_SIZE);
 272
 273         h_offset = window->src.x * bpp;
 274         v_offset = window->src.y;
 275         h_size = window->src.w * bpp;
 276         v_size = window->src.h;
 277
 278         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 279         tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
 280
 281         /*
 282          * For DDA computations the number of bytes per pixel for YUV planar
 283          * modes needs to take into account all Y, U and V components.
 284          */
 285         if (yuv && planar)
 286                 bpp = 2;
 287
 288         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 289         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 290
 291         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 292         tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
 293
 294         h_dda = compute_initial_dda(window->src.x);
 295         v_dda = compute_initial_dda(window->src.y);
 296
 297         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
 298         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
 299
 300         tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
 301         tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
 302
 303         tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
 304
 305         if (yuv && planar) {
 306                 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
 307                 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
 308                 value = window->stride[1] << 16 | window->stride[0];
 309                 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
 310         } else {
 311                 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
 312         }
 313
 314         if (window->bottom_up)
 315                 v_offset += window->src.h - 1;
 316
 317         tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 318         tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 319
 320         if (dc->soc->supports_block_linear) {
 321                 unsigned long height = window->tiling.value;
 322
 323                 switch (window->tiling.mode) {
 324                 case TEGRA_BO_TILING_MODE_PITCH:
 325                         value = DC_WINBUF_SURFACE_KIND_PITCH;
 326                         break;
 327
 328                 case TEGRA_BO_TILING_MODE_TILED:
 329                         value = DC_WINBUF_SURFACE_KIND_TILED;
 330                         break;
 331
 332                 case TEGRA_BO_TILING_MODE_BLOCK:
 333                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 334                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 335                         break;
 336                 }
 337
 338                 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
 339         } else {
 340                 switch (window->tiling.mode) {
 341                 case TEGRA_BO_TILING_MODE_PITCH:
 342                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 343                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 344                         break;
 345
 346                 case TEGRA_BO_TILING_MODE_TILED:
 347                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 348                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
 349                         break;
 350
 351                 case TEGRA_BO_TILING_MODE_BLOCK:
 352                         /*
 353                          * No need to handle this here because ->atomic_check
 354                          * will already have filtered it out.
 355                          */
 356                         break;
 357                 }
 358
 359                 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
 360         }
 361
 362         value = WIN_ENABLE;
 363
 364         if (yuv) {
 365                 /* setup default colorspace conversion coefficients */
 366                 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
 367                 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
 368                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
 369                 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
 370                 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
 371                 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
 372                 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
 373                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
 374
 375                 value |= CSC_ENABLE;
 376         } else if (window->bits_per_pixel < 24) {
 377                 value |= COLOR_EXPAND;
 378         }
 379
 380         if (window->bottom_up)
 381                 value |= V_DIRECTION;
 382
 383         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 384
 385         /*
 386          * Disable blending and assume Window A is the bottom-most window,
 387          * Window C is the top-most window and Window B is in the middle.
 388          */
 389         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
 390         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
 391
 392         switch (index) {
 393         case 0:
 394                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
 395                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 396                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 397                 break;
 398
 399         case 1:
 400                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 401                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 402                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 403                 break;
 404
 405         case 2:
 406                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 407                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
 408                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
 409                 break;
 410         }
 411
 412         spin_unlock_irqrestore(&dc->lock, flags);
 413 }
 414
 415 static void tegra_plane_destroy(struct drm_plane *plane)
 416 {
 417         struct tegra_plane *p = to_tegra_plane(plane);
 418
 419         drm_plane_cleanup(plane);
 420         kfree(p);
 421 }
 422
 423 static const u32 tegra_primary_plane_formats[] = {
 424         DRM_FORMAT_XBGR8888,
 425         DRM_FORMAT_XRGB8888,
 426         DRM_FORMAT_RGB565,
 427 };
 428
 429 static void tegra_primary_plane_destroy(struct drm_plane *plane)
 430 {
 431         tegra_plane_destroy(plane);
 432 }
 433
 434 static void tegra_plane_reset(struct drm_plane *plane)
 435 {
 436         struct tegra_plane_state *state;
 437
 438         if (plane->state)
 439                 __drm_atomic_helper_plane_destroy_state(plane->state);
 440
 441         kfree(plane->state);
 442         plane->state = NULL;
 443
 444         state = kzalloc(sizeof(*state), GFP_KERNEL);
 445         if (state) {
 446                 plane->state = &state->base;
 447                 plane->state->plane = plane;
 448         }
 449 }
 450
 451 static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
 452 {
 453         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 454         struct tegra_plane_state *copy;
 455
 456         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
 457         if (!copy)
 458                 return NULL;
 459
 460         __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
 461         copy->tiling = state->tiling;
 462         copy->format = state->format;
 463         copy->swap = state->swap;
 464
 465         return &copy->base;
 466 }
 467
 468 static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
 469                                              struct drm_plane_state *state)
 470 {
 471         __drm_atomic_helper_plane_destroy_state(state);
 472         kfree(state);
 473 }
 474
 475 static const struct drm_plane_funcs tegra_primary_plane_funcs = {
 476         .update_plane = drm_atomic_helper_update_plane,
 477         .disable_plane = drm_atomic_helper_disable_plane,
 478         .destroy = tegra_primary_plane_destroy,
 479         .reset = tegra_plane_reset,
 480         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 481         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 482 };
 483
 484 static int tegra_plane_state_add(struct tegra_plane *plane,
 485                                  struct drm_plane_state *state)
 486 {
 487         struct drm_crtc_state *crtc_state;
 488         struct tegra_dc_state *tegra;
 489         struct drm_rect clip;
 490         int err;
 491
 492         /* Propagate errors from allocation or locking failures. */
 493         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
 494         if (IS_ERR(crtc_state))
 495                 return PTR_ERR(crtc_state);
 496
 497         clip.x1 = 0;
 498         clip.y1 = 0;
 499         clip.x2 = crtc_state->mode.hdisplay;
 500         clip.y2 = crtc_state->mode.vdisplay;
 501
 502         /* Check plane state for visibility and calculate clipping bounds */
 503         err = drm_plane_helper_check_state(state, &clip, 0, INT_MAX,
 504                                            true, true);
 505         if (err < 0)
 506                 return err;
 507
 508         tegra = to_dc_state(crtc_state);
 509
 510         tegra->planes |= WIN_A_ACT_REQ << plane->index;
 511
 512         return 0;
 513 }
 514
 515 static int tegra_plane_atomic_check(struct drm_plane *plane,
 516                                     struct drm_plane_state *state)
 517 {
 518         struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
 519         struct tegra_bo_tiling *tiling = &plane_state->tiling;
 520         struct tegra_plane *tegra = to_tegra_plane(plane);
 521         struct tegra_dc *dc = to_tegra_dc(state->crtc);
 522         int err;
 523
 524         /* no need for further checks if the plane is being disabled */
 525         if (!state->crtc)
 526                 return 0;
 527
 528         err = tegra_dc_format(state->fb->format->format, &plane_state->format,
 529                               &plane_state->swap);
 530         if (err < 0)
 531                 return err;
 532
 533         err = tegra_fb_get_tiling(state->fb, tiling);
 534         if (err < 0)
 535                 return err;
 536
 537         if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
 538             !dc->soc->supports_block_linear) {
 539                 DRM_ERROR("hardware doesn't support block linear mode\n");
 540                 return -EINVAL;
 541         }
 542
 543         /*
 544          * Tegra doesn't support different strides for U and V planes so we
 545          * error out if the user tries to display a framebuffer with such a
 546          * configuration.
 547          */
 548         if (state->fb->format->num_planes > 2) {
 549                 if (state->fb->pitches[2] != state->fb->pitches[1]) {
 550                         DRM_ERROR("unsupported UV-plane configuration\n");
 551                         return -EINVAL;
 552                 }
 553         }
 554
 555         err = tegra_plane_state_add(tegra, state);
 556         if (err < 0)
 557                 return err;
 558
 559         return 0;
 560 }
 561
 562 static void tegra_dc_disable_window(struct tegra_dc *dc, int index)
 563 {
 564         unsigned long flags;
 565         u32 value;
 566
 567         spin_lock_irqsave(&dc->lock, flags);
 568
 569         value = WINDOW_A_SELECT << index;
 570         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 571
 572         value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
 573         value &= ~WIN_ENABLE;
 574         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 575
 576         spin_unlock_irqrestore(&dc->lock, flags);
 577 }
 578
 579 static void tegra_plane_atomic_update(struct drm_plane *plane,
 580                                       struct drm_plane_state *old_state)
 581 {
 582         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 583         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 584         struct drm_framebuffer *fb = plane->state->fb;
 585         struct tegra_plane *p = to_tegra_plane(plane);
 586         struct tegra_dc_window window;
 587         unsigned int i;
 588
 589         /* rien ne va plus */
 590         if (!plane->state->crtc || !plane->state->fb)
 591                 return;
 592
 593         if (!plane->state->visible)
 594                 return tegra_dc_disable_window(dc, p->index);
 595
 596         memset(&window, 0, sizeof(window));
 597         window.src.x = plane->state->src.x1 >> 16;
 598         window.src.y = plane->state->src.y1 >> 16;
 599         window.src.w = drm_rect_width(&plane->state->src) >> 16;
 600         window.src.h = drm_rect_height(&plane->state->src) >> 16;
 601         window.dst.x = plane->state->dst.x1;
 602         window.dst.y = plane->state->dst.y1;
 603         window.dst.w = drm_rect_width(&plane->state->dst);
 604         window.dst.h = drm_rect_height(&plane->state->dst);
 605         window.bits_per_pixel = fb->format->cpp[0] * 8;
 606         window.bottom_up = tegra_fb_is_bottom_up(fb);
 607
 608         /* copy from state */
 609         window.tiling = state->tiling;
 610         window.format = state->format;
 611         window.swap = state->swap;
 612
 613         for (i = 0; i < fb->format->num_planes; i++) {
 614                 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
 615
 616                 window.base[i] = bo->paddr + fb->offsets[i];
 617
 618                 /*
 619                  * Tegra uses a shared stride for UV planes. Framebuffers are
 620                  * already checked for this in the tegra_plane_atomic_check()
 621                  * function, so it's safe to ignore the V-plane pitch here.
 622                  */
 623                 if (i < 2)
 624                         window.stride[i] = fb->pitches[i];
 625         }
 626
 627         tegra_dc_setup_window(dc, p->index, &window);
 628 }
 629
 630 static void tegra_plane_atomic_disable(struct drm_plane *plane,
 631                                        struct drm_plane_state *old_state)
 632 {
 633         struct tegra_plane *p = to_tegra_plane(plane);
 634         struct tegra_dc *dc;
 635
 636         /* rien ne va plus */
 637         if (!old_state || !old_state->crtc)
 638                 return;
 639
 640         dc = to_tegra_dc(old_state->crtc);
 641
 642         tegra_dc_disable_window(dc, p->index);
 643 }
 644
 645 static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
 646         .atomic_check = tegra_plane_atomic_check,
 647         .atomic_update = tegra_plane_atomic_update,
 648         .atomic_disable = tegra_plane_atomic_disable,
 649 };
 650
 651 static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
 652                                                        struct tegra_dc *dc)
 653 {
 654         /*
 655          * Ideally this would use drm_crtc_mask(), but that would require the
 656          * CRTC to already be in the mode_config's list of CRTCs. However, it
 657          * will only be added to that list in the drm_crtc_init_with_planes()
 658          * (in tegra_dc_init()), which in turn requires registration of these
 659          * planes. So we have ourselves a nice little chicken and egg problem
 660          * here.
 661          *
 662          * We work around this by manually creating the mask from the number
 663          * of CRTCs that have been registered, and should therefore always be
 664          * the same as drm_crtc_index() after registration.
 665          */
 666         unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
 667         struct tegra_plane *plane;
 668         unsigned int num_formats;
 669         const u32 *formats;
 670         int err;
 671
 672         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 673         if (!plane)
 674                 return ERR_PTR(-ENOMEM);
 675
 676         num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
 677         formats = tegra_primary_plane_formats;
 678
 679         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 680                                        &tegra_primary_plane_funcs, formats,
 681                                        num_formats, NULL,
 682                                        DRM_PLANE_TYPE_PRIMARY, NULL);
 683         if (err < 0) {
 684                 kfree(plane);
 685                 return ERR_PTR(err);
 686         }
 687
 688         drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
 689
 690         return &plane->base;
 691 }
 692
 693 static const u32 tegra_cursor_plane_formats[] = {
 694         DRM_FORMAT_RGBA8888,
 695 };
 696
 697 static int tegra_cursor_atomic_check(struct drm_plane *plane,
 698                                      struct drm_plane_state *state)
 699 {
 700         struct tegra_plane *tegra = to_tegra_plane(plane);
 701         int err;
 702
 703         /* no need for further checks if the plane is being disabled */
 704         if (!state->crtc)
 705                 return 0;
 706
 707         /* scaling not supported for cursor */
 708         if ((state->src_w >> 16 != state->crtc_w) ||
 709             (state->src_h >> 16 != state->crtc_h))
 710                 return -EINVAL;
 711
 712         /* only square cursors supported */
 713         if (state->src_w != state->src_h)
 714                 return -EINVAL;
 715
 716         if (state->crtc_w != 32 && state->crtc_w != 64 &&
 717             state->crtc_w != 128 && state->crtc_w != 256)
 718                 return -EINVAL;
 719
 720         err = tegra_plane_state_add(tegra, state);
 721         if (err < 0)
 722                 return err;
 723
 724         return 0;
 725 }
 726
 727 static void tegra_cursor_atomic_update(struct drm_plane *plane,
 728                                        struct drm_plane_state *old_state)
 729 {
 730         struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
 731         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 732         struct drm_plane_state *state = plane->state;
 733         u32 value = CURSOR_CLIP_DISPLAY;
 734
 735         /* rien ne va plus */
 736         if (!plane->state->crtc || !plane->state->fb)
 737                 return;
 738
 739         switch (state->crtc_w) {
 740         case 32:
 741                 value |= CURSOR_SIZE_32x32;
 742                 break;
 743
 744         case 64:
 745                 value |= CURSOR_SIZE_64x64;
 746                 break;
 747
 748         case 128:
 749                 value |= CURSOR_SIZE_128x128;
 750                 break;
 751
 752         case 256:
 753                 value |= CURSOR_SIZE_256x256;
 754                 break;
 755
 756         default:
 757                 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
 758                      state->crtc_h);
 759                 return;
 760         }
 761
 762         value |= (bo->paddr >> 10) & 0x3fffff;
 763         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
 764
 765 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 766         value = (bo->paddr >> 32) & 0x3;
 767         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
 768 #endif
 769
 770         /* enable cursor and set blend mode */
 771         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 772         value |= CURSOR_ENABLE;
 773         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 774
 775         value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
 776         value &= ~CURSOR_DST_BLEND_MASK;
 777         value &= ~CURSOR_SRC_BLEND_MASK;
 778         value |= CURSOR_MODE_NORMAL;
 779         value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
 780         value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
 781         value |= CURSOR_ALPHA;
 782         tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
 783
 784         /* position the cursor */
 785         value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
 786         tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
 787 }
 788
 789 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
 790                                         struct drm_plane_state *old_state)
 791 {
 792         struct tegra_dc *dc;
 793         u32 value;
 794
 795         /* rien ne va plus */
 796         if (!old_state || !old_state->crtc)
 797                 return;
 798
 799         dc = to_tegra_dc(old_state->crtc);
 800
 801         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 802         value &= ~CURSOR_ENABLE;
 803         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 804 }
 805
 806 static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
 807         .update_plane = drm_atomic_helper_update_plane,
 808         .disable_plane = drm_atomic_helper_disable_plane,
 809         .destroy = tegra_plane_destroy,
 810         .reset = tegra_plane_reset,
 811         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 812         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 813 };
 814
 815 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
 816         .atomic_check = tegra_cursor_atomic_check,
 817         .atomic_update = tegra_cursor_atomic_update,
 818         .atomic_disable = tegra_cursor_atomic_disable,
 819 };
 820
 821 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
 822                                                       struct tegra_dc *dc)
 823 {
 824         struct tegra_plane *plane;
 825         unsigned int num_formats;
 826         const u32 *formats;
 827         int err;
 828
 829         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 830         if (!plane)
 831                 return ERR_PTR(-ENOMEM);
 832
 833         /*
 834          * This index is kind of fake. The cursor isn't a regular plane, but
 835          * its update and activation request bits in DC_CMD_STATE_CONTROL do
 836          * use the same programming. Setting this fake index here allows the
 837          * code in tegra_add_plane_state() to do the right thing without the
 838          * need to special-casing the cursor plane.
 839          */
 840         plane->index = 6;
 841
 842         num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
 843         formats = tegra_cursor_plane_formats;
 844
 845         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
 846                                        &tegra_cursor_plane_funcs, formats,
 847                                        num_formats, NULL,
 848                                        DRM_PLANE_TYPE_CURSOR, NULL);
 849         if (err < 0) {
 850                 kfree(plane);
 851                 return ERR_PTR(err);
 852         }
 853
 854         drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
 855
 856         return &plane->base;
 857 }
 858
 859 static void tegra_overlay_plane_destroy(struct drm_plane *plane)
 860 {
 861         tegra_plane_destroy(plane);
 862 }
 863
 864 static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
 865         .update_plane = drm_atomic_helper_update_plane,
 866         .disable_plane = drm_atomic_helper_disable_plane,
 867         .destroy = tegra_overlay_plane_destroy,
 868         .reset = tegra_plane_reset,
 869         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 870         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 871 };
 872
 873 static const uint32_t tegra_overlay_plane_formats[] = {
 874         DRM_FORMAT_XBGR8888,
 875         DRM_FORMAT_XRGB8888,
 876         DRM_FORMAT_RGB565,
 877         DRM_FORMAT_UYVY,
 878         DRM_FORMAT_YUYV,
 879         DRM_FORMAT_YUV420,
 880         DRM_FORMAT_YUV422,
 881 };
 882
 883 static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
 884         .atomic_check = tegra_plane_atomic_check,
 885         .atomic_update = tegra_plane_atomic_update,
 886         .atomic_disable = tegra_plane_atomic_disable,
 887 };
 888
 889 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
 890                                                        struct tegra_dc *dc,
 891                                                        unsigned int index)
 892 {
 893         struct tegra_plane *plane;
 894         unsigned int num_formats;
 895         const u32 *formats;
 896         int err;
 897
 898         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 899         if (!plane)
 900                 return ERR_PTR(-ENOMEM);
 901
 902         plane->index = index;
 903
 904         num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
 905         formats = tegra_overlay_plane_formats;
 906
 907         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
 908                                        &tegra_overlay_plane_funcs, formats,
 909                                        num_formats, NULL,
 910                                        DRM_PLANE_TYPE_OVERLAY, NULL);
 911         if (err < 0) {
 912                 kfree(plane);
 913                 return ERR_PTR(err);
 914         }
 915
 916         drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
 917
 918         return &plane->base;
 919 }
 920
 921 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
 922 {
 923         struct drm_plane *plane;
 924         unsigned int i;
 925
 926         for (i = 0; i < 2; i++) {
 927                 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
 928                 if (IS_ERR(plane))
 929                         return PTR_ERR(plane);
 930         }
 931
 932         return 0;
 933 }
 934
 935 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
 936 {
 937         struct tegra_dc *dc = to_tegra_dc(crtc);
 938
 939         if (dc->syncpt)
 940                 return host1x_syncpt_read(dc->syncpt);
 941
 942         /* fallback to software emulated VBLANK counter */
 943         return drm_crtc_vblank_count(&dc->base);
 944 }
 945
 946 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
 947 {
 948         struct tegra_dc *dc = to_tegra_dc(crtc);
 949         unsigned long value, flags;
 950
 951         spin_lock_irqsave(&dc->lock, flags);
 952
 953         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 954         value |= VBLANK_INT;
 955         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 956
 957         spin_unlock_irqrestore(&dc->lock, flags);
 958
 959         return 0;
 960 }
 961
 962 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
 963 {
 964         struct tegra_dc *dc = to_tegra_dc(crtc);
 965         unsigned long value, flags;
 966
 967         spin_lock_irqsave(&dc->lock, flags);
 968
 969         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 970         value &= ~VBLANK_INT;
 971         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 972
 973         spin_unlock_irqrestore(&dc->lock, flags);
 974 }
 975
 976 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
 977 {
 978         struct drm_device *drm = dc->base.dev;
 979         struct drm_crtc *crtc = &dc->base;
 980         unsigned long flags, base;
 981         struct tegra_bo *bo;
 982
 983         spin_lock_irqsave(&drm->event_lock, flags);
 984
 985         if (!dc->event) {
 986                 spin_unlock_irqrestore(&drm->event_lock, flags);
 987                 return;
 988         }
 989
 990         bo = tegra_fb_get_plane(crtc->primary->fb, 0);
 991
 992         spin_lock(&dc->lock);
 993
 994         /* check if new start address has been latched */
 995         tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
 996         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
 997         base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
 998         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
 999
1000         spin_unlock(&dc->lock);
1001
1002         if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
1003                 drm_crtc_send_vblank_event(crtc, dc->event);
1004                 drm_crtc_vblank_put(crtc);
1005                 dc->event = NULL;
1006         }
1007
1008         spin_unlock_irqrestore(&drm->event_lock, flags);
1009 }
1010
1011 static void tegra_dc_destroy(struct drm_crtc *crtc)
1012 {
1013         drm_crtc_cleanup(crtc);
1014 }
1015
1016 static void tegra_crtc_reset(struct drm_crtc *crtc)
1017 {
1018         struct tegra_dc_state *state;
1019
1020         if (crtc->state)
1021                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1022
1023         kfree(crtc->state);
1024         crtc->state = NULL;
1025
1026         state = kzalloc(sizeof(*state), GFP_KERNEL);
1027         if (state) {
1028                 crtc->state = &state->base;
1029                 crtc->state->crtc = crtc;
1030         }
1031
1032         drm_crtc_vblank_reset(crtc);
1033 }
1034
1035 static struct drm_crtc_state *
1036 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1037 {
1038         struct tegra_dc_state *state = to_dc_state(crtc->state);
1039         struct tegra_dc_state *copy;
1040
1041         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1042         if (!copy)
1043                 return NULL;
1044
1045         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1046         copy->clk = state->clk;
1047         copy->pclk = state->pclk;
1048         copy->div = state->div;
1049         copy->planes = state->planes;
1050
1051         return &copy->base;
1052 }
1053
1054 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1055                                             struct drm_crtc_state *state)
1056 {
1057         __drm_atomic_helper_crtc_destroy_state(state);
1058         kfree(state);
1059 }
1060
1061 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1062         .page_flip = drm_atomic_helper_page_flip,
1063         .set_config = drm_atomic_helper_set_config,
1064         .destroy = tegra_dc_destroy,
1065         .reset = tegra_crtc_reset,
1066         .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1067         .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1068         .get_vblank_counter = tegra_dc_get_vblank_counter,
1069         .enable_vblank = tegra_dc_enable_vblank,
1070         .disable_vblank = tegra_dc_disable_vblank,
1071 };
1072
1073 static int tegra_dc_set_timings(struct tegra_dc *dc,
1074                                 struct drm_display_mode *mode)
1075 {
1076         unsigned int h_ref_to_sync = 1;
1077         unsigned int v_ref_to_sync = 1;
1078         unsigned long value;
1079
1080         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1081
1082         value = (v_ref_to_sync << 16) | h_ref_to_sync;
1083         tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1084
1085         value = ((mode->vsync_end - mode->vsync_start) << 16) |
1086                 ((mode->hsync_end - mode->hsync_start) <<  0);
1087         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1088
1089         value = ((mode->vtotal - mode->vsync_end) << 16) |
1090                 ((mode->htotal - mode->hsync_end) <<  0);
1091         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1092
1093         value = ((mode->vsync_start - mode->vdisplay) << 16) |
1094                 ((mode->hsync_start - mode->hdisplay) <<  0);
1095         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1096
1097         value = (mode->vdisplay << 16) | mode->hdisplay;
1098         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1099
1100         return 0;
1101 }
1102
1103 /**
1104  * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1105  *     state
1106  * @dc: display controller
1107  * @crtc_state: CRTC atomic state
1108  * @clk: parent clock for display controller
1109  * @pclk: pixel clock
1110  * @div: shift clock divider
1111  *
1112  * Returns:
1113  * 0 on success or a negative error-code on failure.
1114  */
1115 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1116                                struct drm_crtc_state *crtc_state,
1117                                struct clk *clk, unsigned long pclk,
1118                                unsigned int div)
1119 {
1120         struct tegra_dc_state *state = to_dc_state(crtc_state);
1121
1122         if (!clk_has_parent(dc->clk, clk))
1123                 return -EINVAL;
1124
1125         state->clk = clk;
1126         state->pclk = pclk;
1127         state->div = div;
1128
1129         return 0;
1130 }
1131
1132 static void tegra_dc_commit_state(struct tegra_dc *dc,
1133                                   struct tegra_dc_state *state)
1134 {
1135         u32 value;
1136         int err;
1137
1138         err = clk_set_parent(dc->clk, state->clk);
1139         if (err < 0)
1140                 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1141
1142         /*
1143          * Outputs may not want to change the parent clock rate. This is only
1144          * relevant to Tegra20 where only a single display PLL is available.
1145          * Since that PLL would typically be used for HDMI, an internal LVDS
1146          * panel would need to be driven by some other clock such as PLL_P
1147          * which is shared with other peripherals. Changing the clock rate
1148          * should therefore be avoided.
1149          */
1150         if (state->pclk > 0) {
1151                 err = clk_set_rate(state->clk, state->pclk);
1152                 if (err < 0)
1153                         dev_err(dc->dev,
1154                                 "failed to set clock rate to %lu Hz\n",
1155                                 state->pclk);
1156         }
1157
1158         DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1159                       state->div);
1160         DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1161
1162         value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1163         tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1164 }
1165
1166 static void tegra_dc_stop(struct tegra_dc *dc)
1167 {
1168         u32 value;
1169
1170         /* stop the display controller */
1171         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1172         value &= ~DISP_CTRL_MODE_MASK;
1173         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1174
1175         tegra_dc_commit(dc);
1176 }
1177
1178 static bool tegra_dc_idle(struct tegra_dc *dc)
1179 {
1180         u32 value;
1181
1182         value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1183
1184         return (value & DISP_CTRL_MODE_MASK) == 0;
1185 }
1186
1187 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1188 {
1189         timeout = jiffies + msecs_to_jiffies(timeout);
1190
1191         while (time_before(jiffies, timeout)) {
1192                 if (tegra_dc_idle(dc))
1193                         return 0;
1194
1195                 usleep_range(1000, 2000);
1196         }
1197
1198         dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1199         return -ETIMEDOUT;
1200 }
1201
1202 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1203                                       struct drm_crtc_state *old_state)
1204 {
1205         struct tegra_dc *dc = to_tegra_dc(crtc);
1206         u32 value;
1207
1208         if (!tegra_dc_idle(dc)) {
1209                 tegra_dc_stop(dc);
1210
1211                 /*
1212                  * Ignore the return value, there isn't anything useful to do
1213                  * in case this fails.
1214                  */
1215                 tegra_dc_wait_idle(dc, 100);
1216         }
1217
1218         /*
1219          * This should really be part of the RGB encoder driver, but clearing
1220          * these bits has the side-effect of stopping the display controller.
1221          * When that happens no VBLANK interrupts will be raised. At the same
1222          * time the encoder is disabled before the display controller, so the
1223          * above code is always going to timeout waiting for the controller
1224          * to go idle.
1225          *
1226          * Given the close coupling between the RGB encoder and the display
1227          * controller doing it here is still kind of okay. None of the other
1228          * encoder drivers require these bits to be cleared.
1229          *
1230          * XXX: Perhaps given that the display controller is switched off at
1231          * this point anyway maybe clearing these bits isn't even useful for
1232          * the RGB encoder?
1233          */
1234         if (dc->rgb) {
1235                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1236                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1237                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1238                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1239         }
1240
1241         tegra_dc_stats_reset(&dc->stats);
1242         drm_crtc_vblank_off(crtc);
1243
1244         pm_runtime_put_sync(dc->dev);
1245 }
1246
1247 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1248                                      struct drm_crtc_state *old_state)
1249 {
1250         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1251         struct tegra_dc_state *state = to_dc_state(crtc->state);
1252         struct tegra_dc *dc = to_tegra_dc(crtc);
1253         u32 value;
1254
1255         pm_runtime_get_sync(dc->dev);
1256
1257         /* initialize display controller */
1258         if (dc->syncpt) {
1259                 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1260
1261                 value = SYNCPT_CNTRL_NO_STALL;
1262                 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1263
1264                 value = SYNCPT_VSYNC_ENABLE | syncpt;
1265                 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1266         }
1267
1268         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1269                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1270         tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1271
1272         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1273                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1274         tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1275
1276         /* initialize timer */
1277         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1278                 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1279         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1280
1281         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1282                 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1283         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1284
1285         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1286                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1287         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1288
1289         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1290                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1291         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1292
1293         if (dc->soc->supports_border_color)
1294                 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1295
1296         /* apply PLL and pixel clock changes */
1297         tegra_dc_commit_state(dc, state);
1298
1299         /* program display mode */
1300         tegra_dc_set_timings(dc, mode);
1301
1302         /* interlacing isn't supported yet, so disable it */
1303         if (dc->soc->supports_interlacing) {
1304                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1305                 value &= ~INTERLACE_ENABLE;
1306                 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1307         }
1308
1309         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1310         value &= ~DISP_CTRL_MODE_MASK;
1311         value |= DISP_CTRL_MODE_C_DISPLAY;
1312         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1313
1314         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1315         value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1316                  PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1317         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1318
1319         tegra_dc_commit(dc);
1320
1321         drm_crtc_vblank_on(crtc);
1322 }
1323
1324 static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1325                                    struct drm_crtc_state *state)
1326 {
1327         return 0;
1328 }
1329
1330 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1331                                     struct drm_crtc_state *old_crtc_state)
1332 {
1333         struct tegra_dc *dc = to_tegra_dc(crtc);
1334
1335         if (crtc->state->event) {
1336                 crtc->state->event->pipe = drm_crtc_index(crtc);
1337
1338                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1339
1340                 dc->event = crtc->state->event;
1341                 crtc->state->event = NULL;
1342         }
1343 }
1344
1345 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1346                                     struct drm_crtc_state *old_crtc_state)
1347 {
1348         struct tegra_dc_state *state = to_dc_state(crtc->state);
1349         struct tegra_dc *dc = to_tegra_dc(crtc);
1350
1351         tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1352         tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
1353 }
1354
1355 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1356         .atomic_check = tegra_crtc_atomic_check,
1357         .atomic_begin = tegra_crtc_atomic_begin,
1358         .atomic_flush = tegra_crtc_atomic_flush,
1359         .atomic_enable = tegra_crtc_atomic_enable,
1360         .atomic_disable = tegra_crtc_atomic_disable,
1361 };
1362
1363 static irqreturn_t tegra_dc_irq(int irq, void *data)
1364 {
1365         struct tegra_dc *dc = data;
1366         unsigned long status;
1367
1368         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1369         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1370
1371         if (status & FRAME_END_INT) {
1372                 /*
1373                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1374                 */
1375                 dc->stats.frames++;
1376         }
1377
1378         if (status & VBLANK_INT) {
1379                 /*
1380                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1381                 */
1382                 drm_crtc_handle_vblank(&dc->base);
1383                 tegra_dc_finish_page_flip(dc);
1384                 dc->stats.vblank++;
1385         }
1386
1387         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1388                 /*
1389                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1390                 */
1391                 dc->stats.underflow++;
1392         }
1393
1394         if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1395                 /*
1396                 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1397                 */
1398                 dc->stats.overflow++;
1399         }
1400
1401         return IRQ_HANDLED;
1402 }
1403
1404 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1405 {
1406         struct drm_info_node *node = s->private;
1407         struct tegra_dc *dc = node->info_ent->data;
1408         int err = 0;
1409
1410         drm_modeset_lock(&dc->base.mutex, NULL);
1411
1412         if (!dc->base.state->active) {
1413                 err = -EBUSY;
1414                 goto unlock;
1415         }
1416
1417 #define DUMP_REG(name)                                          \
1418         seq_printf(s, "%-40s %#05x %08x\n", #name, name,        \
1419                    tegra_dc_readl(dc, name))
1420
1421         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1422         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1423         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1424         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1425         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1426         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1427         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1428         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1429         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1430         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1431         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1432         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1433         DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1434         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1435         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1436         DUMP_REG(DC_CMD_SIGNAL_RAISE);
1437         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1438         DUMP_REG(DC_CMD_INT_STATUS);
1439         DUMP_REG(DC_CMD_INT_MASK);
1440         DUMP_REG(DC_CMD_INT_ENABLE);
1441         DUMP_REG(DC_CMD_INT_TYPE);
1442         DUMP_REG(DC_CMD_INT_POLARITY);
1443         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1444         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1445         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1446         DUMP_REG(DC_CMD_STATE_ACCESS);
1447         DUMP_REG(DC_CMD_STATE_CONTROL);
1448         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1449         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1450         DUMP_REG(DC_COM_CRC_CONTROL);
1451         DUMP_REG(DC_COM_CRC_CHECKSUM);
1452         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1453         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1454         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1455         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1456         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1457         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1458         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1459         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1460         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1461         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1462         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1463         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1464         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1465         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1466         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1467         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1468         DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1469         DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1470         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1471         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1472         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1473         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1474         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1475         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1476         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1477         DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1478         DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1479         DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1480         DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1481         DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1482         DUMP_REG(DC_COM_SPI_CONTROL);
1483         DUMP_REG(DC_COM_SPI_START_BYTE);
1484         DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1485         DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1486         DUMP_REG(DC_COM_HSPI_CS_DC);
1487         DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1488         DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1489         DUMP_REG(DC_COM_GPIO_CTRL);
1490         DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1491         DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1492         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1493         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1494         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1495         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1496         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1497         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1498         DUMP_REG(DC_DISP_REF_TO_SYNC);
1499         DUMP_REG(DC_DISP_SYNC_WIDTH);
1500         DUMP_REG(DC_DISP_BACK_PORCH);
1501         DUMP_REG(DC_DISP_ACTIVE);
1502         DUMP_REG(DC_DISP_FRONT_PORCH);
1503         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1504         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1505         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1506         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1507         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1508         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1509         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1510         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1511         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1512         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1513         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1514         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1515         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1516         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1517         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1518         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1519         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1520         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1521         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1522         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1523         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1524         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1525         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1526         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1527         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1528         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1529         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1530         DUMP_REG(DC_DISP_M0_CONTROL);
1531         DUMP_REG(DC_DISP_M1_CONTROL);
1532         DUMP_REG(DC_DISP_DI_CONTROL);
1533         DUMP_REG(DC_DISP_PP_CONTROL);
1534         DUMP_REG(DC_DISP_PP_SELECT_A);
1535         DUMP_REG(DC_DISP_PP_SELECT_B);
1536         DUMP_REG(DC_DISP_PP_SELECT_C);
1537         DUMP_REG(DC_DISP_PP_SELECT_D);
1538         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1539         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1540         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1541         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1542         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1543         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1544         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1545         DUMP_REG(DC_DISP_BORDER_COLOR);
1546         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1547         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1548         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1549         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1550         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1551         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1552         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1553         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1554         DUMP_REG(DC_DISP_CURSOR_POSITION);
1555         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1556         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1557         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1558         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1559         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1560         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1561         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1562         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1563         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1564         DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1565         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1566         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1567         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1568         DUMP_REG(DC_DISP_SD_CONTROL);
1569         DUMP_REG(DC_DISP_SD_CSC_COEFF);
1570         DUMP_REG(DC_DISP_SD_LUT(0));
1571         DUMP_REG(DC_DISP_SD_LUT(1));
1572         DUMP_REG(DC_DISP_SD_LUT(2));
1573         DUMP_REG(DC_DISP_SD_LUT(3));
1574         DUMP_REG(DC_DISP_SD_LUT(4));
1575         DUMP_REG(DC_DISP_SD_LUT(5));
1576         DUMP_REG(DC_DISP_SD_LUT(6));
1577         DUMP_REG(DC_DISP_SD_LUT(7));
1578         DUMP_REG(DC_DISP_SD_LUT(8));
1579         DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1580         DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1581         DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1582         DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1583         DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1584         DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1585         DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1586         DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1587         DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1588         DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1589         DUMP_REG(DC_DISP_SD_BL_TF(0));
1590         DUMP_REG(DC_DISP_SD_BL_TF(1));
1591         DUMP_REG(DC_DISP_SD_BL_TF(2));
1592         DUMP_REG(DC_DISP_SD_BL_TF(3));
1593         DUMP_REG(DC_DISP_SD_BL_CONTROL);
1594         DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1595         DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1596         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1597         DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1598         DUMP_REG(DC_WIN_WIN_OPTIONS);
1599         DUMP_REG(DC_WIN_BYTE_SWAP);
1600         DUMP_REG(DC_WIN_BUFFER_CONTROL);
1601         DUMP_REG(DC_WIN_COLOR_DEPTH);
1602         DUMP_REG(DC_WIN_POSITION);
1603         DUMP_REG(DC_WIN_SIZE);
1604         DUMP_REG(DC_WIN_PRESCALED_SIZE);
1605         DUMP_REG(DC_WIN_H_INITIAL_DDA);
1606         DUMP_REG(DC_WIN_V_INITIAL_DDA);
1607         DUMP_REG(DC_WIN_DDA_INC);
1608         DUMP_REG(DC_WIN_LINE_STRIDE);
1609         DUMP_REG(DC_WIN_BUF_STRIDE);
1610         DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1611         DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1612         DUMP_REG(DC_WIN_DV_CONTROL);
1613         DUMP_REG(DC_WIN_BLEND_NOKEY);
1614         DUMP_REG(DC_WIN_BLEND_1WIN);
1615         DUMP_REG(DC_WIN_BLEND_2WIN_X);
1616         DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1617         DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1618         DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1619         DUMP_REG(DC_WINBUF_START_ADDR);
1620         DUMP_REG(DC_WINBUF_START_ADDR_NS);
1621         DUMP_REG(DC_WINBUF_START_ADDR_U);
1622         DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1623         DUMP_REG(DC_WINBUF_START_ADDR_V);
1624         DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1625         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1626         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1627         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1628         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1629         DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1630         DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1631         DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1632         DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1633
1634 #undef DUMP_REG
1635
1636 unlock:
1637         drm_modeset_unlock(&dc->base.mutex);
1638         return err;
1639 }
1640
1641 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1642 {
1643         struct drm_info_node *node = s->private;
1644         struct tegra_dc *dc = node->info_ent->data;
1645         int err = 0;
1646         u32 value;
1647
1648         drm_modeset_lock(&dc->base.mutex, NULL);
1649
1650         if (!dc->base.state->active) {
1651                 err = -EBUSY;
1652                 goto unlock;
1653         }
1654
1655         value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1656         tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1657         tegra_dc_commit(dc);
1658
1659         drm_crtc_wait_one_vblank(&dc->base);
1660         drm_crtc_wait_one_vblank(&dc->base);
1661
1662         value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1663         seq_printf(s, "%08x\n", value);
1664
1665         tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1666
1667 unlock:
1668         drm_modeset_unlock(&dc->base.mutex);
1669         return err;
1670 }
1671
1672 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1673 {
1674         struct drm_info_node *node = s->private;
1675         struct tegra_dc *dc = node->info_ent->data;
1676
1677         seq_printf(s, "frames: %lu\n", dc->stats.frames);
1678         seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1679         seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1680         seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1681
1682         return 0;
1683 }
1684
1685 static struct drm_info_list debugfs_files[] = {
1686         { "regs", tegra_dc_show_regs, 0, NULL },
1687         { "crc", tegra_dc_show_crc, 0, NULL },
1688         { "stats", tegra_dc_show_stats, 0, NULL },
1689 };
1690
1691 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1692 {
1693         unsigned int i;
1694         char *name;
1695         int err;
1696
1697         name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1698         dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1699         kfree(name);
1700
1701         if (!dc->debugfs)
1702                 return -ENOMEM;
1703
1704         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1705                                     GFP_KERNEL);
1706         if (!dc->debugfs_files) {
1707                 err = -ENOMEM;
1708                 goto remove;
1709         }
1710
1711         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1712                 dc->debugfs_files[i].data = dc;
1713
1714         err = drm_debugfs_create_files(dc->debugfs_files,
1715                                        ARRAY_SIZE(debugfs_files),
1716                                        dc->debugfs, minor);
1717         if (err < 0)
1718                 goto free;
1719
1720         dc->minor = minor;
1721
1722         return 0;
1723
1724 free:
1725         kfree(dc->debugfs_files);
1726         dc->debugfs_files = NULL;
1727 remove:
1728         debugfs_remove(dc->debugfs);
1729         dc->debugfs = NULL;
1730
1731         return err;
1732 }
1733
1734 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1735 {
1736         drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1737                                  dc->minor);
1738         dc->minor = NULL;
1739
1740         kfree(dc->debugfs_files);
1741         dc->debugfs_files = NULL;
1742
1743         debugfs_remove(dc->debugfs);
1744         dc->debugfs = NULL;
1745
1746         return 0;
1747 }
1748
1749 static int tegra_dc_init(struct host1x_client *client)
1750 {
1751         struct drm_device *drm = dev_get_drvdata(client->parent);
1752         unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1753         struct tegra_dc *dc = host1x_client_to_dc(client);
1754         struct tegra_drm *tegra = drm->dev_private;
1755         struct drm_plane *primary = NULL;
1756         struct drm_plane *cursor = NULL;
1757         int err;
1758
1759         dc->syncpt = host1x_syncpt_request(dc->dev, flags);
1760         if (!dc->syncpt)
1761                 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1762
1763         if (tegra->domain) {
1764                 err = iommu_attach_device(tegra->domain, dc->dev);
1765                 if (err < 0) {
1766                         dev_err(dc->dev, "failed to attach to domain: %d\n",
1767                                 err);
1768                         return err;
1769                 }
1770
1771                 dc->domain = tegra->domain;
1772         }
1773
1774         primary = tegra_dc_primary_plane_create(drm, dc);
1775         if (IS_ERR(primary)) {
1776                 err = PTR_ERR(primary);
1777                 goto cleanup;
1778         }
1779
1780         if (dc->soc->supports_cursor) {
1781                 cursor = tegra_dc_cursor_plane_create(drm, dc);
1782                 if (IS_ERR(cursor)) {
1783                         err = PTR_ERR(cursor);
1784                         goto cleanup;
1785                 }
1786         }
1787
1788         err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1789                                         &tegra_crtc_funcs, NULL);
1790         if (err < 0)
1791                 goto cleanup;
1792
1793         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1794
1795         /*
1796          * Keep track of the minimum pitch alignment across all display
1797          * controllers.
1798          */
1799         if (dc->soc->pitch_align > tegra->pitch_align)
1800                 tegra->pitch_align = dc->soc->pitch_align;
1801
1802         err = tegra_dc_rgb_init(drm, dc);
1803         if (err < 0 && err != -ENODEV) {
1804                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1805                 goto cleanup;
1806         }
1807
1808         err = tegra_dc_add_planes(drm, dc);
1809         if (err < 0)
1810                 goto cleanup;
1811
1812         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1813                 err = tegra_dc_debugfs_init(dc, drm->primary);
1814                 if (err < 0)
1815                         dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1816         }
1817
1818         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1819                                dev_name(dc->dev), dc);
1820         if (err < 0) {
1821                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1822                         err);
1823                 goto cleanup;
1824         }
1825
1826         return 0;
1827
1828 cleanup:
1829         if (cursor)
1830                 drm_plane_cleanup(cursor);
1831
1832         if (primary)
1833                 drm_plane_cleanup(primary);
1834
1835         if (tegra->domain) {
1836                 iommu_detach_device(tegra->domain, dc->dev);
1837                 dc->domain = NULL;
1838         }
1839
1840         return err;
1841 }
1842
1843 static int tegra_dc_exit(struct host1x_client *client)
1844 {
1845         struct tegra_dc *dc = host1x_client_to_dc(client);
1846         int err;
1847
1848         devm_free_irq(dc->dev, dc->irq, dc);
1849
1850         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1851                 err = tegra_dc_debugfs_exit(dc);
1852                 if (err < 0)
1853                         dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1854         }
1855
1856         err = tegra_dc_rgb_exit(dc);
1857         if (err) {
1858                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1859                 return err;
1860         }
1861
1862         if (dc->domain) {
1863                 iommu_detach_device(dc->domain, dc->dev);
1864                 dc->domain = NULL;
1865         }
1866
1867         host1x_syncpt_free(dc->syncpt);
1868
1869         return 0;
1870 }
1871
1872 static const struct host1x_client_ops dc_client_ops = {
1873         .init = tegra_dc_init,
1874         .exit = tegra_dc_exit,
1875 };
1876
1877 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1878         .supports_border_color = true,
1879         .supports_interlacing = false,
1880         .supports_cursor = false,
1881         .supports_block_linear = false,
1882         .pitch_align = 8,
1883         .has_powergate = false,
1884         .broken_reset = true,
1885 };
1886
1887 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1888         .supports_border_color = true,
1889         .supports_interlacing = false,
1890         .supports_cursor = false,
1891         .supports_block_linear = false,
1892         .pitch_align = 8,
1893         .has_powergate = false,
1894         .broken_reset = false,
1895 };
1896
1897 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1898         .supports_border_color = true,
1899         .supports_interlacing = false,
1900         .supports_cursor = false,
1901         .supports_block_linear = false,
1902         .pitch_align = 64,
1903         .has_powergate = true,
1904         .broken_reset = false,
1905 };
1906
1907 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1908         .supports_border_color = false,
1909         .supports_interlacing = true,
1910         .supports_cursor = true,
1911         .supports_block_linear = true,
1912         .pitch_align = 64,
1913         .has_powergate = true,
1914         .broken_reset = false,
1915 };
1916
1917 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1918         .supports_border_color = false,
1919         .supports_interlacing = true,
1920         .supports_cursor = true,
1921         .supports_block_linear = true,
1922         .pitch_align = 64,
1923         .has_powergate = true,
1924         .broken_reset = false,
1925 };
1926
1927 static const struct of_device_id tegra_dc_of_match[] = {
1928         {
1929                 .compatible = "nvidia,tegra210-dc",
1930                 .data = &tegra210_dc_soc_info,
1931         }, {
1932                 .compatible = "nvidia,tegra124-dc",
1933                 .data = &tegra124_dc_soc_info,
1934         }, {
1935                 .compatible = "nvidia,tegra114-dc",
1936                 .data = &tegra114_dc_soc_info,
1937         }, {
1938                 .compatible = "nvidia,tegra30-dc",
1939                 .data = &tegra30_dc_soc_info,
1940         }, {
1941                 .compatible = "nvidia,tegra20-dc",
1942                 .data = &tegra20_dc_soc_info,
1943         }, {
1944                 /* sentinel */
1945         }
1946 };
1947 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1948
1949 static int tegra_dc_parse_dt(struct tegra_dc *dc)
1950 {
1951         struct device_node *np;
1952         u32 value = 0;
1953         int err;
1954
1955         err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1956         if (err < 0) {
1957                 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1958
1959                 /*
1960                  * If the nvidia,head property isn't present, try to find the
1961                  * correct head number by looking up the position of this
1962                  * display controller's node within the device tree. Assuming
1963                  * that the nodes are ordered properly in the DTS file and
1964                  * that the translation into a flattened device tree blob
1965                  * preserves that ordering this will actually yield the right
1966                  * head number.
1967                  *
1968                  * If those assumptions don't hold, this will still work for
1969                  * cases where only a single display controller is used.
1970                  */
1971                 for_each_matching_node(np, tegra_dc_of_match) {
1972                         if (np == dc->dev->of_node) {
1973                                 of_node_put(np);
1974                                 break;
1975                         }
1976
1977                         value++;
1978                 }
1979         }
1980
1981         dc->pipe = value;
1982
1983         return 0;
1984 }
1985
1986 static int tegra_dc_probe(struct platform_device *pdev)
1987 {
1988         const struct of_device_id *id;
1989         struct resource *regs;
1990         struct tegra_dc *dc;
1991         int err;
1992
1993         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1994         if (!dc)
1995                 return -ENOMEM;
1996
1997         id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1998         if (!id)
1999                 return -ENODEV;
2000
2001         spin_lock_init(&dc->lock);
2002         INIT_LIST_HEAD(&dc->list);
2003         dc->dev = &pdev->dev;
2004         dc->soc = id->data;
2005
2006         err = tegra_dc_parse_dt(dc);
2007         if (err < 0)
2008                 return err;
2009
2010         dc->clk = devm_clk_get(&pdev->dev, NULL);
2011         if (IS_ERR(dc->clk)) {
2012                 dev_err(&pdev->dev, "failed to get clock\n");
2013                 return PTR_ERR(dc->clk);
2014         }
2015
2016         dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2017         if (IS_ERR(dc->rst)) {
2018                 dev_err(&pdev->dev, "failed to get reset\n");
2019                 return PTR_ERR(dc->rst);
2020         }
2021
2022         if (!dc->soc->broken_reset)
2023                 reset_control_assert(dc->rst);
2024
2025         if (dc->soc->has_powergate) {
2026                 if (dc->pipe == 0)
2027                         dc->powergate = TEGRA_POWERGATE_DIS;
2028                 else
2029                         dc->powergate = TEGRA_POWERGATE_DISB;
2030
2031                 tegra_powergate_power_off(dc->powergate);
2032         }
2033
2034         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2035         dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2036         if (IS_ERR(dc->regs))
2037                 return PTR_ERR(dc->regs);
2038
2039         dc->irq = platform_get_irq(pdev, 0);
2040         if (dc->irq < 0) {
2041                 dev_err(&pdev->dev, "failed to get IRQ\n");
2042                 return -ENXIO;
2043         }
2044
2045         err = tegra_dc_rgb_probe(dc);
2046         if (err < 0 && err != -ENODEV) {
2047                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2048                 return err;
2049         }
2050
2051         platform_set_drvdata(pdev, dc);
2052         pm_runtime_enable(&pdev->dev);
2053
2054         INIT_LIST_HEAD(&dc->client.list);
2055         dc->client.ops = &dc_client_ops;
2056         dc->client.dev = &pdev->dev;
2057
2058         err = host1x_client_register(&dc->client);
2059         if (err < 0) {
2060                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2061                         err);
2062                 return err;
2063         }
2064
2065         return 0;
2066 }
2067
2068 static int tegra_dc_remove(struct platform_device *pdev)
2069 {
2070         struct tegra_dc *dc = platform_get_drvdata(pdev);
2071         int err;
2072
2073         err = host1x_client_unregister(&dc->client);
2074         if (err < 0) {
2075                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2076                         err);
2077                 return err;
2078         }
2079
2080         err = tegra_dc_rgb_remove(dc);
2081         if (err < 0) {
2082                 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2083                 return err;
2084         }
2085
2086         pm_runtime_disable(&pdev->dev);
2087
2088         return 0;
2089 }
2090
2091 #ifdef CONFIG_PM
2092 static int tegra_dc_suspend(struct device *dev)
2093 {
2094         struct tegra_dc *dc = dev_get_drvdata(dev);
2095         int err;
2096
2097         if (!dc->soc->broken_reset) {
2098                 err = reset_control_assert(dc->rst);
2099                 if (err < 0) {
2100                         dev_err(dev, "failed to assert reset: %d\n", err);
2101                         return err;
2102                 }
2103         }
2104
2105         if (dc->soc->has_powergate)
2106                 tegra_powergate_power_off(dc->powergate);
2107
2108         clk_disable_unprepare(dc->clk);
2109
2110         return 0;
2111 }
2112
2113 static int tegra_dc_resume(struct device *dev)
2114 {
2115         struct tegra_dc *dc = dev_get_drvdata(dev);
2116         int err;
2117
2118         if (dc->soc->has_powergate) {
2119                 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2120                                                         dc->rst);
2121                 if (err < 0) {
2122                         dev_err(dev, "failed to power partition: %d\n", err);
2123                         return err;
2124                 }
2125         } else {
2126                 err = clk_prepare_enable(dc->clk);
2127                 if (err < 0) {
2128                         dev_err(dev, "failed to enable clock: %d\n", err);
2129                         return err;
2130                 }
2131
2132                 if (!dc->soc->broken_reset) {
2133                         err = reset_control_deassert(dc->rst);
2134                         if (err < 0) {
2135                                 dev_err(dev,
2136                                         "failed to deassert reset: %d\n", err);
2137                                 return err;
2138                         }
2139                 }
2140         }
2141
2142         return 0;
2143 }
2144 #endif
2145
2146 static const struct dev_pm_ops tegra_dc_pm_ops = {
2147         SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2148 };
2149
2150 struct platform_driver tegra_dc_driver = {
2151         .driver = {
2152                 .name = "tegra-dc",
2153                 .of_match_table = tegra_dc_of_match,
2154                 .pm = &tegra_dc_pm_ops,
2155         },
2156         .probe = tegra_dc_probe,
2157         .remove = tegra_dc_remove,
2158 };