drivers/gpu/drm/rcar-du/rcar_du_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
   4  *
   5  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   6  *
   7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/mutex.h>
  12 #include <linux/sys_soc.h>
  13
  14 #include <drm/drmP.h>
  15 #include <drm/drm_atomic.h>
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_crtc.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_fb_cma_helper.h>
  20 #include <drm/drm_gem_cma_helper.h>
  21 #include <drm/drm_plane_helper.h>
  22
  23 #include "rcar_du_crtc.h"
  24 #include "rcar_du_drv.h"
  25 #include "rcar_du_kms.h"
  26 #include "rcar_du_plane.h"
  27 #include "rcar_du_regs.h"
  28 #include "rcar_du_vsp.h"
  29
  30 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  31 {
  32         struct rcar_du_device *rcdu = rcrtc->group->dev;
  33
  34         return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  35 }
  36
  37 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  38 {
  39         struct rcar_du_device *rcdu = rcrtc->group->dev;
  40
  41         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  42 }
  43
  44 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  45 {
  46         struct rcar_du_device *rcdu = rcrtc->group->dev;
  47
  48         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  49                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  50 }
  51
  52 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  53 {
  54         struct rcar_du_device *rcdu = rcrtc->group->dev;
  55
  56         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  57                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  58 }
  59
  60 void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set)
  61 {
  62         struct rcar_du_device *rcdu = rcrtc->group->dev;
  63
  64         rcrtc->dsysr = (rcrtc->dsysr & ~clr) | set;
  65         rcar_du_write(rcdu, rcrtc->mmio_offset + DSYSR, rcrtc->dsysr);
  66 }
  67
  68 /* -----------------------------------------------------------------------------
  69  * Hardware Setup
  70  */
  71
  72 struct dpll_info {
  73         unsigned int output;
  74         unsigned int fdpll;
  75         unsigned int n;
  76         unsigned int m;
  77 };
  78
  79 static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
  80                                  struct dpll_info *dpll,
  81                                  unsigned long input,
  82                                  unsigned long target)
  83 {
  84         unsigned long best_diff = (unsigned long)-1;
  85         unsigned long diff;
  86         unsigned int fdpll;
  87         unsigned int m;
  88         unsigned int n;
  89
  90         /*
  91          *   fin                                 fvco        fout       fclkout
  92          * in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
  93          *              +-> |  |                             |
  94          *              |                                    |
  95          *              +---------------- [1/N] <------------+
  96          *
  97          *      fclkout = fvco / P / FDPLL -- (1)
  98          *
  99          * fin/M = fvco/P/N
 100          *
 101          *      fvco = fin * P *  N / M -- (2)
 102          *
 103          * (1) + (2) indicates
 104          *
 105          *      fclkout = fin * N / M / FDPLL
 106          *
 107          * NOTES
 108          *      N       : (n + 1)
 109          *      M       : (m + 1)
 110          *      FDPLL   : (fdpll + 1)
 111          *      P       : 2
 112          *      2kHz < fvco < 4096MHz
 113          *
 114          * To minimize the jitter,
 115          * N : as large as possible
 116          * M : as small as possible
 117          */
 118         for (m = 0; m < 4; m++) {
 119                 for (n = 119; n > 38; n--) {
 120                         /*
 121                          * This code only runs on 64-bit architectures, the
 122                          * unsigned long type can thus be used for 64-bit
 123                          * computation. It will still compile without any
 124                          * warning on 32-bit architectures.
 125                          *
 126                          * To optimize calculations, use fout instead of fvco
 127                          * to verify the VCO frequency constraint.
 128                          */
 129                         unsigned long fout = input * (n + 1) / (m + 1);
 130
 131                         if (fout < 1000 || fout > 2048 * 1000 * 1000U)
 132                                 continue;
 133
 134                         for (fdpll = 1; fdpll < 32; fdpll++) {
 135                                 unsigned long output;
 136
 137                                 output = fout / (fdpll + 1);
 138                                 if (output >= 400 * 1000 * 1000)
 139                                         continue;
 140
 141                                 diff = abs((long)output - (long)target);
 142                                 if (best_diff > diff) {
 143                                         best_diff = diff;
 144                                         dpll->n = n;
 145                                         dpll->m = m;
 146                                         dpll->fdpll = fdpll;
 147                                         dpll->output = output;
 148                                 }
 149
 150                                 if (diff == 0)
 151                                         goto done;
 152                         }
 153                 }
 154         }
 155
 156 done:
 157         dev_dbg(rcrtc->group->dev->dev,
 158                 "output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n",
 159                  dpll->output, dpll->fdpll, dpll->n, dpll->m,
 160                  best_diff);
 161 }
 162
 163 struct du_clk_params {
 164         struct clk *clk;
 165         unsigned long rate;
 166         unsigned long diff;
 167         u32 escr;
 168 };
 169
 170 static void rcar_du_escr_divider(struct clk *clk, unsigned long target,
 171                                  u32 escr, struct du_clk_params *params)
 172 {
 173         unsigned long rate;
 174         unsigned long diff;
 175         u32 div;
 176
 177         /*
 178          * If the target rate has already been achieved perfectly we can't do
 179          * better.
 180          */
 181         if (params->diff == 0)
 182                 return;
 183
 184         /*
 185          * Compute the input clock rate and internal divisor values to obtain
 186          * the clock rate closest to the target frequency.
 187          */
 188         rate = clk_round_rate(clk, target);
 189         div = clamp(DIV_ROUND_CLOSEST(rate, target), 1UL, 64UL) - 1;
 190         diff = abs(rate / (div + 1) - target);
 191
 192         /*
 193          * Store the parameters if the resulting frequency is better than any
 194          * previously calculated value.
 195          */
 196         if (diff < params->diff) {
 197                 params->clk = clk;
 198                 params->rate = rate;
 199                 params->diff = diff;
 200                 params->escr = escr | div;
 201         }
 202 }
 203
 204 static const struct soc_device_attribute rcar_du_r8a7795_es1[] = {
 205         { .soc_id = "r8a7795", .revision = "ES1.*" },
 206         { /* sentinel */ }
 207 };
 208
 209 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 210 {
 211         const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
 212         struct rcar_du_device *rcdu = rcrtc->group->dev;
 213         unsigned long mode_clock = mode->clock * 1000;
 214         u32 dsmr;
 215         u32 escr;
 216
 217         if (rcdu->info->dpll_mask & (1 << rcrtc->index)) {
 218                 unsigned long target = mode_clock;
 219                 struct dpll_info dpll = { 0 };
 220                 unsigned long extclk;
 221                 u32 dpllcr;
 222                 u32 div = 0;
 223
 224                 /*
 225                  * DU channels that have a display PLL can't use the internal
 226                  * system clock, and have no internal clock divider.
 227                  */
 228
 229                 /*
 230                  * The H3 ES1.x exhibits dot clock duty cycle stability issues.
 231                  * We can work around them by configuring the DPLL to twice the
 232                  * desired frequency, coupled with a /2 post-divider. Restrict
 233                  * the workaround to H3 ES1.x as ES2.0 and all other SoCs have
 234                  * no post-divider when a display PLL is present (as shown by
 235                  * the workaround breaking HDMI output on M3-W during testing).
 236                  */
 237                 if (soc_device_match(rcar_du_r8a7795_es1)) {
 238                         target *= 2;
 239                         div = 1;
 240                 }
 241
 242                 extclk = clk_get_rate(rcrtc->extclock);
 243                 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);
 244
 245                 dpllcr = DPLLCR_CODE | DPLLCR_CLKE
 246                        | DPLLCR_FDPLL(dpll.fdpll)
 247                        | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)
 248                        | DPLLCR_STBY;
 249
 250                 if (rcrtc->index == 1)
 251                         dpllcr |= DPLLCR_PLCS1
 252                                |  DPLLCR_INCS_DOTCLKIN1;
 253                 else
 254                         dpllcr |= DPLLCR_PLCS0
 255                                |  DPLLCR_INCS_DOTCLKIN0;
 256
 257                 rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr);
 258
 259                 escr = ESCR_DCLKSEL_DCLKIN | div;
 260         } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) {
 261                 /*
 262                  * Use the LVDS PLL output as the dot clock when outputting to
 263                  * the LVDS encoder on an SoC that supports this clock routing
 264                  * option. We use the clock directly in that case, without any
 265                  * additional divider.
 266                  */
 267                 escr = ESCR_DCLKSEL_DCLKIN;
 268         } else {
 269                 struct du_clk_params params = { .diff = (unsigned long)-1 };
 270
 271                 rcar_du_escr_divider(rcrtc->clock, mode_clock,
 272                                      ESCR_DCLKSEL_CLKS, &params);
 273                 if (rcrtc->extclock)
 274                         rcar_du_escr_divider(rcrtc->extclock, mode_clock,
 275                                              ESCR_DCLKSEL_DCLKIN, &params);
 276
 277                 dev_dbg(rcrtc->group->dev->dev, "mode clock %lu %s rate %lu\n",
 278                         mode_clock, params.clk == rcrtc->clock ? "cpg" : "ext",
 279                         params.rate);
 280
 281                 clk_set_rate(params.clk, params.rate);
 282                 escr = params.escr;
 283         }
 284
 285         dev_dbg(rcrtc->group->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
 286
 287         rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
 288         rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
 289
 290         /* Signal polarities */
 291         dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
 292              | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
 293              | ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? DSMR_ODEV : 0)
 294              | DSMR_DIPM_DISP | DSMR_CSPM;
 295         rcar_du_crtc_write(rcrtc, DSMR, dsmr);
 296
 297         /* Display timings */
 298         rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
 299         rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
 300                                         mode->hdisplay - 19);
 301         rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
 302                                         mode->hsync_start - 1);
 303         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 304
 305         rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
 306                                         mode->crtc_vsync_end - 2);
 307         rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
 308                                         mode->crtc_vsync_end +
 309                                         mode->crtc_vdisplay - 2);
 310         rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
 311                                         mode->crtc_vsync_end +
 312                                         mode->crtc_vsync_start - 1);
 313         rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
 314
 315         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start - 1);
 316         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 317 }
 318
 319 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
 320                                enum rcar_du_output output)
 321 {
 322         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 323         struct rcar_du_device *rcdu = rcrtc->group->dev;
 324
 325         /*
 326          * Store the route from the CRTC output to the DU output. The DU will be
 327          * configured when starting the CRTC.
 328          */
 329         rcrtc->outputs |= BIT(output);
 330
 331         /*
 332          * Store RGB routing to DPAD0, the hardware will be configured when
 333          * starting the CRTC.
 334          */
 335         if (output == RCAR_DU_OUTPUT_DPAD0)
 336                 rcdu->dpad0_source = rcrtc->index;
 337 }
 338
 339 static unsigned int plane_zpos(struct rcar_du_plane *plane)
 340 {
 341         return plane->plane.state->normalized_zpos;
 342 }
 343
 344 static const struct rcar_du_format_info *
 345 plane_format(struct rcar_du_plane *plane)
 346 {
 347         return to_rcar_plane_state(plane->plane.state)->format;
 348 }
 349
 350 static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
 351 {
 352         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
 353         struct rcar_du_device *rcdu = rcrtc->group->dev;
 354         unsigned int num_planes = 0;
 355         unsigned int dptsr_planes;
 356         unsigned int hwplanes = 0;
 357         unsigned int prio = 0;
 358         unsigned int i;
 359         u32 dspr = 0;
 360
 361         for (i = 0; i < rcrtc->group->num_planes; ++i) {
 362                 struct rcar_du_plane *plane = &rcrtc->group->planes[i];
 363                 unsigned int j;
 364
 365                 if (plane->plane.state->crtc != &rcrtc->crtc ||
 366                     !plane->plane.state->visible)
 367                         continue;
 368
 369                 /* Insert the plane in the sorted planes array. */
 370                 for (j = num_planes++; j > 0; --j) {
 371                         if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
 372                                 break;
 373                         planes[j] = planes[j-1];
 374                 }
 375
 376                 planes[j] = plane;
 377                 prio += plane_format(plane)->planes * 4;
 378         }
 379
 380         for (i = 0; i < num_planes; ++i) {
 381                 struct rcar_du_plane *plane = planes[i];
 382                 struct drm_plane_state *state = plane->plane.state;
 383                 unsigned int index = to_rcar_plane_state(state)->hwindex;
 384
 385                 prio -= 4;
 386                 dspr |= (index + 1) << prio;
 387                 hwplanes |= 1 << index;
 388
 389                 if (plane_format(plane)->planes == 2) {
 390                         index = (index + 1) % 8;
 391
 392                         prio -= 4;
 393                         dspr |= (index + 1) << prio;
 394                         hwplanes |= 1 << index;
 395                 }
 396         }
 397
 398         /* If VSP+DU integration is enabled the plane assignment is fixed. */
 399         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
 400                 if (rcdu->info->gen < 3) {
 401                         dspr = (rcrtc->index % 2) + 1;
 402                         hwplanes = 1 << (rcrtc->index % 2);
 403                 } else {
 404                         dspr = (rcrtc->index % 2) ? 3 : 1;
 405                         hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
 406                 }
 407         }
 408
 409         /*
 410          * Update the planes to display timing and dot clock generator
 411          * associations.
 412          *
 413          * Updating the DPTSR register requires restarting the CRTC group,
 414          * resulting in visible flicker. To mitigate the issue only update the
 415          * association if needed by enabled planes. Planes being disabled will
 416          * keep their current association.
 417          */
 418         mutex_lock(&rcrtc->group->lock);
 419
 420         dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
 421                      : rcrtc->group->dptsr_planes & ~hwplanes;
 422
 423         if (dptsr_planes != rcrtc->group->dptsr_planes) {
 424                 rcar_du_group_write(rcrtc->group, DPTSR,
 425                                     (dptsr_planes << 16) | dptsr_planes);
 426                 rcrtc->group->dptsr_planes = dptsr_planes;
 427
 428                 if (rcrtc->group->used_crtcs)
 429                         rcar_du_group_restart(rcrtc->group);
 430         }
 431
 432         /* Restart the group if plane sources have changed. */
 433         if (rcrtc->group->need_restart)
 434                 rcar_du_group_restart(rcrtc->group);
 435
 436         mutex_unlock(&rcrtc->group->lock);
 437
 438         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
 439                             dspr);
 440 }
 441
 442 /* -----------------------------------------------------------------------------
 443  * Page Flip
 444  */
 445
 446 void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
 447 {
 448         struct drm_pending_vblank_event *event;
 449         struct drm_device *dev = rcrtc->crtc.dev;
 450         unsigned long flags;
 451
 452         spin_lock_irqsave(&dev->event_lock, flags);
 453         event = rcrtc->event;
 454         rcrtc->event = NULL;
 455         spin_unlock_irqrestore(&dev->event_lock, flags);
 456
 457         if (event == NULL)
 458                 return;
 459
 460         spin_lock_irqsave(&dev->event_lock, flags);
 461         drm_crtc_send_vblank_event(&rcrtc->crtc, event);
 462         wake_up(&rcrtc->flip_wait);
 463         spin_unlock_irqrestore(&dev->event_lock, flags);
 464
 465         drm_crtc_vblank_put(&rcrtc->crtc);
 466 }
 467
 468 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
 469 {
 470         struct drm_device *dev = rcrtc->crtc.dev;
 471         unsigned long flags;
 472         bool pending;
 473
 474         spin_lock_irqsave(&dev->event_lock, flags);
 475         pending = rcrtc->event != NULL;
 476         spin_unlock_irqrestore(&dev->event_lock, flags);
 477
 478         return pending;
 479 }
 480
 481 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
 482 {
 483         struct rcar_du_device *rcdu = rcrtc->group->dev;
 484
 485         if (wait_event_timeout(rcrtc->flip_wait,
 486                                !rcar_du_crtc_page_flip_pending(rcrtc),
 487                                msecs_to_jiffies(50)))
 488                 return;
 489
 490         dev_warn(rcdu->dev, "page flip timeout\n");
 491
 492         rcar_du_crtc_finish_page_flip(rcrtc);
 493 }
 494
 495 /* -----------------------------------------------------------------------------
 496  * Start/Stop and Suspend/Resume
 497  */
 498
 499 static void rcar_du_crtc_setup(struct rcar_du_crtc *rcrtc)
 500 {
 501         /* Set display off and background to black */
 502         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
 503         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
 504
 505         /* Configure display timings and output routing */
 506         rcar_du_crtc_set_display_timing(rcrtc);
 507         rcar_du_group_set_routing(rcrtc->group);
 508
 509         /* Start with all planes disabled. */
 510         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
 511
 512         /* Enable the VSP compositor. */
 513         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 514                 rcar_du_vsp_enable(rcrtc);
 515
 516         /* Turn vertical blanking interrupt reporting on. */
 517         drm_crtc_vblank_on(&rcrtc->crtc);
 518 }
 519
 520 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
 521 {
 522         int ret;
 523
 524         /*
 525          * Guard against double-get, as the function is called from both the
 526          * .atomic_enable() and .atomic_begin() handlers.
 527          */
 528         if (rcrtc->initialized)
 529                 return 0;
 530
 531         ret = clk_prepare_enable(rcrtc->clock);
 532         if (ret < 0)
 533                 return ret;
 534
 535         ret = clk_prepare_enable(rcrtc->extclock);
 536         if (ret < 0)
 537                 goto error_clock;
 538
 539         ret = rcar_du_group_get(rcrtc->group);
 540         if (ret < 0)
 541                 goto error_group;
 542
 543         rcar_du_crtc_setup(rcrtc);
 544         rcrtc->initialized = true;
 545
 546         return 0;
 547
 548 error_group:
 549         clk_disable_unprepare(rcrtc->extclock);
 550 error_clock:
 551         clk_disable_unprepare(rcrtc->clock);
 552         return ret;
 553 }
 554
 555 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
 556 {
 557         rcar_du_group_put(rcrtc->group);
 558
 559         clk_disable_unprepare(rcrtc->extclock);
 560         clk_disable_unprepare(rcrtc->clock);
 561
 562         rcrtc->initialized = false;
 563 }
 564
 565 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 566 {
 567         bool interlaced;
 568
 569         /*
 570          * Select master sync mode. This enables display operation in master
 571          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 572          * actively driven).
 573          */
 574         interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
 575         rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
 576                                    (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
 577                                    DSYSR_TVM_MASTER);
 578
 579         rcar_du_group_start_stop(rcrtc->group, true);
 580 }
 581
 582 static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
 583 {
 584         struct rcar_du_device *rcdu = rcrtc->group->dev;
 585         struct drm_crtc *crtc = &rcrtc->crtc;
 586         u32 status;
 587
 588         /* Make sure vblank interrupts are enabled. */
 589         drm_crtc_vblank_get(crtc);
 590
 591         /*
 592          * Disable planes and calculate how many vertical blanking interrupts we
 593          * have to wait for. If a vertical blanking interrupt has been triggered
 594          * but not processed yet, we don't know whether it occurred before or
 595          * after the planes got disabled. We thus have to wait for two vblank
 596          * interrupts in that case.
 597          */
 598         spin_lock_irq(&rcrtc->vblank_lock);
 599         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
 600         status = rcar_du_crtc_read(rcrtc, DSSR);
 601         rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1;
 602         spin_unlock_irq(&rcrtc->vblank_lock);
 603
 604         if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
 605                                 msecs_to_jiffies(100)))
 606                 dev_warn(rcdu->dev, "vertical blanking timeout\n");
 607
 608         drm_crtc_vblank_put(crtc);
 609 }
 610
 611 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
 612 {
 613         struct drm_crtc *crtc = &rcrtc->crtc;
 614
 615         /*
 616          * Disable all planes and wait for the change to take effect. This is
 617          * required as the plane enable registers are updated on vblank, and no
 618          * vblank will occur once the CRTC is stopped. Disabling planes when
 619          * starting the CRTC thus wouldn't be enough as it would start scanning
 620          * out immediately from old frame buffers until the next vblank.
 621          *
 622          * This increases the CRTC stop delay, especially when multiple CRTCs
 623          * are stopped in one operation as we now wait for one vblank per CRTC.
 624          * Whether this can be improved needs to be researched.
 625          */
 626         rcar_du_crtc_disable_planes(rcrtc);
 627
 628         /*
 629          * Disable vertical blanking interrupt reporting. We first need to wait
 630          * for page flip completion before stopping the CRTC as userspace
 631          * expects page flips to eventually complete.
 632          */
 633         rcar_du_crtc_wait_page_flip(rcrtc);
 634         drm_crtc_vblank_off(crtc);
 635
 636         /* Disable the VSP compositor. */
 637         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 638                 rcar_du_vsp_disable(rcrtc);
 639
 640         /*
 641          * Select switch sync mode. This stops display operation and configures
 642          * the HSYNC and VSYNC signals as inputs.
 643          *
 644          * TODO: Find another way to stop the display for DUs that don't support
 645          * TVM sync.
 646          */
 647         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_TVM_SYNC))
 648                 rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK,
 649                                            DSYSR_TVM_SWITCH);
 650
 651         rcar_du_group_start_stop(rcrtc->group, false);
 652 }
 653
 654 /* -----------------------------------------------------------------------------
 655  * CRTC Functions
 656  */
 657
 658 static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
 659                                        struct drm_crtc_state *old_state)
 660 {
 661         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 662
 663         rcar_du_crtc_get(rcrtc);
 664         rcar_du_crtc_start(rcrtc);
 665 }
 666
 667 static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,
 668                                         struct drm_crtc_state *old_state)
 669 {
 670         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 671
 672         rcar_du_crtc_stop(rcrtc);
 673         rcar_du_crtc_put(rcrtc);
 674
 675         spin_lock_irq(&crtc->dev->event_lock);
 676         if (crtc->state->event) {
 677                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 678                 crtc->state->event = NULL;
 679         }
 680         spin_unlock_irq(&crtc->dev->event_lock);
 681
 682         rcrtc->outputs = 0;
 683 }
 684
 685 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
 686                                       struct drm_crtc_state *old_crtc_state)
 687 {
 688         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 689
 690         WARN_ON(!crtc->state->enable);
 691
 692         /*
 693          * If a mode set is in progress we can be called with the CRTC disabled.
 694          * We thus need to first get and setup the CRTC in order to configure
 695          * planes. We must *not* put the CRTC in .atomic_flush(), as it must be
 696          * kept awake until the .atomic_enable() call that will follow. The get
 697          * operation in .atomic_enable() will in that case be a no-op, and the
 698          * CRTC will be put later in .atomic_disable().
 699          *
 700          * If a mode set is not in progress the CRTC is enabled, and the
 701          * following get call will be a no-op. There is thus no need to balance
 702          * it in .atomic_flush() either.
 703          */
 704         rcar_du_crtc_get(rcrtc);
 705
 706         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 707                 rcar_du_vsp_atomic_begin(rcrtc);
 708 }
 709
 710 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
 711                                       struct drm_crtc_state *old_crtc_state)
 712 {
 713         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 714         struct drm_device *dev = rcrtc->crtc.dev;
 715         unsigned long flags;
 716
 717         rcar_du_crtc_update_planes(rcrtc);
 718
 719         if (crtc->state->event) {
 720                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 721
 722                 spin_lock_irqsave(&dev->event_lock, flags);
 723                 rcrtc->event = crtc->state->event;
 724                 crtc->state->event = NULL;
 725                 spin_unlock_irqrestore(&dev->event_lock, flags);
 726         }
 727
 728         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 729                 rcar_du_vsp_atomic_flush(rcrtc);
 730 }
 731
 732 enum drm_mode_status rcar_du_crtc_mode_valid(struct drm_crtc *crtc,
 733                                    const struct drm_display_mode *mode)
 734 {
 735         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 736         struct rcar_du_device *rcdu = rcrtc->group->dev;
 737         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 738         unsigned int vbp;
 739
 740         if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))
 741                 return MODE_NO_INTERLACE;
 742
 743         /*
 744          * The hardware requires a minimum combined horizontal sync and back
 745          * porch of 20 pixels and a minimum vertical back porch of 3 lines.
 746          */
 747         if (mode->htotal - mode->hsync_start < 20)
 748                 return MODE_HBLANK_NARROW;
 749
 750         vbp = (mode->vtotal - mode->vsync_end) / (interlaced ? 2 : 1);
 751         if (vbp < 3)
 752                 return MODE_VBLANK_NARROW;
 753
 754         return MODE_OK;
 755 }
 756
 757 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
 758         .atomic_begin = rcar_du_crtc_atomic_begin,
 759         .atomic_flush = rcar_du_crtc_atomic_flush,
 760         .atomic_enable = rcar_du_crtc_atomic_enable,
 761         .atomic_disable = rcar_du_crtc_atomic_disable,
 762         .mode_valid = rcar_du_crtc_mode_valid,
 763 };
 764
 765 static void rcar_du_crtc_crc_init(struct rcar_du_crtc *rcrtc)
 766 {
 767         struct rcar_du_device *rcdu = rcrtc->group->dev;
 768         const char **sources;
 769         unsigned int count;
 770         int i = -1;
 771
 772         /* CRC available only on Gen3 HW. */
 773         if (rcdu->info->gen < 3)
 774                 return;
 775
 776         /* Reserve 1 for "auto" source. */
 777         count = rcrtc->vsp->num_planes + 1;
 778
 779         sources = kmalloc_array(count, sizeof(*sources), GFP_KERNEL);
 780         if (!sources)
 781                 return;
 782
 783         sources[0] = kstrdup("auto", GFP_KERNEL);
 784         if (!sources[0])
 785                 goto error;
 786
 787         for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
 788                 struct drm_plane *plane = &rcrtc->vsp->planes[i].plane;
 789                 char name[16];
 790
 791                 sprintf(name, "plane%u", plane->base.id);
 792                 sources[i + 1] = kstrdup(name, GFP_KERNEL);
 793                 if (!sources[i + 1])
 794                         goto error;
 795         }
 796
 797         rcrtc->sources = sources;
 798         rcrtc->sources_count = count;
 799         return;
 800
 801 error:
 802         while (i >= 0) {
 803                 kfree(sources[i]);
 804                 i--;
 805         }
 806         kfree(sources);
 807 }
 808
 809 static void rcar_du_crtc_crc_cleanup(struct rcar_du_crtc *rcrtc)
 810 {
 811         unsigned int i;
 812
 813         if (!rcrtc->sources)
 814                 return;
 815
 816         for (i = 0; i < rcrtc->sources_count; i++)
 817                 kfree(rcrtc->sources[i]);
 818         kfree(rcrtc->sources);
 819
 820         rcrtc->sources = NULL;
 821         rcrtc->sources_count = 0;
 822 }
 823
 824 static struct drm_crtc_state *
 825 rcar_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
 826 {
 827         struct rcar_du_crtc_state *state;
 828         struct rcar_du_crtc_state *copy;
 829
 830         if (WARN_ON(!crtc->state))
 831                 return NULL;
 832
 833         state = to_rcar_crtc_state(crtc->state);
 834         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
 835         if (copy == NULL)
 836                 return NULL;
 837
 838         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->state);
 839
 840         return &copy->state;
 841 }
 842
 843 static void rcar_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
 844                                               struct drm_crtc_state *state)
 845 {
 846         __drm_atomic_helper_crtc_destroy_state(state);
 847         kfree(to_rcar_crtc_state(state));
 848 }
 849
 850 static void rcar_du_crtc_cleanup(struct drm_crtc *crtc)
 851 {
 852         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 853
 854         rcar_du_crtc_crc_cleanup(rcrtc);
 855
 856         return drm_crtc_cleanup(crtc);
 857 }
 858
 859 static void rcar_du_crtc_reset(struct drm_crtc *crtc)
 860 {
 861         struct rcar_du_crtc_state *state;
 862
 863         if (crtc->state) {
 864                 rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
 865                 crtc->state = NULL;
 866         }
 867
 868         state = kzalloc(sizeof(*state), GFP_KERNEL);
 869         if (state == NULL)
 870                 return;
 871
 872         state->crc.source = VSP1_DU_CRC_NONE;
 873         state->crc.index = 0;
 874
 875         crtc->state = &state->state;
 876         crtc->state->crtc = crtc;
 877 }
 878
 879 static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
 880 {
 881         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 882
 883         rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
 884         rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
 885         rcrtc->vblank_enable = true;
 886
 887         return 0;
 888 }
 889
 890 static void rcar_du_crtc_disable_vblank(struct drm_crtc *crtc)
 891 {
 892         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 893
 894         rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
 895         rcrtc->vblank_enable = false;
 896 }
 897
 898 static int rcar_du_crtc_parse_crc_source(struct rcar_du_crtc *rcrtc,
 899                                          const char *source_name,
 900                                          enum vsp1_du_crc_source *source)
 901 {
 902         unsigned int index;
 903         int ret;
 904
 905         /*
 906          * Parse the source name. Supported values are "plane%u" to compute the
 907          * CRC on an input plane (%u is the plane ID), and "auto" to compute the
 908          * CRC on the composer (VSP) output.
 909          */
 910
 911         if (!source_name) {
 912                 *source = VSP1_DU_CRC_NONE;
 913                 return 0;
 914         } else if (!strcmp(source_name, "auto")) {
 915                 *source = VSP1_DU_CRC_OUTPUT;
 916                 return 0;
 917         } else if (strstarts(source_name, "plane")) {
 918                 unsigned int i;
 919
 920                 *source = VSP1_DU_CRC_PLANE;
 921
 922                 ret = kstrtouint(source_name + strlen("plane"), 10, &index);
 923                 if (ret < 0)
 924                         return ret;
 925
 926                 for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
 927                         if (index == rcrtc->vsp->planes[i].plane.base.id)
 928                                 return i;
 929                 }
 930         }
 931
 932         return -EINVAL;
 933 }
 934
 935 static int rcar_du_crtc_verify_crc_source(struct drm_crtc *crtc,
 936                                           const char *source_name,
 937                                           size_t *values_cnt)
 938 {
 939         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 940         enum vsp1_du_crc_source source;
 941
 942         if (rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source) < 0) {
 943                 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
 944                 return -EINVAL;
 945         }
 946
 947         *values_cnt = 1;
 948         return 0;
 949 }
 950
 951 const char *const *rcar_du_crtc_get_crc_sources(struct drm_crtc *crtc,
 952                                                 size_t *count)
 953 {
 954         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 955
 956         *count = rcrtc->sources_count;
 957         return rcrtc->sources;
 958 }
 959
 960 static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc,
 961                                        const char *source_name)
 962 {
 963         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 964         struct drm_modeset_acquire_ctx ctx;
 965         struct drm_crtc_state *crtc_state;
 966         struct drm_atomic_state *state;
 967         enum vsp1_du_crc_source source;
 968         unsigned int index;
 969         int ret;
 970
 971         ret = rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source);
 972         if (ret < 0)
 973                 return ret;
 974
 975         index = ret;
 976
 977         /* Perform an atomic commit to set the CRC source. */
 978         drm_modeset_acquire_init(&ctx, 0);
 979
 980         state = drm_atomic_state_alloc(crtc->dev);
 981         if (!state) {
 982                 ret = -ENOMEM;
 983                 goto unlock;
 984         }
 985
 986         state->acquire_ctx = &ctx;
 987
 988 retry:
 989         crtc_state = drm_atomic_get_crtc_state(state, crtc);
 990         if (!IS_ERR(crtc_state)) {
 991                 struct rcar_du_crtc_state *rcrtc_state;
 992
 993                 rcrtc_state = to_rcar_crtc_state(crtc_state);
 994                 rcrtc_state->crc.source = source;
 995                 rcrtc_state->crc.index = index;
 996
 997                 ret = drm_atomic_commit(state);
 998         } else {
 999                 ret = PTR_ERR(crtc_state);
1000         }
1001
1002         if (ret == -EDEADLK) {
1003                 drm_atomic_state_clear(state);
1004                 drm_modeset_backoff(&ctx);
1005                 goto retry;
1006         }
1007
1008         drm_atomic_state_put(state);
1009
1010 unlock:
1011         drm_modeset_drop_locks(&ctx);
1012         drm_modeset_acquire_fini(&ctx);
1013
1014         return ret;
1015 }
1016
1017 static const struct drm_crtc_funcs crtc_funcs_gen2 = {
1018         .reset = rcar_du_crtc_reset,
1019         .destroy = drm_crtc_cleanup,
1020         .set_config = drm_atomic_helper_set_config,
1021         .page_flip = drm_atomic_helper_page_flip,
1022         .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1023         .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1024         .enable_vblank = rcar_du_crtc_enable_vblank,
1025         .disable_vblank = rcar_du_crtc_disable_vblank,
1026 };
1027
1028 static const struct drm_crtc_funcs crtc_funcs_gen3 = {
1029         .reset = rcar_du_crtc_reset,
1030         .destroy = rcar_du_crtc_cleanup,
1031         .set_config = drm_atomic_helper_set_config,
1032         .page_flip = drm_atomic_helper_page_flip,
1033         .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1034         .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1035         .enable_vblank = rcar_du_crtc_enable_vblank,
1036         .disable_vblank = rcar_du_crtc_disable_vblank,
1037         .set_crc_source = rcar_du_crtc_set_crc_source,
1038         .verify_crc_source = rcar_du_crtc_verify_crc_source,
1039         .get_crc_sources = rcar_du_crtc_get_crc_sources,
1040 };
1041
1042 /* -----------------------------------------------------------------------------
1043  * Interrupt Handling
1044  */
1045
1046 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
1047 {
1048         struct rcar_du_crtc *rcrtc = arg;
1049         struct rcar_du_device *rcdu = rcrtc->group->dev;
1050         irqreturn_t ret = IRQ_NONE;
1051         u32 status;
1052
1053         spin_lock(&rcrtc->vblank_lock);
1054
1055         status = rcar_du_crtc_read(rcrtc, DSSR);
1056         rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
1057
1058         if (status & DSSR_VBK) {
1059                 /*
1060                  * Wake up the vblank wait if the counter reaches 0. This must
1061                  * be protected by the vblank_lock to avoid races in
1062                  * rcar_du_crtc_disable_planes().
1063                  */
1064                 if (rcrtc->vblank_count) {
1065                         if (--rcrtc->vblank_count == 0)
1066                                 wake_up(&rcrtc->vblank_wait);
1067                 }
1068         }
1069
1070         spin_unlock(&rcrtc->vblank_lock);
1071
1072         if (status & DSSR_VBK) {
1073                 if (rcdu->info->gen < 3) {
1074                         drm_crtc_handle_vblank(&rcrtc->crtc);
1075                         rcar_du_crtc_finish_page_flip(rcrtc);
1076                 }
1077
1078                 ret = IRQ_HANDLED;
1079         }
1080
1081         return ret;
1082 }
1083
1084 /* -----------------------------------------------------------------------------
1085  * Initialization
1086  */
1087
1088 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
1089                         unsigned int hwindex)
1090 {
1091         static const unsigned int mmio_offsets[] = {
1092                 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
1093         };
1094
1095         struct rcar_du_device *rcdu = rgrp->dev;
1096         struct platform_device *pdev = to_platform_device(rcdu->dev);
1097         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
1098         struct drm_crtc *crtc = &rcrtc->crtc;
1099         struct drm_plane *primary;
1100         unsigned int irqflags;
1101         struct clk *clk;
1102         char clk_name[9];
1103         char *name;
1104         int irq;
1105         int ret;
1106
1107         /* Get the CRTC clock and the optional external clock. */
1108         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1109                 sprintf(clk_name, "du.%u", hwindex);
1110                 name = clk_name;
1111         } else {
1112                 name = NULL;
1113         }
1114
1115         rcrtc->clock = devm_clk_get(rcdu->dev, name);
1116         if (IS_ERR(rcrtc->clock)) {
1117                 dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex);
1118                 return PTR_ERR(rcrtc->clock);
1119         }
1120
1121         sprintf(clk_name, "dclkin.%u", hwindex);
1122         clk = devm_clk_get(rcdu->dev, clk_name);
1123         if (!IS_ERR(clk)) {
1124                 rcrtc->extclock = clk;
1125         } else if (PTR_ERR(clk) == -EPROBE_DEFER) {
1126                 return -EPROBE_DEFER;
1127         } else if (rcdu->info->dpll_mask & BIT(hwindex)) {
1128                 /*
1129                  * DU channels that have a display PLL can't use the internal
1130                  * system clock and thus require an external clock.
1131                  */
1132                 ret = PTR_ERR(clk);
1133                 dev_err(rcdu->dev, "can't get dclkin.%u: %d\n", hwindex, ret);
1134                 return ret;
1135         }
1136
1137         init_waitqueue_head(&rcrtc->flip_wait);
1138         init_waitqueue_head(&rcrtc->vblank_wait);
1139         spin_lock_init(&rcrtc->vblank_lock);
1140
1141         rcrtc->group = rgrp;
1142         rcrtc->mmio_offset = mmio_offsets[hwindex];
1143         rcrtc->index = hwindex;
1144         rcrtc->dsysr = (rcrtc->index % 2 ? 0 : DSYSR_DRES) | DSYSR_TVM_TVSYNC;
1145
1146         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
1147                 primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
1148         else
1149                 primary = &rgrp->planes[swindex % 2].plane;
1150
1151         ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary, NULL,
1152                                         rcdu->info->gen <= 2 ?
1153                                         &crtc_funcs_gen2 : &crtc_funcs_gen3,
1154                                         NULL);
1155         if (ret < 0)
1156                 return ret;
1157
1158         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
1159
1160         /* Start with vertical blanking interrupt reporting disabled. */
1161         drm_crtc_vblank_off(crtc);
1162
1163         /* Register the interrupt handler. */
1164         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1165                 /* The IRQ's are associated with the CRTC (sw)index. */
1166                 irq = platform_get_irq(pdev, swindex);
1167                 irqflags = 0;
1168         } else {
1169                 irq = platform_get_irq(pdev, 0);
1170                 irqflags = IRQF_SHARED;
1171         }
1172
1173         if (irq < 0) {
1174                 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", swindex);
1175                 return irq;
1176         }
1177
1178         ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
1179                                dev_name(rcdu->dev), rcrtc);
1180         if (ret < 0) {
1181                 dev_err(rcdu->dev,
1182                         "failed to register IRQ for CRTC %u\n", swindex);
1183                 return ret;
1184         }
1185
1186         rcar_du_crtc_crc_init(rcrtc);
1187
1188         return 0;
1189 }