drivers/gpu/drm/radeon/rs690.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "atom.h"
  32 #include "rs690d.h"
  33
  34 int rs690_mc_wait_for_idle(struct radeon_device *rdev)
  35 {
  36         unsigned i;
  37         uint32_t tmp;
  38
  39         for (i = 0; i < rdev->usec_timeout; i++) {
  40                 /* read MC_STATUS */
  41                 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
  42                 if (G_000090_MC_SYSTEM_IDLE(tmp))
  43                         return 0;
  44                 udelay(1);
  45         }
  46         return -1;
  47 }
  48
  49 static void rs690_gpu_init(struct radeon_device *rdev)
  50 {
  51         /* FIXME: is this correct ? */
  52         r420_pipes_init(rdev);
  53         if (rs690_mc_wait_for_idle(rdev)) {
  54                 printk(KERN_WARNING "Failed to wait MC idle while "
  55                        "programming pipes. Bad things might happen.\n");
  56         }
  57 }
  58
  59 union igp_info {
  60         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
  61         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
  62 };
  63
  64 void rs690_pm_info(struct radeon_device *rdev)
  65 {
  66         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
  67         union igp_info *info;
  68         uint16_t data_offset;
  69         uint8_t frev, crev;
  70         fixed20_12 tmp;
  71
  72         if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
  73                                    &frev, &crev, &data_offset)) {
  74                 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
  75
  76                 /* Get various system informations from bios */
  77                 switch (crev) {
  78                 case 1:
  79                         tmp.full = dfixed_const(100);
  80                         rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
  81                         rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  82                         if (le16_to_cpu(info->info.usK8MemoryClock))
  83                                 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
  84                         else if (rdev->clock.default_mclk) {
  85                                 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
  86                                 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
  87                         } else
  88                                 rdev->pm.igp_system_mclk.full = dfixed_const(400);
  89                         rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
  90                         rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
  91                         break;
  92                 case 2:
  93                         tmp.full = dfixed_const(100);
  94                         rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
  95                         rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  96                         if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
  97                                 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
  98                         else if (rdev->clock.default_mclk)
  99                                 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
 100                         else
 101                                 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
 102                         rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
 103                         rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
 104                         rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
 105                         rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
 106                         break;
 107                 default:
 108                         /* We assume the slower possible clock ie worst case */
 109                         rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
 110                         rdev->pm.igp_system_mclk.full = dfixed_const(200);
 111                         rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
 112                         rdev->pm.igp_ht_link_width.full = dfixed_const(8);
 113                         DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 114                         break;
 115                 }
 116         } else {
 117                 /* We assume the slower possible clock ie worst case */
 118                 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
 119                 rdev->pm.igp_system_mclk.full = dfixed_const(200);
 120                 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
 121                 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
 122                 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 123         }
 124         /* Compute various bandwidth */
 125         /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4  */
 126         tmp.full = dfixed_const(4);
 127         rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
 128         /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
 129          *              = ht_clk * ht_width / 5
 130          */
 131         tmp.full = dfixed_const(5);
 132         rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
 133                                                 rdev->pm.igp_ht_link_width);
 134         rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
 135         if (tmp.full < rdev->pm.max_bandwidth.full) {
 136                 /* HT link is a limiting factor */
 137                 rdev->pm.max_bandwidth.full = tmp.full;
 138         }
 139         /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
 140          *                    = (sideport_clk * 14) / 10
 141          */
 142         tmp.full = dfixed_const(14);
 143         rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
 144         tmp.full = dfixed_const(10);
 145         rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
 146 }
 147
 148 static void rs690_mc_init(struct radeon_device *rdev)
 149 {
 150         u64 base;
 151         uint32_t h_addr, l_addr;
 152         unsigned long long k8_addr;
 153
 154         rs400_gart_adjust_size(rdev);
 155         rdev->mc.vram_is_ddr = true;
 156         rdev->mc.vram_width = 128;
 157         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 158         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 159         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
 160         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
 161         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 162         base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
 163         base = G_000100_MC_FB_START(base) << 16;
 164         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 165
 166         /* Use K8 direct mapping for fast fb access. */
 167         rdev->fastfb_working = false;
 168         h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
 169         l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
 170         k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
 171 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
 172         if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
 173 #endif
 174         {
 175                 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
 176                  * memory is present.
 177                  */
 178                 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
 179                         DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
 180                                         (unsigned long long)rdev->mc.aper_base, k8_addr);
 181                         rdev->mc.aper_base = (resource_size_t)k8_addr;
 182                         rdev->fastfb_working = true;
 183                 }
 184         }
 185
 186         rs690_pm_info(rdev);
 187         radeon_vram_location(rdev, &rdev->mc, base);
 188         rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
 189         radeon_gtt_location(rdev, &rdev->mc);
 190         radeon_update_bandwidth_info(rdev);
 191 }
 192
 193 void rs690_line_buffer_adjust(struct radeon_device *rdev,
 194                               struct drm_display_mode *mode1,
 195                               struct drm_display_mode *mode2)
 196 {
 197         u32 tmp;
 198
 199         /*
 200          * Line Buffer Setup
 201          * There is a single line buffer shared by both display controllers.
 202          * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 203          * the display controllers.  The paritioning can either be done
 204          * manually or via one of four preset allocations specified in bits 1:0:
 205          *  0 - line buffer is divided in half and shared between crtc
 206          *  1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
 207          *  2 - D1 gets the whole buffer
 208          *  3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
 209          * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
 210          * allocation mode. In manual allocation mode, D1 always starts at 0,
 211          * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
 212          */
 213         tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
 214         tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
 215         /* auto */
 216         if (mode1 && mode2) {
 217                 if (mode1->hdisplay > mode2->hdisplay) {
 218                         if (mode1->hdisplay > 2560)
 219                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
 220                         else
 221                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 222                 } else if (mode2->hdisplay > mode1->hdisplay) {
 223                         if (mode2->hdisplay > 2560)
 224                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 225                         else
 226                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 227                 } else
 228                         tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 229         } else if (mode1) {
 230                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
 231         } else if (mode2) {
 232                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 233         }
 234         WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
 235 }
 236
 237 struct rs690_watermark {
 238         u32        lb_request_fifo_depth;
 239         fixed20_12 num_line_pair;
 240         fixed20_12 estimated_width;
 241         fixed20_12 worst_case_latency;
 242         fixed20_12 consumption_rate;
 243         fixed20_12 active_time;
 244         fixed20_12 dbpp;
 245         fixed20_12 priority_mark_max;
 246         fixed20_12 priority_mark;
 247         fixed20_12 sclk;
 248 };
 249
 250 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
 251                                   struct radeon_crtc *crtc,
 252                                   struct rs690_watermark *wm)
 253 {
 254         struct drm_display_mode *mode = &crtc->base.mode;
 255         fixed20_12 a, b, c;
 256         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 257         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 258
 259         if (!crtc->base.enabled) {
 260                 /* FIXME: wouldn't it better to set priority mark to maximum */
 261                 wm->lb_request_fifo_depth = 4;
 262                 return;
 263         }
 264
 265         if (crtc->vsc.full > dfixed_const(2))
 266                 wm->num_line_pair.full = dfixed_const(2);
 267         else
 268                 wm->num_line_pair.full = dfixed_const(1);
 269
 270         b.full = dfixed_const(mode->crtc_hdisplay);
 271         c.full = dfixed_const(256);
 272         a.full = dfixed_div(b, c);
 273         request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
 274         request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
 275         if (a.full < dfixed_const(4)) {
 276                 wm->lb_request_fifo_depth = 4;
 277         } else {
 278                 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
 279         }
 280
 281         /* Determine consumption rate
 282          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 283          *  vtaps = number of vertical taps,
 284          *  vsc = vertical scaling ratio, defined as source/destination
 285          *  hsc = horizontal scaling ration, defined as source/destination
 286          */
 287         a.full = dfixed_const(mode->clock);
 288         b.full = dfixed_const(1000);
 289         a.full = dfixed_div(a, b);
 290         pclk.full = dfixed_div(b, a);
 291         if (crtc->rmx_type != RMX_OFF) {
 292                 b.full = dfixed_const(2);
 293                 if (crtc->vsc.full > b.full)
 294                         b.full = crtc->vsc.full;
 295                 b.full = dfixed_mul(b, crtc->hsc);
 296                 c.full = dfixed_const(2);
 297                 b.full = dfixed_div(b, c);
 298                 consumption_time.full = dfixed_div(pclk, b);
 299         } else {
 300                 consumption_time.full = pclk.full;
 301         }
 302         a.full = dfixed_const(1);
 303         wm->consumption_rate.full = dfixed_div(a, consumption_time);
 304
 305
 306         /* Determine line time
 307          *  LineTime = total time for one line of displayhtotal
 308          *  LineTime = total number of horizontal pixels
 309          *  pclk = pixel clock period(ns)
 310          */
 311         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
 312         line_time.full = dfixed_mul(a, pclk);
 313
 314         /* Determine active time
 315          *  ActiveTime = time of active region of display within one line,
 316          *  hactive = total number of horizontal active pixels
 317          *  htotal = total number of horizontal pixels
 318          */
 319         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
 320         b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
 321         wm->active_time.full = dfixed_mul(line_time, b);
 322         wm->active_time.full = dfixed_div(wm->active_time, a);
 323
 324         /* Maximun bandwidth is the minimun bandwidth of all component */
 325         rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
 326         if (rdev->mc.igp_sideport_enabled) {
 327                 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
 328                         rdev->pm.sideport_bandwidth.full)
 329                         rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
 330                 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
 331                 read_delay_latency.full = dfixed_div(read_delay_latency,
 332                         rdev->pm.igp_sideport_mclk);
 333         } else {
 334                 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
 335                         rdev->pm.k8_bandwidth.full)
 336                         rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
 337                 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
 338                         rdev->pm.ht_bandwidth.full)
 339                         rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
 340                 read_delay_latency.full = dfixed_const(5000);
 341         }
 342
 343         /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
 344         a.full = dfixed_const(16);
 345         rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
 346         a.full = dfixed_const(1000);
 347         rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
 348         /* Determine chunk time
 349          * ChunkTime = the time it takes the DCP to send one chunk of data
 350          * to the LB which consists of pipeline delay and inter chunk gap
 351          * sclk = system clock(ns)
 352          */
 353         a.full = dfixed_const(256 * 13);
 354         chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
 355         a.full = dfixed_const(10);
 356         chunk_time.full = dfixed_div(chunk_time, a);
 357
 358         /* Determine the worst case latency
 359          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 360          * WorstCaseLatency = worst case time from urgent to when the MC starts
 361          *                    to return data
 362          * READ_DELAY_IDLE_MAX = constant of 1us
 363          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
 364          *             which consists of pipeline delay and inter chunk gap
 365          */
 366         if (dfixed_trunc(wm->num_line_pair) > 1) {
 367                 a.full = dfixed_const(3);
 368                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
 369                 wm->worst_case_latency.full += read_delay_latency.full;
 370         } else {
 371                 a.full = dfixed_const(2);
 372                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
 373                 wm->worst_case_latency.full += read_delay_latency.full;
 374         }
 375
 376         /* Determine the tolerable latency
 377          * TolerableLatency = Any given request has only 1 line time
 378          *                    for the data to be returned
 379          * LBRequestFifoDepth = Number of chunk requests the LB can
 380          *                      put into the request FIFO for a display
 381          *  LineTime = total time for one line of display
 382          *  ChunkTime = the time it takes the DCP to send one chunk
 383          *              of data to the LB which consists of
 384          *  pipeline delay and inter chunk gap
 385          */
 386         if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
 387                 tolerable_latency.full = line_time.full;
 388         } else {
 389                 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
 390                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
 391                 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
 392                 tolerable_latency.full = line_time.full - tolerable_latency.full;
 393         }
 394         /* We assume worst case 32bits (4 bytes) */
 395         wm->dbpp.full = dfixed_const(4 * 8);
 396
 397         /* Determine the maximum priority mark
 398          *  width = viewport width in pixels
 399          */
 400         a.full = dfixed_const(16);
 401         wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
 402         wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
 403         wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
 404
 405         /* Determine estimated width */
 406         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
 407         estimated_width.full = dfixed_div(estimated_width, consumption_time);
 408         if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
 409                 wm->priority_mark.full = dfixed_const(10);
 410         } else {
 411                 a.full = dfixed_const(16);
 412                 wm->priority_mark.full = dfixed_div(estimated_width, a);
 413                 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
 414                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
 415         }
 416 }
 417
 418 void rs690_bandwidth_update(struct radeon_device *rdev)
 419 {
 420         struct drm_display_mode *mode0 = NULL;
 421         struct drm_display_mode *mode1 = NULL;
 422         struct rs690_watermark wm0;
 423         struct rs690_watermark wm1;
 424         u32 tmp;
 425         u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
 426         u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
 427         fixed20_12 priority_mark02, priority_mark12, fill_rate;
 428         fixed20_12 a, b;
 429
 430         radeon_update_display_priority(rdev);
 431
 432         if (rdev->mode_info.crtcs[0]->base.enabled)
 433                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 434         if (rdev->mode_info.crtcs[1]->base.enabled)
 435                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 436         /*
 437          * Set display0/1 priority up in the memory controller for
 438          * modes if the user specifies HIGH for displaypriority
 439          * option.
 440          */
 441         if ((rdev->disp_priority == 2) &&
 442             ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
 443                 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
 444                 tmp &= C_000104_MC_DISP0R_INIT_LAT;
 445                 tmp &= C_000104_MC_DISP1R_INIT_LAT;
 446                 if (mode0)
 447                         tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
 448                 if (mode1)
 449                         tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
 450                 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
 451         }
 452         rs690_line_buffer_adjust(rdev, mode0, mode1);
 453
 454         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
 455                 WREG32(R_006C9C_DCP_CONTROL, 0);
 456         if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 457                 WREG32(R_006C9C_DCP_CONTROL, 2);
 458
 459         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
 460         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 461
 462         tmp = (wm0.lb_request_fifo_depth - 1);
 463         tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
 464         WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
 465
 466         if (mode0 && mode1) {
 467                 if (dfixed_trunc(wm0.dbpp) > 64)
 468                         a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
 469                 else
 470                         a.full = wm0.num_line_pair.full;
 471                 if (dfixed_trunc(wm1.dbpp) > 64)
 472                         b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
 473                 else
 474                         b.full = wm1.num_line_pair.full;
 475                 a.full += b.full;
 476                 fill_rate.full = dfixed_div(wm0.sclk, a);
 477                 if (wm0.consumption_rate.full > fill_rate.full) {
 478                         b.full = wm0.consumption_rate.full - fill_rate.full;
 479                         b.full = dfixed_mul(b, wm0.active_time);
 480                         a.full = dfixed_mul(wm0.worst_case_latency,
 481                                                 wm0.consumption_rate);
 482                         a.full = a.full + b.full;
 483                         b.full = dfixed_const(16 * 1000);
 484                         priority_mark02.full = dfixed_div(a, b);
 485                 } else {
 486                         a.full = dfixed_mul(wm0.worst_case_latency,
 487                                                 wm0.consumption_rate);
 488                         b.full = dfixed_const(16 * 1000);
 489                         priority_mark02.full = dfixed_div(a, b);
 490                 }
 491                 if (wm1.consumption_rate.full > fill_rate.full) {
 492                         b.full = wm1.consumption_rate.full - fill_rate.full;
 493                         b.full = dfixed_mul(b, wm1.active_time);
 494                         a.full = dfixed_mul(wm1.worst_case_latency,
 495                                                 wm1.consumption_rate);
 496                         a.full = a.full + b.full;
 497                         b.full = dfixed_const(16 * 1000);
 498                         priority_mark12.full = dfixed_div(a, b);
 499                 } else {
 500                         a.full = dfixed_mul(wm1.worst_case_latency,
 501                                                 wm1.consumption_rate);
 502                         b.full = dfixed_const(16 * 1000);
 503                         priority_mark12.full = dfixed_div(a, b);
 504                 }
 505                 if (wm0.priority_mark.full > priority_mark02.full)
 506                         priority_mark02.full = wm0.priority_mark.full;
 507                 if (dfixed_trunc(priority_mark02) < 0)
 508                         priority_mark02.full = 0;
 509                 if (wm0.priority_mark_max.full > priority_mark02.full)
 510                         priority_mark02.full = wm0.priority_mark_max.full;
 511                 if (wm1.priority_mark.full > priority_mark12.full)
 512                         priority_mark12.full = wm1.priority_mark.full;
 513                 if (dfixed_trunc(priority_mark12) < 0)
 514                         priority_mark12.full = 0;
 515                 if (wm1.priority_mark_max.full > priority_mark12.full)
 516                         priority_mark12.full = wm1.priority_mark_max.full;
 517                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
 518                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
 519                 if (rdev->disp_priority == 2) {
 520                         d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 521                         d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 522                 }
 523         } else if (mode0) {
 524                 if (dfixed_trunc(wm0.dbpp) > 64)
 525                         a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
 526                 else
 527                         a.full = wm0.num_line_pair.full;
 528                 fill_rate.full = dfixed_div(wm0.sclk, a);
 529                 if (wm0.consumption_rate.full > fill_rate.full) {
 530                         b.full = wm0.consumption_rate.full - fill_rate.full;
 531                         b.full = dfixed_mul(b, wm0.active_time);
 532                         a.full = dfixed_mul(wm0.worst_case_latency,
 533                                                 wm0.consumption_rate);
 534                         a.full = a.full + b.full;
 535                         b.full = dfixed_const(16 * 1000);
 536                         priority_mark02.full = dfixed_div(a, b);
 537                 } else {
 538                         a.full = dfixed_mul(wm0.worst_case_latency,
 539                                                 wm0.consumption_rate);
 540                         b.full = dfixed_const(16 * 1000);
 541                         priority_mark02.full = dfixed_div(a, b);
 542                 }
 543                 if (wm0.priority_mark.full > priority_mark02.full)
 544                         priority_mark02.full = wm0.priority_mark.full;
 545                 if (dfixed_trunc(priority_mark02) < 0)
 546                         priority_mark02.full = 0;
 547                 if (wm0.priority_mark_max.full > priority_mark02.full)
 548                         priority_mark02.full = wm0.priority_mark_max.full;
 549                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
 550                 if (rdev->disp_priority == 2)
 551                         d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 552         } else if (mode1) {
 553                 if (dfixed_trunc(wm1.dbpp) > 64)
 554                         a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
 555                 else
 556                         a.full = wm1.num_line_pair.full;
 557                 fill_rate.full = dfixed_div(wm1.sclk, a);
 558                 if (wm1.consumption_rate.full > fill_rate.full) {
 559                         b.full = wm1.consumption_rate.full - fill_rate.full;
 560                         b.full = dfixed_mul(b, wm1.active_time);
 561                         a.full = dfixed_mul(wm1.worst_case_latency,
 562                                                 wm1.consumption_rate);
 563                         a.full = a.full + b.full;
 564                         b.full = dfixed_const(16 * 1000);
 565                         priority_mark12.full = dfixed_div(a, b);
 566                 } else {
 567                         a.full = dfixed_mul(wm1.worst_case_latency,
 568                                                 wm1.consumption_rate);
 569                         b.full = dfixed_const(16 * 1000);
 570                         priority_mark12.full = dfixed_div(a, b);
 571                 }
 572                 if (wm1.priority_mark.full > priority_mark12.full)
 573                         priority_mark12.full = wm1.priority_mark.full;
 574                 if (dfixed_trunc(priority_mark12) < 0)
 575                         priority_mark12.full = 0;
 576                 if (wm1.priority_mark_max.full > priority_mark12.full)
 577                         priority_mark12.full = wm1.priority_mark_max.full;
 578                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
 579                 if (rdev->disp_priority == 2)
 580                         d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 581         }
 582
 583         WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
 584         WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
 585         WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
 586         WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
 587 }
 588
 589 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 590 {
 591         uint32_t r;
 592
 593         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
 594         r = RREG32(R_00007C_MC_DATA);
 595         WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
 596         return r;
 597 }
 598
 599 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 600 {
 601         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
 602                 S_000078_MC_IND_WR_EN(1));
 603         WREG32(R_00007C_MC_DATA, v);
 604         WREG32(R_000078_MC_INDEX, 0x7F);
 605 }
 606
 607 static void rs690_mc_program(struct radeon_device *rdev)
 608 {
 609         struct rv515_mc_save save;
 610
 611         /* Stops all mc clients */
 612         rv515_mc_stop(rdev, &save);
 613
 614         /* Wait for mc idle */
 615         if (rs690_mc_wait_for_idle(rdev))
 616                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 617         /* Program MC, should be a 32bits limited address space */
 618         WREG32_MC(R_000100_MCCFG_FB_LOCATION,
 619                         S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
 620                         S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
 621         WREG32(R_000134_HDP_FB_LOCATION,
 622                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 623
 624         rv515_mc_resume(rdev, &save);
 625 }
 626
 627 static int rs690_startup(struct radeon_device *rdev)
 628 {
 629         int r;
 630
 631         rs690_mc_program(rdev);
 632         /* Resume clock */
 633         rv515_clock_startup(rdev);
 634         /* Initialize GPU configuration (# pipes, ...) */
 635         rs690_gpu_init(rdev);
 636         /* Initialize GART (initialize after TTM so we can allocate
 637          * memory through TTM but finalize after TTM) */
 638         r = rs400_gart_enable(rdev);
 639         if (r)
 640                 return r;
 641
 642         /* allocate wb buffer */
 643         r = radeon_wb_init(rdev);
 644         if (r)
 645                 return r;
 646
 647         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 648         if (r) {
 649                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 650                 return r;
 651         }
 652
 653         /* Enable IRQ */
 654         if (!rdev->irq.installed) {
 655                 r = radeon_irq_kms_init(rdev);
 656                 if (r)
 657                         return r;
 658         }
 659
 660         rs600_irq_set(rdev);
 661         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 662         /* 1M ring buffer */
 663         r = r100_cp_init(rdev, 1024 * 1024);
 664         if (r) {
 665                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
 666                 return r;
 667         }
 668
 669         r = radeon_ib_pool_init(rdev);
 670         if (r) {
 671                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 672                 return r;
 673         }
 674
 675         r = r600_audio_init(rdev);
 676         if (r) {
 677                 dev_err(rdev->dev, "failed initializing audio\n");
 678                 return r;
 679         }
 680
 681         return 0;
 682 }
 683
 684 int rs690_resume(struct radeon_device *rdev)
 685 {
 686         int r;
 687
 688         /* Make sur GART are not working */
 689         rs400_gart_disable(rdev);
 690         /* Resume clock before doing reset */
 691         rv515_clock_startup(rdev);
 692         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 693         if (radeon_asic_reset(rdev)) {
 694                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 695                         RREG32(R_000E40_RBBM_STATUS),
 696                         RREG32(R_0007C0_CP_STAT));
 697         }
 698         /* post */
 699         atom_asic_init(rdev->mode_info.atom_context);
 700         /* Resume clock after posting */
 701         rv515_clock_startup(rdev);
 702         /* Initialize surface registers */
 703         radeon_surface_init(rdev);
 704
 705         rdev->accel_working = true;
 706         r = rs690_startup(rdev);
 707         if (r) {
 708                 rdev->accel_working = false;
 709         }
 710         return r;
 711 }
 712
 713 int rs690_suspend(struct radeon_device *rdev)
 714 {
 715         r600_audio_fini(rdev);
 716         r100_cp_disable(rdev);
 717         radeon_wb_disable(rdev);
 718         rs600_irq_disable(rdev);
 719         rs400_gart_disable(rdev);
 720         return 0;
 721 }
 722
 723 void rs690_fini(struct radeon_device *rdev)
 724 {
 725         r600_audio_fini(rdev);
 726         r100_cp_fini(rdev);
 727         radeon_wb_fini(rdev);
 728         radeon_ib_pool_fini(rdev);
 729         radeon_gem_fini(rdev);
 730         rs400_gart_fini(rdev);
 731         radeon_irq_kms_fini(rdev);
 732         radeon_fence_driver_fini(rdev);
 733         radeon_bo_fini(rdev);
 734         radeon_atombios_fini(rdev);
 735         kfree(rdev->bios);
 736         rdev->bios = NULL;
 737 }
 738
 739 int rs690_init(struct radeon_device *rdev)
 740 {
 741         int r;
 742
 743         /* Disable VGA */
 744         rv515_vga_render_disable(rdev);
 745         /* Initialize scratch registers */
 746         radeon_scratch_init(rdev);
 747         /* Initialize surface registers */
 748         radeon_surface_init(rdev);
 749         /* restore some register to sane defaults */
 750         r100_restore_sanity(rdev);
 751         /* TODO: disable VGA need to use VGA request */
 752         /* BIOS*/
 753         if (!radeon_get_bios(rdev)) {
 754                 if (ASIC_IS_AVIVO(rdev))
 755                         return -EINVAL;
 756         }
 757         if (rdev->is_atom_bios) {
 758                 r = radeon_atombios_init(rdev);
 759                 if (r)
 760                         return r;
 761         } else {
 762                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 763                 return -EINVAL;
 764         }
 765         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 766         if (radeon_asic_reset(rdev)) {
 767                 dev_warn(rdev->dev,
 768                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 769                         RREG32(R_000E40_RBBM_STATUS),
 770                         RREG32(R_0007C0_CP_STAT));
 771         }
 772         /* check if cards are posted or not */
 773         if (radeon_boot_test_post_card(rdev) == false)
 774                 return -EINVAL;
 775
 776         /* Initialize clocks */
 777         radeon_get_clock_info(rdev->ddev);
 778         /* initialize memory controller */
 779         rs690_mc_init(rdev);
 780         rv515_debugfs(rdev);
 781         /* Fence driver */
 782         r = radeon_fence_driver_init(rdev);
 783         if (r)
 784                 return r;
 785         /* Memory manager */
 786         r = radeon_bo_init(rdev);
 787         if (r)
 788                 return r;
 789         r = rs400_gart_init(rdev);
 790         if (r)
 791                 return r;
 792         rs600_set_safe_registers(rdev);
 793
 794         rdev->accel_working = true;
 795         r = rs690_startup(rdev);
 796         if (r) {
 797                 /* Somethings want wront with the accel init stop accel */
 798                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 799                 r100_cp_fini(rdev);
 800                 radeon_wb_fini(rdev);
 801                 radeon_ib_pool_fini(rdev);
 802                 rs400_gart_fini(rdev);
 803                 radeon_irq_kms_fini(rdev);
 804                 rdev->accel_working = false;
 805         }
 806         return 0;
 807 }