drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <linux/pm_runtime.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_edid.h>
  36
  37 #include <linux/gcd.h>
  38
  39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  40 {
  41         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  42         struct drm_device *dev = crtc->dev;
  43         struct radeon_device *rdev = dev->dev_private;
  44         int i;
  45
  46         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  47         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  48
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  51         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  52
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  55         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  56
  57         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  58         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  59         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  60
  61         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  62         for (i = 0; i < 256; i++) {
  63                 WREG32(AVIVO_DC_LUT_30_COLOR,
  64                              (radeon_crtc->lut_r[i] << 20) |
  65                              (radeon_crtc->lut_g[i] << 10) |
  66                              (radeon_crtc->lut_b[i] << 0));
  67         }
  68
  69         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  70 }
  71
  72 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  73 {
  74         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  75         struct drm_device *dev = crtc->dev;
  76         struct radeon_device *rdev = dev->dev_private;
  77         int i;
  78
  79         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  80         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  81
  82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  83         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  84         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  85
  86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  87         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  88         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  89
  90         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  91         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  92
  93         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  94         for (i = 0; i < 256; i++) {
  95                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  96                        (radeon_crtc->lut_r[i] << 20) |
  97                        (radeon_crtc->lut_g[i] << 10) |
  98                        (radeon_crtc->lut_b[i] << 0));
  99         }
 100 }
 101
 102 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 103 {
 104         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 105         struct drm_device *dev = crtc->dev;
 106         struct radeon_device *rdev = dev->dev_private;
 107         int i;
 108
 109         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 110
 111         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 112                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 113                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 114         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 115                NI_GRPH_PRESCALE_BYPASS);
 116         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 117                NI_OVL_PRESCALE_BYPASS);
 118         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 119                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 120                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 121
 122         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 123
 124         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 125         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 126         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 127
 128         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 129         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 130         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 131
 132         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 133         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 134
 135         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 136         for (i = 0; i < 256; i++) {
 137                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 138                        (radeon_crtc->lut_r[i] << 20) |
 139                        (radeon_crtc->lut_g[i] << 10) |
 140                        (radeon_crtc->lut_b[i] << 0));
 141         }
 142
 143         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 144                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 145                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 146                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 147                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 148         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 149                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 150                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 151         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 152                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 153                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 154         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 155                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 156                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 157         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 158         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 159         if (ASIC_IS_DCE8(rdev)) {
 160                 /* XXX this only needs to be programmed once per crtc at startup,
 161                  * not sure where the best place for it is
 162                  */
 163                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 164                        CIK_CURSOR_ALPHA_BLND_ENA);
 165         }
 166 }
 167
 168 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 169 {
 170         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 171         struct drm_device *dev = crtc->dev;
 172         struct radeon_device *rdev = dev->dev_private;
 173         int i;
 174         uint32_t dac2_cntl;
 175
 176         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 177         if (radeon_crtc->crtc_id == 0)
 178                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 179         else
 180                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 181         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 182
 183         WREG8(RADEON_PALETTE_INDEX, 0);
 184         for (i = 0; i < 256; i++) {
 185                 WREG32(RADEON_PALETTE_30_DATA,
 186                              (radeon_crtc->lut_r[i] << 20) |
 187                              (radeon_crtc->lut_g[i] << 10) |
 188                              (radeon_crtc->lut_b[i] << 0));
 189         }
 190 }
 191
 192 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 193 {
 194         struct drm_device *dev = crtc->dev;
 195         struct radeon_device *rdev = dev->dev_private;
 196
 197         if (!crtc->enabled)
 198                 return;
 199
 200         if (ASIC_IS_DCE5(rdev))
 201                 dce5_crtc_load_lut(crtc);
 202         else if (ASIC_IS_DCE4(rdev))
 203                 dce4_crtc_load_lut(crtc);
 204         else if (ASIC_IS_AVIVO(rdev))
 205                 avivo_crtc_load_lut(crtc);
 206         else
 207                 legacy_crtc_load_lut(crtc);
 208 }
 209
 210 /** Sets the color ramps on behalf of fbcon */
 211 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 212                               u16 blue, int regno)
 213 {
 214         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 215
 216         radeon_crtc->lut_r[regno] = red >> 6;
 217         radeon_crtc->lut_g[regno] = green >> 6;
 218         radeon_crtc->lut_b[regno] = blue >> 6;
 219 }
 220
 221 /** Gets the color ramps on behalf of fbcon */
 222 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 223                               u16 *blue, int regno)
 224 {
 225         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 226
 227         *red = radeon_crtc->lut_r[regno] << 6;
 228         *green = radeon_crtc->lut_g[regno] << 6;
 229         *blue = radeon_crtc->lut_b[regno] << 6;
 230 }
 231
 232 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 233                                   u16 *blue, uint32_t start, uint32_t size)
 234 {
 235         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 236         int end = (start + size > 256) ? 256 : start + size, i;
 237
 238         /* userspace palettes are always correct as is */
 239         for (i = start; i < end; i++) {
 240                 radeon_crtc->lut_r[i] = red[i] >> 6;
 241                 radeon_crtc->lut_g[i] = green[i] >> 6;
 242                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 243         }
 244         radeon_crtc_load_lut(crtc);
 245 }
 246
 247 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 248 {
 249         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 250
 251         drm_crtc_cleanup(crtc);
 252         kfree(radeon_crtc);
 253 }
 254
 255 /*
 256  * Handle unpin events outside the interrupt handler proper.
 257  */
 258 static void radeon_unpin_work_func(struct work_struct *__work)
 259 {
 260         struct radeon_unpin_work *work =
 261                 container_of(__work, struct radeon_unpin_work, work);
 262         int r;
 263
 264         /* unpin of the old buffer */
 265         r = radeon_bo_reserve(work->old_rbo, false);
 266         if (likely(r == 0)) {
 267                 r = radeon_bo_unpin(work->old_rbo);
 268                 if (unlikely(r != 0)) {
 269                         DRM_ERROR("failed to unpin buffer after flip\n");
 270                 }
 271                 radeon_bo_unreserve(work->old_rbo);
 272         } else
 273                 DRM_ERROR("failed to reserve buffer after flip\n");
 274
 275         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 276         kfree(work);
 277 }
 278
 279 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 280 {
 281         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 282         struct radeon_unpin_work *work;
 283         unsigned long flags;
 284         u32 update_pending;
 285         int vpos, hpos;
 286
 287         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 288         work = radeon_crtc->unpin_work;
 289         if (work == NULL ||
 290             (work->fence && !radeon_fence_signaled(work->fence))) {
 291                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 292                 return;
 293         }
 294         /* New pageflip, or just completion of a previous one? */
 295         if (!radeon_crtc->deferred_flip_completion) {
 296                 /* do the flip (mmio) */
 297                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 298         } else {
 299                 /* This is just a completion of a flip queued in crtc
 300                  * at last invocation. Make sure we go directly to
 301                  * completion routine.
 302                  */
 303                 update_pending = 0;
 304                 radeon_crtc->deferred_flip_completion = 0;
 305         }
 306
 307         /* Has the pageflip already completed in crtc, or is it certain
 308          * to complete in this vblank?
 309          */
 310         if (update_pending &&
 311             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
 312                                                                &vpos, &hpos, NULL, NULL)) &&
 313             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 314              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 315                 /* crtc didn't flip in this target vblank interval,
 316                  * but flip is pending in crtc. Based on the current
 317                  * scanout position we know that the current frame is
 318                  * (nearly) complete and the flip will (likely)
 319                  * complete before the start of the next frame.
 320                  */
 321                 update_pending = 0;
 322         }
 323         if (update_pending) {
 324                 /* crtc didn't flip in this target vblank interval,
 325                  * but flip is pending in crtc. It will complete it
 326                  * in next vblank interval, so complete the flip at
 327                  * next vblank irq.
 328                  */
 329                 radeon_crtc->deferred_flip_completion = 1;
 330                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 331                 return;
 332         }
 333
 334         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 335         radeon_crtc->unpin_work = NULL;
 336
 337         /* wakeup userspace */
 338         if (work->event)
 339                 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
 340
 341         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 342
 343         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 344         radeon_fence_unref(&work->fence);
 345         radeon_post_page_flip(work->rdev, work->crtc_id);
 346         schedule_work(&work->work);
 347 }
 348
 349 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 350                                  struct drm_framebuffer *fb,
 351                                  struct drm_pending_vblank_event *event,
 352                                  uint32_t page_flip_flags)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         struct radeon_device *rdev = dev->dev_private;
 356         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 357         struct radeon_framebuffer *old_radeon_fb;
 358         struct radeon_framebuffer *new_radeon_fb;
 359         struct drm_gem_object *obj;
 360         struct radeon_bo *rbo;
 361         struct radeon_unpin_work *work;
 362         unsigned long flags;
 363         u32 tiling_flags, pitch_pixels;
 364         u64 base;
 365         int r;
 366
 367         work = kzalloc(sizeof *work, GFP_KERNEL);
 368         if (work == NULL)
 369                 return -ENOMEM;
 370
 371         work->event = event;
 372         work->rdev = rdev;
 373         work->crtc_id = radeon_crtc->crtc_id;
 374         old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 375         new_radeon_fb = to_radeon_framebuffer(fb);
 376         /* schedule unpin of the old buffer */
 377         obj = old_radeon_fb->obj;
 378         /* take a reference to the old object */
 379         drm_gem_object_reference(obj);
 380         rbo = gem_to_radeon_bo(obj);
 381         work->old_rbo = rbo;
 382         obj = new_radeon_fb->obj;
 383         rbo = gem_to_radeon_bo(obj);
 384
 385         spin_lock(&rbo->tbo.bdev->fence_lock);
 386         if (rbo->tbo.sync_obj)
 387                 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
 388         spin_unlock(&rbo->tbo.bdev->fence_lock);
 389
 390         INIT_WORK(&work->work, radeon_unpin_work_func);
 391
 392         /* We borrow the event spin lock for protecting unpin_work */
 393         spin_lock_irqsave(&dev->event_lock, flags);
 394         if (radeon_crtc->unpin_work) {
 395                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 396                 r = -EBUSY;
 397                 goto unlock_free;
 398         }
 399         radeon_crtc->unpin_work = work;
 400         radeon_crtc->deferred_flip_completion = 0;
 401         spin_unlock_irqrestore(&dev->event_lock, flags);
 402
 403         /* pin the new buffer */
 404         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 405                          work->old_rbo, rbo);
 406
 407         r = radeon_bo_reserve(rbo, false);
 408         if (unlikely(r != 0)) {
 409                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 410                 goto pflip_cleanup;
 411         }
 412         /* Only 27 bit offset for legacy CRTC */
 413         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
 414                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 415         if (unlikely(r != 0)) {
 416                 radeon_bo_unreserve(rbo);
 417                 r = -EINVAL;
 418                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 419                 goto pflip_cleanup;
 420         }
 421         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 422         radeon_bo_unreserve(rbo);
 423
 424         if (!ASIC_IS_AVIVO(rdev)) {
 425                 /* crtc offset is from display base addr not FB location */
 426                 base -= radeon_crtc->legacy_display_base_addr;
 427                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 428
 429                 if (tiling_flags & RADEON_TILING_MACRO) {
 430                         if (ASIC_IS_R300(rdev)) {
 431                                 base &= ~0x7ff;
 432                         } else {
 433                                 int byteshift = fb->bits_per_pixel >> 4;
 434                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 435                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 436                         }
 437                 } else {
 438                         int offset = crtc->y * pitch_pixels + crtc->x;
 439                         switch (fb->bits_per_pixel) {
 440                         case 8:
 441                         default:
 442                                 offset *= 1;
 443                                 break;
 444                         case 15:
 445                         case 16:
 446                                 offset *= 2;
 447                                 break;
 448                         case 24:
 449                                 offset *= 3;
 450                                 break;
 451                         case 32:
 452                                 offset *= 4;
 453                                 break;
 454                         }
 455                         base += offset;
 456                 }
 457                 base &= ~7;
 458         }
 459
 460         spin_lock_irqsave(&dev->event_lock, flags);
 461         work->new_crtc_base = base;
 462         spin_unlock_irqrestore(&dev->event_lock, flags);
 463
 464         /* update crtc fb */
 465         crtc->primary->fb = fb;
 466
 467         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 468         if (r) {
 469                 DRM_ERROR("failed to get vblank before flip\n");
 470                 goto pflip_cleanup1;
 471         }
 472
 473         /* set the proper interrupt */
 474         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 475
 476         return 0;
 477
 478 pflip_cleanup1:
 479         if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
 480                 DRM_ERROR("failed to reserve new rbo in error path\n");
 481                 goto pflip_cleanup;
 482         }
 483         if (unlikely(radeon_bo_unpin(rbo) != 0)) {
 484                 DRM_ERROR("failed to unpin new rbo in error path\n");
 485         }
 486         radeon_bo_unreserve(rbo);
 487
 488 pflip_cleanup:
 489         spin_lock_irqsave(&dev->event_lock, flags);
 490         radeon_crtc->unpin_work = NULL;
 491 unlock_free:
 492         spin_unlock_irqrestore(&dev->event_lock, flags);
 493         drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
 494         radeon_fence_unref(&work->fence);
 495         kfree(work);
 496
 497         return r;
 498 }
 499
 500 static int
 501 radeon_crtc_set_config(struct drm_mode_set *set)
 502 {
 503         struct drm_device *dev;
 504         struct radeon_device *rdev;
 505         struct drm_crtc *crtc;
 506         bool active = false;
 507         int ret;
 508
 509         if (!set || !set->crtc)
 510                 return -EINVAL;
 511
 512         dev = set->crtc->dev;
 513
 514         ret = pm_runtime_get_sync(dev->dev);
 515         if (ret < 0)
 516                 return ret;
 517
 518         ret = drm_crtc_helper_set_config(set);
 519
 520         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 521                 if (crtc->enabled)
 522                         active = true;
 523
 524         pm_runtime_mark_last_busy(dev->dev);
 525
 526         rdev = dev->dev_private;
 527         /* if we have active crtcs and we don't have a power ref,
 528            take the current one */
 529         if (active && !rdev->have_disp_power_ref) {
 530                 rdev->have_disp_power_ref = true;
 531                 return ret;
 532         }
 533         /* if we have no active crtcs, then drop the power ref
 534            we got before */
 535         if (!active && rdev->have_disp_power_ref) {
 536                 pm_runtime_put_autosuspend(dev->dev);
 537                 rdev->have_disp_power_ref = false;
 538         }
 539
 540         /* drop the power reference we got coming in here */
 541         pm_runtime_put_autosuspend(dev->dev);
 542         return ret;
 543 }
 544 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 545         .cursor_set = radeon_crtc_cursor_set,
 546         .cursor_move = radeon_crtc_cursor_move,
 547         .gamma_set = radeon_crtc_gamma_set,
 548         .set_config = radeon_crtc_set_config,
 549         .destroy = radeon_crtc_destroy,
 550         .page_flip = radeon_crtc_page_flip,
 551 };
 552
 553 static void radeon_crtc_init(struct drm_device *dev, int index)
 554 {
 555         struct radeon_device *rdev = dev->dev_private;
 556         struct radeon_crtc *radeon_crtc;
 557         int i;
 558
 559         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 560         if (radeon_crtc == NULL)
 561                 return;
 562
 563         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 564
 565         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 566         radeon_crtc->crtc_id = index;
 567         rdev->mode_info.crtcs[index] = radeon_crtc;
 568
 569         if (rdev->family >= CHIP_BONAIRE) {
 570                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 571                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 572         } else {
 573                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 574                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 575         }
 576         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 577         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 578
 579 #if 0
 580         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 581         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 582         radeon_crtc->mode_set.num_connectors = 0;
 583 #endif
 584
 585         for (i = 0; i < 256; i++) {
 586                 radeon_crtc->lut_r[i] = i << 2;
 587                 radeon_crtc->lut_g[i] = i << 2;
 588                 radeon_crtc->lut_b[i] = i << 2;
 589         }
 590
 591         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 592                 radeon_atombios_init_crtc(dev, radeon_crtc);
 593         else
 594                 radeon_legacy_init_crtc(dev, radeon_crtc);
 595 }
 596
 597 static const char *encoder_names[38] = {
 598         "NONE",
 599         "INTERNAL_LVDS",
 600         "INTERNAL_TMDS1",
 601         "INTERNAL_TMDS2",
 602         "INTERNAL_DAC1",
 603         "INTERNAL_DAC2",
 604         "INTERNAL_SDVOA",
 605         "INTERNAL_SDVOB",
 606         "SI170B",
 607         "CH7303",
 608         "CH7301",
 609         "INTERNAL_DVO1",
 610         "EXTERNAL_SDVOA",
 611         "EXTERNAL_SDVOB",
 612         "TITFP513",
 613         "INTERNAL_LVTM1",
 614         "VT1623",
 615         "HDMI_SI1930",
 616         "HDMI_INTERNAL",
 617         "INTERNAL_KLDSCP_TMDS1",
 618         "INTERNAL_KLDSCP_DVO1",
 619         "INTERNAL_KLDSCP_DAC1",
 620         "INTERNAL_KLDSCP_DAC2",
 621         "SI178",
 622         "MVPU_FPGA",
 623         "INTERNAL_DDI",
 624         "VT1625",
 625         "HDMI_SI1932",
 626         "DP_AN9801",
 627         "DP_DP501",
 628         "INTERNAL_UNIPHY",
 629         "INTERNAL_KLDSCP_LVTMA",
 630         "INTERNAL_UNIPHY1",
 631         "INTERNAL_UNIPHY2",
 632         "NUTMEG",
 633         "TRAVIS",
 634         "INTERNAL_VCE",
 635         "INTERNAL_UNIPHY3",
 636 };
 637
 638 static const char *hpd_names[6] = {
 639         "HPD1",
 640         "HPD2",
 641         "HPD3",
 642         "HPD4",
 643         "HPD5",
 644         "HPD6",
 645 };
 646
 647 static void radeon_print_display_setup(struct drm_device *dev)
 648 {
 649         struct drm_connector *connector;
 650         struct radeon_connector *radeon_connector;
 651         struct drm_encoder *encoder;
 652         struct radeon_encoder *radeon_encoder;
 653         uint32_t devices;
 654         int i = 0;
 655
 656         DRM_INFO("Radeon Display Connectors\n");
 657         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 658                 radeon_connector = to_radeon_connector(connector);
 659                 DRM_INFO("Connector %d:\n", i);
 660                 DRM_INFO("  %s\n", drm_get_connector_name(connector));
 661                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 662                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 663                 if (radeon_connector->ddc_bus) {
 664                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 665                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 666                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 667                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 668                                  radeon_connector->ddc_bus->rec.a_data_reg,
 669                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 670                                  radeon_connector->ddc_bus->rec.en_data_reg,
 671                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 672                                  radeon_connector->ddc_bus->rec.y_data_reg);
 673                         if (radeon_connector->router.ddc_valid)
 674                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 675                                          radeon_connector->router.ddc_mux_control_pin,
 676                                          radeon_connector->router.ddc_mux_state);
 677                         if (radeon_connector->router.cd_valid)
 678                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 679                                          radeon_connector->router.cd_mux_control_pin,
 680                                          radeon_connector->router.cd_mux_state);
 681                 } else {
 682                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 683                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 684                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 685                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 686                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 687                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 688                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 689                 }
 690                 DRM_INFO("  Encoders:\n");
 691                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 692                         radeon_encoder = to_radeon_encoder(encoder);
 693                         devices = radeon_encoder->devices & radeon_connector->devices;
 694                         if (devices) {
 695                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 696                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 697                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 698                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 699                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 700                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 701                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 702                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 703                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 704                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 705                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 706                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 707                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 708                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 709                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 710                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 711                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 712                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 713                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 714                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 715                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 716                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 717                         }
 718                 }
 719                 i++;
 720         }
 721 }
 722
 723 static bool radeon_setup_enc_conn(struct drm_device *dev)
 724 {
 725         struct radeon_device *rdev = dev->dev_private;
 726         bool ret = false;
 727
 728         if (rdev->bios) {
 729                 if (rdev->is_atom_bios) {
 730                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 731                         if (ret == false)
 732                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 733                 } else {
 734                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 735                         if (ret == false)
 736                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 737                 }
 738         } else {
 739                 if (!ASIC_IS_AVIVO(rdev))
 740                         ret = radeon_get_legacy_connector_info_from_table(dev);
 741         }
 742         if (ret) {
 743                 radeon_setup_encoder_clones(dev);
 744                 radeon_print_display_setup(dev);
 745         }
 746
 747         return ret;
 748 }
 749
 750 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 751 {
 752         struct drm_device *dev = radeon_connector->base.dev;
 753         struct radeon_device *rdev = dev->dev_private;
 754         int ret = 0;
 755
 756         /* on hw with routers, select right port */
 757         if (radeon_connector->router.ddc_valid)
 758                 radeon_router_select_ddc_port(radeon_connector);
 759
 760         if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 761             ENCODER_OBJECT_ID_NONE) {
 762                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 763
 764                 if (dig->dp_i2c_bus)
 765                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 766                                                               &dig->dp_i2c_bus->adapter);
 767         } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 768                    (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 769                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 770
 771                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 772                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 773                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 774                                                               &dig->dp_i2c_bus->adapter);
 775                 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 776                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 777                                                               &radeon_connector->ddc_bus->adapter);
 778         } else {
 779                 if (radeon_connector->ddc_bus && !radeon_connector->edid)
 780                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 781                                                               &radeon_connector->ddc_bus->adapter);
 782         }
 783
 784         if (!radeon_connector->edid) {
 785                 if (rdev->is_atom_bios) {
 786                         /* some laptops provide a hardcoded edid in rom for LCDs */
 787                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 788                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 789                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 790                 } else
 791                         /* some servers provide a hardcoded edid in rom for KVMs */
 792                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 793         }
 794         if (radeon_connector->edid) {
 795                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 796                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 797                 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
 798                 return ret;
 799         }
 800         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 801         return 0;
 802 }
 803
 804 /* avivo */
 805
 806 /**
 807  * avivo_reduce_ratio - fractional number reduction
 808  *
 809  * @nom: nominator
 810  * @den: denominator
 811  * @nom_min: minimum value for nominator
 812  * @den_min: minimum value for denominator
 813  *
 814  * Find the greatest common divisor and apply it on both nominator and
 815  * denominator, but make nominator and denominator are at least as large
 816  * as their minimum values.
 817  */
 818 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 819                                unsigned nom_min, unsigned den_min)
 820 {
 821         unsigned tmp;
 822
 823         /* reduce the numbers to a simpler ratio */
 824         tmp = gcd(*nom, *den);
 825         *nom /= tmp;
 826         *den /= tmp;
 827
 828         /* make sure nominator is large enough */
 829         if (*nom < nom_min) {
 830                 tmp = (nom_min + *nom - 1) / *nom;
 831                 *nom *= tmp;
 832                 *den *= tmp;
 833         }
 834
 835         /* make sure the denominator is large enough */
 836         if (*den < den_min) {
 837                 tmp = (den_min + *den - 1) / *den;
 838                 *nom *= tmp;
 839                 *den *= tmp;
 840         }
 841 }
 842
 843 /**
 844  * radeon_compute_pll_avivo - compute PLL paramaters
 845  *
 846  * @pll: information about the PLL
 847  * @dot_clock_p: resulting pixel clock
 848  * fb_div_p: resulting feedback divider
 849  * frac_fb_div_p: fractional part of the feedback divider
 850  * ref_div_p: resulting reference divider
 851  * post_div_p: resulting reference divider
 852  *
 853  * Try to calculate the PLL parameters to generate the given frequency:
 854  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 855  */
 856 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 857                               u32 freq,
 858                               u32 *dot_clock_p,
 859                               u32 *fb_div_p,
 860                               u32 *frac_fb_div_p,
 861                               u32 *ref_div_p,
 862                               u32 *post_div_p)
 863 {
 864         unsigned fb_div_min, fb_div_max, fb_div;
 865         unsigned post_div_min, post_div_max, post_div;
 866         unsigned ref_div_min, ref_div_max, ref_div;
 867         unsigned post_div_best, diff_best;
 868         unsigned nom, den, tmp;
 869
 870         /* determine allowed feedback divider range */
 871         fb_div_min = pll->min_feedback_div;
 872         fb_div_max = pll->max_feedback_div;
 873
 874         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 875                 fb_div_min *= 10;
 876                 fb_div_max *= 10;
 877         }
 878
 879         /* determine allowed ref divider range */
 880         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 881                 ref_div_min = pll->reference_div;
 882         else
 883                 ref_div_min = pll->min_ref_div;
 884         ref_div_max = pll->max_ref_div;
 885
 886         /* determine allowed post divider range */
 887         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
 888                 post_div_min = pll->post_div;
 889                 post_div_max = pll->post_div;
 890         } else {
 891                 unsigned target_clock = freq / 10;
 892                 unsigned vco_min, vco_max;
 893
 894                 if (pll->flags & RADEON_PLL_IS_LCD) {
 895                         vco_min = pll->lcd_pll_out_min;
 896                         vco_max = pll->lcd_pll_out_max;
 897                 } else {
 898                         vco_min = pll->pll_out_min;
 899                         vco_max = pll->pll_out_max;
 900                 }
 901
 902                 post_div_min = vco_min / target_clock;
 903                 if ((target_clock * post_div_min) < vco_min)
 904                         ++post_div_min;
 905                 if (post_div_min < pll->min_post_div)
 906                         post_div_min = pll->min_post_div;
 907
 908                 post_div_max = vco_max / target_clock;
 909                 if ((target_clock * post_div_max) > vco_max)
 910                         --post_div_max;
 911                 if (post_div_max > pll->max_post_div)
 912                         post_div_max = pll->max_post_div;
 913         }
 914
 915         /* represent the searched ratio as fractional number */
 916         nom = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? freq : freq / 10;
 917         den = pll->reference_freq;
 918
 919         /* reduce the numbers to a simpler ratio */
 920         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
 921
 922         /* now search for a post divider */
 923         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
 924                 post_div_best = post_div_min;
 925         else
 926                 post_div_best = post_div_max;
 927         diff_best = ~0;
 928
 929         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
 930                 unsigned diff = abs(den - den / post_div * post_div);
 931                 if (diff < diff_best || (diff == diff_best &&
 932                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
 933
 934                         post_div_best = post_div;
 935                         diff_best = diff;
 936                 }
 937         }
 938         post_div = post_div_best;
 939
 940         /* get matching reference and feedback divider */
 941         ref_div = max(den / post_div, 1u);
 942         fb_div = nom;
 943
 944         /* we're almost done, but reference and feedback
 945            divider might be to large now */
 946
 947         tmp = ref_div;
 948
 949         if (fb_div > fb_div_max) {
 950                 ref_div = ref_div * fb_div_max / fb_div;
 951                 fb_div = fb_div_max;
 952         }
 953
 954         if (ref_div > ref_div_max) {
 955                 ref_div = ref_div_max;
 956                 fb_div = nom * ref_div_max / tmp;
 957         }
 958
 959         /* reduce the numbers to a simpler ratio once more */
 960         /* this also makes sure that the reference divider is large enough */
 961         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
 962
 963         /* and finally save the result */
 964         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 965                 *fb_div_p = fb_div / 10;
 966                 *frac_fb_div_p = fb_div % 10;
 967         } else {
 968                 *fb_div_p = fb_div;
 969                 *frac_fb_div_p = 0;
 970         }
 971
 972         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
 973                         (pll->reference_freq * *frac_fb_div_p)) /
 974                        (ref_div * post_div * 10);
 975         *ref_div_p = ref_div;
 976         *post_div_p = post_div;
 977
 978         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 979                       freq, *dot_clock_p, *fb_div_p, *frac_fb_div_p,
 980                       ref_div, post_div);
 981 }
 982
 983 /* pre-avivo */
 984 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 985 {
 986         uint64_t mod;
 987
 988         n += d / 2;
 989
 990         mod = do_div(n, d);
 991         return n;
 992 }
 993
 994 void radeon_compute_pll_legacy(struct radeon_pll *pll,
 995                                uint64_t freq,
 996                                uint32_t *dot_clock_p,
 997                                uint32_t *fb_div_p,
 998                                uint32_t *frac_fb_div_p,
 999                                uint32_t *ref_div_p,
1000                                uint32_t *post_div_p)
1001 {
1002         uint32_t min_ref_div = pll->min_ref_div;
1003         uint32_t max_ref_div = pll->max_ref_div;
1004         uint32_t min_post_div = pll->min_post_div;
1005         uint32_t max_post_div = pll->max_post_div;
1006         uint32_t min_fractional_feed_div = 0;
1007         uint32_t max_fractional_feed_div = 0;
1008         uint32_t best_vco = pll->best_vco;
1009         uint32_t best_post_div = 1;
1010         uint32_t best_ref_div = 1;
1011         uint32_t best_feedback_div = 1;
1012         uint32_t best_frac_feedback_div = 0;
1013         uint32_t best_freq = -1;
1014         uint32_t best_error = 0xffffffff;
1015         uint32_t best_vco_diff = 1;
1016         uint32_t post_div;
1017         u32 pll_out_min, pll_out_max;
1018
1019         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1020         freq = freq * 1000;
1021
1022         if (pll->flags & RADEON_PLL_IS_LCD) {
1023                 pll_out_min = pll->lcd_pll_out_min;
1024                 pll_out_max = pll->lcd_pll_out_max;
1025         } else {
1026                 pll_out_min = pll->pll_out_min;
1027                 pll_out_max = pll->pll_out_max;
1028         }
1029
1030         if (pll_out_min > 64800)
1031                 pll_out_min = 64800;
1032
1033         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1034                 min_ref_div = max_ref_div = pll->reference_div;
1035         else {
1036                 while (min_ref_div < max_ref_div-1) {
1037                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1038                         uint32_t pll_in = pll->reference_freq / mid;
1039                         if (pll_in < pll->pll_in_min)
1040                                 max_ref_div = mid;
1041                         else if (pll_in > pll->pll_in_max)
1042                                 min_ref_div = mid;
1043                         else
1044                                 break;
1045                 }
1046         }
1047
1048         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1049                 min_post_div = max_post_div = pll->post_div;
1050
1051         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1052                 min_fractional_feed_div = pll->min_frac_feedback_div;
1053                 max_fractional_feed_div = pll->max_frac_feedback_div;
1054         }
1055
1056         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1057                 uint32_t ref_div;
1058
1059                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1060                         continue;
1061
1062                 /* legacy radeons only have a few post_divs */
1063                 if (pll->flags & RADEON_PLL_LEGACY) {
1064                         if ((post_div == 5) ||
1065                             (post_div == 7) ||
1066                             (post_div == 9) ||
1067                             (post_div == 10) ||
1068                             (post_div == 11) ||
1069                             (post_div == 13) ||
1070                             (post_div == 14) ||
1071                             (post_div == 15))
1072                                 continue;
1073                 }
1074
1075                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1076                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1077                         uint32_t pll_in = pll->reference_freq / ref_div;
1078                         uint32_t min_feed_div = pll->min_feedback_div;
1079                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1080
1081                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1082                                 continue;
1083
1084                         while (min_feed_div < max_feed_div) {
1085                                 uint32_t vco;
1086                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1087                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1088                                 uint32_t frac_feedback_div;
1089                                 uint64_t tmp;
1090
1091                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1092
1093                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1094                                 vco = radeon_div(tmp, ref_div);
1095
1096                                 if (vco < pll_out_min) {
1097                                         min_feed_div = feedback_div + 1;
1098                                         continue;
1099                                 } else if (vco > pll_out_max) {
1100                                         max_feed_div = feedback_div;
1101                                         continue;
1102                                 }
1103
1104                                 while (min_frac_feed_div < max_frac_feed_div) {
1105                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1106                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1107                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1108                                         current_freq = radeon_div(tmp, ref_div * post_div);
1109
1110                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1111                                                 if (freq < current_freq)
1112                                                         error = 0xffffffff;
1113                                                 else
1114                                                         error = freq - current_freq;
1115                                         } else
1116                                                 error = abs(current_freq - freq);
1117                                         vco_diff = abs(vco - best_vco);
1118
1119                                         if ((best_vco == 0 && error < best_error) ||
1120                                             (best_vco != 0 &&
1121                                              ((best_error > 100 && error < best_error - 100) ||
1122                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1123                                                 best_post_div = post_div;
1124                                                 best_ref_div = ref_div;
1125                                                 best_feedback_div = feedback_div;
1126                                                 best_frac_feedback_div = frac_feedback_div;
1127                                                 best_freq = current_freq;
1128                                                 best_error = error;
1129                                                 best_vco_diff = vco_diff;
1130                                         } else if (current_freq == freq) {
1131                                                 if (best_freq == -1) {
1132                                                         best_post_div = post_div;
1133                                                         best_ref_div = ref_div;
1134                                                         best_feedback_div = feedback_div;
1135                                                         best_frac_feedback_div = frac_feedback_div;
1136                                                         best_freq = current_freq;
1137                                                         best_error = error;
1138                                                         best_vco_diff = vco_diff;
1139                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1140                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1141                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1142                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1143                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1144                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1145                                                         best_post_div = post_div;
1146                                                         best_ref_div = ref_div;
1147                                                         best_feedback_div = feedback_div;
1148                                                         best_frac_feedback_div = frac_feedback_div;
1149                                                         best_freq = current_freq;
1150                                                         best_error = error;
1151                                                         best_vco_diff = vco_diff;
1152                                                 }
1153                                         }
1154                                         if (current_freq < freq)
1155                                                 min_frac_feed_div = frac_feedback_div + 1;
1156                                         else
1157                                                 max_frac_feed_div = frac_feedback_div;
1158                                 }
1159                                 if (current_freq < freq)
1160                                         min_feed_div = feedback_div + 1;
1161                                 else
1162                                         max_feed_div = feedback_div;
1163                         }
1164                 }
1165         }
1166
1167         *dot_clock_p = best_freq / 10000;
1168         *fb_div_p = best_feedback_div;
1169         *frac_fb_div_p = best_frac_feedback_div;
1170         *ref_div_p = best_ref_div;
1171         *post_div_p = best_post_div;
1172         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1173                       (long long)freq,
1174                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1175                       best_ref_div, best_post_div);
1176
1177 }
1178
1179 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1180 {
1181         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1182
1183         if (radeon_fb->obj) {
1184                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1185         }
1186         drm_framebuffer_cleanup(fb);
1187         kfree(radeon_fb);
1188 }
1189
1190 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1191                                                   struct drm_file *file_priv,
1192                                                   unsigned int *handle)
1193 {
1194         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1195
1196         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1197 }
1198
1199 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1200         .destroy = radeon_user_framebuffer_destroy,
1201         .create_handle = radeon_user_framebuffer_create_handle,
1202 };
1203
1204 int
1205 radeon_framebuffer_init(struct drm_device *dev,
1206                         struct radeon_framebuffer *rfb,
1207                         struct drm_mode_fb_cmd2 *mode_cmd,
1208                         struct drm_gem_object *obj)
1209 {
1210         int ret;
1211         rfb->obj = obj;
1212         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1213         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1214         if (ret) {
1215                 rfb->obj = NULL;
1216                 return ret;
1217         }
1218         return 0;
1219 }
1220
1221 static struct drm_framebuffer *
1222 radeon_user_framebuffer_create(struct drm_device *dev,
1223                                struct drm_file *file_priv,
1224                                struct drm_mode_fb_cmd2 *mode_cmd)
1225 {
1226         struct drm_gem_object *obj;
1227         struct radeon_framebuffer *radeon_fb;
1228         int ret;
1229
1230         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1231         if (obj ==  NULL) {
1232                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1233                         "can't create framebuffer\n", mode_cmd->handles[0]);
1234                 return ERR_PTR(-ENOENT);
1235         }
1236
1237         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1238         if (radeon_fb == NULL) {
1239                 drm_gem_object_unreference_unlocked(obj);
1240                 return ERR_PTR(-ENOMEM);
1241         }
1242
1243         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1244         if (ret) {
1245                 kfree(radeon_fb);
1246                 drm_gem_object_unreference_unlocked(obj);
1247                 return ERR_PTR(ret);
1248         }
1249
1250         return &radeon_fb->base;
1251 }
1252
1253 static void radeon_output_poll_changed(struct drm_device *dev)
1254 {
1255         struct radeon_device *rdev = dev->dev_private;
1256         radeon_fb_output_poll_changed(rdev);
1257 }
1258
1259 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1260         .fb_create = radeon_user_framebuffer_create,
1261         .output_poll_changed = radeon_output_poll_changed
1262 };
1263
1264 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1265 {       { 0, "driver" },
1266         { 1, "bios" },
1267 };
1268
1269 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1270 {       { TV_STD_NTSC, "ntsc" },
1271         { TV_STD_PAL, "pal" },
1272         { TV_STD_PAL_M, "pal-m" },
1273         { TV_STD_PAL_60, "pal-60" },
1274         { TV_STD_NTSC_J, "ntsc-j" },
1275         { TV_STD_SCART_PAL, "scart-pal" },
1276         { TV_STD_PAL_CN, "pal-cn" },
1277         { TV_STD_SECAM, "secam" },
1278 };
1279
1280 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1281 {       { UNDERSCAN_OFF, "off" },
1282         { UNDERSCAN_ON, "on" },
1283         { UNDERSCAN_AUTO, "auto" },
1284 };
1285
1286 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1287 {       { RADEON_AUDIO_DISABLE, "off" },
1288         { RADEON_AUDIO_ENABLE, "on" },
1289         { RADEON_AUDIO_AUTO, "auto" },
1290 };
1291
1292 /* XXX support different dither options? spatial, temporal, both, etc. */
1293 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1294 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1295         { RADEON_FMT_DITHER_ENABLE, "on" },
1296 };
1297
1298 static int radeon_modeset_create_props(struct radeon_device *rdev)
1299 {
1300         int sz;
1301
1302         if (rdev->is_atom_bios) {
1303                 rdev->mode_info.coherent_mode_property =
1304                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1305                 if (!rdev->mode_info.coherent_mode_property)
1306                         return -ENOMEM;
1307         }
1308
1309         if (!ASIC_IS_AVIVO(rdev)) {
1310                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1311                 rdev->mode_info.tmds_pll_property =
1312                         drm_property_create_enum(rdev->ddev, 0,
1313                                             "tmds_pll",
1314                                             radeon_tmds_pll_enum_list, sz);
1315         }
1316
1317         rdev->mode_info.load_detect_property =
1318                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1319         if (!rdev->mode_info.load_detect_property)
1320                 return -ENOMEM;
1321
1322         drm_mode_create_scaling_mode_property(rdev->ddev);
1323
1324         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1325         rdev->mode_info.tv_std_property =
1326                 drm_property_create_enum(rdev->ddev, 0,
1327                                     "tv standard",
1328                                     radeon_tv_std_enum_list, sz);
1329
1330         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1331         rdev->mode_info.underscan_property =
1332                 drm_property_create_enum(rdev->ddev, 0,
1333                                     "underscan",
1334                                     radeon_underscan_enum_list, sz);
1335
1336         rdev->mode_info.underscan_hborder_property =
1337                 drm_property_create_range(rdev->ddev, 0,
1338                                         "underscan hborder", 0, 128);
1339         if (!rdev->mode_info.underscan_hborder_property)
1340                 return -ENOMEM;
1341
1342         rdev->mode_info.underscan_vborder_property =
1343                 drm_property_create_range(rdev->ddev, 0,
1344                                         "underscan vborder", 0, 128);
1345         if (!rdev->mode_info.underscan_vborder_property)
1346                 return -ENOMEM;
1347
1348         sz = ARRAY_SIZE(radeon_audio_enum_list);
1349         rdev->mode_info.audio_property =
1350                 drm_property_create_enum(rdev->ddev, 0,
1351                                          "audio",
1352                                          radeon_audio_enum_list, sz);
1353
1354         sz = ARRAY_SIZE(radeon_dither_enum_list);
1355         rdev->mode_info.dither_property =
1356                 drm_property_create_enum(rdev->ddev, 0,
1357                                          "dither",
1358                                          radeon_dither_enum_list, sz);
1359
1360         return 0;
1361 }
1362
1363 void radeon_update_display_priority(struct radeon_device *rdev)
1364 {
1365         /* adjustment options for the display watermarks */
1366         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1367                 /* set display priority to high for r3xx, rv515 chips
1368                  * this avoids flickering due to underflow to the
1369                  * display controllers during heavy acceleration.
1370                  * Don't force high on rs4xx igp chips as it seems to
1371                  * affect the sound card.  See kernel bug 15982.
1372                  */
1373                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1374                     !(rdev->flags & RADEON_IS_IGP))
1375                         rdev->disp_priority = 2;
1376                 else
1377                         rdev->disp_priority = 0;
1378         } else
1379                 rdev->disp_priority = radeon_disp_priority;
1380
1381 }
1382
1383 /*
1384  * Allocate hdmi structs and determine register offsets
1385  */
1386 static void radeon_afmt_init(struct radeon_device *rdev)
1387 {
1388         int i;
1389
1390         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1391                 rdev->mode_info.afmt[i] = NULL;
1392
1393         if (ASIC_IS_NODCE(rdev)) {
1394                 /* nothing to do */
1395         } else if (ASIC_IS_DCE4(rdev)) {
1396                 static uint32_t eg_offsets[] = {
1397                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1398                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1399                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1400                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1401                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1402                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1403                         0x13830 - 0x7030,
1404                 };
1405                 int num_afmt;
1406
1407                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1408                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1409                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1410                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1411                 if (ASIC_IS_DCE8(rdev))
1412                         num_afmt = 7;
1413                 else if (ASIC_IS_DCE6(rdev))
1414                         num_afmt = 6;
1415                 else if (ASIC_IS_DCE5(rdev))
1416                         num_afmt = 6;
1417                 else if (ASIC_IS_DCE41(rdev))
1418                         num_afmt = 2;
1419                 else /* DCE4 */
1420                         num_afmt = 6;
1421
1422                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1423                 for (i = 0; i < num_afmt; i++) {
1424                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1425                         if (rdev->mode_info.afmt[i]) {
1426                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1427                                 rdev->mode_info.afmt[i]->id = i;
1428                         }
1429                 }
1430         } else if (ASIC_IS_DCE3(rdev)) {
1431                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1432                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1433                 if (rdev->mode_info.afmt[0]) {
1434                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1435                         rdev->mode_info.afmt[0]->id = 0;
1436                 }
1437                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1438                 if (rdev->mode_info.afmt[1]) {
1439                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1440                         rdev->mode_info.afmt[1]->id = 1;
1441                 }
1442         } else if (ASIC_IS_DCE2(rdev)) {
1443                 /* DCE2 has at least 1 routable audio block */
1444                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1445                 if (rdev->mode_info.afmt[0]) {
1446                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1447                         rdev->mode_info.afmt[0]->id = 0;
1448                 }
1449                 /* r6xx has 2 routable audio blocks */
1450                 if (rdev->family >= CHIP_R600) {
1451                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1452                         if (rdev->mode_info.afmt[1]) {
1453                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1454                                 rdev->mode_info.afmt[1]->id = 1;
1455                         }
1456                 }
1457         }
1458 }
1459
1460 static void radeon_afmt_fini(struct radeon_device *rdev)
1461 {
1462         int i;
1463
1464         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1465                 kfree(rdev->mode_info.afmt[i]);
1466                 rdev->mode_info.afmt[i] = NULL;
1467         }
1468 }
1469
1470 int radeon_modeset_init(struct radeon_device *rdev)
1471 {
1472         int i;
1473         int ret;
1474
1475         drm_mode_config_init(rdev->ddev);
1476         rdev->mode_info.mode_config_initialized = true;
1477
1478         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1479
1480         if (ASIC_IS_DCE5(rdev)) {
1481                 rdev->ddev->mode_config.max_width = 16384;
1482                 rdev->ddev->mode_config.max_height = 16384;
1483         } else if (ASIC_IS_AVIVO(rdev)) {
1484                 rdev->ddev->mode_config.max_width = 8192;
1485                 rdev->ddev->mode_config.max_height = 8192;
1486         } else {
1487                 rdev->ddev->mode_config.max_width = 4096;
1488                 rdev->ddev->mode_config.max_height = 4096;
1489         }
1490
1491         rdev->ddev->mode_config.preferred_depth = 24;
1492         rdev->ddev->mode_config.prefer_shadow = 1;
1493
1494         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1495
1496         ret = radeon_modeset_create_props(rdev);
1497         if (ret) {
1498                 return ret;
1499         }
1500
1501         /* init i2c buses */
1502         radeon_i2c_init(rdev);
1503
1504         /* check combios for a valid hardcoded EDID - Sun servers */
1505         if (!rdev->is_atom_bios) {
1506                 /* check for hardcoded EDID in BIOS */
1507                 radeon_combios_check_hardcoded_edid(rdev);
1508         }
1509
1510         /* allocate crtcs */
1511         for (i = 0; i < rdev->num_crtc; i++) {
1512                 radeon_crtc_init(rdev->ddev, i);
1513         }
1514
1515         /* okay we should have all the bios connectors */
1516         ret = radeon_setup_enc_conn(rdev->ddev);
1517         if (!ret) {
1518                 return ret;
1519         }
1520
1521         /* init dig PHYs, disp eng pll */
1522         if (rdev->is_atom_bios) {
1523                 radeon_atom_encoder_init(rdev);
1524                 radeon_atom_disp_eng_pll_init(rdev);
1525         }
1526
1527         /* initialize hpd */
1528         radeon_hpd_init(rdev);
1529
1530         /* setup afmt */
1531         radeon_afmt_init(rdev);
1532
1533         radeon_fbdev_init(rdev);
1534         drm_kms_helper_poll_init(rdev->ddev);
1535
1536         if (rdev->pm.dpm_enabled) {
1537                 /* do dpm late init */
1538                 ret = radeon_pm_late_init(rdev);
1539                 if (ret) {
1540                         rdev->pm.dpm_enabled = false;
1541                         DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1542                 }
1543                 /* set the dpm state for PX since there won't be
1544                  * a modeset to call this.
1545                  */
1546                 radeon_pm_compute_clocks(rdev);
1547         }
1548
1549         return 0;
1550 }
1551
1552 void radeon_modeset_fini(struct radeon_device *rdev)
1553 {
1554         radeon_fbdev_fini(rdev);
1555         kfree(rdev->mode_info.bios_hardcoded_edid);
1556
1557         if (rdev->mode_info.mode_config_initialized) {
1558                 radeon_afmt_fini(rdev);
1559                 drm_kms_helper_poll_fini(rdev->ddev);
1560                 radeon_hpd_fini(rdev);
1561                 drm_mode_config_cleanup(rdev->ddev);
1562                 rdev->mode_info.mode_config_initialized = false;
1563         }
1564         /* free i2c buses */
1565         radeon_i2c_fini(rdev);
1566 }
1567
1568 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1569 {
1570         /* try and guess if this is a tv or a monitor */
1571         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1572             (mode->vdisplay == 576) || /* 576p */
1573             (mode->vdisplay == 720) || /* 720p */
1574             (mode->vdisplay == 1080)) /* 1080p */
1575                 return true;
1576         else
1577                 return false;
1578 }
1579
1580 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1581                                 const struct drm_display_mode *mode,
1582                                 struct drm_display_mode *adjusted_mode)
1583 {
1584         struct drm_device *dev = crtc->dev;
1585         struct radeon_device *rdev = dev->dev_private;
1586         struct drm_encoder *encoder;
1587         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1588         struct radeon_encoder *radeon_encoder;
1589         struct drm_connector *connector;
1590         struct radeon_connector *radeon_connector;
1591         bool first = true;
1592         u32 src_v = 1, dst_v = 1;
1593         u32 src_h = 1, dst_h = 1;
1594
1595         radeon_crtc->h_border = 0;
1596         radeon_crtc->v_border = 0;
1597
1598         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1599                 if (encoder->crtc != crtc)
1600                         continue;
1601                 radeon_encoder = to_radeon_encoder(encoder);
1602                 connector = radeon_get_connector_for_encoder(encoder);
1603                 radeon_connector = to_radeon_connector(connector);
1604
1605                 if (first) {
1606                         /* set scaling */
1607                         if (radeon_encoder->rmx_type == RMX_OFF)
1608                                 radeon_crtc->rmx_type = RMX_OFF;
1609                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1610                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1611                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1612                         else
1613                                 radeon_crtc->rmx_type = RMX_OFF;
1614                         /* copy native mode */
1615                         memcpy(&radeon_crtc->native_mode,
1616                                &radeon_encoder->native_mode,
1617                                 sizeof(struct drm_display_mode));
1618                         src_v = crtc->mode.vdisplay;
1619                         dst_v = radeon_crtc->native_mode.vdisplay;
1620                         src_h = crtc->mode.hdisplay;
1621                         dst_h = radeon_crtc->native_mode.hdisplay;
1622
1623                         /* fix up for overscan on hdmi */
1624                         if (ASIC_IS_AVIVO(rdev) &&
1625                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1626                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1627                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1628                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1629                               is_hdtv_mode(mode)))) {
1630                                 if (radeon_encoder->underscan_hborder != 0)
1631                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1632                                 else
1633                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1634                                 if (radeon_encoder->underscan_vborder != 0)
1635                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1636                                 else
1637                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1638                                 radeon_crtc->rmx_type = RMX_FULL;
1639                                 src_v = crtc->mode.vdisplay;
1640                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1641                                 src_h = crtc->mode.hdisplay;
1642                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1643                         }
1644                         first = false;
1645                 } else {
1646                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1647                                 /* WARNING: Right now this can't happen but
1648                                  * in the future we need to check that scaling
1649                                  * are consistent across different encoder
1650                                  * (ie all encoder can work with the same
1651                                  *  scaling).
1652                                  */
1653                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1654                                 return false;
1655                         }
1656                 }
1657         }
1658         if (radeon_crtc->rmx_type != RMX_OFF) {
1659                 fixed20_12 a, b;
1660                 a.full = dfixed_const(src_v);
1661                 b.full = dfixed_const(dst_v);
1662                 radeon_crtc->vsc.full = dfixed_div(a, b);
1663                 a.full = dfixed_const(src_h);
1664                 b.full = dfixed_const(dst_h);
1665                 radeon_crtc->hsc.full = dfixed_div(a, b);
1666         } else {
1667                 radeon_crtc->vsc.full = dfixed_const(1);
1668                 radeon_crtc->hsc.full = dfixed_const(1);
1669         }
1670         return true;
1671 }
1672
1673 /*
1674  * Retrieve current video scanout position of crtc on a given gpu, and
1675  * an optional accurate timestamp of when query happened.
1676  *
1677  * \param dev Device to query.
1678  * \param crtc Crtc to query.
1679  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1680  * \param *vpos Location where vertical scanout position should be stored.
1681  * \param *hpos Location where horizontal scanout position should go.
1682  * \param *stime Target location for timestamp taken immediately before
1683  *               scanout position query. Can be NULL to skip timestamp.
1684  * \param *etime Target location for timestamp taken immediately after
1685  *               scanout position query. Can be NULL to skip timestamp.
1686  *
1687  * Returns vpos as a positive number while in active scanout area.
1688  * Returns vpos as a negative number inside vblank, counting the number
1689  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1690  * until start of active scanout / end of vblank."
1691  *
1692  * \return Flags, or'ed together as follows:
1693  *
1694  * DRM_SCANOUTPOS_VALID = Query successful.
1695  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1696  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1697  * this flag means that returned position may be offset by a constant but
1698  * unknown small number of scanlines wrt. real scanout position.
1699  *
1700  */
1701 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1702                                int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1703 {
1704         u32 stat_crtc = 0, vbl = 0, position = 0;
1705         int vbl_start, vbl_end, vtotal, ret = 0;
1706         bool in_vbl = true;
1707
1708         struct radeon_device *rdev = dev->dev_private;
1709
1710         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1711
1712         /* Get optional system timestamp before query. */
1713         if (stime)
1714                 *stime = ktime_get();
1715
1716         if (ASIC_IS_DCE4(rdev)) {
1717                 if (crtc == 0) {
1718                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1719                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1720                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1721                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1722                         ret |= DRM_SCANOUTPOS_VALID;
1723                 }
1724                 if (crtc == 1) {
1725                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1726                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1727                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1728                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1729                         ret |= DRM_SCANOUTPOS_VALID;
1730                 }
1731                 if (crtc == 2) {
1732                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1733                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1734                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1735                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1736                         ret |= DRM_SCANOUTPOS_VALID;
1737                 }
1738                 if (crtc == 3) {
1739                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1740                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1741                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1742                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1743                         ret |= DRM_SCANOUTPOS_VALID;
1744                 }
1745                 if (crtc == 4) {
1746                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1747                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1748                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1749                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1750                         ret |= DRM_SCANOUTPOS_VALID;
1751                 }
1752                 if (crtc == 5) {
1753                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1754                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1755                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1756                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1757                         ret |= DRM_SCANOUTPOS_VALID;
1758                 }
1759         } else if (ASIC_IS_AVIVO(rdev)) {
1760                 if (crtc == 0) {
1761                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1762                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1763                         ret |= DRM_SCANOUTPOS_VALID;
1764                 }
1765                 if (crtc == 1) {
1766                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1767                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1768                         ret |= DRM_SCANOUTPOS_VALID;
1769                 }
1770         } else {
1771                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1772                 if (crtc == 0) {
1773                         /* Assume vbl_end == 0, get vbl_start from
1774                          * upper 16 bits.
1775                          */
1776                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1777                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1778                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1779                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1780                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1781                         if (!(stat_crtc & 1))
1782                                 in_vbl = false;
1783
1784                         ret |= DRM_SCANOUTPOS_VALID;
1785                 }
1786                 if (crtc == 1) {
1787                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1788                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1789                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1790                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1791                         if (!(stat_crtc & 1))
1792                                 in_vbl = false;
1793
1794                         ret |= DRM_SCANOUTPOS_VALID;
1795                 }
1796         }
1797
1798         /* Get optional system timestamp after query. */
1799         if (etime)
1800                 *etime = ktime_get();
1801
1802         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1803
1804         /* Decode into vertical and horizontal scanout position. */
1805         *vpos = position & 0x1fff;
1806         *hpos = (position >> 16) & 0x1fff;
1807
1808         /* Valid vblank area boundaries from gpu retrieved? */
1809         if (vbl > 0) {
1810                 /* Yes: Decode. */
1811                 ret |= DRM_SCANOUTPOS_ACCURATE;
1812                 vbl_start = vbl & 0x1fff;
1813                 vbl_end = (vbl >> 16) & 0x1fff;
1814         }
1815         else {
1816                 /* No: Fake something reasonable which gives at least ok results. */
1817                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1818                 vbl_end = 0;
1819         }
1820
1821         /* Test scanout position against vblank region. */
1822         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1823                 in_vbl = false;
1824
1825         /* Check if inside vblank area and apply corrective offsets:
1826          * vpos will then be >=0 in video scanout area, but negative
1827          * within vblank area, counting down the number of lines until
1828          * start of scanout.
1829          */
1830
1831         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1832         if (in_vbl && (*vpos >= vbl_start)) {
1833                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1834                 *vpos = *vpos - vtotal;
1835         }
1836
1837         /* Correct for shifted end of vbl at vbl_end. */
1838         *vpos = *vpos - vbl_end;
1839
1840         /* In vblank? */
1841         if (in_vbl)
1842                 ret |= DRM_SCANOUTPOS_INVBL;
1843
1844         /* Is vpos outside nominal vblank area, but less than
1845          * 1/100 of a frame height away from start of vblank?
1846          * If so, assume this isn't a massively delayed vblank
1847          * interrupt, but a vblank interrupt that fired a few
1848          * microseconds before true start of vblank. Compensate
1849          * by adding a full frame duration to the final timestamp.
1850          * Happens, e.g., on ATI R500, R600.
1851          *
1852          * We only do this if DRM_CALLED_FROM_VBLIRQ.
1853          */
1854         if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1855                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1856                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1857
1858                 if (vbl_start - *vpos < vtotal / 100) {
1859                         *vpos -= vtotal;
1860
1861                         /* Signal this correction as "applied". */
1862                         ret |= 0x8;
1863                 }
1864         }
1865
1866         return ret;
1867 }