drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <linux/pm_runtime.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_plane_helper.h>
  36 #include <drm/drm_edid.h>
  37
  38 #include <linux/gcd.h>
  39
  40 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  41 {
  42         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  43         struct drm_device *dev = crtc->dev;
  44         struct radeon_device *rdev = dev->dev_private;
  45         int i;
  46
  47         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  48         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  49
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  51         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  52         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  53
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  55         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  56         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  57
  58         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  59         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  60         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  61
  62         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  63         for (i = 0; i < 256; i++) {
  64                 WREG32(AVIVO_DC_LUT_30_COLOR,
  65                              (radeon_crtc->lut_r[i] << 20) |
  66                              (radeon_crtc->lut_g[i] << 10) |
  67                              (radeon_crtc->lut_b[i] << 0));
  68         }
  69
  70         /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
  71         WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
  72 }
  73
  74 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  75 {
  76         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  77         struct drm_device *dev = crtc->dev;
  78         struct radeon_device *rdev = dev->dev_private;
  79         int i;
  80
  81         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  82         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  83
  84         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  85         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  86         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  87
  88         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  89         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  90         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  91
  92         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  93         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  94
  95         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  96         for (i = 0; i < 256; i++) {
  97                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  98                        (radeon_crtc->lut_r[i] << 20) |
  99                        (radeon_crtc->lut_g[i] << 10) |
 100                        (radeon_crtc->lut_b[i] << 0));
 101         }
 102 }
 103
 104 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 105 {
 106         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 107         struct drm_device *dev = crtc->dev;
 108         struct radeon_device *rdev = dev->dev_private;
 109         int i;
 110
 111         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 112
 113         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 114                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 115                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 116         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 117                NI_GRPH_PRESCALE_BYPASS);
 118         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 119                NI_OVL_PRESCALE_BYPASS);
 120         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 121                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 122                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 123
 124         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 125
 126         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 127         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 128         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 129
 130         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 131         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 132         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 133
 134         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 135         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 136
 137         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 138         for (i = 0; i < 256; i++) {
 139                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 140                        (radeon_crtc->lut_r[i] << 20) |
 141                        (radeon_crtc->lut_g[i] << 10) |
 142                        (radeon_crtc->lut_b[i] << 0));
 143         }
 144
 145         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 146                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 147                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 148                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 149                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 150         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 151                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 152                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 153         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 154                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 155                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 156         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 157                (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
 158                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 159         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 160         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 161         if (ASIC_IS_DCE8(rdev)) {
 162                 /* XXX this only needs to be programmed once per crtc at startup,
 163                  * not sure where the best place for it is
 164                  */
 165                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 166                        CIK_CURSOR_ALPHA_BLND_ENA);
 167         }
 168 }
 169
 170 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 171 {
 172         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 173         struct drm_device *dev = crtc->dev;
 174         struct radeon_device *rdev = dev->dev_private;
 175         int i;
 176         uint32_t dac2_cntl;
 177
 178         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 179         if (radeon_crtc->crtc_id == 0)
 180                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 181         else
 182                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 183         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 184
 185         WREG8(RADEON_PALETTE_INDEX, 0);
 186         for (i = 0; i < 256; i++) {
 187                 WREG32(RADEON_PALETTE_30_DATA,
 188                              (radeon_crtc->lut_r[i] << 20) |
 189                              (radeon_crtc->lut_g[i] << 10) |
 190                              (radeon_crtc->lut_b[i] << 0));
 191         }
 192 }
 193
 194 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 195 {
 196         struct drm_device *dev = crtc->dev;
 197         struct radeon_device *rdev = dev->dev_private;
 198
 199         if (!crtc->enabled)
 200                 return;
 201
 202         if (ASIC_IS_DCE5(rdev))
 203                 dce5_crtc_load_lut(crtc);
 204         else if (ASIC_IS_DCE4(rdev))
 205                 dce4_crtc_load_lut(crtc);
 206         else if (ASIC_IS_AVIVO(rdev))
 207                 avivo_crtc_load_lut(crtc);
 208         else
 209                 legacy_crtc_load_lut(crtc);
 210 }
 211
 212 /** Sets the color ramps on behalf of fbcon */
 213 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 214                               u16 blue, int regno)
 215 {
 216         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 217
 218         radeon_crtc->lut_r[regno] = red >> 6;
 219         radeon_crtc->lut_g[regno] = green >> 6;
 220         radeon_crtc->lut_b[regno] = blue >> 6;
 221 }
 222
 223 /** Gets the color ramps on behalf of fbcon */
 224 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 225                               u16 *blue, int regno)
 226 {
 227         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 228
 229         *red = radeon_crtc->lut_r[regno] << 6;
 230         *green = radeon_crtc->lut_g[regno] << 6;
 231         *blue = radeon_crtc->lut_b[regno] << 6;
 232 }
 233
 234 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 235                                  u16 *blue, uint32_t size)
 236 {
 237         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 238         int i;
 239
 240         /* userspace palettes are always correct as is */
 241         for (i = 0; i < size; i++) {
 242                 radeon_crtc->lut_r[i] = red[i] >> 6;
 243                 radeon_crtc->lut_g[i] = green[i] >> 6;
 244                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 245         }
 246         radeon_crtc_load_lut(crtc);
 247
 248         return 0;
 249 }
 250
 251 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 252 {
 253         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 254
 255         drm_crtc_cleanup(crtc);
 256         destroy_workqueue(radeon_crtc->flip_queue);
 257         kfree(radeon_crtc);
 258 }
 259
 260 /**
 261  * radeon_unpin_work_func - unpin old buffer object
 262  *
 263  * @__work - kernel work item
 264  *
 265  * Unpin the old frame buffer object outside of the interrupt handler
 266  */
 267 static void radeon_unpin_work_func(struct work_struct *__work)
 268 {
 269         struct radeon_flip_work *work =
 270                 container_of(__work, struct radeon_flip_work, unpin_work);
 271         int r;
 272
 273         /* unpin of the old buffer */
 274         r = radeon_bo_reserve(work->old_rbo, false);
 275         if (likely(r == 0)) {
 276                 r = radeon_bo_unpin(work->old_rbo);
 277                 if (unlikely(r != 0)) {
 278                         DRM_ERROR("failed to unpin buffer after flip\n");
 279                 }
 280                 radeon_bo_unreserve(work->old_rbo);
 281         } else
 282                 DRM_ERROR("failed to reserve buffer after flip\n");
 283
 284         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 285         kfree(work);
 286 }
 287
 288 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
 289 {
 290         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 291         unsigned long flags;
 292         u32 update_pending;
 293         int vpos, hpos;
 294
 295         /* can happen during initialization */
 296         if (radeon_crtc == NULL)
 297                 return;
 298
 299         /* Skip the pageflip completion check below (based on polling) on
 300          * asics which reliably support hw pageflip completion irqs. pflip
 301          * irqs are a reliable and race-free method of handling pageflip
 302          * completion detection. A use_pflipirq module parameter < 2 allows
 303          * to override this in case of asics with faulty pflip irqs.
 304          * A module parameter of 0 would only use this polling based path,
 305          * a parameter of 1 would use pflip irq only as a backup to this
 306          * path, as in Linux 3.16.
 307          */
 308         if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
 309                 return;
 310
 311         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 312         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 313                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 314                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 315                                  radeon_crtc->flip_status,
 316                                  RADEON_FLIP_SUBMITTED);
 317                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 318                 return;
 319         }
 320
 321         update_pending = radeon_page_flip_pending(rdev, crtc_id);
 322
 323         /* Has the pageflip already completed in crtc, or is it certain
 324          * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
 325          * distance to start of "fudged earlier" vblank in vpos, distance to
 326          * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
 327          * the last few scanlines before start of real vblank, where the vblank
 328          * irq can fire, so we have sampled update_pending a bit too early and
 329          * know the flip will complete at leading edge of the upcoming real
 330          * vblank. On pre-AVIVO hardware, flips also complete inside the real
 331          * vblank, not only at leading edge, so if update_pending for hpos >= 0
 332          *  == inside real vblank, the flip will complete almost immediately.
 333          * Note that this method of completion handling is still not 100% race
 334          * free, as we could execute before the radeon_flip_work_func managed
 335          * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
 336          * but the flip still gets programmed into hw and completed during
 337          * vblank, leading to a delayed emission of the flip completion event.
 338          * This applies at least to pre-AVIVO hardware, where flips are always
 339          * completing inside vblank, not only at leading edge of vblank.
 340          */
 341         if (update_pending &&
 342             (DRM_SCANOUTPOS_VALID &
 343              radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 344                                         GET_DISTANCE_TO_VBLANKSTART,
 345                                         &vpos, &hpos, NULL, NULL,
 346                                         &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
 347             ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
 348                 /* crtc didn't flip in this target vblank interval,
 349                  * but flip is pending in crtc. Based on the current
 350                  * scanout position we know that the current frame is
 351                  * (nearly) complete and the flip will (likely)
 352                  * complete before the start of the next frame.
 353                  */
 354                 update_pending = 0;
 355         }
 356         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 357         if (!update_pending)
 358                 radeon_crtc_handle_flip(rdev, crtc_id);
 359 }
 360
 361 /**
 362  * radeon_crtc_handle_flip - page flip completed
 363  *
 364  * @rdev: radeon device pointer
 365  * @crtc_id: crtc number this event is for
 366  *
 367  * Called when we are sure that a page flip for this crtc is completed.
 368  */
 369 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 370 {
 371         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 372         struct radeon_flip_work *work;
 373         unsigned long flags;
 374
 375         /* this can happen at init */
 376         if (radeon_crtc == NULL)
 377                 return;
 378
 379         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 380         work = radeon_crtc->flip_work;
 381         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 382                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 383                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 384                                  radeon_crtc->flip_status,
 385                                  RADEON_FLIP_SUBMITTED);
 386                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 387                 return;
 388         }
 389
 390         /* Pageflip completed. Clean up. */
 391         radeon_crtc->flip_status = RADEON_FLIP_NONE;
 392         radeon_crtc->flip_work = NULL;
 393
 394         /* wakeup userspace */
 395         if (work->event)
 396                 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
 397
 398         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 399
 400         drm_crtc_vblank_put(&radeon_crtc->base);
 401         radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
 402         queue_work(radeon_crtc->flip_queue, &work->unpin_work);
 403 }
 404
 405 /**
 406  * radeon_flip_work_func - page flip framebuffer
 407  *
 408  * @work - kernel work item
 409  *
 410  * Wait for the buffer object to become idle and do the actual page flip
 411  */
 412 static void radeon_flip_work_func(struct work_struct *__work)
 413 {
 414         struct radeon_flip_work *work =
 415                 container_of(__work, struct radeon_flip_work, flip_work);
 416         struct radeon_device *rdev = work->rdev;
 417         struct drm_device *dev = rdev->ddev;
 418         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
 419
 420         struct drm_crtc *crtc = &radeon_crtc->base;
 421         unsigned long flags;
 422         int r;
 423         int vpos, hpos;
 424
 425         down_read(&rdev->exclusive_lock);
 426         if (work->fence) {
 427                 struct radeon_fence *fence;
 428
 429                 fence = to_radeon_fence(work->fence);
 430                 if (fence && fence->rdev == rdev) {
 431                         r = radeon_fence_wait(fence, false);
 432                         if (r == -EDEADLK) {
 433                                 up_read(&rdev->exclusive_lock);
 434                                 do {
 435                                         r = radeon_gpu_reset(rdev);
 436                                 } while (r == -EAGAIN);
 437                                 down_read(&rdev->exclusive_lock);
 438                         }
 439                 } else
 440                         r = fence_wait(work->fence, false);
 441
 442                 if (r)
 443                         DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
 444
 445                 /* We continue with the page flip even if we failed to wait on
 446                  * the fence, otherwise the DRM core and userspace will be
 447                  * confused about which BO the CRTC is scanning out
 448                  */
 449
 450                 fence_put(work->fence);
 451                 work->fence = NULL;
 452         }
 453
 454         /* Wait until we're out of the vertical blank period before the one
 455          * targeted by the flip
 456          */
 457         while (radeon_crtc->enabled &&
 458                (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
 459                                            &vpos, &hpos, NULL, NULL,
 460                                            &crtc->hwmode)
 461                 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 462                (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 463                (int)(work->target_vblank -
 464                      dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0)
 465                 usleep_range(1000, 2000);
 466
 467         /* We borrow the event spin lock for protecting flip_status */
 468         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 469
 470         /* set the proper interrupt */
 471         radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
 472
 473         /* do the flip (mmio) */
 474         radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
 475
 476         radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
 477         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 478         up_read(&rdev->exclusive_lock);
 479 }
 480
 481 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
 482                                         struct drm_framebuffer *fb,
 483                                         struct drm_pending_vblank_event *event,
 484                                         uint32_t page_flip_flags,
 485                                         uint32_t target)
 486 {
 487         struct drm_device *dev = crtc->dev;
 488         struct radeon_device *rdev = dev->dev_private;
 489         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 490         struct radeon_framebuffer *old_radeon_fb;
 491         struct radeon_framebuffer *new_radeon_fb;
 492         struct drm_gem_object *obj;
 493         struct radeon_flip_work *work;
 494         struct radeon_bo *new_rbo;
 495         uint32_t tiling_flags, pitch_pixels;
 496         uint64_t base;
 497         unsigned long flags;
 498         int r;
 499
 500         work = kzalloc(sizeof *work, GFP_KERNEL);
 501         if (work == NULL)
 502                 return -ENOMEM;
 503
 504         INIT_WORK(&work->flip_work, radeon_flip_work_func);
 505         INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
 506
 507         work->rdev = rdev;
 508         work->crtc_id = radeon_crtc->crtc_id;
 509         work->event = event;
 510         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 511
 512         /* schedule unpin of the old buffer */
 513         old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 514         obj = old_radeon_fb->obj;
 515
 516         /* take a reference to the old object */
 517         drm_gem_object_reference(obj);
 518         work->old_rbo = gem_to_radeon_bo(obj);
 519
 520         new_radeon_fb = to_radeon_framebuffer(fb);
 521         obj = new_radeon_fb->obj;
 522         new_rbo = gem_to_radeon_bo(obj);
 523
 524         /* pin the new buffer */
 525         DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
 526                          work->old_rbo, new_rbo);
 527
 528         r = radeon_bo_reserve(new_rbo, false);
 529         if (unlikely(r != 0)) {
 530                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 531                 goto cleanup;
 532         }
 533         /* Only 27 bit offset for legacy CRTC */
 534         r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
 535                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 536         if (unlikely(r != 0)) {
 537                 radeon_bo_unreserve(new_rbo);
 538                 r = -EINVAL;
 539                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 540                 goto cleanup;
 541         }
 542         work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
 543         radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
 544         radeon_bo_unreserve(new_rbo);
 545
 546         if (!ASIC_IS_AVIVO(rdev)) {
 547                 /* crtc offset is from display base addr not FB location */
 548                 base -= radeon_crtc->legacy_display_base_addr;
 549                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 550
 551                 if (tiling_flags & RADEON_TILING_MACRO) {
 552                         if (ASIC_IS_R300(rdev)) {
 553                                 base &= ~0x7ff;
 554                         } else {
 555                                 int byteshift = fb->bits_per_pixel >> 4;
 556                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 557                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 558                         }
 559                 } else {
 560                         int offset = crtc->y * pitch_pixels + crtc->x;
 561                         switch (fb->bits_per_pixel) {
 562                         case 8:
 563                         default:
 564                                 offset *= 1;
 565                                 break;
 566                         case 15:
 567                         case 16:
 568                                 offset *= 2;
 569                                 break;
 570                         case 24:
 571                                 offset *= 3;
 572                                 break;
 573                         case 32:
 574                                 offset *= 4;
 575                                 break;
 576                         }
 577                         base += offset;
 578                 }
 579                 base &= ~7;
 580         }
 581         work->base = base;
 582         work->target_vblank = target - drm_crtc_vblank_count(crtc) +
 583                 dev->driver->get_vblank_counter(dev, work->crtc_id);
 584
 585         /* We borrow the event spin lock for protecting flip_work */
 586         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 587
 588         if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
 589                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 590                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 591                 r = -EBUSY;
 592                 goto pflip_cleanup;
 593         }
 594         radeon_crtc->flip_status = RADEON_FLIP_PENDING;
 595         radeon_crtc->flip_work = work;
 596
 597         /* update crtc fb */
 598         crtc->primary->fb = fb;
 599
 600         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 601
 602         queue_work(radeon_crtc->flip_queue, &work->flip_work);
 603         return 0;
 604
 605 pflip_cleanup:
 606         if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
 607                 DRM_ERROR("failed to reserve new rbo in error path\n");
 608                 goto cleanup;
 609         }
 610         if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
 611                 DRM_ERROR("failed to unpin new rbo in error path\n");
 612         }
 613         radeon_bo_unreserve(new_rbo);
 614
 615 cleanup:
 616         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 617         fence_put(work->fence);
 618         kfree(work);
 619         return r;
 620 }
 621
 622 static int
 623 radeon_crtc_set_config(struct drm_mode_set *set)
 624 {
 625         struct drm_device *dev;
 626         struct radeon_device *rdev;
 627         struct drm_crtc *crtc;
 628         bool active = false;
 629         int ret;
 630
 631         if (!set || !set->crtc)
 632                 return -EINVAL;
 633
 634         dev = set->crtc->dev;
 635
 636         ret = pm_runtime_get_sync(dev->dev);
 637         if (ret < 0)
 638                 return ret;
 639
 640         ret = drm_crtc_helper_set_config(set);
 641
 642         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 643                 if (crtc->enabled)
 644                         active = true;
 645
 646         pm_runtime_mark_last_busy(dev->dev);
 647
 648         rdev = dev->dev_private;
 649         /* if we have active crtcs and we don't have a power ref,
 650            take the current one */
 651         if (active && !rdev->have_disp_power_ref) {
 652                 rdev->have_disp_power_ref = true;
 653                 return ret;
 654         }
 655         /* if we have no active crtcs, then drop the power ref
 656            we got before */
 657         if (!active && rdev->have_disp_power_ref) {
 658                 pm_runtime_put_autosuspend(dev->dev);
 659                 rdev->have_disp_power_ref = false;
 660         }
 661
 662         /* drop the power reference we got coming in here */
 663         pm_runtime_put_autosuspend(dev->dev);
 664         return ret;
 665 }
 666
 667 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 668         .cursor_set2 = radeon_crtc_cursor_set2,
 669         .cursor_move = radeon_crtc_cursor_move,
 670         .gamma_set = radeon_crtc_gamma_set,
 671         .set_config = radeon_crtc_set_config,
 672         .destroy = radeon_crtc_destroy,
 673         .page_flip_target = radeon_crtc_page_flip_target,
 674 };
 675
 676 static void radeon_crtc_init(struct drm_device *dev, int index)
 677 {
 678         struct radeon_device *rdev = dev->dev_private;
 679         struct radeon_crtc *radeon_crtc;
 680         int i;
 681
 682         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 683         if (radeon_crtc == NULL)
 684                 return;
 685
 686         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 687
 688         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 689         radeon_crtc->crtc_id = index;
 690         radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
 691         rdev->mode_info.crtcs[index] = radeon_crtc;
 692
 693         if (rdev->family >= CHIP_BONAIRE) {
 694                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 695                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 696         } else {
 697                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 698                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 699         }
 700         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 701         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 702
 703 #if 0
 704         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 705         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 706         radeon_crtc->mode_set.num_connectors = 0;
 707 #endif
 708
 709         for (i = 0; i < 256; i++) {
 710                 radeon_crtc->lut_r[i] = i << 2;
 711                 radeon_crtc->lut_g[i] = i << 2;
 712                 radeon_crtc->lut_b[i] = i << 2;
 713         }
 714
 715         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 716                 radeon_atombios_init_crtc(dev, radeon_crtc);
 717         else
 718                 radeon_legacy_init_crtc(dev, radeon_crtc);
 719 }
 720
 721 static const char *encoder_names[38] = {
 722         "NONE",
 723         "INTERNAL_LVDS",
 724         "INTERNAL_TMDS1",
 725         "INTERNAL_TMDS2",
 726         "INTERNAL_DAC1",
 727         "INTERNAL_DAC2",
 728         "INTERNAL_SDVOA",
 729         "INTERNAL_SDVOB",
 730         "SI170B",
 731         "CH7303",
 732         "CH7301",
 733         "INTERNAL_DVO1",
 734         "EXTERNAL_SDVOA",
 735         "EXTERNAL_SDVOB",
 736         "TITFP513",
 737         "INTERNAL_LVTM1",
 738         "VT1623",
 739         "HDMI_SI1930",
 740         "HDMI_INTERNAL",
 741         "INTERNAL_KLDSCP_TMDS1",
 742         "INTERNAL_KLDSCP_DVO1",
 743         "INTERNAL_KLDSCP_DAC1",
 744         "INTERNAL_KLDSCP_DAC2",
 745         "SI178",
 746         "MVPU_FPGA",
 747         "INTERNAL_DDI",
 748         "VT1625",
 749         "HDMI_SI1932",
 750         "DP_AN9801",
 751         "DP_DP501",
 752         "INTERNAL_UNIPHY",
 753         "INTERNAL_KLDSCP_LVTMA",
 754         "INTERNAL_UNIPHY1",
 755         "INTERNAL_UNIPHY2",
 756         "NUTMEG",
 757         "TRAVIS",
 758         "INTERNAL_VCE",
 759         "INTERNAL_UNIPHY3",
 760 };
 761
 762 static const char *hpd_names[6] = {
 763         "HPD1",
 764         "HPD2",
 765         "HPD3",
 766         "HPD4",
 767         "HPD5",
 768         "HPD6",
 769 };
 770
 771 static void radeon_print_display_setup(struct drm_device *dev)
 772 {
 773         struct drm_connector *connector;
 774         struct radeon_connector *radeon_connector;
 775         struct drm_encoder *encoder;
 776         struct radeon_encoder *radeon_encoder;
 777         uint32_t devices;
 778         int i = 0;
 779
 780         DRM_INFO("Radeon Display Connectors\n");
 781         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 782                 radeon_connector = to_radeon_connector(connector);
 783                 DRM_INFO("Connector %d:\n", i);
 784                 DRM_INFO("  %s\n", connector->name);
 785                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 786                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 787                 if (radeon_connector->ddc_bus) {
 788                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 789                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 790                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 791                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 792                                  radeon_connector->ddc_bus->rec.a_data_reg,
 793                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 794                                  radeon_connector->ddc_bus->rec.en_data_reg,
 795                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 796                                  radeon_connector->ddc_bus->rec.y_data_reg);
 797                         if (radeon_connector->router.ddc_valid)
 798                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 799                                          radeon_connector->router.ddc_mux_control_pin,
 800                                          radeon_connector->router.ddc_mux_state);
 801                         if (radeon_connector->router.cd_valid)
 802                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 803                                          radeon_connector->router.cd_mux_control_pin,
 804                                          radeon_connector->router.cd_mux_state);
 805                 } else {
 806                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 807                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 808                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 809                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 810                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 811                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 812                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 813                 }
 814                 DRM_INFO("  Encoders:\n");
 815                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 816                         radeon_encoder = to_radeon_encoder(encoder);
 817                         devices = radeon_encoder->devices & radeon_connector->devices;
 818                         if (devices) {
 819                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 820                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 821                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 822                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 823                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 824                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 825                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 826                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 827                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 828                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 829                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 830                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 831                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 832                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 833                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 834                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 835                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 836                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 837                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 838                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 839                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 840                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 841                         }
 842                 }
 843                 i++;
 844         }
 845 }
 846
 847 static bool radeon_setup_enc_conn(struct drm_device *dev)
 848 {
 849         struct radeon_device *rdev = dev->dev_private;
 850         bool ret = false;
 851
 852         if (rdev->bios) {
 853                 if (rdev->is_atom_bios) {
 854                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 855                         if (ret == false)
 856                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 857                 } else {
 858                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 859                         if (ret == false)
 860                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 861                 }
 862         } else {
 863                 if (!ASIC_IS_AVIVO(rdev))
 864                         ret = radeon_get_legacy_connector_info_from_table(dev);
 865         }
 866         if (ret) {
 867                 radeon_setup_encoder_clones(dev);
 868                 radeon_print_display_setup(dev);
 869         }
 870
 871         return ret;
 872 }
 873
 874 /* avivo */
 875
 876 /**
 877  * avivo_reduce_ratio - fractional number reduction
 878  *
 879  * @nom: nominator
 880  * @den: denominator
 881  * @nom_min: minimum value for nominator
 882  * @den_min: minimum value for denominator
 883  *
 884  * Find the greatest common divisor and apply it on both nominator and
 885  * denominator, but make nominator and denominator are at least as large
 886  * as their minimum values.
 887  */
 888 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 889                                unsigned nom_min, unsigned den_min)
 890 {
 891         unsigned tmp;
 892
 893         /* reduce the numbers to a simpler ratio */
 894         tmp = gcd(*nom, *den);
 895         *nom /= tmp;
 896         *den /= tmp;
 897
 898         /* make sure nominator is large enough */
 899         if (*nom < nom_min) {
 900                 tmp = DIV_ROUND_UP(nom_min, *nom);
 901                 *nom *= tmp;
 902                 *den *= tmp;
 903         }
 904
 905         /* make sure the denominator is large enough */
 906         if (*den < den_min) {
 907                 tmp = DIV_ROUND_UP(den_min, *den);
 908                 *nom *= tmp;
 909                 *den *= tmp;
 910         }
 911 }
 912
 913 /**
 914  * avivo_get_fb_ref_div - feedback and ref divider calculation
 915  *
 916  * @nom: nominator
 917  * @den: denominator
 918  * @post_div: post divider
 919  * @fb_div_max: feedback divider maximum
 920  * @ref_div_max: reference divider maximum
 921  * @fb_div: resulting feedback divider
 922  * @ref_div: resulting reference divider
 923  *
 924  * Calculate feedback and reference divider for a given post divider. Makes
 925  * sure we stay within the limits.
 926  */
 927 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
 928                                  unsigned fb_div_max, unsigned ref_div_max,
 929                                  unsigned *fb_div, unsigned *ref_div)
 930 {
 931         /* limit reference * post divider to a maximum */
 932         ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
 933
 934         /* get matching reference and feedback divider */
 935         *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
 936         *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
 937
 938         /* limit fb divider to its maximum */
 939         if (*fb_div > fb_div_max) {
 940                 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
 941                 *fb_div = fb_div_max;
 942         }
 943 }
 944
 945 /**
 946  * radeon_compute_pll_avivo - compute PLL paramaters
 947  *
 948  * @pll: information about the PLL
 949  * @dot_clock_p: resulting pixel clock
 950  * fb_div_p: resulting feedback divider
 951  * frac_fb_div_p: fractional part of the feedback divider
 952  * ref_div_p: resulting reference divider
 953  * post_div_p: resulting reference divider
 954  *
 955  * Try to calculate the PLL parameters to generate the given frequency:
 956  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 957  */
 958 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 959                               u32 freq,
 960                               u32 *dot_clock_p,
 961                               u32 *fb_div_p,
 962                               u32 *frac_fb_div_p,
 963                               u32 *ref_div_p,
 964                               u32 *post_div_p)
 965 {
 966         unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
 967                 freq : freq / 10;
 968
 969         unsigned fb_div_min, fb_div_max, fb_div;
 970         unsigned post_div_min, post_div_max, post_div;
 971         unsigned ref_div_min, ref_div_max, ref_div;
 972         unsigned post_div_best, diff_best;
 973         unsigned nom, den;
 974
 975         /* determine allowed feedback divider range */
 976         fb_div_min = pll->min_feedback_div;
 977         fb_div_max = pll->max_feedback_div;
 978
 979         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 980                 fb_div_min *= 10;
 981                 fb_div_max *= 10;
 982         }
 983
 984         /* determine allowed ref divider range */
 985         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 986                 ref_div_min = pll->reference_div;
 987         else
 988                 ref_div_min = pll->min_ref_div;
 989
 990         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
 991             pll->flags & RADEON_PLL_USE_REF_DIV)
 992                 ref_div_max = pll->reference_div;
 993         else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
 994                 /* fix for problems on RS880 */
 995                 ref_div_max = min(pll->max_ref_div, 7u);
 996         else
 997                 ref_div_max = pll->max_ref_div;
 998
 999         /* determine allowed post divider range */
1000         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1001                 post_div_min = pll->post_div;
1002                 post_div_max = pll->post_div;
1003         } else {
1004                 unsigned vco_min, vco_max;
1005
1006                 if (pll->flags & RADEON_PLL_IS_LCD) {
1007                         vco_min = pll->lcd_pll_out_min;
1008                         vco_max = pll->lcd_pll_out_max;
1009                 } else {
1010                         vco_min = pll->pll_out_min;
1011                         vco_max = pll->pll_out_max;
1012                 }
1013
1014                 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1015                         vco_min *= 10;
1016                         vco_max *= 10;
1017                 }
1018
1019                 post_div_min = vco_min / target_clock;
1020                 if ((target_clock * post_div_min) < vco_min)
1021                         ++post_div_min;
1022                 if (post_div_min < pll->min_post_div)
1023                         post_div_min = pll->min_post_div;
1024
1025                 post_div_max = vco_max / target_clock;
1026                 if ((target_clock * post_div_max) > vco_max)
1027                         --post_div_max;
1028                 if (post_div_max > pll->max_post_div)
1029                         post_div_max = pll->max_post_div;
1030         }
1031
1032         /* represent the searched ratio as fractional number */
1033         nom = target_clock;
1034         den = pll->reference_freq;
1035
1036         /* reduce the numbers to a simpler ratio */
1037         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1038
1039         /* now search for a post divider */
1040         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1041                 post_div_best = post_div_min;
1042         else
1043                 post_div_best = post_div_max;
1044         diff_best = ~0;
1045
1046         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1047                 unsigned diff;
1048                 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1049                                      ref_div_max, &fb_div, &ref_div);
1050                 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1051                         (ref_div * post_div));
1052
1053                 if (diff < diff_best || (diff == diff_best &&
1054                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1055
1056                         post_div_best = post_div;
1057                         diff_best = diff;
1058                 }
1059         }
1060         post_div = post_div_best;
1061
1062         /* get the feedback and reference divider for the optimal value */
1063         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1064                              &fb_div, &ref_div);
1065
1066         /* reduce the numbers to a simpler ratio once more */
1067         /* this also makes sure that the reference divider is large enough */
1068         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1069
1070         /* avoid high jitter with small fractional dividers */
1071         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1072                 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1073                 if (fb_div < fb_div_min) {
1074                         unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1075                         fb_div *= tmp;
1076                         ref_div *= tmp;
1077                 }
1078         }
1079
1080         /* and finally save the result */
1081         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1082                 *fb_div_p = fb_div / 10;
1083                 *frac_fb_div_p = fb_div % 10;
1084         } else {
1085                 *fb_div_p = fb_div;
1086                 *frac_fb_div_p = 0;
1087         }
1088
1089         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1090                         (pll->reference_freq * *frac_fb_div_p)) /
1091                        (ref_div * post_div * 10);
1092         *ref_div_p = ref_div;
1093         *post_div_p = post_div;
1094
1095         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1096                       freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1097                       ref_div, post_div);
1098 }
1099
1100 /* pre-avivo */
1101 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1102 {
1103         uint64_t mod;
1104
1105         n += d / 2;
1106
1107         mod = do_div(n, d);
1108         return n;
1109 }
1110
1111 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1112                                uint64_t freq,
1113                                uint32_t *dot_clock_p,
1114                                uint32_t *fb_div_p,
1115                                uint32_t *frac_fb_div_p,
1116                                uint32_t *ref_div_p,
1117                                uint32_t *post_div_p)
1118 {
1119         uint32_t min_ref_div = pll->min_ref_div;
1120         uint32_t max_ref_div = pll->max_ref_div;
1121         uint32_t min_post_div = pll->min_post_div;
1122         uint32_t max_post_div = pll->max_post_div;
1123         uint32_t min_fractional_feed_div = 0;
1124         uint32_t max_fractional_feed_div = 0;
1125         uint32_t best_vco = pll->best_vco;
1126         uint32_t best_post_div = 1;
1127         uint32_t best_ref_div = 1;
1128         uint32_t best_feedback_div = 1;
1129         uint32_t best_frac_feedback_div = 0;
1130         uint32_t best_freq = -1;
1131         uint32_t best_error = 0xffffffff;
1132         uint32_t best_vco_diff = 1;
1133         uint32_t post_div;
1134         u32 pll_out_min, pll_out_max;
1135
1136         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1137         freq = freq * 1000;
1138
1139         if (pll->flags & RADEON_PLL_IS_LCD) {
1140                 pll_out_min = pll->lcd_pll_out_min;
1141                 pll_out_max = pll->lcd_pll_out_max;
1142         } else {
1143                 pll_out_min = pll->pll_out_min;
1144                 pll_out_max = pll->pll_out_max;
1145         }
1146
1147         if (pll_out_min > 64800)
1148                 pll_out_min = 64800;
1149
1150         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1151                 min_ref_div = max_ref_div = pll->reference_div;
1152         else {
1153                 while (min_ref_div < max_ref_div-1) {
1154                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1155                         uint32_t pll_in = pll->reference_freq / mid;
1156                         if (pll_in < pll->pll_in_min)
1157                                 max_ref_div = mid;
1158                         else if (pll_in > pll->pll_in_max)
1159                                 min_ref_div = mid;
1160                         else
1161                                 break;
1162                 }
1163         }
1164
1165         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1166                 min_post_div = max_post_div = pll->post_div;
1167
1168         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1169                 min_fractional_feed_div = pll->min_frac_feedback_div;
1170                 max_fractional_feed_div = pll->max_frac_feedback_div;
1171         }
1172
1173         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1174                 uint32_t ref_div;
1175
1176                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1177                         continue;
1178
1179                 /* legacy radeons only have a few post_divs */
1180                 if (pll->flags & RADEON_PLL_LEGACY) {
1181                         if ((post_div == 5) ||
1182                             (post_div == 7) ||
1183                             (post_div == 9) ||
1184                             (post_div == 10) ||
1185                             (post_div == 11) ||
1186                             (post_div == 13) ||
1187                             (post_div == 14) ||
1188                             (post_div == 15))
1189                                 continue;
1190                 }
1191
1192                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1193                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1194                         uint32_t pll_in = pll->reference_freq / ref_div;
1195                         uint32_t min_feed_div = pll->min_feedback_div;
1196                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1197
1198                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1199                                 continue;
1200
1201                         while (min_feed_div < max_feed_div) {
1202                                 uint32_t vco;
1203                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1204                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1205                                 uint32_t frac_feedback_div;
1206                                 uint64_t tmp;
1207
1208                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1209
1210                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1211                                 vco = radeon_div(tmp, ref_div);
1212
1213                                 if (vco < pll_out_min) {
1214                                         min_feed_div = feedback_div + 1;
1215                                         continue;
1216                                 } else if (vco > pll_out_max) {
1217                                         max_feed_div = feedback_div;
1218                                         continue;
1219                                 }
1220
1221                                 while (min_frac_feed_div < max_frac_feed_div) {
1222                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1223                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1224                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1225                                         current_freq = radeon_div(tmp, ref_div * post_div);
1226
1227                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1228                                                 if (freq < current_freq)
1229                                                         error = 0xffffffff;
1230                                                 else
1231                                                         error = freq - current_freq;
1232                                         } else
1233                                                 error = abs(current_freq - freq);
1234                                         vco_diff = abs(vco - best_vco);
1235
1236                                         if ((best_vco == 0 && error < best_error) ||
1237                                             (best_vco != 0 &&
1238                                              ((best_error > 100 && error < best_error - 100) ||
1239                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1240                                                 best_post_div = post_div;
1241                                                 best_ref_div = ref_div;
1242                                                 best_feedback_div = feedback_div;
1243                                                 best_frac_feedback_div = frac_feedback_div;
1244                                                 best_freq = current_freq;
1245                                                 best_error = error;
1246                                                 best_vco_diff = vco_diff;
1247                                         } else if (current_freq == freq) {
1248                                                 if (best_freq == -1) {
1249                                                         best_post_div = post_div;
1250                                                         best_ref_div = ref_div;
1251                                                         best_feedback_div = feedback_div;
1252                                                         best_frac_feedback_div = frac_feedback_div;
1253                                                         best_freq = current_freq;
1254                                                         best_error = error;
1255                                                         best_vco_diff = vco_diff;
1256                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1257                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1258                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1259                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1260                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1261                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1262                                                         best_post_div = post_div;
1263                                                         best_ref_div = ref_div;
1264                                                         best_feedback_div = feedback_div;
1265                                                         best_frac_feedback_div = frac_feedback_div;
1266                                                         best_freq = current_freq;
1267                                                         best_error = error;
1268                                                         best_vco_diff = vco_diff;
1269                                                 }
1270                                         }
1271                                         if (current_freq < freq)
1272                                                 min_frac_feed_div = frac_feedback_div + 1;
1273                                         else
1274                                                 max_frac_feed_div = frac_feedback_div;
1275                                 }
1276                                 if (current_freq < freq)
1277                                         min_feed_div = feedback_div + 1;
1278                                 else
1279                                         max_feed_div = feedback_div;
1280                         }
1281                 }
1282         }
1283
1284         *dot_clock_p = best_freq / 10000;
1285         *fb_div_p = best_feedback_div;
1286         *frac_fb_div_p = best_frac_feedback_div;
1287         *ref_div_p = best_ref_div;
1288         *post_div_p = best_post_div;
1289         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1290                       (long long)freq,
1291                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1292                       best_ref_div, best_post_div);
1293
1294 }
1295
1296 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1297 {
1298         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1299
1300         drm_gem_object_unreference_unlocked(radeon_fb->obj);
1301         drm_framebuffer_cleanup(fb);
1302         kfree(radeon_fb);
1303 }
1304
1305 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1306                                                   struct drm_file *file_priv,
1307                                                   unsigned int *handle)
1308 {
1309         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1310
1311         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1312 }
1313
1314 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1315         .destroy = radeon_user_framebuffer_destroy,
1316         .create_handle = radeon_user_framebuffer_create_handle,
1317 };
1318
1319 int
1320 radeon_framebuffer_init(struct drm_device *dev,
1321                         struct radeon_framebuffer *rfb,
1322                         const struct drm_mode_fb_cmd2 *mode_cmd,
1323                         struct drm_gem_object *obj)
1324 {
1325         int ret;
1326         rfb->obj = obj;
1327         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1328         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1329         if (ret) {
1330                 rfb->obj = NULL;
1331                 return ret;
1332         }
1333         return 0;
1334 }
1335
1336 static struct drm_framebuffer *
1337 radeon_user_framebuffer_create(struct drm_device *dev,
1338                                struct drm_file *file_priv,
1339                                const struct drm_mode_fb_cmd2 *mode_cmd)
1340 {
1341         struct drm_gem_object *obj;
1342         struct radeon_framebuffer *radeon_fb;
1343         int ret;
1344
1345         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1346         if (obj ==  NULL) {
1347                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1348                         "can't create framebuffer\n", mode_cmd->handles[0]);
1349                 return ERR_PTR(-ENOENT);
1350         }
1351
1352         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1353         if (radeon_fb == NULL) {
1354                 drm_gem_object_unreference_unlocked(obj);
1355                 return ERR_PTR(-ENOMEM);
1356         }
1357
1358         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1359         if (ret) {
1360                 kfree(radeon_fb);
1361                 drm_gem_object_unreference_unlocked(obj);
1362                 return ERR_PTR(ret);
1363         }
1364
1365         return &radeon_fb->base;
1366 }
1367
1368 static void radeon_output_poll_changed(struct drm_device *dev)
1369 {
1370         struct radeon_device *rdev = dev->dev_private;
1371         radeon_fb_output_poll_changed(rdev);
1372 }
1373
1374 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1375         .fb_create = radeon_user_framebuffer_create,
1376         .output_poll_changed = radeon_output_poll_changed
1377 };
1378
1379 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1380 {       { 0, "driver" },
1381         { 1, "bios" },
1382 };
1383
1384 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1385 {       { TV_STD_NTSC, "ntsc" },
1386         { TV_STD_PAL, "pal" },
1387         { TV_STD_PAL_M, "pal-m" },
1388         { TV_STD_PAL_60, "pal-60" },
1389         { TV_STD_NTSC_J, "ntsc-j" },
1390         { TV_STD_SCART_PAL, "scart-pal" },
1391         { TV_STD_PAL_CN, "pal-cn" },
1392         { TV_STD_SECAM, "secam" },
1393 };
1394
1395 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1396 {       { UNDERSCAN_OFF, "off" },
1397         { UNDERSCAN_ON, "on" },
1398         { UNDERSCAN_AUTO, "auto" },
1399 };
1400
1401 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1402 {       { RADEON_AUDIO_DISABLE, "off" },
1403         { RADEON_AUDIO_ENABLE, "on" },
1404         { RADEON_AUDIO_AUTO, "auto" },
1405 };
1406
1407 /* XXX support different dither options? spatial, temporal, both, etc. */
1408 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1409 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1410         { RADEON_FMT_DITHER_ENABLE, "on" },
1411 };
1412
1413 static struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1414 {       { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1415         { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1416         { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1417         { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1418 };
1419
1420 static int radeon_modeset_create_props(struct radeon_device *rdev)
1421 {
1422         int sz;
1423
1424         if (rdev->is_atom_bios) {
1425                 rdev->mode_info.coherent_mode_property =
1426                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1427                 if (!rdev->mode_info.coherent_mode_property)
1428                         return -ENOMEM;
1429         }
1430
1431         if (!ASIC_IS_AVIVO(rdev)) {
1432                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1433                 rdev->mode_info.tmds_pll_property =
1434                         drm_property_create_enum(rdev->ddev, 0,
1435                                             "tmds_pll",
1436                                             radeon_tmds_pll_enum_list, sz);
1437         }
1438
1439         rdev->mode_info.load_detect_property =
1440                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1441         if (!rdev->mode_info.load_detect_property)
1442                 return -ENOMEM;
1443
1444         drm_mode_create_scaling_mode_property(rdev->ddev);
1445
1446         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1447         rdev->mode_info.tv_std_property =
1448                 drm_property_create_enum(rdev->ddev, 0,
1449                                     "tv standard",
1450                                     radeon_tv_std_enum_list, sz);
1451
1452         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1453         rdev->mode_info.underscan_property =
1454                 drm_property_create_enum(rdev->ddev, 0,
1455                                     "underscan",
1456                                     radeon_underscan_enum_list, sz);
1457
1458         rdev->mode_info.underscan_hborder_property =
1459                 drm_property_create_range(rdev->ddev, 0,
1460                                         "underscan hborder", 0, 128);
1461         if (!rdev->mode_info.underscan_hborder_property)
1462                 return -ENOMEM;
1463
1464         rdev->mode_info.underscan_vborder_property =
1465                 drm_property_create_range(rdev->ddev, 0,
1466                                         "underscan vborder", 0, 128);
1467         if (!rdev->mode_info.underscan_vborder_property)
1468                 return -ENOMEM;
1469
1470         sz = ARRAY_SIZE(radeon_audio_enum_list);
1471         rdev->mode_info.audio_property =
1472                 drm_property_create_enum(rdev->ddev, 0,
1473                                          "audio",
1474                                          radeon_audio_enum_list, sz);
1475
1476         sz = ARRAY_SIZE(radeon_dither_enum_list);
1477         rdev->mode_info.dither_property =
1478                 drm_property_create_enum(rdev->ddev, 0,
1479                                          "dither",
1480                                          radeon_dither_enum_list, sz);
1481
1482         sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1483         rdev->mode_info.output_csc_property =
1484                 drm_property_create_enum(rdev->ddev, 0,
1485                                          "output_csc",
1486                                          radeon_output_csc_enum_list, sz);
1487
1488         return 0;
1489 }
1490
1491 void radeon_update_display_priority(struct radeon_device *rdev)
1492 {
1493         /* adjustment options for the display watermarks */
1494         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1495                 /* set display priority to high for r3xx, rv515 chips
1496                  * this avoids flickering due to underflow to the
1497                  * display controllers during heavy acceleration.
1498                  * Don't force high on rs4xx igp chips as it seems to
1499                  * affect the sound card.  See kernel bug 15982.
1500                  */
1501                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1502                     !(rdev->flags & RADEON_IS_IGP))
1503                         rdev->disp_priority = 2;
1504                 else
1505                         rdev->disp_priority = 0;
1506         } else
1507                 rdev->disp_priority = radeon_disp_priority;
1508
1509 }
1510
1511 /*
1512  * Allocate hdmi structs and determine register offsets
1513  */
1514 static void radeon_afmt_init(struct radeon_device *rdev)
1515 {
1516         int i;
1517
1518         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1519                 rdev->mode_info.afmt[i] = NULL;
1520
1521         if (ASIC_IS_NODCE(rdev)) {
1522                 /* nothing to do */
1523         } else if (ASIC_IS_DCE4(rdev)) {
1524                 static uint32_t eg_offsets[] = {
1525                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1526                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1527                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1528                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1529                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1530                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1531                         0x13830 - 0x7030,
1532                 };
1533                 int num_afmt;
1534
1535                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1536                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1537                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1538                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1539                 if (ASIC_IS_DCE8(rdev))
1540                         num_afmt = 7;
1541                 else if (ASIC_IS_DCE6(rdev))
1542                         num_afmt = 6;
1543                 else if (ASIC_IS_DCE5(rdev))
1544                         num_afmt = 6;
1545                 else if (ASIC_IS_DCE41(rdev))
1546                         num_afmt = 2;
1547                 else /* DCE4 */
1548                         num_afmt = 6;
1549
1550                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1551                 for (i = 0; i < num_afmt; i++) {
1552                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1553                         if (rdev->mode_info.afmt[i]) {
1554                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1555                                 rdev->mode_info.afmt[i]->id = i;
1556                         }
1557                 }
1558         } else if (ASIC_IS_DCE3(rdev)) {
1559                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1560                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1561                 if (rdev->mode_info.afmt[0]) {
1562                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1563                         rdev->mode_info.afmt[0]->id = 0;
1564                 }
1565                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1566                 if (rdev->mode_info.afmt[1]) {
1567                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1568                         rdev->mode_info.afmt[1]->id = 1;
1569                 }
1570         } else if (ASIC_IS_DCE2(rdev)) {
1571                 /* DCE2 has at least 1 routable audio block */
1572                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1573                 if (rdev->mode_info.afmt[0]) {
1574                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1575                         rdev->mode_info.afmt[0]->id = 0;
1576                 }
1577                 /* r6xx has 2 routable audio blocks */
1578                 if (rdev->family >= CHIP_R600) {
1579                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1580                         if (rdev->mode_info.afmt[1]) {
1581                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1582                                 rdev->mode_info.afmt[1]->id = 1;
1583                         }
1584                 }
1585         }
1586 }
1587
1588 static void radeon_afmt_fini(struct radeon_device *rdev)
1589 {
1590         int i;
1591
1592         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1593                 kfree(rdev->mode_info.afmt[i]);
1594                 rdev->mode_info.afmt[i] = NULL;
1595         }
1596 }
1597
1598 int radeon_modeset_init(struct radeon_device *rdev)
1599 {
1600         int i;
1601         int ret;
1602
1603         drm_mode_config_init(rdev->ddev);
1604         rdev->mode_info.mode_config_initialized = true;
1605
1606         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1607
1608         if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1609                 rdev->ddev->mode_config.async_page_flip = true;
1610
1611         if (ASIC_IS_DCE5(rdev)) {
1612                 rdev->ddev->mode_config.max_width = 16384;
1613                 rdev->ddev->mode_config.max_height = 16384;
1614         } else if (ASIC_IS_AVIVO(rdev)) {
1615                 rdev->ddev->mode_config.max_width = 8192;
1616                 rdev->ddev->mode_config.max_height = 8192;
1617         } else {
1618                 rdev->ddev->mode_config.max_width = 4096;
1619                 rdev->ddev->mode_config.max_height = 4096;
1620         }
1621
1622         rdev->ddev->mode_config.preferred_depth = 24;
1623         rdev->ddev->mode_config.prefer_shadow = 1;
1624
1625         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1626
1627         ret = radeon_modeset_create_props(rdev);
1628         if (ret) {
1629                 return ret;
1630         }
1631
1632         /* init i2c buses */
1633         radeon_i2c_init(rdev);
1634
1635         /* check combios for a valid hardcoded EDID - Sun servers */
1636         if (!rdev->is_atom_bios) {
1637                 /* check for hardcoded EDID in BIOS */
1638                 radeon_combios_check_hardcoded_edid(rdev);
1639         }
1640
1641         /* allocate crtcs */
1642         for (i = 0; i < rdev->num_crtc; i++) {
1643                 radeon_crtc_init(rdev->ddev, i);
1644         }
1645
1646         /* okay we should have all the bios connectors */
1647         ret = radeon_setup_enc_conn(rdev->ddev);
1648         if (!ret) {
1649                 return ret;
1650         }
1651
1652         /* init dig PHYs, disp eng pll */
1653         if (rdev->is_atom_bios) {
1654                 radeon_atom_encoder_init(rdev);
1655                 radeon_atom_disp_eng_pll_init(rdev);
1656         }
1657
1658         /* initialize hpd */
1659         radeon_hpd_init(rdev);
1660
1661         /* setup afmt */
1662         radeon_afmt_init(rdev);
1663
1664         radeon_fbdev_init(rdev);
1665         drm_kms_helper_poll_init(rdev->ddev);
1666
1667         /* do pm late init */
1668         ret = radeon_pm_late_init(rdev);
1669
1670         return 0;
1671 }
1672
1673 void radeon_modeset_fini(struct radeon_device *rdev)
1674 {
1675         radeon_fbdev_fini(rdev);
1676         kfree(rdev->mode_info.bios_hardcoded_edid);
1677
1678         /* free i2c buses */
1679         radeon_i2c_fini(rdev);
1680
1681         if (rdev->mode_info.mode_config_initialized) {
1682                 radeon_afmt_fini(rdev);
1683                 drm_kms_helper_poll_fini(rdev->ddev);
1684                 radeon_hpd_fini(rdev);
1685                 drm_crtc_force_disable_all(rdev->ddev);
1686                 drm_mode_config_cleanup(rdev->ddev);
1687                 rdev->mode_info.mode_config_initialized = false;
1688         }
1689 }
1690
1691 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1692 {
1693         /* try and guess if this is a tv or a monitor */
1694         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1695             (mode->vdisplay == 576) || /* 576p */
1696             (mode->vdisplay == 720) || /* 720p */
1697             (mode->vdisplay == 1080)) /* 1080p */
1698                 return true;
1699         else
1700                 return false;
1701 }
1702
1703 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1704                                 const struct drm_display_mode *mode,
1705                                 struct drm_display_mode *adjusted_mode)
1706 {
1707         struct drm_device *dev = crtc->dev;
1708         struct radeon_device *rdev = dev->dev_private;
1709         struct drm_encoder *encoder;
1710         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1711         struct radeon_encoder *radeon_encoder;
1712         struct drm_connector *connector;
1713         struct radeon_connector *radeon_connector;
1714         bool first = true;
1715         u32 src_v = 1, dst_v = 1;
1716         u32 src_h = 1, dst_h = 1;
1717
1718         radeon_crtc->h_border = 0;
1719         radeon_crtc->v_border = 0;
1720
1721         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1722                 if (encoder->crtc != crtc)
1723                         continue;
1724                 radeon_encoder = to_radeon_encoder(encoder);
1725                 connector = radeon_get_connector_for_encoder(encoder);
1726                 radeon_connector = to_radeon_connector(connector);
1727
1728                 if (first) {
1729                         /* set scaling */
1730                         if (radeon_encoder->rmx_type == RMX_OFF)
1731                                 radeon_crtc->rmx_type = RMX_OFF;
1732                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1733                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1734                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1735                         else
1736                                 radeon_crtc->rmx_type = RMX_OFF;
1737                         /* copy native mode */
1738                         memcpy(&radeon_crtc->native_mode,
1739                                &radeon_encoder->native_mode,
1740                                 sizeof(struct drm_display_mode));
1741                         src_v = crtc->mode.vdisplay;
1742                         dst_v = radeon_crtc->native_mode.vdisplay;
1743                         src_h = crtc->mode.hdisplay;
1744                         dst_h = radeon_crtc->native_mode.hdisplay;
1745
1746                         /* fix up for overscan on hdmi */
1747                         if (ASIC_IS_AVIVO(rdev) &&
1748                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1749                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1750                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1751                               drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1752                               is_hdtv_mode(mode)))) {
1753                                 if (radeon_encoder->underscan_hborder != 0)
1754                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1755                                 else
1756                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1757                                 if (radeon_encoder->underscan_vborder != 0)
1758                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1759                                 else
1760                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1761                                 radeon_crtc->rmx_type = RMX_FULL;
1762                                 src_v = crtc->mode.vdisplay;
1763                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1764                                 src_h = crtc->mode.hdisplay;
1765                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1766                         }
1767                         first = false;
1768                 } else {
1769                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1770                                 /* WARNING: Right now this can't happen but
1771                                  * in the future we need to check that scaling
1772                                  * are consistent across different encoder
1773                                  * (ie all encoder can work with the same
1774                                  *  scaling).
1775                                  */
1776                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1777                                 return false;
1778                         }
1779                 }
1780         }
1781         if (radeon_crtc->rmx_type != RMX_OFF) {
1782                 fixed20_12 a, b;
1783                 a.full = dfixed_const(src_v);
1784                 b.full = dfixed_const(dst_v);
1785                 radeon_crtc->vsc.full = dfixed_div(a, b);
1786                 a.full = dfixed_const(src_h);
1787                 b.full = dfixed_const(dst_h);
1788                 radeon_crtc->hsc.full = dfixed_div(a, b);
1789         } else {
1790                 radeon_crtc->vsc.full = dfixed_const(1);
1791                 radeon_crtc->hsc.full = dfixed_const(1);
1792         }
1793         return true;
1794 }
1795
1796 /*
1797  * Retrieve current video scanout position of crtc on a given gpu, and
1798  * an optional accurate timestamp of when query happened.
1799  *
1800  * \param dev Device to query.
1801  * \param crtc Crtc to query.
1802  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1803  *              For driver internal use only also supports these flags:
1804  *
1805  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1806  *              of a fudged earlier start of vblank.
1807  *
1808  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1809  *              fudged earlier start of vblank in *vpos and the distance
1810  *              to true start of vblank in *hpos.
1811  *
1812  * \param *vpos Location where vertical scanout position should be stored.
1813  * \param *hpos Location where horizontal scanout position should go.
1814  * \param *stime Target location for timestamp taken immediately before
1815  *               scanout position query. Can be NULL to skip timestamp.
1816  * \param *etime Target location for timestamp taken immediately after
1817  *               scanout position query. Can be NULL to skip timestamp.
1818  *
1819  * Returns vpos as a positive number while in active scanout area.
1820  * Returns vpos as a negative number inside vblank, counting the number
1821  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1822  * until start of active scanout / end of vblank."
1823  *
1824  * \return Flags, or'ed together as follows:
1825  *
1826  * DRM_SCANOUTPOS_VALID = Query successful.
1827  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1828  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1829  * this flag means that returned position may be offset by a constant but
1830  * unknown small number of scanlines wrt. real scanout position.
1831  *
1832  */
1833 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1834                                unsigned int flags, int *vpos, int *hpos,
1835                                ktime_t *stime, ktime_t *etime,
1836                                const struct drm_display_mode *mode)
1837 {
1838         u32 stat_crtc = 0, vbl = 0, position = 0;
1839         int vbl_start, vbl_end, vtotal, ret = 0;
1840         bool in_vbl = true;
1841
1842         struct radeon_device *rdev = dev->dev_private;
1843
1844         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1845
1846         /* Get optional system timestamp before query. */
1847         if (stime)
1848                 *stime = ktime_get();
1849
1850         if (ASIC_IS_DCE4(rdev)) {
1851                 if (pipe == 0) {
1852                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1853                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1854                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1855                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1856                         ret |= DRM_SCANOUTPOS_VALID;
1857                 }
1858                 if (pipe == 1) {
1859                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1860                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1861                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1862                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1863                         ret |= DRM_SCANOUTPOS_VALID;
1864                 }
1865                 if (pipe == 2) {
1866                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1867                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1868                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1869                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1870                         ret |= DRM_SCANOUTPOS_VALID;
1871                 }
1872                 if (pipe == 3) {
1873                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1874                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1875                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1876                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1877                         ret |= DRM_SCANOUTPOS_VALID;
1878                 }
1879                 if (pipe == 4) {
1880                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1881                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1882                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1883                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1884                         ret |= DRM_SCANOUTPOS_VALID;
1885                 }
1886                 if (pipe == 5) {
1887                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1888                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1889                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1890                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1891                         ret |= DRM_SCANOUTPOS_VALID;
1892                 }
1893         } else if (ASIC_IS_AVIVO(rdev)) {
1894                 if (pipe == 0) {
1895                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1896                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1897                         ret |= DRM_SCANOUTPOS_VALID;
1898                 }
1899                 if (pipe == 1) {
1900                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1901                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1902                         ret |= DRM_SCANOUTPOS_VALID;
1903                 }
1904         } else {
1905                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1906                 if (pipe == 0) {
1907                         /* Assume vbl_end == 0, get vbl_start from
1908                          * upper 16 bits.
1909                          */
1910                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1911                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1912                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1913                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1914                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1915                         if (!(stat_crtc & 1))
1916                                 in_vbl = false;
1917
1918                         ret |= DRM_SCANOUTPOS_VALID;
1919                 }
1920                 if (pipe == 1) {
1921                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1922                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1923                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1924                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1925                         if (!(stat_crtc & 1))
1926                                 in_vbl = false;
1927
1928                         ret |= DRM_SCANOUTPOS_VALID;
1929                 }
1930         }
1931
1932         /* Get optional system timestamp after query. */
1933         if (etime)
1934                 *etime = ktime_get();
1935
1936         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1937
1938         /* Decode into vertical and horizontal scanout position. */
1939         *vpos = position & 0x1fff;
1940         *hpos = (position >> 16) & 0x1fff;
1941
1942         /* Valid vblank area boundaries from gpu retrieved? */
1943         if (vbl > 0) {
1944                 /* Yes: Decode. */
1945                 ret |= DRM_SCANOUTPOS_ACCURATE;
1946                 vbl_start = vbl & 0x1fff;
1947                 vbl_end = (vbl >> 16) & 0x1fff;
1948         }
1949         else {
1950                 /* No: Fake something reasonable which gives at least ok results. */
1951                 vbl_start = mode->crtc_vdisplay;
1952                 vbl_end = 0;
1953         }
1954
1955         /* Called from driver internal vblank counter query code? */
1956         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1957             /* Caller wants distance from real vbl_start in *hpos */
1958             *hpos = *vpos - vbl_start;
1959         }
1960
1961         /* Fudge vblank to start a few scanlines earlier to handle the
1962          * problem that vblank irqs fire a few scanlines before start
1963          * of vblank. Some driver internal callers need the true vblank
1964          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1965          *
1966          * The cause of the "early" vblank irq is that the irq is triggered
1967          * by the line buffer logic when the line buffer read position enters
1968          * the vblank, whereas our crtc scanout position naturally lags the
1969          * line buffer read position.
1970          */
1971         if (!(flags & USE_REAL_VBLANKSTART))
1972                 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1973
1974         /* Test scanout position against vblank region. */
1975         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1976                 in_vbl = false;
1977
1978         /* In vblank? */
1979         if (in_vbl)
1980             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1981
1982         /* Called from driver internal vblank counter query code? */
1983         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1984                 /* Caller wants distance from fudged earlier vbl_start */
1985                 *vpos -= vbl_start;
1986                 return ret;
1987         }
1988
1989         /* Check if inside vblank area and apply corrective offsets:
1990          * vpos will then be >=0 in video scanout area, but negative
1991          * within vblank area, counting down the number of lines until
1992          * start of scanout.
1993          */
1994
1995         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1996         if (in_vbl && (*vpos >= vbl_start)) {
1997                 vtotal = mode->crtc_vtotal;
1998                 *vpos = *vpos - vtotal;
1999         }
2000
2001         /* Correct for shifted end of vbl at vbl_end. */
2002         *vpos = *vpos - vbl_end;
2003
2004         return ret;
2005 }