drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50
  51 /* Firmware Names */
  52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  53 MODULE_FIRMWARE("radeon/R600_me.bin");
  54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV610_me.bin");
  56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV630_me.bin");
  58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV620_me.bin");
  60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV635_me.bin");
  62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV670_me.bin");
  64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RS780_me.bin");
  66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RV770_me.bin");
  68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  69 MODULE_FIRMWARE("radeon/RV730_me.bin");
  70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  71 MODULE_FIRMWARE("radeon/RV710_me.bin");
  72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  86
  87 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  88
  89 /* r600,rv610,rv630,rv620,rv635,rv670 */
  90 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  91 void r600_gpu_init(struct radeon_device *rdev);
  92 void r600_fini(struct radeon_device *rdev);
  93 void r600_irq_disable(struct radeon_device *rdev);
  94
  95 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
  96 {
  97         int i;
  98
  99         rdev->pm.dynpm_can_upclock = true;
 100         rdev->pm.dynpm_can_downclock = true;
 101
 102         /* power state array is low to high, default is first */
 103         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 104                 int min_power_state_index = 0;
 105
 106                 if (rdev->pm.num_power_states > 2)
 107                         min_power_state_index = 1;
 108
 109                 switch (rdev->pm.dynpm_planned_action) {
 110                 case DYNPM_ACTION_MINIMUM:
 111                         rdev->pm.requested_power_state_index = min_power_state_index;
 112                         rdev->pm.requested_clock_mode_index = 0;
 113                         rdev->pm.dynpm_can_downclock = false;
 114                         break;
 115                 case DYNPM_ACTION_DOWNCLOCK:
 116                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 117                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 118                                 rdev->pm.dynpm_can_downclock = false;
 119                         } else {
 120                                 if (rdev->pm.active_crtc_count > 1) {
 121                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 122                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 123                                                         continue;
 124                                                 else if (i >= rdev->pm.current_power_state_index) {
 125                                                         rdev->pm.requested_power_state_index =
 126                                                                 rdev->pm.current_power_state_index;
 127                                                         break;
 128                                                 } else {
 129                                                         rdev->pm.requested_power_state_index = i;
 130                                                         break;
 131                                                 }
 132                                         }
 133                                 } else {
 134                                         if (rdev->pm.current_power_state_index == 0)
 135                                                 rdev->pm.requested_power_state_index =
 136                                                         rdev->pm.num_power_states - 1;
 137                                         else
 138                                                 rdev->pm.requested_power_state_index =
 139                                                         rdev->pm.current_power_state_index - 1;
 140                                 }
 141                         }
 142                         rdev->pm.requested_clock_mode_index = 0;
 143                         /* don't use the power state if crtcs are active and no display flag is set */
 144                         if ((rdev->pm.active_crtc_count > 0) &&
 145                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 146                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 147                              RADEON_PM_MODE_NO_DISPLAY)) {
 148                                 rdev->pm.requested_power_state_index++;
 149                         }
 150                         break;
 151                 case DYNPM_ACTION_UPCLOCK:
 152                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 153                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 154                                 rdev->pm.dynpm_can_upclock = false;
 155                         } else {
 156                                 if (rdev->pm.active_crtc_count > 1) {
 157                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 158                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 159                                                         continue;
 160                                                 else if (i <= rdev->pm.current_power_state_index) {
 161                                                         rdev->pm.requested_power_state_index =
 162                                                                 rdev->pm.current_power_state_index;
 163                                                         break;
 164                                                 } else {
 165                                                         rdev->pm.requested_power_state_index = i;
 166                                                         break;
 167                                                 }
 168                                         }
 169                                 } else
 170                                         rdev->pm.requested_power_state_index =
 171                                                 rdev->pm.current_power_state_index + 1;
 172                         }
 173                         rdev->pm.requested_clock_mode_index = 0;
 174                         break;
 175                 case DYNPM_ACTION_DEFAULT:
 176                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 177                         rdev->pm.requested_clock_mode_index = 0;
 178                         rdev->pm.dynpm_can_upclock = false;
 179                         break;
 180                 case DYNPM_ACTION_NONE:
 181                 default:
 182                         DRM_ERROR("Requested mode for not defined action\n");
 183                         return;
 184                 }
 185         } else {
 186                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 187                 /* for now just select the first power state and switch between clock modes */
 188                 /* power state array is low to high, default is first (0) */
 189                 if (rdev->pm.active_crtc_count > 1) {
 190                         rdev->pm.requested_power_state_index = -1;
 191                         /* start at 1 as we don't want the default mode */
 192                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 193                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 194                                         continue;
 195                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 196                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 197                                         rdev->pm.requested_power_state_index = i;
 198                                         break;
 199                                 }
 200                         }
 201                         /* if nothing selected, grab the default state. */
 202                         if (rdev->pm.requested_power_state_index == -1)
 203                                 rdev->pm.requested_power_state_index = 0;
 204                 } else
 205                         rdev->pm.requested_power_state_index = 1;
 206
 207                 switch (rdev->pm.dynpm_planned_action) {
 208                 case DYNPM_ACTION_MINIMUM:
 209                         rdev->pm.requested_clock_mode_index = 0;
 210                         rdev->pm.dynpm_can_downclock = false;
 211                         break;
 212                 case DYNPM_ACTION_DOWNCLOCK:
 213                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 214                                 if (rdev->pm.current_clock_mode_index == 0) {
 215                                         rdev->pm.requested_clock_mode_index = 0;
 216                                         rdev->pm.dynpm_can_downclock = false;
 217                                 } else
 218                                         rdev->pm.requested_clock_mode_index =
 219                                                 rdev->pm.current_clock_mode_index - 1;
 220                         } else {
 221                                 rdev->pm.requested_clock_mode_index = 0;
 222                                 rdev->pm.dynpm_can_downclock = false;
 223                         }
 224                         /* don't use the power state if crtcs are active and no display flag is set */
 225                         if ((rdev->pm.active_crtc_count > 0) &&
 226                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 227                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 228                              RADEON_PM_MODE_NO_DISPLAY)) {
 229                                 rdev->pm.requested_clock_mode_index++;
 230                         }
 231                         break;
 232                 case DYNPM_ACTION_UPCLOCK:
 233                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 234                                 if (rdev->pm.current_clock_mode_index ==
 235                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 236                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 237                                         rdev->pm.dynpm_can_upclock = false;
 238                                 } else
 239                                         rdev->pm.requested_clock_mode_index =
 240                                                 rdev->pm.current_clock_mode_index + 1;
 241                         } else {
 242                                 rdev->pm.requested_clock_mode_index =
 243                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 244                                 rdev->pm.dynpm_can_upclock = false;
 245                         }
 246                         break;
 247                 case DYNPM_ACTION_DEFAULT:
 248                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 249                         rdev->pm.requested_clock_mode_index = 0;
 250                         rdev->pm.dynpm_can_upclock = false;
 251                         break;
 252                 case DYNPM_ACTION_NONE:
 253                 default:
 254                         DRM_ERROR("Requested mode for not defined action\n");
 255                         return;
 256                 }
 257         }
 258
 259         DRM_DEBUG("Requested: e: %d m: %d p: %d\n",
 260                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 261                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 262                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 263                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 264                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 265                   pcie_lanes);
 266 }
 267
 268 static int r600_pm_get_type_index(struct radeon_device *rdev,
 269                                   enum radeon_pm_state_type ps_type,
 270                                   int instance)
 271 {
 272         int i;
 273         int found_instance = -1;
 274
 275         for (i = 0; i < rdev->pm.num_power_states; i++) {
 276                 if (rdev->pm.power_state[i].type == ps_type) {
 277                         found_instance++;
 278                         if (found_instance == instance)
 279                                 return i;
 280                 }
 281         }
 282         /* return default if no match */
 283         return rdev->pm.default_power_state_index;
 284 }
 285
 286 void rs780_pm_init_profile(struct radeon_device *rdev)
 287 {
 288         if (rdev->pm.num_power_states == 2) {
 289                 /* default */
 290                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 291                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 292                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 293                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 294                 /* low sh */
 295                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 296                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 297                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 298                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 299                 /* mid sh */
 300                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 301                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 302                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 303                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 304                 /* high sh */
 305                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 306                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 307                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 308                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 309                 /* low mh */
 310                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 311                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 312                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 313                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 314                 /* mid mh */
 315                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 316                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 317                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 319                 /* high mh */
 320                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 321                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 322                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 324         } else if (rdev->pm.num_power_states == 3) {
 325                 /* default */
 326                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 327                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 328                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 329                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 330                 /* low sh */
 331                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 332                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 333                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 334                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 335                 /* mid sh */
 336                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 337                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 338                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 339                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 340                 /* high sh */
 341                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 342                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 343                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 344                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 345                 /* low mh */
 346                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 347                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 348                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 349                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 350                 /* mid mh */
 351                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 352                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 353                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 354                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 355                 /* high mh */
 356                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 357                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 358                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 359                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 360         } else {
 361                 /* default */
 362                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 363                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 364                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 365                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 366                 /* low sh */
 367                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 368                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 369                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 370                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 371                 /* mid sh */
 372                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 373                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 374                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 375                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 376                 /* high sh */
 377                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 378                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 379                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 380                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 381                 /* low mh */
 382                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 383                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 384                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 385                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 386                 /* mid mh */
 387                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 388                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 389                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 390                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 391                 /* high mh */
 392                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 393                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 394                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 395                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 396         }
 397 }
 398
 399 void r600_pm_init_profile(struct radeon_device *rdev)
 400 {
 401         if (rdev->family == CHIP_R600) {
 402                 /* XXX */
 403                 /* default */
 404                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 405                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 406                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 407                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 408                 /* low sh */
 409                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 410                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 411                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 412                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 413                 /* mid sh */
 414                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 415                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 416                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 417                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 418                 /* high sh */
 419                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 420                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 421                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 422                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 423                 /* low mh */
 424                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 425                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 426                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 427                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 428                 /* mid mh */
 429                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 430                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 431                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 432                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 433                 /* high mh */
 434                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 435                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 436                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 437                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 438         } else {
 439                 if (rdev->pm.num_power_states < 4) {
 440                         /* default */
 441                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 442                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 443                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 444                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 445                         /* low sh */
 446                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 447                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 448                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 449                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 450                         /* mid sh */
 451                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 452                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 453                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 454                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 455                         /* high sh */
 456                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 457                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 458                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 459                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 460                         /* low mh */
 461                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 462                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 463                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 464                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 465                         /* low mh */
 466                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 467                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 468                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 469                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 470                         /* high mh */
 471                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 472                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 473                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 474                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 475                 } else {
 476                         /* default */
 477                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 478                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 479                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 480                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 481                         /* low sh */
 482                         if (rdev->flags & RADEON_IS_MOBILITY) {
 483                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 484                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 485                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 486                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 487                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 488                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 489                         } else {
 490                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 491                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 492                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 493                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 494                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 495                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 496                         }
 497                         /* mid sh */
 498                         if (rdev->flags & RADEON_IS_MOBILITY) {
 499                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 500                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 501                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 502                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 503                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 504                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 505                         } else {
 506                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 507                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 508                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 509                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 510                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 511                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 512                         }
 513                         /* high sh */
 514                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
 515                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 516                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
 517                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 518                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 519                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 520                         /* low mh */
 521                         if (rdev->flags & RADEON_IS_MOBILITY) {
 522                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 523                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 524                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 525                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 526                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 527                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 528                         } else {
 529                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 530                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 531                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 532                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 533                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 534                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 535                         }
 536                         /* mid mh */
 537                         if (rdev->flags & RADEON_IS_MOBILITY) {
 538                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 539                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 540                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 541                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 542                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 543                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 544                         } else {
 545                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 546                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 547                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 548                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 549                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 550                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 551                         }
 552                         /* high mh */
 553                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
 554                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 555                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
 556                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 557                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 558                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 559                 }
 560         }
 561 }
 562
 563 void r600_pm_misc(struct radeon_device *rdev)
 564 {
 565         int req_ps_idx = rdev->pm.requested_power_state_index;
 566         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 567         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 568         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 569
 570         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 571                 if (voltage->voltage != rdev->pm.current_vddc) {
 572                         radeon_atom_set_voltage(rdev, voltage->voltage);
 573                         rdev->pm.current_vddc = voltage->voltage;
 574                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 575                 }
 576         }
 577 }
 578
 579 bool r600_gui_idle(struct radeon_device *rdev)
 580 {
 581         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 582                 return false;
 583         else
 584                 return true;
 585 }
 586
 587 /* hpd for digital panel detect/disconnect */
 588 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 589 {
 590         bool connected = false;
 591
 592         if (ASIC_IS_DCE3(rdev)) {
 593                 switch (hpd) {
 594                 case RADEON_HPD_1:
 595                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 596                                 connected = true;
 597                         break;
 598                 case RADEON_HPD_2:
 599                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 600                                 connected = true;
 601                         break;
 602                 case RADEON_HPD_3:
 603                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 604                                 connected = true;
 605                         break;
 606                 case RADEON_HPD_4:
 607                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 608                                 connected = true;
 609                         break;
 610                         /* DCE 3.2 */
 611                 case RADEON_HPD_5:
 612                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 613                                 connected = true;
 614                         break;
 615                 case RADEON_HPD_6:
 616                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 617                                 connected = true;
 618                         break;
 619                 default:
 620                         break;
 621                 }
 622         } else {
 623                 switch (hpd) {
 624                 case RADEON_HPD_1:
 625                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 626                                 connected = true;
 627                         break;
 628                 case RADEON_HPD_2:
 629                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 630                                 connected = true;
 631                         break;
 632                 case RADEON_HPD_3:
 633                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 634                                 connected = true;
 635                         break;
 636                 default:
 637                         break;
 638                 }
 639         }
 640         return connected;
 641 }
 642
 643 void r600_hpd_set_polarity(struct radeon_device *rdev,
 644                            enum radeon_hpd_id hpd)
 645 {
 646         u32 tmp;
 647         bool connected = r600_hpd_sense(rdev, hpd);
 648
 649         if (ASIC_IS_DCE3(rdev)) {
 650                 switch (hpd) {
 651                 case RADEON_HPD_1:
 652                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 653                         if (connected)
 654                                 tmp &= ~DC_HPDx_INT_POLARITY;
 655                         else
 656                                 tmp |= DC_HPDx_INT_POLARITY;
 657                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 658                         break;
 659                 case RADEON_HPD_2:
 660                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 661                         if (connected)
 662                                 tmp &= ~DC_HPDx_INT_POLARITY;
 663                         else
 664                                 tmp |= DC_HPDx_INT_POLARITY;
 665                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 666                         break;
 667                 case RADEON_HPD_3:
 668                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 669                         if (connected)
 670                                 tmp &= ~DC_HPDx_INT_POLARITY;
 671                         else
 672                                 tmp |= DC_HPDx_INT_POLARITY;
 673                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 674                         break;
 675                 case RADEON_HPD_4:
 676                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 677                         if (connected)
 678                                 tmp &= ~DC_HPDx_INT_POLARITY;
 679                         else
 680                                 tmp |= DC_HPDx_INT_POLARITY;
 681                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 682                         break;
 683                 case RADEON_HPD_5:
 684                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 685                         if (connected)
 686                                 tmp &= ~DC_HPDx_INT_POLARITY;
 687                         else
 688                                 tmp |= DC_HPDx_INT_POLARITY;
 689                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 690                         break;
 691                         /* DCE 3.2 */
 692                 case RADEON_HPD_6:
 693                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 694                         if (connected)
 695                                 tmp &= ~DC_HPDx_INT_POLARITY;
 696                         else
 697                                 tmp |= DC_HPDx_INT_POLARITY;
 698                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 699                         break;
 700                 default:
 701                         break;
 702                 }
 703         } else {
 704                 switch (hpd) {
 705                 case RADEON_HPD_1:
 706                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 707                         if (connected)
 708                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 709                         else
 710                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 711                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 712                         break;
 713                 case RADEON_HPD_2:
 714                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 715                         if (connected)
 716                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 717                         else
 718                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 719                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 720                         break;
 721                 case RADEON_HPD_3:
 722                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 723                         if (connected)
 724                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 725                         else
 726                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 727                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 728                         break;
 729                 default:
 730                         break;
 731                 }
 732         }
 733 }
 734
 735 void r600_hpd_init(struct radeon_device *rdev)
 736 {
 737         struct drm_device *dev = rdev->ddev;
 738         struct drm_connector *connector;
 739
 740         if (ASIC_IS_DCE3(rdev)) {
 741                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 742                 if (ASIC_IS_DCE32(rdev))
 743                         tmp |= DC_HPDx_EN;
 744
 745                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 746                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 747                         switch (radeon_connector->hpd.hpd) {
 748                         case RADEON_HPD_1:
 749                                 WREG32(DC_HPD1_CONTROL, tmp);
 750                                 rdev->irq.hpd[0] = true;
 751                                 break;
 752                         case RADEON_HPD_2:
 753                                 WREG32(DC_HPD2_CONTROL, tmp);
 754                                 rdev->irq.hpd[1] = true;
 755                                 break;
 756                         case RADEON_HPD_3:
 757                                 WREG32(DC_HPD3_CONTROL, tmp);
 758                                 rdev->irq.hpd[2] = true;
 759                                 break;
 760                         case RADEON_HPD_4:
 761                                 WREG32(DC_HPD4_CONTROL, tmp);
 762                                 rdev->irq.hpd[3] = true;
 763                                 break;
 764                                 /* DCE 3.2 */
 765                         case RADEON_HPD_5:
 766                                 WREG32(DC_HPD5_CONTROL, tmp);
 767                                 rdev->irq.hpd[4] = true;
 768                                 break;
 769                         case RADEON_HPD_6:
 770                                 WREG32(DC_HPD6_CONTROL, tmp);
 771                                 rdev->irq.hpd[5] = true;
 772                                 break;
 773                         default:
 774                                 break;
 775                         }
 776                 }
 777         } else {
 778                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 779                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 780                         switch (radeon_connector->hpd.hpd) {
 781                         case RADEON_HPD_1:
 782                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 783                                 rdev->irq.hpd[0] = true;
 784                                 break;
 785                         case RADEON_HPD_2:
 786                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 787                                 rdev->irq.hpd[1] = true;
 788                                 break;
 789                         case RADEON_HPD_3:
 790                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 791                                 rdev->irq.hpd[2] = true;
 792                                 break;
 793                         default:
 794                                 break;
 795                         }
 796                 }
 797         }
 798         if (rdev->irq.installed)
 799                 r600_irq_set(rdev);
 800 }
 801
 802 void r600_hpd_fini(struct radeon_device *rdev)
 803 {
 804         struct drm_device *dev = rdev->ddev;
 805         struct drm_connector *connector;
 806
 807         if (ASIC_IS_DCE3(rdev)) {
 808                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 809                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 810                         switch (radeon_connector->hpd.hpd) {
 811                         case RADEON_HPD_1:
 812                                 WREG32(DC_HPD1_CONTROL, 0);
 813                                 rdev->irq.hpd[0] = false;
 814                                 break;
 815                         case RADEON_HPD_2:
 816                                 WREG32(DC_HPD2_CONTROL, 0);
 817                                 rdev->irq.hpd[1] = false;
 818                                 break;
 819                         case RADEON_HPD_3:
 820                                 WREG32(DC_HPD3_CONTROL, 0);
 821                                 rdev->irq.hpd[2] = false;
 822                                 break;
 823                         case RADEON_HPD_4:
 824                                 WREG32(DC_HPD4_CONTROL, 0);
 825                                 rdev->irq.hpd[3] = false;
 826                                 break;
 827                                 /* DCE 3.2 */
 828                         case RADEON_HPD_5:
 829                                 WREG32(DC_HPD5_CONTROL, 0);
 830                                 rdev->irq.hpd[4] = false;
 831                                 break;
 832                         case RADEON_HPD_6:
 833                                 WREG32(DC_HPD6_CONTROL, 0);
 834                                 rdev->irq.hpd[5] = false;
 835                                 break;
 836                         default:
 837                                 break;
 838                         }
 839                 }
 840         } else {
 841                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 842                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 843                         switch (radeon_connector->hpd.hpd) {
 844                         case RADEON_HPD_1:
 845                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 846                                 rdev->irq.hpd[0] = false;
 847                                 break;
 848                         case RADEON_HPD_2:
 849                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 850                                 rdev->irq.hpd[1] = false;
 851                                 break;
 852                         case RADEON_HPD_3:
 853                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 854                                 rdev->irq.hpd[2] = false;
 855                                 break;
 856                         default:
 857                                 break;
 858                         }
 859                 }
 860         }
 861 }
 862
 863 /*
 864  * R600 PCIE GART
 865  */
 866 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 867 {
 868         unsigned i;
 869         u32 tmp;
 870
 871         /* flush hdp cache so updates hit vram */
 872         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 873
 874         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 875         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 876         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 877         for (i = 0; i < rdev->usec_timeout; i++) {
 878                 /* read MC_STATUS */
 879                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 880                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 881                 if (tmp == 2) {
 882                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 883                         return;
 884                 }
 885                 if (tmp) {
 886                         return;
 887                 }
 888                 udelay(1);
 889         }
 890 }
 891
 892 int r600_pcie_gart_init(struct radeon_device *rdev)
 893 {
 894         int r;
 895
 896         if (rdev->gart.table.vram.robj) {
 897                 WARN(1, "R600 PCIE GART already initialized.\n");
 898                 return 0;
 899         }
 900         /* Initialize common gart structure */
 901         r = radeon_gart_init(rdev);
 902         if (r)
 903                 return r;
 904         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 905         return radeon_gart_table_vram_alloc(rdev);
 906 }
 907
 908 int r600_pcie_gart_enable(struct radeon_device *rdev)
 909 {
 910         u32 tmp;
 911         int r, i;
 912
 913         if (rdev->gart.table.vram.robj == NULL) {
 914                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 915                 return -EINVAL;
 916         }
 917         r = radeon_gart_table_vram_pin(rdev);
 918         if (r)
 919                 return r;
 920         radeon_gart_restore(rdev);
 921
 922         /* Setup L2 cache */
 923         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 924                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 925                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 926         WREG32(VM_L2_CNTL2, 0);
 927         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 928         /* Setup TLB control */
 929         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 930                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 931                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 932                 ENABLE_WAIT_L2_QUERY;
 933         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 934         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 935         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 936         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 937         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 938         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 939         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 940         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 941         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 942         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 943         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 944         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 945         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 946         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 947         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 948         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 949         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 950         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 951                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 952         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 953                         (u32)(rdev->dummy_page.addr >> 12));
 954         for (i = 1; i < 7; i++)
 955                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 956
 957         r600_pcie_gart_tlb_flush(rdev);
 958         rdev->gart.ready = true;
 959         return 0;
 960 }
 961
 962 void r600_pcie_gart_disable(struct radeon_device *rdev)
 963 {
 964         u32 tmp;
 965         int i, r;
 966
 967         /* Disable all tables */
 968         for (i = 0; i < 7; i++)
 969                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 970
 971         /* Disable L2 cache */
 972         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 973                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 974         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 975         /* Setup L1 TLB control */
 976         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 977                 ENABLE_WAIT_L2_QUERY;
 978         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 979         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 980         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 981         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 982         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 983         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 984         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 985         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 986         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 987         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 988         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 989         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 990         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 991         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 992         if (rdev->gart.table.vram.robj) {
 993                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 994                 if (likely(r == 0)) {
 995                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 996                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 997                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 998                 }
 999         }
1000 }
1001
1002 void r600_pcie_gart_fini(struct radeon_device *rdev)
1003 {
1004         radeon_gart_fini(rdev);
1005         r600_pcie_gart_disable(rdev);
1006         radeon_gart_table_vram_free(rdev);
1007 }
1008
1009 void r600_agp_enable(struct radeon_device *rdev)
1010 {
1011         u32 tmp;
1012         int i;
1013
1014         /* Setup L2 cache */
1015         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1016                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1017                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1018         WREG32(VM_L2_CNTL2, 0);
1019         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1020         /* Setup TLB control */
1021         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1022                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1023                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1024                 ENABLE_WAIT_L2_QUERY;
1025         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1026         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1027         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1028         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1029         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1030         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1031         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1032         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1033         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1034         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1035         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1036         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1037         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1038         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1039         for (i = 0; i < 7; i++)
1040                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1041 }
1042
1043 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1044 {
1045         unsigned i;
1046         u32 tmp;
1047
1048         for (i = 0; i < rdev->usec_timeout; i++) {
1049                 /* read MC_STATUS */
1050                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1051                 if (!tmp)
1052                         return 0;
1053                 udelay(1);
1054         }
1055         return -1;
1056 }
1057
1058 static void r600_mc_program(struct radeon_device *rdev)
1059 {
1060         struct rv515_mc_save save;
1061         u32 tmp;
1062         int i, j;
1063
1064         /* Initialize HDP */
1065         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1066                 WREG32((0x2c14 + j), 0x00000000);
1067                 WREG32((0x2c18 + j), 0x00000000);
1068                 WREG32((0x2c1c + j), 0x00000000);
1069                 WREG32((0x2c20 + j), 0x00000000);
1070                 WREG32((0x2c24 + j), 0x00000000);
1071         }
1072         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1073
1074         rv515_mc_stop(rdev, &save);
1075         if (r600_mc_wait_for_idle(rdev)) {
1076                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1077         }
1078         /* Lockout access through VGA aperture (doesn't exist before R600) */
1079         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1080         /* Update configuration */
1081         if (rdev->flags & RADEON_IS_AGP) {
1082                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1083                         /* VRAM before AGP */
1084                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1085                                 rdev->mc.vram_start >> 12);
1086                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1087                                 rdev->mc.gtt_end >> 12);
1088                 } else {
1089                         /* VRAM after AGP */
1090                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1091                                 rdev->mc.gtt_start >> 12);
1092                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1093                                 rdev->mc.vram_end >> 12);
1094                 }
1095         } else {
1096                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1097                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1098         }
1099         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1100         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1101         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1102         WREG32(MC_VM_FB_LOCATION, tmp);
1103         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1104         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1105         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1106         if (rdev->flags & RADEON_IS_AGP) {
1107                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1108                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1109                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1110         } else {
1111                 WREG32(MC_VM_AGP_BASE, 0);
1112                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1113                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1114         }
1115         if (r600_mc_wait_for_idle(rdev)) {
1116                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1117         }
1118         rv515_mc_resume(rdev, &save);
1119         /* we need to own VRAM, so turn off the VGA renderer here
1120          * to stop it overwriting our objects */
1121         rv515_vga_render_disable(rdev);
1122 }
1123
1124 /**
1125  * r600_vram_gtt_location - try to find VRAM & GTT location
1126  * @rdev: radeon device structure holding all necessary informations
1127  * @mc: memory controller structure holding memory informations
1128  *
1129  * Function will place try to place VRAM at same place as in CPU (PCI)
1130  * address space as some GPU seems to have issue when we reprogram at
1131  * different address space.
1132  *
1133  * If there is not enough space to fit the unvisible VRAM after the
1134  * aperture then we limit the VRAM size to the aperture.
1135  *
1136  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1137  * them to be in one from GPU point of view so that we can program GPU to
1138  * catch access outside them (weird GPU policy see ??).
1139  *
1140  * This function will never fails, worst case are limiting VRAM or GTT.
1141  *
1142  * Note: GTT start, end, size should be initialized before calling this
1143  * function on AGP platform.
1144  */
1145 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1146 {
1147         u64 size_bf, size_af;
1148
1149         if (mc->mc_vram_size > 0xE0000000) {
1150                 /* leave room for at least 512M GTT */
1151                 dev_warn(rdev->dev, "limiting VRAM\n");
1152                 mc->real_vram_size = 0xE0000000;
1153                 mc->mc_vram_size = 0xE0000000;
1154         }
1155         if (rdev->flags & RADEON_IS_AGP) {
1156                 size_bf = mc->gtt_start;
1157                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1158                 if (size_bf > size_af) {
1159                         if (mc->mc_vram_size > size_bf) {
1160                                 dev_warn(rdev->dev, "limiting VRAM\n");
1161                                 mc->real_vram_size = size_bf;
1162                                 mc->mc_vram_size = size_bf;
1163                         }
1164                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1165                 } else {
1166                         if (mc->mc_vram_size > size_af) {
1167                                 dev_warn(rdev->dev, "limiting VRAM\n");
1168                                 mc->real_vram_size = size_af;
1169                                 mc->mc_vram_size = size_af;
1170                         }
1171                         mc->vram_start = mc->gtt_end;
1172                 }
1173                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1174                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1175                                 mc->mc_vram_size >> 20, mc->vram_start,
1176                                 mc->vram_end, mc->real_vram_size >> 20);
1177         } else {
1178                 u64 base = 0;
1179                 if (rdev->flags & RADEON_IS_IGP)
1180                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1181                 radeon_vram_location(rdev, &rdev->mc, base);
1182                 rdev->mc.gtt_base_align = 0;
1183                 radeon_gtt_location(rdev, mc);
1184         }
1185 }
1186
1187 int r600_mc_init(struct radeon_device *rdev)
1188 {
1189         u32 tmp;
1190         int chansize, numchan;
1191
1192         /* Get VRAM informations */
1193         rdev->mc.vram_is_ddr = true;
1194         tmp = RREG32(RAMCFG);
1195         if (tmp & CHANSIZE_OVERRIDE) {
1196                 chansize = 16;
1197         } else if (tmp & CHANSIZE_MASK) {
1198                 chansize = 64;
1199         } else {
1200                 chansize = 32;
1201         }
1202         tmp = RREG32(CHMAP);
1203         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1204         case 0:
1205         default:
1206                 numchan = 1;
1207                 break;
1208         case 1:
1209                 numchan = 2;
1210                 break;
1211         case 2:
1212                 numchan = 4;
1213                 break;
1214         case 3:
1215                 numchan = 8;
1216                 break;
1217         }
1218         rdev->mc.vram_width = numchan * chansize;
1219         /* Could aper size report 0 ? */
1220         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1221         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1222         /* Setup GPU memory space */
1223         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1224         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1225         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1226         r600_vram_gtt_location(rdev, &rdev->mc);
1227
1228         if (rdev->flags & RADEON_IS_IGP) {
1229                 rs690_pm_info(rdev);
1230                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1231         }
1232         radeon_update_bandwidth_info(rdev);
1233         return 0;
1234 }
1235
1236 /* We doesn't check that the GPU really needs a reset we simply do the
1237  * reset, it's up to the caller to determine if the GPU needs one. We
1238  * might add an helper function to check that.
1239  */
1240 int r600_gpu_soft_reset(struct radeon_device *rdev)
1241 {
1242         struct rv515_mc_save save;
1243         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1244                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1245                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1246                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1247                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1248                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1249                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1250                                 S_008010_GUI_ACTIVE(1);
1251         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1252                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1253                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1254                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1255                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1256                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1257                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1258                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1259         u32 tmp;
1260
1261         dev_info(rdev->dev, "GPU softreset \n");
1262         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1263                 RREG32(R_008010_GRBM_STATUS));
1264         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1265                 RREG32(R_008014_GRBM_STATUS2));
1266         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1267                 RREG32(R_000E50_SRBM_STATUS));
1268         rv515_mc_stop(rdev, &save);
1269         if (r600_mc_wait_for_idle(rdev)) {
1270                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1271         }
1272         /* Disable CP parsing/prefetching */
1273         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1274         /* Check if any of the rendering block is busy and reset it */
1275         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1276             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1277                 tmp = S_008020_SOFT_RESET_CR(1) |
1278                         S_008020_SOFT_RESET_DB(1) |
1279                         S_008020_SOFT_RESET_CB(1) |
1280                         S_008020_SOFT_RESET_PA(1) |
1281                         S_008020_SOFT_RESET_SC(1) |
1282                         S_008020_SOFT_RESET_SMX(1) |
1283                         S_008020_SOFT_RESET_SPI(1) |
1284                         S_008020_SOFT_RESET_SX(1) |
1285                         S_008020_SOFT_RESET_SH(1) |
1286                         S_008020_SOFT_RESET_TC(1) |
1287                         S_008020_SOFT_RESET_TA(1) |
1288                         S_008020_SOFT_RESET_VC(1) |
1289                         S_008020_SOFT_RESET_VGT(1);
1290                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1291                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1292                 RREG32(R_008020_GRBM_SOFT_RESET);
1293                 mdelay(15);
1294                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1295         }
1296         /* Reset CP (we always reset CP) */
1297         tmp = S_008020_SOFT_RESET_CP(1);
1298         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1299         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1300         RREG32(R_008020_GRBM_SOFT_RESET);
1301         mdelay(15);
1302         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1303         /* Wait a little for things to settle down */
1304         mdelay(1);
1305         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1306                 RREG32(R_008010_GRBM_STATUS));
1307         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1308                 RREG32(R_008014_GRBM_STATUS2));
1309         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1310                 RREG32(R_000E50_SRBM_STATUS));
1311         rv515_mc_resume(rdev, &save);
1312         return 0;
1313 }
1314
1315 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1316 {
1317         u32 srbm_status;
1318         u32 grbm_status;
1319         u32 grbm_status2;
1320         int r;
1321
1322         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1323         grbm_status = RREG32(R_008010_GRBM_STATUS);
1324         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1325         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1326                 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1327                 return false;
1328         }
1329         /* force CP activities */
1330         r = radeon_ring_lock(rdev, 2);
1331         if (!r) {
1332                 /* PACKET2 NOP */
1333                 radeon_ring_write(rdev, 0x80000000);
1334                 radeon_ring_write(rdev, 0x80000000);
1335                 radeon_ring_unlock_commit(rdev);
1336         }
1337         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1338         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1339 }
1340
1341 int r600_asic_reset(struct radeon_device *rdev)
1342 {
1343         return r600_gpu_soft_reset(rdev);
1344 }
1345
1346 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1347                                              u32 num_backends,
1348                                              u32 backend_disable_mask)
1349 {
1350         u32 backend_map = 0;
1351         u32 enabled_backends_mask;
1352         u32 enabled_backends_count;
1353         u32 cur_pipe;
1354         u32 swizzle_pipe[R6XX_MAX_PIPES];
1355         u32 cur_backend;
1356         u32 i;
1357
1358         if (num_tile_pipes > R6XX_MAX_PIPES)
1359                 num_tile_pipes = R6XX_MAX_PIPES;
1360         if (num_tile_pipes < 1)
1361                 num_tile_pipes = 1;
1362         if (num_backends > R6XX_MAX_BACKENDS)
1363                 num_backends = R6XX_MAX_BACKENDS;
1364         if (num_backends < 1)
1365                 num_backends = 1;
1366
1367         enabled_backends_mask = 0;
1368         enabled_backends_count = 0;
1369         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1370                 if (((backend_disable_mask >> i) & 1) == 0) {
1371                         enabled_backends_mask |= (1 << i);
1372                         ++enabled_backends_count;
1373                 }
1374                 if (enabled_backends_count == num_backends)
1375                         break;
1376         }
1377
1378         if (enabled_backends_count == 0) {
1379                 enabled_backends_mask = 1;
1380                 enabled_backends_count = 1;
1381         }
1382
1383         if (enabled_backends_count != num_backends)
1384                 num_backends = enabled_backends_count;
1385
1386         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1387         switch (num_tile_pipes) {
1388         case 1:
1389                 swizzle_pipe[0] = 0;
1390                 break;
1391         case 2:
1392                 swizzle_pipe[0] = 0;
1393                 swizzle_pipe[1] = 1;
1394                 break;
1395         case 3:
1396                 swizzle_pipe[0] = 0;
1397                 swizzle_pipe[1] = 1;
1398                 swizzle_pipe[2] = 2;
1399                 break;
1400         case 4:
1401                 swizzle_pipe[0] = 0;
1402                 swizzle_pipe[1] = 1;
1403                 swizzle_pipe[2] = 2;
1404                 swizzle_pipe[3] = 3;
1405                 break;
1406         case 5:
1407                 swizzle_pipe[0] = 0;
1408                 swizzle_pipe[1] = 1;
1409                 swizzle_pipe[2] = 2;
1410                 swizzle_pipe[3] = 3;
1411                 swizzle_pipe[4] = 4;
1412                 break;
1413         case 6:
1414                 swizzle_pipe[0] = 0;
1415                 swizzle_pipe[1] = 2;
1416                 swizzle_pipe[2] = 4;
1417                 swizzle_pipe[3] = 5;
1418                 swizzle_pipe[4] = 1;
1419                 swizzle_pipe[5] = 3;
1420                 break;
1421         case 7:
1422                 swizzle_pipe[0] = 0;
1423                 swizzle_pipe[1] = 2;
1424                 swizzle_pipe[2] = 4;
1425                 swizzle_pipe[3] = 6;
1426                 swizzle_pipe[4] = 1;
1427                 swizzle_pipe[5] = 3;
1428                 swizzle_pipe[6] = 5;
1429                 break;
1430         case 8:
1431                 swizzle_pipe[0] = 0;
1432                 swizzle_pipe[1] = 2;
1433                 swizzle_pipe[2] = 4;
1434                 swizzle_pipe[3] = 6;
1435                 swizzle_pipe[4] = 1;
1436                 swizzle_pipe[5] = 3;
1437                 swizzle_pipe[6] = 5;
1438                 swizzle_pipe[7] = 7;
1439                 break;
1440         }
1441
1442         cur_backend = 0;
1443         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1444                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1445                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1446
1447                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1448
1449                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1450         }
1451
1452         return backend_map;
1453 }
1454
1455 int r600_count_pipe_bits(uint32_t val)
1456 {
1457         int i, ret = 0;
1458
1459         for (i = 0; i < 32; i++) {
1460                 ret += val & 1;
1461                 val >>= 1;
1462         }
1463         return ret;
1464 }
1465
1466 void r600_gpu_init(struct radeon_device *rdev)
1467 {
1468         u32 tiling_config;
1469         u32 ramcfg;
1470         u32 backend_map;
1471         u32 cc_rb_backend_disable;
1472         u32 cc_gc_shader_pipe_config;
1473         u32 tmp;
1474         int i, j;
1475         u32 sq_config;
1476         u32 sq_gpr_resource_mgmt_1 = 0;
1477         u32 sq_gpr_resource_mgmt_2 = 0;
1478         u32 sq_thread_resource_mgmt = 0;
1479         u32 sq_stack_resource_mgmt_1 = 0;
1480         u32 sq_stack_resource_mgmt_2 = 0;
1481
1482         /* FIXME: implement */
1483         switch (rdev->family) {
1484         case CHIP_R600:
1485                 rdev->config.r600.max_pipes = 4;
1486                 rdev->config.r600.max_tile_pipes = 8;
1487                 rdev->config.r600.max_simds = 4;
1488                 rdev->config.r600.max_backends = 4;
1489                 rdev->config.r600.max_gprs = 256;
1490                 rdev->config.r600.max_threads = 192;
1491                 rdev->config.r600.max_stack_entries = 256;
1492                 rdev->config.r600.max_hw_contexts = 8;
1493                 rdev->config.r600.max_gs_threads = 16;
1494                 rdev->config.r600.sx_max_export_size = 128;
1495                 rdev->config.r600.sx_max_export_pos_size = 16;
1496                 rdev->config.r600.sx_max_export_smx_size = 128;
1497                 rdev->config.r600.sq_num_cf_insts = 2;
1498                 break;
1499         case CHIP_RV630:
1500         case CHIP_RV635:
1501                 rdev->config.r600.max_pipes = 2;
1502                 rdev->config.r600.max_tile_pipes = 2;
1503                 rdev->config.r600.max_simds = 3;
1504                 rdev->config.r600.max_backends = 1;
1505                 rdev->config.r600.max_gprs = 128;
1506                 rdev->config.r600.max_threads = 192;
1507                 rdev->config.r600.max_stack_entries = 128;
1508                 rdev->config.r600.max_hw_contexts = 8;
1509                 rdev->config.r600.max_gs_threads = 4;
1510                 rdev->config.r600.sx_max_export_size = 128;
1511                 rdev->config.r600.sx_max_export_pos_size = 16;
1512                 rdev->config.r600.sx_max_export_smx_size = 128;
1513                 rdev->config.r600.sq_num_cf_insts = 2;
1514                 break;
1515         case CHIP_RV610:
1516         case CHIP_RV620:
1517         case CHIP_RS780:
1518         case CHIP_RS880:
1519                 rdev->config.r600.max_pipes = 1;
1520                 rdev->config.r600.max_tile_pipes = 1;
1521                 rdev->config.r600.max_simds = 2;
1522                 rdev->config.r600.max_backends = 1;
1523                 rdev->config.r600.max_gprs = 128;
1524                 rdev->config.r600.max_threads = 192;
1525                 rdev->config.r600.max_stack_entries = 128;
1526                 rdev->config.r600.max_hw_contexts = 4;
1527                 rdev->config.r600.max_gs_threads = 4;
1528                 rdev->config.r600.sx_max_export_size = 128;
1529                 rdev->config.r600.sx_max_export_pos_size = 16;
1530                 rdev->config.r600.sx_max_export_smx_size = 128;
1531                 rdev->config.r600.sq_num_cf_insts = 1;
1532                 break;
1533         case CHIP_RV670:
1534                 rdev->config.r600.max_pipes = 4;
1535                 rdev->config.r600.max_tile_pipes = 4;
1536                 rdev->config.r600.max_simds = 4;
1537                 rdev->config.r600.max_backends = 4;
1538                 rdev->config.r600.max_gprs = 192;
1539                 rdev->config.r600.max_threads = 192;
1540                 rdev->config.r600.max_stack_entries = 256;
1541                 rdev->config.r600.max_hw_contexts = 8;
1542                 rdev->config.r600.max_gs_threads = 16;
1543                 rdev->config.r600.sx_max_export_size = 128;
1544                 rdev->config.r600.sx_max_export_pos_size = 16;
1545                 rdev->config.r600.sx_max_export_smx_size = 128;
1546                 rdev->config.r600.sq_num_cf_insts = 2;
1547                 break;
1548         default:
1549                 break;
1550         }
1551
1552         /* Initialize HDP */
1553         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1554                 WREG32((0x2c14 + j), 0x00000000);
1555                 WREG32((0x2c18 + j), 0x00000000);
1556                 WREG32((0x2c1c + j), 0x00000000);
1557                 WREG32((0x2c20 + j), 0x00000000);
1558                 WREG32((0x2c24 + j), 0x00000000);
1559         }
1560
1561         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1562
1563         /* Setup tiling */
1564         tiling_config = 0;
1565         ramcfg = RREG32(RAMCFG);
1566         switch (rdev->config.r600.max_tile_pipes) {
1567         case 1:
1568                 tiling_config |= PIPE_TILING(0);
1569                 break;
1570         case 2:
1571                 tiling_config |= PIPE_TILING(1);
1572                 break;
1573         case 4:
1574                 tiling_config |= PIPE_TILING(2);
1575                 break;
1576         case 8:
1577                 tiling_config |= PIPE_TILING(3);
1578                 break;
1579         default:
1580                 break;
1581         }
1582         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1583         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1584         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1585         tiling_config |= GROUP_SIZE(0);
1586         rdev->config.r600.tiling_group_size = 256;
1587         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1588         if (tmp > 3) {
1589                 tiling_config |= ROW_TILING(3);
1590                 tiling_config |= SAMPLE_SPLIT(3);
1591         } else {
1592                 tiling_config |= ROW_TILING(tmp);
1593                 tiling_config |= SAMPLE_SPLIT(tmp);
1594         }
1595         tiling_config |= BANK_SWAPS(1);
1596
1597         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1598         cc_rb_backend_disable |=
1599                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1600
1601         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1602         cc_gc_shader_pipe_config |=
1603                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1604         cc_gc_shader_pipe_config |=
1605                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1606
1607         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1608                                                         (R6XX_MAX_BACKENDS -
1609                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1610                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1611                                                         (cc_rb_backend_disable >> 16));
1612
1613         tiling_config |= BACKEND_MAP(backend_map);
1614         WREG32(GB_TILING_CONFIG, tiling_config);
1615         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1616         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1617
1618         /* Setup pipes */
1619         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1620         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1621         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1622
1623         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1624         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1625         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1626
1627         /* Setup some CP states */
1628         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1629         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1630
1631         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1632                              SYNC_WALKER | SYNC_ALIGNER));
1633         /* Setup various GPU states */
1634         if (rdev->family == CHIP_RV670)
1635                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1636
1637         tmp = RREG32(SX_DEBUG_1);
1638         tmp |= SMX_EVENT_RELEASE;
1639         if ((rdev->family > CHIP_R600))
1640                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1641         WREG32(SX_DEBUG_1, tmp);
1642
1643         if (((rdev->family) == CHIP_R600) ||
1644             ((rdev->family) == CHIP_RV630) ||
1645             ((rdev->family) == CHIP_RV610) ||
1646             ((rdev->family) == CHIP_RV620) ||
1647             ((rdev->family) == CHIP_RS780) ||
1648             ((rdev->family) == CHIP_RS880)) {
1649                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1650         } else {
1651                 WREG32(DB_DEBUG, 0);
1652         }
1653         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1654                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1655
1656         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1657         WREG32(VGT_NUM_INSTANCES, 0);
1658
1659         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1660         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1661
1662         tmp = RREG32(SQ_MS_FIFO_SIZES);
1663         if (((rdev->family) == CHIP_RV610) ||
1664             ((rdev->family) == CHIP_RV620) ||
1665             ((rdev->family) == CHIP_RS780) ||
1666             ((rdev->family) == CHIP_RS880)) {
1667                 tmp = (CACHE_FIFO_SIZE(0xa) |
1668                        FETCH_FIFO_HIWATER(0xa) |
1669                        DONE_FIFO_HIWATER(0xe0) |
1670                        ALU_UPDATE_FIFO_HIWATER(0x8));
1671         } else if (((rdev->family) == CHIP_R600) ||
1672                    ((rdev->family) == CHIP_RV630)) {
1673                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1674                 tmp |= DONE_FIFO_HIWATER(0x4);
1675         }
1676         WREG32(SQ_MS_FIFO_SIZES, tmp);
1677
1678         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1679          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1680          */
1681         sq_config = RREG32(SQ_CONFIG);
1682         sq_config &= ~(PS_PRIO(3) |
1683                        VS_PRIO(3) |
1684                        GS_PRIO(3) |
1685                        ES_PRIO(3));
1686         sq_config |= (DX9_CONSTS |
1687                       VC_ENABLE |
1688                       PS_PRIO(0) |
1689                       VS_PRIO(1) |
1690                       GS_PRIO(2) |
1691                       ES_PRIO(3));
1692
1693         if ((rdev->family) == CHIP_R600) {
1694                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1695                                           NUM_VS_GPRS(124) |
1696                                           NUM_CLAUSE_TEMP_GPRS(4));
1697                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1698                                           NUM_ES_GPRS(0));
1699                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1700                                            NUM_VS_THREADS(48) |
1701                                            NUM_GS_THREADS(4) |
1702                                            NUM_ES_THREADS(4));
1703                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1704                                             NUM_VS_STACK_ENTRIES(128));
1705                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1706                                             NUM_ES_STACK_ENTRIES(0));
1707         } else if (((rdev->family) == CHIP_RV610) ||
1708                    ((rdev->family) == CHIP_RV620) ||
1709                    ((rdev->family) == CHIP_RS780) ||
1710                    ((rdev->family) == CHIP_RS880)) {
1711                 /* no vertex cache */
1712                 sq_config &= ~VC_ENABLE;
1713
1714                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1715                                           NUM_VS_GPRS(44) |
1716                                           NUM_CLAUSE_TEMP_GPRS(2));
1717                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1718                                           NUM_ES_GPRS(17));
1719                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1720                                            NUM_VS_THREADS(78) |
1721                                            NUM_GS_THREADS(4) |
1722                                            NUM_ES_THREADS(31));
1723                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1724                                             NUM_VS_STACK_ENTRIES(40));
1725                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1726                                             NUM_ES_STACK_ENTRIES(16));
1727         } else if (((rdev->family) == CHIP_RV630) ||
1728                    ((rdev->family) == CHIP_RV635)) {
1729                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1730                                           NUM_VS_GPRS(44) |
1731                                           NUM_CLAUSE_TEMP_GPRS(2));
1732                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1733                                           NUM_ES_GPRS(18));
1734                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1735                                            NUM_VS_THREADS(78) |
1736                                            NUM_GS_THREADS(4) |
1737                                            NUM_ES_THREADS(31));
1738                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1739                                             NUM_VS_STACK_ENTRIES(40));
1740                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1741                                             NUM_ES_STACK_ENTRIES(16));
1742         } else if ((rdev->family) == CHIP_RV670) {
1743                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1744                                           NUM_VS_GPRS(44) |
1745                                           NUM_CLAUSE_TEMP_GPRS(2));
1746                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1747                                           NUM_ES_GPRS(17));
1748                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1749                                            NUM_VS_THREADS(78) |
1750                                            NUM_GS_THREADS(4) |
1751                                            NUM_ES_THREADS(31));
1752                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1753                                             NUM_VS_STACK_ENTRIES(64));
1754                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1755                                             NUM_ES_STACK_ENTRIES(64));
1756         }
1757
1758         WREG32(SQ_CONFIG, sq_config);
1759         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1760         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1761         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1762         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1763         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1764
1765         if (((rdev->family) == CHIP_RV610) ||
1766             ((rdev->family) == CHIP_RV620) ||
1767             ((rdev->family) == CHIP_RS780) ||
1768             ((rdev->family) == CHIP_RS880)) {
1769                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1770         } else {
1771                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1772         }
1773
1774         /* More default values. 2D/3D driver should adjust as needed */
1775         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1776                                          S1_X(0x4) | S1_Y(0xc)));
1777         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1778                                          S1_X(0x2) | S1_Y(0x2) |
1779                                          S2_X(0xa) | S2_Y(0x6) |
1780                                          S3_X(0x6) | S3_Y(0xa)));
1781         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1782                                              S1_X(0x4) | S1_Y(0xc) |
1783                                              S2_X(0x1) | S2_Y(0x6) |
1784                                              S3_X(0xa) | S3_Y(0xe)));
1785         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1786                                              S5_X(0x0) | S5_Y(0x0) |
1787                                              S6_X(0xb) | S6_Y(0x4) |
1788                                              S7_X(0x7) | S7_Y(0x8)));
1789
1790         WREG32(VGT_STRMOUT_EN, 0);
1791         tmp = rdev->config.r600.max_pipes * 16;
1792         switch (rdev->family) {
1793         case CHIP_RV610:
1794         case CHIP_RV620:
1795         case CHIP_RS780:
1796         case CHIP_RS880:
1797                 tmp += 32;
1798                 break;
1799         case CHIP_RV670:
1800                 tmp += 128;
1801                 break;
1802         default:
1803                 break;
1804         }
1805         if (tmp > 256) {
1806                 tmp = 256;
1807         }
1808         WREG32(VGT_ES_PER_GS, 128);
1809         WREG32(VGT_GS_PER_ES, tmp);
1810         WREG32(VGT_GS_PER_VS, 2);
1811         WREG32(VGT_GS_VERTEX_REUSE, 16);
1812
1813         /* more default values. 2D/3D driver should adjust as needed */
1814         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1815         WREG32(VGT_STRMOUT_EN, 0);
1816         WREG32(SX_MISC, 0);
1817         WREG32(PA_SC_MODE_CNTL, 0);
1818         WREG32(PA_SC_AA_CONFIG, 0);
1819         WREG32(PA_SC_LINE_STIPPLE, 0);
1820         WREG32(SPI_INPUT_Z, 0);
1821         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1822         WREG32(CB_COLOR7_FRAG, 0);
1823
1824         /* Clear render buffer base addresses */
1825         WREG32(CB_COLOR0_BASE, 0);
1826         WREG32(CB_COLOR1_BASE, 0);
1827         WREG32(CB_COLOR2_BASE, 0);
1828         WREG32(CB_COLOR3_BASE, 0);
1829         WREG32(CB_COLOR4_BASE, 0);
1830         WREG32(CB_COLOR5_BASE, 0);
1831         WREG32(CB_COLOR6_BASE, 0);
1832         WREG32(CB_COLOR7_BASE, 0);
1833         WREG32(CB_COLOR7_FRAG, 0);
1834
1835         switch (rdev->family) {
1836         case CHIP_RV610:
1837         case CHIP_RV620:
1838         case CHIP_RS780:
1839         case CHIP_RS880:
1840                 tmp = TC_L2_SIZE(8);
1841                 break;
1842         case CHIP_RV630:
1843         case CHIP_RV635:
1844                 tmp = TC_L2_SIZE(4);
1845                 break;
1846         case CHIP_R600:
1847                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1848                 break;
1849         default:
1850                 tmp = TC_L2_SIZE(0);
1851                 break;
1852         }
1853         WREG32(TC_CNTL, tmp);
1854
1855         tmp = RREG32(HDP_HOST_PATH_CNTL);
1856         WREG32(HDP_HOST_PATH_CNTL, tmp);
1857
1858         tmp = RREG32(ARB_POP);
1859         tmp |= ENABLE_TC128;
1860         WREG32(ARB_POP, tmp);
1861
1862         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1863         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1864                                NUM_CLIP_SEQ(3)));
1865         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1866 }
1867
1868
1869 /*
1870  * Indirect registers accessor
1871  */
1872 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1873 {
1874         u32 r;
1875
1876         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1877         (void)RREG32(PCIE_PORT_INDEX);
1878         r = RREG32(PCIE_PORT_DATA);
1879         return r;
1880 }
1881
1882 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1883 {
1884         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1885         (void)RREG32(PCIE_PORT_INDEX);
1886         WREG32(PCIE_PORT_DATA, (v));
1887         (void)RREG32(PCIE_PORT_DATA);
1888 }
1889
1890 /*
1891  * CP & Ring
1892  */
1893 void r600_cp_stop(struct radeon_device *rdev)
1894 {
1895         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1896 }
1897
1898 int r600_init_microcode(struct radeon_device *rdev)
1899 {
1900         struct platform_device *pdev;
1901         const char *chip_name;
1902         const char *rlc_chip_name;
1903         size_t pfp_req_size, me_req_size, rlc_req_size;
1904         char fw_name[30];
1905         int err;
1906
1907         DRM_DEBUG("\n");
1908
1909         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1910         err = IS_ERR(pdev);
1911         if (err) {
1912                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1913                 return -EINVAL;
1914         }
1915
1916         switch (rdev->family) {
1917         case CHIP_R600:
1918                 chip_name = "R600";
1919                 rlc_chip_name = "R600";
1920                 break;
1921         case CHIP_RV610:
1922                 chip_name = "RV610";
1923                 rlc_chip_name = "R600";
1924                 break;
1925         case CHIP_RV630:
1926                 chip_name = "RV630";
1927                 rlc_chip_name = "R600";
1928                 break;
1929         case CHIP_RV620:
1930                 chip_name = "RV620";
1931                 rlc_chip_name = "R600";
1932                 break;
1933         case CHIP_RV635:
1934                 chip_name = "RV635";
1935                 rlc_chip_name = "R600";
1936                 break;
1937         case CHIP_RV670:
1938                 chip_name = "RV670";
1939                 rlc_chip_name = "R600";
1940                 break;
1941         case CHIP_RS780:
1942         case CHIP_RS880:
1943                 chip_name = "RS780";
1944                 rlc_chip_name = "R600";
1945                 break;
1946         case CHIP_RV770:
1947                 chip_name = "RV770";
1948                 rlc_chip_name = "R700";
1949                 break;
1950         case CHIP_RV730:
1951         case CHIP_RV740:
1952                 chip_name = "RV730";
1953                 rlc_chip_name = "R700";
1954                 break;
1955         case CHIP_RV710:
1956                 chip_name = "RV710";
1957                 rlc_chip_name = "R700";
1958                 break;
1959         case CHIP_CEDAR:
1960                 chip_name = "CEDAR";
1961                 rlc_chip_name = "CEDAR";
1962                 break;
1963         case CHIP_REDWOOD:
1964                 chip_name = "REDWOOD";
1965                 rlc_chip_name = "REDWOOD";
1966                 break;
1967         case CHIP_JUNIPER:
1968                 chip_name = "JUNIPER";
1969                 rlc_chip_name = "JUNIPER";
1970                 break;
1971         case CHIP_CYPRESS:
1972         case CHIP_HEMLOCK:
1973                 chip_name = "CYPRESS";
1974                 rlc_chip_name = "CYPRESS";
1975                 break;
1976         default: BUG();
1977         }
1978
1979         if (rdev->family >= CHIP_CEDAR) {
1980                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1981                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
1982                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
1983         } else if (rdev->family >= CHIP_RV770) {
1984                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1985                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1986                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1987         } else {
1988                 pfp_req_size = PFP_UCODE_SIZE * 4;
1989                 me_req_size = PM4_UCODE_SIZE * 12;
1990                 rlc_req_size = RLC_UCODE_SIZE * 4;
1991         }
1992
1993         DRM_INFO("Loading %s Microcode\n", chip_name);
1994
1995         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1996         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1997         if (err)
1998                 goto out;
1999         if (rdev->pfp_fw->size != pfp_req_size) {
2000                 printk(KERN_ERR
2001                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2002                        rdev->pfp_fw->size, fw_name);
2003                 err = -EINVAL;
2004                 goto out;
2005         }
2006
2007         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2008         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2009         if (err)
2010                 goto out;
2011         if (rdev->me_fw->size != me_req_size) {
2012                 printk(KERN_ERR
2013                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2014                        rdev->me_fw->size, fw_name);
2015                 err = -EINVAL;
2016         }
2017
2018         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2019         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2020         if (err)
2021                 goto out;
2022         if (rdev->rlc_fw->size != rlc_req_size) {
2023                 printk(KERN_ERR
2024                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2025                        rdev->rlc_fw->size, fw_name);
2026                 err = -EINVAL;
2027         }
2028
2029 out:
2030         platform_device_unregister(pdev);
2031
2032         if (err) {
2033                 if (err != -EINVAL)
2034                         printk(KERN_ERR
2035                                "r600_cp: Failed to load firmware \"%s\"\n",
2036                                fw_name);
2037                 release_firmware(rdev->pfp_fw);
2038                 rdev->pfp_fw = NULL;
2039                 release_firmware(rdev->me_fw);
2040                 rdev->me_fw = NULL;
2041                 release_firmware(rdev->rlc_fw);
2042                 rdev->rlc_fw = NULL;
2043         }
2044         return err;
2045 }
2046
2047 static int r600_cp_load_microcode(struct radeon_device *rdev)
2048 {
2049         const __be32 *fw_data;
2050         int i;
2051
2052         if (!rdev->me_fw || !rdev->pfp_fw)
2053                 return -EINVAL;
2054
2055         r600_cp_stop(rdev);
2056
2057         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2058
2059         /* Reset cp */
2060         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2061         RREG32(GRBM_SOFT_RESET);
2062         mdelay(15);
2063         WREG32(GRBM_SOFT_RESET, 0);
2064
2065         WREG32(CP_ME_RAM_WADDR, 0);
2066
2067         fw_data = (const __be32 *)rdev->me_fw->data;
2068         WREG32(CP_ME_RAM_WADDR, 0);
2069         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2070                 WREG32(CP_ME_RAM_DATA,
2071                        be32_to_cpup(fw_data++));
2072
2073         fw_data = (const __be32 *)rdev->pfp_fw->data;
2074         WREG32(CP_PFP_UCODE_ADDR, 0);
2075         for (i = 0; i < PFP_UCODE_SIZE; i++)
2076                 WREG32(CP_PFP_UCODE_DATA,
2077                        be32_to_cpup(fw_data++));
2078
2079         WREG32(CP_PFP_UCODE_ADDR, 0);
2080         WREG32(CP_ME_RAM_WADDR, 0);
2081         WREG32(CP_ME_RAM_RADDR, 0);
2082         return 0;
2083 }
2084
2085 int r600_cp_start(struct radeon_device *rdev)
2086 {
2087         int r;
2088         uint32_t cp_me;
2089
2090         r = radeon_ring_lock(rdev, 7);
2091         if (r) {
2092                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2093                 return r;
2094         }
2095         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2096         radeon_ring_write(rdev, 0x1);
2097         if (rdev->family >= CHIP_CEDAR) {
2098                 radeon_ring_write(rdev, 0x0);
2099                 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
2100         } else if (rdev->family >= CHIP_RV770) {
2101                 radeon_ring_write(rdev, 0x0);
2102                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2103         } else {
2104                 radeon_ring_write(rdev, 0x3);
2105                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2106         }
2107         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2108         radeon_ring_write(rdev, 0);
2109         radeon_ring_write(rdev, 0);
2110         radeon_ring_unlock_commit(rdev);
2111
2112         cp_me = 0xff;
2113         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2114         return 0;
2115 }
2116
2117 int r600_cp_resume(struct radeon_device *rdev)
2118 {
2119         u32 tmp;
2120         u32 rb_bufsz;
2121         int r;
2122
2123         /* Reset cp */
2124         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2125         RREG32(GRBM_SOFT_RESET);
2126         mdelay(15);
2127         WREG32(GRBM_SOFT_RESET, 0);
2128
2129         /* Set ring buffer size */
2130         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2131         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2132 #ifdef __BIG_ENDIAN
2133         tmp |= BUF_SWAP_32BIT;
2134 #endif
2135         WREG32(CP_RB_CNTL, tmp);
2136         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2137
2138         /* Set the write pointer delay */
2139         WREG32(CP_RB_WPTR_DELAY, 0);
2140
2141         /* Initialize the ring buffer's read and write pointers */
2142         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2143         WREG32(CP_RB_RPTR_WR, 0);
2144         WREG32(CP_RB_WPTR, 0);
2145         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
2146         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
2147         mdelay(1);
2148         WREG32(CP_RB_CNTL, tmp);
2149
2150         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2151         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2152
2153         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2154         rdev->cp.wptr = RREG32(CP_RB_WPTR);
2155
2156         r600_cp_start(rdev);
2157         rdev->cp.ready = true;
2158         r = radeon_ring_test(rdev);
2159         if (r) {
2160                 rdev->cp.ready = false;
2161                 return r;
2162         }
2163         return 0;
2164 }
2165
2166 void r600_cp_commit(struct radeon_device *rdev)
2167 {
2168         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2169         (void)RREG32(CP_RB_WPTR);
2170 }
2171
2172 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2173 {
2174         u32 rb_bufsz;
2175
2176         /* Align ring size */
2177         rb_bufsz = drm_order(ring_size / 8);
2178         ring_size = (1 << (rb_bufsz + 1)) * 4;
2179         rdev->cp.ring_size = ring_size;
2180         rdev->cp.align_mask = 16 - 1;
2181 }
2182
2183 void r600_cp_fini(struct radeon_device *rdev)
2184 {
2185         r600_cp_stop(rdev);
2186         radeon_ring_fini(rdev);
2187 }
2188
2189
2190 /*
2191  * GPU scratch registers helpers function.
2192  */
2193 void r600_scratch_init(struct radeon_device *rdev)
2194 {
2195         int i;
2196
2197         rdev->scratch.num_reg = 7;
2198         for (i = 0; i < rdev->scratch.num_reg; i++) {
2199                 rdev->scratch.free[i] = true;
2200                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
2201         }
2202 }
2203
2204 int r600_ring_test(struct radeon_device *rdev)
2205 {
2206         uint32_t scratch;
2207         uint32_t tmp = 0;
2208         unsigned i;
2209         int r;
2210
2211         r = radeon_scratch_get(rdev, &scratch);
2212         if (r) {
2213                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2214                 return r;
2215         }
2216         WREG32(scratch, 0xCAFEDEAD);
2217         r = radeon_ring_lock(rdev, 3);
2218         if (r) {
2219                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2220                 radeon_scratch_free(rdev, scratch);
2221                 return r;
2222         }
2223         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2224         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2225         radeon_ring_write(rdev, 0xDEADBEEF);
2226         radeon_ring_unlock_commit(rdev);
2227         for (i = 0; i < rdev->usec_timeout; i++) {
2228                 tmp = RREG32(scratch);
2229                 if (tmp == 0xDEADBEEF)
2230                         break;
2231                 DRM_UDELAY(1);
2232         }
2233         if (i < rdev->usec_timeout) {
2234                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2235         } else {
2236                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2237                           scratch, tmp);
2238                 r = -EINVAL;
2239         }
2240         radeon_scratch_free(rdev, scratch);
2241         return r;
2242 }
2243
2244 void r600_wb_disable(struct radeon_device *rdev)
2245 {
2246         int r;
2247
2248         WREG32(SCRATCH_UMSK, 0);
2249         if (rdev->wb.wb_obj) {
2250                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2251                 if (unlikely(r != 0))
2252                         return;
2253                 radeon_bo_kunmap(rdev->wb.wb_obj);
2254                 radeon_bo_unpin(rdev->wb.wb_obj);
2255                 radeon_bo_unreserve(rdev->wb.wb_obj);
2256         }
2257 }
2258
2259 void r600_wb_fini(struct radeon_device *rdev)
2260 {
2261         r600_wb_disable(rdev);
2262         if (rdev->wb.wb_obj) {
2263                 radeon_bo_unref(&rdev->wb.wb_obj);
2264                 rdev->wb.wb = NULL;
2265                 rdev->wb.wb_obj = NULL;
2266         }
2267 }
2268
2269 int r600_wb_enable(struct radeon_device *rdev)
2270 {
2271         int r;
2272
2273         if (rdev->wb.wb_obj == NULL) {
2274                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
2275                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
2276                 if (r) {
2277                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
2278                         return r;
2279                 }
2280                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2281                 if (unlikely(r != 0)) {
2282                         r600_wb_fini(rdev);
2283                         return r;
2284                 }
2285                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
2286                                 &rdev->wb.gpu_addr);
2287                 if (r) {
2288                         radeon_bo_unreserve(rdev->wb.wb_obj);
2289                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
2290                         r600_wb_fini(rdev);
2291                         return r;
2292                 }
2293                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
2294                 radeon_bo_unreserve(rdev->wb.wb_obj);
2295                 if (r) {
2296                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
2297                         r600_wb_fini(rdev);
2298                         return r;
2299                 }
2300         }
2301         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
2302         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
2303         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
2304         WREG32(SCRATCH_UMSK, 0xff);
2305         return 0;
2306 }
2307
2308 void r600_fence_ring_emit(struct radeon_device *rdev,
2309                           struct radeon_fence *fence)
2310 {
2311         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
2312
2313         radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2314         radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2315         /* wait for 3D idle clean */
2316         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2317         radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2318         radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2319         /* Emit fence sequence & fire IRQ */
2320         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2321         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2322         radeon_ring_write(rdev, fence->seq);
2323         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2324         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2325         radeon_ring_write(rdev, RB_INT_STAT);
2326 }
2327
2328 int r600_copy_blit(struct radeon_device *rdev,
2329                    uint64_t src_offset, uint64_t dst_offset,
2330                    unsigned num_pages, struct radeon_fence *fence)
2331 {
2332         int r;
2333
2334         mutex_lock(&rdev->r600_blit.mutex);
2335         rdev->r600_blit.vb_ib = NULL;
2336         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2337         if (r) {
2338                 if (rdev->r600_blit.vb_ib)
2339                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2340                 mutex_unlock(&rdev->r600_blit.mutex);
2341                 return r;
2342         }
2343         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2344         r600_blit_done_copy(rdev, fence);
2345         mutex_unlock(&rdev->r600_blit.mutex);
2346         return 0;
2347 }
2348
2349 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2350                          uint32_t tiling_flags, uint32_t pitch,
2351                          uint32_t offset, uint32_t obj_size)
2352 {
2353         /* FIXME: implement */
2354         return 0;
2355 }
2356
2357 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2358 {
2359         /* FIXME: implement */
2360 }
2361
2362
2363 bool r600_card_posted(struct radeon_device *rdev)
2364 {
2365         uint32_t reg;
2366
2367         /* first check CRTCs */
2368         reg = RREG32(D1CRTC_CONTROL) |
2369                 RREG32(D2CRTC_CONTROL);
2370         if (reg & CRTC_EN)
2371                 return true;
2372
2373         /* then check MEM_SIZE, in case the crtcs are off */
2374         if (RREG32(CONFIG_MEMSIZE))
2375                 return true;
2376
2377         return false;
2378 }
2379
2380 int r600_startup(struct radeon_device *rdev)
2381 {
2382         int r;
2383
2384         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2385                 r = r600_init_microcode(rdev);
2386                 if (r) {
2387                         DRM_ERROR("Failed to load firmware!\n");
2388                         return r;
2389                 }
2390         }
2391
2392         r600_mc_program(rdev);
2393         if (rdev->flags & RADEON_IS_AGP) {
2394                 r600_agp_enable(rdev);
2395         } else {
2396                 r = r600_pcie_gart_enable(rdev);
2397                 if (r)
2398                         return r;
2399         }
2400         r600_gpu_init(rdev);
2401         r = r600_blit_init(rdev);
2402         if (r) {
2403                 r600_blit_fini(rdev);
2404                 rdev->asic->copy = NULL;
2405                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2406         }
2407         /* pin copy shader into vram */
2408         if (rdev->r600_blit.shader_obj) {
2409                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2410                 if (unlikely(r != 0))
2411                         return r;
2412                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2413                                 &rdev->r600_blit.shader_gpu_addr);
2414                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2415                 if (r) {
2416                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
2417                         return r;
2418                 }
2419         }
2420         /* Enable IRQ */
2421         r = r600_irq_init(rdev);
2422         if (r) {
2423                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2424                 radeon_irq_kms_fini(rdev);
2425                 return r;
2426         }
2427         r600_irq_set(rdev);
2428
2429         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2430         if (r)
2431                 return r;
2432         r = r600_cp_load_microcode(rdev);
2433         if (r)
2434                 return r;
2435         r = r600_cp_resume(rdev);
2436         if (r)
2437                 return r;
2438         /* write back buffer are not vital so don't worry about failure */
2439         r600_wb_enable(rdev);
2440         return 0;
2441 }
2442
2443 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2444 {
2445         uint32_t temp;
2446
2447         temp = RREG32(CONFIG_CNTL);
2448         if (state == false) {
2449                 temp &= ~(1<<0);
2450                 temp |= (1<<1);
2451         } else {
2452                 temp &= ~(1<<1);
2453         }
2454         WREG32(CONFIG_CNTL, temp);
2455 }
2456
2457 int r600_resume(struct radeon_device *rdev)
2458 {
2459         int r;
2460
2461         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2462          * posting will perform necessary task to bring back GPU into good
2463          * shape.
2464          */
2465         /* post card */
2466         atom_asic_init(rdev->mode_info.atom_context);
2467         /* Initialize clocks */
2468         r = radeon_clocks_init(rdev);
2469         if (r) {
2470                 return r;
2471         }
2472
2473         r = r600_startup(rdev);
2474         if (r) {
2475                 DRM_ERROR("r600 startup failed on resume\n");
2476                 return r;
2477         }
2478
2479         r = r600_ib_test(rdev);
2480         if (r) {
2481                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2482                 return r;
2483         }
2484
2485         r = r600_audio_init(rdev);
2486         if (r) {
2487                 DRM_ERROR("radeon: audio resume failed\n");
2488                 return r;
2489         }
2490
2491         return r;
2492 }
2493
2494 int r600_suspend(struct radeon_device *rdev)
2495 {
2496         int r;
2497
2498         r600_audio_fini(rdev);
2499         /* FIXME: we should wait for ring to be empty */
2500         r600_cp_stop(rdev);
2501         rdev->cp.ready = false;
2502         r600_irq_suspend(rdev);
2503         r600_wb_disable(rdev);
2504         r600_pcie_gart_disable(rdev);
2505         /* unpin shaders bo */
2506         if (rdev->r600_blit.shader_obj) {
2507                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2508                 if (!r) {
2509                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2510                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2511                 }
2512         }
2513         return 0;
2514 }
2515
2516 /* Plan is to move initialization in that function and use
2517  * helper function so that radeon_device_init pretty much
2518  * do nothing more than calling asic specific function. This
2519  * should also allow to remove a bunch of callback function
2520  * like vram_info.
2521  */
2522 int r600_init(struct radeon_device *rdev)
2523 {
2524         int r;
2525
2526         r = radeon_dummy_page_init(rdev);
2527         if (r)
2528                 return r;
2529         if (r600_debugfs_mc_info_init(rdev)) {
2530                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2531         }
2532         /* This don't do much */
2533         r = radeon_gem_init(rdev);
2534         if (r)
2535                 return r;
2536         /* Read BIOS */
2537         if (!radeon_get_bios(rdev)) {
2538                 if (ASIC_IS_AVIVO(rdev))
2539                         return -EINVAL;
2540         }
2541         /* Must be an ATOMBIOS */
2542         if (!rdev->is_atom_bios) {
2543                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2544                 return -EINVAL;
2545         }
2546         r = radeon_atombios_init(rdev);
2547         if (r)
2548                 return r;
2549         /* Post card if necessary */
2550         if (!r600_card_posted(rdev)) {
2551                 if (!rdev->bios) {
2552                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2553                         return -EINVAL;
2554                 }
2555                 DRM_INFO("GPU not posted. posting now...\n");
2556                 atom_asic_init(rdev->mode_info.atom_context);
2557         }
2558         /* Initialize scratch registers */
2559         r600_scratch_init(rdev);
2560         /* Initialize surface registers */
2561         radeon_surface_init(rdev);
2562         /* Initialize clocks */
2563         radeon_get_clock_info(rdev->ddev);
2564         r = radeon_clocks_init(rdev);
2565         if (r)
2566                 return r;
2567         /* Fence driver */
2568         r = radeon_fence_driver_init(rdev);
2569         if (r)
2570                 return r;
2571         if (rdev->flags & RADEON_IS_AGP) {
2572                 r = radeon_agp_init(rdev);
2573                 if (r)
2574                         radeon_agp_disable(rdev);
2575         }
2576         r = r600_mc_init(rdev);
2577         if (r)
2578                 return r;
2579         /* Memory manager */
2580         r = radeon_bo_init(rdev);
2581         if (r)
2582                 return r;
2583
2584         r = radeon_irq_kms_init(rdev);
2585         if (r)
2586                 return r;
2587
2588         rdev->cp.ring_obj = NULL;
2589         r600_ring_init(rdev, 1024 * 1024);
2590
2591         rdev->ih.ring_obj = NULL;
2592         r600_ih_ring_init(rdev, 64 * 1024);
2593
2594         r = r600_pcie_gart_init(rdev);
2595         if (r)
2596                 return r;
2597
2598         rdev->accel_working = true;
2599         r = r600_startup(rdev);
2600         if (r) {
2601                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2602                 r600_cp_fini(rdev);
2603                 r600_wb_fini(rdev);
2604                 r600_irq_fini(rdev);
2605                 radeon_irq_kms_fini(rdev);
2606                 r600_pcie_gart_fini(rdev);
2607                 rdev->accel_working = false;
2608         }
2609         if (rdev->accel_working) {
2610                 r = radeon_ib_pool_init(rdev);
2611                 if (r) {
2612                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2613                         rdev->accel_working = false;
2614                 } else {
2615                         r = r600_ib_test(rdev);
2616                         if (r) {
2617                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2618                                 rdev->accel_working = false;
2619                         }
2620                 }
2621         }
2622
2623         r = r600_audio_init(rdev);
2624         if (r)
2625                 return r; /* TODO error handling */
2626         return 0;
2627 }
2628
2629 void r600_fini(struct radeon_device *rdev)
2630 {
2631         r600_audio_fini(rdev);
2632         r600_blit_fini(rdev);
2633         r600_cp_fini(rdev);
2634         r600_wb_fini(rdev);
2635         r600_irq_fini(rdev);
2636         radeon_irq_kms_fini(rdev);
2637         r600_pcie_gart_fini(rdev);
2638         radeon_agp_fini(rdev);
2639         radeon_gem_fini(rdev);
2640         radeon_fence_driver_fini(rdev);
2641         radeon_clocks_fini(rdev);
2642         radeon_bo_fini(rdev);
2643         radeon_atombios_fini(rdev);
2644         kfree(rdev->bios);
2645         rdev->bios = NULL;
2646         radeon_dummy_page_fini(rdev);
2647 }
2648
2649
2650 /*
2651  * CS stuff
2652  */
2653 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2654 {
2655         /* FIXME: implement */
2656         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2657         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2658         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2659         radeon_ring_write(rdev, ib->length_dw);
2660 }
2661
2662 int r600_ib_test(struct radeon_device *rdev)
2663 {
2664         struct radeon_ib *ib;
2665         uint32_t scratch;
2666         uint32_t tmp = 0;
2667         unsigned i;
2668         int r;
2669
2670         r = radeon_scratch_get(rdev, &scratch);
2671         if (r) {
2672                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2673                 return r;
2674         }
2675         WREG32(scratch, 0xCAFEDEAD);
2676         r = radeon_ib_get(rdev, &ib);
2677         if (r) {
2678                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2679                 return r;
2680         }
2681         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2682         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2683         ib->ptr[2] = 0xDEADBEEF;
2684         ib->ptr[3] = PACKET2(0);
2685         ib->ptr[4] = PACKET2(0);
2686         ib->ptr[5] = PACKET2(0);
2687         ib->ptr[6] = PACKET2(0);
2688         ib->ptr[7] = PACKET2(0);
2689         ib->ptr[8] = PACKET2(0);
2690         ib->ptr[9] = PACKET2(0);
2691         ib->ptr[10] = PACKET2(0);
2692         ib->ptr[11] = PACKET2(0);
2693         ib->ptr[12] = PACKET2(0);
2694         ib->ptr[13] = PACKET2(0);
2695         ib->ptr[14] = PACKET2(0);
2696         ib->ptr[15] = PACKET2(0);
2697         ib->length_dw = 16;
2698         r = radeon_ib_schedule(rdev, ib);
2699         if (r) {
2700                 radeon_scratch_free(rdev, scratch);
2701                 radeon_ib_free(rdev, &ib);
2702                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2703                 return r;
2704         }
2705         r = radeon_fence_wait(ib->fence, false);
2706         if (r) {
2707                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2708                 return r;
2709         }
2710         for (i = 0; i < rdev->usec_timeout; i++) {
2711                 tmp = RREG32(scratch);
2712                 if (tmp == 0xDEADBEEF)
2713                         break;
2714                 DRM_UDELAY(1);
2715         }
2716         if (i < rdev->usec_timeout) {
2717                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2718         } else {
2719                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2720                           scratch, tmp);
2721                 r = -EINVAL;
2722         }
2723         radeon_scratch_free(rdev, scratch);
2724         radeon_ib_free(rdev, &ib);
2725         return r;
2726 }
2727
2728 /*
2729  * Interrupts
2730  *
2731  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2732  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2733  * writing to the ring and the GPU consuming, the GPU writes to the ring
2734  * and host consumes.  As the host irq handler processes interrupts, it
2735  * increments the rptr.  When the rptr catches up with the wptr, all the
2736  * current interrupts have been processed.
2737  */
2738
2739 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2740 {
2741         u32 rb_bufsz;
2742
2743         /* Align ring size */
2744         rb_bufsz = drm_order(ring_size / 4);
2745         ring_size = (1 << rb_bufsz) * 4;
2746         rdev->ih.ring_size = ring_size;
2747         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2748         rdev->ih.rptr = 0;
2749 }
2750
2751 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2752 {
2753         int r;
2754
2755         /* Allocate ring buffer */
2756         if (rdev->ih.ring_obj == NULL) {
2757                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2758                                      true,
2759                                      RADEON_GEM_DOMAIN_GTT,
2760                                      &rdev->ih.ring_obj);
2761                 if (r) {
2762                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2763                         return r;
2764                 }
2765                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2766                 if (unlikely(r != 0))
2767                         return r;
2768                 r = radeon_bo_pin(rdev->ih.ring_obj,
2769                                   RADEON_GEM_DOMAIN_GTT,
2770                                   &rdev->ih.gpu_addr);
2771                 if (r) {
2772                         radeon_bo_unreserve(rdev->ih.ring_obj);
2773                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2774                         return r;
2775                 }
2776                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2777                                    (void **)&rdev->ih.ring);
2778                 radeon_bo_unreserve(rdev->ih.ring_obj);
2779                 if (r) {
2780                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2781                         return r;
2782                 }
2783         }
2784         return 0;
2785 }
2786
2787 static void r600_ih_ring_fini(struct radeon_device *rdev)
2788 {
2789         int r;
2790         if (rdev->ih.ring_obj) {
2791                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2792                 if (likely(r == 0)) {
2793                         radeon_bo_kunmap(rdev->ih.ring_obj);
2794                         radeon_bo_unpin(rdev->ih.ring_obj);
2795                         radeon_bo_unreserve(rdev->ih.ring_obj);
2796                 }
2797                 radeon_bo_unref(&rdev->ih.ring_obj);
2798                 rdev->ih.ring = NULL;
2799                 rdev->ih.ring_obj = NULL;
2800         }
2801 }
2802
2803 void r600_rlc_stop(struct radeon_device *rdev)
2804 {
2805
2806         if ((rdev->family >= CHIP_RV770) &&
2807             (rdev->family <= CHIP_RV740)) {
2808                 /* r7xx asics need to soft reset RLC before halting */
2809                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2810                 RREG32(SRBM_SOFT_RESET);
2811                 udelay(15000);
2812                 WREG32(SRBM_SOFT_RESET, 0);
2813                 RREG32(SRBM_SOFT_RESET);
2814         }
2815
2816         WREG32(RLC_CNTL, 0);
2817 }
2818
2819 static void r600_rlc_start(struct radeon_device *rdev)
2820 {
2821         WREG32(RLC_CNTL, RLC_ENABLE);
2822 }
2823
2824 static int r600_rlc_init(struct radeon_device *rdev)
2825 {
2826         u32 i;
2827         const __be32 *fw_data;
2828
2829         if (!rdev->rlc_fw)
2830                 return -EINVAL;
2831
2832         r600_rlc_stop(rdev);
2833
2834         WREG32(RLC_HB_BASE, 0);
2835         WREG32(RLC_HB_CNTL, 0);
2836         WREG32(RLC_HB_RPTR, 0);
2837         WREG32(RLC_HB_WPTR, 0);
2838         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2839         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2840         WREG32(RLC_MC_CNTL, 0);
2841         WREG32(RLC_UCODE_CNTL, 0);
2842
2843         fw_data = (const __be32 *)rdev->rlc_fw->data;
2844         if (rdev->family >= CHIP_CEDAR) {
2845                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2846                         WREG32(RLC_UCODE_ADDR, i);
2847                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2848                 }
2849         } else if (rdev->family >= CHIP_RV770) {
2850                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2851                         WREG32(RLC_UCODE_ADDR, i);
2852                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2853                 }
2854         } else {
2855                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2856                         WREG32(RLC_UCODE_ADDR, i);
2857                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2858                 }
2859         }
2860         WREG32(RLC_UCODE_ADDR, 0);
2861
2862         r600_rlc_start(rdev);
2863
2864         return 0;
2865 }
2866
2867 static void r600_enable_interrupts(struct radeon_device *rdev)
2868 {
2869         u32 ih_cntl = RREG32(IH_CNTL);
2870         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2871
2872         ih_cntl |= ENABLE_INTR;
2873         ih_rb_cntl |= IH_RB_ENABLE;
2874         WREG32(IH_CNTL, ih_cntl);
2875         WREG32(IH_RB_CNTL, ih_rb_cntl);
2876         rdev->ih.enabled = true;
2877 }
2878
2879 void r600_disable_interrupts(struct radeon_device *rdev)
2880 {
2881         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2882         u32 ih_cntl = RREG32(IH_CNTL);
2883
2884         ih_rb_cntl &= ~IH_RB_ENABLE;
2885         ih_cntl &= ~ENABLE_INTR;
2886         WREG32(IH_RB_CNTL, ih_rb_cntl);
2887         WREG32(IH_CNTL, ih_cntl);
2888         /* set rptr, wptr to 0 */
2889         WREG32(IH_RB_RPTR, 0);
2890         WREG32(IH_RB_WPTR, 0);
2891         rdev->ih.enabled = false;
2892         rdev->ih.wptr = 0;
2893         rdev->ih.rptr = 0;
2894 }
2895
2896 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2897 {
2898         u32 tmp;
2899
2900         WREG32(CP_INT_CNTL, 0);
2901         WREG32(GRBM_INT_CNTL, 0);
2902         WREG32(DxMODE_INT_MASK, 0);
2903         if (ASIC_IS_DCE3(rdev)) {
2904                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2905                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2906                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2907                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2908                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2909                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2910                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2911                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2912                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2913                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2914                 if (ASIC_IS_DCE32(rdev)) {
2915                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2916                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2917                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2918                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2919                 }
2920         } else {
2921                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2922                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2923                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2924                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2925                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2926                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2927                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2928                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2929         }
2930 }
2931
2932 int r600_irq_init(struct radeon_device *rdev)
2933 {
2934         int ret = 0;
2935         int rb_bufsz;
2936         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2937
2938         /* allocate ring */
2939         ret = r600_ih_ring_alloc(rdev);
2940         if (ret)
2941                 return ret;
2942
2943         /* disable irqs */
2944         r600_disable_interrupts(rdev);
2945
2946         /* init rlc */
2947         ret = r600_rlc_init(rdev);
2948         if (ret) {
2949                 r600_ih_ring_fini(rdev);
2950                 return ret;
2951         }
2952
2953         /* setup interrupt control */
2954         /* set dummy read address to ring address */
2955         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2956         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2957         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2958          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2959          */
2960         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2961         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2962         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2963         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2964
2965         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2966         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2967
2968         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2969                       IH_WPTR_OVERFLOW_CLEAR |
2970                       (rb_bufsz << 1));
2971         /* WPTR writeback, not yet */
2972         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2973         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2974         WREG32(IH_RB_WPTR_ADDR_HI, 0);
2975
2976         WREG32(IH_RB_CNTL, ih_rb_cntl);
2977
2978         /* set rptr, wptr to 0 */
2979         WREG32(IH_RB_RPTR, 0);
2980         WREG32(IH_RB_WPTR, 0);
2981
2982         /* Default settings for IH_CNTL (disabled at first) */
2983         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2984         /* RPTR_REARM only works if msi's are enabled */
2985         if (rdev->msi_enabled)
2986                 ih_cntl |= RPTR_REARM;
2987
2988 #ifdef __BIG_ENDIAN
2989         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2990 #endif
2991         WREG32(IH_CNTL, ih_cntl);
2992
2993         /* force the active interrupt state to all disabled */
2994         if (rdev->family >= CHIP_CEDAR)
2995                 evergreen_disable_interrupt_state(rdev);
2996         else
2997                 r600_disable_interrupt_state(rdev);
2998
2999         /* enable irqs */
3000         r600_enable_interrupts(rdev);
3001
3002         return ret;
3003 }
3004
3005 void r600_irq_suspend(struct radeon_device *rdev)
3006 {
3007         r600_irq_disable(rdev);
3008         r600_rlc_stop(rdev);
3009 }
3010
3011 void r600_irq_fini(struct radeon_device *rdev)
3012 {
3013         r600_irq_suspend(rdev);
3014         r600_ih_ring_fini(rdev);
3015 }
3016
3017 int r600_irq_set(struct radeon_device *rdev)
3018 {
3019         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3020         u32 mode_int = 0;
3021         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3022         u32 grbm_int_cntl = 0;
3023         u32 hdmi1, hdmi2;
3024
3025         if (!rdev->irq.installed) {
3026                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
3027                 return -EINVAL;
3028         }
3029         /* don't enable anything if the ih is disabled */
3030         if (!rdev->ih.enabled) {
3031                 r600_disable_interrupts(rdev);
3032                 /* force the active interrupt state to all disabled */
3033                 r600_disable_interrupt_state(rdev);
3034                 return 0;
3035         }
3036
3037         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3038         if (ASIC_IS_DCE3(rdev)) {
3039                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3040                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3041                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3042                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3043                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3044                 if (ASIC_IS_DCE32(rdev)) {
3045                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3046                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3047                 }
3048         } else {
3049                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3050                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3051                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3052                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3053         }
3054
3055         if (rdev->irq.sw_int) {
3056                 DRM_DEBUG("r600_irq_set: sw int\n");
3057                 cp_int_cntl |= RB_INT_ENABLE;
3058         }
3059         if (rdev->irq.crtc_vblank_int[0]) {
3060                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3061                 mode_int |= D1MODE_VBLANK_INT_MASK;
3062         }
3063         if (rdev->irq.crtc_vblank_int[1]) {
3064                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3065                 mode_int |= D2MODE_VBLANK_INT_MASK;
3066         }
3067         if (rdev->irq.hpd[0]) {
3068                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3069                 hpd1 |= DC_HPDx_INT_EN;
3070         }
3071         if (rdev->irq.hpd[1]) {
3072                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3073                 hpd2 |= DC_HPDx_INT_EN;
3074         }
3075         if (rdev->irq.hpd[2]) {
3076                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3077                 hpd3 |= DC_HPDx_INT_EN;
3078         }
3079         if (rdev->irq.hpd[3]) {
3080                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3081                 hpd4 |= DC_HPDx_INT_EN;
3082         }
3083         if (rdev->irq.hpd[4]) {
3084                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3085                 hpd5 |= DC_HPDx_INT_EN;
3086         }
3087         if (rdev->irq.hpd[5]) {
3088                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3089                 hpd6 |= DC_HPDx_INT_EN;
3090         }
3091         if (rdev->irq.hdmi[0]) {
3092                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3093                 hdmi1 |= R600_HDMI_INT_EN;
3094         }
3095         if (rdev->irq.hdmi[1]) {
3096                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3097                 hdmi2 |= R600_HDMI_INT_EN;
3098         }
3099         if (rdev->irq.gui_idle) {
3100                 DRM_DEBUG("gui idle\n");
3101                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3102         }
3103
3104         WREG32(CP_INT_CNTL, cp_int_cntl);
3105         WREG32(DxMODE_INT_MASK, mode_int);
3106         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3107         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3108         if (ASIC_IS_DCE3(rdev)) {
3109                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3110                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3111                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3112                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3113                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3114                 if (ASIC_IS_DCE32(rdev)) {
3115                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3116                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3117                 }
3118         } else {
3119                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3120                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3121                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3122                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3123         }
3124
3125         return 0;
3126 }
3127
3128 static inline void r600_irq_ack(struct radeon_device *rdev,
3129                                 u32 *disp_int,
3130                                 u32 *disp_int_cont,
3131                                 u32 *disp_int_cont2)
3132 {
3133         u32 tmp;
3134
3135         if (ASIC_IS_DCE3(rdev)) {
3136                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3137                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3138                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3139         } else {
3140                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3141                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3142                 *disp_int_cont2 = 0;
3143         }
3144
3145         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
3146                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3147         if (*disp_int & LB_D1_VLINE_INTERRUPT)
3148                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3149         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
3150                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3151         if (*disp_int & LB_D2_VLINE_INTERRUPT)
3152                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3153         if (*disp_int & DC_HPD1_INTERRUPT) {
3154                 if (ASIC_IS_DCE3(rdev)) {
3155                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3156                         tmp |= DC_HPDx_INT_ACK;
3157                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3158                 } else {
3159                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3160                         tmp |= DC_HPDx_INT_ACK;
3161                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3162                 }
3163         }
3164         if (*disp_int & DC_HPD2_INTERRUPT) {
3165                 if (ASIC_IS_DCE3(rdev)) {
3166                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3167                         tmp |= DC_HPDx_INT_ACK;
3168                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3169                 } else {
3170                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3171                         tmp |= DC_HPDx_INT_ACK;
3172                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3173                 }
3174         }
3175         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3176                 if (ASIC_IS_DCE3(rdev)) {
3177                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3178                         tmp |= DC_HPDx_INT_ACK;
3179                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3180                 } else {
3181                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3182                         tmp |= DC_HPDx_INT_ACK;
3183                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3184                 }
3185         }
3186         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3187                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3188                 tmp |= DC_HPDx_INT_ACK;
3189                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3190         }
3191         if (ASIC_IS_DCE32(rdev)) {
3192                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3193                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3194                         tmp |= DC_HPDx_INT_ACK;
3195                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3196                 }
3197                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3198                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3199                         tmp |= DC_HPDx_INT_ACK;
3200                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3201                 }
3202         }
3203         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3204                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3205         }
3206         if (ASIC_IS_DCE3(rdev)) {
3207                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3208                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3209                 }
3210         } else {
3211                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3212                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3213                 }
3214         }
3215 }
3216
3217 void r600_irq_disable(struct radeon_device *rdev)
3218 {
3219         u32 disp_int, disp_int_cont, disp_int_cont2;
3220
3221         r600_disable_interrupts(rdev);
3222         /* Wait and acknowledge irq */
3223         mdelay(1);
3224         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3225         r600_disable_interrupt_state(rdev);
3226 }
3227
3228 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3229 {
3230         u32 wptr, tmp;
3231
3232         /* XXX use writeback */
3233         wptr = RREG32(IH_RB_WPTR);
3234
3235         if (wptr & RB_OVERFLOW) {
3236                 /* When a ring buffer overflow happen start parsing interrupt
3237                  * from the last not overwritten vector (wptr + 16). Hopefully
3238                  * this should allow us to catchup.
3239                  */
3240                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3241                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3242                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3243                 tmp = RREG32(IH_RB_CNTL);
3244                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3245                 WREG32(IH_RB_CNTL, tmp);
3246         }
3247         return (wptr & rdev->ih.ptr_mask);
3248 }
3249
3250 /*        r600 IV Ring
3251  * Each IV ring entry is 128 bits:
3252  * [7:0]    - interrupt source id
3253  * [31:8]   - reserved
3254  * [59:32]  - interrupt source data
3255  * [127:60]  - reserved
3256  *
3257  * The basic interrupt vector entries
3258  * are decoded as follows:
3259  * src_id  src_data  description
3260  *      1         0  D1 Vblank
3261  *      1         1  D1 Vline
3262  *      5         0  D2 Vblank
3263  *      5         1  D2 Vline
3264  *     19         0  FP Hot plug detection A
3265  *     19         1  FP Hot plug detection B
3266  *     19         2  DAC A auto-detection
3267  *     19         3  DAC B auto-detection
3268  *     21         4  HDMI block A
3269  *     21         5  HDMI block B
3270  *    176         -  CP_INT RB
3271  *    177         -  CP_INT IB1
3272  *    178         -  CP_INT IB2
3273  *    181         -  EOP Interrupt
3274  *    233         -  GUI Idle
3275  *
3276  * Note, these are based on r600 and may need to be
3277  * adjusted or added to on newer asics
3278  */
3279
3280 int r600_irq_process(struct radeon_device *rdev)
3281 {
3282         u32 wptr = r600_get_ih_wptr(rdev);
3283         u32 rptr = rdev->ih.rptr;
3284         u32 src_id, src_data;
3285         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
3286         unsigned long flags;
3287         bool queue_hotplug = false;
3288
3289         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3290         if (!rdev->ih.enabled)
3291                 return IRQ_NONE;
3292
3293         spin_lock_irqsave(&rdev->ih.lock, flags);
3294
3295         if (rptr == wptr) {
3296                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3297                 return IRQ_NONE;
3298         }
3299         if (rdev->shutdown) {
3300                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3301                 return IRQ_NONE;
3302         }
3303
3304 restart_ih:
3305         /* display interrupts */
3306         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3307
3308         rdev->ih.wptr = wptr;
3309         while (rptr != wptr) {
3310                 /* wptr/rptr are in bytes! */
3311                 ring_index = rptr / 4;
3312                 src_id =  rdev->ih.ring[ring_index] & 0xff;
3313                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3314
3315                 switch (src_id) {
3316                 case 1: /* D1 vblank/vline */
3317                         switch (src_data) {
3318                         case 0: /* D1 vblank */
3319                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3320                                         drm_handle_vblank(rdev->ddev, 0);
3321                                         rdev->pm.vblank_sync = true;
3322                                         wake_up(&rdev->irq.vblank_queue);
3323                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3324                                         DRM_DEBUG("IH: D1 vblank\n");
3325                                 }
3326                                 break;
3327                         case 1: /* D1 vline */
3328                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3329                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
3330                                         DRM_DEBUG("IH: D1 vline\n");
3331                                 }
3332                                 break;
3333                         default:
3334                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3335                                 break;
3336                         }
3337                         break;
3338                 case 5: /* D2 vblank/vline */
3339                         switch (src_data) {
3340                         case 0: /* D2 vblank */
3341                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3342                                         drm_handle_vblank(rdev->ddev, 1);
3343                                         rdev->pm.vblank_sync = true;
3344                                         wake_up(&rdev->irq.vblank_queue);
3345                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3346                                         DRM_DEBUG("IH: D2 vblank\n");
3347                                 }
3348                                 break;
3349                         case 1: /* D1 vline */
3350                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3351                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
3352                                         DRM_DEBUG("IH: D2 vline\n");
3353                                 }
3354                                 break;
3355                         default:
3356                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3357                                 break;
3358                         }
3359                         break;
3360                 case 19: /* HPD/DAC hotplug */
3361                         switch (src_data) {
3362                         case 0:
3363                                 if (disp_int & DC_HPD1_INTERRUPT) {
3364                                         disp_int &= ~DC_HPD1_INTERRUPT;
3365                                         queue_hotplug = true;
3366                                         DRM_DEBUG("IH: HPD1\n");
3367                                 }
3368                                 break;
3369                         case 1:
3370                                 if (disp_int & DC_HPD2_INTERRUPT) {
3371                                         disp_int &= ~DC_HPD2_INTERRUPT;
3372                                         queue_hotplug = true;
3373                                         DRM_DEBUG("IH: HPD2\n");
3374                                 }
3375                                 break;
3376                         case 4:
3377                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3378                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
3379                                         queue_hotplug = true;
3380                                         DRM_DEBUG("IH: HPD3\n");
3381                                 }
3382                                 break;
3383                         case 5:
3384                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3385                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
3386                                         queue_hotplug = true;
3387                                         DRM_DEBUG("IH: HPD4\n");
3388                                 }
3389                                 break;
3390                         case 10:
3391                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
3392                                         disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3393                                         queue_hotplug = true;
3394                                         DRM_DEBUG("IH: HPD5\n");
3395                                 }
3396                                 break;
3397                         case 12:
3398                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
3399                                         disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3400                                         queue_hotplug = true;
3401                                         DRM_DEBUG("IH: HPD6\n");
3402                                 }
3403                                 break;
3404                         default:
3405                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3406                                 break;
3407                         }
3408                         break;
3409                 case 21: /* HDMI */
3410                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3411                         r600_audio_schedule_polling(rdev);
3412                         break;
3413                 case 176: /* CP_INT in ring buffer */
3414                 case 177: /* CP_INT in IB1 */
3415                 case 178: /* CP_INT in IB2 */
3416                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3417                         radeon_fence_process(rdev);
3418                         break;
3419                 case 181: /* CP EOP event */
3420                         DRM_DEBUG("IH: CP EOP\n");
3421                         break;
3422                 case 233: /* GUI IDLE */
3423                         DRM_DEBUG("IH: CP EOP\n");
3424                         rdev->pm.gui_idle = true;
3425                         wake_up(&rdev->irq.idle_queue);
3426                         break;
3427                 default:
3428                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3429                         break;
3430                 }
3431
3432                 /* wptr/rptr are in bytes! */
3433                 rptr += 16;
3434                 rptr &= rdev->ih.ptr_mask;
3435         }
3436         /* make sure wptr hasn't changed while processing */
3437         wptr = r600_get_ih_wptr(rdev);
3438         if (wptr != rdev->ih.wptr)
3439                 goto restart_ih;
3440         if (queue_hotplug)
3441                 queue_work(rdev->wq, &rdev->hotplug_work);
3442         rdev->ih.rptr = rptr;
3443         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3444         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3445         return IRQ_HANDLED;
3446 }
3447
3448 /*
3449  * Debugfs info
3450  */
3451 #if defined(CONFIG_DEBUG_FS)
3452
3453 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3454 {
3455         struct drm_info_node *node = (struct drm_info_node *) m->private;
3456         struct drm_device *dev = node->minor->dev;
3457         struct radeon_device *rdev = dev->dev_private;
3458         unsigned count, i, j;
3459
3460         radeon_ring_free_size(rdev);
3461         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3462         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3463         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3464         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3465         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3466         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3467         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3468         seq_printf(m, "%u dwords in ring\n", count);
3469         i = rdev->cp.rptr;
3470         for (j = 0; j <= count; j++) {
3471                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3472                 i = (i + 1) & rdev->cp.ptr_mask;
3473         }
3474         return 0;
3475 }
3476
3477 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3478 {
3479         struct drm_info_node *node = (struct drm_info_node *) m->private;
3480         struct drm_device *dev = node->minor->dev;
3481         struct radeon_device *rdev = dev->dev_private;
3482
3483         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3484         DREG32_SYS(m, rdev, VM_L2_STATUS);
3485         return 0;
3486 }
3487
3488 static struct drm_info_list r600_mc_info_list[] = {
3489         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3490         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3491 };
3492 #endif
3493
3494 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3495 {
3496 #if defined(CONFIG_DEBUG_FS)
3497         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3498 #else
3499         return 0;
3500 #endif
3501 }
3502
3503 /**
3504  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3505  * rdev: radeon device structure
3506  * bo: buffer object struct which userspace is waiting for idle
3507  *
3508  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3509  * through ring buffer, this leads to corruption in rendering, see
3510  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3511  * directly perform HDP flush by writing register through MMIO.
3512  */
3513 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3514 {
3515         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3516 }