2 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
22 struct drm_plane base;
27 spinlock_t pipe_lock; /* protect REG_MDP5_PIPE_* registers */
30 uint32_t flush_mask; /* used to commit pipe registers */
37 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
39 static int mdp5_plane_mode_set(struct drm_plane *plane,
40 struct drm_crtc *crtc, struct drm_framebuffer *fb,
41 int crtc_x, int crtc_y,
42 unsigned int crtc_w, unsigned int crtc_h,
43 uint32_t src_x, uint32_t src_y,
44 uint32_t src_w, uint32_t src_h);
45 static void set_scanout_locked(struct drm_plane *plane,
46 struct drm_framebuffer *fb);
48 static struct mdp5_kms *get_kms(struct drm_plane *plane)
50 struct msm_drm_private *priv = plane->dev->dev_private;
51 return to_mdp5_kms(to_mdp_kms(priv->kms));
54 static bool plane_enabled(struct drm_plane_state *state)
56 return state->fb && state->crtc;
59 static int mdp5_plane_disable(struct drm_plane *plane)
61 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
62 struct mdp5_kms *mdp5_kms = get_kms(plane);
63 enum mdp5_pipe pipe = mdp5_plane->pipe;
65 DBG("%s: disable", mdp5_plane->name);
68 /* Release the memory we requested earlier from the SMP: */
69 mdp5_smp_release(mdp5_kms->smp, pipe);
75 static void mdp5_plane_destroy(struct drm_plane *plane)
77 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
79 drm_plane_helper_disable(plane);
80 drm_plane_cleanup(plane);
85 /* helper to install properties which are common to planes and crtcs */
86 void mdp5_plane_install_properties(struct drm_plane *plane,
87 struct drm_mode_object *obj)
92 int mdp5_plane_set_property(struct drm_plane *plane,
93 struct drm_property *property, uint64_t val)
99 static void mdp5_plane_reset(struct drm_plane *plane)
101 struct mdp5_plane_state *mdp5_state;
103 if (plane->state && plane->state->fb)
104 drm_framebuffer_unreference(plane->state->fb);
106 kfree(to_mdp5_plane_state(plane->state));
107 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
109 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
110 mdp5_state->zpos = 0;
112 mdp5_state->zpos = 1 + drm_plane_index(plane);
114 mdp5_state->base.plane = plane;
116 plane->state = &mdp5_state->base;
119 static struct drm_plane_state *
120 mdp5_plane_duplicate_state(struct drm_plane *plane)
122 struct mdp5_plane_state *mdp5_state;
124 if (WARN_ON(!plane->state))
127 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
128 sizeof(*mdp5_state), GFP_KERNEL);
130 if (mdp5_state && mdp5_state->base.fb)
131 drm_framebuffer_reference(mdp5_state->base.fb);
133 mdp5_state->mode_changed = false;
134 mdp5_state->pending = false;
136 return &mdp5_state->base;
139 static void mdp5_plane_destroy_state(struct drm_plane *plane,
140 struct drm_plane_state *state)
143 drm_framebuffer_unreference(state->fb);
145 kfree(to_mdp5_plane_state(state));
148 static const struct drm_plane_funcs mdp5_plane_funcs = {
149 .update_plane = drm_atomic_helper_update_plane,
150 .disable_plane = drm_atomic_helper_disable_plane,
151 .destroy = mdp5_plane_destroy,
152 .set_property = mdp5_plane_set_property,
153 .reset = mdp5_plane_reset,
154 .atomic_duplicate_state = mdp5_plane_duplicate_state,
155 .atomic_destroy_state = mdp5_plane_destroy_state,
158 static int mdp5_plane_prepare_fb(struct drm_plane *plane,
159 struct drm_framebuffer *fb)
161 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
162 struct mdp5_kms *mdp5_kms = get_kms(plane);
164 DBG("%s: prepare: FB[%u]", mdp5_plane->name, fb->base.id);
165 return msm_framebuffer_prepare(fb, mdp5_kms->id);
168 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
169 struct drm_framebuffer *fb)
171 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
172 struct mdp5_kms *mdp5_kms = get_kms(plane);
174 DBG("%s: cleanup: FB[%u]", mdp5_plane->name, fb->base.id);
175 msm_framebuffer_cleanup(fb, mdp5_kms->id);
178 static int mdp5_plane_atomic_check(struct drm_plane *plane,
179 struct drm_plane_state *state)
181 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
182 struct drm_plane_state *old_state = plane->state;
184 DBG("%s: check (%d -> %d)", mdp5_plane->name,
185 plane_enabled(old_state), plane_enabled(state));
187 if (plane_enabled(state) && plane_enabled(old_state)) {
188 /* we cannot change SMP block configuration during scanout: */
189 bool full_modeset = false;
190 if (state->fb->pixel_format != old_state->fb->pixel_format) {
191 DBG("%s: pixel_format change!", mdp5_plane->name);
194 if (state->src_w != old_state->src_w) {
195 DBG("%s: src_w change!", mdp5_plane->name);
198 if (to_mdp5_plane_state(old_state)->pending) {
199 DBG("%s: still pending!", mdp5_plane->name);
203 struct drm_crtc_state *crtc_state =
204 drm_atomic_get_crtc_state(state->state, state->crtc);
205 crtc_state->mode_changed = true;
206 to_mdp5_plane_state(state)->mode_changed = true;
209 to_mdp5_plane_state(state)->mode_changed = true;
215 static void mdp5_plane_atomic_update(struct drm_plane *plane,
216 struct drm_plane_state *old_state)
218 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
219 struct drm_plane_state *state = plane->state;
221 DBG("%s: update", mdp5_plane->name);
223 if (!plane_enabled(state)) {
224 to_mdp5_plane_state(state)->pending = true;
225 mdp5_plane_disable(plane);
226 } else if (to_mdp5_plane_state(state)->mode_changed) {
228 to_mdp5_plane_state(state)->pending = true;
229 ret = mdp5_plane_mode_set(plane,
230 state->crtc, state->fb,
231 state->crtc_x, state->crtc_y,
232 state->crtc_w, state->crtc_h,
233 state->src_x, state->src_y,
234 state->src_w, state->src_h);
235 /* atomic_check should have ensured that this doesn't fail */
239 spin_lock_irqsave(&mdp5_plane->pipe_lock, flags);
240 set_scanout_locked(plane, state->fb);
241 spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags);
245 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
246 .prepare_fb = mdp5_plane_prepare_fb,
247 .cleanup_fb = mdp5_plane_cleanup_fb,
248 .atomic_check = mdp5_plane_atomic_check,
249 .atomic_update = mdp5_plane_atomic_update,
252 static void set_scanout_locked(struct drm_plane *plane,
253 struct drm_framebuffer *fb)
255 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
256 struct mdp5_kms *mdp5_kms = get_kms(plane);
257 enum mdp5_pipe pipe = mdp5_plane->pipe;
259 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
260 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
261 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
263 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
264 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
265 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
267 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
268 msm_framebuffer_iova(fb, mdp5_kms->id, 0));
269 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
270 msm_framebuffer_iova(fb, mdp5_kms->id, 1));
271 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
272 msm_framebuffer_iova(fb, mdp5_kms->id, 2));
273 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
274 msm_framebuffer_iova(fb, mdp5_kms->id, 4));
279 /* Note: mdp5_plane->pipe_lock must be locked */
280 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
282 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
283 ~MDP5_PIPE_OP_MODE_CSC_1_EN;
285 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
288 /* Note: mdp5_plane->pipe_lock must be locked */
289 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
292 uint32_t i, mode = 0; /* RGB, no CSC */
298 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
299 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
300 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
301 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
302 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
303 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
305 matrix = csc->matrix;
306 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
307 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
308 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
309 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
310 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
311 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
312 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
313 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
314 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
315 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
316 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
317 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
318 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
319 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
321 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
322 uint32_t *pre_clamp = csc->pre_clamp;
323 uint32_t *post_clamp = csc->post_clamp;
325 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
326 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
327 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
329 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
330 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
331 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
333 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
334 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
336 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
337 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
341 #define PHASE_STEP_SHIFT 21
342 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */
344 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
348 if (src == 0 || dst == 0)
352 * PHASE_STEP_X/Y is coded on 26 bits (25:0),
353 * where 2^21 represents the unity "1" in fixed-point hardware design.
354 * This leaves 5 bits for the integer part (downscale case):
355 * -> maximum downscale ratio = 0b1_1111 = 31
357 if (src > (dst * DOWN_SCALE_RATIO_MAX))
360 unit = 1 << PHASE_STEP_SHIFT;
361 *out_phase = mult_frac(unit, src, dst);
366 static int calc_scalex_steps(uint32_t pixel_format, uint32_t src, uint32_t dest,
367 uint32_t phasex_steps[2])
369 uint32_t phasex_step;
373 ret = calc_phase_step(src, dest, &phasex_step);
377 hsub = drm_format_horz_chroma_subsampling(pixel_format);
379 phasex_steps[0] = phasex_step;
380 phasex_steps[1] = phasex_step / hsub;
385 static int calc_scaley_steps(uint32_t pixel_format, uint32_t src, uint32_t dest,
386 uint32_t phasey_steps[2])
388 uint32_t phasey_step;
392 ret = calc_phase_step(src, dest, &phasey_step);
396 vsub = drm_format_vert_chroma_subsampling(pixel_format);
398 phasey_steps[0] = phasey_step;
399 phasey_steps[1] = phasey_step / vsub;
404 static uint32_t get_scalex_config(uint32_t src, uint32_t dest)
408 filter = (src <= dest) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
410 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
411 MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(filter) |
412 MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(filter) |
413 MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(filter);
416 static uint32_t get_scaley_config(uint32_t src, uint32_t dest)
420 filter = (src <= dest) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
422 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
423 MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(filter) |
424 MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(filter) |
425 MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(filter);
428 static int mdp5_plane_mode_set(struct drm_plane *plane,
429 struct drm_crtc *crtc, struct drm_framebuffer *fb,
430 int crtc_x, int crtc_y,
431 unsigned int crtc_w, unsigned int crtc_h,
432 uint32_t src_x, uint32_t src_y,
433 uint32_t src_w, uint32_t src_h)
435 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
436 struct mdp5_kms *mdp5_kms = get_kms(plane);
437 struct device *dev = mdp5_kms->dev->dev;
438 enum mdp5_pipe pipe = mdp5_plane->pipe;
439 const struct mdp_format *format;
440 uint32_t nplanes, config = 0;
441 /* below array -> index 0: comp 0/3 ; index 1: comp 1/2 */
442 uint32_t phasex_step[2] = {0,}, phasey_step[2] = {0,};
443 uint32_t hdecm = 0, vdecm = 0;
448 nplanes = drm_format_num_planes(fb->pixel_format);
450 /* bad formats should already be rejected: */
451 if (WARN_ON(nplanes > pipe2nclients(pipe)))
454 format = to_mdp_format(msm_framebuffer_format(fb));
455 pix_format = format->base.pixel_format;
457 /* src values are in Q16 fixed point, convert to integer: */
463 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", mdp5_plane->name,
464 fb->base.id, src_x, src_y, src_w, src_h,
465 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
467 /* Request some memory from the SMP: */
468 ret = mdp5_smp_request(mdp5_kms->smp,
469 mdp5_plane->pipe, fb->pixel_format, src_w);
474 * Currently we update the hw for allocations/requests immediately,
475 * but once atomic modeset/pageflip is in place, the allocation
476 * would move into atomic->check_plane_state(), while updating the
477 * hw would remain here:
479 mdp5_smp_configure(mdp5_kms->smp, pipe);
481 /* SCALE is used to both scale and up-sample chroma components */
483 if ((src_w != crtc_w) || MDP_FORMAT_IS_YUV(format)) {
484 /* TODO calc hdecm */
485 ret = calc_scalex_steps(pix_format, src_w, crtc_w, phasex_step);
487 dev_err(dev, "X scaling (%d -> %d) failed: %d\n",
491 config |= get_scalex_config(src_w, crtc_w);
494 if ((src_h != crtc_h) || MDP_FORMAT_IS_YUV(format)) {
495 /* TODO calc vdecm */
496 ret = calc_scaley_steps(pix_format, src_h, crtc_h, phasey_step);
498 dev_err(dev, "Y scaling (%d -> %d) failed: %d\n",
502 config |= get_scaley_config(src_h, crtc_h);
505 spin_lock_irqsave(&mdp5_plane->pipe_lock, flags);
507 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
508 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_w) |
509 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_h));
511 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
512 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
513 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
515 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
516 MDP5_PIPE_SRC_XY_X(src_x) |
517 MDP5_PIPE_SRC_XY_Y(src_y));
519 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
520 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
521 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
523 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
524 MDP5_PIPE_OUT_XY_X(crtc_x) |
525 MDP5_PIPE_OUT_XY_Y(crtc_y));
527 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
528 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
529 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
530 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
531 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
532 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
533 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
534 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
535 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
536 MDP5_PIPE_SRC_FORMAT_NUM_PLANES(format->fetch_type) |
537 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
539 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
540 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
541 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
542 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
543 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
545 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
546 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
548 /* not using secure mode: */
549 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
551 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
553 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
555 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
557 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
559 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
560 MDP5_PIPE_DECIMATION_VERT(vdecm) |
561 MDP5_PIPE_DECIMATION_HORZ(hdecm));
562 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), config);
564 if (MDP_FORMAT_IS_YUV(format))
565 csc_enable(mdp5_kms, pipe,
566 mdp_get_default_csc_cfg(CSC_YUV2RGB));
568 csc_disable(mdp5_kms, pipe);
570 set_scanout_locked(plane, fb);
572 spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags);
577 void mdp5_plane_complete_flip(struct drm_plane *plane)
579 struct mdp5_kms *mdp5_kms = get_kms(plane);
580 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
581 enum mdp5_pipe pipe = mdp5_plane->pipe;
583 DBG("%s: complete flip", mdp5_plane->name);
585 mdp5_smp_commit(mdp5_kms->smp, pipe);
587 to_mdp5_plane_state(plane->state)->pending = false;
590 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
592 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
593 return mdp5_plane->pipe;
596 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
598 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
600 return mdp5_plane->flush_mask;
603 /* initialize plane */
604 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
605 enum mdp5_pipe pipe, bool private_plane, uint32_t reg_offset)
607 struct drm_plane *plane = NULL;
608 struct mdp5_plane *mdp5_plane;
610 enum drm_plane_type type;
612 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
618 plane = &mdp5_plane->base;
620 mdp5_plane->pipe = pipe;
621 mdp5_plane->name = pipe2name(pipe);
623 mdp5_plane->nformats = mdp5_get_formats(pipe, mdp5_plane->formats,
624 ARRAY_SIZE(mdp5_plane->formats));
626 mdp5_plane->flush_mask = mdp_ctl_flush_mask_pipe(pipe);
627 mdp5_plane->reg_offset = reg_offset;
628 spin_lock_init(&mdp5_plane->pipe_lock);
630 type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
631 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
632 mdp5_plane->formats, mdp5_plane->nformats,
637 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
639 mdp5_plane_install_properties(plane, &plane->base);
645 mdp5_plane_destroy(plane);