drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c

   1 /*
   2  * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "mdp5_kms.h"
  20
  21 #include <linux/sort.h>
  22 #include <drm/drm_mode.h>
  23 #include "drm_crtc.h"
  24 #include "drm_crtc_helper.h"
  25 #include "drm_flip_work.h"
  26
  27 #define CURSOR_WIDTH    64
  28 #define CURSOR_HEIGHT   64
  29
  30 #define SSPP_MAX        (SSPP_RGB3 + 1) /* TODO: Add SSPP_MAX in mdp5.xml.h */
  31
  32 struct mdp5_crtc {
  33         struct drm_crtc base;
  34         char name[8];
  35         int id;
  36         bool enabled;
  37
  38         /* layer mixer used for this CRTC (+ its lock): */
  39 #define GET_LM_ID(crtc_id)      ((crtc_id == 3) ? 5 : crtc_id)
  40         int lm;
  41         spinlock_t lm_lock;     /* protect REG_MDP5_LM_* registers */
  42
  43         /* CTL used for this CRTC: */
  44         struct mdp5_ctl *ctl;
  45
  46         /* if there is a pending flip, these will be non-null: */
  47         struct drm_pending_vblank_event *event;
  48
  49         /* Bits have been flushed at the last commit,
  50          * used to decide if a vsync has happened since last commit.
  51          */
  52         u32 flushed_mask;
  53
  54 #define PENDING_CURSOR 0x1
  55 #define PENDING_FLIP   0x2
  56         atomic_t pending;
  57
  58         /* for unref'ing cursor bo's after scanout completes: */
  59         struct drm_flip_work unref_cursor_work;
  60
  61         struct mdp_irq vblank;
  62         struct mdp_irq err;
  63         struct mdp_irq pp_done;
  64
  65         struct completion pp_completion;
  66
  67         bool cmd_mode;
  68
  69         struct {
  70                 /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
  71                 spinlock_t lock;
  72
  73                 /* current cursor being scanned out: */
  74                 struct drm_gem_object *scanout_bo;
  75                 uint32_t width, height;
  76                 uint32_t x, y;
  77         } cursor;
  78 };
  79 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
  80
  81 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
  82 {
  83         struct msm_drm_private *priv = crtc->dev->dev_private;
  84         return to_mdp5_kms(to_mdp_kms(priv->kms));
  85 }
  86
  87 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
  88 {
  89         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  90
  91         atomic_or(pending, &mdp5_crtc->pending);
  92         mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
  93 }
  94
  95 static void request_pp_done_pending(struct drm_crtc *crtc)
  96 {
  97         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  98         reinit_completion(&mdp5_crtc->pp_completion);
  99 }
 100
 101 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
 102 {
 103         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 104
 105         DBG("%s: flush=%08x", mdp5_crtc->name, flush_mask);
 106         return mdp5_ctl_commit(mdp5_crtc->ctl, flush_mask);
 107 }
 108
 109 /*
 110  * flush updates, to make sure hw is updated to new scanout fb,
 111  * so that we can safely queue unref to current fb (ie. next
 112  * vblank we know hw is done w/ previous scanout_fb).
 113  */
 114 static u32 crtc_flush_all(struct drm_crtc *crtc)
 115 {
 116         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 117         struct drm_plane *plane;
 118         uint32_t flush_mask = 0;
 119
 120         /* this should not happen: */
 121         if (WARN_ON(!mdp5_crtc->ctl))
 122                 return 0;
 123
 124         drm_atomic_crtc_for_each_plane(plane, crtc) {
 125                 flush_mask |= mdp5_plane_get_flush(plane);
 126         }
 127
 128         flush_mask |= mdp_ctl_flush_mask_lm(mdp5_crtc->lm);
 129
 130         return crtc_flush(crtc, flush_mask);
 131 }
 132
 133 /* if file!=NULL, this is preclose potential cancel-flip path */
 134 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
 135 {
 136         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 137         struct drm_device *dev = crtc->dev;
 138         struct drm_pending_vblank_event *event;
 139         struct drm_plane *plane;
 140         unsigned long flags;
 141
 142         spin_lock_irqsave(&dev->event_lock, flags);
 143         event = mdp5_crtc->event;
 144         if (event) {
 145                 /* if regular vblank case (!file) or if cancel-flip from
 146                  * preclose on file that requested flip, then send the
 147                  * event:
 148                  */
 149                 if (!file || (event->base.file_priv == file)) {
 150                         mdp5_crtc->event = NULL;
 151                         DBG("%s: send event: %p", mdp5_crtc->name, event);
 152                         drm_crtc_send_vblank_event(crtc, event);
 153                 }
 154         }
 155         spin_unlock_irqrestore(&dev->event_lock, flags);
 156
 157         drm_atomic_crtc_for_each_plane(plane, crtc) {
 158                 mdp5_plane_complete_flip(plane);
 159         }
 160
 161         if (mdp5_crtc->ctl && !crtc->state->enable) {
 162                 /* set STAGE_UNUSED for all layers */
 163                 mdp5_ctl_blend(mdp5_crtc->ctl, NULL, 0, 0);
 164                 mdp5_crtc->ctl = NULL;
 165         }
 166 }
 167
 168 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
 169 {
 170         struct mdp5_crtc *mdp5_crtc =
 171                 container_of(work, struct mdp5_crtc, unref_cursor_work);
 172         struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
 173
 174         msm_gem_put_iova(val, mdp5_kms->id);
 175         drm_gem_object_unreference_unlocked(val);
 176 }
 177
 178 static void mdp5_crtc_destroy(struct drm_crtc *crtc)
 179 {
 180         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 181
 182         drm_crtc_cleanup(crtc);
 183         drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
 184
 185         kfree(mdp5_crtc);
 186 }
 187
 188 /*
 189  * blend_setup() - blend all the planes of a CRTC
 190  *
 191  * If no base layer is available, border will be enabled as the base layer.
 192  * Otherwise all layers will be blended based on their stage calculated
 193  * in mdp5_crtc_atomic_check.
 194  */
 195 static void blend_setup(struct drm_crtc *crtc)
 196 {
 197         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 198         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 199         struct drm_plane *plane;
 200         const struct mdp5_cfg_hw *hw_cfg;
 201         struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
 202         const struct mdp_format *format;
 203         uint32_t lm = mdp5_crtc->lm;
 204         uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
 205         unsigned long flags;
 206         uint8_t stage[STAGE_MAX + 1];
 207         int i, plane_cnt = 0;
 208 #define blender(stage)  ((stage) - STAGE0)
 209
 210         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 211
 212         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 213
 214         /* ctl could be released already when we are shutting down: */
 215         if (!mdp5_crtc->ctl)
 216                 goto out;
 217
 218         /* Collect all plane information */
 219         drm_atomic_crtc_for_each_plane(plane, crtc) {
 220                 pstate = to_mdp5_plane_state(plane->state);
 221                 pstates[pstate->stage] = pstate;
 222                 stage[pstate->stage] = mdp5_plane_pipe(plane);
 223                 plane_cnt++;
 224         }
 225
 226         if (!pstates[STAGE_BASE]) {
 227                 ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
 228                 DBG("Border Color is enabled");
 229         }
 230
 231         /* The reset for blending */
 232         for (i = STAGE0; i <= STAGE_MAX; i++) {
 233                 if (!pstates[i])
 234                         continue;
 235
 236                 format = to_mdp_format(
 237                         msm_framebuffer_format(pstates[i]->base.fb));
 238                 plane = pstates[i]->base.plane;
 239                 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 240                         MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
 241                 fg_alpha = pstates[i]->alpha;
 242                 bg_alpha = 0xFF - pstates[i]->alpha;
 243                 DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
 244
 245                 if (format->alpha_enable && pstates[i]->premultiplied) {
 246                         blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 247                                 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 248                         if (fg_alpha != 0xff) {
 249                                 bg_alpha = fg_alpha;
 250                                 blend_op |=
 251                                         MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
 252                                         MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
 253                         } else {
 254                                 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
 255                         }
 256                 } else if (format->alpha_enable) {
 257                         blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
 258                                 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 259                         if (fg_alpha != 0xff) {
 260                                 bg_alpha = fg_alpha;
 261                                 blend_op |=
 262                                        MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA |
 263                                        MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA |
 264                                        MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
 265                                        MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
 266                         } else {
 267                                 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
 268                         }
 269                 }
 270
 271                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
 272                                 blender(i)), blend_op);
 273                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
 274                                 blender(i)), fg_alpha);
 275                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
 276                                 blender(i)), bg_alpha);
 277         }
 278
 279         mdp5_ctl_blend(mdp5_crtc->ctl, stage, plane_cnt, ctl_blend_flags);
 280
 281 out:
 282         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 283 }
 284
 285 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
 286 {
 287         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 288         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 289         unsigned long flags;
 290         struct drm_display_mode *mode;
 291
 292         if (WARN_ON(!crtc->state))
 293                 return;
 294
 295         mode = &crtc->state->adjusted_mode;
 296
 297         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 298                         mdp5_crtc->name, mode->base.id, mode->name,
 299                         mode->vrefresh, mode->clock,
 300                         mode->hdisplay, mode->hsync_start,
 301                         mode->hsync_end, mode->htotal,
 302                         mode->vdisplay, mode->vsync_start,
 303                         mode->vsync_end, mode->vtotal,
 304                         mode->type, mode->flags);
 305
 306         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 307         mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(mdp5_crtc->lm),
 308                         MDP5_LM_OUT_SIZE_WIDTH(mode->hdisplay) |
 309                         MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
 310         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 311 }
 312
 313 static void mdp5_crtc_disable(struct drm_crtc *crtc)
 314 {
 315         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 316         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 317
 318         DBG("%s", mdp5_crtc->name);
 319
 320         if (WARN_ON(!mdp5_crtc->enabled))
 321                 return;
 322
 323         if (mdp5_crtc->cmd_mode)
 324                 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
 325
 326         mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
 327         mdp5_disable(mdp5_kms);
 328
 329         mdp5_crtc->enabled = false;
 330 }
 331
 332 static void mdp5_crtc_enable(struct drm_crtc *crtc)
 333 {
 334         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 335         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 336
 337         DBG("%s", mdp5_crtc->name);
 338
 339         if (WARN_ON(mdp5_crtc->enabled))
 340                 return;
 341
 342         mdp5_enable(mdp5_kms);
 343         mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
 344
 345         if (mdp5_crtc->cmd_mode)
 346                 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
 347
 348         mdp5_crtc->enabled = true;
 349 }
 350
 351 struct plane_state {
 352         struct drm_plane *plane;
 353         struct mdp5_plane_state *state;
 354 };
 355
 356 static int pstate_cmp(const void *a, const void *b)
 357 {
 358         struct plane_state *pa = (struct plane_state *)a;
 359         struct plane_state *pb = (struct plane_state *)b;
 360         return pa->state->zpos - pb->state->zpos;
 361 }
 362
 363 /* is there a helper for this? */
 364 static bool is_fullscreen(struct drm_crtc_state *cstate,
 365                 struct drm_plane_state *pstate)
 366 {
 367         return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) &&
 368                 ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) &&
 369                 ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay);
 370 }
 371
 372 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
 373                 struct drm_crtc_state *state)
 374 {
 375         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 376         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 377         struct drm_plane *plane;
 378         struct drm_device *dev = crtc->dev;
 379         struct plane_state pstates[STAGE_MAX + 1];
 380         const struct mdp5_cfg_hw *hw_cfg;
 381         const struct drm_plane_state *pstate;
 382         int cnt = 0, base = 0, i;
 383
 384         DBG("%s: check", mdp5_crtc->name);
 385
 386         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 387                 pstates[cnt].plane = plane;
 388                 pstates[cnt].state = to_mdp5_plane_state(pstate);
 389
 390                 cnt++;
 391         }
 392
 393         /* assign a stage based on sorted zpos property */
 394         sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
 395
 396         /* if the bottom-most layer is not fullscreen, we need to use
 397          * it for solid-color:
 398          */
 399         if ((cnt > 0) && !is_fullscreen(state, &pstates[0].state->base))
 400                 base++;
 401
 402         /* verify that there are not too many planes attached to crtc
 403          * and that we don't have conflicting mixer stages:
 404          */
 405         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 406
 407         if ((cnt + base) >= hw_cfg->lm.nb_stages) {
 408                 dev_err(dev->dev, "too many planes!\n");
 409                 return -EINVAL;
 410         }
 411
 412         for (i = 0; i < cnt; i++) {
 413                 pstates[i].state->stage = STAGE_BASE + i + base;
 414                 DBG("%s: assign pipe %s on stage=%d", mdp5_crtc->name,
 415                                 pipe2name(mdp5_plane_pipe(pstates[i].plane)),
 416                                 pstates[i].state->stage);
 417         }
 418
 419         return 0;
 420 }
 421
 422 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc,
 423                                    struct drm_crtc_state *old_crtc_state)
 424 {
 425         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 426         DBG("%s: begin", mdp5_crtc->name);
 427 }
 428
 429 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
 430                                    struct drm_crtc_state *old_crtc_state)
 431 {
 432         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 433         struct drm_device *dev = crtc->dev;
 434         unsigned long flags;
 435
 436         DBG("%s: event: %p", mdp5_crtc->name, crtc->state->event);
 437
 438         WARN_ON(mdp5_crtc->event);
 439
 440         spin_lock_irqsave(&dev->event_lock, flags);
 441         mdp5_crtc->event = crtc->state->event;
 442         spin_unlock_irqrestore(&dev->event_lock, flags);
 443
 444         /*
 445          * If no CTL has been allocated in mdp5_crtc_atomic_check(),
 446          * it means we are trying to flush a CRTC whose state is disabled:
 447          * nothing else needs to be done.
 448          */
 449         if (unlikely(!mdp5_crtc->ctl))
 450                 return;
 451
 452         blend_setup(crtc);
 453
 454         /* PP_DONE irq is only used by command mode for now.
 455          * It is better to request pending before FLUSH and START trigger
 456          * to make sure no pp_done irq missed.
 457          * This is safe because no pp_done will happen before SW trigger
 458          * in command mode.
 459          */
 460         if (mdp5_crtc->cmd_mode)
 461                 request_pp_done_pending(crtc);
 462
 463         mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
 464
 465         request_pending(crtc, PENDING_FLIP);
 466 }
 467
 468 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
 469 {
 470         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 471         uint32_t xres = crtc->mode.hdisplay;
 472         uint32_t yres = crtc->mode.vdisplay;
 473
 474         /*
 475          * Cursor Region Of Interest (ROI) is a plane read from cursor
 476          * buffer to render. The ROI region is determined by the visibility of
 477          * the cursor point. In the default Cursor image the cursor point will
 478          * be at the top left of the cursor image, unless it is specified
 479          * otherwise using hotspot feature.
 480          *
 481          * If the cursor point reaches the right (xres - x < cursor.width) or
 482          * bottom (yres - y < cursor.height) boundary of the screen, then ROI
 483          * width and ROI height need to be evaluated to crop the cursor image
 484          * accordingly.
 485          * (xres-x) will be new cursor width when x > (xres - cursor.width)
 486          * (yres-y) will be new cursor height when y > (yres - cursor.height)
 487          */
 488         *roi_w = min(mdp5_crtc->cursor.width, xres -
 489                         mdp5_crtc->cursor.x);
 490         *roi_h = min(mdp5_crtc->cursor.height, yres -
 491                         mdp5_crtc->cursor.y);
 492 }
 493
 494 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
 495                 struct drm_file *file, uint32_t handle,
 496                 uint32_t width, uint32_t height)
 497 {
 498         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 499         struct drm_device *dev = crtc->dev;
 500         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 501         struct drm_gem_object *cursor_bo, *old_bo = NULL;
 502         uint32_t blendcfg, cursor_addr, stride;
 503         int ret, lm;
 504         enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
 505         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 506         uint32_t roi_w, roi_h;
 507         bool cursor_enable = true;
 508         unsigned long flags;
 509
 510         if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
 511                 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
 512                 return -EINVAL;
 513         }
 514
 515         if (NULL == mdp5_crtc->ctl)
 516                 return -EINVAL;
 517
 518         if (!handle) {
 519                 DBG("Cursor off");
 520                 cursor_enable = false;
 521                 goto set_cursor;
 522         }
 523
 524         cursor_bo = drm_gem_object_lookup(file, handle);
 525         if (!cursor_bo)
 526                 return -ENOENT;
 527
 528         ret = msm_gem_get_iova(cursor_bo, mdp5_kms->id, &cursor_addr);
 529         if (ret)
 530                 return -EINVAL;
 531
 532         lm = mdp5_crtc->lm;
 533         stride = width * drm_format_plane_cpp(DRM_FORMAT_ARGB8888, 0);
 534
 535         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 536         old_bo = mdp5_crtc->cursor.scanout_bo;
 537
 538         mdp5_crtc->cursor.scanout_bo = cursor_bo;
 539         mdp5_crtc->cursor.width = width;
 540         mdp5_crtc->cursor.height = height;
 541
 542         get_roi(crtc, &roi_w, &roi_h);
 543
 544         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
 545         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
 546                         MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
 547         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
 548                         MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
 549                         MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
 550         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
 551                         MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 552                         MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 553         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr);
 554
 555         blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
 556         blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
 557         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
 558
 559         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 560
 561 set_cursor:
 562         ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, 0, cursor_enable);
 563         if (ret) {
 564                 dev_err(dev->dev, "failed to %sable cursor: %d\n",
 565                                 cursor_enable ? "en" : "dis", ret);
 566                 goto end;
 567         }
 568
 569         crtc_flush(crtc, flush_mask);
 570
 571 end:
 572         if (old_bo) {
 573                 drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
 574                 /* enable vblank to complete cursor work: */
 575                 request_pending(crtc, PENDING_CURSOR);
 576         }
 577         return ret;
 578 }
 579
 580 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 581 {
 582         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 583         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 584         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 585         uint32_t roi_w;
 586         uint32_t roi_h;
 587         unsigned long flags;
 588
 589         /* In case the CRTC is disabled, just drop the cursor update */
 590         if (unlikely(!crtc->state->enable))
 591                 return 0;
 592
 593         mdp5_crtc->cursor.x = x = max(x, 0);
 594         mdp5_crtc->cursor.y = y = max(y, 0);
 595
 596         get_roi(crtc, &roi_w, &roi_h);
 597
 598         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 599         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(mdp5_crtc->lm),
 600                         MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 601                         MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 602         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(mdp5_crtc->lm),
 603                         MDP5_LM_CURSOR_START_XY_Y_START(y) |
 604                         MDP5_LM_CURSOR_START_XY_X_START(x));
 605         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 606
 607         crtc_flush(crtc, flush_mask);
 608
 609         return 0;
 610 }
 611
 612 static const struct drm_crtc_funcs mdp5_crtc_funcs = {
 613         .set_config = drm_atomic_helper_set_config,
 614         .destroy = mdp5_crtc_destroy,
 615         .page_flip = drm_atomic_helper_page_flip,
 616         .set_property = drm_atomic_helper_crtc_set_property,
 617         .reset = drm_atomic_helper_crtc_reset,
 618         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 619         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 620         .cursor_set = mdp5_crtc_cursor_set,
 621         .cursor_move = mdp5_crtc_cursor_move,
 622 };
 623
 624 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
 625         .mode_set_nofb = mdp5_crtc_mode_set_nofb,
 626         .disable = mdp5_crtc_disable,
 627         .enable = mdp5_crtc_enable,
 628         .atomic_check = mdp5_crtc_atomic_check,
 629         .atomic_begin = mdp5_crtc_atomic_begin,
 630         .atomic_flush = mdp5_crtc_atomic_flush,
 631 };
 632
 633 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
 634 {
 635         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
 636         struct drm_crtc *crtc = &mdp5_crtc->base;
 637         struct msm_drm_private *priv = crtc->dev->dev_private;
 638         unsigned pending;
 639
 640         mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
 641
 642         pending = atomic_xchg(&mdp5_crtc->pending, 0);
 643
 644         if (pending & PENDING_FLIP) {
 645                 complete_flip(crtc, NULL);
 646         }
 647
 648         if (pending & PENDING_CURSOR)
 649                 drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq);
 650 }
 651
 652 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
 653 {
 654         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
 655
 656         DBG("%s: error: %08x", mdp5_crtc->name, irqstatus);
 657 }
 658
 659 static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
 660 {
 661         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
 662                                                                 pp_done);
 663
 664         complete(&mdp5_crtc->pp_completion);
 665 }
 666
 667 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
 668 {
 669         struct drm_device *dev = crtc->dev;
 670         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 671         int ret;
 672
 673         ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
 674                                                 msecs_to_jiffies(50));
 675         if (ret == 0)
 676                 dev_warn(dev->dev, "pp done time out, lm=%d\n", mdp5_crtc->lm);
 677 }
 678
 679 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
 680 {
 681         struct drm_device *dev = crtc->dev;
 682         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 683         int ret;
 684
 685         /* Should not call this function if crtc is disabled. */
 686         if (!mdp5_crtc->ctl)
 687                 return;
 688
 689         ret = drm_crtc_vblank_get(crtc);
 690         if (ret)
 691                 return;
 692
 693         ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
 694                 ((mdp5_ctl_get_commit_status(mdp5_crtc->ctl) &
 695                 mdp5_crtc->flushed_mask) == 0),
 696                 msecs_to_jiffies(50));
 697         if (ret <= 0)
 698                 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
 699
 700         mdp5_crtc->flushed_mask = 0;
 701
 702         drm_crtc_vblank_put(crtc);
 703 }
 704
 705 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
 706 {
 707         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 708         return mdp5_crtc->vblank.irqmask;
 709 }
 710
 711 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc,
 712                 struct mdp5_interface *intf, struct mdp5_ctl *ctl)
 713 {
 714         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 715         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 716         int lm = mdp5_crtc_get_lm(crtc);
 717
 718         /* now that we know what irq's we want: */
 719         mdp5_crtc->err.irqmask = intf2err(intf->num);
 720         mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf);
 721
 722         if ((intf->type == INTF_DSI) &&
 723                 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
 724                 mdp5_crtc->pp_done.irqmask = lm2ppdone(lm);
 725                 mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
 726                 mdp5_crtc->cmd_mode = true;
 727         } else {
 728                 mdp5_crtc->pp_done.irqmask = 0;
 729                 mdp5_crtc->pp_done.irq = NULL;
 730                 mdp5_crtc->cmd_mode = false;
 731         }
 732
 733         mdp_irq_update(&mdp5_kms->base);
 734
 735         mdp5_crtc->ctl = ctl;
 736         mdp5_ctl_set_pipeline(ctl, intf, lm);
 737 }
 738
 739 int mdp5_crtc_get_lm(struct drm_crtc *crtc)
 740 {
 741         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 742         return WARN_ON(!crtc) ? -EINVAL : mdp5_crtc->lm;
 743 }
 744
 745 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
 746 {
 747         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 748
 749         if (mdp5_crtc->cmd_mode)
 750                 mdp5_crtc_wait_for_pp_done(crtc);
 751         else
 752                 mdp5_crtc_wait_for_flush_done(crtc);
 753 }
 754
 755 /* initialize crtc */
 756 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
 757                 struct drm_plane *plane, int id)
 758 {
 759         struct drm_crtc *crtc = NULL;
 760         struct mdp5_crtc *mdp5_crtc;
 761
 762         mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
 763         if (!mdp5_crtc)
 764                 return ERR_PTR(-ENOMEM);
 765
 766         crtc = &mdp5_crtc->base;
 767
 768         mdp5_crtc->id = id;
 769         mdp5_crtc->lm = GET_LM_ID(id);
 770
 771         spin_lock_init(&mdp5_crtc->lm_lock);
 772         spin_lock_init(&mdp5_crtc->cursor.lock);
 773         init_completion(&mdp5_crtc->pp_completion);
 774
 775         mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
 776         mdp5_crtc->err.irq = mdp5_crtc_err_irq;
 777
 778         snprintf(mdp5_crtc->name, sizeof(mdp5_crtc->name), "%s:%d",
 779                         pipe2name(mdp5_plane_pipe(plane)), id);
 780
 781         drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp5_crtc_funcs,
 782                                   NULL);
 783
 784         drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
 785                         "unref cursor", unref_cursor_worker);
 786
 787         drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);
 788         plane->crtc = crtc;
 789
 790         return crtc;
 791 }