drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/platform_device.h>
  15
  16 #include "dsi_phy.h"
  17
  18 #define S_DIV_ROUND_UP(n, d)    \
  19         (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
  20
  21 static inline s32 linear_inter(s32 tmax, s32 tmin, s32 percent,
  22                                 s32 min_result, bool even)
  23 {
  24         s32 v;
  25
  26         v = (tmax - tmin) * percent;
  27         v = S_DIV_ROUND_UP(v, 100) + tmin;
  28         if (even && (v & 0x1))
  29                 return max_t(s32, min_result, v - 1);
  30         else
  31                 return max_t(s32, min_result, v);
  32 }
  33
  34 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing,
  35                                         s32 ui, s32 coeff, s32 pcnt)
  36 {
  37         s32 tmax, tmin, clk_z;
  38         s32 temp;
  39
  40         /* reset */
  41         temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui;
  42         tmin = S_DIV_ROUND_UP(temp, ui) - 2;
  43         if (tmin > 255) {
  44                 tmax = 511;
  45                 clk_z = linear_inter(2 * tmin, tmin, pcnt, 0, true);
  46         } else {
  47                 tmax = 255;
  48                 clk_z = linear_inter(tmax, tmin, pcnt, 0, true);
  49         }
  50
  51         /* adjust */
  52         temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7;
  53         timing->clk_zero = clk_z + 8 - temp;
  54 }
  55
  56 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
  57                              struct msm_dsi_phy_clk_request *clk_req)
  58 {
  59         const unsigned long bit_rate = clk_req->bitclk_rate;
  60         const unsigned long esc_rate = clk_req->escclk_rate;
  61         s32 ui, lpx;
  62         s32 tmax, tmin;
  63         s32 pcnt0 = 10;
  64         s32 pcnt1 = (bit_rate > 1200000000) ? 15 : 10;
  65         s32 pcnt2 = 10;
  66         s32 pcnt3 = (bit_rate > 180000000) ? 10 : 40;
  67         s32 coeff = 1000; /* Precision, should avoid overflow */
  68         s32 temp;
  69
  70         if (!bit_rate || !esc_rate)
  71                 return -EINVAL;
  72
  73         ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
  74         lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
  75
  76         tmax = S_DIV_ROUND_UP(95 * coeff, ui) - 2;
  77         tmin = S_DIV_ROUND_UP(38 * coeff, ui) - 2;
  78         timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true);
  79
  80         temp = lpx / ui;
  81         if (temp & 0x1)
  82                 timing->hs_rqst = temp;
  83         else
  84                 timing->hs_rqst = max_t(s32, 0, temp - 2);
  85
  86         /* Calculate clk_zero after clk_prepare and hs_rqst */
  87         dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2);
  88
  89         temp = 105 * coeff + 12 * ui - 20 * coeff;
  90         tmax = S_DIV_ROUND_UP(temp, ui) - 2;
  91         tmin = S_DIV_ROUND_UP(60 * coeff, ui) - 2;
  92         timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
  93
  94         temp = 85 * coeff + 6 * ui;
  95         tmax = S_DIV_ROUND_UP(temp, ui) - 2;
  96         temp = 40 * coeff + 4 * ui;
  97         tmin = S_DIV_ROUND_UP(temp, ui) - 2;
  98         timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true);
  99
 100         tmax = 255;
 101         temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui;
 102         temp = 145 * coeff + 10 * ui - temp;
 103         tmin = S_DIV_ROUND_UP(temp, ui) - 2;
 104         timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true);
 105
 106         temp = 105 * coeff + 12 * ui - 20 * coeff;
 107         tmax = S_DIV_ROUND_UP(temp, ui) - 2;
 108         temp = 60 * coeff + 4 * ui;
 109         tmin = DIV_ROUND_UP(temp, ui) - 2;
 110         timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
 111
 112         tmax = 255;
 113         tmin = S_DIV_ROUND_UP(100 * coeff, ui) - 2;
 114         timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true);
 115
 116         tmax = 63;
 117         temp = ((timing->hs_exit >> 1) + 1) * 2 * ui;
 118         temp = 60 * coeff + 52 * ui - 24 * ui - temp;
 119         tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
 120         timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0,
 121                                                        false);
 122         tmax = 63;
 123         temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui;
 124         temp += ((timing->clk_zero >> 1) + 1) * 2 * ui;
 125         temp += 8 * ui + lpx;
 126         tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
 127         if (tmin > tmax) {
 128                 temp = linear_inter(2 * tmax, tmin, pcnt2, 0, false);
 129                 timing->shared_timings.clk_pre = temp >> 1;
 130                 timing->shared_timings.clk_pre_inc_by_2 = true;
 131         } else {
 132                 timing->shared_timings.clk_pre =
 133                                 linear_inter(tmax, tmin, pcnt2, 0, false);
 134                 timing->shared_timings.clk_pre_inc_by_2 = false;
 135         }
 136
 137         timing->ta_go = 3;
 138         timing->ta_sure = 0;
 139         timing->ta_get = 4;
 140
 141         DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
 142                 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
 143                 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
 144                 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
 145                 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
 146                 timing->hs_rqst);
 147
 148         return 0;
 149 }
 150
 151 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
 152                                 struct msm_dsi_phy_clk_request *clk_req)
 153 {
 154         const unsigned long bit_rate = clk_req->bitclk_rate;
 155         const unsigned long esc_rate = clk_req->escclk_rate;
 156         s32 ui, ui_x8, lpx;
 157         s32 tmax, tmin;
 158         s32 pcnt0 = 50;
 159         s32 pcnt1 = 50;
 160         s32 pcnt2 = 10;
 161         s32 pcnt3 = 30;
 162         s32 pcnt4 = 10;
 163         s32 pcnt5 = 2;
 164         s32 coeff = 1000; /* Precision, should avoid overflow */
 165         s32 hb_en, hb_en_ckln, pd_ckln, pd;
 166         s32 val, val_ckln;
 167         s32 temp;
 168
 169         if (!bit_rate || !esc_rate)
 170                 return -EINVAL;
 171
 172         timing->hs_halfbyte_en = 0;
 173         hb_en = 0;
 174         timing->hs_halfbyte_en_ckln = 0;
 175         hb_en_ckln = 0;
 176         timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3;
 177         pd_ckln = timing->hs_prep_dly_ckln;
 178         timing->hs_prep_dly = (bit_rate > 120000000) ? 0 : 1;
 179         pd = timing->hs_prep_dly;
 180
 181         val = (hb_en << 2) + (pd << 1);
 182         val_ckln = (hb_en_ckln << 2) + (pd_ckln << 1);
 183
 184         ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
 185         ui_x8 = ui << 3;
 186         lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
 187
 188         temp = S_DIV_ROUND_UP(38 * coeff - val_ckln * ui, ui_x8);
 189         tmin = max_t(s32, temp, 0);
 190         temp = (95 * coeff - val_ckln * ui) / ui_x8;
 191         tmax = max_t(s32, temp, 0);
 192         timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
 193
 194         temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui;
 195         tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
 196         tmax = (tmin > 255) ? 511 : 255;
 197         timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
 198
 199         tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
 200         temp = 105 * coeff + 12 * ui - 20 * coeff;
 201         tmax = (temp + 3 * ui) / ui_x8;
 202         timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
 203
 204         temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui - val * ui, ui_x8);
 205         tmin = max_t(s32, temp, 0);
 206         temp = (85 * coeff + 6 * ui - val * ui) / ui_x8;
 207         tmax = max_t(s32, temp, 0);
 208         timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
 209
 210         temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui;
 211         tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
 212         tmax = 255;
 213         timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
 214
 215         tmin = DIV_ROUND_UP(60 * coeff + 4 * ui + 3 * ui, ui_x8);
 216         temp = 105 * coeff + 12 * ui - 20 * coeff;
 217         tmax = (temp + 3 * ui) / ui_x8;
 218         timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
 219
 220         temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
 221         timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
 222
 223         tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
 224         tmax = 255;
 225         timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
 226
 227         temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
 228         timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
 229
 230         temp = 60 * coeff + 52 * ui - 43 * ui;
 231         tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
 232         tmax = 63;
 233         timing->shared_timings.clk_post =
 234                                 linear_inter(tmax, tmin, pcnt2, 0, false);
 235
 236         temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui;
 237         temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui;
 238         temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
 239                                 (((timing->hs_rqst_ckln << 3) + 8) * ui);
 240         tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
 241         tmax = 63;
 242         if (tmin > tmax) {
 243                 temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
 244                 timing->shared_timings.clk_pre = temp >> 1;
 245                 timing->shared_timings.clk_pre_inc_by_2 = 1;
 246         } else {
 247                 timing->shared_timings.clk_pre =
 248                                 linear_inter(tmax, tmin, pcnt2, 0, false);
 249                 timing->shared_timings.clk_pre_inc_by_2 = 0;
 250         }
 251
 252         timing->ta_go = 3;
 253         timing->ta_sure = 0;
 254         timing->ta_get = 4;
 255
 256         DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
 257             timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
 258             timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
 259             timing->clk_trail, timing->clk_prepare, timing->hs_exit,
 260             timing->hs_zero, timing->hs_prepare, timing->hs_trail,
 261             timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
 262             timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
 263             timing->hs_prep_dly_ckln);
 264
 265         return 0;
 266 }
 267
 268 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
 269                                 u32 bit_mask)
 270 {
 271         int phy_id = phy->id;
 272         u32 val;
 273
 274         if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
 275                 return;
 276
 277         val = dsi_phy_read(phy->base + reg);
 278
 279         if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
 280                 dsi_phy_write(phy->base + reg, val | bit_mask);
 281         else
 282                 dsi_phy_write(phy->base + reg, val & (~bit_mask));
 283 }
 284
 285 static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
 286 {
 287         struct regulator_bulk_data *s = phy->supplies;
 288         const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
 289         struct device *dev = &phy->pdev->dev;
 290         int num = phy->cfg->reg_cfg.num;
 291         int i, ret;
 292
 293         for (i = 0; i < num; i++)
 294                 s[i].supply = regs[i].name;
 295
 296         ret = devm_regulator_bulk_get(dev, num, s);
 297         if (ret < 0) {
 298                 dev_err(dev, "%s: failed to init regulator, ret=%d\n",
 299                                                 __func__, ret);
 300                 return ret;
 301         }
 302
 303         return 0;
 304 }
 305
 306 static void dsi_phy_regulator_disable(struct msm_dsi_phy *phy)
 307 {
 308         struct regulator_bulk_data *s = phy->supplies;
 309         const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
 310         int num = phy->cfg->reg_cfg.num;
 311         int i;
 312
 313         DBG("");
 314         for (i = num - 1; i >= 0; i--)
 315                 if (regs[i].disable_load >= 0)
 316                         regulator_set_load(s[i].consumer, regs[i].disable_load);
 317
 318         regulator_bulk_disable(num, s);
 319 }
 320
 321 static int dsi_phy_regulator_enable(struct msm_dsi_phy *phy)
 322 {
 323         struct regulator_bulk_data *s = phy->supplies;
 324         const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
 325         struct device *dev = &phy->pdev->dev;
 326         int num = phy->cfg->reg_cfg.num;
 327         int ret, i;
 328
 329         DBG("");
 330         for (i = 0; i < num; i++) {
 331                 if (regs[i].enable_load >= 0) {
 332                         ret = regulator_set_load(s[i].consumer,
 333                                                         regs[i].enable_load);
 334                         if (ret < 0) {
 335                                 dev_err(dev,
 336                                         "regulator %d set op mode failed, %d\n",
 337                                         i, ret);
 338                                 goto fail;
 339                         }
 340                 }
 341         }
 342
 343         ret = regulator_bulk_enable(num, s);
 344         if (ret < 0) {
 345                 dev_err(dev, "regulator enable failed, %d\n", ret);
 346                 goto fail;
 347         }
 348
 349         return 0;
 350
 351 fail:
 352         for (i--; i >= 0; i--)
 353                 regulator_set_load(s[i].consumer, regs[i].disable_load);
 354         return ret;
 355 }
 356
 357 static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)
 358 {
 359         struct device *dev = &phy->pdev->dev;
 360         int ret;
 361
 362         pm_runtime_get_sync(dev);
 363
 364         ret = clk_prepare_enable(phy->ahb_clk);
 365         if (ret) {
 366                 dev_err(dev, "%s: can't enable ahb clk, %d\n", __func__, ret);
 367                 pm_runtime_put_sync(dev);
 368         }
 369
 370         return ret;
 371 }
 372
 373 static void dsi_phy_disable_resource(struct msm_dsi_phy *phy)
 374 {
 375         clk_disable_unprepare(phy->ahb_clk);
 376         pm_runtime_put_autosuspend(&phy->pdev->dev);
 377 }
 378
 379 static const struct of_device_id dsi_phy_dt_match[] = {
 380 #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
 381         { .compatible = "qcom,dsi-phy-28nm-hpm",
 382           .data = &dsi_phy_28nm_hpm_cfgs },
 383         { .compatible = "qcom,dsi-phy-28nm-lp",
 384           .data = &dsi_phy_28nm_lp_cfgs },
 385 #endif
 386 #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
 387         { .compatible = "qcom,dsi-phy-20nm",
 388           .data = &dsi_phy_20nm_cfgs },
 389 #endif
 390 #ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY
 391         { .compatible = "qcom,dsi-phy-28nm-8960",
 392           .data = &dsi_phy_28nm_8960_cfgs },
 393 #endif
 394 #ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
 395         { .compatible = "qcom,dsi-phy-14nm",
 396           .data = &dsi_phy_14nm_cfgs },
 397 #endif
 398         {}
 399 };
 400
 401 /*
 402  * Currently, we only support one SoC for each PHY type. When we have multiple
 403  * SoCs for the same PHY, we can try to make the index searching a bit more
 404  * clever.
 405  */
 406 static int dsi_phy_get_id(struct msm_dsi_phy *phy)
 407 {
 408         struct platform_device *pdev = phy->pdev;
 409         const struct msm_dsi_phy_cfg *cfg = phy->cfg;
 410         struct resource *res;
 411         int i;
 412
 413         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_phy");
 414         if (!res)
 415                 return -EINVAL;
 416
 417         for (i = 0; i < cfg->num_dsi_phy; i++) {
 418                 if (cfg->io_start[i] == res->start)
 419                         return i;
 420         }
 421
 422         return -EINVAL;
 423 }
 424
 425 int msm_dsi_phy_init_common(struct msm_dsi_phy *phy)
 426 {
 427         struct platform_device *pdev = phy->pdev;
 428         int ret = 0;
 429
 430         phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
 431                                 "DSI_PHY_REG");
 432         if (IS_ERR(phy->reg_base)) {
 433                 dev_err(&pdev->dev, "%s: failed to map phy regulator base\n",
 434                         __func__);
 435                 ret = -ENOMEM;
 436                 goto fail;
 437         }
 438
 439 fail:
 440         return ret;
 441 }
 442
 443 static int dsi_phy_driver_probe(struct platform_device *pdev)
 444 {
 445         struct msm_dsi_phy *phy;
 446         struct device *dev = &pdev->dev;
 447         const struct of_device_id *match;
 448         int ret;
 449
 450         phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 451         if (!phy)
 452                 return -ENOMEM;
 453
 454         match = of_match_node(dsi_phy_dt_match, dev->of_node);
 455         if (!match)
 456                 return -ENODEV;
 457
 458         phy->cfg = match->data;
 459         phy->pdev = pdev;
 460
 461         phy->id = dsi_phy_get_id(phy);
 462         if (phy->id < 0) {
 463                 ret = phy->id;
 464                 dev_err(dev, "%s: couldn't identify PHY index, %d\n",
 465                         __func__, ret);
 466                 goto fail;
 467         }
 468
 469         phy->regulator_ldo_mode = of_property_read_bool(dev->of_node,
 470                                 "qcom,dsi-phy-regulator-ldo-mode");
 471
 472         phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
 473         if (IS_ERR(phy->base)) {
 474                 dev_err(dev, "%s: failed to map phy base\n", __func__);
 475                 ret = -ENOMEM;
 476                 goto fail;
 477         }
 478
 479         ret = dsi_phy_regulator_init(phy);
 480         if (ret) {
 481                 dev_err(dev, "%s: failed to init regulator\n", __func__);
 482                 goto fail;
 483         }
 484
 485         phy->ahb_clk = devm_clk_get(dev, "iface_clk");
 486         if (IS_ERR(phy->ahb_clk)) {
 487                 dev_err(dev, "%s: Unable to get ahb clk\n", __func__);
 488                 ret = PTR_ERR(phy->ahb_clk);
 489                 goto fail;
 490         }
 491
 492         if (phy->cfg->ops.init) {
 493                 ret = phy->cfg->ops.init(phy);
 494                 if (ret)
 495                         goto fail;
 496         }
 497
 498         /* PLL init will call into clk_register which requires
 499          * register access, so we need to enable power and ahb clock.
 500          */
 501         ret = dsi_phy_enable_resource(phy);
 502         if (ret)
 503                 goto fail;
 504
 505         phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id);
 506         if (!phy->pll)
 507                 dev_info(dev,
 508                         "%s: pll init failed, need separate pll clk driver\n",
 509                         __func__);
 510
 511         dsi_phy_disable_resource(phy);
 512
 513         platform_set_drvdata(pdev, phy);
 514
 515         return 0;
 516
 517 fail:
 518         return ret;
 519 }
 520
 521 static int dsi_phy_driver_remove(struct platform_device *pdev)
 522 {
 523         struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
 524
 525         if (phy && phy->pll) {
 526                 msm_dsi_pll_destroy(phy->pll);
 527                 phy->pll = NULL;
 528         }
 529
 530         platform_set_drvdata(pdev, NULL);
 531
 532         return 0;
 533 }
 534
 535 static struct platform_driver dsi_phy_platform_driver = {
 536         .probe      = dsi_phy_driver_probe,
 537         .remove     = dsi_phy_driver_remove,
 538         .driver     = {
 539                 .name   = "msm_dsi_phy",
 540                 .of_match_table = dsi_phy_dt_match,
 541         },
 542 };
 543
 544 void __init msm_dsi_phy_driver_register(void)
 545 {
 546         platform_driver_register(&dsi_phy_platform_driver);
 547 }
 548
 549 void __exit msm_dsi_phy_driver_unregister(void)
 550 {
 551         platform_driver_unregister(&dsi_phy_platform_driver);
 552 }
 553
 554 int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
 555                         struct msm_dsi_phy_clk_request *clk_req)
 556 {
 557         struct device *dev = &phy->pdev->dev;
 558         int ret;
 559
 560         if (!phy || !phy->cfg->ops.enable)
 561                 return -EINVAL;
 562
 563         ret = dsi_phy_enable_resource(phy);
 564         if (ret) {
 565                 dev_err(dev, "%s: resource enable failed, %d\n",
 566                         __func__, ret);
 567                 goto res_en_fail;
 568         }
 569
 570         ret = dsi_phy_regulator_enable(phy);
 571         if (ret) {
 572                 dev_err(dev, "%s: regulator enable failed, %d\n",
 573                         __func__, ret);
 574                 goto reg_en_fail;
 575         }
 576
 577         ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req);
 578         if (ret) {
 579                 dev_err(dev, "%s: phy enable failed, %d\n", __func__, ret);
 580                 goto phy_en_fail;
 581         }
 582
 583         /*
 584          * Resetting DSI PHY silently changes its PLL registers to reset status,
 585          * which will confuse clock driver and result in wrong output rate of
 586          * link clocks. Restore PLL status if its PLL is being used as clock
 587          * source.
 588          */
 589         if (phy->usecase != MSM_DSI_PHY_SLAVE) {
 590                 ret = msm_dsi_pll_restore_state(phy->pll);
 591                 if (ret) {
 592                         dev_err(dev, "%s: failed to restore pll state, %d\n",
 593                                 __func__, ret);
 594                         goto pll_restor_fail;
 595                 }
 596         }
 597
 598         return 0;
 599
 600 pll_restor_fail:
 601         if (phy->cfg->ops.disable)
 602                 phy->cfg->ops.disable(phy);
 603 phy_en_fail:
 604         dsi_phy_regulator_disable(phy);
 605 reg_en_fail:
 606         dsi_phy_disable_resource(phy);
 607 res_en_fail:
 608         return ret;
 609 }
 610
 611 void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
 612 {
 613         if (!phy || !phy->cfg->ops.disable)
 614                 return;
 615
 616         /* Save PLL status if it is a clock source */
 617         if (phy->usecase != MSM_DSI_PHY_SLAVE)
 618                 msm_dsi_pll_save_state(phy->pll);
 619
 620         phy->cfg->ops.disable(phy);
 621
 622         dsi_phy_regulator_disable(phy);
 623         dsi_phy_disable_resource(phy);
 624 }
 625
 626 void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
 627                         struct msm_dsi_phy_shared_timings *shared_timings)
 628 {
 629         memcpy(shared_timings, &phy->timing.shared_timings,
 630                sizeof(*shared_timings));
 631 }
 632
 633 struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy)
 634 {
 635         if (!phy)
 636                 return NULL;
 637
 638         return phy->pll;
 639 }
 640
 641 void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
 642                              enum msm_dsi_phy_usecase uc)
 643 {
 644         if (phy)
 645                 phy->usecase = uc;
 646 }