drivers/gpu/drm/meson/meson_drv.h

   1 /*
   2  * Copyright (C) 2016 BayLibre, SAS
   3  * Author: Neil Armstrong <narmstrong@baylibre.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of the
   8  * License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef __MESON_DRV_H
  20 #define __MESON_DRV_H
  21
  22 #include <linux/platform_device.h>
  23 #include <linux/regmap.h>
  24 #include <linux/of.h>
  25 #include <linux/soc/amlogic/meson-canvas.h>
  26 #include <drm/drmP.h>
  27
  28 struct meson_drm {
  29         struct device *dev;
  30         void __iomem *io_base;
  31         struct regmap *hhi;
  32         int vsync_irq;
  33
  34         struct meson_canvas *canvas;
  35         u8 canvas_id_osd1;
  36         u8 canvas_id_vd1_0;
  37         u8 canvas_id_vd1_1;
  38         u8 canvas_id_vd1_2;
  39
  40         struct drm_device *drm;
  41         struct drm_crtc *crtc;
  42         struct drm_plane *primary_plane;
  43         struct drm_plane *overlay_plane;
  44
  45         /* Components Data */
  46         struct {
  47                 bool osd1_enabled;
  48                 bool osd1_interlace;
  49                 bool osd1_commit;
  50                 uint32_t osd1_ctrl_stat;
  51                 uint32_t osd1_blk0_cfg[5];
  52                 uint32_t osd1_addr;
  53                 uint32_t osd1_stride;
  54                 uint32_t osd1_height;
  55                 uint32_t osd_sc_ctrl0;
  56                 uint32_t osd_sc_i_wh_m1;
  57                 uint32_t osd_sc_o_h_start_end;
  58                 uint32_t osd_sc_o_v_start_end;
  59                 uint32_t osd_sc_v_ini_phase;
  60                 uint32_t osd_sc_v_phase_step;
  61                 uint32_t osd_sc_h_ini_phase;
  62                 uint32_t osd_sc_h_phase_step;
  63                 uint32_t osd_sc_h_ctrl0;
  64                 uint32_t osd_sc_v_ctrl0;
  65                 uint32_t osd_blend_din0_scope_h;
  66                 uint32_t osd_blend_din0_scope_v;
  67                 uint32_t osb_blend0_size;
  68                 uint32_t osb_blend1_size;
  69
  70                 bool vd1_enabled;
  71                 bool vd1_commit;
  72                 unsigned int vd1_planes;
  73                 uint32_t vd1_if0_gen_reg;
  74                 uint32_t vd1_if0_luma_x0;
  75                 uint32_t vd1_if0_luma_y0;
  76                 uint32_t vd1_if0_chroma_x0;
  77                 uint32_t vd1_if0_chroma_y0;
  78                 uint32_t vd1_if0_repeat_loop;
  79                 uint32_t vd1_if0_luma0_rpt_pat;
  80                 uint32_t vd1_if0_chroma0_rpt_pat;
  81                 uint32_t vd1_range_map_y;
  82                 uint32_t vd1_range_map_cb;
  83                 uint32_t vd1_range_map_cr;
  84                 uint32_t viu_vd1_fmt_w;
  85                 uint32_t vd1_if0_canvas0;
  86                 uint32_t vd1_if0_gen_reg2;
  87                 uint32_t viu_vd1_fmt_ctrl;
  88                 uint32_t vd1_addr0;
  89                 uint32_t vd1_addr1;
  90                 uint32_t vd1_addr2;
  91                 uint32_t vd1_stride0;
  92                 uint32_t vd1_stride1;
  93                 uint32_t vd1_stride2;
  94                 uint32_t vd1_height0;
  95                 uint32_t vd1_height1;
  96                 uint32_t vd1_height2;
  97                 uint32_t vpp_pic_in_height;
  98                 uint32_t vpp_postblend_vd1_h_start_end;
  99                 uint32_t vpp_postblend_vd1_v_start_end;
 100                 uint32_t vpp_hsc_region12_startp;
 101                 uint32_t vpp_hsc_region34_startp;
 102                 uint32_t vpp_hsc_region4_endp;
 103                 uint32_t vpp_hsc_start_phase_step;
 104                 uint32_t vpp_hsc_region1_phase_slope;
 105                 uint32_t vpp_hsc_region3_phase_slope;
 106                 uint32_t vpp_line_in_length;
 107                 uint32_t vpp_preblend_h_size;
 108                 uint32_t vpp_vsc_region12_startp;
 109                 uint32_t vpp_vsc_region34_startp;
 110                 uint32_t vpp_vsc_region4_endp;
 111                 uint32_t vpp_vsc_start_phase_step;
 112                 uint32_t vpp_vsc_ini_phase;
 113                 uint32_t vpp_vsc_phase_ctrl;
 114                 uint32_t vpp_hsc_phase_ctrl;
 115                 uint32_t vpp_blend_vd2_h_start_end;
 116                 uint32_t vpp_blend_vd2_v_start_end;
 117         } viu;
 118
 119         struct {
 120                 unsigned int current_mode;
 121                 bool hdmi_repeat;
 122                 bool venc_repeat;
 123                 bool hdmi_use_enci;
 124         } venc;
 125 };
 126
 127 static inline int meson_vpu_is_compatible(struct meson_drm *priv,
 128                                           const char *compat)
 129 {
 130         return of_device_is_compatible(priv->dev->of_node, compat);
 131 }
 132
 133 #endif /* __MESON_DRV_H */