drivers/gpu/drm/i915/selftests/intel_uncore.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "../i915_selftest.h"
  26
  27 static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
  28                                 unsigned int num_ranges,
  29                                 bool is_watertight)
  30 {
  31         unsigned int i;
  32         s32 prev;
  33
  34         for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
  35                 /* Check that the table is watertight */
  36                 if (is_watertight && (prev + 1) != (s32)ranges->start) {
  37                         pr_err("%s: entry[%d]:(%x, %x) is not watertight to previous (%x)\n",
  38                                __func__, i, ranges->start, ranges->end, prev);
  39                         return -EINVAL;
  40                 }
  41
  42                 /* Check that the table never goes backwards */
  43                 if (prev >= (s32)ranges->start) {
  44                         pr_err("%s: entry[%d]:(%x, %x) is less than the previous (%x)\n",
  45                                __func__, i, ranges->start, ranges->end, prev);
  46                         return -EINVAL;
  47                 }
  48
  49                 /* Check that the entry is valid */
  50                 if (ranges->start >= ranges->end) {
  51                         pr_err("%s: entry[%d]:(%x, %x) has negative length\n",
  52                                __func__, i, ranges->start, ranges->end);
  53                         return -EINVAL;
  54                 }
  55
  56                 prev = ranges->end;
  57         }
  58
  59         return 0;
  60 }
  61
  62 static int intel_shadow_table_check(void)
  63 {
  64         struct {
  65                 const i915_reg_t *regs;
  66                 unsigned int size;
  67         } reg_lists[] = {
  68                 { gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
  69                 { gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
  70         };
  71         const i915_reg_t *reg;
  72         unsigned int i, j;
  73         s32 prev;
  74
  75         for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) {
  76                 reg = reg_lists[j].regs;
  77                 for (i = 0, prev = -1; i < reg_lists[j].size; i++, reg++) {
  78                         u32 offset = i915_mmio_reg_offset(*reg);
  79
  80                         if (prev >= (s32)offset) {
  81                                 pr_err("%s: entry[%d]:(%x) is before previous (%x)\n",
  82                                        __func__, i, offset, prev);
  83                                 return -EINVAL;
  84                         }
  85
  86                         prev = offset;
  87                 }
  88         }
  89
  90         return 0;
  91 }
  92
  93 int intel_uncore_mock_selftests(void)
  94 {
  95         struct {
  96                 const struct intel_forcewake_range *ranges;
  97                 unsigned int num_ranges;
  98                 bool is_watertight;
  99         } fw[] = {
 100                 { __vlv_fw_ranges, ARRAY_SIZE(__vlv_fw_ranges), false },
 101                 { __chv_fw_ranges, ARRAY_SIZE(__chv_fw_ranges), false },
 102                 { __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
 103                 { __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
 104         };
 105         int err, i;
 106
 107         for (i = 0; i < ARRAY_SIZE(fw); i++) {
 108                 err = intel_fw_table_check(fw[i].ranges,
 109                                            fw[i].num_ranges,
 110                                            fw[i].is_watertight);
 111                 if (err)
 112                         return err;
 113         }
 114
 115         err = intel_shadow_table_check();
 116         if (err)
 117                 return err;
 118
 119         return 0;
 120 }
 121
 122 static int live_forcewake_ops(void *arg)
 123 {
 124         static const struct reg {
 125                 const char *name;
 126                 unsigned long platforms;
 127                 unsigned int offset;
 128         } registers[] = {
 129                 {
 130                         "RING_START",
 131                         INTEL_GEN_MASK(6, 7),
 132                         0x38,
 133                 },
 134                 {
 135                         "RING_MI_MODE",
 136                         INTEL_GEN_MASK(8, BITS_PER_LONG),
 137                         0x9c,
 138                 }
 139         };
 140         const struct reg *r;
 141         struct drm_i915_private *i915 = arg;
 142         struct intel_uncore_forcewake_domain *domain;
 143         struct intel_uncore *uncore = &i915->uncore;
 144         struct intel_engine_cs *engine;
 145         enum intel_engine_id id;
 146         intel_wakeref_t wakeref;
 147         unsigned int tmp;
 148         int err = 0;
 149
 150         GEM_BUG_ON(i915->gt.awake);
 151
 152         /* vlv/chv with their pcu behave differently wrt reads */
 153         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
 154                 pr_debug("PCU fakes forcewake badly; skipping\n");
 155                 return 0;
 156         }
 157
 158         /* We have to pick carefully to get the exact behaviour we need */
 159         for (r = registers; r->name; r++)
 160                 if (r->platforms & INTEL_INFO(i915)->gen_mask)
 161                         break;
 162         if (!r->name) {
 163                 pr_debug("Forcewaked register not known for %s; skipping\n",
 164                          intel_platform_name(INTEL_INFO(i915)->platform));
 165                 return 0;
 166         }
 167
 168         wakeref = intel_runtime_pm_get(i915);
 169
 170         for_each_fw_domain(domain, uncore, tmp) {
 171                 smp_store_mb(domain->active, false);
 172                 if (!hrtimer_cancel(&domain->timer))
 173                         continue;
 174
 175                 intel_uncore_fw_release_timer(&domain->timer);
 176         }
 177
 178         for_each_engine(engine, i915, id) {
 179                 i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);
 180                 u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset;
 181                 enum forcewake_domains fw_domains;
 182                 u32 val;
 183
 184                 if (!engine->default_state)
 185                         continue;
 186
 187                 fw_domains = intel_uncore_forcewake_for_reg(i915, mmio,
 188                                                             FW_REG_READ);
 189                 if (!fw_domains)
 190                         continue;
 191
 192                 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 193                         if (!domain->wake_count)
 194                                 continue;
 195
 196                         pr_err("fw_domain %s still active, aborting test!\n",
 197                                intel_uncore_forcewake_domain_to_str(domain->id));
 198                         err = -EINVAL;
 199                         goto out_rpm;
 200                 }
 201
 202                 intel_uncore_forcewake_get(uncore, fw_domains);
 203                 val = readl(reg);
 204                 intel_uncore_forcewake_put(uncore, fw_domains);
 205
 206                 /* Flush the forcewake release (delayed onto a timer) */
 207                 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 208                         smp_store_mb(domain->active, false);
 209                         if (hrtimer_cancel(&domain->timer))
 210                                 intel_uncore_fw_release_timer(&domain->timer);
 211
 212                         preempt_disable();
 213                         err = wait_ack_clear(domain, FORCEWAKE_KERNEL);
 214                         preempt_enable();
 215                         if (err) {
 216                                 pr_err("Failed to clear fw_domain %s\n",
 217                                        intel_uncore_forcewake_domain_to_str(domain->id));
 218                                 goto out_rpm;
 219                         }
 220                 }
 221
 222                 if (!val) {
 223                         pr_err("%s:%s was zero while fw was held!\n",
 224                                engine->name, r->name);
 225                         err = -EINVAL;
 226                         goto out_rpm;
 227                 }
 228
 229                 /* We then expect the read to return 0 outside of the fw */
 230                 if (wait_for(readl(reg) == 0, 100)) {
 231                         pr_err("%s:%s=%0x, fw_domains 0x%x still up after 100ms!\n",
 232                                engine->name, r->name, readl(reg), fw_domains);
 233                         err = -ETIMEDOUT;
 234                         goto out_rpm;
 235                 }
 236         }
 237
 238 out_rpm:
 239         intel_runtime_pm_put(i915, wakeref);
 240         return err;
 241 }
 242
 243 static int live_forcewake_domains(void *arg)
 244 {
 245 #define FW_RANGE 0x40000
 246         struct drm_i915_private *dev_priv = arg;
 247         struct intel_uncore *uncore = &dev_priv->uncore;
 248         unsigned long *valid;
 249         u32 offset;
 250         int err;
 251
 252         if (!HAS_FPGA_DBG_UNCLAIMED(dev_priv) &&
 253             !IS_VALLEYVIEW(dev_priv) &&
 254             !IS_CHERRYVIEW(dev_priv))
 255                 return 0;
 256
 257         /*
 258          * This test may lockup the machine or cause GPU hangs afterwards.
 259          */
 260         if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
 261                 return 0;
 262
 263         valid = bitmap_zalloc(FW_RANGE, GFP_KERNEL);
 264         if (!valid)
 265                 return -ENOMEM;
 266
 267         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 268
 269         check_for_unclaimed_mmio(uncore);
 270         for (offset = 0; offset < FW_RANGE; offset += 4) {
 271                 i915_reg_t reg = { offset };
 272
 273                 (void)I915_READ_FW(reg);
 274                 if (!check_for_unclaimed_mmio(uncore))
 275                         set_bit(offset, valid);
 276         }
 277
 278         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 279
 280         err = 0;
 281         for_each_set_bit(offset, valid, FW_RANGE) {
 282                 i915_reg_t reg = { offset };
 283
 284                 iosf_mbi_punit_acquire();
 285                 intel_uncore_forcewake_reset(uncore);
 286                 iosf_mbi_punit_release();
 287
 288                 check_for_unclaimed_mmio(uncore);
 289
 290                 (void)I915_READ(reg);
 291                 if (check_for_unclaimed_mmio(uncore)) {
 292                         pr_err("Unclaimed mmio read to register 0x%04x\n",
 293                                offset);
 294                         err = -EINVAL;
 295                 }
 296         }
 297
 298         bitmap_free(valid);
 299         return err;
 300 }
 301
 302 int intel_uncore_live_selftests(struct drm_i915_private *i915)
 303 {
 304         static const struct i915_subtest tests[] = {
 305                 SUBTEST(live_forcewake_ops),
 306                 SUBTEST(live_forcewake_domains),
 307         };
 308
 309         int err;
 310
 311         /* Confirm the table we load is still valid */
 312         err = intel_fw_table_check(i915->uncore.fw_domains_table,
 313                                    i915->uncore.fw_domains_table_entries,
 314                                    INTEL_GEN(i915) >= 9);
 315         if (err)
 316                 return err;
 317
 318         return i915_subtests(tests, i915);
 319 }