drivers/gpu/drm/i915/selftests/i915_gem_object.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "../i915_selftest.h"
  26
  27 #include "mock_gem_device.h"
  28 #include "huge_gem_object.h"
  29
  30 static int igt_gem_object(void *arg)
  31 {
  32         struct drm_i915_private *i915 = arg;
  33         struct drm_i915_gem_object *obj;
  34         int err = -ENOMEM;
  35
  36         /* Basic test to ensure we can create an object */
  37
  38         obj = i915_gem_object_create(i915, PAGE_SIZE);
  39         if (IS_ERR(obj)) {
  40                 err = PTR_ERR(obj);
  41                 pr_err("i915_gem_object_create failed, err=%d\n", err);
  42                 goto out;
  43         }
  44
  45         err = 0;
  46         i915_gem_object_put(obj);
  47 out:
  48         return err;
  49 }
  50
  51 static int igt_phys_object(void *arg)
  52 {
  53         struct drm_i915_private *i915 = arg;
  54         struct drm_i915_gem_object *obj;
  55         int err;
  56
  57         /* Create an object and bind it to a contiguous set of physical pages,
  58          * i.e. exercise the i915_gem_object_phys API.
  59          */
  60
  61         obj = i915_gem_object_create(i915, PAGE_SIZE);
  62         if (IS_ERR(obj)) {
  63                 err = PTR_ERR(obj);
  64                 pr_err("i915_gem_object_create failed, err=%d\n", err);
  65                 goto out;
  66         }
  67
  68         mutex_lock(&i915->drm.struct_mutex);
  69         err = i915_gem_object_attach_phys(obj, PAGE_SIZE);
  70         mutex_unlock(&i915->drm.struct_mutex);
  71         if (err) {
  72                 pr_err("i915_gem_object_attach_phys failed, err=%d\n", err);
  73                 goto out_obj;
  74         }
  75
  76         if (obj->ops != &i915_gem_phys_ops) {
  77                 pr_err("i915_gem_object_attach_phys did not create a phys object\n");
  78                 err = -EINVAL;
  79                 goto out_obj;
  80         }
  81
  82         if (!atomic_read(&obj->mm.pages_pin_count)) {
  83                 pr_err("i915_gem_object_attach_phys did not pin its phys pages\n");
  84                 err = -EINVAL;
  85                 goto out_obj;
  86         }
  87
  88         /* Make the object dirty so that put_pages must do copy back the data */
  89         mutex_lock(&i915->drm.struct_mutex);
  90         err = i915_gem_object_set_to_gtt_domain(obj, true);
  91         mutex_unlock(&i915->drm.struct_mutex);
  92         if (err) {
  93                 pr_err("i915_gem_object_set_to_gtt_domain failed with err=%d\n",
  94                        err);
  95                 goto out_obj;
  96         }
  97
  98 out_obj:
  99         i915_gem_object_put(obj);
 100 out:
 101         return err;
 102 }
 103
 104 static int igt_gem_huge(void *arg)
 105 {
 106         const unsigned int nreal = 509; /* just to be awkward */
 107         struct drm_i915_private *i915 = arg;
 108         struct drm_i915_gem_object *obj;
 109         unsigned int n;
 110         int err;
 111
 112         /* Basic sanitycheck of our huge fake object allocation */
 113
 114         obj = huge_gem_object(i915,
 115                               nreal * PAGE_SIZE,
 116                               i915->ggtt.vm.total + PAGE_SIZE);
 117         if (IS_ERR(obj))
 118                 return PTR_ERR(obj);
 119
 120         err = i915_gem_object_pin_pages(obj);
 121         if (err) {
 122                 pr_err("Failed to allocate %u pages (%lu total), err=%d\n",
 123                        nreal, obj->base.size / PAGE_SIZE, err);
 124                 goto out;
 125         }
 126
 127         for (n = 0; n < obj->base.size / PAGE_SIZE; n++) {
 128                 if (i915_gem_object_get_page(obj, n) !=
 129                     i915_gem_object_get_page(obj, n % nreal)) {
 130                         pr_err("Page lookup mismatch at index %u [%u]\n",
 131                                n, n % nreal);
 132                         err = -EINVAL;
 133                         goto out_unpin;
 134                 }
 135         }
 136
 137 out_unpin:
 138         i915_gem_object_unpin_pages(obj);
 139 out:
 140         i915_gem_object_put(obj);
 141         return err;
 142 }
 143
 144 struct tile {
 145         unsigned int width;
 146         unsigned int height;
 147         unsigned int stride;
 148         unsigned int size;
 149         unsigned int tiling;
 150         unsigned int swizzle;
 151 };
 152
 153 static u64 swizzle_bit(unsigned int bit, u64 offset)
 154 {
 155         return (offset & BIT_ULL(bit)) >> (bit - 6);
 156 }
 157
 158 static u64 tiled_offset(const struct tile *tile, u64 v)
 159 {
 160         u64 x, y;
 161
 162         if (tile->tiling == I915_TILING_NONE)
 163                 return v;
 164
 165         y = div64_u64_rem(v, tile->stride, &x);
 166         v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height;
 167
 168         if (tile->tiling == I915_TILING_X) {
 169                 v += y * tile->width;
 170                 v += div64_u64_rem(x, tile->width, &x) << tile->size;
 171                 v += x;
 172         } else if (tile->width == 128) {
 173                 const unsigned int ytile_span = 16;
 174                 const unsigned int ytile_height = 512;
 175
 176                 v += y * ytile_span;
 177                 v += div64_u64_rem(x, ytile_span, &x) * ytile_height;
 178                 v += x;
 179         } else {
 180                 const unsigned int ytile_span = 32;
 181                 const unsigned int ytile_height = 256;
 182
 183                 v += y * ytile_span;
 184                 v += div64_u64_rem(x, ytile_span, &x) * ytile_height;
 185                 v += x;
 186         }
 187
 188         switch (tile->swizzle) {
 189         case I915_BIT_6_SWIZZLE_9:
 190                 v ^= swizzle_bit(9, v);
 191                 break;
 192         case I915_BIT_6_SWIZZLE_9_10:
 193                 v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v);
 194                 break;
 195         case I915_BIT_6_SWIZZLE_9_11:
 196                 v ^= swizzle_bit(9, v) ^ swizzle_bit(11, v);
 197                 break;
 198         case I915_BIT_6_SWIZZLE_9_10_11:
 199                 v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v) ^ swizzle_bit(11, v);
 200                 break;
 201         }
 202
 203         return v;
 204 }
 205
 206 static int check_partial_mapping(struct drm_i915_gem_object *obj,
 207                                  const struct tile *tile,
 208                                  unsigned long end_time)
 209 {
 210         const unsigned int nreal = obj->scratch / PAGE_SIZE;
 211         const unsigned long npages = obj->base.size / PAGE_SIZE;
 212         struct i915_vma *vma;
 213         unsigned long page;
 214         int err;
 215
 216         if (igt_timeout(end_time,
 217                         "%s: timed out before tiling=%d stride=%d\n",
 218                         __func__, tile->tiling, tile->stride))
 219                 return -EINTR;
 220
 221         err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride);
 222         if (err) {
 223                 pr_err("Failed to set tiling mode=%u, stride=%u, err=%d\n",
 224                        tile->tiling, tile->stride, err);
 225                 return err;
 226         }
 227
 228         GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);
 229         GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride);
 230
 231         for_each_prime_number_from(page, 1, npages) {
 232                 struct i915_ggtt_view view =
 233                         compute_partial_view(obj, page, MIN_CHUNK_PAGES);
 234                 u32 __iomem *io;
 235                 struct page *p;
 236                 unsigned int n;
 237                 u64 offset;
 238                 u32 *cpu;
 239
 240                 GEM_BUG_ON(view.partial.size > nreal);
 241                 cond_resched();
 242
 243                 err = i915_gem_object_set_to_gtt_domain(obj, true);
 244                 if (err) {
 245                         pr_err("Failed to flush to GTT write domain; err=%d\n",
 246                                err);
 247                         return err;
 248                 }
 249
 250                 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
 251                 if (IS_ERR(vma)) {
 252                         pr_err("Failed to pin partial view: offset=%lu; err=%d\n",
 253                                page, (int)PTR_ERR(vma));
 254                         return PTR_ERR(vma);
 255                 }
 256
 257                 n = page - view.partial.offset;
 258                 GEM_BUG_ON(n >= view.partial.size);
 259
 260                 io = i915_vma_pin_iomap(vma);
 261                 i915_vma_unpin(vma);
 262                 if (IS_ERR(io)) {
 263                         pr_err("Failed to iomap partial view: offset=%lu; err=%d\n",
 264                                page, (int)PTR_ERR(io));
 265                         return PTR_ERR(io);
 266                 }
 267
 268                 iowrite32(page, io + n * PAGE_SIZE/sizeof(*io));
 269                 i915_vma_unpin_iomap(vma);
 270
 271                 offset = tiled_offset(tile, page << PAGE_SHIFT);
 272                 if (offset >= obj->base.size)
 273                         continue;
 274
 275                 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
 276
 277                 p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
 278                 cpu = kmap(p) + offset_in_page(offset);
 279                 drm_clflush_virt_range(cpu, sizeof(*cpu));
 280                 if (*cpu != (u32)page) {
 281                         pr_err("Partial view for %lu [%u] (offset=%llu, size=%u [%llu, row size %u], fence=%d, tiling=%d, stride=%d) misalignment, expected write to page (%llu + %u [0x%llx]) of 0x%x, found 0x%x\n",
 282                                page, n,
 283                                view.partial.offset,
 284                                view.partial.size,
 285                                vma->size >> PAGE_SHIFT,
 286                                tile->tiling ? tile_row_pages(obj) : 0,
 287                                vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride,
 288                                offset >> PAGE_SHIFT,
 289                                (unsigned int)offset_in_page(offset),
 290                                offset,
 291                                (u32)page, *cpu);
 292                         err = -EINVAL;
 293                 }
 294                 *cpu = 0;
 295                 drm_clflush_virt_range(cpu, sizeof(*cpu));
 296                 kunmap(p);
 297                 if (err)
 298                         return err;
 299
 300                 i915_vma_destroy(vma);
 301         }
 302
 303         return 0;
 304 }
 305
 306 static int igt_partial_tiling(void *arg)
 307 {
 308         const unsigned int nreal = 1 << 12; /* largest tile row x2 */
 309         struct drm_i915_private *i915 = arg;
 310         struct drm_i915_gem_object *obj;
 311         intel_wakeref_t wakeref;
 312         int tiling;
 313         int err;
 314
 315         /* We want to check the page mapping and fencing of a large object
 316          * mmapped through the GTT. The object we create is larger than can
 317          * possibly be mmaped as a whole, and so we must use partial GGTT vma.
 318          * We then check that a write through each partial GGTT vma ends up
 319          * in the right set of pages within the object, and with the expected
 320          * tiling, which we verify by manual swizzling.
 321          */
 322
 323         obj = huge_gem_object(i915,
 324                               nreal << PAGE_SHIFT,
 325                               (1 + next_prime_number(i915->ggtt.vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
 326         if (IS_ERR(obj))
 327                 return PTR_ERR(obj);
 328
 329         err = i915_gem_object_pin_pages(obj);
 330         if (err) {
 331                 pr_err("Failed to allocate %u pages (%lu total), err=%d\n",
 332                        nreal, obj->base.size / PAGE_SIZE, err);
 333                 goto out;
 334         }
 335
 336         mutex_lock(&i915->drm.struct_mutex);
 337         wakeref = intel_runtime_pm_get(i915);
 338
 339         if (1) {
 340                 IGT_TIMEOUT(end);
 341                 struct tile tile;
 342
 343                 tile.height = 1;
 344                 tile.width = 1;
 345                 tile.size = 0;
 346                 tile.stride = 0;
 347                 tile.swizzle = I915_BIT_6_SWIZZLE_NONE;
 348                 tile.tiling = I915_TILING_NONE;
 349
 350                 err = check_partial_mapping(obj, &tile, end);
 351                 if (err && err != -EINTR)
 352                         goto out_unlock;
 353         }
 354
 355         for (tiling = I915_TILING_X; tiling <= I915_TILING_Y; tiling++) {
 356                 IGT_TIMEOUT(end);
 357                 unsigned int max_pitch;
 358                 unsigned int pitch;
 359                 struct tile tile;
 360
 361                 if (i915->quirks & QUIRK_PIN_SWIZZLED_PAGES)
 362                         /*
 363                          * The swizzling pattern is actually unknown as it
 364                          * varies based on physical address of each page.
 365                          * See i915_gem_detect_bit_6_swizzle().
 366                          */
 367                         break;
 368
 369                 tile.tiling = tiling;
 370                 switch (tiling) {
 371                 case I915_TILING_X:
 372                         tile.swizzle = i915->mm.bit_6_swizzle_x;
 373                         break;
 374                 case I915_TILING_Y:
 375                         tile.swizzle = i915->mm.bit_6_swizzle_y;
 376                         break;
 377                 }
 378
 379                 GEM_BUG_ON(tile.swizzle == I915_BIT_6_SWIZZLE_UNKNOWN);
 380                 if (tile.swizzle == I915_BIT_6_SWIZZLE_9_17 ||
 381                     tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)
 382                         continue;
 383
 384                 if (INTEL_GEN(i915) <= 2) {
 385                         tile.height = 16;
 386                         tile.width = 128;
 387                         tile.size = 11;
 388                 } else if (tile.tiling == I915_TILING_Y &&
 389                            HAS_128_BYTE_Y_TILING(i915)) {
 390                         tile.height = 32;
 391                         tile.width = 128;
 392                         tile.size = 12;
 393                 } else {
 394                         tile.height = 8;
 395                         tile.width = 512;
 396                         tile.size = 12;
 397                 }
 398
 399                 if (INTEL_GEN(i915) < 4)
 400                         max_pitch = 8192 / tile.width;
 401                 else if (INTEL_GEN(i915) < 7)
 402                         max_pitch = 128 * I965_FENCE_MAX_PITCH_VAL / tile.width;
 403                 else
 404                         max_pitch = 128 * GEN7_FENCE_MAX_PITCH_VAL / tile.width;
 405
 406                 for (pitch = max_pitch; pitch; pitch >>= 1) {
 407                         tile.stride = tile.width * pitch;
 408                         err = check_partial_mapping(obj, &tile, end);
 409                         if (err == -EINTR)
 410                                 goto next_tiling;
 411                         if (err)
 412                                 goto out_unlock;
 413
 414                         if (pitch > 2 && INTEL_GEN(i915) >= 4) {
 415                                 tile.stride = tile.width * (pitch - 1);
 416                                 err = check_partial_mapping(obj, &tile, end);
 417                                 if (err == -EINTR)
 418                                         goto next_tiling;
 419                                 if (err)
 420                                         goto out_unlock;
 421                         }
 422
 423                         if (pitch < max_pitch && INTEL_GEN(i915) >= 4) {
 424                                 tile.stride = tile.width * (pitch + 1);
 425                                 err = check_partial_mapping(obj, &tile, end);
 426                                 if (err == -EINTR)
 427                                         goto next_tiling;
 428                                 if (err)
 429                                         goto out_unlock;
 430                         }
 431                 }
 432
 433                 if (INTEL_GEN(i915) >= 4) {
 434                         for_each_prime_number(pitch, max_pitch) {
 435                                 tile.stride = tile.width * pitch;
 436                                 err = check_partial_mapping(obj, &tile, end);
 437                                 if (err == -EINTR)
 438                                         goto next_tiling;
 439                                 if (err)
 440                                         goto out_unlock;
 441                         }
 442                 }
 443
 444 next_tiling: ;
 445         }
 446
 447 out_unlock:
 448         intel_runtime_pm_put(i915, wakeref);
 449         mutex_unlock(&i915->drm.struct_mutex);
 450         i915_gem_object_unpin_pages(obj);
 451 out:
 452         i915_gem_object_put(obj);
 453         return err;
 454 }
 455
 456 static int make_obj_busy(struct drm_i915_gem_object *obj)
 457 {
 458         struct drm_i915_private *i915 = to_i915(obj->base.dev);
 459         struct i915_request *rq;
 460         struct i915_vma *vma;
 461         int err;
 462
 463         vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
 464         if (IS_ERR(vma))
 465                 return PTR_ERR(vma);
 466
 467         err = i915_vma_pin(vma, 0, 0, PIN_USER);
 468         if (err)
 469                 return err;
 470
 471         rq = i915_request_alloc(i915->engine[RCS], i915->kernel_context);
 472         if (IS_ERR(rq)) {
 473                 i915_vma_unpin(vma);
 474                 return PTR_ERR(rq);
 475         }
 476
 477         err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
 478
 479         i915_request_add(rq);
 480
 481         __i915_gem_object_release_unless_active(obj);
 482         i915_vma_unpin(vma);
 483
 484         return err;
 485 }
 486
 487 static bool assert_mmap_offset(struct drm_i915_private *i915,
 488                                unsigned long size,
 489                                int expected)
 490 {
 491         struct drm_i915_gem_object *obj;
 492         int err;
 493
 494         obj = i915_gem_object_create_internal(i915, size);
 495         if (IS_ERR(obj))
 496                 return PTR_ERR(obj);
 497
 498         err = i915_gem_object_create_mmap_offset(obj);
 499         i915_gem_object_put(obj);
 500
 501         return err == expected;
 502 }
 503
 504 static void disable_retire_worker(struct drm_i915_private *i915)
 505 {
 506         i915_gem_shrinker_unregister(i915);
 507
 508         mutex_lock(&i915->drm.struct_mutex);
 509         if (!i915->gt.active_requests++) {
 510                 intel_wakeref_t wakeref;
 511
 512                 with_intel_runtime_pm(i915, wakeref)
 513                         i915_gem_unpark(i915);
 514         }
 515         mutex_unlock(&i915->drm.struct_mutex);
 516
 517         cancel_delayed_work_sync(&i915->gt.retire_work);
 518         cancel_delayed_work_sync(&i915->gt.idle_work);
 519 }
 520
 521 static int igt_mmap_offset_exhaustion(void *arg)
 522 {
 523         struct drm_i915_private *i915 = arg;
 524         struct drm_mm *mm = &i915->drm.vma_offset_manager->vm_addr_space_mm;
 525         struct drm_i915_gem_object *obj;
 526         struct drm_mm_node resv, *hole;
 527         u64 hole_start, hole_end;
 528         int loop, err;
 529
 530         /* Disable background reaper */
 531         disable_retire_worker(i915);
 532         GEM_BUG_ON(!i915->gt.awake);
 533
 534         /* Trim the device mmap space to only a page */
 535         memset(&resv, 0, sizeof(resv));
 536         drm_mm_for_each_hole(hole, mm, hole_start, hole_end) {
 537                 resv.start = hole_start;
 538                 resv.size = hole_end - hole_start - 1; /* PAGE_SIZE units */
 539                 err = drm_mm_reserve_node(mm, &resv);
 540                 if (err) {
 541                         pr_err("Failed to trim VMA manager, err=%d\n", err);
 542                         goto out_park;
 543                 }
 544                 break;
 545         }
 546
 547         /* Just fits! */
 548         if (!assert_mmap_offset(i915, PAGE_SIZE, 0)) {
 549                 pr_err("Unable to insert object into single page hole\n");
 550                 err = -EINVAL;
 551                 goto out;
 552         }
 553
 554         /* Too large */
 555         if (!assert_mmap_offset(i915, 2*PAGE_SIZE, -ENOSPC)) {
 556                 pr_err("Unexpectedly succeeded in inserting too large object into single page hole\n");
 557                 err = -EINVAL;
 558                 goto out;
 559         }
 560
 561         /* Fill the hole, further allocation attempts should then fail */
 562         obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
 563         if (IS_ERR(obj)) {
 564                 err = PTR_ERR(obj);
 565                 goto out;
 566         }
 567
 568         err = i915_gem_object_create_mmap_offset(obj);
 569         if (err) {
 570                 pr_err("Unable to insert object into reclaimed hole\n");
 571                 goto err_obj;
 572         }
 573
 574         if (!assert_mmap_offset(i915, PAGE_SIZE, -ENOSPC)) {
 575                 pr_err("Unexpectedly succeeded in inserting object into no holes!\n");
 576                 err = -EINVAL;
 577                 goto err_obj;
 578         }
 579
 580         i915_gem_object_put(obj);
 581
 582         /* Now fill with busy dead objects that we expect to reap */
 583         for (loop = 0; loop < 3; loop++) {
 584                 intel_wakeref_t wakeref;
 585
 586                 if (i915_terminally_wedged(&i915->gpu_error))
 587                         break;
 588
 589                 obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
 590                 if (IS_ERR(obj)) {
 591                         err = PTR_ERR(obj);
 592                         goto out;
 593                 }
 594
 595                 err = 0;
 596                 mutex_lock(&i915->drm.struct_mutex);
 597                 with_intel_runtime_pm(i915, wakeref)
 598                         err = make_obj_busy(obj);
 599                 mutex_unlock(&i915->drm.struct_mutex);
 600                 if (err) {
 601                         pr_err("[loop %d] Failed to busy the object\n", loop);
 602                         goto err_obj;
 603                 }
 604
 605                 /* NB we rely on the _active_ reference to access obj now */
 606                 GEM_BUG_ON(!i915_gem_object_is_active(obj));
 607                 err = i915_gem_object_create_mmap_offset(obj);
 608                 if (err) {
 609                         pr_err("[loop %d] i915_gem_object_create_mmap_offset failed with err=%d\n",
 610                                loop, err);
 611                         goto out;
 612                 }
 613         }
 614
 615 out:
 616         drm_mm_remove_node(&resv);
 617 out_park:
 618         mutex_lock(&i915->drm.struct_mutex);
 619         if (--i915->gt.active_requests)
 620                 queue_delayed_work(i915->wq, &i915->gt.retire_work, 0);
 621         else
 622                 queue_delayed_work(i915->wq, &i915->gt.idle_work, 0);
 623         mutex_unlock(&i915->drm.struct_mutex);
 624         i915_gem_shrinker_register(i915);
 625         return err;
 626 err_obj:
 627         i915_gem_object_put(obj);
 628         goto out;
 629 }
 630
 631 int i915_gem_object_mock_selftests(void)
 632 {
 633         static const struct i915_subtest tests[] = {
 634                 SUBTEST(igt_gem_object),
 635                 SUBTEST(igt_phys_object),
 636         };
 637         struct drm_i915_private *i915;
 638         int err;
 639
 640         i915 = mock_gem_device();
 641         if (!i915)
 642                 return -ENOMEM;
 643
 644         err = i915_subtests(tests, i915);
 645
 646         drm_dev_put(&i915->drm);
 647         return err;
 648 }
 649
 650 int i915_gem_object_live_selftests(struct drm_i915_private *i915)
 651 {
 652         static const struct i915_subtest tests[] = {
 653                 SUBTEST(igt_gem_huge),
 654                 SUBTEST(igt_partial_tiling),
 655                 SUBTEST(igt_mmap_offset_exhaustion),
 656         };
 657
 658         return i915_subtests(tests, i915);
 659 }