drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_fourcc.h>
  36 #include <drm/drm_rect.h>
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include "intel_drv.h"
  40 #include "intel_frontbuffer.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  45                              int usecs)
  46 {
  47         /* paranoia */
  48         if (!adjusted_mode->crtc_htotal)
  49                 return 1;
  50
  51         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  52                             1000 * adjusted_mode->crtc_htotal);
  53 }
  54
  55 /* FIXME: We should instead only take spinlocks once for the entire update
  56  * instead of once per mmio. */
  57 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
  58 #define VBLANK_EVASION_TIME_US 250
  59 #else
  60 #define VBLANK_EVASION_TIME_US 100
  61 #endif
  62
  63 /**
  64  * intel_pipe_update_start() - start update of a set of display registers
  65  * @new_crtc_state: the new crtc state
  66  *
  67  * Mark the start of an update to pipe registers that should be updated
  68  * atomically regarding vblank. If the next vblank will happens within
  69  * the next 100 us, this function waits until the vblank passes.
  70  *
  71  * After a successful call to this function, interrupts will be disabled
  72  * until a subsequent call to intel_pipe_update_end(). That is done to
  73  * avoid random delays.
  74  */
  75 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
  76 {
  77         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
  78         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  79         const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
  80         long timeout = msecs_to_jiffies_timeout(1);
  81         int scanline, min, max, vblank_start;
  82         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  83         bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
  84                 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
  85         DEFINE_WAIT(wait);
  86         u32 psr_status;
  87
  88         vblank_start = adjusted_mode->crtc_vblank_start;
  89         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  90                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  91
  92         /* FIXME needs to be calibrated sensibly */
  93         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
  94                                                       VBLANK_EVASION_TIME_US);
  95         max = vblank_start - 1;
  96
  97         if (min <= 0 || max <= 0)
  98                 goto irq_disable;
  99
 100         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 101                 goto irq_disable;
 102
 103         /*
 104          * Wait for psr to idle out after enabling the VBL interrupts
 105          * VBL interrupts will start the PSR exit and prevent a PSR
 106          * re-entry as well.
 107          */
 108         if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
 109                 DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n",
 110                           psr_status);
 111
 112         local_irq_disable();
 113
 114         crtc->debug.min_vbl = min;
 115         crtc->debug.max_vbl = max;
 116         trace_i915_pipe_update_start(crtc);
 117
 118         for (;;) {
 119                 /*
 120                  * prepare_to_wait() has a memory barrier, which guarantees
 121                  * other CPUs can see the task state update by the time we
 122                  * read the scanline.
 123                  */
 124                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 125
 126                 scanline = intel_get_crtc_scanline(crtc);
 127                 if (scanline < min || scanline > max)
 128                         break;
 129
 130                 if (!timeout) {
 131                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 132                                   pipe_name(crtc->pipe));
 133                         break;
 134                 }
 135
 136                 local_irq_enable();
 137
 138                 timeout = schedule_timeout(timeout);
 139
 140                 local_irq_disable();
 141         }
 142
 143         finish_wait(wq, &wait);
 144
 145         drm_crtc_vblank_put(&crtc->base);
 146
 147         /*
 148          * On VLV/CHV DSI the scanline counter would appear to
 149          * increment approx. 1/3 of a scanline before start of vblank.
 150          * The registers still get latched at start of vblank however.
 151          * This means we must not write any registers on the first
 152          * line of vblank (since not the whole line is actually in
 153          * vblank). And unfortunately we can't use the interrupt to
 154          * wait here since it will fire too soon. We could use the
 155          * frame start interrupt instead since it will fire after the
 156          * critical scanline, but that would require more changes
 157          * in the interrupt code. So for now we'll just do the nasty
 158          * thing and poll for the bad scanline to pass us by.
 159          *
 160          * FIXME figure out if BXT+ DSI suffers from this as well
 161          */
 162         while (need_vlv_dsi_wa && scanline == vblank_start)
 163                 scanline = intel_get_crtc_scanline(crtc);
 164
 165         crtc->debug.scanline_start = scanline;
 166         crtc->debug.start_vbl_time = ktime_get();
 167         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 168
 169         trace_i915_pipe_update_vblank_evaded(crtc);
 170         return;
 171
 172 irq_disable:
 173         local_irq_disable();
 174 }
 175
 176 /**
 177  * intel_pipe_update_end() - end update of a set of display registers
 178  * @new_crtc_state: the new crtc state
 179  *
 180  * Mark the end of an update started with intel_pipe_update_start(). This
 181  * re-enables interrupts and verifies the update was actually completed
 182  * before a vblank.
 183  */
 184 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 185 {
 186         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
 187         enum pipe pipe = crtc->pipe;
 188         int scanline_end = intel_get_crtc_scanline(crtc);
 189         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 190         ktime_t end_vbl_time = ktime_get();
 191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 192
 193         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 194
 195         /* We're still in the vblank-evade critical section, this can't race.
 196          * Would be slightly nice to just grab the vblank count and arm the
 197          * event outside of the critical section - the spinlock might spin for a
 198          * while ... */
 199         if (new_crtc_state->base.event) {
 200                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 201
 202                 spin_lock(&crtc->base.dev->event_lock);
 203                 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
 204                 spin_unlock(&crtc->base.dev->event_lock);
 205
 206                 new_crtc_state->base.event = NULL;
 207         }
 208
 209         local_irq_enable();
 210
 211         if (intel_vgpu_active(dev_priv))
 212                 return;
 213
 214         if (crtc->debug.start_vbl_count &&
 215             crtc->debug.start_vbl_count != end_vbl_count) {
 216                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 217                           pipe_name(pipe), crtc->debug.start_vbl_count,
 218                           end_vbl_count,
 219                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 220                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 221                           crtc->debug.scanline_start, scanline_end);
 222         }
 223 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
 224         else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 225                  VBLANK_EVASION_TIME_US)
 226                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 227                          pipe_name(pipe),
 228                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 229                          VBLANK_EVASION_TIME_US);
 230 #endif
 231 }
 232
 233 int intel_plane_check_stride(const struct intel_plane_state *plane_state)
 234 {
 235         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 236         const struct drm_framebuffer *fb = plane_state->base.fb;
 237         unsigned int rotation = plane_state->base.rotation;
 238         u32 stride, max_stride;
 239
 240         /* FIXME other color planes? */
 241         stride = plane_state->color_plane[0].stride;
 242         max_stride = plane->max_stride(plane, fb->format->format,
 243                                        fb->modifier, rotation);
 244
 245         if (stride > max_stride) {
 246                 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
 247                               fb->base.id, stride,
 248                               plane->base.base.id, plane->base.name, max_stride);
 249                 return -EINVAL;
 250         }
 251
 252         return 0;
 253 }
 254
 255 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 256 {
 257         const struct drm_framebuffer *fb = plane_state->base.fb;
 258         struct drm_rect *src = &plane_state->base.src;
 259         u32 src_x, src_y, src_w, src_h;
 260
 261         /*
 262          * Hardware doesn't handle subpixel coordinates.
 263          * Adjust to (macro)pixel boundary, but be careful not to
 264          * increase the source viewport size, because that could
 265          * push the downscaling factor out of bounds.
 266          */
 267         src_x = src->x1 >> 16;
 268         src_w = drm_rect_width(src) >> 16;
 269         src_y = src->y1 >> 16;
 270         src_h = drm_rect_height(src) >> 16;
 271
 272         src->x1 = src_x << 16;
 273         src->x2 = (src_x + src_w) << 16;
 274         src->y1 = src_y << 16;
 275         src->y2 = (src_y + src_h) << 16;
 276
 277         if (fb->format->is_yuv &&
 278             fb->format->format != DRM_FORMAT_NV12 &&
 279             (src_x & 1 || src_w & 1)) {
 280                 DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
 281                               src_x, src_w);
 282                 return -EINVAL;
 283         }
 284
 285         return 0;
 286 }
 287
 288 unsigned int
 289 skl_plane_max_stride(struct intel_plane *plane,
 290                      u32 pixel_format, u64 modifier,
 291                      unsigned int rotation)
 292 {
 293         int cpp = drm_format_plane_cpp(pixel_format, 0);
 294
 295         /*
 296          * "The stride in bytes must not exceed the
 297          * of the size of 8K pixels and 32K bytes."
 298          */
 299         if (drm_rotation_90_or_270(rotation))
 300                 return min(8192, 32768 / cpp);
 301         else
 302                 return min(8192 * cpp, 32768);
 303 }
 304
 305 static void
 306 skl_program_scaler(struct intel_plane *plane,
 307                    const struct intel_crtc_state *crtc_state,
 308                    const struct intel_plane_state *plane_state)
 309 {
 310         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 311         enum pipe pipe = plane->pipe;
 312         int scaler_id = plane_state->scaler_id;
 313         const struct intel_scaler *scaler =
 314                 &crtc_state->scaler_state.scalers[scaler_id];
 315         int crtc_x = plane_state->base.dst.x1;
 316         int crtc_y = plane_state->base.dst.y1;
 317         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 318         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 319         u16 y_hphase, uv_rgb_hphase;
 320         u16 y_vphase, uv_rgb_vphase;
 321
 322         /* TODO: handle sub-pixel coordinates */
 323         if (plane_state->base.fb->format->format == DRM_FORMAT_NV12) {
 324                 y_hphase = skl_scaler_calc_phase(1, false);
 325                 y_vphase = skl_scaler_calc_phase(1, false);
 326
 327                 /* MPEG2 chroma siting convention */
 328                 uv_rgb_hphase = skl_scaler_calc_phase(2, true);
 329                 uv_rgb_vphase = skl_scaler_calc_phase(2, false);
 330         } else {
 331                 /* not used */
 332                 y_hphase = 0;
 333                 y_vphase = 0;
 334
 335                 uv_rgb_hphase = skl_scaler_calc_phase(1, false);
 336                 uv_rgb_vphase = skl_scaler_calc_phase(1, false);
 337         }
 338
 339         I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 340                       PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);
 341         I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 342         I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
 343                       PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
 344         I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
 345                       PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
 346         I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 347         I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);
 348 }
 349
 350 void
 351 skl_update_plane(struct intel_plane *plane,
 352                  const struct intel_crtc_state *crtc_state,
 353                  const struct intel_plane_state *plane_state)
 354 {
 355         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 356         enum plane_id plane_id = plane->id;
 357         enum pipe pipe = plane->pipe;
 358         u32 plane_ctl = plane_state->ctl;
 359         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 360         u32 surf_addr = plane_state->color_plane[0].offset;
 361         u32 stride = skl_plane_stride(plane_state, 0);
 362         u32 aux_stride = skl_plane_stride(plane_state, 1);
 363         int crtc_x = plane_state->base.dst.x1;
 364         int crtc_y = plane_state->base.dst.y1;
 365         uint32_t x = plane_state->color_plane[0].x;
 366         uint32_t y = plane_state->color_plane[0].y;
 367         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 368         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 369         unsigned long irqflags;
 370
 371         /* Sizes are 0 based */
 372         src_w--;
 373         src_h--;
 374
 375         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 376
 377         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 378                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 379                               plane_state->color_ctl);
 380
 381         if (key->flags) {
 382                 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 383                 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 384                 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 385         }
 386
 387         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 388         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 389         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 390         I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 391                       (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
 392         I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
 393                       (plane_state->color_plane[1].y << 16) |
 394                       plane_state->color_plane[1].x);
 395
 396         if (plane_state->scaler_id >= 0) {
 397                 skl_program_scaler(plane, crtc_state, plane_state);
 398
 399                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
 400         } else {
 401                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 402         }
 403
 404         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 405         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 406                       intel_plane_ggtt_offset(plane_state) + surf_addr);
 407         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 408
 409         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 410 }
 411
 412 void
 413 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 414 {
 415         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 416         enum plane_id plane_id = plane->id;
 417         enum pipe pipe = plane->pipe;
 418         unsigned long irqflags;
 419
 420         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 421
 422         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 423
 424         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 425         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 426
 427         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 428 }
 429
 430 bool
 431 skl_plane_get_hw_state(struct intel_plane *plane,
 432                        enum pipe *pipe)
 433 {
 434         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 435         enum intel_display_power_domain power_domain;
 436         enum plane_id plane_id = plane->id;
 437         bool ret;
 438
 439         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 440         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 441                 return false;
 442
 443         ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
 444
 445         *pipe = plane->pipe;
 446
 447         intel_display_power_put(dev_priv, power_domain);
 448
 449         return ret;
 450 }
 451
 452 static void
 453 chv_update_csc(const struct intel_plane_state *plane_state)
 454 {
 455         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 456         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 457         const struct drm_framebuffer *fb = plane_state->base.fb;
 458         enum plane_id plane_id = plane->id;
 459         /*
 460          * |r|   | c0 c1 c2 |   |cr|
 461          * |g| = | c3 c4 c5 | x |y |
 462          * |b|   | c6 c7 c8 |   |cb|
 463          *
 464          * Coefficients are s3.12.
 465          *
 466          * Cb and Cr apparently come in as signed already, and
 467          * we always get full range data in on account of CLRC0/1.
 468          */
 469         static const s16 csc_matrix[][9] = {
 470                 /* BT.601 full range YCbCr -> full range RGB */
 471                 [DRM_COLOR_YCBCR_BT601] = {
 472                          5743, 4096,     0,
 473                         -2925, 4096, -1410,
 474                             0, 4096,  7258,
 475                 },
 476                 /* BT.709 full range YCbCr -> full range RGB */
 477                 [DRM_COLOR_YCBCR_BT709] = {
 478                          6450, 4096,     0,
 479                         -1917, 4096,  -767,
 480                             0, 4096,  7601,
 481                 },
 482         };
 483         const s16 *csc = csc_matrix[plane_state->base.color_encoding];
 484
 485         /* Seems RGB data bypasses the CSC always */
 486         if (!fb->format->is_yuv)
 487                 return;
 488
 489         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 490         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 491         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 492
 493         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
 494         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
 495         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
 496         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
 497         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
 498
 499         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
 500         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 501         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 502
 503         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 504         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 505         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 506 }
 507
 508 #define SIN_0 0
 509 #define COS_0 1
 510
 511 static void
 512 vlv_update_clrc(const struct intel_plane_state *plane_state)
 513 {
 514         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 515         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 516         const struct drm_framebuffer *fb = plane_state->base.fb;
 517         enum pipe pipe = plane->pipe;
 518         enum plane_id plane_id = plane->id;
 519         int contrast, brightness, sh_scale, sh_sin, sh_cos;
 520
 521         if (fb->format->is_yuv &&
 522             plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
 523                 /*
 524                  * Expand limited range to full range:
 525                  * Contrast is applied first and is used to expand Y range.
 526                  * Brightness is applied second and is used to remove the
 527                  * offset from Y. Saturation/hue is used to expand CbCr range.
 528                  */
 529                 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
 530                 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
 531                 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
 532                 sh_sin = SIN_0 * sh_scale;
 533                 sh_cos = COS_0 * sh_scale;
 534         } else {
 535                 /* Pass-through everything. */
 536                 contrast = 1 << 6;
 537                 brightness = 0;
 538                 sh_scale = 1 << 7;
 539                 sh_sin = SIN_0 * sh_scale;
 540                 sh_cos = COS_0 * sh_scale;
 541         }
 542
 543         /* FIXME these register are single buffered :( */
 544         I915_WRITE_FW(SPCLRC0(pipe, plane_id),
 545                       SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
 546         I915_WRITE_FW(SPCLRC1(pipe, plane_id),
 547                       SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
 548 }
 549
 550 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 551                           const struct intel_plane_state *plane_state)
 552 {
 553         const struct drm_framebuffer *fb = plane_state->base.fb;
 554         unsigned int rotation = plane_state->base.rotation;
 555         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 556         u32 sprctl;
 557
 558         sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
 559
 560         switch (fb->format->format) {
 561         case DRM_FORMAT_YUYV:
 562                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 563                 break;
 564         case DRM_FORMAT_YVYU:
 565                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 566                 break;
 567         case DRM_FORMAT_UYVY:
 568                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 569                 break;
 570         case DRM_FORMAT_VYUY:
 571                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 572                 break;
 573         case DRM_FORMAT_RGB565:
 574                 sprctl |= SP_FORMAT_BGR565;
 575                 break;
 576         case DRM_FORMAT_XRGB8888:
 577                 sprctl |= SP_FORMAT_BGRX8888;
 578                 break;
 579         case DRM_FORMAT_ARGB8888:
 580                 sprctl |= SP_FORMAT_BGRA8888;
 581                 break;
 582         case DRM_FORMAT_XBGR2101010:
 583                 sprctl |= SP_FORMAT_RGBX1010102;
 584                 break;
 585         case DRM_FORMAT_ABGR2101010:
 586                 sprctl |= SP_FORMAT_RGBA1010102;
 587                 break;
 588         case DRM_FORMAT_XBGR8888:
 589                 sprctl |= SP_FORMAT_RGBX8888;
 590                 break;
 591         case DRM_FORMAT_ABGR8888:
 592                 sprctl |= SP_FORMAT_RGBA8888;
 593                 break;
 594         default:
 595                 MISSING_CASE(fb->format->format);
 596                 return 0;
 597         }
 598
 599         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 600                 sprctl |= SP_YUV_FORMAT_BT709;
 601
 602         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 603                 sprctl |= SP_TILED;
 604
 605         if (rotation & DRM_MODE_ROTATE_180)
 606                 sprctl |= SP_ROTATE_180;
 607
 608         if (rotation & DRM_MODE_REFLECT_X)
 609                 sprctl |= SP_MIRROR;
 610
 611         if (key->flags & I915_SET_COLORKEY_SOURCE)
 612                 sprctl |= SP_SOURCE_KEY;
 613
 614         return sprctl;
 615 }
 616
 617 static void
 618 vlv_update_plane(struct intel_plane *plane,
 619                  const struct intel_crtc_state *crtc_state,
 620                  const struct intel_plane_state *plane_state)
 621 {
 622         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 623         const struct drm_framebuffer *fb = plane_state->base.fb;
 624         enum pipe pipe = plane->pipe;
 625         enum plane_id plane_id = plane->id;
 626         u32 sprctl = plane_state->ctl;
 627         u32 sprsurf_offset = plane_state->color_plane[0].offset;
 628         u32 linear_offset;
 629         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 630         int crtc_x = plane_state->base.dst.x1;
 631         int crtc_y = plane_state->base.dst.y1;
 632         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 633         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 634         uint32_t x = plane_state->color_plane[0].x;
 635         uint32_t y = plane_state->color_plane[0].y;
 636         unsigned long irqflags;
 637
 638         /* Sizes are 0 based */
 639         crtc_w--;
 640         crtc_h--;
 641
 642         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 643
 644         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 645
 646         vlv_update_clrc(plane_state);
 647
 648         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 649                 chv_update_csc(plane_state);
 650
 651         if (key->flags) {
 652                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
 653                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 654                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
 655         }
 656         I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
 657                       plane_state->color_plane[0].stride);
 658         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 659
 660         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 661                 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 662         else
 663                 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
 664
 665         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
 666
 667         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 668         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
 669         I915_WRITE_FW(SPSURF(pipe, plane_id),
 670                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 671         POSTING_READ_FW(SPSURF(pipe, plane_id));
 672
 673         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 674 }
 675
 676 static void
 677 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 678 {
 679         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 680         enum pipe pipe = plane->pipe;
 681         enum plane_id plane_id = plane->id;
 682         unsigned long irqflags;
 683
 684         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 685
 686         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
 687
 688         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
 689         POSTING_READ_FW(SPSURF(pipe, plane_id));
 690
 691         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 692 }
 693
 694 static bool
 695 vlv_plane_get_hw_state(struct intel_plane *plane,
 696                        enum pipe *pipe)
 697 {
 698         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 699         enum intel_display_power_domain power_domain;
 700         enum plane_id plane_id = plane->id;
 701         bool ret;
 702
 703         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 704         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 705                 return false;
 706
 707         ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
 708
 709         *pipe = plane->pipe;
 710
 711         intel_display_power_put(dev_priv, power_domain);
 712
 713         return ret;
 714 }
 715
 716 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 717                           const struct intel_plane_state *plane_state)
 718 {
 719         struct drm_i915_private *dev_priv =
 720                 to_i915(plane_state->base.plane->dev);
 721         const struct drm_framebuffer *fb = plane_state->base.fb;
 722         unsigned int rotation = plane_state->base.rotation;
 723         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 724         u32 sprctl;
 725
 726         sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
 727
 728         if (IS_IVYBRIDGE(dev_priv))
 729                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 730
 731         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 732                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 733
 734         switch (fb->format->format) {
 735         case DRM_FORMAT_XBGR8888:
 736                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 737                 break;
 738         case DRM_FORMAT_XRGB8888:
 739                 sprctl |= SPRITE_FORMAT_RGBX888;
 740                 break;
 741         case DRM_FORMAT_YUYV:
 742                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 743                 break;
 744         case DRM_FORMAT_YVYU:
 745                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 746                 break;
 747         case DRM_FORMAT_UYVY:
 748                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 749                 break;
 750         case DRM_FORMAT_VYUY:
 751                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 752                 break;
 753         default:
 754                 MISSING_CASE(fb->format->format);
 755                 return 0;
 756         }
 757
 758         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 759                 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
 760
 761         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 762                 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
 763
 764         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 765                 sprctl |= SPRITE_TILED;
 766
 767         if (rotation & DRM_MODE_ROTATE_180)
 768                 sprctl |= SPRITE_ROTATE_180;
 769
 770         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 771                 sprctl |= SPRITE_DEST_KEY;
 772         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 773                 sprctl |= SPRITE_SOURCE_KEY;
 774
 775         return sprctl;
 776 }
 777
 778 static void
 779 ivb_update_plane(struct intel_plane *plane,
 780                  const struct intel_crtc_state *crtc_state,
 781                  const struct intel_plane_state *plane_state)
 782 {
 783         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 784         const struct drm_framebuffer *fb = plane_state->base.fb;
 785         enum pipe pipe = plane->pipe;
 786         u32 sprctl = plane_state->ctl, sprscale = 0;
 787         u32 sprsurf_offset = plane_state->color_plane[0].offset;
 788         u32 linear_offset;
 789         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 790         int crtc_x = plane_state->base.dst.x1;
 791         int crtc_y = plane_state->base.dst.y1;
 792         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 793         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 794         uint32_t x = plane_state->color_plane[0].x;
 795         uint32_t y = plane_state->color_plane[0].y;
 796         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 797         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 798         unsigned long irqflags;
 799
 800         /* Sizes are 0 based */
 801         src_w--;
 802         src_h--;
 803         crtc_w--;
 804         crtc_h--;
 805
 806         if (crtc_w != src_w || crtc_h != src_h)
 807                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 808
 809         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 810
 811         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 812
 813         if (key->flags) {
 814                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
 815                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
 816                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
 817         }
 818
 819         I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
 820         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 821
 822         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 823          * register */
 824         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 825                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
 826         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 827                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 828         else
 829                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
 830
 831         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 832         if (IS_IVYBRIDGE(dev_priv))
 833                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
 834         I915_WRITE_FW(SPRCTL(pipe), sprctl);
 835         I915_WRITE_FW(SPRSURF(pipe),
 836                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 837         POSTING_READ_FW(SPRSURF(pipe));
 838
 839         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 840 }
 841
 842 static void
 843 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 844 {
 845         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 846         enum pipe pipe = plane->pipe;
 847         unsigned long irqflags;
 848
 849         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 850
 851         I915_WRITE_FW(SPRCTL(pipe), 0);
 852         /* Can't leave the scaler enabled... */
 853         if (IS_IVYBRIDGE(dev_priv))
 854                 I915_WRITE_FW(SPRSCALE(pipe), 0);
 855
 856         I915_WRITE_FW(SPRSURF(pipe), 0);
 857         POSTING_READ_FW(SPRSURF(pipe));
 858
 859         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 860 }
 861
 862 static bool
 863 ivb_plane_get_hw_state(struct intel_plane *plane,
 864                        enum pipe *pipe)
 865 {
 866         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 867         enum intel_display_power_domain power_domain;
 868         bool ret;
 869
 870         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 871         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 872                 return false;
 873
 874         ret =  I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;
 875
 876         *pipe = plane->pipe;
 877
 878         intel_display_power_put(dev_priv, power_domain);
 879
 880         return ret;
 881 }
 882
 883 static unsigned int
 884 g4x_sprite_max_stride(struct intel_plane *plane,
 885                       u32 pixel_format, u64 modifier,
 886                       unsigned int rotation)
 887 {
 888         return 16384;
 889 }
 890
 891 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 892                           const struct intel_plane_state *plane_state)
 893 {
 894         struct drm_i915_private *dev_priv =
 895                 to_i915(plane_state->base.plane->dev);
 896         const struct drm_framebuffer *fb = plane_state->base.fb;
 897         unsigned int rotation = plane_state->base.rotation;
 898         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 899         u32 dvscntr;
 900
 901         dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
 902
 903         if (IS_GEN6(dev_priv))
 904                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
 905
 906         switch (fb->format->format) {
 907         case DRM_FORMAT_XBGR8888:
 908                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 909                 break;
 910         case DRM_FORMAT_XRGB8888:
 911                 dvscntr |= DVS_FORMAT_RGBX888;
 912                 break;
 913         case DRM_FORMAT_YUYV:
 914                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 915                 break;
 916         case DRM_FORMAT_YVYU:
 917                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 918                 break;
 919         case DRM_FORMAT_UYVY:
 920                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 921                 break;
 922         case DRM_FORMAT_VYUY:
 923                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 924                 break;
 925         default:
 926                 MISSING_CASE(fb->format->format);
 927                 return 0;
 928         }
 929
 930         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 931                 dvscntr |= DVS_YUV_FORMAT_BT709;
 932
 933         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 934                 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
 935
 936         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 937                 dvscntr |= DVS_TILED;
 938
 939         if (rotation & DRM_MODE_ROTATE_180)
 940                 dvscntr |= DVS_ROTATE_180;
 941
 942         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 943                 dvscntr |= DVS_DEST_KEY;
 944         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 945                 dvscntr |= DVS_SOURCE_KEY;
 946
 947         return dvscntr;
 948 }
 949
 950 static void
 951 g4x_update_plane(struct intel_plane *plane,
 952                  const struct intel_crtc_state *crtc_state,
 953                  const struct intel_plane_state *plane_state)
 954 {
 955         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 956         const struct drm_framebuffer *fb = plane_state->base.fb;
 957         enum pipe pipe = plane->pipe;
 958         u32 dvscntr = plane_state->ctl, dvsscale = 0;
 959         u32 dvssurf_offset = plane_state->color_plane[0].offset;
 960         u32 linear_offset;
 961         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 962         int crtc_x = plane_state->base.dst.x1;
 963         int crtc_y = plane_state->base.dst.y1;
 964         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 965         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 966         uint32_t x = plane_state->color_plane[0].x;
 967         uint32_t y = plane_state->color_plane[0].y;
 968         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 969         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 970         unsigned long irqflags;
 971
 972         /* Sizes are 0 based */
 973         src_w--;
 974         src_h--;
 975         crtc_w--;
 976         crtc_h--;
 977
 978         if (crtc_w != src_w || crtc_h != src_h)
 979                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 980
 981         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 982
 983         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 984
 985         if (key->flags) {
 986                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
 987                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
 988                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
 989         }
 990
 991         I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
 992         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 993
 994         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 995                 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
 996         else
 997                 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
 998
 999         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
1000         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
1001         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
1002         I915_WRITE_FW(DVSSURF(pipe),
1003                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
1004         POSTING_READ_FW(DVSSURF(pipe));
1005
1006         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1007 }
1008
1009 static void
1010 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
1011 {
1012         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1013         enum pipe pipe = plane->pipe;
1014         unsigned long irqflags;
1015
1016         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1017
1018         I915_WRITE_FW(DVSCNTR(pipe), 0);
1019         /* Disable the scaler */
1020         I915_WRITE_FW(DVSSCALE(pipe), 0);
1021
1022         I915_WRITE_FW(DVSSURF(pipe), 0);
1023         POSTING_READ_FW(DVSSURF(pipe));
1024
1025         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1026 }
1027
1028 static bool
1029 g4x_plane_get_hw_state(struct intel_plane *plane,
1030                        enum pipe *pipe)
1031 {
1032         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1033         enum intel_display_power_domain power_domain;
1034         bool ret;
1035
1036         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1037         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1038                 return false;
1039
1040         ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;
1041
1042         *pipe = plane->pipe;
1043
1044         intel_display_power_put(dev_priv, power_domain);
1045
1046         return ret;
1047 }
1048
1049 static int
1050 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
1051                          struct intel_plane_state *plane_state)
1052 {
1053         const struct drm_framebuffer *fb = plane_state->base.fb;
1054         const struct drm_rect *src = &plane_state->base.src;
1055         const struct drm_rect *dst = &plane_state->base.dst;
1056         int src_x, src_y, src_w, src_h, crtc_w, crtc_h;
1057         const struct drm_display_mode *adjusted_mode =
1058                 &crtc_state->base.adjusted_mode;
1059         unsigned int cpp = fb->format->cpp[0];
1060         unsigned int width_bytes;
1061         int min_width, min_height;
1062
1063         crtc_w = drm_rect_width(dst);
1064         crtc_h = drm_rect_height(dst);
1065
1066         src_x = src->x1 >> 16;
1067         src_y = src->y1 >> 16;
1068         src_w = drm_rect_width(src) >> 16;
1069         src_h = drm_rect_height(src) >> 16;
1070
1071         if (src_w == crtc_w && src_h == crtc_h)
1072                 return 0;
1073
1074         min_width = 3;
1075
1076         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1077                 if (src_h & 1) {
1078                         DRM_DEBUG_KMS("Source height must be even with interlaced modes\n");
1079                         return -EINVAL;
1080                 }
1081                 min_height = 6;
1082         } else {
1083                 min_height = 3;
1084         }
1085
1086         width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1087
1088         if (src_w < min_width || src_h < min_height ||
1089             src_w > 2048 || src_h > 2048) {
1090                 DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
1091                               src_w, src_h, min_width, min_height, 2048, 2048);
1092                 return -EINVAL;
1093         }
1094
1095         if (width_bytes > 4096) {
1096                 DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n",
1097                               width_bytes, 4096);
1098                 return -EINVAL;
1099         }
1100
1101         if (width_bytes > 4096 || fb->pitches[0] > 4096) {
1102                 DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
1103                               fb->pitches[0], 4096);
1104                 return -EINVAL;
1105         }
1106
1107         return 0;
1108 }
1109
1110 static int
1111 g4x_sprite_check(struct intel_crtc_state *crtc_state,
1112                  struct intel_plane_state *plane_state)
1113 {
1114         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1115         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1116         int max_scale, min_scale;
1117         int ret;
1118
1119         if (INTEL_GEN(dev_priv) < 7) {
1120                 min_scale = 1;
1121                 max_scale = 16 << 16;
1122         } else if (IS_IVYBRIDGE(dev_priv)) {
1123                 min_scale = 1;
1124                 max_scale = 2 << 16;
1125         } else {
1126                 min_scale = DRM_PLANE_HELPER_NO_SCALING;
1127                 max_scale = DRM_PLANE_HELPER_NO_SCALING;
1128         }
1129
1130         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1131                                                   &crtc_state->base,
1132                                                   min_scale, max_scale,
1133                                                   true, true);
1134         if (ret)
1135                 return ret;
1136
1137         if (!plane_state->base.visible)
1138                 return 0;
1139
1140         ret = intel_plane_check_src_coordinates(plane_state);
1141         if (ret)
1142                 return ret;
1143
1144         ret = g4x_sprite_check_scaling(crtc_state, plane_state);
1145         if (ret)
1146                 return ret;
1147
1148         ret = i9xx_check_plane_surface(plane_state);
1149         if (ret)
1150                 return ret;
1151
1152         if (INTEL_GEN(dev_priv) >= 7)
1153                 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
1154         else
1155                 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
1156
1157         return 0;
1158 }
1159
1160 int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
1161 {
1162         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1163         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1164         unsigned int rotation = plane_state->base.rotation;
1165
1166         /* CHV ignores the mirror bit when the rotate bit is set :( */
1167         if (IS_CHERRYVIEW(dev_priv) &&
1168             rotation & DRM_MODE_ROTATE_180 &&
1169             rotation & DRM_MODE_REFLECT_X) {
1170                 DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n");
1171                 return -EINVAL;
1172         }
1173
1174         return 0;
1175 }
1176
1177 static int
1178 vlv_sprite_check(struct intel_crtc_state *crtc_state,
1179                  struct intel_plane_state *plane_state)
1180 {
1181         int ret;
1182
1183         ret = chv_plane_check_rotation(plane_state);
1184         if (ret)
1185                 return ret;
1186
1187         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1188                                                   &crtc_state->base,
1189                                                   DRM_PLANE_HELPER_NO_SCALING,
1190                                                   DRM_PLANE_HELPER_NO_SCALING,
1191                                                   true, true);
1192         if (ret)
1193                 return ret;
1194
1195         if (!plane_state->base.visible)
1196                 return 0;
1197
1198         ret = intel_plane_check_src_coordinates(plane_state);
1199         if (ret)
1200                 return ret;
1201
1202         ret = i9xx_check_plane_surface(plane_state);
1203         if (ret)
1204                 return ret;
1205
1206         plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
1207
1208         return 0;
1209 }
1210
1211 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
1212                               const struct intel_plane_state *plane_state)
1213 {
1214         const struct drm_framebuffer *fb = plane_state->base.fb;
1215         unsigned int rotation = plane_state->base.rotation;
1216         struct drm_format_name_buf format_name;
1217
1218         if (!fb)
1219                 return 0;
1220
1221         if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
1222             is_ccs_modifier(fb->modifier)) {
1223                 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation (%x)\n",
1224                               rotation);
1225                 return -EINVAL;
1226         }
1227
1228         if (rotation & DRM_MODE_REFLECT_X &&
1229             fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1230                 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
1231                 return -EINVAL;
1232         }
1233
1234         if (drm_rotation_90_or_270(rotation)) {
1235                 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
1236                     fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
1237                         DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
1238                         return -EINVAL;
1239                 }
1240
1241                 /*
1242                  * 90/270 is not allowed with RGB64 16:16:16:16,
1243                  * RGB 16-bit 5:6:5, and Indexed 8-bit.
1244                  * TBD: Add RGB64 case once its added in supported format list.
1245                  */
1246                 switch (fb->format->format) {
1247                 case DRM_FORMAT_C8:
1248                 case DRM_FORMAT_RGB565:
1249                         DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
1250                                       drm_get_format_name(fb->format->format,
1251                                                           &format_name));
1252                         return -EINVAL;
1253                 default:
1254                         break;
1255                 }
1256         }
1257
1258         /* Y-tiling is not supported in IF-ID Interlace mode */
1259         if (crtc_state->base.enable &&
1260             crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
1261             (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
1262              fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
1263              fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
1264              fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
1265                 DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
1266                 return -EINVAL;
1267         }
1268
1269         return 0;
1270 }
1271
1272 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
1273                                            const struct intel_plane_state *plane_state)
1274 {
1275         struct drm_i915_private *dev_priv =
1276                 to_i915(plane_state->base.plane->dev);
1277         int crtc_x = plane_state->base.dst.x1;
1278         int crtc_w = drm_rect_width(&plane_state->base.dst);
1279         int pipe_src_w = crtc_state->pipe_src_w;
1280
1281         /*
1282          * Display WA #1175: cnl,glk
1283          * Planes other than the cursor may cause FIFO underflow and display
1284          * corruption if starting less than 4 pixels from the right edge of
1285          * the screen.
1286          * Besides the above WA fix the similar problem, where planes other
1287          * than the cursor ending less than 4 pixels from the left edge of the
1288          * screen may cause FIFO underflow and display corruption.
1289          */
1290         if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
1291             (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
1292                 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
1293                               crtc_x + crtc_w < 4 ? "end" : "start",
1294                               crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
1295                               4, pipe_src_w - 4);
1296                 return -ERANGE;
1297         }
1298
1299         return 0;
1300 }
1301
1302 int skl_plane_check(struct intel_crtc_state *crtc_state,
1303                     struct intel_plane_state *plane_state)
1304 {
1305         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1306         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1307         int max_scale, min_scale;
1308         int ret;
1309
1310         ret = skl_plane_check_fb(crtc_state, plane_state);
1311         if (ret)
1312                 return ret;
1313
1314         /* use scaler when colorkey is not required */
1315         if (!plane_state->ckey.flags) {
1316                 const struct drm_framebuffer *fb = plane_state->base.fb;
1317
1318                 min_scale = 1;
1319                 max_scale = skl_max_scale(crtc_state,
1320                                           fb ? fb->format->format : 0);
1321         } else {
1322                 min_scale = DRM_PLANE_HELPER_NO_SCALING;
1323                 max_scale = DRM_PLANE_HELPER_NO_SCALING;
1324         }
1325
1326         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1327                                                   &crtc_state->base,
1328                                                   min_scale, max_scale,
1329                                                   true, true);
1330         if (ret)
1331                 return ret;
1332
1333         if (!plane_state->base.visible)
1334                 return 0;
1335
1336         ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
1337         if (ret)
1338                 return ret;
1339
1340         ret = intel_plane_check_src_coordinates(plane_state);
1341         if (ret)
1342                 return ret;
1343
1344         ret = skl_check_plane_surface(plane_state);
1345         if (ret)
1346                 return ret;
1347
1348         plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
1349
1350         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1351                 plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
1352                                                              plane_state);
1353
1354         return 0;
1355 }
1356
1357 static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
1358 {
1359         return INTEL_GEN(dev_priv) >= 9;
1360 }
1361
1362 static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
1363                                  const struct drm_intel_sprite_colorkey *set)
1364 {
1365         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1366         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1367         struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1368
1369         *key = *set;
1370
1371         /*
1372          * We want src key enabled on the
1373          * sprite and not on the primary.
1374          */
1375         if (plane->id == PLANE_PRIMARY &&
1376             set->flags & I915_SET_COLORKEY_SOURCE)
1377                 key->flags = 0;
1378
1379         /*
1380          * On SKL+ we want dst key enabled on
1381          * the primary and not on the sprite.
1382          */
1383         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
1384             set->flags & I915_SET_COLORKEY_DESTINATION)
1385                 key->flags = 0;
1386 }
1387
1388 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
1389                                     struct drm_file *file_priv)
1390 {
1391         struct drm_i915_private *dev_priv = to_i915(dev);
1392         struct drm_intel_sprite_colorkey *set = data;
1393         struct drm_plane *plane;
1394         struct drm_plane_state *plane_state;
1395         struct drm_atomic_state *state;
1396         struct drm_modeset_acquire_ctx ctx;
1397         int ret = 0;
1398
1399         /* ignore the pointless "none" flag */
1400         set->flags &= ~I915_SET_COLORKEY_NONE;
1401
1402         if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1403                 return -EINVAL;
1404
1405         /* Make sure we don't try to enable both src & dest simultaneously */
1406         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1407                 return -EINVAL;
1408
1409         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1410             set->flags & I915_SET_COLORKEY_DESTINATION)
1411                 return -EINVAL;
1412
1413         plane = drm_plane_find(dev, file_priv, set->plane_id);
1414         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1415                 return -ENOENT;
1416
1417         /*
1418          * SKL+ only plane 2 can do destination keying against plane 1.
1419          * Also multiple planes can't do destination keying on the same
1420          * pipe simultaneously.
1421          */
1422         if (INTEL_GEN(dev_priv) >= 9 &&
1423             to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
1424             set->flags & I915_SET_COLORKEY_DESTINATION)
1425                 return -EINVAL;
1426
1427         drm_modeset_acquire_init(&ctx, 0);
1428
1429         state = drm_atomic_state_alloc(plane->dev);
1430         if (!state) {
1431                 ret = -ENOMEM;
1432                 goto out;
1433         }
1434         state->acquire_ctx = &ctx;
1435
1436         while (1) {
1437                 plane_state = drm_atomic_get_plane_state(state, plane);
1438                 ret = PTR_ERR_OR_ZERO(plane_state);
1439                 if (!ret)
1440                         intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1441
1442                 /*
1443                  * On some platforms we have to configure
1444                  * the dst colorkey on the primary plane.
1445                  */
1446                 if (!ret && has_dst_key_in_primary_plane(dev_priv)) {
1447                         struct intel_crtc *crtc =
1448                                 intel_get_crtc_for_pipe(dev_priv,
1449                                                         to_intel_plane(plane)->pipe);
1450
1451                         plane_state = drm_atomic_get_plane_state(state,
1452                                                                  crtc->base.primary);
1453                         ret = PTR_ERR_OR_ZERO(plane_state);
1454                         if (!ret)
1455                                 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1456                 }
1457
1458                 if (!ret)
1459                         ret = drm_atomic_commit(state);
1460
1461                 if (ret != -EDEADLK)
1462                         break;
1463
1464                 drm_atomic_state_clear(state);
1465                 drm_modeset_backoff(&ctx);
1466         }
1467
1468         drm_atomic_state_put(state);
1469 out:
1470         drm_modeset_drop_locks(&ctx);
1471         drm_modeset_acquire_fini(&ctx);
1472         return ret;
1473 }
1474
1475 static const uint32_t g4x_plane_formats[] = {
1476         DRM_FORMAT_XRGB8888,
1477         DRM_FORMAT_YUYV,
1478         DRM_FORMAT_YVYU,
1479         DRM_FORMAT_UYVY,
1480         DRM_FORMAT_VYUY,
1481 };
1482
1483 static const uint64_t i9xx_plane_format_modifiers[] = {
1484         I915_FORMAT_MOD_X_TILED,
1485         DRM_FORMAT_MOD_LINEAR,
1486         DRM_FORMAT_MOD_INVALID
1487 };
1488
1489 static const uint32_t snb_plane_formats[] = {
1490         DRM_FORMAT_XBGR8888,
1491         DRM_FORMAT_XRGB8888,
1492         DRM_FORMAT_YUYV,
1493         DRM_FORMAT_YVYU,
1494         DRM_FORMAT_UYVY,
1495         DRM_FORMAT_VYUY,
1496 };
1497
1498 static const uint32_t vlv_plane_formats[] = {
1499         DRM_FORMAT_RGB565,
1500         DRM_FORMAT_ABGR8888,
1501         DRM_FORMAT_ARGB8888,
1502         DRM_FORMAT_XBGR8888,
1503         DRM_FORMAT_XRGB8888,
1504         DRM_FORMAT_XBGR2101010,
1505         DRM_FORMAT_ABGR2101010,
1506         DRM_FORMAT_YUYV,
1507         DRM_FORMAT_YVYU,
1508         DRM_FORMAT_UYVY,
1509         DRM_FORMAT_VYUY,
1510 };
1511
1512 static uint32_t skl_plane_formats[] = {
1513         DRM_FORMAT_RGB565,
1514         DRM_FORMAT_ABGR8888,
1515         DRM_FORMAT_ARGB8888,
1516         DRM_FORMAT_XBGR8888,
1517         DRM_FORMAT_XRGB8888,
1518         DRM_FORMAT_YUYV,
1519         DRM_FORMAT_YVYU,
1520         DRM_FORMAT_UYVY,
1521         DRM_FORMAT_VYUY,
1522 };
1523
1524 static uint32_t skl_planar_formats[] = {
1525         DRM_FORMAT_RGB565,
1526         DRM_FORMAT_ABGR8888,
1527         DRM_FORMAT_ARGB8888,
1528         DRM_FORMAT_XBGR8888,
1529         DRM_FORMAT_XRGB8888,
1530         DRM_FORMAT_YUYV,
1531         DRM_FORMAT_YVYU,
1532         DRM_FORMAT_UYVY,
1533         DRM_FORMAT_VYUY,
1534         DRM_FORMAT_NV12,
1535 };
1536
1537 static const uint64_t skl_plane_format_modifiers_noccs[] = {
1538         I915_FORMAT_MOD_Yf_TILED,
1539         I915_FORMAT_MOD_Y_TILED,
1540         I915_FORMAT_MOD_X_TILED,
1541         DRM_FORMAT_MOD_LINEAR,
1542         DRM_FORMAT_MOD_INVALID
1543 };
1544
1545 static const uint64_t skl_plane_format_modifiers_ccs[] = {
1546         I915_FORMAT_MOD_Yf_TILED_CCS,
1547         I915_FORMAT_MOD_Y_TILED_CCS,
1548         I915_FORMAT_MOD_Yf_TILED,
1549         I915_FORMAT_MOD_Y_TILED,
1550         I915_FORMAT_MOD_X_TILED,
1551         DRM_FORMAT_MOD_LINEAR,
1552         DRM_FORMAT_MOD_INVALID
1553 };
1554
1555 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
1556                                             u32 format, u64 modifier)
1557 {
1558         switch (modifier) {
1559         case DRM_FORMAT_MOD_LINEAR:
1560         case I915_FORMAT_MOD_X_TILED:
1561                 break;
1562         default:
1563                 return false;
1564         }
1565
1566         switch (format) {
1567         case DRM_FORMAT_XRGB8888:
1568         case DRM_FORMAT_YUYV:
1569         case DRM_FORMAT_YVYU:
1570         case DRM_FORMAT_UYVY:
1571         case DRM_FORMAT_VYUY:
1572                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1573                     modifier == I915_FORMAT_MOD_X_TILED)
1574                         return true;
1575                 /* fall through */
1576         default:
1577                 return false;
1578         }
1579 }
1580
1581 static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
1582                                             u32 format, u64 modifier)
1583 {
1584         switch (modifier) {
1585         case DRM_FORMAT_MOD_LINEAR:
1586         case I915_FORMAT_MOD_X_TILED:
1587                 break;
1588         default:
1589                 return false;
1590         }
1591
1592         switch (format) {
1593         case DRM_FORMAT_XRGB8888:
1594         case DRM_FORMAT_XBGR8888:
1595         case DRM_FORMAT_YUYV:
1596         case DRM_FORMAT_YVYU:
1597         case DRM_FORMAT_UYVY:
1598         case DRM_FORMAT_VYUY:
1599                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1600                     modifier == I915_FORMAT_MOD_X_TILED)
1601                         return true;
1602                 /* fall through */
1603         default:
1604                 return false;
1605         }
1606 }
1607
1608 static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
1609                                             u32 format, u64 modifier)
1610 {
1611         switch (modifier) {
1612         case DRM_FORMAT_MOD_LINEAR:
1613         case I915_FORMAT_MOD_X_TILED:
1614                 break;
1615         default:
1616                 return false;
1617         }
1618
1619         switch (format) {
1620         case DRM_FORMAT_RGB565:
1621         case DRM_FORMAT_ABGR8888:
1622         case DRM_FORMAT_ARGB8888:
1623         case DRM_FORMAT_XBGR8888:
1624         case DRM_FORMAT_XRGB8888:
1625         case DRM_FORMAT_XBGR2101010:
1626         case DRM_FORMAT_ABGR2101010:
1627         case DRM_FORMAT_YUYV:
1628         case DRM_FORMAT_YVYU:
1629         case DRM_FORMAT_UYVY:
1630         case DRM_FORMAT_VYUY:
1631                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1632                     modifier == I915_FORMAT_MOD_X_TILED)
1633                         return true;
1634                 /* fall through */
1635         default:
1636                 return false;
1637         }
1638 }
1639
1640 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
1641                                            u32 format, u64 modifier)
1642 {
1643         struct intel_plane *plane = to_intel_plane(_plane);
1644
1645         switch (modifier) {
1646         case DRM_FORMAT_MOD_LINEAR:
1647         case I915_FORMAT_MOD_X_TILED:
1648         case I915_FORMAT_MOD_Y_TILED:
1649         case I915_FORMAT_MOD_Yf_TILED:
1650                 break;
1651         case I915_FORMAT_MOD_Y_TILED_CCS:
1652         case I915_FORMAT_MOD_Yf_TILED_CCS:
1653                 if (!plane->has_ccs)
1654                         return false;
1655                 break;
1656         default:
1657                 return false;
1658         }
1659
1660         switch (format) {
1661         case DRM_FORMAT_XRGB8888:
1662         case DRM_FORMAT_XBGR8888:
1663         case DRM_FORMAT_ARGB8888:
1664         case DRM_FORMAT_ABGR8888:
1665                 if (is_ccs_modifier(modifier))
1666                         return true;
1667                 /* fall through */
1668         case DRM_FORMAT_RGB565:
1669         case DRM_FORMAT_XRGB2101010:
1670         case DRM_FORMAT_XBGR2101010:
1671         case DRM_FORMAT_YUYV:
1672         case DRM_FORMAT_YVYU:
1673         case DRM_FORMAT_UYVY:
1674         case DRM_FORMAT_VYUY:
1675         case DRM_FORMAT_NV12:
1676                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1677                         return true;
1678                 /* fall through */
1679         case DRM_FORMAT_C8:
1680                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1681                     modifier == I915_FORMAT_MOD_X_TILED ||
1682                     modifier == I915_FORMAT_MOD_Y_TILED)
1683                         return true;
1684                 /* fall through */
1685         default:
1686                 return false;
1687         }
1688 }
1689
1690 static const struct drm_plane_funcs g4x_sprite_funcs = {
1691         .update_plane = drm_atomic_helper_update_plane,
1692         .disable_plane = drm_atomic_helper_disable_plane,
1693         .destroy = intel_plane_destroy,
1694         .atomic_get_property = intel_plane_atomic_get_property,
1695         .atomic_set_property = intel_plane_atomic_set_property,
1696         .atomic_duplicate_state = intel_plane_duplicate_state,
1697         .atomic_destroy_state = intel_plane_destroy_state,
1698         .format_mod_supported = g4x_sprite_format_mod_supported,
1699 };
1700
1701 static const struct drm_plane_funcs snb_sprite_funcs = {
1702         .update_plane = drm_atomic_helper_update_plane,
1703         .disable_plane = drm_atomic_helper_disable_plane,
1704         .destroy = intel_plane_destroy,
1705         .atomic_get_property = intel_plane_atomic_get_property,
1706         .atomic_set_property = intel_plane_atomic_set_property,
1707         .atomic_duplicate_state = intel_plane_duplicate_state,
1708         .atomic_destroy_state = intel_plane_destroy_state,
1709         .format_mod_supported = snb_sprite_format_mod_supported,
1710 };
1711
1712 static const struct drm_plane_funcs vlv_sprite_funcs = {
1713         .update_plane = drm_atomic_helper_update_plane,
1714         .disable_plane = drm_atomic_helper_disable_plane,
1715         .destroy = intel_plane_destroy,
1716         .atomic_get_property = intel_plane_atomic_get_property,
1717         .atomic_set_property = intel_plane_atomic_set_property,
1718         .atomic_duplicate_state = intel_plane_duplicate_state,
1719         .atomic_destroy_state = intel_plane_destroy_state,
1720         .format_mod_supported = vlv_sprite_format_mod_supported,
1721 };
1722
1723 static const struct drm_plane_funcs skl_plane_funcs = {
1724         .update_plane = drm_atomic_helper_update_plane,
1725         .disable_plane = drm_atomic_helper_disable_plane,
1726         .destroy = intel_plane_destroy,
1727         .atomic_get_property = intel_plane_atomic_get_property,
1728         .atomic_set_property = intel_plane_atomic_set_property,
1729         .atomic_duplicate_state = intel_plane_duplicate_state,
1730         .atomic_destroy_state = intel_plane_destroy_state,
1731         .format_mod_supported = skl_plane_format_mod_supported,
1732 };
1733
1734 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
1735                        enum pipe pipe, enum plane_id plane_id)
1736 {
1737         if (plane_id == PLANE_CURSOR)
1738                 return false;
1739
1740         if (INTEL_GEN(dev_priv) >= 10)
1741                 return true;
1742
1743         if (IS_GEMINILAKE(dev_priv))
1744                 return pipe != PIPE_C;
1745
1746         return pipe != PIPE_C &&
1747                 (plane_id == PLANE_PRIMARY ||
1748                  plane_id == PLANE_SPRITE0);
1749 }
1750
1751 struct intel_plane *
1752 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1753                           enum pipe pipe, int plane)
1754 {
1755         struct intel_plane *intel_plane = NULL;
1756         struct intel_plane_state *state = NULL;
1757         const struct drm_plane_funcs *plane_funcs;
1758         unsigned long possible_crtcs;
1759         const uint32_t *plane_formats;
1760         const uint64_t *modifiers;
1761         unsigned int supported_rotations;
1762         int num_plane_formats;
1763         int ret;
1764
1765         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1766         if (!intel_plane) {
1767                 ret = -ENOMEM;
1768                 goto fail;
1769         }
1770
1771         state = intel_create_plane_state(&intel_plane->base);
1772         if (!state) {
1773                 ret = -ENOMEM;
1774                 goto fail;
1775         }
1776         intel_plane->base.state = &state->base;
1777
1778         if (INTEL_GEN(dev_priv) >= 9) {
1779                 state->scaler_id = -1;
1780
1781                 intel_plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
1782                                                          PLANE_SPRITE0 + plane);
1783
1784                 intel_plane->max_stride = skl_plane_max_stride;
1785                 intel_plane->update_plane = skl_update_plane;
1786                 intel_plane->disable_plane = skl_disable_plane;
1787                 intel_plane->get_hw_state = skl_plane_get_hw_state;
1788                 intel_plane->check_plane = skl_plane_check;
1789
1790                 if (skl_plane_has_planar(dev_priv, pipe,
1791                                          PLANE_SPRITE0 + plane)) {
1792                         plane_formats = skl_planar_formats;
1793                         num_plane_formats = ARRAY_SIZE(skl_planar_formats);
1794                 } else {
1795                         plane_formats = skl_plane_formats;
1796                         num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1797                 }
1798
1799                 if (intel_plane->has_ccs)
1800                         modifiers = skl_plane_format_modifiers_ccs;
1801                 else
1802                         modifiers = skl_plane_format_modifiers_noccs;
1803
1804                 plane_funcs = &skl_plane_funcs;
1805         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1806                 intel_plane->max_stride = i9xx_plane_max_stride;
1807                 intel_plane->update_plane = vlv_update_plane;
1808                 intel_plane->disable_plane = vlv_disable_plane;
1809                 intel_plane->get_hw_state = vlv_plane_get_hw_state;
1810                 intel_plane->check_plane = vlv_sprite_check;
1811
1812                 plane_formats = vlv_plane_formats;
1813                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1814                 modifiers = i9xx_plane_format_modifiers;
1815
1816                 plane_funcs = &vlv_sprite_funcs;
1817         } else if (INTEL_GEN(dev_priv) >= 7) {
1818                 intel_plane->max_stride = g4x_sprite_max_stride;
1819                 intel_plane->update_plane = ivb_update_plane;
1820                 intel_plane->disable_plane = ivb_disable_plane;
1821                 intel_plane->get_hw_state = ivb_plane_get_hw_state;
1822                 intel_plane->check_plane = g4x_sprite_check;
1823
1824                 plane_formats = snb_plane_formats;
1825                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1826                 modifiers = i9xx_plane_format_modifiers;
1827
1828                 plane_funcs = &snb_sprite_funcs;
1829         } else {
1830                 intel_plane->max_stride = g4x_sprite_max_stride;
1831                 intel_plane->update_plane = g4x_update_plane;
1832                 intel_plane->disable_plane = g4x_disable_plane;
1833                 intel_plane->get_hw_state = g4x_plane_get_hw_state;
1834                 intel_plane->check_plane = g4x_sprite_check;
1835
1836                 modifiers = i9xx_plane_format_modifiers;
1837                 if (IS_GEN6(dev_priv)) {
1838                         plane_formats = snb_plane_formats;
1839                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1840
1841                         plane_funcs = &snb_sprite_funcs;
1842                 } else {
1843                         plane_formats = g4x_plane_formats;
1844                         num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1845
1846                         plane_funcs = &g4x_sprite_funcs;
1847                 }
1848         }
1849
1850         if (INTEL_GEN(dev_priv) >= 9) {
1851                 supported_rotations =
1852                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1853                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1854         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1855                 supported_rotations =
1856                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1857                         DRM_MODE_REFLECT_X;
1858         } else {
1859                 supported_rotations =
1860                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1861         }
1862
1863         intel_plane->pipe = pipe;
1864         intel_plane->i9xx_plane = plane;
1865         intel_plane->id = PLANE_SPRITE0 + plane;
1866         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);
1867
1868         possible_crtcs = (1 << pipe);
1869
1870         if (INTEL_GEN(dev_priv) >= 9)
1871                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1872                                                possible_crtcs, plane_funcs,
1873                                                plane_formats, num_plane_formats,
1874                                                modifiers,
1875                                                DRM_PLANE_TYPE_OVERLAY,
1876                                                "plane %d%c", plane + 2, pipe_name(pipe));
1877         else
1878                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1879                                                possible_crtcs, plane_funcs,
1880                                                plane_formats, num_plane_formats,
1881                                                modifiers,
1882                                                DRM_PLANE_TYPE_OVERLAY,
1883                                                "sprite %c", sprite_name(pipe, plane));
1884         if (ret)
1885                 goto fail;
1886
1887         drm_plane_create_rotation_property(&intel_plane->base,
1888                                            DRM_MODE_ROTATE_0,
1889                                            supported_rotations);
1890
1891         drm_plane_create_color_properties(&intel_plane->base,
1892                                           BIT(DRM_COLOR_YCBCR_BT601) |
1893                                           BIT(DRM_COLOR_YCBCR_BT709),
1894                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1895                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1896                                           DRM_COLOR_YCBCR_BT709,
1897                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
1898
1899         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1900
1901         return intel_plane;
1902
1903 fail:
1904         kfree(state);
1905         kfree(intel_plane);
1906
1907         return ERR_PTR(ret);
1908 }