drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_fourcc.h>
  36 #include <drm/drm_rect.h>
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include "intel_drv.h"
  40 #include "intel_frontbuffer.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 bool intel_format_is_yuv(u32 format)
  45 {
  46         switch (format) {
  47         case DRM_FORMAT_YUYV:
  48         case DRM_FORMAT_UYVY:
  49         case DRM_FORMAT_VYUY:
  50         case DRM_FORMAT_YVYU:
  51         case DRM_FORMAT_NV12:
  52                 return true;
  53         default:
  54                 return false;
  55         }
  56 }
  57
  58 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  59                              int usecs)
  60 {
  61         /* paranoia */
  62         if (!adjusted_mode->crtc_htotal)
  63                 return 1;
  64
  65         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  66                             1000 * adjusted_mode->crtc_htotal);
  67 }
  68
  69 /* FIXME: We should instead only take spinlocks once for the entire update
  70  * instead of once per mmio. */
  71 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
  72 #define VBLANK_EVASION_TIME_US 250
  73 #else
  74 #define VBLANK_EVASION_TIME_US 100
  75 #endif
  76
  77 /**
  78  * intel_pipe_update_start() - start update of a set of display registers
  79  * @new_crtc_state: the new crtc state
  80  *
  81  * Mark the start of an update to pipe registers that should be updated
  82  * atomically regarding vblank. If the next vblank will happens within
  83  * the next 100 us, this function waits until the vblank passes.
  84  *
  85  * After a successful call to this function, interrupts will be disabled
  86  * until a subsequent call to intel_pipe_update_end(). That is done to
  87  * avoid random delays.
  88  */
  89 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
  90 {
  91         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
  92         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  93         const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
  94         long timeout = msecs_to_jiffies_timeout(1);
  95         int scanline, min, max, vblank_start;
  96         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  97         bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
  98                 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
  99         DEFINE_WAIT(wait);
 100
 101         vblank_start = adjusted_mode->crtc_vblank_start;
 102         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 103                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
 104
 105         /* FIXME needs to be calibrated sensibly */
 106         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
 107                                                       VBLANK_EVASION_TIME_US);
 108         max = vblank_start - 1;
 109
 110         local_irq_disable();
 111
 112         if (min <= 0 || max <= 0)
 113                 return;
 114
 115         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 116                 return;
 117
 118         crtc->debug.min_vbl = min;
 119         crtc->debug.max_vbl = max;
 120         trace_i915_pipe_update_start(crtc);
 121
 122         for (;;) {
 123                 /*
 124                  * prepare_to_wait() has a memory barrier, which guarantees
 125                  * other CPUs can see the task state update by the time we
 126                  * read the scanline.
 127                  */
 128                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 129
 130                 scanline = intel_get_crtc_scanline(crtc);
 131                 if (scanline < min || scanline > max)
 132                         break;
 133
 134                 if (timeout <= 0) {
 135                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 136                                   pipe_name(crtc->pipe));
 137                         break;
 138                 }
 139
 140                 local_irq_enable();
 141
 142                 timeout = schedule_timeout(timeout);
 143
 144                 local_irq_disable();
 145         }
 146
 147         finish_wait(wq, &wait);
 148
 149         drm_crtc_vblank_put(&crtc->base);
 150
 151         /*
 152          * On VLV/CHV DSI the scanline counter would appear to
 153          * increment approx. 1/3 of a scanline before start of vblank.
 154          * The registers still get latched at start of vblank however.
 155          * This means we must not write any registers on the first
 156          * line of vblank (since not the whole line is actually in
 157          * vblank). And unfortunately we can't use the interrupt to
 158          * wait here since it will fire too soon. We could use the
 159          * frame start interrupt instead since it will fire after the
 160          * critical scanline, but that would require more changes
 161          * in the interrupt code. So for now we'll just do the nasty
 162          * thing and poll for the bad scanline to pass us by.
 163          *
 164          * FIXME figure out if BXT+ DSI suffers from this as well
 165          */
 166         while (need_vlv_dsi_wa && scanline == vblank_start)
 167                 scanline = intel_get_crtc_scanline(crtc);
 168
 169         crtc->debug.scanline_start = scanline;
 170         crtc->debug.start_vbl_time = ktime_get();
 171         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 172
 173         trace_i915_pipe_update_vblank_evaded(crtc);
 174 }
 175
 176 /**
 177  * intel_pipe_update_end() - end update of a set of display registers
 178  * @new_crtc_state: the new crtc state
 179  *
 180  * Mark the end of an update started with intel_pipe_update_start(). This
 181  * re-enables interrupts and verifies the update was actually completed
 182  * before a vblank.
 183  */
 184 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 185 {
 186         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
 187         enum pipe pipe = crtc->pipe;
 188         int scanline_end = intel_get_crtc_scanline(crtc);
 189         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 190         ktime_t end_vbl_time = ktime_get();
 191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 192
 193         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 194
 195         /* We're still in the vblank-evade critical section, this can't race.
 196          * Would be slightly nice to just grab the vblank count and arm the
 197          * event outside of the critical section - the spinlock might spin for a
 198          * while ... */
 199         if (new_crtc_state->base.event) {
 200                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 201
 202                 spin_lock(&crtc->base.dev->event_lock);
 203                 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
 204                 spin_unlock(&crtc->base.dev->event_lock);
 205
 206                 new_crtc_state->base.event = NULL;
 207         }
 208
 209         local_irq_enable();
 210
 211         if (intel_vgpu_active(dev_priv))
 212                 return;
 213
 214         if (crtc->debug.start_vbl_count &&
 215             crtc->debug.start_vbl_count != end_vbl_count) {
 216                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 217                           pipe_name(pipe), crtc->debug.start_vbl_count,
 218                           end_vbl_count,
 219                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 220                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 221                           crtc->debug.scanline_start, scanline_end);
 222         }
 223 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
 224         else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 225                  VBLANK_EVASION_TIME_US)
 226                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 227                          pipe_name(pipe),
 228                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 229                          VBLANK_EVASION_TIME_US);
 230 #endif
 231 }
 232
 233 void
 234 skl_update_plane(struct intel_plane *plane,
 235                  const struct intel_crtc_state *crtc_state,
 236                  const struct intel_plane_state *plane_state)
 237 {
 238         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 239         const struct drm_framebuffer *fb = plane_state->base.fb;
 240         enum plane_id plane_id = plane->id;
 241         enum pipe pipe = plane->pipe;
 242         u32 plane_ctl = plane_state->ctl;
 243         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 244         u32 surf_addr = plane_state->main.offset;
 245         unsigned int rotation = plane_state->base.rotation;
 246         u32 stride = skl_plane_stride(fb, 0, rotation);
 247         u32 aux_stride = skl_plane_stride(fb, 1, rotation);
 248         int crtc_x = plane_state->base.dst.x1;
 249         int crtc_y = plane_state->base.dst.y1;
 250         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 251         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 252         uint32_t x = plane_state->main.x;
 253         uint32_t y = plane_state->main.y;
 254         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 255         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 256         unsigned long irqflags;
 257
 258         /* Sizes are 0 based */
 259         src_w--;
 260         src_h--;
 261         crtc_w--;
 262         crtc_h--;
 263
 264         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 265
 266         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 267                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 268                               plane_state->color_ctl);
 269
 270         if (key->flags) {
 271                 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 272                 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 273                 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 274         }
 275
 276         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 277         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 278         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 279         I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 280                       (plane_state->aux.offset - surf_addr) | aux_stride);
 281         I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
 282                       (plane_state->aux.y << 16) | plane_state->aux.x);
 283
 284         /* program plane scaler */
 285         if (plane_state->scaler_id >= 0) {
 286                 int scaler_id = plane_state->scaler_id;
 287                 const struct intel_scaler *scaler;
 288
 289                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 290
 291                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 292                               PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 293                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 294                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 295                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
 296                               ((crtc_w + 1) << 16)|(crtc_h + 1));
 297
 298                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
 299         } else {
 300                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 301         }
 302
 303         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 304         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 305                       intel_plane_ggtt_offset(plane_state) + surf_addr);
 306         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 307
 308         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 309 }
 310
 311 void
 312 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 313 {
 314         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 315         enum plane_id plane_id = plane->id;
 316         enum pipe pipe = plane->pipe;
 317         unsigned long irqflags;
 318
 319         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 320
 321         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 322
 323         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 324         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 325
 326         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 327 }
 328
 329 bool
 330 skl_plane_get_hw_state(struct intel_plane *plane)
 331 {
 332         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 333         enum intel_display_power_domain power_domain;
 334         enum plane_id plane_id = plane->id;
 335         enum pipe pipe = plane->pipe;
 336         bool ret;
 337
 338         power_domain = POWER_DOMAIN_PIPE(pipe);
 339         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 340                 return false;
 341
 342         ret = I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
 343
 344         intel_display_power_put(dev_priv, power_domain);
 345
 346         return ret;
 347 }
 348
 349 static void
 350 chv_update_csc(const struct intel_plane_state *plane_state)
 351 {
 352         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 353         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 354         const struct drm_framebuffer *fb = plane_state->base.fb;
 355         enum plane_id plane_id = plane->id;
 356         /*
 357          * |r|   | c0 c1 c2 |   |cr|
 358          * |g| = | c3 c4 c5 | x |y |
 359          * |b|   | c6 c7 c8 |   |cb|
 360          *
 361          * Coefficients are s3.12.
 362          *
 363          * Cb and Cr apparently come in as signed already, and
 364          * we always get full range data in on account of CLRC0/1.
 365          */
 366         static const s16 csc_matrix[][9] = {
 367                 /* BT.601 full range YCbCr -> full range RGB */
 368                 [DRM_COLOR_YCBCR_BT601] = {
 369                          5743, 4096,     0,
 370                         -2925, 4096, -1410,
 371                             0, 4096,  7258,
 372                 },
 373                 /* BT.709 full range YCbCr -> full range RGB */
 374                 [DRM_COLOR_YCBCR_BT709] = {
 375                          6450, 4096,     0,
 376                         -1917, 4096,  -767,
 377                             0, 4096,  7601,
 378                 },
 379         };
 380         const s16 *csc = csc_matrix[plane_state->base.color_encoding];
 381
 382         /* Seems RGB data bypasses the CSC always */
 383         if (!intel_format_is_yuv(fb->format->format))
 384                 return;
 385
 386         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 387         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 388         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 389
 390         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
 391         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
 392         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
 393         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
 394         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
 395
 396         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
 397         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 398         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 399
 400         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 401         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 402         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 403 }
 404
 405 #define SIN_0 0
 406 #define COS_0 1
 407
 408 static void
 409 vlv_update_clrc(const struct intel_plane_state *plane_state)
 410 {
 411         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 412         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 413         const struct drm_framebuffer *fb = plane_state->base.fb;
 414         enum pipe pipe = plane->pipe;
 415         enum plane_id plane_id = plane->id;
 416         int contrast, brightness, sh_scale, sh_sin, sh_cos;
 417
 418         if (intel_format_is_yuv(fb->format->format) &&
 419             plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
 420                 /*
 421                  * Expand limited range to full range:
 422                  * Contrast is applied first and is used to expand Y range.
 423                  * Brightness is applied second and is used to remove the
 424                  * offset from Y. Saturation/hue is used to expand CbCr range.
 425                  */
 426                 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
 427                 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
 428                 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
 429                 sh_sin = SIN_0 * sh_scale;
 430                 sh_cos = COS_0 * sh_scale;
 431         } else {
 432                 /* Pass-through everything. */
 433                 contrast = 1 << 6;
 434                 brightness = 0;
 435                 sh_scale = 1 << 7;
 436                 sh_sin = SIN_0 * sh_scale;
 437                 sh_cos = COS_0 * sh_scale;
 438         }
 439
 440         /* FIXME these register are single buffered :( */
 441         I915_WRITE_FW(SPCLRC0(pipe, plane_id),
 442                       SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
 443         I915_WRITE_FW(SPCLRC1(pipe, plane_id),
 444                       SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
 445 }
 446
 447 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 448                           const struct intel_plane_state *plane_state)
 449 {
 450         const struct drm_framebuffer *fb = plane_state->base.fb;
 451         unsigned int rotation = plane_state->base.rotation;
 452         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 453         u32 sprctl;
 454
 455         sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
 456
 457         switch (fb->format->format) {
 458         case DRM_FORMAT_YUYV:
 459                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 460                 break;
 461         case DRM_FORMAT_YVYU:
 462                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 463                 break;
 464         case DRM_FORMAT_UYVY:
 465                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 466                 break;
 467         case DRM_FORMAT_VYUY:
 468                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 469                 break;
 470         case DRM_FORMAT_RGB565:
 471                 sprctl |= SP_FORMAT_BGR565;
 472                 break;
 473         case DRM_FORMAT_XRGB8888:
 474                 sprctl |= SP_FORMAT_BGRX8888;
 475                 break;
 476         case DRM_FORMAT_ARGB8888:
 477                 sprctl |= SP_FORMAT_BGRA8888;
 478                 break;
 479         case DRM_FORMAT_XBGR2101010:
 480                 sprctl |= SP_FORMAT_RGBX1010102;
 481                 break;
 482         case DRM_FORMAT_ABGR2101010:
 483                 sprctl |= SP_FORMAT_RGBA1010102;
 484                 break;
 485         case DRM_FORMAT_XBGR8888:
 486                 sprctl |= SP_FORMAT_RGBX8888;
 487                 break;
 488         case DRM_FORMAT_ABGR8888:
 489                 sprctl |= SP_FORMAT_RGBA8888;
 490                 break;
 491         default:
 492                 MISSING_CASE(fb->format->format);
 493                 return 0;
 494         }
 495
 496         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 497                 sprctl |= SP_YUV_FORMAT_BT709;
 498
 499         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 500                 sprctl |= SP_TILED;
 501
 502         if (rotation & DRM_MODE_ROTATE_180)
 503                 sprctl |= SP_ROTATE_180;
 504
 505         if (rotation & DRM_MODE_REFLECT_X)
 506                 sprctl |= SP_MIRROR;
 507
 508         if (key->flags & I915_SET_COLORKEY_SOURCE)
 509                 sprctl |= SP_SOURCE_KEY;
 510
 511         return sprctl;
 512 }
 513
 514 static void
 515 vlv_update_plane(struct intel_plane *plane,
 516                  const struct intel_crtc_state *crtc_state,
 517                  const struct intel_plane_state *plane_state)
 518 {
 519         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 520         const struct drm_framebuffer *fb = plane_state->base.fb;
 521         enum pipe pipe = plane->pipe;
 522         enum plane_id plane_id = plane->id;
 523         u32 sprctl = plane_state->ctl;
 524         u32 sprsurf_offset = plane_state->main.offset;
 525         u32 linear_offset;
 526         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 527         int crtc_x = plane_state->base.dst.x1;
 528         int crtc_y = plane_state->base.dst.y1;
 529         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 530         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 531         uint32_t x = plane_state->main.x;
 532         uint32_t y = plane_state->main.y;
 533         unsigned long irqflags;
 534
 535         /* Sizes are 0 based */
 536         crtc_w--;
 537         crtc_h--;
 538
 539         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 540
 541         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 542
 543         vlv_update_clrc(plane_state);
 544
 545         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 546                 chv_update_csc(plane_state);
 547
 548         if (key->flags) {
 549                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
 550                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 551                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
 552         }
 553         I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
 554         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 555
 556         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 557                 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 558         else
 559                 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
 560
 561         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
 562
 563         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 564         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
 565         I915_WRITE_FW(SPSURF(pipe, plane_id),
 566                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 567         POSTING_READ_FW(SPSURF(pipe, plane_id));
 568
 569         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 570 }
 571
 572 static void
 573 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 574 {
 575         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 576         enum pipe pipe = plane->pipe;
 577         enum plane_id plane_id = plane->id;
 578         unsigned long irqflags;
 579
 580         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 581
 582         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
 583
 584         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
 585         POSTING_READ_FW(SPSURF(pipe, plane_id));
 586
 587         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 588 }
 589
 590 static bool
 591 vlv_plane_get_hw_state(struct intel_plane *plane)
 592 {
 593         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 594         enum intel_display_power_domain power_domain;
 595         enum plane_id plane_id = plane->id;
 596         enum pipe pipe = plane->pipe;
 597         bool ret;
 598
 599         power_domain = POWER_DOMAIN_PIPE(pipe);
 600         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 601                 return false;
 602
 603         ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
 604
 605         intel_display_power_put(dev_priv, power_domain);
 606
 607         return ret;
 608 }
 609
 610 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 611                           const struct intel_plane_state *plane_state)
 612 {
 613         struct drm_i915_private *dev_priv =
 614                 to_i915(plane_state->base.plane->dev);
 615         const struct drm_framebuffer *fb = plane_state->base.fb;
 616         unsigned int rotation = plane_state->base.rotation;
 617         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 618         u32 sprctl;
 619
 620         sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
 621
 622         if (IS_IVYBRIDGE(dev_priv))
 623                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 624
 625         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 626                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 627
 628         switch (fb->format->format) {
 629         case DRM_FORMAT_XBGR8888:
 630                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 631                 break;
 632         case DRM_FORMAT_XRGB8888:
 633                 sprctl |= SPRITE_FORMAT_RGBX888;
 634                 break;
 635         case DRM_FORMAT_YUYV:
 636                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 637                 break;
 638         case DRM_FORMAT_YVYU:
 639                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 640                 break;
 641         case DRM_FORMAT_UYVY:
 642                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 643                 break;
 644         case DRM_FORMAT_VYUY:
 645                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 646                 break;
 647         default:
 648                 MISSING_CASE(fb->format->format);
 649                 return 0;
 650         }
 651
 652         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 653                 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
 654
 655         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 656                 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
 657
 658         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 659                 sprctl |= SPRITE_TILED;
 660
 661         if (rotation & DRM_MODE_ROTATE_180)
 662                 sprctl |= SPRITE_ROTATE_180;
 663
 664         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 665                 sprctl |= SPRITE_DEST_KEY;
 666         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 667                 sprctl |= SPRITE_SOURCE_KEY;
 668
 669         return sprctl;
 670 }
 671
 672 static void
 673 ivb_update_plane(struct intel_plane *plane,
 674                  const struct intel_crtc_state *crtc_state,
 675                  const struct intel_plane_state *plane_state)
 676 {
 677         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 678         const struct drm_framebuffer *fb = plane_state->base.fb;
 679         enum pipe pipe = plane->pipe;
 680         u32 sprctl = plane_state->ctl, sprscale = 0;
 681         u32 sprsurf_offset = plane_state->main.offset;
 682         u32 linear_offset;
 683         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 684         int crtc_x = plane_state->base.dst.x1;
 685         int crtc_y = plane_state->base.dst.y1;
 686         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 687         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 688         uint32_t x = plane_state->main.x;
 689         uint32_t y = plane_state->main.y;
 690         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 691         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 692         unsigned long irqflags;
 693
 694         /* Sizes are 0 based */
 695         src_w--;
 696         src_h--;
 697         crtc_w--;
 698         crtc_h--;
 699
 700         if (crtc_w != src_w || crtc_h != src_h)
 701                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 702
 703         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 704
 705         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 706
 707         if (key->flags) {
 708                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
 709                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
 710                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
 711         }
 712
 713         I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
 714         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 715
 716         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 717          * register */
 718         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 719                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
 720         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 721                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 722         else
 723                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
 724
 725         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 726         if (plane->can_scale)
 727                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
 728         I915_WRITE_FW(SPRCTL(pipe), sprctl);
 729         I915_WRITE_FW(SPRSURF(pipe),
 730                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 731         POSTING_READ_FW(SPRSURF(pipe));
 732
 733         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 734 }
 735
 736 static void
 737 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 738 {
 739         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 740         enum pipe pipe = plane->pipe;
 741         unsigned long irqflags;
 742
 743         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 744
 745         I915_WRITE_FW(SPRCTL(pipe), 0);
 746         /* Can't leave the scaler enabled... */
 747         if (plane->can_scale)
 748                 I915_WRITE_FW(SPRSCALE(pipe), 0);
 749
 750         I915_WRITE_FW(SPRSURF(pipe), 0);
 751         POSTING_READ_FW(SPRSURF(pipe));
 752
 753         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 754 }
 755
 756 static bool
 757 ivb_plane_get_hw_state(struct intel_plane *plane)
 758 {
 759         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 760         enum intel_display_power_domain power_domain;
 761         enum pipe pipe = plane->pipe;
 762         bool ret;
 763
 764         power_domain = POWER_DOMAIN_PIPE(pipe);
 765         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 766                 return false;
 767
 768         ret =  I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
 769
 770         intel_display_power_put(dev_priv, power_domain);
 771
 772         return ret;
 773 }
 774
 775 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 776                           const struct intel_plane_state *plane_state)
 777 {
 778         struct drm_i915_private *dev_priv =
 779                 to_i915(plane_state->base.plane->dev);
 780         const struct drm_framebuffer *fb = plane_state->base.fb;
 781         unsigned int rotation = plane_state->base.rotation;
 782         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 783         u32 dvscntr;
 784
 785         dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
 786
 787         if (IS_GEN6(dev_priv))
 788                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
 789
 790         switch (fb->format->format) {
 791         case DRM_FORMAT_XBGR8888:
 792                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 793                 break;
 794         case DRM_FORMAT_XRGB8888:
 795                 dvscntr |= DVS_FORMAT_RGBX888;
 796                 break;
 797         case DRM_FORMAT_YUYV:
 798                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 799                 break;
 800         case DRM_FORMAT_YVYU:
 801                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 802                 break;
 803         case DRM_FORMAT_UYVY:
 804                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 805                 break;
 806         case DRM_FORMAT_VYUY:
 807                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 808                 break;
 809         default:
 810                 MISSING_CASE(fb->format->format);
 811                 return 0;
 812         }
 813
 814         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 815                 dvscntr |= DVS_YUV_FORMAT_BT709;
 816
 817         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 818                 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
 819
 820         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 821                 dvscntr |= DVS_TILED;
 822
 823         if (rotation & DRM_MODE_ROTATE_180)
 824                 dvscntr |= DVS_ROTATE_180;
 825
 826         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 827                 dvscntr |= DVS_DEST_KEY;
 828         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 829                 dvscntr |= DVS_SOURCE_KEY;
 830
 831         return dvscntr;
 832 }
 833
 834 static void
 835 g4x_update_plane(struct intel_plane *plane,
 836                  const struct intel_crtc_state *crtc_state,
 837                  const struct intel_plane_state *plane_state)
 838 {
 839         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 840         const struct drm_framebuffer *fb = plane_state->base.fb;
 841         enum pipe pipe = plane->pipe;
 842         u32 dvscntr = plane_state->ctl, dvsscale = 0;
 843         u32 dvssurf_offset = plane_state->main.offset;
 844         u32 linear_offset;
 845         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 846         int crtc_x = plane_state->base.dst.x1;
 847         int crtc_y = plane_state->base.dst.y1;
 848         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 849         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 850         uint32_t x = plane_state->main.x;
 851         uint32_t y = plane_state->main.y;
 852         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 853         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 854         unsigned long irqflags;
 855
 856         /* Sizes are 0 based */
 857         src_w--;
 858         src_h--;
 859         crtc_w--;
 860         crtc_h--;
 861
 862         if (crtc_w != src_w || crtc_h != src_h)
 863                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 864
 865         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 866
 867         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 868
 869         if (key->flags) {
 870                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
 871                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
 872                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
 873         }
 874
 875         I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
 876         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 877
 878         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 879                 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
 880         else
 881                 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
 882
 883         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 884         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
 885         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
 886         I915_WRITE_FW(DVSSURF(pipe),
 887                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
 888         POSTING_READ_FW(DVSSURF(pipe));
 889
 890         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 891 }
 892
 893 static void
 894 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 895 {
 896         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 897         enum pipe pipe = plane->pipe;
 898         unsigned long irqflags;
 899
 900         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 901
 902         I915_WRITE_FW(DVSCNTR(pipe), 0);
 903         /* Disable the scaler */
 904         I915_WRITE_FW(DVSSCALE(pipe), 0);
 905
 906         I915_WRITE_FW(DVSSURF(pipe), 0);
 907         POSTING_READ_FW(DVSSURF(pipe));
 908
 909         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 910 }
 911
 912 static bool
 913 g4x_plane_get_hw_state(struct intel_plane *plane)
 914 {
 915         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 916         enum intel_display_power_domain power_domain;
 917         enum pipe pipe = plane->pipe;
 918         bool ret;
 919
 920         power_domain = POWER_DOMAIN_PIPE(pipe);
 921         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 922                 return false;
 923
 924         ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
 925
 926         intel_display_power_put(dev_priv, power_domain);
 927
 928         return ret;
 929 }
 930
 931 static int
 932 intel_check_sprite_plane(struct intel_plane *plane,
 933                          struct intel_crtc_state *crtc_state,
 934                          struct intel_plane_state *state)
 935 {
 936         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 937         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 938         struct drm_framebuffer *fb = state->base.fb;
 939         int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
 940         int max_scale, min_scale;
 941         bool can_scale;
 942         int ret;
 943         uint32_t pixel_format = 0;
 944
 945         if (!fb) {
 946                 state->base.visible = false;
 947                 return 0;
 948         }
 949
 950         /* Don't modify another pipe's plane */
 951         if (plane->pipe != crtc->pipe) {
 952                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 953                 return -EINVAL;
 954         }
 955
 956         /* FIXME check all gen limits */
 957         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > max_stride) {
 958                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 959                 return -EINVAL;
 960         }
 961
 962         /* setup can_scale, min_scale, max_scale */
 963         if (INTEL_GEN(dev_priv) >= 9) {
 964                 if (state->base.fb)
 965                         pixel_format = state->base.fb->format->format;
 966                 /* use scaler when colorkey is not required */
 967                 if (!state->ckey.flags) {
 968                         can_scale = 1;
 969                         min_scale = 1;
 970                         max_scale =
 971                                 skl_max_scale(crtc, crtc_state, pixel_format);
 972                 } else {
 973                         can_scale = 0;
 974                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 975                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 976                 }
 977         } else {
 978                 can_scale = plane->can_scale;
 979                 max_scale = plane->max_downscale << 16;
 980                 min_scale = plane->can_scale ? 1 : (1 << 16);
 981         }
 982
 983         ret = drm_atomic_helper_check_plane_state(&state->base,
 984                                                   &crtc_state->base,
 985                                                   min_scale, max_scale,
 986                                                   true, true);
 987         if (ret)
 988                 return ret;
 989
 990         if (state->base.visible) {
 991                 struct drm_rect *src = &state->base.src;
 992                 struct drm_rect *dst = &state->base.dst;
 993                 unsigned int crtc_w = drm_rect_width(dst);
 994                 unsigned int crtc_h = drm_rect_height(dst);
 995                 uint32_t src_x, src_y, src_w, src_h;
 996
 997                 /*
 998                  * Hardware doesn't handle subpixel coordinates.
 999                  * Adjust to (macro)pixel boundary, but be careful not to
1000                  * increase the source viewport size, because that could
1001                  * push the downscaling factor out of bounds.
1002                  */
1003                 src_x = src->x1 >> 16;
1004                 src_w = drm_rect_width(src) >> 16;
1005                 src_y = src->y1 >> 16;
1006                 src_h = drm_rect_height(src) >> 16;
1007
1008                 src->x1 = src_x << 16;
1009                 src->x2 = (src_x + src_w) << 16;
1010                 src->y1 = src_y << 16;
1011                 src->y2 = (src_y + src_h) << 16;
1012
1013                 if (intel_format_is_yuv(fb->format->format) &&
1014                     (src_x % 2 || src_w % 2)) {
1015                         DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
1016                                       src_x, src_w);
1017                         return -EINVAL;
1018                 }
1019
1020                 /* Check size restrictions when scaling */
1021                 if (src_w != crtc_w || src_h != crtc_h) {
1022                         unsigned int width_bytes;
1023                         int cpp = fb->format->cpp[0];
1024
1025                         WARN_ON(!can_scale);
1026
1027                         width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1028
1029                         /* FIXME interlacing min height is 6 */
1030                         if (INTEL_GEN(dev_priv) < 9 && (
1031                              src_w < 3 || src_h < 3 ||
1032                              src_w > 2048 || src_h > 2048 ||
1033                              crtc_w < 3 || crtc_h < 3 ||
1034                              width_bytes > 4096 || fb->pitches[0] > 4096)) {
1035                                 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
1036                                 return -EINVAL;
1037                         }
1038                 }
1039         }
1040
1041         if (INTEL_GEN(dev_priv) >= 9) {
1042                 ret = skl_check_plane_surface(crtc_state, state);
1043                 if (ret)
1044                         return ret;
1045
1046                 state->ctl = skl_plane_ctl(crtc_state, state);
1047         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1048                 ret = i9xx_check_plane_surface(state);
1049                 if (ret)
1050                         return ret;
1051
1052                 state->ctl = vlv_sprite_ctl(crtc_state, state);
1053         } else if (INTEL_GEN(dev_priv) >= 7) {
1054                 ret = i9xx_check_plane_surface(state);
1055                 if (ret)
1056                         return ret;
1057
1058                 state->ctl = ivb_sprite_ctl(crtc_state, state);
1059         } else {
1060                 ret = i9xx_check_plane_surface(state);
1061                 if (ret)
1062                         return ret;
1063
1064                 state->ctl = g4x_sprite_ctl(crtc_state, state);
1065         }
1066
1067         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1068                 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
1069
1070         return 0;
1071 }
1072
1073 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
1074                                     struct drm_file *file_priv)
1075 {
1076         struct drm_i915_private *dev_priv = to_i915(dev);
1077         struct drm_intel_sprite_colorkey *set = data;
1078         struct drm_plane *plane;
1079         struct drm_plane_state *plane_state;
1080         struct drm_atomic_state *state;
1081         struct drm_modeset_acquire_ctx ctx;
1082         int ret = 0;
1083
1084         /* ignore the pointless "none" flag */
1085         set->flags &= ~I915_SET_COLORKEY_NONE;
1086
1087         if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1088                 return -EINVAL;
1089
1090         /* Make sure we don't try to enable both src & dest simultaneously */
1091         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1092                 return -EINVAL;
1093
1094         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1095             set->flags & I915_SET_COLORKEY_DESTINATION)
1096                 return -EINVAL;
1097
1098         plane = drm_plane_find(dev, file_priv, set->plane_id);
1099         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1100                 return -ENOENT;
1101
1102         drm_modeset_acquire_init(&ctx, 0);
1103
1104         state = drm_atomic_state_alloc(plane->dev);
1105         if (!state) {
1106                 ret = -ENOMEM;
1107                 goto out;
1108         }
1109         state->acquire_ctx = &ctx;
1110
1111         while (1) {
1112                 plane_state = drm_atomic_get_plane_state(state, plane);
1113                 ret = PTR_ERR_OR_ZERO(plane_state);
1114                 if (!ret) {
1115                         to_intel_plane_state(plane_state)->ckey = *set;
1116                         ret = drm_atomic_commit(state);
1117                 }
1118
1119                 if (ret != -EDEADLK)
1120                         break;
1121
1122                 drm_atomic_state_clear(state);
1123                 drm_modeset_backoff(&ctx);
1124         }
1125
1126         drm_atomic_state_put(state);
1127 out:
1128         drm_modeset_drop_locks(&ctx);
1129         drm_modeset_acquire_fini(&ctx);
1130         return ret;
1131 }
1132
1133 static const uint32_t g4x_plane_formats[] = {
1134         DRM_FORMAT_XRGB8888,
1135         DRM_FORMAT_YUYV,
1136         DRM_FORMAT_YVYU,
1137         DRM_FORMAT_UYVY,
1138         DRM_FORMAT_VYUY,
1139 };
1140
1141 static const uint64_t i9xx_plane_format_modifiers[] = {
1142         I915_FORMAT_MOD_X_TILED,
1143         DRM_FORMAT_MOD_LINEAR,
1144         DRM_FORMAT_MOD_INVALID
1145 };
1146
1147 static const uint32_t snb_plane_formats[] = {
1148         DRM_FORMAT_XBGR8888,
1149         DRM_FORMAT_XRGB8888,
1150         DRM_FORMAT_YUYV,
1151         DRM_FORMAT_YVYU,
1152         DRM_FORMAT_UYVY,
1153         DRM_FORMAT_VYUY,
1154 };
1155
1156 static const uint32_t vlv_plane_formats[] = {
1157         DRM_FORMAT_RGB565,
1158         DRM_FORMAT_ABGR8888,
1159         DRM_FORMAT_ARGB8888,
1160         DRM_FORMAT_XBGR8888,
1161         DRM_FORMAT_XRGB8888,
1162         DRM_FORMAT_XBGR2101010,
1163         DRM_FORMAT_ABGR2101010,
1164         DRM_FORMAT_YUYV,
1165         DRM_FORMAT_YVYU,
1166         DRM_FORMAT_UYVY,
1167         DRM_FORMAT_VYUY,
1168 };
1169
1170 static uint32_t skl_plane_formats[] = {
1171         DRM_FORMAT_RGB565,
1172         DRM_FORMAT_ABGR8888,
1173         DRM_FORMAT_ARGB8888,
1174         DRM_FORMAT_XBGR8888,
1175         DRM_FORMAT_XRGB8888,
1176         DRM_FORMAT_YUYV,
1177         DRM_FORMAT_YVYU,
1178         DRM_FORMAT_UYVY,
1179         DRM_FORMAT_VYUY,
1180 };
1181
1182 static const uint64_t skl_plane_format_modifiers_noccs[] = {
1183         I915_FORMAT_MOD_Yf_TILED,
1184         I915_FORMAT_MOD_Y_TILED,
1185         I915_FORMAT_MOD_X_TILED,
1186         DRM_FORMAT_MOD_LINEAR,
1187         DRM_FORMAT_MOD_INVALID
1188 };
1189
1190 static const uint64_t skl_plane_format_modifiers_ccs[] = {
1191         I915_FORMAT_MOD_Yf_TILED_CCS,
1192         I915_FORMAT_MOD_Y_TILED_CCS,
1193         I915_FORMAT_MOD_Yf_TILED,
1194         I915_FORMAT_MOD_Y_TILED,
1195         I915_FORMAT_MOD_X_TILED,
1196         DRM_FORMAT_MOD_LINEAR,
1197         DRM_FORMAT_MOD_INVALID
1198 };
1199
1200 static bool g4x_mod_supported(uint32_t format, uint64_t modifier)
1201 {
1202         switch (format) {
1203         case DRM_FORMAT_XRGB8888:
1204         case DRM_FORMAT_YUYV:
1205         case DRM_FORMAT_YVYU:
1206         case DRM_FORMAT_UYVY:
1207         case DRM_FORMAT_VYUY:
1208                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1209                     modifier == I915_FORMAT_MOD_X_TILED)
1210                         return true;
1211                 /* fall through */
1212         default:
1213                 return false;
1214         }
1215 }
1216
1217 static bool snb_mod_supported(uint32_t format, uint64_t modifier)
1218 {
1219         switch (format) {
1220         case DRM_FORMAT_XRGB8888:
1221         case DRM_FORMAT_XBGR8888:
1222         case DRM_FORMAT_YUYV:
1223         case DRM_FORMAT_YVYU:
1224         case DRM_FORMAT_UYVY:
1225         case DRM_FORMAT_VYUY:
1226                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1227                     modifier == I915_FORMAT_MOD_X_TILED)
1228                         return true;
1229                 /* fall through */
1230         default:
1231                 return false;
1232         }
1233 }
1234
1235 static bool vlv_mod_supported(uint32_t format, uint64_t modifier)
1236 {
1237         switch (format) {
1238         case DRM_FORMAT_RGB565:
1239         case DRM_FORMAT_ABGR8888:
1240         case DRM_FORMAT_ARGB8888:
1241         case DRM_FORMAT_XBGR8888:
1242         case DRM_FORMAT_XRGB8888:
1243         case DRM_FORMAT_XBGR2101010:
1244         case DRM_FORMAT_ABGR2101010:
1245         case DRM_FORMAT_YUYV:
1246         case DRM_FORMAT_YVYU:
1247         case DRM_FORMAT_UYVY:
1248         case DRM_FORMAT_VYUY:
1249                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1250                     modifier == I915_FORMAT_MOD_X_TILED)
1251                         return true;
1252                 /* fall through */
1253         default:
1254                 return false;
1255         }
1256 }
1257
1258 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
1259 {
1260         switch (format) {
1261         case DRM_FORMAT_XRGB8888:
1262         case DRM_FORMAT_XBGR8888:
1263         case DRM_FORMAT_ARGB8888:
1264         case DRM_FORMAT_ABGR8888:
1265                 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
1266                     modifier == I915_FORMAT_MOD_Y_TILED_CCS)
1267                         return true;
1268                 /* fall through */
1269         case DRM_FORMAT_RGB565:
1270         case DRM_FORMAT_XRGB2101010:
1271         case DRM_FORMAT_XBGR2101010:
1272         case DRM_FORMAT_YUYV:
1273         case DRM_FORMAT_YVYU:
1274         case DRM_FORMAT_UYVY:
1275         case DRM_FORMAT_VYUY:
1276                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1277                         return true;
1278                 /* fall through */
1279         case DRM_FORMAT_C8:
1280                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1281                     modifier == I915_FORMAT_MOD_X_TILED ||
1282                     modifier == I915_FORMAT_MOD_Y_TILED)
1283                         return true;
1284                 /* fall through */
1285         default:
1286                 return false;
1287         }
1288 }
1289
1290 static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
1291                                                     uint32_t format,
1292                                                     uint64_t modifier)
1293 {
1294         struct drm_i915_private *dev_priv = to_i915(plane->dev);
1295
1296         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
1297                 return false;
1298
1299         if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
1300             modifier != DRM_FORMAT_MOD_LINEAR)
1301                 return false;
1302
1303         if (INTEL_GEN(dev_priv) >= 9)
1304                 return skl_mod_supported(format, modifier);
1305         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1306                 return vlv_mod_supported(format, modifier);
1307         else if (INTEL_GEN(dev_priv) >= 6)
1308                 return snb_mod_supported(format, modifier);
1309         else
1310                 return g4x_mod_supported(format, modifier);
1311 }
1312
1313 static const struct drm_plane_funcs intel_sprite_plane_funcs = {
1314         .update_plane = drm_atomic_helper_update_plane,
1315         .disable_plane = drm_atomic_helper_disable_plane,
1316         .destroy = intel_plane_destroy,
1317         .atomic_get_property = intel_plane_atomic_get_property,
1318         .atomic_set_property = intel_plane_atomic_set_property,
1319         .atomic_duplicate_state = intel_plane_duplicate_state,
1320         .atomic_destroy_state = intel_plane_destroy_state,
1321         .format_mod_supported = intel_sprite_plane_format_mod_supported,
1322 };
1323
1324 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
1325                        enum pipe pipe, enum plane_id plane_id)
1326 {
1327         if (plane_id == PLANE_CURSOR)
1328                 return false;
1329
1330         if (INTEL_GEN(dev_priv) >= 10)
1331                 return true;
1332
1333         if (IS_GEMINILAKE(dev_priv))
1334                 return pipe != PIPE_C;
1335
1336         return pipe != PIPE_C &&
1337                 (plane_id == PLANE_PRIMARY ||
1338                  plane_id == PLANE_SPRITE0);
1339 }
1340
1341 struct intel_plane *
1342 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1343                           enum pipe pipe, int plane)
1344 {
1345         struct intel_plane *intel_plane = NULL;
1346         struct intel_plane_state *state = NULL;
1347         unsigned long possible_crtcs;
1348         const uint32_t *plane_formats;
1349         const uint64_t *modifiers;
1350         unsigned int supported_rotations;
1351         int num_plane_formats;
1352         int ret;
1353
1354         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1355         if (!intel_plane) {
1356                 ret = -ENOMEM;
1357                 goto fail;
1358         }
1359
1360         state = intel_create_plane_state(&intel_plane->base);
1361         if (!state) {
1362                 ret = -ENOMEM;
1363                 goto fail;
1364         }
1365         intel_plane->base.state = &state->base;
1366
1367         if (INTEL_GEN(dev_priv) >= 9) {
1368                 intel_plane->can_scale = true;
1369                 state->scaler_id = -1;
1370
1371                 intel_plane->update_plane = skl_update_plane;
1372                 intel_plane->disable_plane = skl_disable_plane;
1373                 intel_plane->get_hw_state = skl_plane_get_hw_state;
1374
1375                 plane_formats = skl_plane_formats;
1376                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1377
1378                 if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
1379                         modifiers = skl_plane_format_modifiers_ccs;
1380                 else
1381                         modifiers = skl_plane_format_modifiers_noccs;
1382         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1383                 intel_plane->can_scale = false;
1384                 intel_plane->max_downscale = 1;
1385
1386                 intel_plane->update_plane = vlv_update_plane;
1387                 intel_plane->disable_plane = vlv_disable_plane;
1388                 intel_plane->get_hw_state = vlv_plane_get_hw_state;
1389
1390                 plane_formats = vlv_plane_formats;
1391                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1392                 modifiers = i9xx_plane_format_modifiers;
1393         } else if (INTEL_GEN(dev_priv) >= 7) {
1394                 if (IS_IVYBRIDGE(dev_priv)) {
1395                         intel_plane->can_scale = true;
1396                         intel_plane->max_downscale = 2;
1397                 } else {
1398                         intel_plane->can_scale = false;
1399                         intel_plane->max_downscale = 1;
1400                 }
1401
1402                 intel_plane->update_plane = ivb_update_plane;
1403                 intel_plane->disable_plane = ivb_disable_plane;
1404                 intel_plane->get_hw_state = ivb_plane_get_hw_state;
1405
1406                 plane_formats = snb_plane_formats;
1407                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1408                 modifiers = i9xx_plane_format_modifiers;
1409         } else {
1410                 intel_plane->can_scale = true;
1411                 intel_plane->max_downscale = 16;
1412
1413                 intel_plane->update_plane = g4x_update_plane;
1414                 intel_plane->disable_plane = g4x_disable_plane;
1415                 intel_plane->get_hw_state = g4x_plane_get_hw_state;
1416
1417                 modifiers = i9xx_plane_format_modifiers;
1418                 if (IS_GEN6(dev_priv)) {
1419                         plane_formats = snb_plane_formats;
1420                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1421                 } else {
1422                         plane_formats = g4x_plane_formats;
1423                         num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1424                 }
1425         }
1426
1427         if (INTEL_GEN(dev_priv) >= 9) {
1428                 supported_rotations =
1429                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1430                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1431         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1432                 supported_rotations =
1433                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1434                         DRM_MODE_REFLECT_X;
1435         } else {
1436                 supported_rotations =
1437                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1438         }
1439
1440         intel_plane->pipe = pipe;
1441         intel_plane->i9xx_plane = plane;
1442         intel_plane->id = PLANE_SPRITE0 + plane;
1443         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);
1444         intel_plane->check_plane = intel_check_sprite_plane;
1445
1446         possible_crtcs = (1 << pipe);
1447
1448         if (INTEL_GEN(dev_priv) >= 9)
1449                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1450                                                possible_crtcs, &intel_sprite_plane_funcs,
1451                                                plane_formats, num_plane_formats,
1452                                                modifiers,
1453                                                DRM_PLANE_TYPE_OVERLAY,
1454                                                "plane %d%c", plane + 2, pipe_name(pipe));
1455         else
1456                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1457                                                possible_crtcs, &intel_sprite_plane_funcs,
1458                                                plane_formats, num_plane_formats,
1459                                                modifiers,
1460                                                DRM_PLANE_TYPE_OVERLAY,
1461                                                "sprite %c", sprite_name(pipe, plane));
1462         if (ret)
1463                 goto fail;
1464
1465         drm_plane_create_rotation_property(&intel_plane->base,
1466                                            DRM_MODE_ROTATE_0,
1467                                            supported_rotations);
1468
1469         drm_plane_create_color_properties(&intel_plane->base,
1470                                           BIT(DRM_COLOR_YCBCR_BT601) |
1471                                           BIT(DRM_COLOR_YCBCR_BT709),
1472                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1473                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1474                                           DRM_COLOR_YCBCR_BT709,
1475                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
1476
1477         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1478
1479         return intel_plane;
1480
1481 fail:
1482         kfree(state);
1483         kfree(intel_plane);
1484
1485         return ERR_PTR(ret);
1486 }