drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34
  35 /**
  36  * DOC: RC6
  37  *
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 static void gen9_init_clock_gating(struct drm_device *dev)
  59 {
  60         struct drm_i915_private *dev_priv = dev->dev_private;
  61
  62         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  63         I915_WRITE(CHICKEN_PAR1_1,
  64                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  65
  66         I915_WRITE(GEN8_CONFIG0,
  67                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  68
  69         /* WaEnableChickenDCPR:skl,bxt,kbl */
  70         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  71                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  72
  73         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  74         /* WaFbcWakeMemOn:skl,bxt,kbl */
  75         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  76                    DISP_FBC_WM_DIS |
  77                    DISP_FBC_MEMORY_WAKE);
  78
  79         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  80         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  81                    ILK_DPFC_DISABLE_DUMMY0);
  82 }
  83
  84 static void bxt_init_clock_gating(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = to_i915(dev);
  87
  88         gen9_init_clock_gating(dev);
  89
  90         /* WaDisableSDEUnitClockGating:bxt */
  91         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  92                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  93
  94         /*
  95          * FIXME:
  96          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  97          */
  98         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  99                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 100
 101         /*
 102          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 103          * to stay fully on.
 104          */
 105         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 106                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 107                            PWM1_GATING_DIS | PWM2_GATING_DIS);
 108 }
 109
 110 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 111 {
 112         struct drm_i915_private *dev_priv = to_i915(dev);
 113         u32 tmp;
 114
 115         tmp = I915_READ(CLKCFG);
 116
 117         switch (tmp & CLKCFG_FSB_MASK) {
 118         case CLKCFG_FSB_533:
 119                 dev_priv->fsb_freq = 533; /* 133*4 */
 120                 break;
 121         case CLKCFG_FSB_800:
 122                 dev_priv->fsb_freq = 800; /* 200*4 */
 123                 break;
 124         case CLKCFG_FSB_667:
 125                 dev_priv->fsb_freq =  667; /* 167*4 */
 126                 break;
 127         case CLKCFG_FSB_400:
 128                 dev_priv->fsb_freq = 400; /* 100*4 */
 129                 break;
 130         }
 131
 132         switch (tmp & CLKCFG_MEM_MASK) {
 133         case CLKCFG_MEM_533:
 134                 dev_priv->mem_freq = 533;
 135                 break;
 136         case CLKCFG_MEM_667:
 137                 dev_priv->mem_freq = 667;
 138                 break;
 139         case CLKCFG_MEM_800:
 140                 dev_priv->mem_freq = 800;
 141                 break;
 142         }
 143
 144         /* detect pineview DDR3 setting */
 145         tmp = I915_READ(CSHRDDR3CTL);
 146         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 147 }
 148
 149 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 150 {
 151         struct drm_i915_private *dev_priv = to_i915(dev);
 152         u16 ddrpll, csipll;
 153
 154         ddrpll = I915_READ16(DDRMPLL1);
 155         csipll = I915_READ16(CSIPLL0);
 156
 157         switch (ddrpll & 0xff) {
 158         case 0xc:
 159                 dev_priv->mem_freq = 800;
 160                 break;
 161         case 0x10:
 162                 dev_priv->mem_freq = 1066;
 163                 break;
 164         case 0x14:
 165                 dev_priv->mem_freq = 1333;
 166                 break;
 167         case 0x18:
 168                 dev_priv->mem_freq = 1600;
 169                 break;
 170         default:
 171                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 172                                  ddrpll & 0xff);
 173                 dev_priv->mem_freq = 0;
 174                 break;
 175         }
 176
 177         dev_priv->ips.r_t = dev_priv->mem_freq;
 178
 179         switch (csipll & 0x3ff) {
 180         case 0x00c:
 181                 dev_priv->fsb_freq = 3200;
 182                 break;
 183         case 0x00e:
 184                 dev_priv->fsb_freq = 3733;
 185                 break;
 186         case 0x010:
 187                 dev_priv->fsb_freq = 4266;
 188                 break;
 189         case 0x012:
 190                 dev_priv->fsb_freq = 4800;
 191                 break;
 192         case 0x014:
 193                 dev_priv->fsb_freq = 5333;
 194                 break;
 195         case 0x016:
 196                 dev_priv->fsb_freq = 5866;
 197                 break;
 198         case 0x018:
 199                 dev_priv->fsb_freq = 6400;
 200                 break;
 201         default:
 202                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 203                                  csipll & 0x3ff);
 204                 dev_priv->fsb_freq = 0;
 205                 break;
 206         }
 207
 208         if (dev_priv->fsb_freq == 3200) {
 209                 dev_priv->ips.c_m = 0;
 210         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 211                 dev_priv->ips.c_m = 1;
 212         } else {
 213                 dev_priv->ips.c_m = 2;
 214         }
 215 }
 216
 217 static const struct cxsr_latency cxsr_latency_table[] = {
 218         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 219         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 220         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 221         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 222         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 223
 224         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 225         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 226         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 227         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 228         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 229
 230         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 231         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 232         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 233         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 234         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 235
 236         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 237         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 238         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 239         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 240         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 241
 242         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 243         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 244         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 245         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 246         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 247
 248         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 249         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 250         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 251         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 252         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 253 };
 254
 255 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 256                                                          int is_ddr3,
 257                                                          int fsb,
 258                                                          int mem)
 259 {
 260         const struct cxsr_latency *latency;
 261         int i;
 262
 263         if (fsb == 0 || mem == 0)
 264                 return NULL;
 265
 266         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 267                 latency = &cxsr_latency_table[i];
 268                 if (is_desktop == latency->is_desktop &&
 269                     is_ddr3 == latency->is_ddr3 &&
 270                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 271                         return latency;
 272         }
 273
 274         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 275
 276         return NULL;
 277 }
 278
 279 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 280 {
 281         u32 val;
 282
 283         mutex_lock(&dev_priv->rps.hw_lock);
 284
 285         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 286         if (enable)
 287                 val &= ~FORCE_DDR_HIGH_FREQ;
 288         else
 289                 val |= FORCE_DDR_HIGH_FREQ;
 290         val &= ~FORCE_DDR_LOW_FREQ;
 291         val |= FORCE_DDR_FREQ_REQ_ACK;
 292         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 293
 294         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 295                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 296                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 297
 298         mutex_unlock(&dev_priv->rps.hw_lock);
 299 }
 300
 301 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 302 {
 303         u32 val;
 304
 305         mutex_lock(&dev_priv->rps.hw_lock);
 306
 307         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 308         if (enable)
 309                 val |= DSP_MAXFIFO_PM5_ENABLE;
 310         else
 311                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 312         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 313
 314         mutex_unlock(&dev_priv->rps.hw_lock);
 315 }
 316
 317 #define FW_WM(value, plane) \
 318         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 319
 320 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 321 {
 322         struct drm_device *dev = &dev_priv->drm;
 323         u32 val;
 324
 325         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 326                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 327                 POSTING_READ(FW_BLC_SELF_VLV);
 328                 dev_priv->wm.vlv.cxsr = enable;
 329         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 330                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 331                 POSTING_READ(FW_BLC_SELF);
 332         } else if (IS_PINEVIEW(dev)) {
 333                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 334                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 335                 I915_WRITE(DSPFW3, val);
 336                 POSTING_READ(DSPFW3);
 337         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 338                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 339                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 340                 I915_WRITE(FW_BLC_SELF, val);
 341                 POSTING_READ(FW_BLC_SELF);
 342         } else if (IS_I915GM(dev)) {
 343                 /*
 344                  * FIXME can't find a bit like this for 915G, and
 345                  * and yet it does have the related watermark in
 346                  * FW_BLC_SELF. What's going on?
 347                  */
 348                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 349                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 350                 I915_WRITE(INSTPM, val);
 351                 POSTING_READ(INSTPM);
 352         } else {
 353                 return;
 354         }
 355
 356         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 357                       enable ? "enabled" : "disabled");
 358 }
 359
 360
 361 /*
 362  * Latency for FIFO fetches is dependent on several factors:
 363  *   - memory configuration (speed, channels)
 364  *   - chipset
 365  *   - current MCH state
 366  * It can be fairly high in some situations, so here we assume a fairly
 367  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 368  * set this value too high, the FIFO will fetch frequently to stay full)
 369  * and power consumption (set it too low to save power and we might see
 370  * FIFO underruns and display "flicker").
 371  *
 372  * A value of 5us seems to be a good balance; safe for very low end
 373  * platforms but not overly aggressive on lower latency configs.
 374  */
 375 static const int pessimal_latency_ns = 5000;
 376
 377 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 378         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 379
 380 static int vlv_get_fifo_size(struct drm_device *dev,
 381                               enum pipe pipe, int plane)
 382 {
 383         struct drm_i915_private *dev_priv = to_i915(dev);
 384         int sprite0_start, sprite1_start, size;
 385
 386         switch (pipe) {
 387                 uint32_t dsparb, dsparb2, dsparb3;
 388         case PIPE_A:
 389                 dsparb = I915_READ(DSPARB);
 390                 dsparb2 = I915_READ(DSPARB2);
 391                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 392                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 393                 break;
 394         case PIPE_B:
 395                 dsparb = I915_READ(DSPARB);
 396                 dsparb2 = I915_READ(DSPARB2);
 397                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 398                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 399                 break;
 400         case PIPE_C:
 401                 dsparb2 = I915_READ(DSPARB2);
 402                 dsparb3 = I915_READ(DSPARB3);
 403                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 404                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 405                 break;
 406         default:
 407                 return 0;
 408         }
 409
 410         switch (plane) {
 411         case 0:
 412                 size = sprite0_start;
 413                 break;
 414         case 1:
 415                 size = sprite1_start - sprite0_start;
 416                 break;
 417         case 2:
 418                 size = 512 - 1 - sprite1_start;
 419                 break;
 420         default:
 421                 return 0;
 422         }
 423
 424         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 425                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 426                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 427                       size);
 428
 429         return size;
 430 }
 431
 432 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 433 {
 434         struct drm_i915_private *dev_priv = to_i915(dev);
 435         uint32_t dsparb = I915_READ(DSPARB);
 436         int size;
 437
 438         size = dsparb & 0x7f;
 439         if (plane)
 440                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 441
 442         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 443                       plane ? "B" : "A", size);
 444
 445         return size;
 446 }
 447
 448 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 449 {
 450         struct drm_i915_private *dev_priv = to_i915(dev);
 451         uint32_t dsparb = I915_READ(DSPARB);
 452         int size;
 453
 454         size = dsparb & 0x1ff;
 455         if (plane)
 456                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 457         size >>= 1; /* Convert to cachelines */
 458
 459         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 460                       plane ? "B" : "A", size);
 461
 462         return size;
 463 }
 464
 465 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 466 {
 467         struct drm_i915_private *dev_priv = to_i915(dev);
 468         uint32_t dsparb = I915_READ(DSPARB);
 469         int size;
 470
 471         size = dsparb & 0x7f;
 472         size >>= 2; /* Convert to cachelines */
 473
 474         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 475                       plane ? "B" : "A",
 476                       size);
 477
 478         return size;
 479 }
 480
 481 /* Pineview has different values for various configs */
 482 static const struct intel_watermark_params pineview_display_wm = {
 483         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 484         .max_wm = PINEVIEW_MAX_WM,
 485         .default_wm = PINEVIEW_DFT_WM,
 486         .guard_size = PINEVIEW_GUARD_WM,
 487         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 488 };
 489 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 490         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 491         .max_wm = PINEVIEW_MAX_WM,
 492         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 493         .guard_size = PINEVIEW_GUARD_WM,
 494         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 495 };
 496 static const struct intel_watermark_params pineview_cursor_wm = {
 497         .fifo_size = PINEVIEW_CURSOR_FIFO,
 498         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 499         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 500         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 501         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 502 };
 503 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 504         .fifo_size = PINEVIEW_CURSOR_FIFO,
 505         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 506         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 507         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 508         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 509 };
 510 static const struct intel_watermark_params g4x_wm_info = {
 511         .fifo_size = G4X_FIFO_SIZE,
 512         .max_wm = G4X_MAX_WM,
 513         .default_wm = G4X_MAX_WM,
 514         .guard_size = 2,
 515         .cacheline_size = G4X_FIFO_LINE_SIZE,
 516 };
 517 static const struct intel_watermark_params g4x_cursor_wm_info = {
 518         .fifo_size = I965_CURSOR_FIFO,
 519         .max_wm = I965_CURSOR_MAX_WM,
 520         .default_wm = I965_CURSOR_DFT_WM,
 521         .guard_size = 2,
 522         .cacheline_size = G4X_FIFO_LINE_SIZE,
 523 };
 524 static const struct intel_watermark_params i965_cursor_wm_info = {
 525         .fifo_size = I965_CURSOR_FIFO,
 526         .max_wm = I965_CURSOR_MAX_WM,
 527         .default_wm = I965_CURSOR_DFT_WM,
 528         .guard_size = 2,
 529         .cacheline_size = I915_FIFO_LINE_SIZE,
 530 };
 531 static const struct intel_watermark_params i945_wm_info = {
 532         .fifo_size = I945_FIFO_SIZE,
 533         .max_wm = I915_MAX_WM,
 534         .default_wm = 1,
 535         .guard_size = 2,
 536         .cacheline_size = I915_FIFO_LINE_SIZE,
 537 };
 538 static const struct intel_watermark_params i915_wm_info = {
 539         .fifo_size = I915_FIFO_SIZE,
 540         .max_wm = I915_MAX_WM,
 541         .default_wm = 1,
 542         .guard_size = 2,
 543         .cacheline_size = I915_FIFO_LINE_SIZE,
 544 };
 545 static const struct intel_watermark_params i830_a_wm_info = {
 546         .fifo_size = I855GM_FIFO_SIZE,
 547         .max_wm = I915_MAX_WM,
 548         .default_wm = 1,
 549         .guard_size = 2,
 550         .cacheline_size = I830_FIFO_LINE_SIZE,
 551 };
 552 static const struct intel_watermark_params i830_bc_wm_info = {
 553         .fifo_size = I855GM_FIFO_SIZE,
 554         .max_wm = I915_MAX_WM/2,
 555         .default_wm = 1,
 556         .guard_size = 2,
 557         .cacheline_size = I830_FIFO_LINE_SIZE,
 558 };
 559 static const struct intel_watermark_params i845_wm_info = {
 560         .fifo_size = I830_FIFO_SIZE,
 561         .max_wm = I915_MAX_WM,
 562         .default_wm = 1,
 563         .guard_size = 2,
 564         .cacheline_size = I830_FIFO_LINE_SIZE,
 565 };
 566
 567 /**
 568  * intel_calculate_wm - calculate watermark level
 569  * @clock_in_khz: pixel clock
 570  * @wm: chip FIFO params
 571  * @cpp: bytes per pixel
 572  * @latency_ns: memory latency for the platform
 573  *
 574  * Calculate the watermark level (the level at which the display plane will
 575  * start fetching from memory again).  Each chip has a different display
 576  * FIFO size and allocation, so the caller needs to figure that out and pass
 577  * in the correct intel_watermark_params structure.
 578  *
 579  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 580  * on the pixel size.  When it reaches the watermark level, it'll start
 581  * fetching FIFO line sized based chunks from memory until the FIFO fills
 582  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 583  * will occur, and a display engine hang could result.
 584  */
 585 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 586                                         const struct intel_watermark_params *wm,
 587                                         int fifo_size, int cpp,
 588                                         unsigned long latency_ns)
 589 {
 590         long entries_required, wm_size;
 591
 592         /*
 593          * Note: we need to make sure we don't overflow for various clock &
 594          * latency values.
 595          * clocks go from a few thousand to several hundred thousand.
 596          * latency is usually a few thousand
 597          */
 598         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 599                 1000;
 600         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 601
 602         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 603
 604         wm_size = fifo_size - (entries_required + wm->guard_size);
 605
 606         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 607
 608         /* Don't promote wm_size to unsigned... */
 609         if (wm_size > (long)wm->max_wm)
 610                 wm_size = wm->max_wm;
 611         if (wm_size <= 0)
 612                 wm_size = wm->default_wm;
 613
 614         /*
 615          * Bspec seems to indicate that the value shouldn't be lower than
 616          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 617          * Lets go for 8 which is the burst size since certain platforms
 618          * already use a hardcoded 8 (which is what the spec says should be
 619          * done).
 620          */
 621         if (wm_size <= 8)
 622                 wm_size = 8;
 623
 624         return wm_size;
 625 }
 626
 627 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 628 {
 629         struct drm_crtc *crtc, *enabled = NULL;
 630
 631         for_each_crtc(dev, crtc) {
 632                 if (intel_crtc_active(crtc)) {
 633                         if (enabled)
 634                                 return NULL;
 635                         enabled = crtc;
 636                 }
 637         }
 638
 639         return enabled;
 640 }
 641
 642 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 643 {
 644         struct drm_device *dev = unused_crtc->dev;
 645         struct drm_i915_private *dev_priv = to_i915(dev);
 646         struct drm_crtc *crtc;
 647         const struct cxsr_latency *latency;
 648         u32 reg;
 649         unsigned long wm;
 650
 651         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 652                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 653         if (!latency) {
 654                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 655                 intel_set_memory_cxsr(dev_priv, false);
 656                 return;
 657         }
 658
 659         crtc = single_enabled_crtc(dev);
 660         if (crtc) {
 661                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 662                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 663                 int clock = adjusted_mode->crtc_clock;
 664
 665                 /* Display SR */
 666                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 667                                         pineview_display_wm.fifo_size,
 668                                         cpp, latency->display_sr);
 669                 reg = I915_READ(DSPFW1);
 670                 reg &= ~DSPFW_SR_MASK;
 671                 reg |= FW_WM(wm, SR);
 672                 I915_WRITE(DSPFW1, reg);
 673                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 674
 675                 /* cursor SR */
 676                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 677                                         pineview_display_wm.fifo_size,
 678                                         cpp, latency->cursor_sr);
 679                 reg = I915_READ(DSPFW3);
 680                 reg &= ~DSPFW_CURSOR_SR_MASK;
 681                 reg |= FW_WM(wm, CURSOR_SR);
 682                 I915_WRITE(DSPFW3, reg);
 683
 684                 /* Display HPLL off SR */
 685                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 686                                         pineview_display_hplloff_wm.fifo_size,
 687                                         cpp, latency->display_hpll_disable);
 688                 reg = I915_READ(DSPFW3);
 689                 reg &= ~DSPFW_HPLL_SR_MASK;
 690                 reg |= FW_WM(wm, HPLL_SR);
 691                 I915_WRITE(DSPFW3, reg);
 692
 693                 /* cursor HPLL off SR */
 694                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 695                                         pineview_display_hplloff_wm.fifo_size,
 696                                         cpp, latency->cursor_hpll_disable);
 697                 reg = I915_READ(DSPFW3);
 698                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 699                 reg |= FW_WM(wm, HPLL_CURSOR);
 700                 I915_WRITE(DSPFW3, reg);
 701                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 702
 703                 intel_set_memory_cxsr(dev_priv, true);
 704         } else {
 705                 intel_set_memory_cxsr(dev_priv, false);
 706         }
 707 }
 708
 709 static bool g4x_compute_wm0(struct drm_device *dev,
 710                             int plane,
 711                             const struct intel_watermark_params *display,
 712                             int display_latency_ns,
 713                             const struct intel_watermark_params *cursor,
 714                             int cursor_latency_ns,
 715                             int *plane_wm,
 716                             int *cursor_wm)
 717 {
 718         struct drm_crtc *crtc;
 719         const struct drm_display_mode *adjusted_mode;
 720         int htotal, hdisplay, clock, cpp;
 721         int line_time_us, line_count;
 722         int entries, tlb_miss;
 723
 724         crtc = intel_get_crtc_for_plane(dev, plane);
 725         if (!intel_crtc_active(crtc)) {
 726                 *cursor_wm = cursor->guard_size;
 727                 *plane_wm = display->guard_size;
 728                 return false;
 729         }
 730
 731         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 732         clock = adjusted_mode->crtc_clock;
 733         htotal = adjusted_mode->crtc_htotal;
 734         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 735         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 736
 737         /* Use the small buffer method to calculate plane watermark */
 738         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 739         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 740         if (tlb_miss > 0)
 741                 entries += tlb_miss;
 742         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 743         *plane_wm = entries + display->guard_size;
 744         if (*plane_wm > (int)display->max_wm)
 745                 *plane_wm = display->max_wm;
 746
 747         /* Use the large buffer method to calculate cursor watermark */
 748         line_time_us = max(htotal * 1000 / clock, 1);
 749         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 750         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 751         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 752         if (tlb_miss > 0)
 753                 entries += tlb_miss;
 754         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 755         *cursor_wm = entries + cursor->guard_size;
 756         if (*cursor_wm > (int)cursor->max_wm)
 757                 *cursor_wm = (int)cursor->max_wm;
 758
 759         return true;
 760 }
 761
 762 /*
 763  * Check the wm result.
 764  *
 765  * If any calculated watermark values is larger than the maximum value that
 766  * can be programmed into the associated watermark register, that watermark
 767  * must be disabled.
 768  */
 769 static bool g4x_check_srwm(struct drm_device *dev,
 770                            int display_wm, int cursor_wm,
 771                            const struct intel_watermark_params *display,
 772                            const struct intel_watermark_params *cursor)
 773 {
 774         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 775                       display_wm, cursor_wm);
 776
 777         if (display_wm > display->max_wm) {
 778                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 779                               display_wm, display->max_wm);
 780                 return false;
 781         }
 782
 783         if (cursor_wm > cursor->max_wm) {
 784                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 785                               cursor_wm, cursor->max_wm);
 786                 return false;
 787         }
 788
 789         if (!(display_wm || cursor_wm)) {
 790                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 791                 return false;
 792         }
 793
 794         return true;
 795 }
 796
 797 static bool g4x_compute_srwm(struct drm_device *dev,
 798                              int plane,
 799                              int latency_ns,
 800                              const struct intel_watermark_params *display,
 801                              const struct intel_watermark_params *cursor,
 802                              int *display_wm, int *cursor_wm)
 803 {
 804         struct drm_crtc *crtc;
 805         const struct drm_display_mode *adjusted_mode;
 806         int hdisplay, htotal, cpp, clock;
 807         unsigned long line_time_us;
 808         int line_count, line_size;
 809         int small, large;
 810         int entries;
 811
 812         if (!latency_ns) {
 813                 *display_wm = *cursor_wm = 0;
 814                 return false;
 815         }
 816
 817         crtc = intel_get_crtc_for_plane(dev, plane);
 818         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 819         clock = adjusted_mode->crtc_clock;
 820         htotal = adjusted_mode->crtc_htotal;
 821         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 822         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 823
 824         line_time_us = max(htotal * 1000 / clock, 1);
 825         line_count = (latency_ns / line_time_us + 1000) / 1000;
 826         line_size = hdisplay * cpp;
 827
 828         /* Use the minimum of the small and large buffer method for primary */
 829         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 830         large = line_count * line_size;
 831
 832         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 833         *display_wm = entries + display->guard_size;
 834
 835         /* calculate the self-refresh watermark for display cursor */
 836         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 837         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 838         *cursor_wm = entries + cursor->guard_size;
 839
 840         return g4x_check_srwm(dev,
 841                               *display_wm, *cursor_wm,
 842                               display, cursor);
 843 }
 844
 845 #define FW_WM_VLV(value, plane) \
 846         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 847
 848 static void vlv_write_wm_values(struct intel_crtc *crtc,
 849                                 const struct vlv_wm_values *wm)
 850 {
 851         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 852         enum pipe pipe = crtc->pipe;
 853
 854         I915_WRITE(VLV_DDL(pipe),
 855                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 856                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 857                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 858                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 859
 860         I915_WRITE(DSPFW1,
 861                    FW_WM(wm->sr.plane, SR) |
 862                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 863                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 864                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 865         I915_WRITE(DSPFW2,
 866                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 867                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 868                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 869         I915_WRITE(DSPFW3,
 870                    FW_WM(wm->sr.cursor, CURSOR_SR));
 871
 872         if (IS_CHERRYVIEW(dev_priv)) {
 873                 I915_WRITE(DSPFW7_CHV,
 874                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 875                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 876                 I915_WRITE(DSPFW8_CHV,
 877                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 878                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 879                 I915_WRITE(DSPFW9_CHV,
 880                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 881                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 882                 I915_WRITE(DSPHOWM,
 883                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 884                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 885                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 886                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 887                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 888                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 889                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 890                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 891                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 892                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 893         } else {
 894                 I915_WRITE(DSPFW7,
 895                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 896                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 897                 I915_WRITE(DSPHOWM,
 898                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 899                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 900                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 901                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 902                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 903                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 904                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 905         }
 906
 907         /* zero (unused) WM1 watermarks */
 908         I915_WRITE(DSPFW4, 0);
 909         I915_WRITE(DSPFW5, 0);
 910         I915_WRITE(DSPFW6, 0);
 911         I915_WRITE(DSPHOWM1, 0);
 912
 913         POSTING_READ(DSPFW1);
 914 }
 915
 916 #undef FW_WM_VLV
 917
 918 enum vlv_wm_level {
 919         VLV_WM_LEVEL_PM2,
 920         VLV_WM_LEVEL_PM5,
 921         VLV_WM_LEVEL_DDR_DVFS,
 922 };
 923
 924 /* latency must be in 0.1us units. */
 925 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 926                                    unsigned int pipe_htotal,
 927                                    unsigned int horiz_pixels,
 928                                    unsigned int cpp,
 929                                    unsigned int latency)
 930 {
 931         unsigned int ret;
 932
 933         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 934         ret = (ret + 1) * horiz_pixels * cpp;
 935         ret = DIV_ROUND_UP(ret, 64);
 936
 937         return ret;
 938 }
 939
 940 static void vlv_setup_wm_latency(struct drm_device *dev)
 941 {
 942         struct drm_i915_private *dev_priv = to_i915(dev);
 943
 944         /* all latencies in usec */
 945         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 946
 947         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 948
 949         if (IS_CHERRYVIEW(dev_priv)) {
 950                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 951                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 952
 953                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 954         }
 955 }
 956
 957 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 958                                      struct intel_crtc *crtc,
 959                                      const struct intel_plane_state *state,
 960                                      int level)
 961 {
 962         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 963         int clock, htotal, cpp, width, wm;
 964
 965         if (dev_priv->wm.pri_latency[level] == 0)
 966                 return USHRT_MAX;
 967
 968         if (!state->base.visible)
 969                 return 0;
 970
 971         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 972         clock = crtc->config->base.adjusted_mode.crtc_clock;
 973         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 974         width = crtc->config->pipe_src_w;
 975         if (WARN_ON(htotal == 0))
 976                 htotal = 1;
 977
 978         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 979                 /*
 980                  * FIXME the formula gives values that are
 981                  * too big for the cursor FIFO, and hence we
 982                  * would never be able to use cursors. For
 983                  * now just hardcode the watermark.
 984                  */
 985                 wm = 63;
 986         } else {
 987                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 988                                     dev_priv->wm.pri_latency[level] * 10);
 989         }
 990
 991         return min_t(int, wm, USHRT_MAX);
 992 }
 993
 994 static void vlv_compute_fifo(struct intel_crtc *crtc)
 995 {
 996         struct drm_device *dev = crtc->base.dev;
 997         struct vlv_wm_state *wm_state = &crtc->wm_state;
 998         struct intel_plane *plane;
 999         unsigned int total_rate = 0;
1000         const int fifo_size = 512 - 1;
1001         int fifo_extra, fifo_left = fifo_size;
1002
1003         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1004                 struct intel_plane_state *state =
1005                         to_intel_plane_state(plane->base.state);
1006
1007                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1008                         continue;
1009
1010                 if (state->base.visible) {
1011                         wm_state->num_active_planes++;
1012                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013                 }
1014         }
1015
1016         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1017                 struct intel_plane_state *state =
1018                         to_intel_plane_state(plane->base.state);
1019                 unsigned int rate;
1020
1021                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022                         plane->wm.fifo_size = 63;
1023                         continue;
1024                 }
1025
1026                 if (!state->base.visible) {
1027                         plane->wm.fifo_size = 0;
1028                         continue;
1029                 }
1030
1031                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1032                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1033                 fifo_left -= plane->wm.fifo_size;
1034         }
1035
1036         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1037
1038         /* spread the remainder evenly */
1039         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040                 int plane_extra;
1041
1042                 if (fifo_left == 0)
1043                         break;
1044
1045                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046                         continue;
1047
1048                 /* give it all to the first plane if none are active */
1049                 if (plane->wm.fifo_size == 0 &&
1050                     wm_state->num_active_planes)
1051                         continue;
1052
1053                 plane_extra = min(fifo_extra, fifo_left);
1054                 plane->wm.fifo_size += plane_extra;
1055                 fifo_left -= plane_extra;
1056         }
1057
1058         WARN_ON(fifo_left != 0);
1059 }
1060
1061 static void vlv_invert_wms(struct intel_crtc *crtc)
1062 {
1063         struct vlv_wm_state *wm_state = &crtc->wm_state;
1064         int level;
1065
1066         for (level = 0; level < wm_state->num_levels; level++) {
1067                 struct drm_device *dev = crtc->base.dev;
1068                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1069                 struct intel_plane *plane;
1070
1071                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1072                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1073
1074                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1075                         switch (plane->base.type) {
1076                                 int sprite;
1077                         case DRM_PLANE_TYPE_CURSOR:
1078                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1079                                         wm_state->wm[level].cursor;
1080                                 break;
1081                         case DRM_PLANE_TYPE_PRIMARY:
1082                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1083                                         wm_state->wm[level].primary;
1084                                 break;
1085                         case DRM_PLANE_TYPE_OVERLAY:
1086                                 sprite = plane->plane;
1087                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1088                                         wm_state->wm[level].sprite[sprite];
1089                                 break;
1090                         }
1091                 }
1092         }
1093 }
1094
1095 static void vlv_compute_wm(struct intel_crtc *crtc)
1096 {
1097         struct drm_device *dev = crtc->base.dev;
1098         struct vlv_wm_state *wm_state = &crtc->wm_state;
1099         struct intel_plane *plane;
1100         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1101         int level;
1102
1103         memset(wm_state, 0, sizeof(*wm_state));
1104
1105         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1106         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1107
1108         wm_state->num_active_planes = 0;
1109
1110         vlv_compute_fifo(crtc);
1111
1112         if (wm_state->num_active_planes != 1)
1113                 wm_state->cxsr = false;
1114
1115         if (wm_state->cxsr) {
1116                 for (level = 0; level < wm_state->num_levels; level++) {
1117                         wm_state->sr[level].plane = sr_fifo_size;
1118                         wm_state->sr[level].cursor = 63;
1119                 }
1120         }
1121
1122         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123                 struct intel_plane_state *state =
1124                         to_intel_plane_state(plane->base.state);
1125
1126                 if (!state->base.visible)
1127                         continue;
1128
1129                 /* normal watermarks */
1130                 for (level = 0; level < wm_state->num_levels; level++) {
1131                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1132                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1133
1134                         /* hack */
1135                         if (WARN_ON(level == 0 && wm > max_wm))
1136                                 wm = max_wm;
1137
1138                         if (wm > plane->wm.fifo_size)
1139                                 break;
1140
1141                         switch (plane->base.type) {
1142                                 int sprite;
1143                         case DRM_PLANE_TYPE_CURSOR:
1144                                 wm_state->wm[level].cursor = wm;
1145                                 break;
1146                         case DRM_PLANE_TYPE_PRIMARY:
1147                                 wm_state->wm[level].primary = wm;
1148                                 break;
1149                         case DRM_PLANE_TYPE_OVERLAY:
1150                                 sprite = plane->plane;
1151                                 wm_state->wm[level].sprite[sprite] = wm;
1152                                 break;
1153                         }
1154                 }
1155
1156                 wm_state->num_levels = level;
1157
1158                 if (!wm_state->cxsr)
1159                         continue;
1160
1161                 /* maxfifo watermarks */
1162                 switch (plane->base.type) {
1163                         int sprite, level;
1164                 case DRM_PLANE_TYPE_CURSOR:
1165                         for (level = 0; level < wm_state->num_levels; level++)
1166                                 wm_state->sr[level].cursor =
1167                                         wm_state->wm[level].cursor;
1168                         break;
1169                 case DRM_PLANE_TYPE_PRIMARY:
1170                         for (level = 0; level < wm_state->num_levels; level++)
1171                                 wm_state->sr[level].plane =
1172                                         min(wm_state->sr[level].plane,
1173                                             wm_state->wm[level].primary);
1174                         break;
1175                 case DRM_PLANE_TYPE_OVERLAY:
1176                         sprite = plane->plane;
1177                         for (level = 0; level < wm_state->num_levels; level++)
1178                                 wm_state->sr[level].plane =
1179                                         min(wm_state->sr[level].plane,
1180                                             wm_state->wm[level].sprite[sprite]);
1181                         break;
1182                 }
1183         }
1184
1185         /* clear any (partially) filled invalid levels */
1186         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1187                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1188                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1189         }
1190
1191         vlv_invert_wms(crtc);
1192 }
1193
1194 #define VLV_FIFO(plane, value) \
1195         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1196
1197 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1198 {
1199         struct drm_device *dev = crtc->base.dev;
1200         struct drm_i915_private *dev_priv = to_i915(dev);
1201         struct intel_plane *plane;
1202         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1203
1204         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1205                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1206                         WARN_ON(plane->wm.fifo_size != 63);
1207                         continue;
1208                 }
1209
1210                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1211                         sprite0_start = plane->wm.fifo_size;
1212                 else if (plane->plane == 0)
1213                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1214                 else
1215                         fifo_size = sprite1_start + plane->wm.fifo_size;
1216         }
1217
1218         WARN_ON(fifo_size != 512 - 1);
1219
1220         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1221                       pipe_name(crtc->pipe), sprite0_start,
1222                       sprite1_start, fifo_size);
1223
1224         switch (crtc->pipe) {
1225                 uint32_t dsparb, dsparb2, dsparb3;
1226         case PIPE_A:
1227                 dsparb = I915_READ(DSPARB);
1228                 dsparb2 = I915_READ(DSPARB2);
1229
1230                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1231                             VLV_FIFO(SPRITEB, 0xff));
1232                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1233                            VLV_FIFO(SPRITEB, sprite1_start));
1234
1235                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1236                              VLV_FIFO(SPRITEB_HI, 0x1));
1237                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1238                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1239
1240                 I915_WRITE(DSPARB, dsparb);
1241                 I915_WRITE(DSPARB2, dsparb2);
1242                 break;
1243         case PIPE_B:
1244                 dsparb = I915_READ(DSPARB);
1245                 dsparb2 = I915_READ(DSPARB2);
1246
1247                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1248                             VLV_FIFO(SPRITED, 0xff));
1249                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1250                            VLV_FIFO(SPRITED, sprite1_start));
1251
1252                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1253                              VLV_FIFO(SPRITED_HI, 0xff));
1254                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1255                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1256
1257                 I915_WRITE(DSPARB, dsparb);
1258                 I915_WRITE(DSPARB2, dsparb2);
1259                 break;
1260         case PIPE_C:
1261                 dsparb3 = I915_READ(DSPARB3);
1262                 dsparb2 = I915_READ(DSPARB2);
1263
1264                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1265                              VLV_FIFO(SPRITEF, 0xff));
1266                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1267                             VLV_FIFO(SPRITEF, sprite1_start));
1268
1269                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1270                              VLV_FIFO(SPRITEF_HI, 0xff));
1271                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1272                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1273
1274                 I915_WRITE(DSPARB3, dsparb3);
1275                 I915_WRITE(DSPARB2, dsparb2);
1276                 break;
1277         default:
1278                 break;
1279         }
1280 }
1281
1282 #undef VLV_FIFO
1283
1284 static void vlv_merge_wm(struct drm_device *dev,
1285                          struct vlv_wm_values *wm)
1286 {
1287         struct intel_crtc *crtc;
1288         int num_active_crtcs = 0;
1289
1290         wm->level = to_i915(dev)->wm.max_level;
1291         wm->cxsr = true;
1292
1293         for_each_intel_crtc(dev, crtc) {
1294                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1295
1296                 if (!crtc->active)
1297                         continue;
1298
1299                 if (!wm_state->cxsr)
1300                         wm->cxsr = false;
1301
1302                 num_active_crtcs++;
1303                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1304         }
1305
1306         if (num_active_crtcs != 1)
1307                 wm->cxsr = false;
1308
1309         if (num_active_crtcs > 1)
1310                 wm->level = VLV_WM_LEVEL_PM2;
1311
1312         for_each_intel_crtc(dev, crtc) {
1313                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1314                 enum pipe pipe = crtc->pipe;
1315
1316                 if (!crtc->active)
1317                         continue;
1318
1319                 wm->pipe[pipe] = wm_state->wm[wm->level];
1320                 if (wm->cxsr)
1321                         wm->sr = wm_state->sr[wm->level];
1322
1323                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1324                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1325                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1326                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1327         }
1328 }
1329
1330 static void vlv_update_wm(struct drm_crtc *crtc)
1331 {
1332         struct drm_device *dev = crtc->dev;
1333         struct drm_i915_private *dev_priv = to_i915(dev);
1334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1335         enum pipe pipe = intel_crtc->pipe;
1336         struct vlv_wm_values wm = {};
1337
1338         vlv_compute_wm(intel_crtc);
1339         vlv_merge_wm(dev, &wm);
1340
1341         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1342                 /* FIXME should be part of crtc atomic commit */
1343                 vlv_pipe_set_fifo_size(intel_crtc);
1344                 return;
1345         }
1346
1347         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1348             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1349                 chv_set_memory_dvfs(dev_priv, false);
1350
1351         if (wm.level < VLV_WM_LEVEL_PM5 &&
1352             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1353                 chv_set_memory_pm5(dev_priv, false);
1354
1355         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1356                 intel_set_memory_cxsr(dev_priv, false);
1357
1358         /* FIXME should be part of crtc atomic commit */
1359         vlv_pipe_set_fifo_size(intel_crtc);
1360
1361         vlv_write_wm_values(intel_crtc, &wm);
1362
1363         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1364                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1365                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1366                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1367                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1368
1369         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1370                 intel_set_memory_cxsr(dev_priv, true);
1371
1372         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1373             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1374                 chv_set_memory_pm5(dev_priv, true);
1375
1376         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1377             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1378                 chv_set_memory_dvfs(dev_priv, true);
1379
1380         dev_priv->wm.vlv = wm;
1381 }
1382
1383 #define single_plane_enabled(mask) is_power_of_2(mask)
1384
1385 static void g4x_update_wm(struct drm_crtc *crtc)
1386 {
1387         struct drm_device *dev = crtc->dev;
1388         static const int sr_latency_ns = 12000;
1389         struct drm_i915_private *dev_priv = to_i915(dev);
1390         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1391         int plane_sr, cursor_sr;
1392         unsigned int enabled = 0;
1393         bool cxsr_enabled;
1394
1395         if (g4x_compute_wm0(dev, PIPE_A,
1396                             &g4x_wm_info, pessimal_latency_ns,
1397                             &g4x_cursor_wm_info, pessimal_latency_ns,
1398                             &planea_wm, &cursora_wm))
1399                 enabled |= 1 << PIPE_A;
1400
1401         if (g4x_compute_wm0(dev, PIPE_B,
1402                             &g4x_wm_info, pessimal_latency_ns,
1403                             &g4x_cursor_wm_info, pessimal_latency_ns,
1404                             &planeb_wm, &cursorb_wm))
1405                 enabled |= 1 << PIPE_B;
1406
1407         if (single_plane_enabled(enabled) &&
1408             g4x_compute_srwm(dev, ffs(enabled) - 1,
1409                              sr_latency_ns,
1410                              &g4x_wm_info,
1411                              &g4x_cursor_wm_info,
1412                              &plane_sr, &cursor_sr)) {
1413                 cxsr_enabled = true;
1414         } else {
1415                 cxsr_enabled = false;
1416                 intel_set_memory_cxsr(dev_priv, false);
1417                 plane_sr = cursor_sr = 0;
1418         }
1419
1420         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1421                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1422                       planea_wm, cursora_wm,
1423                       planeb_wm, cursorb_wm,
1424                       plane_sr, cursor_sr);
1425
1426         I915_WRITE(DSPFW1,
1427                    FW_WM(plane_sr, SR) |
1428                    FW_WM(cursorb_wm, CURSORB) |
1429                    FW_WM(planeb_wm, PLANEB) |
1430                    FW_WM(planea_wm, PLANEA));
1431         I915_WRITE(DSPFW2,
1432                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1433                    FW_WM(cursora_wm, CURSORA));
1434         /* HPLL off in SR has some issues on G4x... disable it */
1435         I915_WRITE(DSPFW3,
1436                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1437                    FW_WM(cursor_sr, CURSOR_SR));
1438
1439         if (cxsr_enabled)
1440                 intel_set_memory_cxsr(dev_priv, true);
1441 }
1442
1443 static void i965_update_wm(struct drm_crtc *unused_crtc)
1444 {
1445         struct drm_device *dev = unused_crtc->dev;
1446         struct drm_i915_private *dev_priv = to_i915(dev);
1447         struct drm_crtc *crtc;
1448         int srwm = 1;
1449         int cursor_sr = 16;
1450         bool cxsr_enabled;
1451
1452         /* Calc sr entries for one plane configs */
1453         crtc = single_enabled_crtc(dev);
1454         if (crtc) {
1455                 /* self-refresh has much higher latency */
1456                 static const int sr_latency_ns = 12000;
1457                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1458                 int clock = adjusted_mode->crtc_clock;
1459                 int htotal = adjusted_mode->crtc_htotal;
1460                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1461                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1462                 unsigned long line_time_us;
1463                 int entries;
1464
1465                 line_time_us = max(htotal * 1000 / clock, 1);
1466
1467                 /* Use ns/us then divide to preserve precision */
1468                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1469                         cpp * hdisplay;
1470                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1471                 srwm = I965_FIFO_SIZE - entries;
1472                 if (srwm < 0)
1473                         srwm = 1;
1474                 srwm &= 0x1ff;
1475                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1476                               entries, srwm);
1477
1478                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1479                         cpp * crtc->cursor->state->crtc_w;
1480                 entries = DIV_ROUND_UP(entries,
1481                                           i965_cursor_wm_info.cacheline_size);
1482                 cursor_sr = i965_cursor_wm_info.fifo_size -
1483                         (entries + i965_cursor_wm_info.guard_size);
1484
1485                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1486                         cursor_sr = i965_cursor_wm_info.max_wm;
1487
1488                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1489                               "cursor %d\n", srwm, cursor_sr);
1490
1491                 cxsr_enabled = true;
1492         } else {
1493                 cxsr_enabled = false;
1494                 /* Turn off self refresh if both pipes are enabled */
1495                 intel_set_memory_cxsr(dev_priv, false);
1496         }
1497
1498         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1499                       srwm);
1500
1501         /* 965 has limitations... */
1502         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1503                    FW_WM(8, CURSORB) |
1504                    FW_WM(8, PLANEB) |
1505                    FW_WM(8, PLANEA));
1506         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1507                    FW_WM(8, PLANEC_OLD));
1508         /* update cursor SR watermark */
1509         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1510
1511         if (cxsr_enabled)
1512                 intel_set_memory_cxsr(dev_priv, true);
1513 }
1514
1515 #undef FW_WM
1516
1517 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1518 {
1519         struct drm_device *dev = unused_crtc->dev;
1520         struct drm_i915_private *dev_priv = to_i915(dev);
1521         const struct intel_watermark_params *wm_info;
1522         uint32_t fwater_lo;
1523         uint32_t fwater_hi;
1524         int cwm, srwm = 1;
1525         int fifo_size;
1526         int planea_wm, planeb_wm;
1527         struct drm_crtc *crtc, *enabled = NULL;
1528
1529         if (IS_I945GM(dev))
1530                 wm_info = &i945_wm_info;
1531         else if (!IS_GEN2(dev))
1532                 wm_info = &i915_wm_info;
1533         else
1534                 wm_info = &i830_a_wm_info;
1535
1536         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1537         crtc = intel_get_crtc_for_plane(dev, 0);
1538         if (intel_crtc_active(crtc)) {
1539                 const struct drm_display_mode *adjusted_mode;
1540                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1541                 if (IS_GEN2(dev))
1542                         cpp = 4;
1543
1544                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1545                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1546                                                wm_info, fifo_size, cpp,
1547                                                pessimal_latency_ns);
1548                 enabled = crtc;
1549         } else {
1550                 planea_wm = fifo_size - wm_info->guard_size;
1551                 if (planea_wm > (long)wm_info->max_wm)
1552                         planea_wm = wm_info->max_wm;
1553         }
1554
1555         if (IS_GEN2(dev))
1556                 wm_info = &i830_bc_wm_info;
1557
1558         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1559         crtc = intel_get_crtc_for_plane(dev, 1);
1560         if (intel_crtc_active(crtc)) {
1561                 const struct drm_display_mode *adjusted_mode;
1562                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1563                 if (IS_GEN2(dev))
1564                         cpp = 4;
1565
1566                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1567                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1568                                                wm_info, fifo_size, cpp,
1569                                                pessimal_latency_ns);
1570                 if (enabled == NULL)
1571                         enabled = crtc;
1572                 else
1573                         enabled = NULL;
1574         } else {
1575                 planeb_wm = fifo_size - wm_info->guard_size;
1576                 if (planeb_wm > (long)wm_info->max_wm)
1577                         planeb_wm = wm_info->max_wm;
1578         }
1579
1580         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
1582         if (IS_I915GM(dev) && enabled) {
1583                 struct drm_i915_gem_object *obj;
1584
1585                 obj = intel_fb_obj(enabled->primary->state->fb);
1586
1587                 /* self-refresh seems busted with untiled */
1588                 if (!i915_gem_object_is_tiled(obj))
1589                         enabled = NULL;
1590         }
1591
1592         /*
1593          * Overlay gets an aggressive default since video jitter is bad.
1594          */
1595         cwm = 2;
1596
1597         /* Play safe and disable self-refresh before adjusting watermarks. */
1598         intel_set_memory_cxsr(dev_priv, false);
1599
1600         /* Calc sr entries for one plane configs */
1601         if (HAS_FW_BLC(dev) && enabled) {
1602                 /* self-refresh has much higher latency */
1603                 static const int sr_latency_ns = 6000;
1604                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1605                 int clock = adjusted_mode->crtc_clock;
1606                 int htotal = adjusted_mode->crtc_htotal;
1607                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1608                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1609                 unsigned long line_time_us;
1610                 int entries;
1611
1612                 if (IS_I915GM(dev) || IS_I945GM(dev))
1613                         cpp = 4;
1614
1615                 line_time_us = max(htotal * 1000 / clock, 1);
1616
1617                 /* Use ns/us then divide to preserve precision */
1618                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1619                         cpp * hdisplay;
1620                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1621                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1622                 srwm = wm_info->fifo_size - entries;
1623                 if (srwm < 0)
1624                         srwm = 1;
1625
1626                 if (IS_I945G(dev) || IS_I945GM(dev))
1627                         I915_WRITE(FW_BLC_SELF,
1628                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1629                 else
1630                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1631         }
1632
1633         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1634                       planea_wm, planeb_wm, cwm, srwm);
1635
1636         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1637         fwater_hi = (cwm & 0x1f);
1638
1639         /* Set request length to 8 cachelines per fetch */
1640         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1641         fwater_hi = fwater_hi | (1 << 8);
1642
1643         I915_WRITE(FW_BLC, fwater_lo);
1644         I915_WRITE(FW_BLC2, fwater_hi);
1645
1646         if (enabled)
1647                 intel_set_memory_cxsr(dev_priv, true);
1648 }
1649
1650 static void i845_update_wm(struct drm_crtc *unused_crtc)
1651 {
1652         struct drm_device *dev = unused_crtc->dev;
1653         struct drm_i915_private *dev_priv = to_i915(dev);
1654         struct drm_crtc *crtc;
1655         const struct drm_display_mode *adjusted_mode;
1656         uint32_t fwater_lo;
1657         int planea_wm;
1658
1659         crtc = single_enabled_crtc(dev);
1660         if (crtc == NULL)
1661                 return;
1662
1663         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1664         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1665                                        &i845_wm_info,
1666                                        dev_priv->display.get_fifo_size(dev, 0),
1667                                        4, pessimal_latency_ns);
1668         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1669         fwater_lo |= (3<<8) | planea_wm;
1670
1671         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1672
1673         I915_WRITE(FW_BLC, fwater_lo);
1674 }
1675
1676 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1677 {
1678         uint32_t pixel_rate;
1679
1680         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1681
1682         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1683          * adjust the pixel_rate here. */
1684
1685         if (pipe_config->pch_pfit.enabled) {
1686                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1687                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1688
1689                 pipe_w = pipe_config->pipe_src_w;
1690                 pipe_h = pipe_config->pipe_src_h;
1691
1692                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1693                 pfit_h = pfit_size & 0xFFFF;
1694                 if (pipe_w < pfit_w)
1695                         pipe_w = pfit_w;
1696                 if (pipe_h < pfit_h)
1697                         pipe_h = pfit_h;
1698
1699                 if (WARN_ON(!pfit_w || !pfit_h))
1700                         return pixel_rate;
1701
1702                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1703                                      pfit_w * pfit_h);
1704         }
1705
1706         return pixel_rate;
1707 }
1708
1709 /* latency must be in 0.1us units. */
1710 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1711 {
1712         uint64_t ret;
1713
1714         if (WARN(latency == 0, "Latency value missing\n"))
1715                 return UINT_MAX;
1716
1717         ret = (uint64_t) pixel_rate * cpp * latency;
1718         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1719
1720         return ret;
1721 }
1722
1723 /* latency must be in 0.1us units. */
1724 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1725                                uint32_t horiz_pixels, uint8_t cpp,
1726                                uint32_t latency)
1727 {
1728         uint32_t ret;
1729
1730         if (WARN(latency == 0, "Latency value missing\n"))
1731                 return UINT_MAX;
1732         if (WARN_ON(!pipe_htotal))
1733                 return UINT_MAX;
1734
1735         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1736         ret = (ret + 1) * horiz_pixels * cpp;
1737         ret = DIV_ROUND_UP(ret, 64) + 2;
1738         return ret;
1739 }
1740
1741 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1742                            uint8_t cpp)
1743 {
1744         /*
1745          * Neither of these should be possible since this function shouldn't be
1746          * called if the CRTC is off or the plane is invisible.  But let's be
1747          * extra paranoid to avoid a potential divide-by-zero if we screw up
1748          * elsewhere in the driver.
1749          */
1750         if (WARN_ON(!cpp))
1751                 return 0;
1752         if (WARN_ON(!horiz_pixels))
1753                 return 0;
1754
1755         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1756 }
1757
1758 struct ilk_wm_maximums {
1759         uint16_t pri;
1760         uint16_t spr;
1761         uint16_t cur;
1762         uint16_t fbc;
1763 };
1764
1765 /*
1766  * For both WM_PIPE and WM_LP.
1767  * mem_value must be in 0.1us units.
1768  */
1769 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1770                                    const struct intel_plane_state *pstate,
1771                                    uint32_t mem_value,
1772                                    bool is_lp)
1773 {
1774         int cpp = pstate->base.fb ?
1775                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1776         uint32_t method1, method2;
1777
1778         if (!cstate->base.active || !pstate->base.visible)
1779                 return 0;
1780
1781         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1782
1783         if (!is_lp)
1784                 return method1;
1785
1786         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787                                  cstate->base.adjusted_mode.crtc_htotal,
1788                                  drm_rect_width(&pstate->base.dst),
1789                                  cpp, mem_value);
1790
1791         return min(method1, method2);
1792 }
1793
1794 /*
1795  * For both WM_PIPE and WM_LP.
1796  * mem_value must be in 0.1us units.
1797  */
1798 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1799                                    const struct intel_plane_state *pstate,
1800                                    uint32_t mem_value)
1801 {
1802         int cpp = pstate->base.fb ?
1803                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1804         uint32_t method1, method2;
1805
1806         if (!cstate->base.active || !pstate->base.visible)
1807                 return 0;
1808
1809         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1810         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1811                                  cstate->base.adjusted_mode.crtc_htotal,
1812                                  drm_rect_width(&pstate->base.dst),
1813                                  cpp, mem_value);
1814         return min(method1, method2);
1815 }
1816
1817 /*
1818  * For both WM_PIPE and WM_LP.
1819  * mem_value must be in 0.1us units.
1820  */
1821 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1822                                    const struct intel_plane_state *pstate,
1823                                    uint32_t mem_value)
1824 {
1825         /*
1826          * We treat the cursor plane as always-on for the purposes of watermark
1827          * calculation.  Until we have two-stage watermark programming merged,
1828          * this is necessary to avoid flickering.
1829          */
1830         int cpp = 4;
1831         int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1832
1833         if (!cstate->base.active)
1834                 return 0;
1835
1836         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837                               cstate->base.adjusted_mode.crtc_htotal,
1838                               width, cpp, mem_value);
1839 }
1840
1841 /* Only for WM_LP. */
1842 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1843                                    const struct intel_plane_state *pstate,
1844                                    uint32_t pri_val)
1845 {
1846         int cpp = pstate->base.fb ?
1847                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1848
1849         if (!cstate->base.active || !pstate->base.visible)
1850                 return 0;
1851
1852         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1853 }
1854
1855 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1856 {
1857         if (INTEL_INFO(dev)->gen >= 8)
1858                 return 3072;
1859         else if (INTEL_INFO(dev)->gen >= 7)
1860                 return 768;
1861         else
1862                 return 512;
1863 }
1864
1865 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1866                                          int level, bool is_sprite)
1867 {
1868         if (INTEL_INFO(dev)->gen >= 8)
1869                 /* BDW primary/sprite plane watermarks */
1870                 return level == 0 ? 255 : 2047;
1871         else if (INTEL_INFO(dev)->gen >= 7)
1872                 /* IVB/HSW primary/sprite plane watermarks */
1873                 return level == 0 ? 127 : 1023;
1874         else if (!is_sprite)
1875                 /* ILK/SNB primary plane watermarks */
1876                 return level == 0 ? 127 : 511;
1877         else
1878                 /* ILK/SNB sprite plane watermarks */
1879                 return level == 0 ? 63 : 255;
1880 }
1881
1882 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1883                                           int level)
1884 {
1885         if (INTEL_INFO(dev)->gen >= 7)
1886                 return level == 0 ? 63 : 255;
1887         else
1888                 return level == 0 ? 31 : 63;
1889 }
1890
1891 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1892 {
1893         if (INTEL_INFO(dev)->gen >= 8)
1894                 return 31;
1895         else
1896                 return 15;
1897 }
1898
1899 /* Calculate the maximum primary/sprite plane watermark */
1900 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1901                                      int level,
1902                                      const struct intel_wm_config *config,
1903                                      enum intel_ddb_partitioning ddb_partitioning,
1904                                      bool is_sprite)
1905 {
1906         unsigned int fifo_size = ilk_display_fifo_size(dev);
1907
1908         /* if sprites aren't enabled, sprites get nothing */
1909         if (is_sprite && !config->sprites_enabled)
1910                 return 0;
1911
1912         /* HSW allows LP1+ watermarks even with multiple pipes */
1913         if (level == 0 || config->num_pipes_active > 1) {
1914                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1915
1916                 /*
1917                  * For some reason the non self refresh
1918                  * FIFO size is only half of the self
1919                  * refresh FIFO size on ILK/SNB.
1920                  */
1921                 if (INTEL_INFO(dev)->gen <= 6)
1922                         fifo_size /= 2;
1923         }
1924
1925         if (config->sprites_enabled) {
1926                 /* level 0 is always calculated with 1:1 split */
1927                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1928                         if (is_sprite)
1929                                 fifo_size *= 5;
1930                         fifo_size /= 6;
1931                 } else {
1932                         fifo_size /= 2;
1933                 }
1934         }
1935
1936         /* clamp to max that the registers can hold */
1937         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1938 }
1939
1940 /* Calculate the maximum cursor plane watermark */
1941 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1942                                       int level,
1943                                       const struct intel_wm_config *config)
1944 {
1945         /* HSW LP1+ watermarks w/ multiple pipes */
1946         if (level > 0 && config->num_pipes_active > 1)
1947                 return 64;
1948
1949         /* otherwise just report max that registers can hold */
1950         return ilk_cursor_wm_reg_max(dev, level);
1951 }
1952
1953 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1954                                     int level,
1955                                     const struct intel_wm_config *config,
1956                                     enum intel_ddb_partitioning ddb_partitioning,
1957                                     struct ilk_wm_maximums *max)
1958 {
1959         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1960         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1961         max->cur = ilk_cursor_wm_max(dev, level, config);
1962         max->fbc = ilk_fbc_wm_reg_max(dev);
1963 }
1964
1965 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1966                                         int level,
1967                                         struct ilk_wm_maximums *max)
1968 {
1969         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1970         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1971         max->cur = ilk_cursor_wm_reg_max(dev, level);
1972         max->fbc = ilk_fbc_wm_reg_max(dev);
1973 }
1974
1975 static bool ilk_validate_wm_level(int level,
1976                                   const struct ilk_wm_maximums *max,
1977                                   struct intel_wm_level *result)
1978 {
1979         bool ret;
1980
1981         /* already determined to be invalid? */
1982         if (!result->enable)
1983                 return false;
1984
1985         result->enable = result->pri_val <= max->pri &&
1986                          result->spr_val <= max->spr &&
1987                          result->cur_val <= max->cur;
1988
1989         ret = result->enable;
1990
1991         /*
1992          * HACK until we can pre-compute everything,
1993          * and thus fail gracefully if LP0 watermarks
1994          * are exceeded...
1995          */
1996         if (level == 0 && !result->enable) {
1997                 if (result->pri_val > max->pri)
1998                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1999                                       level, result->pri_val, max->pri);
2000                 if (result->spr_val > max->spr)
2001                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2002                                       level, result->spr_val, max->spr);
2003                 if (result->cur_val > max->cur)
2004                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2005                                       level, result->cur_val, max->cur);
2006
2007                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2008                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2009                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2010                 result->enable = true;
2011         }
2012
2013         return ret;
2014 }
2015
2016 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2017                                  const struct intel_crtc *intel_crtc,
2018                                  int level,
2019                                  struct intel_crtc_state *cstate,
2020                                  struct intel_plane_state *pristate,
2021                                  struct intel_plane_state *sprstate,
2022                                  struct intel_plane_state *curstate,
2023                                  struct intel_wm_level *result)
2024 {
2025         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029         /* WM1+ latency values stored in 0.5us units */
2030         if (level > 0) {
2031                 pri_latency *= 5;
2032                 spr_latency *= 5;
2033                 cur_latency *= 5;
2034         }
2035
2036         if (pristate) {
2037                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2038                                                      pri_latency, level);
2039                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2040         }
2041
2042         if (sprstate)
2043                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044
2045         if (curstate)
2046                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2047
2048         result->enable = true;
2049 }
2050
2051 static uint32_t
2052 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2053 {
2054         const struct intel_atomic_state *intel_state =
2055                 to_intel_atomic_state(cstate->base.state);
2056         const struct drm_display_mode *adjusted_mode =
2057                 &cstate->base.adjusted_mode;
2058         u32 linetime, ips_linetime;
2059
2060         if (!cstate->base.active)
2061                 return 0;
2062         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2063                 return 0;
2064         if (WARN_ON(intel_state->cdclk == 0))
2065                 return 0;
2066
2067         /* The WM are computed with base on how long it takes to fill a single
2068          * row at the given clock rate, multiplied by 8.
2069          * */
2070         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2071                                      adjusted_mode->crtc_clock);
2072         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2073                                          intel_state->cdclk);
2074
2075         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2076                PIPE_WM_LINETIME_TIME(linetime);
2077 }
2078
2079 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2080 {
2081         struct drm_i915_private *dev_priv = to_i915(dev);
2082
2083         if (IS_GEN9(dev)) {
2084                 uint32_t val;
2085                 int ret, i;
2086                 int level, max_level = ilk_wm_max_level(dev);
2087
2088                 /* read the first set of memory latencies[0:3] */
2089                 val = 0; /* data0 to be programmed to 0 for first set */
2090                 mutex_lock(&dev_priv->rps.hw_lock);
2091                 ret = sandybridge_pcode_read(dev_priv,
2092                                              GEN9_PCODE_READ_MEM_LATENCY,
2093                                              &val);
2094                 mutex_unlock(&dev_priv->rps.hw_lock);
2095
2096                 if (ret) {
2097                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2098                         return;
2099                 }
2100
2101                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2102                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2103                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2104                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2105                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2106                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2107                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2108
2109                 /* read the second set of memory latencies[4:7] */
2110                 val = 1; /* data0 to be programmed to 1 for second set */
2111                 mutex_lock(&dev_priv->rps.hw_lock);
2112                 ret = sandybridge_pcode_read(dev_priv,
2113                                              GEN9_PCODE_READ_MEM_LATENCY,
2114                                              &val);
2115                 mutex_unlock(&dev_priv->rps.hw_lock);
2116                 if (ret) {
2117                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2118                         return;
2119                 }
2120
2121                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2122                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2123                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2124                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2125                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2126                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2127                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2128
2129                 /*
2130                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2131                  * need to be disabled. We make sure to sanitize the values out
2132                  * of the punit to satisfy this requirement.
2133                  */
2134                 for (level = 1; level <= max_level; level++) {
2135                         if (wm[level] == 0) {
2136                                 for (i = level + 1; i <= max_level; i++)
2137                                         wm[i] = 0;
2138                                 break;
2139                         }
2140                 }
2141
2142                 /*
2143                  * WaWmMemoryReadLatency:skl
2144                  *
2145                  * punit doesn't take into account the read latency so we need
2146                  * to add 2us to the various latency levels we retrieve from the
2147                  * punit when level 0 response data us 0us.
2148                  */
2149                 if (wm[0] == 0) {
2150                         wm[0] += 2;
2151                         for (level = 1; level <= max_level; level++) {
2152                                 if (wm[level] == 0)
2153                                         break;
2154                                 wm[level] += 2;
2155                         }
2156                 }
2157
2158         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2159                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2160
2161                 wm[0] = (sskpd >> 56) & 0xFF;
2162                 if (wm[0] == 0)
2163                         wm[0] = sskpd & 0xF;
2164                 wm[1] = (sskpd >> 4) & 0xFF;
2165                 wm[2] = (sskpd >> 12) & 0xFF;
2166                 wm[3] = (sskpd >> 20) & 0x1FF;
2167                 wm[4] = (sskpd >> 32) & 0x1FF;
2168         } else if (INTEL_INFO(dev)->gen >= 6) {
2169                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2170
2171                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2172                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2173                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2174                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2175         } else if (INTEL_INFO(dev)->gen >= 5) {
2176                 uint32_t mltr = I915_READ(MLTR_ILK);
2177
2178                 /* ILK primary LP0 latency is 700 ns */
2179                 wm[0] = 7;
2180                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2181                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2182         }
2183 }
2184
2185 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2186 {
2187         /* ILK sprite LP0 latency is 1300 ns */
2188         if (IS_GEN5(dev))
2189                 wm[0] = 13;
2190 }
2191
2192 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2193 {
2194         /* ILK cursor LP0 latency is 1300 ns */
2195         if (IS_GEN5(dev))
2196                 wm[0] = 13;
2197
2198         /* WaDoubleCursorLP3Latency:ivb */
2199         if (IS_IVYBRIDGE(dev))
2200                 wm[3] *= 2;
2201 }
2202
2203 int ilk_wm_max_level(const struct drm_device *dev)
2204 {
2205         /* how many WM levels are we expecting */
2206         if (INTEL_INFO(dev)->gen >= 9)
2207                 return 7;
2208         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2209                 return 4;
2210         else if (INTEL_INFO(dev)->gen >= 6)
2211                 return 3;
2212         else
2213                 return 2;
2214 }
2215
2216 static void intel_print_wm_latency(struct drm_device *dev,
2217                                    const char *name,
2218                                    const uint16_t wm[8])
2219 {
2220         int level, max_level = ilk_wm_max_level(dev);
2221
2222         for (level = 0; level <= max_level; level++) {
2223                 unsigned int latency = wm[level];
2224
2225                 if (latency == 0) {
2226                         DRM_ERROR("%s WM%d latency not provided\n",
2227                                   name, level);
2228                         continue;
2229                 }
2230
2231                 /*
2232                  * - latencies are in us on gen9.
2233                  * - before then, WM1+ latency values are in 0.5us units
2234                  */
2235                 if (IS_GEN9(dev))
2236                         latency *= 10;
2237                 else if (level > 0)
2238                         latency *= 5;
2239
2240                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2241                               name, level, wm[level],
2242                               latency / 10, latency % 10);
2243         }
2244 }
2245
2246 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2247                                     uint16_t wm[5], uint16_t min)
2248 {
2249         int level, max_level = ilk_wm_max_level(&dev_priv->drm);
2250
2251         if (wm[0] >= min)
2252                 return false;
2253
2254         wm[0] = max(wm[0], min);
2255         for (level = 1; level <= max_level; level++)
2256                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2257
2258         return true;
2259 }
2260
2261 static void snb_wm_latency_quirk(struct drm_device *dev)
2262 {
2263         struct drm_i915_private *dev_priv = to_i915(dev);
2264         bool changed;
2265
2266         /*
2267          * The BIOS provided WM memory latency values are often
2268          * inadequate for high resolution displays. Adjust them.
2269          */
2270         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2271                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2272                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2273
2274         if (!changed)
2275                 return;
2276
2277         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2278         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2279         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2280         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2281 }
2282
2283 static void ilk_setup_wm_latency(struct drm_device *dev)
2284 {
2285         struct drm_i915_private *dev_priv = to_i915(dev);
2286
2287         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2288
2289         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2290                sizeof(dev_priv->wm.pri_latency));
2291         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2292                sizeof(dev_priv->wm.pri_latency));
2293
2294         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2295         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2296
2297         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2298         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2299         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2300
2301         if (IS_GEN6(dev))
2302                 snb_wm_latency_quirk(dev);
2303 }
2304
2305 static void skl_setup_wm_latency(struct drm_device *dev)
2306 {
2307         struct drm_i915_private *dev_priv = to_i915(dev);
2308
2309         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2310         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2311 }
2312
2313 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2314                                  struct intel_pipe_wm *pipe_wm)
2315 {
2316         /* LP0 watermark maximums depend on this pipe alone */
2317         const struct intel_wm_config config = {
2318                 .num_pipes_active = 1,
2319                 .sprites_enabled = pipe_wm->sprites_enabled,
2320                 .sprites_scaled = pipe_wm->sprites_scaled,
2321         };
2322         struct ilk_wm_maximums max;
2323
2324         /* LP0 watermarks always use 1/2 DDB partitioning */
2325         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2326
2327         /* At least LP0 must be valid */
2328         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2329                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2330                 return false;
2331         }
2332
2333         return true;
2334 }
2335
2336 /* Compute new watermarks for the pipe */
2337 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2338 {
2339         struct drm_atomic_state *state = cstate->base.state;
2340         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2341         struct intel_pipe_wm *pipe_wm;
2342         struct drm_device *dev = state->dev;
2343         const struct drm_i915_private *dev_priv = to_i915(dev);
2344         struct intel_plane *intel_plane;
2345         struct intel_plane_state *pristate = NULL;
2346         struct intel_plane_state *sprstate = NULL;
2347         struct intel_plane_state *curstate = NULL;
2348         int level, max_level = ilk_wm_max_level(dev), usable_level;
2349         struct ilk_wm_maximums max;
2350
2351         pipe_wm = &cstate->wm.ilk.optimal;
2352
2353         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2354                 struct intel_plane_state *ps;
2355
2356                 ps = intel_atomic_get_existing_plane_state(state,
2357                                                            intel_plane);
2358                 if (!ps)
2359                         continue;
2360
2361                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2362                         pristate = ps;
2363                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2364                         sprstate = ps;
2365                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2366                         curstate = ps;
2367         }
2368
2369         pipe_wm->pipe_enabled = cstate->base.active;
2370         if (sprstate) {
2371                 pipe_wm->sprites_enabled = sprstate->base.visible;
2372                 pipe_wm->sprites_scaled = sprstate->base.visible &&
2373                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2374                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2375         }
2376
2377         usable_level = max_level;
2378
2379         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2380         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2381                 usable_level = 1;
2382
2383         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2384         if (pipe_wm->sprites_scaled)
2385                 usable_level = 0;
2386
2387         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2388                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2389
2390         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2391         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2392
2393         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2394                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2395
2396         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2397                 return -EINVAL;
2398
2399         ilk_compute_wm_reg_maximums(dev, 1, &max);
2400
2401         for (level = 1; level <= max_level; level++) {
2402                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2403
2404                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2405                                      pristate, sprstate, curstate, wm);
2406
2407                 /*
2408                  * Disable any watermark level that exceeds the
2409                  * register maximums since such watermarks are
2410                  * always invalid.
2411                  */
2412                 if (level > usable_level)
2413                         continue;
2414
2415                 if (ilk_validate_wm_level(level, &max, wm))
2416                         pipe_wm->wm[level] = *wm;
2417                 else
2418                         usable_level = level;
2419         }
2420
2421         return 0;
2422 }
2423
2424 /*
2425  * Build a set of 'intermediate' watermark values that satisfy both the old
2426  * state and the new state.  These can be programmed to the hardware
2427  * immediately.
2428  */
2429 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2430                                        struct intel_crtc *intel_crtc,
2431                                        struct intel_crtc_state *newstate)
2432 {
2433         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2434         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2435         int level, max_level = ilk_wm_max_level(dev);
2436
2437         /*
2438          * Start with the final, target watermarks, then combine with the
2439          * currently active watermarks to get values that are safe both before
2440          * and after the vblank.
2441          */
2442         *a = newstate->wm.ilk.optimal;
2443         a->pipe_enabled |= b->pipe_enabled;
2444         a->sprites_enabled |= b->sprites_enabled;
2445         a->sprites_scaled |= b->sprites_scaled;
2446
2447         for (level = 0; level <= max_level; level++) {
2448                 struct intel_wm_level *a_wm = &a->wm[level];
2449                 const struct intel_wm_level *b_wm = &b->wm[level];
2450
2451                 a_wm->enable &= b_wm->enable;
2452                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2453                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2454                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2455                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2456         }
2457
2458         /*
2459          * We need to make sure that these merged watermark values are
2460          * actually a valid configuration themselves.  If they're not,
2461          * there's no safe way to transition from the old state to
2462          * the new state, so we need to fail the atomic transaction.
2463          */
2464         if (!ilk_validate_pipe_wm(dev, a))
2465                 return -EINVAL;
2466
2467         /*
2468          * If our intermediate WM are identical to the final WM, then we can
2469          * omit the post-vblank programming; only update if it's different.
2470          */
2471         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2472                 newstate->wm.need_postvbl_update = false;
2473
2474         return 0;
2475 }
2476
2477 /*
2478  * Merge the watermarks from all active pipes for a specific level.
2479  */
2480 static void ilk_merge_wm_level(struct drm_device *dev,
2481                                int level,
2482                                struct intel_wm_level *ret_wm)
2483 {
2484         const struct intel_crtc *intel_crtc;
2485
2486         ret_wm->enable = true;
2487
2488         for_each_intel_crtc(dev, intel_crtc) {
2489                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2490                 const struct intel_wm_level *wm = &active->wm[level];
2491
2492                 if (!active->pipe_enabled)
2493                         continue;
2494
2495                 /*
2496                  * The watermark values may have been used in the past,
2497                  * so we must maintain them in the registers for some
2498                  * time even if the level is now disabled.
2499                  */
2500                 if (!wm->enable)
2501                         ret_wm->enable = false;
2502
2503                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2504                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2505                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2506                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2507         }
2508 }
2509
2510 /*
2511  * Merge all low power watermarks for all active pipes.
2512  */
2513 static void ilk_wm_merge(struct drm_device *dev,
2514                          const struct intel_wm_config *config,
2515                          const struct ilk_wm_maximums *max,
2516                          struct intel_pipe_wm *merged)
2517 {
2518         struct drm_i915_private *dev_priv = to_i915(dev);
2519         int level, max_level = ilk_wm_max_level(dev);
2520         int last_enabled_level = max_level;
2521
2522         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2523         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2524             config->num_pipes_active > 1)
2525                 last_enabled_level = 0;
2526
2527         /* ILK: FBC WM must be disabled always */
2528         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2529
2530         /* merge each WM1+ level */
2531         for (level = 1; level <= max_level; level++) {
2532                 struct intel_wm_level *wm = &merged->wm[level];
2533
2534                 ilk_merge_wm_level(dev, level, wm);
2535
2536                 if (level > last_enabled_level)
2537                         wm->enable = false;
2538                 else if (!ilk_validate_wm_level(level, max, wm))
2539                         /* make sure all following levels get disabled */
2540                         last_enabled_level = level - 1;
2541
2542                 /*
2543                  * The spec says it is preferred to disable
2544                  * FBC WMs instead of disabling a WM level.
2545                  */
2546                 if (wm->fbc_val > max->fbc) {
2547                         if (wm->enable)
2548                                 merged->fbc_wm_enabled = false;
2549                         wm->fbc_val = 0;
2550                 }
2551         }
2552
2553         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2554         /*
2555          * FIXME this is racy. FBC might get enabled later.
2556          * What we should check here is whether FBC can be
2557          * enabled sometime later.
2558          */
2559         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2560             intel_fbc_is_active(dev_priv)) {
2561                 for (level = 2; level <= max_level; level++) {
2562                         struct intel_wm_level *wm = &merged->wm[level];
2563
2564                         wm->enable = false;
2565                 }
2566         }
2567 }
2568
2569 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2570 {
2571         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2572         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2573 }
2574
2575 /* The value we need to program into the WM_LPx latency field */
2576 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2577 {
2578         struct drm_i915_private *dev_priv = to_i915(dev);
2579
2580         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2581                 return 2 * level;
2582         else
2583                 return dev_priv->wm.pri_latency[level];
2584 }
2585
2586 static void ilk_compute_wm_results(struct drm_device *dev,
2587                                    const struct intel_pipe_wm *merged,
2588                                    enum intel_ddb_partitioning partitioning,
2589                                    struct ilk_wm_values *results)
2590 {
2591         struct intel_crtc *intel_crtc;
2592         int level, wm_lp;
2593
2594         results->enable_fbc_wm = merged->fbc_wm_enabled;
2595         results->partitioning = partitioning;
2596
2597         /* LP1+ register values */
2598         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2599                 const struct intel_wm_level *r;
2600
2601                 level = ilk_wm_lp_to_level(wm_lp, merged);
2602
2603                 r = &merged->wm[level];
2604
2605                 /*
2606                  * Maintain the watermark values even if the level is
2607                  * disabled. Doing otherwise could cause underruns.
2608                  */
2609                 results->wm_lp[wm_lp - 1] =
2610                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2611                         (r->pri_val << WM1_LP_SR_SHIFT) |
2612                         r->cur_val;
2613
2614                 if (r->enable)
2615                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2616
2617                 if (INTEL_INFO(dev)->gen >= 8)
2618                         results->wm_lp[wm_lp - 1] |=
2619                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2620                 else
2621                         results->wm_lp[wm_lp - 1] |=
2622                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2623
2624                 /*
2625                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2626                  * level is disabled. Doing otherwise could cause underruns.
2627                  */
2628                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2629                         WARN_ON(wm_lp != 1);
2630                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2631                 } else
2632                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2633         }
2634
2635         /* LP0 register values */
2636         for_each_intel_crtc(dev, intel_crtc) {
2637                 enum pipe pipe = intel_crtc->pipe;
2638                 const struct intel_wm_level *r =
2639                         &intel_crtc->wm.active.ilk.wm[0];
2640
2641                 if (WARN_ON(!r->enable))
2642                         continue;
2643
2644                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2645
2646                 results->wm_pipe[pipe] =
2647                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2648                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2649                         r->cur_val;
2650         }
2651 }
2652
2653 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2654  * case both are at the same level. Prefer r1 in case they're the same. */
2655 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2656                                                   struct intel_pipe_wm *r1,
2657                                                   struct intel_pipe_wm *r2)
2658 {
2659         int level, max_level = ilk_wm_max_level(dev);
2660         int level1 = 0, level2 = 0;
2661
2662         for (level = 1; level <= max_level; level++) {
2663                 if (r1->wm[level].enable)
2664                         level1 = level;
2665                 if (r2->wm[level].enable)
2666                         level2 = level;
2667         }
2668
2669         if (level1 == level2) {
2670                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2671                         return r2;
2672                 else
2673                         return r1;
2674         } else if (level1 > level2) {
2675                 return r1;
2676         } else {
2677                 return r2;
2678         }
2679 }
2680
2681 /* dirty bits used to track which watermarks need changes */
2682 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2683 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2684 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2685 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2686 #define WM_DIRTY_FBC (1 << 24)
2687 #define WM_DIRTY_DDB (1 << 25)
2688
2689 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2690                                          const struct ilk_wm_values *old,
2691                                          const struct ilk_wm_values *new)
2692 {
2693         unsigned int dirty = 0;
2694         enum pipe pipe;
2695         int wm_lp;
2696
2697         for_each_pipe(dev_priv, pipe) {
2698                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2699                         dirty |= WM_DIRTY_LINETIME(pipe);
2700                         /* Must disable LP1+ watermarks too */
2701                         dirty |= WM_DIRTY_LP_ALL;
2702                 }
2703
2704                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2705                         dirty |= WM_DIRTY_PIPE(pipe);
2706                         /* Must disable LP1+ watermarks too */
2707                         dirty |= WM_DIRTY_LP_ALL;
2708                 }
2709         }
2710
2711         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2712                 dirty |= WM_DIRTY_FBC;
2713                 /* Must disable LP1+ watermarks too */
2714                 dirty |= WM_DIRTY_LP_ALL;
2715         }
2716
2717         if (old->partitioning != new->partitioning) {
2718                 dirty |= WM_DIRTY_DDB;
2719                 /* Must disable LP1+ watermarks too */
2720                 dirty |= WM_DIRTY_LP_ALL;
2721         }
2722
2723         /* LP1+ watermarks already deemed dirty, no need to continue */
2724         if (dirty & WM_DIRTY_LP_ALL)
2725                 return dirty;
2726
2727         /* Find the lowest numbered LP1+ watermark in need of an update... */
2728         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2729                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2730                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2731                         break;
2732         }
2733
2734         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2735         for (; wm_lp <= 3; wm_lp++)
2736                 dirty |= WM_DIRTY_LP(wm_lp);
2737
2738         return dirty;
2739 }
2740
2741 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2742                                unsigned int dirty)
2743 {
2744         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2745         bool changed = false;
2746
2747         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2748                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2749                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2750                 changed = true;
2751         }
2752         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2753                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2754                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2755                 changed = true;
2756         }
2757         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2758                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2759                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2760                 changed = true;
2761         }
2762
2763         /*
2764          * Don't touch WM1S_LP_EN here.
2765          * Doing so could cause underruns.
2766          */
2767
2768         return changed;
2769 }
2770
2771 /*
2772  * The spec says we shouldn't write when we don't need, because every write
2773  * causes WMs to be re-evaluated, expending some power.
2774  */
2775 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2776                                 struct ilk_wm_values *results)
2777 {
2778         struct drm_device *dev = &dev_priv->drm;
2779         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2780         unsigned int dirty;
2781         uint32_t val;
2782
2783         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2784         if (!dirty)
2785                 return;
2786
2787         _ilk_disable_lp_wm(dev_priv, dirty);
2788
2789         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2790                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2791         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2792                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2793         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2794                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2795
2796         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2797                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2798         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2799                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2800         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2801                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2802
2803         if (dirty & WM_DIRTY_DDB) {
2804                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2805                         val = I915_READ(WM_MISC);
2806                         if (results->partitioning == INTEL_DDB_PART_1_2)
2807                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2808                         else
2809                                 val |= WM_MISC_DATA_PARTITION_5_6;
2810                         I915_WRITE(WM_MISC, val);
2811                 } else {
2812                         val = I915_READ(DISP_ARB_CTL2);
2813                         if (results->partitioning == INTEL_DDB_PART_1_2)
2814                                 val &= ~DISP_DATA_PARTITION_5_6;
2815                         else
2816                                 val |= DISP_DATA_PARTITION_5_6;
2817                         I915_WRITE(DISP_ARB_CTL2, val);
2818                 }
2819         }
2820
2821         if (dirty & WM_DIRTY_FBC) {
2822                 val = I915_READ(DISP_ARB_CTL);
2823                 if (results->enable_fbc_wm)
2824                         val &= ~DISP_FBC_WM_DIS;
2825                 else
2826                         val |= DISP_FBC_WM_DIS;
2827                 I915_WRITE(DISP_ARB_CTL, val);
2828         }
2829
2830         if (dirty & WM_DIRTY_LP(1) &&
2831             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2832                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2833
2834         if (INTEL_INFO(dev)->gen >= 7) {
2835                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2836                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2837                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2838                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2839         }
2840
2841         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2842                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2843         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2844                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2845         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2846                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2847
2848         dev_priv->wm.hw = *results;
2849 }
2850
2851 bool ilk_disable_lp_wm(struct drm_device *dev)
2852 {
2853         struct drm_i915_private *dev_priv = to_i915(dev);
2854
2855         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2856 }
2857
2858 #define SKL_SAGV_BLOCK_TIME     30 /* µs */
2859
2860 /*
2861  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2862  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2863  * other universal planes are in indices 1..n.  Note that this may leave unused
2864  * indices between the top "sprite" plane and the cursor.
2865  */
2866 static int
2867 skl_wm_plane_id(const struct intel_plane *plane)
2868 {
2869         switch (plane->base.type) {
2870         case DRM_PLANE_TYPE_PRIMARY:
2871                 return 0;
2872         case DRM_PLANE_TYPE_CURSOR:
2873                 return PLANE_CURSOR;
2874         case DRM_PLANE_TYPE_OVERLAY:
2875                 return plane->plane + 1;
2876         default:
2877                 MISSING_CASE(plane->base.type);
2878                 return plane->plane;
2879         }
2880 }
2881
2882 static bool
2883 intel_has_sagv(struct drm_i915_private *dev_priv)
2884 {
2885         if (IS_KABYLAKE(dev_priv))
2886                 return true;
2887
2888         if (IS_SKYLAKE(dev_priv) &&
2889             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2890                 return true;
2891
2892         return false;
2893 }
2894
2895 /*
2896  * SAGV dynamically adjusts the system agent voltage and clock frequencies
2897  * depending on power and performance requirements. The display engine access
2898  * to system memory is blocked during the adjustment time. Because of the
2899  * blocking time, having this enabled can cause full system hangs and/or pipe
2900  * underruns if we don't meet all of the following requirements:
2901  *
2902  *  - <= 1 pipe enabled
2903  *  - All planes can enable watermarks for latencies >= SAGV engine block time
2904  *  - We're not using an interlaced display configuration
2905  */
2906 int
2907 intel_enable_sagv(struct drm_i915_private *dev_priv)
2908 {
2909         int ret;
2910
2911         if (!intel_has_sagv(dev_priv))
2912                 return 0;
2913
2914         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2915                 return 0;
2916
2917         DRM_DEBUG_KMS("Enabling the SAGV\n");
2918         mutex_lock(&dev_priv->rps.hw_lock);
2919
2920         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2921                                       GEN9_SAGV_ENABLE);
2922
2923         /* We don't need to wait for the SAGV when enabling */
2924         mutex_unlock(&dev_priv->rps.hw_lock);
2925
2926         /*
2927          * Some skl systems, pre-release machines in particular,
2928          * don't actually have an SAGV.
2929          */
2930         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2931                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2932                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2933                 return 0;
2934         } else if (ret < 0) {
2935                 DRM_ERROR("Failed to enable the SAGV\n");
2936                 return ret;
2937         }
2938
2939         dev_priv->sagv_status = I915_SAGV_ENABLED;
2940         return 0;
2941 }
2942
2943 static int
2944 intel_do_sagv_disable(struct drm_i915_private *dev_priv)
2945 {
2946         int ret;
2947         uint32_t temp = GEN9_SAGV_DISABLE;
2948
2949         ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2950                                      &temp);
2951         if (ret)
2952                 return ret;
2953         else
2954                 return temp & GEN9_SAGV_IS_DISABLED;
2955 }
2956
2957 int
2958 intel_disable_sagv(struct drm_i915_private *dev_priv)
2959 {
2960         int ret, result;
2961
2962         if (!intel_has_sagv(dev_priv))
2963                 return 0;
2964
2965         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2966                 return 0;
2967
2968         DRM_DEBUG_KMS("Disabling the SAGV\n");
2969         mutex_lock(&dev_priv->rps.hw_lock);
2970
2971         /* bspec says to keep retrying for at least 1 ms */
2972         ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
2973         mutex_unlock(&dev_priv->rps.hw_lock);
2974
2975         if (ret == -ETIMEDOUT) {
2976                 DRM_ERROR("Request to disable SAGV timed out\n");
2977                 return -ETIMEDOUT;
2978         }
2979
2980         /*
2981          * Some skl systems, pre-release machines in particular,
2982          * don't actually have an SAGV.
2983          */
2984         if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
2985                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2986                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2987                 return 0;
2988         } else if (result < 0) {
2989                 DRM_ERROR("Failed to disable the SAGV\n");
2990                 return result;
2991         }
2992
2993         dev_priv->sagv_status = I915_SAGV_DISABLED;
2994         return 0;
2995 }
2996
2997 bool intel_can_enable_sagv(struct drm_atomic_state *state)
2998 {
2999         struct drm_device *dev = state->dev;
3000         struct drm_i915_private *dev_priv = to_i915(dev);
3001         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3002         struct drm_crtc *crtc;
3003         enum pipe pipe;
3004         int level, plane;
3005
3006         if (!intel_has_sagv(dev_priv))
3007                 return false;
3008
3009         /*
3010          * SKL workaround: bspec recommends we disable the SAGV when we have
3011          * more then one pipe enabled
3012          *
3013          * If there are no active CRTCs, no additional checks need be performed
3014          */
3015         if (hweight32(intel_state->active_crtcs) == 0)
3016                 return true;
3017         else if (hweight32(intel_state->active_crtcs) > 1)
3018                 return false;
3019
3020         /* Since we're now guaranteed to only have one active CRTC... */
3021         pipe = ffs(intel_state->active_crtcs) - 1;
3022         crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3023
3024         if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3025                 return false;
3026
3027         for_each_plane(dev_priv, pipe, plane) {
3028                 /* Skip this plane if it's not enabled */
3029                 if (intel_state->wm_results.plane[pipe][plane][0] == 0)
3030                         continue;
3031
3032                 /* Find the highest enabled wm level for this plane */
3033                 for (level = ilk_wm_max_level(dev);
3034                      intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
3035                      { }
3036
3037                 /*
3038                  * If any of the planes on this pipe don't enable wm levels
3039                  * that incur memory latencies higher then 30µs we can't enable
3040                  * the SAGV
3041                  */
3042                 if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
3043                         return false;
3044         }
3045
3046         return true;
3047 }
3048
3049 static void
3050 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3051                                    const struct intel_crtc_state *cstate,
3052                                    struct skl_ddb_entry *alloc, /* out */
3053                                    int *num_active /* out */)
3054 {
3055         struct drm_atomic_state *state = cstate->base.state;
3056         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3057         struct drm_i915_private *dev_priv = to_i915(dev);
3058         struct drm_crtc *for_crtc = cstate->base.crtc;
3059         unsigned int pipe_size, ddb_size;
3060         int nth_active_pipe;
3061         int pipe = to_intel_crtc(for_crtc)->pipe;
3062
3063         if (WARN_ON(!state) || !cstate->base.active) {
3064                 alloc->start = 0;
3065                 alloc->end = 0;
3066                 *num_active = hweight32(dev_priv->active_crtcs);
3067                 return;
3068         }
3069
3070         if (intel_state->active_pipe_changes)
3071                 *num_active = hweight32(intel_state->active_crtcs);
3072         else
3073                 *num_active = hweight32(dev_priv->active_crtcs);
3074
3075         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3076         WARN_ON(ddb_size == 0);
3077
3078         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3079
3080         /*
3081          * If the state doesn't change the active CRTC's, then there's
3082          * no need to recalculate; the existing pipe allocation limits
3083          * should remain unchanged.  Note that we're safe from racing
3084          * commits since any racing commit that changes the active CRTC
3085          * list would need to grab _all_ crtc locks, including the one
3086          * we currently hold.
3087          */
3088         if (!intel_state->active_pipe_changes) {
3089                 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
3090                 return;
3091         }
3092
3093         nth_active_pipe = hweight32(intel_state->active_crtcs &
3094                                     (drm_crtc_mask(for_crtc) - 1));
3095         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3096         alloc->start = nth_active_pipe * ddb_size / *num_active;
3097         alloc->end = alloc->start + pipe_size;
3098 }
3099
3100 static unsigned int skl_cursor_allocation(int num_active)
3101 {
3102         if (num_active == 1)
3103                 return 32;
3104
3105         return 8;
3106 }
3107
3108 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3109 {
3110         entry->start = reg & 0x3ff;
3111         entry->end = (reg >> 16) & 0x3ff;
3112         if (entry->end)
3113                 entry->end += 1;
3114 }
3115
3116 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3117                           struct skl_ddb_allocation *ddb /* out */)
3118 {
3119         enum pipe pipe;
3120         int plane;
3121         u32 val;
3122
3123         memset(ddb, 0, sizeof(*ddb));
3124
3125         for_each_pipe(dev_priv, pipe) {
3126                 enum intel_display_power_domain power_domain;
3127
3128                 power_domain = POWER_DOMAIN_PIPE(pipe);
3129                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3130                         continue;
3131
3132                 for_each_plane(dev_priv, pipe, plane) {
3133                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3134                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3135                                                    val);
3136                 }
3137
3138                 val = I915_READ(CUR_BUF_CFG(pipe));
3139                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3140                                            val);
3141
3142                 intel_display_power_put(dev_priv, power_domain);
3143         }
3144 }
3145
3146 /*
3147  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3148  * The bspec defines downscale amount as:
3149  *
3150  * """
3151  * Horizontal down scale amount = maximum[1, Horizontal source size /
3152  *                                           Horizontal destination size]
3153  * Vertical down scale amount = maximum[1, Vertical source size /
3154  *                                         Vertical destination size]
3155  * Total down scale amount = Horizontal down scale amount *
3156  *                           Vertical down scale amount
3157  * """
3158  *
3159  * Return value is provided in 16.16 fixed point form to retain fractional part.
3160  * Caller should take care of dividing & rounding off the value.
3161  */
3162 static uint32_t
3163 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3164 {
3165         uint32_t downscale_h, downscale_w;
3166         uint32_t src_w, src_h, dst_w, dst_h;
3167
3168         if (WARN_ON(!pstate->base.visible))
3169                 return DRM_PLANE_HELPER_NO_SCALING;
3170
3171         /* n.b., src is 16.16 fixed point, dst is whole integer */
3172         src_w = drm_rect_width(&pstate->base.src);
3173         src_h = drm_rect_height(&pstate->base.src);
3174         dst_w = drm_rect_width(&pstate->base.dst);
3175         dst_h = drm_rect_height(&pstate->base.dst);
3176         if (intel_rotation_90_or_270(pstate->base.rotation))
3177                 swap(dst_w, dst_h);
3178
3179         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3180         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3181
3182         /* Provide result in 16.16 fixed point */
3183         return (uint64_t)downscale_w * downscale_h >> 16;
3184 }
3185
3186 static unsigned int
3187 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3188                              const struct drm_plane_state *pstate,
3189                              int y)
3190 {
3191         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3192         struct drm_framebuffer *fb = pstate->fb;
3193         uint32_t down_scale_amount, data_rate;
3194         uint32_t width = 0, height = 0;
3195         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3196
3197         if (!intel_pstate->base.visible)
3198                 return 0;
3199         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3200                 return 0;
3201         if (y && format != DRM_FORMAT_NV12)
3202                 return 0;
3203
3204         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3205         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3206
3207         if (intel_rotation_90_or_270(pstate->rotation))
3208                 swap(width, height);
3209
3210         /* for planar format */
3211         if (format == DRM_FORMAT_NV12) {
3212                 if (y)  /* y-plane data rate */
3213                         data_rate = width * height *
3214                                 drm_format_plane_cpp(format, 0);
3215                 else    /* uv-plane data rate */
3216                         data_rate = (width / 2) * (height / 2) *
3217                                 drm_format_plane_cpp(format, 1);
3218         } else {
3219                 /* for packed formats */
3220                 data_rate = width * height * drm_format_plane_cpp(format, 0);
3221         }
3222
3223         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3224
3225         return (uint64_t)data_rate * down_scale_amount >> 16;
3226 }
3227
3228 /*
3229  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3230  * a 8192x4096@32bpp framebuffer:
3231  *   3 * 4096 * 8192  * 4 < 2^32
3232  */
3233 static unsigned int
3234 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
3235 {
3236         struct drm_crtc_state *cstate = &intel_cstate->base;
3237         struct drm_atomic_state *state = cstate->state;
3238         struct drm_crtc *crtc = cstate->crtc;
3239         struct drm_device *dev = crtc->dev;
3240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3241         const struct drm_plane *plane;
3242         const struct intel_plane *intel_plane;
3243         struct drm_plane_state *pstate;
3244         unsigned int rate, total_data_rate = 0;
3245         int id;
3246         int i;
3247
3248         if (WARN_ON(!state))
3249                 return 0;
3250
3251         /* Calculate and cache data rate for each plane */
3252         for_each_plane_in_state(state, plane, pstate, i) {
3253                 id = skl_wm_plane_id(to_intel_plane(plane));
3254                 intel_plane = to_intel_plane(plane);
3255
3256                 if (intel_plane->pipe != intel_crtc->pipe)
3257                         continue;
3258
3259                 /* packed/uv */
3260                 rate = skl_plane_relative_data_rate(intel_cstate,
3261                                                     pstate, 0);
3262                 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3263
3264                 /* y-plane */
3265                 rate = skl_plane_relative_data_rate(intel_cstate,
3266                                                     pstate, 1);
3267                 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3268         }
3269
3270         /* Calculate CRTC's total data rate from cached values */
3271         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3272                 int id = skl_wm_plane_id(intel_plane);
3273
3274                 /* packed/uv */
3275                 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3276                 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
3277         }
3278
3279         return total_data_rate;
3280 }
3281
3282 static uint16_t
3283 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3284                   const int y)
3285 {
3286         struct drm_framebuffer *fb = pstate->fb;
3287         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3288         uint32_t src_w, src_h;
3289         uint32_t min_scanlines = 8;
3290         uint8_t plane_bpp;
3291
3292         if (WARN_ON(!fb))
3293                 return 0;
3294
3295         /* For packed formats, no y-plane, return 0 */
3296         if (y && fb->pixel_format != DRM_FORMAT_NV12)
3297                 return 0;
3298
3299         /* For Non Y-tile return 8-blocks */
3300         if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3301             fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3302                 return 8;
3303
3304         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3305         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3306
3307         if (intel_rotation_90_or_270(pstate->rotation))
3308                 swap(src_w, src_h);
3309
3310         /* Halve UV plane width and height for NV12 */
3311         if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3312                 src_w /= 2;
3313                 src_h /= 2;
3314         }
3315
3316         if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3317                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3318         else
3319                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3320
3321         if (intel_rotation_90_or_270(pstate->rotation)) {
3322                 switch (plane_bpp) {
3323                 case 1:
3324                         min_scanlines = 32;
3325                         break;
3326                 case 2:
3327                         min_scanlines = 16;
3328                         break;
3329                 case 4:
3330                         min_scanlines = 8;
3331                         break;
3332                 case 8:
3333                         min_scanlines = 4;
3334                         break;
3335                 default:
3336                         WARN(1, "Unsupported pixel depth %u for rotation",
3337                              plane_bpp);
3338                         min_scanlines = 32;
3339                 }
3340         }
3341
3342         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3343 }
3344
3345 static int
3346 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3347                       struct skl_ddb_allocation *ddb /* out */)
3348 {
3349         struct drm_atomic_state *state = cstate->base.state;
3350         struct drm_crtc *crtc = cstate->base.crtc;
3351         struct drm_device *dev = crtc->dev;
3352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3353         struct intel_plane *intel_plane;
3354         struct drm_plane *plane;
3355         struct drm_plane_state *pstate;
3356         enum pipe pipe = intel_crtc->pipe;
3357         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3358         uint16_t alloc_size, start, cursor_blocks;
3359         uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3360         uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
3361         unsigned int total_data_rate;
3362         int num_active;
3363         int id, i;
3364
3365         /* Clear the partitioning for disabled planes. */
3366         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3367         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3368
3369         if (WARN_ON(!state))
3370                 return 0;
3371
3372         if (!cstate->base.active) {
3373                 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3374                 return 0;
3375         }
3376
3377         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3378         alloc_size = skl_ddb_entry_size(alloc);
3379         if (alloc_size == 0) {
3380                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3381                 return 0;
3382         }
3383
3384         cursor_blocks = skl_cursor_allocation(num_active);
3385         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3386         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3387
3388         alloc_size -= cursor_blocks;
3389
3390         /* 1. Allocate the mininum required blocks for each active plane */
3391         for_each_plane_in_state(state, plane, pstate, i) {
3392                 intel_plane = to_intel_plane(plane);
3393                 id = skl_wm_plane_id(intel_plane);
3394
3395                 if (intel_plane->pipe != pipe)
3396                         continue;
3397
3398                 if (!to_intel_plane_state(pstate)->base.visible) {
3399                         minimum[id] = 0;
3400                         y_minimum[id] = 0;
3401                         continue;
3402                 }
3403                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3404                         minimum[id] = 0;
3405                         y_minimum[id] = 0;
3406                         continue;
3407                 }
3408
3409                 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3410                 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3411         }
3412
3413         for (i = 0; i < PLANE_CURSOR; i++) {
3414                 alloc_size -= minimum[i];
3415                 alloc_size -= y_minimum[i];
3416         }
3417
3418         /*
3419          * 2. Distribute the remaining space in proportion to the amount of
3420          * data each plane needs to fetch from memory.
3421          *
3422          * FIXME: we may not allocate every single block here.
3423          */
3424         total_data_rate = skl_get_total_relative_data_rate(cstate);
3425         if (total_data_rate == 0)
3426                 return 0;
3427
3428         start = alloc->start;
3429         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3430                 unsigned int data_rate, y_data_rate;
3431                 uint16_t plane_blocks, y_plane_blocks = 0;
3432                 int id = skl_wm_plane_id(intel_plane);
3433
3434                 data_rate = cstate->wm.skl.plane_data_rate[id];
3435
3436                 /*
3437                  * allocation for (packed formats) or (uv-plane part of planar format):
3438                  * promote the expression to 64 bits to avoid overflowing, the
3439                  * result is < available as data_rate / total_data_rate < 1
3440                  */
3441                 plane_blocks = minimum[id];
3442                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3443                                         total_data_rate);
3444
3445                 /* Leave disabled planes at (0,0) */
3446                 if (data_rate) {
3447                         ddb->plane[pipe][id].start = start;
3448                         ddb->plane[pipe][id].end = start + plane_blocks;
3449                 }
3450
3451                 start += plane_blocks;
3452
3453                 /*
3454                  * allocation for y_plane part of planar format:
3455                  */
3456                 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3457
3458                 y_plane_blocks = y_minimum[id];
3459                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3460                                         total_data_rate);
3461
3462                 if (y_data_rate) {
3463                         ddb->y_plane[pipe][id].start = start;
3464                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3465                 }
3466
3467                 start += y_plane_blocks;
3468         }
3469
3470         return 0;
3471 }
3472
3473 /*
3474  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3475  * for the read latency) and cpp should always be <= 8, so that
3476  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3477  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3478 */
3479 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3480 {
3481         uint32_t wm_intermediate_val, ret;
3482
3483         if (latency == 0)
3484                 return UINT_MAX;
3485
3486         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3487         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3488
3489         return ret;
3490 }
3491
3492 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3493                                uint32_t latency, uint32_t plane_blocks_per_line)
3494 {
3495         uint32_t ret;
3496         uint32_t wm_intermediate_val;
3497
3498         if (latency == 0)
3499                 return UINT_MAX;
3500
3501         wm_intermediate_val = latency * pixel_rate;
3502         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3503                                 plane_blocks_per_line;
3504
3505         return ret;
3506 }
3507
3508 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3509                                               struct intel_plane_state *pstate)
3510 {
3511         uint64_t adjusted_pixel_rate;
3512         uint64_t downscale_amount;
3513         uint64_t pixel_rate;
3514
3515         /* Shouldn't reach here on disabled planes... */
3516         if (WARN_ON(!pstate->base.visible))
3517                 return 0;
3518
3519         /*
3520          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3521          * with additional adjustments for plane-specific scaling.
3522          */
3523         adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
3524         downscale_amount = skl_plane_downscale_amount(pstate);
3525
3526         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3527         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3528
3529         return pixel_rate;
3530 }
3531
3532 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3533                                 struct intel_crtc_state *cstate,
3534                                 struct intel_plane_state *intel_pstate,
3535                                 uint16_t ddb_allocation,
3536                                 int level,
3537                                 uint16_t *out_blocks, /* out */
3538                                 uint8_t *out_lines, /* out */
3539                                 bool *enabled /* out */)
3540 {
3541         struct drm_plane_state *pstate = &intel_pstate->base;
3542         struct drm_framebuffer *fb = pstate->fb;
3543         uint32_t latency = dev_priv->wm.skl_latency[level];
3544         uint32_t method1, method2;
3545         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3546         uint32_t res_blocks, res_lines;
3547         uint32_t selected_result;
3548         uint8_t cpp;
3549         uint32_t width = 0, height = 0;
3550         uint32_t plane_pixel_rate;
3551         uint32_t y_tile_minimum, y_min_scanlines;
3552
3553         if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3554                 *enabled = false;
3555                 return 0;
3556         }
3557
3558         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3559         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3560
3561         if (intel_rotation_90_or_270(pstate->rotation))
3562                 swap(width, height);
3563
3564         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3565         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3566
3567         if (intel_rotation_90_or_270(pstate->rotation)) {
3568                 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3569                         drm_format_plane_cpp(fb->pixel_format, 1) :
3570                         drm_format_plane_cpp(fb->pixel_format, 0);
3571
3572                 switch (cpp) {
3573                 case 1:
3574                         y_min_scanlines = 16;
3575                         break;
3576                 case 2:
3577                         y_min_scanlines = 8;
3578                         break;
3579                 default:
3580                         WARN(1, "Unsupported pixel depth for rotation");
3581                 case 4:
3582                         y_min_scanlines = 4;
3583                         break;
3584                 }
3585         } else {
3586                 y_min_scanlines = 4;
3587         }
3588
3589         plane_bytes_per_line = width * cpp;
3590         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3591             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3592                 plane_blocks_per_line =
3593                       DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3594                 plane_blocks_per_line /= y_min_scanlines;
3595         } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3596                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3597                                         + 1;
3598         } else {
3599                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3600         }
3601
3602         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3603         method2 = skl_wm_method2(plane_pixel_rate,
3604                                  cstate->base.adjusted_mode.crtc_htotal,
3605                                  latency,
3606                                  plane_blocks_per_line);
3607
3608         y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3609
3610         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3611             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3612                 selected_result = max(method2, y_tile_minimum);
3613         } else {
3614                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3615                         selected_result = min(method1, method2);
3616                 else
3617                         selected_result = method1;
3618         }
3619
3620         res_blocks = selected_result + 1;
3621         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3622
3623         if (level >= 1 && level <= 7) {
3624                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3625                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3626                         res_blocks += y_tile_minimum;
3627                         res_lines += y_min_scanlines;
3628                 } else {
3629                         res_blocks++;
3630                 }
3631         }
3632
3633         if (res_blocks >= ddb_allocation || res_lines > 31) {
3634                 *enabled = false;
3635
3636                 /*
3637                  * If there are no valid level 0 watermarks, then we can't
3638                  * support this display configuration.
3639                  */
3640                 if (level) {
3641                         return 0;
3642                 } else {
3643                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3644                         DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3645                                       to_intel_crtc(cstate->base.crtc)->pipe,
3646                                       skl_wm_plane_id(to_intel_plane(pstate->plane)),
3647                                       res_blocks, ddb_allocation, res_lines);
3648
3649                         return -EINVAL;
3650                 }
3651         }
3652
3653         *out_blocks = res_blocks;
3654         *out_lines = res_lines;
3655         *enabled = true;
3656
3657         return 0;
3658 }
3659
3660 static int
3661 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3662                      struct skl_ddb_allocation *ddb,
3663                      struct intel_crtc_state *cstate,
3664                      int level,
3665                      struct skl_wm_level *result)
3666 {
3667         struct drm_atomic_state *state = cstate->base.state;
3668         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3669         struct drm_plane *plane;
3670         struct intel_plane *intel_plane;
3671         struct intel_plane_state *intel_pstate;
3672         uint16_t ddb_blocks;
3673         enum pipe pipe = intel_crtc->pipe;
3674         int ret;
3675
3676         /*
3677          * We'll only calculate watermarks for planes that are actually
3678          * enabled, so make sure all other planes are set as disabled.
3679          */
3680         memset(result, 0, sizeof(*result));
3681
3682         for_each_intel_plane_mask(&dev_priv->drm,
3683                                   intel_plane,
3684                                   cstate->base.plane_mask) {
3685                 int i = skl_wm_plane_id(intel_plane);
3686
3687                 plane = &intel_plane->base;
3688                 intel_pstate = NULL;
3689                 if (state)
3690                         intel_pstate =
3691                                 intel_atomic_get_existing_plane_state(state,
3692                                                                       intel_plane);
3693
3694                 /*
3695                  * Note: If we start supporting multiple pending atomic commits
3696                  * against the same planes/CRTC's in the future, plane->state
3697                  * will no longer be the correct pre-state to use for the
3698                  * calculations here and we'll need to change where we get the
3699                  * 'unchanged' plane data from.
3700                  *
3701                  * For now this is fine because we only allow one queued commit
3702                  * against a CRTC.  Even if the plane isn't modified by this
3703                  * transaction and we don't have a plane lock, we still have
3704                  * the CRTC's lock, so we know that no other transactions are
3705                  * racing with us to update it.
3706                  */
3707                 if (!intel_pstate)
3708                         intel_pstate = to_intel_plane_state(plane->state);
3709
3710                 WARN_ON(!intel_pstate->base.fb);
3711
3712                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3713
3714                 ret = skl_compute_plane_wm(dev_priv,
3715                                            cstate,
3716                                            intel_pstate,
3717                                            ddb_blocks,
3718                                            level,
3719                                            &result->plane_res_b[i],
3720                                            &result->plane_res_l[i],
3721                                            &result->plane_en[i]);
3722                 if (ret)
3723                         return ret;
3724         }
3725
3726         return 0;
3727 }
3728
3729 static uint32_t
3730 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3731 {
3732         if (!cstate->base.active)
3733                 return 0;
3734
3735         if (WARN_ON(ilk_pipe_pixel_rate(cstate) == 0))
3736                 return 0;
3737
3738         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3739                             ilk_pipe_pixel_rate(cstate));
3740 }
3741
3742 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3743                                       struct skl_wm_level *trans_wm /* out */)
3744 {
3745         struct drm_crtc *crtc = cstate->base.crtc;
3746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3747         struct intel_plane *intel_plane;
3748
3749         if (!cstate->base.active)
3750                 return;
3751
3752         /* Until we know more, just disable transition WMs */
3753         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3754                 int i = skl_wm_plane_id(intel_plane);
3755
3756                 trans_wm->plane_en[i] = false;
3757         }
3758 }
3759
3760 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3761                              struct skl_ddb_allocation *ddb,
3762                              struct skl_pipe_wm *pipe_wm)
3763 {
3764         struct drm_device *dev = cstate->base.crtc->dev;
3765         const struct drm_i915_private *dev_priv = to_i915(dev);
3766         int level, max_level = ilk_wm_max_level(dev);
3767         int ret;
3768
3769         for (level = 0; level <= max_level; level++) {
3770                 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3771                                            level, &pipe_wm->wm[level]);
3772                 if (ret)
3773                         return ret;
3774         }
3775         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3776
3777         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3778
3779         return 0;
3780 }
3781
3782 static void skl_compute_wm_results(struct drm_device *dev,
3783                                    struct skl_pipe_wm *p_wm,
3784                                    struct skl_wm_values *r,
3785                                    struct intel_crtc *intel_crtc)
3786 {
3787         int level, max_level = ilk_wm_max_level(dev);
3788         enum pipe pipe = intel_crtc->pipe;
3789         uint32_t temp;
3790         int i;
3791
3792         for (level = 0; level <= max_level; level++) {
3793                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3794                         temp = 0;
3795
3796                         temp |= p_wm->wm[level].plane_res_l[i] <<
3797                                         PLANE_WM_LINES_SHIFT;
3798                         temp |= p_wm->wm[level].plane_res_b[i];
3799                         if (p_wm->wm[level].plane_en[i])
3800                                 temp |= PLANE_WM_EN;
3801
3802                         r->plane[pipe][i][level] = temp;
3803                 }
3804
3805                 temp = 0;
3806
3807                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3808                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3809
3810                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3811                         temp |= PLANE_WM_EN;
3812
3813                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3814
3815         }
3816
3817         /* transition WMs */
3818         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3819                 temp = 0;
3820                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3821                 temp |= p_wm->trans_wm.plane_res_b[i];
3822                 if (p_wm->trans_wm.plane_en[i])
3823                         temp |= PLANE_WM_EN;
3824
3825                 r->plane_trans[pipe][i] = temp;
3826         }
3827
3828         temp = 0;
3829         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3830         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3831         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3832                 temp |= PLANE_WM_EN;
3833
3834         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3835
3836         r->wm_linetime[pipe] = p_wm->linetime;
3837 }
3838
3839 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3840                                 i915_reg_t reg,
3841                                 const struct skl_ddb_entry *entry)
3842 {
3843         if (entry->end)
3844                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3845         else
3846                 I915_WRITE(reg, 0);
3847 }
3848
3849 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3850                         const struct skl_wm_values *wm,
3851                         int plane)
3852 {
3853         struct drm_crtc *crtc = &intel_crtc->base;
3854         struct drm_device *dev = crtc->dev;
3855         struct drm_i915_private *dev_priv = to_i915(dev);
3856         int level, max_level = ilk_wm_max_level(dev);
3857         enum pipe pipe = intel_crtc->pipe;
3858
3859         for (level = 0; level <= max_level; level++) {
3860                 I915_WRITE(PLANE_WM(pipe, plane, level),
3861                            wm->plane[pipe][plane][level]);
3862         }
3863         I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
3864
3865         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3866                             &wm->ddb.plane[pipe][plane]);
3867         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3868                             &wm->ddb.y_plane[pipe][plane]);
3869 }
3870
3871 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3872                          const struct skl_wm_values *wm)
3873 {
3874         struct drm_crtc *crtc = &intel_crtc->base;
3875         struct drm_device *dev = crtc->dev;
3876         struct drm_i915_private *dev_priv = to_i915(dev);
3877         int level, max_level = ilk_wm_max_level(dev);
3878         enum pipe pipe = intel_crtc->pipe;
3879
3880         for (level = 0; level <= max_level; level++) {
3881                 I915_WRITE(CUR_WM(pipe, level),
3882                            wm->plane[pipe][PLANE_CURSOR][level]);
3883         }
3884         I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
3885
3886         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3887                             &wm->ddb.plane[pipe][PLANE_CURSOR]);
3888 }
3889
3890 bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
3891                                const struct skl_ddb_allocation *new,
3892                                enum pipe pipe)
3893 {
3894         return new->pipe[pipe].start == old->pipe[pipe].start &&
3895                new->pipe[pipe].end == old->pipe[pipe].end;
3896 }
3897
3898 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3899                                            const struct skl_ddb_entry *b)
3900 {
3901         return a->start < b->end && b->start < a->end;
3902 }
3903
3904 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3905                                  const struct skl_ddb_allocation *old,
3906                                  const struct skl_ddb_allocation *new,
3907                                  enum pipe pipe)
3908 {
3909         struct drm_device *dev = state->dev;
3910         struct intel_crtc *intel_crtc;
3911         enum pipe otherp;
3912
3913         for_each_intel_crtc(dev, intel_crtc) {
3914                 otherp = intel_crtc->pipe;
3915
3916                 if (otherp == pipe)
3917                         continue;
3918
3919                 if (skl_ddb_entries_overlap(&new->pipe[pipe],
3920                                             &old->pipe[otherp]))
3921                         return true;
3922         }
3923
3924         return false;
3925 }
3926
3927 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3928                               struct skl_ddb_allocation *ddb, /* out */
3929                               struct skl_pipe_wm *pipe_wm, /* out */
3930                               bool *changed /* out */)
3931 {
3932         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3933         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3934         int ret;
3935
3936         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3937         if (ret)
3938                 return ret;
3939
3940         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3941                 *changed = false;
3942         else
3943                 *changed = true;
3944
3945         return 0;
3946 }
3947
3948 static uint32_t
3949 pipes_modified(struct drm_atomic_state *state)
3950 {
3951         struct drm_crtc *crtc;
3952         struct drm_crtc_state *cstate;
3953         uint32_t i, ret = 0;
3954
3955         for_each_crtc_in_state(state, crtc, cstate, i)
3956                 ret |= drm_crtc_mask(crtc);
3957
3958         return ret;
3959 }
3960
3961 int
3962 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3963 {
3964         struct drm_atomic_state *state = cstate->base.state;
3965         struct drm_device *dev = state->dev;
3966         struct drm_crtc *crtc = cstate->base.crtc;
3967         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3968         struct drm_i915_private *dev_priv = to_i915(dev);
3969         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3970         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3971         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3972         struct drm_plane_state *plane_state;
3973         struct drm_plane *plane;
3974         enum pipe pipe = intel_crtc->pipe;
3975         int id;
3976
3977         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3978
3979         drm_for_each_plane_mask(plane, dev, crtc->state->plane_mask) {
3980                 id = skl_wm_plane_id(to_intel_plane(plane));
3981
3982                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3983                                         &new_ddb->plane[pipe][id]) &&
3984                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3985                                         &new_ddb->y_plane[pipe][id]))
3986                         continue;
3987
3988                 plane_state = drm_atomic_get_plane_state(state, plane);
3989                 if (IS_ERR(plane_state))
3990                         return PTR_ERR(plane_state);
3991         }
3992
3993         return 0;
3994 }
3995
3996 static int
3997 skl_compute_ddb(struct drm_atomic_state *state)
3998 {
3999         struct drm_device *dev = state->dev;
4000         struct drm_i915_private *dev_priv = to_i915(dev);
4001         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4002         struct intel_crtc *intel_crtc;
4003         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4004         uint32_t realloc_pipes = pipes_modified(state);
4005         int ret;
4006
4007         /*
4008          * If this is our first atomic update following hardware readout,
4009          * we can't trust the DDB that the BIOS programmed for us.  Let's
4010          * pretend that all pipes switched active status so that we'll
4011          * ensure a full DDB recompute.
4012          */
4013         if (dev_priv->wm.distrust_bios_wm) {
4014                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4015                                        state->acquire_ctx);
4016                 if (ret)
4017                         return ret;
4018
4019                 intel_state->active_pipe_changes = ~0;
4020
4021                 /*
4022                  * We usually only initialize intel_state->active_crtcs if we
4023                  * we're doing a modeset; make sure this field is always
4024                  * initialized during the sanitization process that happens
4025                  * on the first commit too.
4026                  */
4027                 if (!intel_state->modeset)
4028                         intel_state->active_crtcs = dev_priv->active_crtcs;
4029         }
4030
4031         /*
4032          * If the modeset changes which CRTC's are active, we need to
4033          * recompute the DDB allocation for *all* active pipes, even
4034          * those that weren't otherwise being modified in any way by this
4035          * atomic commit.  Due to the shrinking of the per-pipe allocations
4036          * when new active CRTC's are added, it's possible for a pipe that
4037          * we were already using and aren't changing at all here to suddenly
4038          * become invalid if its DDB needs exceeds its new allocation.
4039          *
4040          * Note that if we wind up doing a full DDB recompute, we can't let
4041          * any other display updates race with this transaction, so we need
4042          * to grab the lock on *all* CRTC's.
4043          */
4044         if (intel_state->active_pipe_changes) {
4045                 realloc_pipes = ~0;
4046                 intel_state->wm_results.dirty_pipes = ~0;
4047         }
4048
4049         /*
4050          * We're not recomputing for the pipes not included in the commit, so
4051          * make sure we start with the current state.
4052          */
4053         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4054
4055         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4056                 struct intel_crtc_state *cstate;
4057
4058                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4059                 if (IS_ERR(cstate))
4060                         return PTR_ERR(cstate);
4061
4062                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4063                 if (ret)
4064                         return ret;
4065
4066                 ret = skl_ddb_add_affected_planes(cstate);
4067                 if (ret)
4068                         return ret;
4069         }
4070
4071         return 0;
4072 }
4073
4074 static void
4075 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4076                      struct skl_wm_values *src,
4077                      enum pipe pipe)
4078 {
4079         dst->wm_linetime[pipe] = src->wm_linetime[pipe];
4080         memcpy(dst->plane[pipe], src->plane[pipe],
4081                sizeof(dst->plane[pipe]));
4082         memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4083                sizeof(dst->plane_trans[pipe]));
4084
4085         dst->ddb.pipe[pipe] = src->ddb.pipe[pipe];
4086         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4087                sizeof(dst->ddb.y_plane[pipe]));
4088         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4089                sizeof(dst->ddb.plane[pipe]));
4090 }
4091
4092 static int
4093 skl_compute_wm(struct drm_atomic_state *state)
4094 {
4095         struct drm_crtc *crtc;
4096         struct drm_crtc_state *cstate;
4097         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4098         struct skl_wm_values *results = &intel_state->wm_results;
4099         struct skl_pipe_wm *pipe_wm;
4100         bool changed = false;
4101         int ret, i;
4102
4103         /*
4104          * If this transaction isn't actually touching any CRTC's, don't
4105          * bother with watermark calculation.  Note that if we pass this
4106          * test, we're guaranteed to hold at least one CRTC state mutex,
4107          * which means we can safely use values like dev_priv->active_crtcs
4108          * since any racing commits that want to update them would need to
4109          * hold _all_ CRTC state mutexes.
4110          */
4111         for_each_crtc_in_state(state, crtc, cstate, i)
4112                 changed = true;
4113         if (!changed)
4114                 return 0;
4115
4116         /* Clear all dirty flags */
4117         results->dirty_pipes = 0;
4118
4119         ret = skl_compute_ddb(state);
4120         if (ret)
4121                 return ret;
4122
4123         /*
4124          * Calculate WM's for all pipes that are part of this transaction.
4125          * Note that the DDB allocation above may have added more CRTC's that
4126          * weren't otherwise being modified (and set bits in dirty_pipes) if
4127          * pipe allocations had to change.
4128          *
4129          * FIXME:  Now that we're doing this in the atomic check phase, we
4130          * should allow skl_update_pipe_wm() to return failure in cases where
4131          * no suitable watermark values can be found.
4132          */
4133         for_each_crtc_in_state(state, crtc, cstate, i) {
4134                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4135                 struct intel_crtc_state *intel_cstate =
4136                         to_intel_crtc_state(cstate);
4137
4138                 pipe_wm = &intel_cstate->wm.skl.optimal;
4139                 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4140                                          &changed);
4141                 if (ret)
4142                         return ret;
4143
4144                 if (changed)
4145                         results->dirty_pipes |= drm_crtc_mask(crtc);
4146
4147                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4148                         /* This pipe's WM's did not change */
4149                         continue;
4150
4151                 intel_cstate->update_wm_pre = true;
4152                 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4153         }
4154
4155         return 0;
4156 }
4157
4158 static void skl_update_wm(struct drm_crtc *crtc)
4159 {
4160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4161         struct drm_device *dev = crtc->dev;
4162         struct drm_i915_private *dev_priv = to_i915(dev);
4163         struct skl_wm_values *results = &dev_priv->wm.skl_results;
4164         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4165         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4166         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4167         enum pipe pipe = intel_crtc->pipe;
4168
4169         if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4170                 return;
4171
4172         intel_crtc->wm.active.skl = *pipe_wm;
4173
4174         mutex_lock(&dev_priv->wm.wm_mutex);
4175
4176         /*
4177          * If this pipe isn't active already, we're going to be enabling it
4178          * very soon. Since it's safe to update a pipe's ddb allocation while
4179          * the pipe's shut off, just do so here. Already active pipes will have
4180          * their watermarks updated once we update their planes.
4181          */
4182         if (crtc->state->active_changed) {
4183                 int plane;
4184
4185                 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4186                         skl_write_plane_wm(intel_crtc, results, plane);
4187
4188                 skl_write_cursor_wm(intel_crtc, results);
4189         }
4190
4191         skl_copy_wm_for_pipe(hw_vals, results, pipe);
4192
4193         mutex_unlock(&dev_priv->wm.wm_mutex);
4194 }
4195
4196 static void ilk_compute_wm_config(struct drm_device *dev,
4197                                   struct intel_wm_config *config)
4198 {
4199         struct intel_crtc *crtc;
4200
4201         /* Compute the currently _active_ config */
4202         for_each_intel_crtc(dev, crtc) {
4203                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4204
4205                 if (!wm->pipe_enabled)
4206                         continue;
4207
4208                 config->sprites_enabled |= wm->sprites_enabled;
4209                 config->sprites_scaled |= wm->sprites_scaled;
4210                 config->num_pipes_active++;
4211         }
4212 }
4213
4214 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4215 {
4216         struct drm_device *dev = &dev_priv->drm;
4217         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4218         struct ilk_wm_maximums max;
4219         struct intel_wm_config config = {};
4220         struct ilk_wm_values results = {};
4221         enum intel_ddb_partitioning partitioning;
4222
4223         ilk_compute_wm_config(dev, &config);
4224
4225         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4226         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4227
4228         /* 5/6 split only in single pipe config on IVB+ */
4229         if (INTEL_INFO(dev)->gen >= 7 &&
4230             config.num_pipes_active == 1 && config.sprites_enabled) {
4231                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4232                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4233
4234                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4235         } else {
4236                 best_lp_wm = &lp_wm_1_2;
4237         }
4238
4239         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4240                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4241
4242         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4243
4244         ilk_write_wm_values(dev_priv, &results);
4245 }
4246
4247 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
4248 {
4249         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4250         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4251
4252         mutex_lock(&dev_priv->wm.wm_mutex);
4253         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4254         ilk_program_watermarks(dev_priv);
4255         mutex_unlock(&dev_priv->wm.wm_mutex);
4256 }
4257
4258 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4259 {
4260         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4261         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4262
4263         mutex_lock(&dev_priv->wm.wm_mutex);
4264         if (cstate->wm.need_postvbl_update) {
4265                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4266                 ilk_program_watermarks(dev_priv);
4267         }
4268         mutex_unlock(&dev_priv->wm.wm_mutex);
4269 }
4270
4271 static void skl_pipe_wm_active_state(uint32_t val,
4272                                      struct skl_pipe_wm *active,
4273                                      bool is_transwm,
4274                                      bool is_cursor,
4275                                      int i,
4276                                      int level)
4277 {
4278         bool is_enabled = (val & PLANE_WM_EN) != 0;
4279
4280         if (!is_transwm) {
4281                 if (!is_cursor) {
4282                         active->wm[level].plane_en[i] = is_enabled;
4283                         active->wm[level].plane_res_b[i] =
4284                                         val & PLANE_WM_BLOCKS_MASK;
4285                         active->wm[level].plane_res_l[i] =
4286                                         (val >> PLANE_WM_LINES_SHIFT) &
4287                                                 PLANE_WM_LINES_MASK;
4288                 } else {
4289                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4290                         active->wm[level].plane_res_b[PLANE_CURSOR] =
4291                                         val & PLANE_WM_BLOCKS_MASK;
4292                         active->wm[level].plane_res_l[PLANE_CURSOR] =
4293                                         (val >> PLANE_WM_LINES_SHIFT) &
4294                                                 PLANE_WM_LINES_MASK;
4295                 }
4296         } else {
4297                 if (!is_cursor) {
4298                         active->trans_wm.plane_en[i] = is_enabled;
4299                         active->trans_wm.plane_res_b[i] =
4300                                         val & PLANE_WM_BLOCKS_MASK;
4301                         active->trans_wm.plane_res_l[i] =
4302                                         (val >> PLANE_WM_LINES_SHIFT) &
4303                                                 PLANE_WM_LINES_MASK;
4304                 } else {
4305                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4306                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
4307                                         val & PLANE_WM_BLOCKS_MASK;
4308                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
4309                                         (val >> PLANE_WM_LINES_SHIFT) &
4310                                                 PLANE_WM_LINES_MASK;
4311                 }
4312         }
4313 }
4314
4315 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4316 {
4317         struct drm_device *dev = crtc->dev;
4318         struct drm_i915_private *dev_priv = to_i915(dev);
4319         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4320         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4321         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4322         struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
4323         enum pipe pipe = intel_crtc->pipe;
4324         int level, i, max_level;
4325         uint32_t temp;
4326
4327         max_level = ilk_wm_max_level(dev);
4328
4329         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4330
4331         for (level = 0; level <= max_level; level++) {
4332                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4333                         hw->plane[pipe][i][level] =
4334                                         I915_READ(PLANE_WM(pipe, i, level));
4335                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
4336         }
4337
4338         for (i = 0; i < intel_num_planes(intel_crtc); i++)
4339                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4340         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
4341
4342         if (!intel_crtc->active)
4343                 return;
4344
4345         hw->dirty_pipes |= drm_crtc_mask(crtc);
4346
4347         active->linetime = hw->wm_linetime[pipe];
4348
4349         for (level = 0; level <= max_level; level++) {
4350                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4351                         temp = hw->plane[pipe][i][level];
4352                         skl_pipe_wm_active_state(temp, active, false,
4353                                                 false, i, level);
4354                 }
4355                 temp = hw->plane[pipe][PLANE_CURSOR][level];
4356                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4357         }
4358
4359         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4360                 temp = hw->plane_trans[pipe][i];
4361                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4362         }
4363
4364         temp = hw->plane_trans[pipe][PLANE_CURSOR];
4365         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4366
4367         intel_crtc->wm.active.skl = *active;
4368 }
4369
4370 void skl_wm_get_hw_state(struct drm_device *dev)
4371 {
4372         struct drm_i915_private *dev_priv = to_i915(dev);
4373         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4374         struct drm_crtc *crtc;
4375
4376         skl_ddb_get_hw_state(dev_priv, ddb);
4377         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4378                 skl_pipe_wm_get_hw_state(crtc);
4379
4380         if (dev_priv->active_crtcs) {
4381                 /* Fully recompute DDB on first atomic commit */
4382                 dev_priv->wm.distrust_bios_wm = true;
4383         } else {
4384                 /* Easy/common case; just sanitize DDB now if everything off */
4385                 memset(ddb, 0, sizeof(*ddb));
4386         }
4387 }
4388
4389 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4390 {
4391         struct drm_device *dev = crtc->dev;
4392         struct drm_i915_private *dev_priv = to_i915(dev);
4393         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4395         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4396         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4397         enum pipe pipe = intel_crtc->pipe;
4398         static const i915_reg_t wm0_pipe_reg[] = {
4399                 [PIPE_A] = WM0_PIPEA_ILK,
4400                 [PIPE_B] = WM0_PIPEB_ILK,
4401                 [PIPE_C] = WM0_PIPEC_IVB,
4402         };
4403
4404         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4405         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4406                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4407
4408         memset(active, 0, sizeof(*active));
4409
4410         active->pipe_enabled = intel_crtc->active;
4411
4412         if (active->pipe_enabled) {
4413                 u32 tmp = hw->wm_pipe[pipe];
4414
4415                 /*
4416                  * For active pipes LP0 watermark is marked as
4417                  * enabled, and LP1+ watermaks as disabled since
4418                  * we can't really reverse compute them in case
4419                  * multiple pipes are active.
4420                  */
4421                 active->wm[0].enable = true;
4422                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4423                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4424                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4425                 active->linetime = hw->wm_linetime[pipe];
4426         } else {
4427                 int level, max_level = ilk_wm_max_level(dev);
4428
4429                 /*
4430                  * For inactive pipes, all watermark levels
4431                  * should be marked as enabled but zeroed,
4432                  * which is what we'd compute them to.
4433                  */
4434                 for (level = 0; level <= max_level; level++)
4435                         active->wm[level].enable = true;
4436         }
4437
4438         intel_crtc->wm.active.ilk = *active;
4439 }
4440
4441 #define _FW_WM(value, plane) \
4442         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4443 #define _FW_WM_VLV(value, plane) \
4444         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4445
4446 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4447                                struct vlv_wm_values *wm)
4448 {
4449         enum pipe pipe;
4450         uint32_t tmp;
4451
4452         for_each_pipe(dev_priv, pipe) {
4453                 tmp = I915_READ(VLV_DDL(pipe));
4454
4455                 wm->ddl[pipe].primary =
4456                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4457                 wm->ddl[pipe].cursor =
4458                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4459                 wm->ddl[pipe].sprite[0] =
4460                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4461                 wm->ddl[pipe].sprite[1] =
4462                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4463         }
4464
4465         tmp = I915_READ(DSPFW1);
4466         wm->sr.plane = _FW_WM(tmp, SR);
4467         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4468         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4469         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4470
4471         tmp = I915_READ(DSPFW2);
4472         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4473         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4474         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4475
4476         tmp = I915_READ(DSPFW3);
4477         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4478
4479         if (IS_CHERRYVIEW(dev_priv)) {
4480                 tmp = I915_READ(DSPFW7_CHV);
4481                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4482                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4483
4484                 tmp = I915_READ(DSPFW8_CHV);
4485                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4486                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4487
4488                 tmp = I915_READ(DSPFW9_CHV);
4489                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4490                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4491
4492                 tmp = I915_READ(DSPHOWM);
4493                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4494                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4495                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4496                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4497                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4498                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4499                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4500                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4501                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4502                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4503         } else {
4504                 tmp = I915_READ(DSPFW7);
4505                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4506                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4507
4508                 tmp = I915_READ(DSPHOWM);
4509                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4510                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4511                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4512                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4513                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4514                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4515                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4516         }
4517 }
4518
4519 #undef _FW_WM
4520 #undef _FW_WM_VLV
4521
4522 void vlv_wm_get_hw_state(struct drm_device *dev)
4523 {
4524         struct drm_i915_private *dev_priv = to_i915(dev);
4525         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4526         struct intel_plane *plane;
4527         enum pipe pipe;
4528         u32 val;
4529
4530         vlv_read_wm_values(dev_priv, wm);
4531
4532         for_each_intel_plane(dev, plane) {
4533                 switch (plane->base.type) {
4534                         int sprite;
4535                 case DRM_PLANE_TYPE_CURSOR:
4536                         plane->wm.fifo_size = 63;
4537                         break;
4538                 case DRM_PLANE_TYPE_PRIMARY:
4539                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4540                         break;
4541                 case DRM_PLANE_TYPE_OVERLAY:
4542                         sprite = plane->plane;
4543                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4544                         break;
4545                 }
4546         }
4547
4548         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4549         wm->level = VLV_WM_LEVEL_PM2;
4550
4551         if (IS_CHERRYVIEW(dev_priv)) {
4552                 mutex_lock(&dev_priv->rps.hw_lock);
4553
4554                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4555                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4556                         wm->level = VLV_WM_LEVEL_PM5;
4557
4558                 /*
4559                  * If DDR DVFS is disabled in the BIOS, Punit
4560                  * will never ack the request. So if that happens
4561                  * assume we don't have to enable/disable DDR DVFS
4562                  * dynamically. To test that just set the REQ_ACK
4563                  * bit to poke the Punit, but don't change the
4564                  * HIGH/LOW bits so that we don't actually change
4565                  * the current state.
4566                  */
4567                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4568                 val |= FORCE_DDR_FREQ_REQ_ACK;
4569                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4570
4571                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4572                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4573                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4574                                       "assuming DDR DVFS is disabled\n");
4575                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4576                 } else {
4577                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4578                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4579                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4580                 }
4581
4582                 mutex_unlock(&dev_priv->rps.hw_lock);
4583         }
4584
4585         for_each_pipe(dev_priv, pipe)
4586                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4587                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4588                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4589
4590         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4591                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4592 }
4593
4594 void ilk_wm_get_hw_state(struct drm_device *dev)
4595 {
4596         struct drm_i915_private *dev_priv = to_i915(dev);
4597         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4598         struct drm_crtc *crtc;
4599
4600         for_each_crtc(dev, crtc)
4601                 ilk_pipe_wm_get_hw_state(crtc);
4602
4603         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4604         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4605         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4606
4607         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4608         if (INTEL_INFO(dev)->gen >= 7) {
4609                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4610                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4611         }
4612
4613         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4614                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4615                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4616         else if (IS_IVYBRIDGE(dev))
4617                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4618                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4619
4620         hw->enable_fbc_wm =
4621                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4622 }
4623
4624 /**
4625  * intel_update_watermarks - update FIFO watermark values based on current modes
4626  *
4627  * Calculate watermark values for the various WM regs based on current mode
4628  * and plane configuration.
4629  *
4630  * There are several cases to deal with here:
4631  *   - normal (i.e. non-self-refresh)
4632  *   - self-refresh (SR) mode
4633  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4634  *   - lines are small relative to FIFO size (buffer can hold more than 2
4635  *     lines), so need to account for TLB latency
4636  *
4637  *   The normal calculation is:
4638  *     watermark = dotclock * bytes per pixel * latency
4639  *   where latency is platform & configuration dependent (we assume pessimal
4640  *   values here).
4641  *
4642  *   The SR calculation is:
4643  *     watermark = (trunc(latency/line time)+1) * surface width *
4644  *       bytes per pixel
4645  *   where
4646  *     line time = htotal / dotclock
4647  *     surface width = hdisplay for normal plane and 64 for cursor
4648  *   and latency is assumed to be high, as above.
4649  *
4650  * The final value programmed to the register should always be rounded up,
4651  * and include an extra 2 entries to account for clock crossings.
4652  *
4653  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4654  * to set the non-SR watermarks to 8.
4655  */
4656 void intel_update_watermarks(struct drm_crtc *crtc)
4657 {
4658         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4659
4660         if (dev_priv->display.update_wm)
4661                 dev_priv->display.update_wm(crtc);
4662 }
4663
4664 /*
4665  * Lock protecting IPS related data structures
4666  */
4667 DEFINE_SPINLOCK(mchdev_lock);
4668
4669 /* Global for IPS driver to get at the current i915 device. Protected by
4670  * mchdev_lock. */
4671 static struct drm_i915_private *i915_mch_dev;
4672
4673 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4674 {
4675         u16 rgvswctl;
4676
4677         assert_spin_locked(&mchdev_lock);
4678
4679         rgvswctl = I915_READ16(MEMSWCTL);
4680         if (rgvswctl & MEMCTL_CMD_STS) {
4681                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4682                 return false; /* still busy with another command */
4683         }
4684
4685         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4686                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4687         I915_WRITE16(MEMSWCTL, rgvswctl);
4688         POSTING_READ16(MEMSWCTL);
4689
4690         rgvswctl |= MEMCTL_CMD_STS;
4691         I915_WRITE16(MEMSWCTL, rgvswctl);
4692
4693         return true;
4694 }
4695
4696 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4697 {
4698         u32 rgvmodectl;
4699         u8 fmax, fmin, fstart, vstart;
4700
4701         spin_lock_irq(&mchdev_lock);
4702
4703         rgvmodectl = I915_READ(MEMMODECTL);
4704
4705         /* Enable temp reporting */
4706         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4707         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4708
4709         /* 100ms RC evaluation intervals */
4710         I915_WRITE(RCUPEI, 100000);
4711         I915_WRITE(RCDNEI, 100000);
4712
4713         /* Set max/min thresholds to 90ms and 80ms respectively */
4714         I915_WRITE(RCBMAXAVG, 90000);
4715         I915_WRITE(RCBMINAVG, 80000);
4716
4717         I915_WRITE(MEMIHYST, 1);
4718
4719         /* Set up min, max, and cur for interrupt handling */
4720         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4721         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4722         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4723                 MEMMODE_FSTART_SHIFT;
4724
4725         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4726                 PXVFREQ_PX_SHIFT;
4727
4728         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4729         dev_priv->ips.fstart = fstart;
4730
4731         dev_priv->ips.max_delay = fstart;
4732         dev_priv->ips.min_delay = fmin;
4733         dev_priv->ips.cur_delay = fstart;
4734
4735         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4736                          fmax, fmin, fstart);
4737
4738         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4739
4740         /*
4741          * Interrupts will be enabled in ironlake_irq_postinstall
4742          */
4743
4744         I915_WRITE(VIDSTART, vstart);
4745         POSTING_READ(VIDSTART);
4746
4747         rgvmodectl |= MEMMODE_SWMODE_EN;
4748         I915_WRITE(MEMMODECTL, rgvmodectl);
4749
4750         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4751                 DRM_ERROR("stuck trying to change perf mode\n");
4752         mdelay(1);
4753
4754         ironlake_set_drps(dev_priv, fstart);
4755
4756         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4757                 I915_READ(DDREC) + I915_READ(CSIEC);
4758         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4759         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4760         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4761
4762         spin_unlock_irq(&mchdev_lock);
4763 }
4764
4765 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4766 {
4767         u16 rgvswctl;
4768
4769         spin_lock_irq(&mchdev_lock);
4770
4771         rgvswctl = I915_READ16(MEMSWCTL);
4772
4773         /* Ack interrupts, disable EFC interrupt */
4774         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4775         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4776         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4777         I915_WRITE(DEIIR, DE_PCU_EVENT);
4778         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4779
4780         /* Go back to the starting frequency */
4781         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4782         mdelay(1);
4783         rgvswctl |= MEMCTL_CMD_STS;
4784         I915_WRITE(MEMSWCTL, rgvswctl);
4785         mdelay(1);
4786
4787         spin_unlock_irq(&mchdev_lock);
4788 }
4789
4790 /* There's a funny hw issue where the hw returns all 0 when reading from
4791  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4792  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4793  * all limits and the gpu stuck at whatever frequency it is at atm).
4794  */
4795 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4796 {
4797         u32 limits;
4798
4799         /* Only set the down limit when we've reached the lowest level to avoid
4800          * getting more interrupts, otherwise leave this clear. This prevents a
4801          * race in the hw when coming out of rc6: There's a tiny window where
4802          * the hw runs at the minimal clock before selecting the desired
4803          * frequency, if the down threshold expires in that window we will not
4804          * receive a down interrupt. */
4805         if (IS_GEN9(dev_priv)) {
4806                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4807                 if (val <= dev_priv->rps.min_freq_softlimit)
4808                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4809         } else {
4810                 limits = dev_priv->rps.max_freq_softlimit << 24;
4811                 if (val <= dev_priv->rps.min_freq_softlimit)
4812                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4813         }
4814
4815         return limits;
4816 }
4817
4818 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4819 {
4820         int new_power;
4821         u32 threshold_up = 0, threshold_down = 0; /* in % */
4822         u32 ei_up = 0, ei_down = 0;
4823
4824         new_power = dev_priv->rps.power;
4825         switch (dev_priv->rps.power) {
4826         case LOW_POWER:
4827                 if (val > dev_priv->rps.efficient_freq + 1 &&
4828                     val > dev_priv->rps.cur_freq)
4829                         new_power = BETWEEN;
4830                 break;
4831
4832         case BETWEEN:
4833                 if (val <= dev_priv->rps.efficient_freq &&
4834                     val < dev_priv->rps.cur_freq)
4835                         new_power = LOW_POWER;
4836                 else if (val >= dev_priv->rps.rp0_freq &&
4837                          val > dev_priv->rps.cur_freq)
4838                         new_power = HIGH_POWER;
4839                 break;
4840
4841         case HIGH_POWER:
4842                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4843                     val < dev_priv->rps.cur_freq)
4844                         new_power = BETWEEN;
4845                 break;
4846         }
4847         /* Max/min bins are special */
4848         if (val <= dev_priv->rps.min_freq_softlimit)
4849                 new_power = LOW_POWER;
4850         if (val >= dev_priv->rps.max_freq_softlimit)
4851                 new_power = HIGH_POWER;
4852         if (new_power == dev_priv->rps.power)
4853                 return;
4854
4855         /* Note the units here are not exactly 1us, but 1280ns. */
4856         switch (new_power) {
4857         case LOW_POWER:
4858                 /* Upclock if more than 95% busy over 16ms */
4859                 ei_up = 16000;
4860                 threshold_up = 95;
4861
4862                 /* Downclock if less than 85% busy over 32ms */
4863                 ei_down = 32000;
4864                 threshold_down = 85;
4865                 break;
4866
4867         case BETWEEN:
4868                 /* Upclock if more than 90% busy over 13ms */
4869                 ei_up = 13000;
4870                 threshold_up = 90;
4871
4872                 /* Downclock if less than 75% busy over 32ms */
4873                 ei_down = 32000;
4874                 threshold_down = 75;
4875                 break;
4876
4877         case HIGH_POWER:
4878                 /* Upclock if more than 85% busy over 10ms */
4879                 ei_up = 10000;
4880                 threshold_up = 85;
4881
4882                 /* Downclock if less than 60% busy over 32ms */
4883                 ei_down = 32000;
4884                 threshold_down = 60;
4885                 break;
4886         }
4887
4888         I915_WRITE(GEN6_RP_UP_EI,
4889                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
4890         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4891                    GT_INTERVAL_FROM_US(dev_priv,
4892                                        ei_up * threshold_up / 100));
4893
4894         I915_WRITE(GEN6_RP_DOWN_EI,
4895                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
4896         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4897                    GT_INTERVAL_FROM_US(dev_priv,
4898                                        ei_down * threshold_down / 100));
4899
4900         I915_WRITE(GEN6_RP_CONTROL,
4901                    GEN6_RP_MEDIA_TURBO |
4902                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4903                    GEN6_RP_MEDIA_IS_GFX |
4904                    GEN6_RP_ENABLE |
4905                    GEN6_RP_UP_BUSY_AVG |
4906                    GEN6_RP_DOWN_IDLE_AVG);
4907
4908         dev_priv->rps.power = new_power;
4909         dev_priv->rps.up_threshold = threshold_up;
4910         dev_priv->rps.down_threshold = threshold_down;
4911         dev_priv->rps.last_adj = 0;
4912 }
4913
4914 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4915 {
4916         u32 mask = 0;
4917
4918         if (val > dev_priv->rps.min_freq_softlimit)
4919                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4920         if (val < dev_priv->rps.max_freq_softlimit)
4921                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4922
4923         mask &= dev_priv->pm_rps_events;
4924
4925         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4926 }
4927
4928 /* gen6_set_rps is called to update the frequency request, but should also be
4929  * called when the range (min_delay and max_delay) is modified so that we can
4930  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4931 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4932 {
4933         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4934         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4935                 return;
4936
4937         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4938         WARN_ON(val > dev_priv->rps.max_freq);
4939         WARN_ON(val < dev_priv->rps.min_freq);
4940
4941         /* min/max delay may still have been modified so be sure to
4942          * write the limits value.
4943          */
4944         if (val != dev_priv->rps.cur_freq) {
4945                 gen6_set_rps_thresholds(dev_priv, val);
4946
4947                 if (IS_GEN9(dev_priv))
4948                         I915_WRITE(GEN6_RPNSWREQ,
4949                                    GEN9_FREQUENCY(val));
4950                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4951                         I915_WRITE(GEN6_RPNSWREQ,
4952                                    HSW_FREQUENCY(val));
4953                 else
4954                         I915_WRITE(GEN6_RPNSWREQ,
4955                                    GEN6_FREQUENCY(val) |
4956                                    GEN6_OFFSET(0) |
4957                                    GEN6_AGGRESSIVE_TURBO);
4958         }
4959
4960         /* Make sure we continue to get interrupts
4961          * until we hit the minimum or maximum frequencies.
4962          */
4963         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4964         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4965
4966         POSTING_READ(GEN6_RPNSWREQ);
4967
4968         dev_priv->rps.cur_freq = val;
4969         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4970 }
4971
4972 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4973 {
4974         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4975         WARN_ON(val > dev_priv->rps.max_freq);
4976         WARN_ON(val < dev_priv->rps.min_freq);
4977
4978         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4979                       "Odd GPU freq value\n"))
4980                 val &= ~1;
4981
4982         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4983
4984         if (val != dev_priv->rps.cur_freq) {
4985                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4986                 if (!IS_CHERRYVIEW(dev_priv))
4987                         gen6_set_rps_thresholds(dev_priv, val);
4988         }
4989
4990         dev_priv->rps.cur_freq = val;
4991         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4992 }
4993
4994 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4995  *
4996  * * If Gfx is Idle, then
4997  * 1. Forcewake Media well.
4998  * 2. Request idle freq.
4999  * 3. Release Forcewake of Media well.
5000 */
5001 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5002 {
5003         u32 val = dev_priv->rps.idle_freq;
5004
5005         if (dev_priv->rps.cur_freq <= val)
5006                 return;
5007
5008         /* Wake up the media well, as that takes a lot less
5009          * power than the Render well. */
5010         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5011         valleyview_set_rps(dev_priv, val);
5012         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5013 }
5014
5015 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5016 {
5017         mutex_lock(&dev_priv->rps.hw_lock);
5018         if (dev_priv->rps.enabled) {
5019                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5020                         gen6_rps_reset_ei(dev_priv);
5021                 I915_WRITE(GEN6_PMINTRMSK,
5022                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5023
5024                 gen6_enable_rps_interrupts(dev_priv);
5025
5026                 /* Ensure we start at the user's desired frequency */
5027                 intel_set_rps(dev_priv,
5028                               clamp(dev_priv->rps.cur_freq,
5029                                     dev_priv->rps.min_freq_softlimit,
5030                                     dev_priv->rps.max_freq_softlimit));
5031         }
5032         mutex_unlock(&dev_priv->rps.hw_lock);
5033 }
5034
5035 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5036 {
5037         /* Flush our bottom-half so that it does not race with us
5038          * setting the idle frequency and so that it is bounded by
5039          * our rpm wakeref. And then disable the interrupts to stop any
5040          * futher RPS reclocking whilst we are asleep.
5041          */
5042         gen6_disable_rps_interrupts(dev_priv);
5043
5044         mutex_lock(&dev_priv->rps.hw_lock);
5045         if (dev_priv->rps.enabled) {
5046                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5047                         vlv_set_rps_idle(dev_priv);
5048                 else
5049                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5050                 dev_priv->rps.last_adj = 0;
5051                 I915_WRITE(GEN6_PMINTRMSK,
5052                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5053         }
5054         mutex_unlock(&dev_priv->rps.hw_lock);
5055
5056         spin_lock(&dev_priv->rps.client_lock);
5057         while (!list_empty(&dev_priv->rps.clients))
5058                 list_del_init(dev_priv->rps.clients.next);
5059         spin_unlock(&dev_priv->rps.client_lock);
5060 }
5061
5062 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5063                     struct intel_rps_client *rps,
5064                     unsigned long submitted)
5065 {
5066         /* This is intentionally racy! We peek at the state here, then
5067          * validate inside the RPS worker.
5068          */
5069         if (!(dev_priv->gt.awake &&
5070               dev_priv->rps.enabled &&
5071               dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5072                 return;
5073
5074         /* Force a RPS boost (and don't count it against the client) if
5075          * the GPU is severely congested.
5076          */
5077         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5078                 rps = NULL;
5079
5080         spin_lock(&dev_priv->rps.client_lock);
5081         if (rps == NULL || list_empty(&rps->link)) {
5082                 spin_lock_irq(&dev_priv->irq_lock);
5083                 if (dev_priv->rps.interrupts_enabled) {
5084                         dev_priv->rps.client_boost = true;
5085                         schedule_work(&dev_priv->rps.work);
5086                 }
5087                 spin_unlock_irq(&dev_priv->irq_lock);
5088
5089                 if (rps != NULL) {
5090                         list_add(&rps->link, &dev_priv->rps.clients);
5091                         rps->boosts++;
5092                 } else
5093                         dev_priv->rps.boosts++;
5094         }
5095         spin_unlock(&dev_priv->rps.client_lock);
5096 }
5097
5098 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5099 {
5100         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5101                 valleyview_set_rps(dev_priv, val);
5102         else
5103                 gen6_set_rps(dev_priv, val);
5104 }
5105
5106 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5107 {
5108         I915_WRITE(GEN6_RC_CONTROL, 0);
5109         I915_WRITE(GEN9_PG_ENABLE, 0);
5110 }
5111
5112 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5113 {
5114         I915_WRITE(GEN6_RP_CONTROL, 0);
5115 }
5116
5117 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5118 {
5119         I915_WRITE(GEN6_RC_CONTROL, 0);
5120         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5121         I915_WRITE(GEN6_RP_CONTROL, 0);
5122 }
5123
5124 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5125 {
5126         I915_WRITE(GEN6_RC_CONTROL, 0);
5127 }
5128
5129 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5130 {
5131         /* we're doing forcewake before Disabling RC6,
5132          * This what the BIOS expects when going into suspend */
5133         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5134
5135         I915_WRITE(GEN6_RC_CONTROL, 0);
5136
5137         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5138 }
5139
5140 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5141 {
5142         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5143                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5144                         mode = GEN6_RC_CTL_RC6_ENABLE;
5145                 else
5146                         mode = 0;
5147         }
5148         if (HAS_RC6p(dev_priv))
5149                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5150                                  "RC6 %s RC6p %s RC6pp %s\n",
5151                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5152                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5153                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5154
5155         else
5156                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5157                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5158 }
5159
5160 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5161 {
5162         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5163         bool enable_rc6 = true;
5164         unsigned long rc6_ctx_base;
5165         u32 rc_ctl;
5166         int rc_sw_target;
5167
5168         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5169         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5170                        RC_SW_TARGET_STATE_SHIFT;
5171         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5172                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5173                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5174                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5175                          rc_sw_target);
5176
5177         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5178                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5179                 enable_rc6 = false;
5180         }
5181
5182         /*
5183          * The exact context size is not known for BXT, so assume a page size
5184          * for this check.
5185          */
5186         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5187         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5188               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5189                                         ggtt->stolen_reserved_size))) {
5190                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5191                 enable_rc6 = false;
5192         }
5193
5194         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5195               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5196               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5197               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5198                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5199                 enable_rc6 = false;
5200         }
5201
5202         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5203             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5204             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5205                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5206                 enable_rc6 = false;
5207         }
5208
5209         if (!I915_READ(GEN6_GFXPAUSE)) {
5210                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5211                 enable_rc6 = false;
5212         }
5213
5214         if (!I915_READ(GEN8_MISC_CTRL0)) {
5215                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5216                 enable_rc6 = false;
5217         }
5218
5219         return enable_rc6;
5220 }
5221
5222 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5223 {
5224         /* No RC6 before Ironlake and code is gone for ilk. */
5225         if (INTEL_INFO(dev_priv)->gen < 6)
5226                 return 0;
5227
5228         if (!enable_rc6)
5229                 return 0;
5230
5231         if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5232                 DRM_INFO("RC6 disabled by BIOS\n");
5233                 return 0;
5234         }
5235
5236         /* Respect the kernel parameter if it is set */
5237         if (enable_rc6 >= 0) {
5238                 int mask;
5239
5240                 if (HAS_RC6p(dev_priv))
5241                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5242                                INTEL_RC6pp_ENABLE;
5243                 else
5244                         mask = INTEL_RC6_ENABLE;
5245
5246                 if ((enable_rc6 & mask) != enable_rc6)
5247                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5248                                          "(requested %d, valid %d)\n",
5249                                          enable_rc6 & mask, enable_rc6, mask);
5250
5251                 return enable_rc6 & mask;
5252         }
5253
5254         if (IS_IVYBRIDGE(dev_priv))
5255                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5256
5257         return INTEL_RC6_ENABLE;
5258 }
5259
5260 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5261 {
5262         /* All of these values are in units of 50MHz */
5263
5264         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5265         if (IS_BROXTON(dev_priv)) {
5266                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5267                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5268                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5269                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5270         } else {
5271                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5272                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5273                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5274                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5275         }
5276         /* hw_max = RP0 until we check for overclocking */
5277         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5278
5279         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5280         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5281             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5282                 u32 ddcc_status = 0;
5283
5284                 if (sandybridge_pcode_read(dev_priv,
5285                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5286                                            &ddcc_status) == 0)
5287                         dev_priv->rps.efficient_freq =
5288                                 clamp_t(u8,
5289                                         ((ddcc_status >> 8) & 0xff),
5290                                         dev_priv->rps.min_freq,
5291                                         dev_priv->rps.max_freq);
5292         }
5293
5294         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5295                 /* Store the frequency values in 16.66 MHZ units, which is
5296                  * the natural hardware unit for SKL
5297                  */
5298                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5299                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5300                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5301                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5302                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5303         }
5304 }
5305
5306 static void reset_rps(struct drm_i915_private *dev_priv,
5307                       void (*set)(struct drm_i915_private *, u8))
5308 {
5309         u8 freq = dev_priv->rps.cur_freq;
5310
5311         /* force a reset */
5312         dev_priv->rps.power = -1;
5313         dev_priv->rps.cur_freq = -1;
5314
5315         set(dev_priv, freq);
5316 }
5317
5318 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5319 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5320 {
5321         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5322
5323         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5324         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5325                 /*
5326                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
5327                  * clear out the Control register just to avoid inconsitency
5328                  * with debugfs interface, which will show  Turbo as enabled
5329                  * only and that is not expected by the User after adding the
5330                  * WaGsvDisableTurbo. Apart from this there is no problem even
5331                  * if the Turbo is left enabled in the Control register, as the
5332                  * Up/Down interrupts would remain masked.
5333                  */
5334                 gen9_disable_rps(dev_priv);
5335                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5336                 return;
5337         }
5338
5339         /* Program defaults and thresholds for RPS*/
5340         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5341                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5342
5343         /* 1 second timeout*/
5344         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5345                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5346
5347         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5348
5349         /* Leaning on the below call to gen6_set_rps to program/setup the
5350          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5351          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5352         reset_rps(dev_priv, gen6_set_rps);
5353
5354         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5355 }
5356
5357 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5358 {
5359         struct intel_engine_cs *engine;
5360         uint32_t rc6_mask = 0;
5361
5362         /* 1a: Software RC state - RC0 */
5363         I915_WRITE(GEN6_RC_STATE, 0);
5364
5365         /* 1b: Get forcewake during program sequence. Although the driver
5366          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5367         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5368
5369         /* 2a: Disable RC states. */
5370         I915_WRITE(GEN6_RC_CONTROL, 0);
5371
5372         /* 2b: Program RC6 thresholds.*/
5373
5374         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5375         if (IS_SKYLAKE(dev_priv))
5376                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5377         else
5378                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5379         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5380         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5381         for_each_engine(engine, dev_priv)
5382                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5383
5384         if (HAS_GUC(dev_priv))
5385                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5386
5387         I915_WRITE(GEN6_RC_SLEEP, 0);
5388
5389         /* 2c: Program Coarse Power Gating Policies. */
5390         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5391         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5392
5393         /* 3a: Enable RC6 */
5394         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5395                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5396         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5397         /* WaRsUseTimeoutMode */
5398         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5399             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5400                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5401                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5402                            GEN7_RC_CTL_TO_MODE |
5403                            rc6_mask);
5404         } else {
5405                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5406                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5407                            GEN6_RC_CTL_EI_MODE(1) |
5408                            rc6_mask);
5409         }
5410
5411         /*
5412          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5413          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5414          */
5415         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5416                 I915_WRITE(GEN9_PG_ENABLE, 0);
5417         else
5418                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5419                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5420
5421         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5422 }
5423
5424 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5425 {
5426         struct intel_engine_cs *engine;
5427         uint32_t rc6_mask = 0;
5428
5429         /* 1a: Software RC state - RC0 */
5430         I915_WRITE(GEN6_RC_STATE, 0);
5431
5432         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5433          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5434         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5435
5436         /* 2a: Disable RC states. */
5437         I915_WRITE(GEN6_RC_CONTROL, 0);
5438
5439         /* 2b: Program RC6 thresholds.*/
5440         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5441         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5442         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5443         for_each_engine(engine, dev_priv)
5444                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5445         I915_WRITE(GEN6_RC_SLEEP, 0);
5446         if (IS_BROADWELL(dev_priv))
5447                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5448         else
5449                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5450
5451         /* 3: Enable RC6 */
5452         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5453                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5454         intel_print_rc6_info(dev_priv, rc6_mask);
5455         if (IS_BROADWELL(dev_priv))
5456                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5457                                 GEN7_RC_CTL_TO_MODE |
5458                                 rc6_mask);
5459         else
5460                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5461                                 GEN6_RC_CTL_EI_MODE(1) |
5462                                 rc6_mask);
5463
5464         /* 4 Program defaults and thresholds for RPS*/
5465         I915_WRITE(GEN6_RPNSWREQ,
5466                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5467         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5468                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5469         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5470         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5471
5472         /* Docs recommend 900MHz, and 300 MHz respectively */
5473         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5474                    dev_priv->rps.max_freq_softlimit << 24 |
5475                    dev_priv->rps.min_freq_softlimit << 16);
5476
5477         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5478         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5479         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5480         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5481
5482         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5483
5484         /* 5: Enable RPS */
5485         I915_WRITE(GEN6_RP_CONTROL,
5486                    GEN6_RP_MEDIA_TURBO |
5487                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5488                    GEN6_RP_MEDIA_IS_GFX |
5489                    GEN6_RP_ENABLE |
5490                    GEN6_RP_UP_BUSY_AVG |
5491                    GEN6_RP_DOWN_IDLE_AVG);
5492
5493         /* 6: Ring frequency + overclocking (our driver does this later */
5494
5495         reset_rps(dev_priv, gen6_set_rps);
5496
5497         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5498 }
5499
5500 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5501 {
5502         struct intel_engine_cs *engine;
5503         u32 rc6vids, rc6_mask = 0;
5504         u32 gtfifodbg;
5505         int rc6_mode;
5506         int ret;
5507
5508         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5509
5510         /* Here begins a magic sequence of register writes to enable
5511          * auto-downclocking.
5512          *
5513          * Perhaps there might be some value in exposing these to
5514          * userspace...
5515          */
5516         I915_WRITE(GEN6_RC_STATE, 0);
5517
5518         /* Clear the DBG now so we don't confuse earlier errors */
5519         gtfifodbg = I915_READ(GTFIFODBG);
5520         if (gtfifodbg) {
5521                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5522                 I915_WRITE(GTFIFODBG, gtfifodbg);
5523         }
5524
5525         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5526
5527         /* disable the counters and set deterministic thresholds */
5528         I915_WRITE(GEN6_RC_CONTROL, 0);
5529
5530         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5531         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5532         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5533         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5534         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5535
5536         for_each_engine(engine, dev_priv)
5537                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5538
5539         I915_WRITE(GEN6_RC_SLEEP, 0);
5540         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5541         if (IS_IVYBRIDGE(dev_priv))
5542                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5543         else
5544                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5545         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5546         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5547
5548         /* Check if we are enabling RC6 */
5549         rc6_mode = intel_enable_rc6();
5550         if (rc6_mode & INTEL_RC6_ENABLE)
5551                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5552
5553         /* We don't use those on Haswell */
5554         if (!IS_HASWELL(dev_priv)) {
5555                 if (rc6_mode & INTEL_RC6p_ENABLE)
5556                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5557
5558                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5559                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5560         }
5561
5562         intel_print_rc6_info(dev_priv, rc6_mask);
5563
5564         I915_WRITE(GEN6_RC_CONTROL,
5565                    rc6_mask |
5566                    GEN6_RC_CTL_EI_MODE(1) |
5567                    GEN6_RC_CTL_HW_ENABLE);
5568
5569         /* Power down if completely idle for over 50ms */
5570         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5571         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5572
5573         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5574         if (ret)
5575                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5576
5577         reset_rps(dev_priv, gen6_set_rps);
5578
5579         rc6vids = 0;
5580         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5581         if (IS_GEN6(dev_priv) && ret) {
5582                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5583         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5584                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5585                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5586                 rc6vids &= 0xffff00;
5587                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5588                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5589                 if (ret)
5590                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5591         }
5592
5593         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5594 }
5595
5596 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5597 {
5598         int min_freq = 15;
5599         unsigned int gpu_freq;
5600         unsigned int max_ia_freq, min_ring_freq;
5601         unsigned int max_gpu_freq, min_gpu_freq;
5602         int scaling_factor = 180;
5603         struct cpufreq_policy *policy;
5604
5605         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5606
5607         policy = cpufreq_cpu_get(0);
5608         if (policy) {
5609                 max_ia_freq = policy->cpuinfo.max_freq;
5610                 cpufreq_cpu_put(policy);
5611         } else {
5612                 /*
5613                  * Default to measured freq if none found, PCU will ensure we
5614                  * don't go over
5615                  */
5616                 max_ia_freq = tsc_khz;
5617         }
5618
5619         /* Convert from kHz to MHz */
5620         max_ia_freq /= 1000;
5621
5622         min_ring_freq = I915_READ(DCLK) & 0xf;
5623         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5624         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5625
5626         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5627                 /* Convert GT frequency to 50 HZ units */
5628                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5629                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5630         } else {
5631                 min_gpu_freq = dev_priv->rps.min_freq;
5632                 max_gpu_freq = dev_priv->rps.max_freq;
5633         }
5634
5635         /*
5636          * For each potential GPU frequency, load a ring frequency we'd like
5637          * to use for memory access.  We do this by specifying the IA frequency
5638          * the PCU should use as a reference to determine the ring frequency.
5639          */
5640         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5641                 int diff = max_gpu_freq - gpu_freq;
5642                 unsigned int ia_freq = 0, ring_freq = 0;
5643
5644                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5645                         /*
5646                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5647                          * No floor required for ring frequency on SKL.
5648                          */
5649                         ring_freq = gpu_freq;
5650                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5651                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5652                         ring_freq = max(min_ring_freq, gpu_freq);
5653                 } else if (IS_HASWELL(dev_priv)) {
5654                         ring_freq = mult_frac(gpu_freq, 5, 4);
5655                         ring_freq = max(min_ring_freq, ring_freq);
5656                         /* leave ia_freq as the default, chosen by cpufreq */
5657                 } else {
5658                         /* On older processors, there is no separate ring
5659                          * clock domain, so in order to boost the bandwidth
5660                          * of the ring, we need to upclock the CPU (ia_freq).
5661                          *
5662                          * For GPU frequencies less than 750MHz,
5663                          * just use the lowest ring freq.
5664                          */
5665                         if (gpu_freq < min_freq)
5666                                 ia_freq = 800;
5667                         else
5668                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5669                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5670                 }
5671
5672                 sandybridge_pcode_write(dev_priv,
5673                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5674                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5675                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5676                                         gpu_freq);
5677         }
5678 }
5679
5680 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5681 {
5682         u32 val, rp0;
5683
5684         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5685
5686         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5687         case 8:
5688                 /* (2 * 4) config */
5689                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5690                 break;
5691         case 12:
5692                 /* (2 * 6) config */
5693                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5694                 break;
5695         case 16:
5696                 /* (2 * 8) config */
5697         default:
5698                 /* Setting (2 * 8) Min RP0 for any other combination */
5699                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5700                 break;
5701         }
5702
5703         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5704
5705         return rp0;
5706 }
5707
5708 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5709 {
5710         u32 val, rpe;
5711
5712         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5713         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5714
5715         return rpe;
5716 }
5717
5718 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5719 {
5720         u32 val, rp1;
5721
5722         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5723         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5724
5725         return rp1;
5726 }
5727
5728 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5729 {
5730         u32 val, rp1;
5731
5732         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5733
5734         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5735
5736         return rp1;
5737 }
5738
5739 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5740 {
5741         u32 val, rp0;
5742
5743         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5744
5745         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5746         /* Clamp to max */
5747         rp0 = min_t(u32, rp0, 0xea);
5748
5749         return rp0;
5750 }
5751
5752 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5753 {
5754         u32 val, rpe;
5755
5756         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5757         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5758         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5759         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5760
5761         return rpe;
5762 }
5763
5764 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5765 {
5766         u32 val;
5767
5768         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5769         /*
5770          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5771          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5772          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5773          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5774          * to make sure it matches what Punit accepts.
5775          */
5776         return max_t(u32, val, 0xc0);
5777 }
5778
5779 /* Check that the pctx buffer wasn't move under us. */
5780 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5781 {
5782         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5783
5784         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5785                              dev_priv->vlv_pctx->stolen->start);
5786 }
5787
5788
5789 /* Check that the pcbr address is not empty. */
5790 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5791 {
5792         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5793
5794         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5795 }
5796
5797 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5798 {
5799         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5800         unsigned long pctx_paddr, paddr;
5801         u32 pcbr;
5802         int pctx_size = 32*1024;
5803
5804         pcbr = I915_READ(VLV_PCBR);
5805         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5806                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5807                 paddr = (dev_priv->mm.stolen_base +
5808                          (ggtt->stolen_size - pctx_size));
5809
5810                 pctx_paddr = (paddr & (~4095));
5811                 I915_WRITE(VLV_PCBR, pctx_paddr);
5812         }
5813
5814         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5815 }
5816
5817 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5818 {
5819         struct drm_i915_gem_object *pctx;
5820         unsigned long pctx_paddr;
5821         u32 pcbr;
5822         int pctx_size = 24*1024;
5823
5824         pcbr = I915_READ(VLV_PCBR);
5825         if (pcbr) {
5826                 /* BIOS set it up already, grab the pre-alloc'd space */
5827                 int pcbr_offset;
5828
5829                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5830                 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5831                                                                       pcbr_offset,
5832                                                                       I915_GTT_OFFSET_NONE,
5833                                                                       pctx_size);
5834                 goto out;
5835         }
5836
5837         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5838
5839         /*
5840          * From the Gunit register HAS:
5841          * The Gfx driver is expected to program this register and ensure
5842          * proper allocation within Gfx stolen memory.  For example, this
5843          * register should be programmed such than the PCBR range does not
5844          * overlap with other ranges, such as the frame buffer, protected
5845          * memory, or any other relevant ranges.
5846          */
5847         pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5848         if (!pctx) {
5849                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5850                 goto out;
5851         }
5852
5853         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5854         I915_WRITE(VLV_PCBR, pctx_paddr);
5855
5856 out:
5857         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5858         dev_priv->vlv_pctx = pctx;
5859 }
5860
5861 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5862 {
5863         if (WARN_ON(!dev_priv->vlv_pctx))
5864                 return;
5865
5866         i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
5867         dev_priv->vlv_pctx = NULL;
5868 }
5869
5870 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5871 {
5872         dev_priv->rps.gpll_ref_freq =
5873                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5874                                   CCK_GPLL_CLOCK_CONTROL,
5875                                   dev_priv->czclk_freq);
5876
5877         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5878                          dev_priv->rps.gpll_ref_freq);
5879 }
5880
5881 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5882 {
5883         u32 val;
5884
5885         valleyview_setup_pctx(dev_priv);
5886
5887         vlv_init_gpll_ref_freq(dev_priv);
5888
5889         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5890         switch ((val >> 6) & 3) {
5891         case 0:
5892         case 1:
5893                 dev_priv->mem_freq = 800;
5894                 break;
5895         case 2:
5896                 dev_priv->mem_freq = 1066;
5897                 break;
5898         case 3:
5899                 dev_priv->mem_freq = 1333;
5900                 break;
5901         }
5902         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5903
5904         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5905         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5906         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5907                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5908                          dev_priv->rps.max_freq);
5909
5910         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5911         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5912                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5913                          dev_priv->rps.efficient_freq);
5914
5915         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5916         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5917                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5918                          dev_priv->rps.rp1_freq);
5919
5920         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5921         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5922                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5923                          dev_priv->rps.min_freq);
5924 }
5925
5926 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5927 {
5928         u32 val;
5929
5930         cherryview_setup_pctx(dev_priv);
5931
5932         vlv_init_gpll_ref_freq(dev_priv);
5933
5934         mutex_lock(&dev_priv->sb_lock);
5935         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5936         mutex_unlock(&dev_priv->sb_lock);
5937
5938         switch ((val >> 2) & 0x7) {
5939         case 3:
5940                 dev_priv->mem_freq = 2000;
5941                 break;
5942         default:
5943                 dev_priv->mem_freq = 1600;
5944                 break;
5945         }
5946         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5947
5948         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5949         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5950         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5951                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5952                          dev_priv->rps.max_freq);
5953
5954         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5955         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5956                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5957                          dev_priv->rps.efficient_freq);
5958
5959         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5960         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5961                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5962                          dev_priv->rps.rp1_freq);
5963
5964         /* PUnit validated range is only [RPe, RP0] */
5965         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5966         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5967                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5968                          dev_priv->rps.min_freq);
5969
5970         WARN_ONCE((dev_priv->rps.max_freq |
5971                    dev_priv->rps.efficient_freq |
5972                    dev_priv->rps.rp1_freq |
5973                    dev_priv->rps.min_freq) & 1,
5974                   "Odd GPU freq values\n");
5975 }
5976
5977 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5978 {
5979         valleyview_cleanup_pctx(dev_priv);
5980 }
5981
5982 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5983 {
5984         struct intel_engine_cs *engine;
5985         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5986
5987         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5988
5989         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5990                                              GT_FIFO_FREE_ENTRIES_CHV);
5991         if (gtfifodbg) {
5992                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5993                                  gtfifodbg);
5994                 I915_WRITE(GTFIFODBG, gtfifodbg);
5995         }
5996
5997         cherryview_check_pctx(dev_priv);
5998
5999         /* 1a & 1b: Get forcewake during program sequence. Although the driver
6000          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6001         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6002
6003         /*  Disable RC states. */
6004         I915_WRITE(GEN6_RC_CONTROL, 0);
6005
6006         /* 2a: Program RC6 thresholds.*/
6007         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6008         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6009         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6010
6011         for_each_engine(engine, dev_priv)
6012                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6013         I915_WRITE(GEN6_RC_SLEEP, 0);
6014
6015         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6016         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6017
6018         /* allows RC6 residency counter to work */
6019         I915_WRITE(VLV_COUNTER_CONTROL,
6020                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6021                                       VLV_MEDIA_RC6_COUNT_EN |
6022                                       VLV_RENDER_RC6_COUNT_EN));
6023
6024         /* For now we assume BIOS is allocating and populating the PCBR  */
6025         pcbr = I915_READ(VLV_PCBR);
6026
6027         /* 3: Enable RC6 */
6028         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6029             (pcbr >> VLV_PCBR_ADDR_SHIFT))
6030                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6031
6032         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6033
6034         /* 4 Program defaults and thresholds for RPS*/
6035         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6036         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6037         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6038         I915_WRITE(GEN6_RP_UP_EI, 66000);
6039         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6040
6041         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6042
6043         /* 5: Enable RPS */
6044         I915_WRITE(GEN6_RP_CONTROL,
6045                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6046                    GEN6_RP_MEDIA_IS_GFX |
6047                    GEN6_RP_ENABLE |
6048                    GEN6_RP_UP_BUSY_AVG |
6049                    GEN6_RP_DOWN_IDLE_AVG);
6050
6051         /* Setting Fixed Bias */
6052         val = VLV_OVERRIDE_EN |
6053                   VLV_SOC_TDP_EN |
6054                   CHV_BIAS_CPU_50_SOC_50;
6055         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6056
6057         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6058
6059         /* RPS code assumes GPLL is used */
6060         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6061
6062         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6063         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6064
6065         reset_rps(dev_priv, valleyview_set_rps);
6066
6067         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6068 }
6069
6070 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6071 {
6072         struct intel_engine_cs *engine;
6073         u32 gtfifodbg, val, rc6_mode = 0;
6074
6075         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6076
6077         valleyview_check_pctx(dev_priv);
6078
6079         gtfifodbg = I915_READ(GTFIFODBG);
6080         if (gtfifodbg) {
6081                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6082                                  gtfifodbg);
6083                 I915_WRITE(GTFIFODBG, gtfifodbg);
6084         }
6085
6086         /* If VLV, Forcewake all wells, else re-direct to regular path */
6087         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6088
6089         /*  Disable RC states. */
6090         I915_WRITE(GEN6_RC_CONTROL, 0);
6091
6092         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6093         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6094         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6095         I915_WRITE(GEN6_RP_UP_EI, 66000);
6096         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6097
6098         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6099
6100         I915_WRITE(GEN6_RP_CONTROL,
6101                    GEN6_RP_MEDIA_TURBO |
6102                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6103                    GEN6_RP_MEDIA_IS_GFX |
6104                    GEN6_RP_ENABLE |
6105                    GEN6_RP_UP_BUSY_AVG |
6106                    GEN6_RP_DOWN_IDLE_CONT);
6107
6108         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6109         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6110         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6111
6112         for_each_engine(engine, dev_priv)
6113                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6114
6115         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6116
6117         /* allows RC6 residency counter to work */
6118         I915_WRITE(VLV_COUNTER_CONTROL,
6119                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6120                                       VLV_RENDER_RC0_COUNT_EN |
6121                                       VLV_MEDIA_RC6_COUNT_EN |
6122                                       VLV_RENDER_RC6_COUNT_EN));
6123
6124         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6125                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6126
6127         intel_print_rc6_info(dev_priv, rc6_mode);
6128
6129         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6130
6131         /* Setting Fixed Bias */
6132         val = VLV_OVERRIDE_EN |
6133                   VLV_SOC_TDP_EN |
6134                   VLV_BIAS_CPU_125_SOC_875;
6135         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6136
6137         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6138
6139         /* RPS code assumes GPLL is used */
6140         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6141
6142         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6143         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6144
6145         reset_rps(dev_priv, valleyview_set_rps);
6146
6147         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6148 }
6149
6150 static unsigned long intel_pxfreq(u32 vidfreq)
6151 {
6152         unsigned long freq;
6153         int div = (vidfreq & 0x3f0000) >> 16;
6154         int post = (vidfreq & 0x3000) >> 12;
6155         int pre = (vidfreq & 0x7);
6156
6157         if (!pre)
6158                 return 0;
6159
6160         freq = ((div * 133333) / ((1<<post) * pre));
6161
6162         return freq;
6163 }
6164
6165 static const struct cparams {
6166         u16 i;
6167         u16 t;
6168         u16 m;
6169         u16 c;
6170 } cparams[] = {
6171         { 1, 1333, 301, 28664 },
6172         { 1, 1066, 294, 24460 },
6173         { 1, 800, 294, 25192 },
6174         { 0, 1333, 276, 27605 },
6175         { 0, 1066, 276, 27605 },
6176         { 0, 800, 231, 23784 },
6177 };
6178
6179 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6180 {
6181         u64 total_count, diff, ret;
6182         u32 count1, count2, count3, m = 0, c = 0;
6183         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6184         int i;
6185
6186         assert_spin_locked(&mchdev_lock);
6187
6188         diff1 = now - dev_priv->ips.last_time1;
6189
6190         /* Prevent division-by-zero if we are asking too fast.
6191          * Also, we don't get interesting results if we are polling
6192          * faster than once in 10ms, so just return the saved value
6193          * in such cases.
6194          */
6195         if (diff1 <= 10)
6196                 return dev_priv->ips.chipset_power;
6197
6198         count1 = I915_READ(DMIEC);
6199         count2 = I915_READ(DDREC);
6200         count3 = I915_READ(CSIEC);
6201
6202         total_count = count1 + count2 + count3;
6203
6204         /* FIXME: handle per-counter overflow */
6205         if (total_count < dev_priv->ips.last_count1) {
6206                 diff = ~0UL - dev_priv->ips.last_count1;
6207                 diff += total_count;
6208         } else {
6209                 diff = total_count - dev_priv->ips.last_count1;
6210         }
6211
6212         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6213                 if (cparams[i].i == dev_priv->ips.c_m &&
6214                     cparams[i].t == dev_priv->ips.r_t) {
6215                         m = cparams[i].m;
6216                         c = cparams[i].c;
6217                         break;
6218                 }
6219         }
6220
6221         diff = div_u64(diff, diff1);
6222         ret = ((m * diff) + c);
6223         ret = div_u64(ret, 10);
6224
6225         dev_priv->ips.last_count1 = total_count;
6226         dev_priv->ips.last_time1 = now;
6227
6228         dev_priv->ips.chipset_power = ret;
6229
6230         return ret;
6231 }
6232
6233 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6234 {
6235         unsigned long val;
6236
6237         if (INTEL_INFO(dev_priv)->gen != 5)
6238                 return 0;
6239
6240         spin_lock_irq(&mchdev_lock);
6241
6242         val = __i915_chipset_val(dev_priv);
6243
6244         spin_unlock_irq(&mchdev_lock);
6245
6246         return val;
6247 }
6248
6249 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6250 {
6251         unsigned long m, x, b;
6252         u32 tsfs;
6253
6254         tsfs = I915_READ(TSFS);
6255
6256         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6257         x = I915_READ8(TR1);
6258
6259         b = tsfs & TSFS_INTR_MASK;
6260
6261         return ((m * x) / 127) - b;
6262 }
6263
6264 static int _pxvid_to_vd(u8 pxvid)
6265 {
6266         if (pxvid == 0)
6267                 return 0;
6268
6269         if (pxvid >= 8 && pxvid < 31)
6270                 pxvid = 31;
6271
6272         return (pxvid + 2) * 125;
6273 }
6274
6275 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6276 {
6277         const int vd = _pxvid_to_vd(pxvid);
6278         const int vm = vd - 1125;
6279
6280         if (INTEL_INFO(dev_priv)->is_mobile)
6281                 return vm > 0 ? vm : 0;
6282
6283         return vd;
6284 }
6285
6286 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6287 {
6288         u64 now, diff, diffms;
6289         u32 count;
6290
6291         assert_spin_locked(&mchdev_lock);
6292
6293         now = ktime_get_raw_ns();
6294         diffms = now - dev_priv->ips.last_time2;
6295         do_div(diffms, NSEC_PER_MSEC);
6296
6297         /* Don't divide by 0 */
6298         if (!diffms)
6299                 return;
6300
6301         count = I915_READ(GFXEC);
6302
6303         if (count < dev_priv->ips.last_count2) {
6304                 diff = ~0UL - dev_priv->ips.last_count2;
6305                 diff += count;
6306         } else {
6307                 diff = count - dev_priv->ips.last_count2;
6308         }
6309
6310         dev_priv->ips.last_count2 = count;
6311         dev_priv->ips.last_time2 = now;
6312
6313         /* More magic constants... */
6314         diff = diff * 1181;
6315         diff = div_u64(diff, diffms * 10);
6316         dev_priv->ips.gfx_power = diff;
6317 }
6318
6319 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6320 {
6321         if (INTEL_INFO(dev_priv)->gen != 5)
6322                 return;
6323
6324         spin_lock_irq(&mchdev_lock);
6325
6326         __i915_update_gfx_val(dev_priv);
6327
6328         spin_unlock_irq(&mchdev_lock);
6329 }
6330
6331 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6332 {
6333         unsigned long t, corr, state1, corr2, state2;
6334         u32 pxvid, ext_v;
6335
6336         assert_spin_locked(&mchdev_lock);
6337
6338         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6339         pxvid = (pxvid >> 24) & 0x7f;
6340         ext_v = pvid_to_extvid(dev_priv, pxvid);
6341
6342         state1 = ext_v;
6343
6344         t = i915_mch_val(dev_priv);
6345
6346         /* Revel in the empirically derived constants */
6347
6348         /* Correction factor in 1/100000 units */
6349         if (t > 80)
6350                 corr = ((t * 2349) + 135940);
6351         else if (t >= 50)
6352                 corr = ((t * 964) + 29317);
6353         else /* < 50 */
6354                 corr = ((t * 301) + 1004);
6355
6356         corr = corr * ((150142 * state1) / 10000 - 78642);
6357         corr /= 100000;
6358         corr2 = (corr * dev_priv->ips.corr);
6359
6360         state2 = (corr2 * state1) / 10000;
6361         state2 /= 100; /* convert to mW */
6362
6363         __i915_update_gfx_val(dev_priv);
6364
6365         return dev_priv->ips.gfx_power + state2;
6366 }
6367
6368 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6369 {
6370         unsigned long val;
6371
6372         if (INTEL_INFO(dev_priv)->gen != 5)
6373                 return 0;
6374
6375         spin_lock_irq(&mchdev_lock);
6376
6377         val = __i915_gfx_val(dev_priv);
6378
6379         spin_unlock_irq(&mchdev_lock);
6380
6381         return val;
6382 }
6383
6384 /**
6385  * i915_read_mch_val - return value for IPS use
6386  *
6387  * Calculate and return a value for the IPS driver to use when deciding whether
6388  * we have thermal and power headroom to increase CPU or GPU power budget.
6389  */
6390 unsigned long i915_read_mch_val(void)
6391 {
6392         struct drm_i915_private *dev_priv;
6393         unsigned long chipset_val, graphics_val, ret = 0;
6394
6395         spin_lock_irq(&mchdev_lock);
6396         if (!i915_mch_dev)
6397                 goto out_unlock;
6398         dev_priv = i915_mch_dev;
6399
6400         chipset_val = __i915_chipset_val(dev_priv);
6401         graphics_val = __i915_gfx_val(dev_priv);
6402
6403         ret = chipset_val + graphics_val;
6404
6405 out_unlock:
6406         spin_unlock_irq(&mchdev_lock);
6407
6408         return ret;
6409 }
6410 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6411
6412 /**
6413  * i915_gpu_raise - raise GPU frequency limit
6414  *
6415  * Raise the limit; IPS indicates we have thermal headroom.
6416  */
6417 bool i915_gpu_raise(void)
6418 {
6419         struct drm_i915_private *dev_priv;
6420         bool ret = true;
6421
6422         spin_lock_irq(&mchdev_lock);
6423         if (!i915_mch_dev) {
6424                 ret = false;
6425                 goto out_unlock;
6426         }
6427         dev_priv = i915_mch_dev;
6428
6429         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6430                 dev_priv->ips.max_delay--;
6431
6432 out_unlock:
6433         spin_unlock_irq(&mchdev_lock);
6434
6435         return ret;
6436 }
6437 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6438
6439 /**
6440  * i915_gpu_lower - lower GPU frequency limit
6441  *
6442  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6443  * frequency maximum.
6444  */
6445 bool i915_gpu_lower(void)
6446 {
6447         struct drm_i915_private *dev_priv;
6448         bool ret = true;
6449
6450         spin_lock_irq(&mchdev_lock);
6451         if (!i915_mch_dev) {
6452                 ret = false;
6453                 goto out_unlock;
6454         }
6455         dev_priv = i915_mch_dev;
6456
6457         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6458                 dev_priv->ips.max_delay++;
6459
6460 out_unlock:
6461         spin_unlock_irq(&mchdev_lock);
6462
6463         return ret;
6464 }
6465 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6466
6467 /**
6468  * i915_gpu_busy - indicate GPU business to IPS
6469  *
6470  * Tell the IPS driver whether or not the GPU is busy.
6471  */
6472 bool i915_gpu_busy(void)
6473 {
6474         bool ret = false;
6475
6476         spin_lock_irq(&mchdev_lock);
6477         if (i915_mch_dev)
6478                 ret = i915_mch_dev->gt.awake;
6479         spin_unlock_irq(&mchdev_lock);
6480
6481         return ret;
6482 }
6483 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6484
6485 /**
6486  * i915_gpu_turbo_disable - disable graphics turbo
6487  *
6488  * Disable graphics turbo by resetting the max frequency and setting the
6489  * current frequency to the default.
6490  */
6491 bool i915_gpu_turbo_disable(void)
6492 {
6493         struct drm_i915_private *dev_priv;
6494         bool ret = true;
6495
6496         spin_lock_irq(&mchdev_lock);
6497         if (!i915_mch_dev) {
6498                 ret = false;
6499                 goto out_unlock;
6500         }
6501         dev_priv = i915_mch_dev;
6502
6503         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6504
6505         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6506                 ret = false;
6507
6508 out_unlock:
6509         spin_unlock_irq(&mchdev_lock);
6510
6511         return ret;
6512 }
6513 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6514
6515 /**
6516  * Tells the intel_ips driver that the i915 driver is now loaded, if
6517  * IPS got loaded first.
6518  *
6519  * This awkward dance is so that neither module has to depend on the
6520  * other in order for IPS to do the appropriate communication of
6521  * GPU turbo limits to i915.
6522  */
6523 static void
6524 ips_ping_for_i915_load(void)
6525 {
6526         void (*link)(void);
6527
6528         link = symbol_get(ips_link_to_i915_driver);
6529         if (link) {
6530                 link();
6531                 symbol_put(ips_link_to_i915_driver);
6532         }
6533 }
6534
6535 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6536 {
6537         /* We only register the i915 ips part with intel-ips once everything is
6538          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6539         spin_lock_irq(&mchdev_lock);
6540         i915_mch_dev = dev_priv;
6541         spin_unlock_irq(&mchdev_lock);
6542
6543         ips_ping_for_i915_load();
6544 }
6545
6546 void intel_gpu_ips_teardown(void)
6547 {
6548         spin_lock_irq(&mchdev_lock);
6549         i915_mch_dev = NULL;
6550         spin_unlock_irq(&mchdev_lock);
6551 }
6552
6553 static void intel_init_emon(struct drm_i915_private *dev_priv)
6554 {
6555         u32 lcfuse;
6556         u8 pxw[16];
6557         int i;
6558
6559         /* Disable to program */
6560         I915_WRITE(ECR, 0);
6561         POSTING_READ(ECR);
6562
6563         /* Program energy weights for various events */
6564         I915_WRITE(SDEW, 0x15040d00);
6565         I915_WRITE(CSIEW0, 0x007f0000);
6566         I915_WRITE(CSIEW1, 0x1e220004);
6567         I915_WRITE(CSIEW2, 0x04000004);
6568
6569         for (i = 0; i < 5; i++)
6570                 I915_WRITE(PEW(i), 0);
6571         for (i = 0; i < 3; i++)
6572                 I915_WRITE(DEW(i), 0);
6573
6574         /* Program P-state weights to account for frequency power adjustment */
6575         for (i = 0; i < 16; i++) {
6576                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6577                 unsigned long freq = intel_pxfreq(pxvidfreq);
6578                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6579                         PXVFREQ_PX_SHIFT;
6580                 unsigned long val;
6581
6582                 val = vid * vid;
6583                 val *= (freq / 1000);
6584                 val *= 255;
6585                 val /= (127*127*900);
6586                 if (val > 0xff)
6587                         DRM_ERROR("bad pxval: %ld\n", val);
6588                 pxw[i] = val;
6589         }
6590         /* Render standby states get 0 weight */
6591         pxw[14] = 0;
6592         pxw[15] = 0;
6593
6594         for (i = 0; i < 4; i++) {
6595                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6596                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6597                 I915_WRITE(PXW(i), val);
6598         }
6599
6600         /* Adjust magic regs to magic values (more experimental results) */
6601         I915_WRITE(OGW0, 0);
6602         I915_WRITE(OGW1, 0);
6603         I915_WRITE(EG0, 0x00007f00);
6604         I915_WRITE(EG1, 0x0000000e);
6605         I915_WRITE(EG2, 0x000e0000);
6606         I915_WRITE(EG3, 0x68000300);
6607         I915_WRITE(EG4, 0x42000000);
6608         I915_WRITE(EG5, 0x00140031);
6609         I915_WRITE(EG6, 0);
6610         I915_WRITE(EG7, 0);
6611
6612         for (i = 0; i < 8; i++)
6613                 I915_WRITE(PXWL(i), 0);
6614
6615         /* Enable PMON + select events */
6616         I915_WRITE(ECR, 0x80000019);
6617
6618         lcfuse = I915_READ(LCFUSE02);
6619
6620         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6621 }
6622
6623 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6624 {
6625         /*
6626          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6627          * requirement.
6628          */
6629         if (!i915.enable_rc6) {
6630                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6631                 intel_runtime_pm_get(dev_priv);
6632         }
6633
6634         mutex_lock(&dev_priv->drm.struct_mutex);
6635         mutex_lock(&dev_priv->rps.hw_lock);
6636
6637         /* Initialize RPS limits (for userspace) */
6638         if (IS_CHERRYVIEW(dev_priv))
6639                 cherryview_init_gt_powersave(dev_priv);
6640         else if (IS_VALLEYVIEW(dev_priv))
6641                 valleyview_init_gt_powersave(dev_priv);
6642         else if (INTEL_GEN(dev_priv) >= 6)
6643                 gen6_init_rps_frequencies(dev_priv);
6644
6645         /* Derive initial user preferences/limits from the hardware limits */
6646         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6647         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6648
6649         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6650         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6651
6652         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6653                 dev_priv->rps.min_freq_softlimit =
6654                         max_t(int,
6655                               dev_priv->rps.efficient_freq,
6656                               intel_freq_opcode(dev_priv, 450));
6657
6658         /* After setting max-softlimit, find the overclock max freq */
6659         if (IS_GEN6(dev_priv) ||
6660             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6661                 u32 params = 0;
6662
6663                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6664                 if (params & BIT(31)) { /* OC supported */
6665                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6666                                          (dev_priv->rps.max_freq & 0xff) * 50,
6667                                          (params & 0xff) * 50);
6668                         dev_priv->rps.max_freq = params & 0xff;
6669                 }
6670         }
6671
6672         /* Finally allow us to boost to max by default */
6673         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6674
6675         mutex_unlock(&dev_priv->rps.hw_lock);
6676         mutex_unlock(&dev_priv->drm.struct_mutex);
6677
6678         intel_autoenable_gt_powersave(dev_priv);
6679 }
6680
6681 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6682 {
6683         if (IS_VALLEYVIEW(dev_priv))
6684                 valleyview_cleanup_gt_powersave(dev_priv);
6685
6686         if (!i915.enable_rc6)
6687                 intel_runtime_pm_put(dev_priv);
6688 }
6689
6690 /**
6691  * intel_suspend_gt_powersave - suspend PM work and helper threads
6692  * @dev_priv: i915 device
6693  *
6694  * We don't want to disable RC6 or other features here, we just want
6695  * to make sure any work we've queued has finished and won't bother
6696  * us while we're suspended.
6697  */
6698 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6699 {
6700         if (INTEL_GEN(dev_priv) < 6)
6701                 return;
6702
6703         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6704                 intel_runtime_pm_put(dev_priv);
6705
6706         /* gen6_rps_idle() will be called later to disable interrupts */
6707 }
6708
6709 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6710 {
6711         dev_priv->rps.enabled = true; /* force disabling */
6712         intel_disable_gt_powersave(dev_priv);
6713
6714         gen6_reset_rps_interrupts(dev_priv);
6715 }
6716
6717 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6718 {
6719         if (!READ_ONCE(dev_priv->rps.enabled))
6720                 return;
6721
6722         mutex_lock(&dev_priv->rps.hw_lock);
6723
6724         if (INTEL_GEN(dev_priv) >= 9) {
6725                 gen9_disable_rc6(dev_priv);
6726                 gen9_disable_rps(dev_priv);
6727         } else if (IS_CHERRYVIEW(dev_priv)) {
6728                 cherryview_disable_rps(dev_priv);
6729         } else if (IS_VALLEYVIEW(dev_priv)) {
6730                 valleyview_disable_rps(dev_priv);
6731         } else if (INTEL_GEN(dev_priv) >= 6) {
6732                 gen6_disable_rps(dev_priv);
6733         }  else if (IS_IRONLAKE_M(dev_priv)) {
6734                 ironlake_disable_drps(dev_priv);
6735         }
6736
6737         dev_priv->rps.enabled = false;
6738         mutex_unlock(&dev_priv->rps.hw_lock);
6739 }
6740
6741 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6742 {
6743         /* We shouldn't be disabling as we submit, so this should be less
6744          * racy than it appears!
6745          */
6746         if (READ_ONCE(dev_priv->rps.enabled))
6747                 return;
6748
6749         /* Powersaving is controlled by the host when inside a VM */
6750         if (intel_vgpu_active(dev_priv))
6751                 return;
6752
6753         mutex_lock(&dev_priv->rps.hw_lock);
6754
6755         if (IS_CHERRYVIEW(dev_priv)) {
6756                 cherryview_enable_rps(dev_priv);
6757         } else if (IS_VALLEYVIEW(dev_priv)) {
6758                 valleyview_enable_rps(dev_priv);
6759         } else if (INTEL_GEN(dev_priv) >= 9) {
6760                 gen9_enable_rc6(dev_priv);
6761                 gen9_enable_rps(dev_priv);
6762                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6763                         gen6_update_ring_freq(dev_priv);
6764         } else if (IS_BROADWELL(dev_priv)) {
6765                 gen8_enable_rps(dev_priv);
6766                 gen6_update_ring_freq(dev_priv);
6767         } else if (INTEL_GEN(dev_priv) >= 6) {
6768                 gen6_enable_rps(dev_priv);
6769                 gen6_update_ring_freq(dev_priv);
6770         } else if (IS_IRONLAKE_M(dev_priv)) {
6771                 ironlake_enable_drps(dev_priv);
6772                 intel_init_emon(dev_priv);
6773         }
6774
6775         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6776         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6777
6778         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6779         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6780
6781         dev_priv->rps.enabled = true;
6782         mutex_unlock(&dev_priv->rps.hw_lock);
6783 }
6784
6785 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6786 {
6787         struct drm_i915_private *dev_priv =
6788                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6789         struct intel_engine_cs *rcs;
6790         struct drm_i915_gem_request *req;
6791
6792         if (READ_ONCE(dev_priv->rps.enabled))
6793                 goto out;
6794
6795         rcs = &dev_priv->engine[RCS];
6796         if (rcs->last_context)
6797                 goto out;
6798
6799         if (!rcs->init_context)
6800                 goto out;
6801
6802         mutex_lock(&dev_priv->drm.struct_mutex);
6803
6804         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6805         if (IS_ERR(req))
6806                 goto unlock;
6807
6808         if (!i915.enable_execlists && i915_switch_context(req) == 0)
6809                 rcs->init_context(req);
6810
6811         /* Mark the device busy, calling intel_enable_gt_powersave() */
6812         i915_add_request_no_flush(req);
6813
6814 unlock:
6815         mutex_unlock(&dev_priv->drm.struct_mutex);
6816 out:
6817         intel_runtime_pm_put(dev_priv);
6818 }
6819
6820 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6821 {
6822         if (READ_ONCE(dev_priv->rps.enabled))
6823                 return;
6824
6825         if (IS_IRONLAKE_M(dev_priv)) {
6826                 ironlake_enable_drps(dev_priv);
6827                 intel_init_emon(dev_priv);
6828         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6829                 /*
6830                  * PCU communication is slow and this doesn't need to be
6831                  * done at any specific time, so do this out of our fast path
6832                  * to make resume and init faster.
6833                  *
6834                  * We depend on the HW RC6 power context save/restore
6835                  * mechanism when entering D3 through runtime PM suspend. So
6836                  * disable RPM until RPS/RC6 is properly setup. We can only
6837                  * get here via the driver load/system resume/runtime resume
6838                  * paths, so the _noresume version is enough (and in case of
6839                  * runtime resume it's necessary).
6840                  */
6841                 if (queue_delayed_work(dev_priv->wq,
6842                                        &dev_priv->rps.autoenable_work,
6843                                        round_jiffies_up_relative(HZ)))
6844                         intel_runtime_pm_get_noresume(dev_priv);
6845         }
6846 }
6847
6848 static void ibx_init_clock_gating(struct drm_device *dev)
6849 {
6850         struct drm_i915_private *dev_priv = to_i915(dev);
6851
6852         /*
6853          * On Ibex Peak and Cougar Point, we need to disable clock
6854          * gating for the panel power sequencer or it will fail to
6855          * start up when no ports are active.
6856          */
6857         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6858 }
6859
6860 static void g4x_disable_trickle_feed(struct drm_device *dev)
6861 {
6862         struct drm_i915_private *dev_priv = to_i915(dev);
6863         enum pipe pipe;
6864
6865         for_each_pipe(dev_priv, pipe) {
6866                 I915_WRITE(DSPCNTR(pipe),
6867                            I915_READ(DSPCNTR(pipe)) |
6868                            DISPPLANE_TRICKLE_FEED_DISABLE);
6869
6870                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6871                 POSTING_READ(DSPSURF(pipe));
6872         }
6873 }
6874
6875 static void ilk_init_lp_watermarks(struct drm_device *dev)
6876 {
6877         struct drm_i915_private *dev_priv = to_i915(dev);
6878
6879         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6880         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6881         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6882
6883         /*
6884          * Don't touch WM1S_LP_EN here.
6885          * Doing so could cause underruns.
6886          */
6887 }
6888
6889 static void ironlake_init_clock_gating(struct drm_device *dev)
6890 {
6891         struct drm_i915_private *dev_priv = to_i915(dev);
6892         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6893
6894         /*
6895          * Required for FBC
6896          * WaFbcDisableDpfcClockGating:ilk
6897          */
6898         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6899                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6900                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6901
6902         I915_WRITE(PCH_3DCGDIS0,
6903                    MARIUNIT_CLOCK_GATE_DISABLE |
6904                    SVSMUNIT_CLOCK_GATE_DISABLE);
6905         I915_WRITE(PCH_3DCGDIS1,
6906                    VFMUNIT_CLOCK_GATE_DISABLE);
6907
6908         /*
6909          * According to the spec the following bits should be set in
6910          * order to enable memory self-refresh
6911          * The bit 22/21 of 0x42004
6912          * The bit 5 of 0x42020
6913          * The bit 15 of 0x45000
6914          */
6915         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6916                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6917                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6918         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6919         I915_WRITE(DISP_ARB_CTL,
6920                    (I915_READ(DISP_ARB_CTL) |
6921                     DISP_FBC_WM_DIS));
6922
6923         ilk_init_lp_watermarks(dev);
6924
6925         /*
6926          * Based on the document from hardware guys the following bits
6927          * should be set unconditionally in order to enable FBC.
6928          * The bit 22 of 0x42000
6929          * The bit 22 of 0x42004
6930          * The bit 7,8,9 of 0x42020.
6931          */
6932         if (IS_IRONLAKE_M(dev)) {
6933                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6934                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6935                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6936                            ILK_FBCQ_DIS);
6937                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6938                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6939                            ILK_DPARB_GATE);
6940         }
6941
6942         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6943
6944         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6945                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6946                    ILK_ELPIN_409_SELECT);
6947         I915_WRITE(_3D_CHICKEN2,
6948                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6949                    _3D_CHICKEN2_WM_READ_PIPELINED);
6950
6951         /* WaDisableRenderCachePipelinedFlush:ilk */
6952         I915_WRITE(CACHE_MODE_0,
6953                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6954
6955         /* WaDisable_RenderCache_OperationalFlush:ilk */
6956         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6957
6958         g4x_disable_trickle_feed(dev);
6959
6960         ibx_init_clock_gating(dev);
6961 }
6962
6963 static void cpt_init_clock_gating(struct drm_device *dev)
6964 {
6965         struct drm_i915_private *dev_priv = to_i915(dev);
6966         int pipe;
6967         uint32_t val;
6968
6969         /*
6970          * On Ibex Peak and Cougar Point, we need to disable clock
6971          * gating for the panel power sequencer or it will fail to
6972          * start up when no ports are active.
6973          */
6974         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6975                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6976                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6977         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6978                    DPLS_EDP_PPS_FIX_DIS);
6979         /* The below fixes the weird display corruption, a few pixels shifted
6980          * downward, on (only) LVDS of some HP laptops with IVY.
6981          */
6982         for_each_pipe(dev_priv, pipe) {
6983                 val = I915_READ(TRANS_CHICKEN2(pipe));
6984                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6985                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6986                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6987                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6988                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6989                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6990                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6991                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6992         }
6993         /* WADP0ClockGatingDisable */
6994         for_each_pipe(dev_priv, pipe) {
6995                 I915_WRITE(TRANS_CHICKEN1(pipe),
6996                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6997         }
6998 }
6999
7000 static void gen6_check_mch_setup(struct drm_device *dev)
7001 {
7002         struct drm_i915_private *dev_priv = to_i915(dev);
7003         uint32_t tmp;
7004
7005         tmp = I915_READ(MCH_SSKPD);
7006         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7007                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7008                               tmp);
7009 }
7010
7011 static void gen6_init_clock_gating(struct drm_device *dev)
7012 {
7013         struct drm_i915_private *dev_priv = to_i915(dev);
7014         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7015
7016         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7017
7018         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7019                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7020                    ILK_ELPIN_409_SELECT);
7021
7022         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7023         I915_WRITE(_3D_CHICKEN,
7024                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7025
7026         /* WaDisable_RenderCache_OperationalFlush:snb */
7027         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7028
7029         /*
7030          * BSpec recoomends 8x4 when MSAA is used,
7031          * however in practice 16x4 seems fastest.
7032          *
7033          * Note that PS/WM thread counts depend on the WIZ hashing
7034          * disable bit, which we don't touch here, but it's good
7035          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7036          */
7037         I915_WRITE(GEN6_GT_MODE,
7038                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7039
7040         ilk_init_lp_watermarks(dev);
7041
7042         I915_WRITE(CACHE_MODE_0,
7043                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7044
7045         I915_WRITE(GEN6_UCGCTL1,
7046                    I915_READ(GEN6_UCGCTL1) |
7047                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7048                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7049
7050         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7051          * gating disable must be set.  Failure to set it results in
7052          * flickering pixels due to Z write ordering failures after
7053          * some amount of runtime in the Mesa "fire" demo, and Unigine
7054          * Sanctuary and Tropics, and apparently anything else with
7055          * alpha test or pixel discard.
7056          *
7057          * According to the spec, bit 11 (RCCUNIT) must also be set,
7058          * but we didn't debug actual testcases to find it out.
7059          *
7060          * WaDisableRCCUnitClockGating:snb
7061          * WaDisableRCPBUnitClockGating:snb
7062          */
7063         I915_WRITE(GEN6_UCGCTL2,
7064                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7065                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7066
7067         /* WaStripsFansDisableFastClipPerformanceFix:snb */
7068         I915_WRITE(_3D_CHICKEN3,
7069                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7070
7071         /*
7072          * Bspec says:
7073          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7074          * 3DSTATE_SF number of SF output attributes is more than 16."
7075          */
7076         I915_WRITE(_3D_CHICKEN3,
7077                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7078
7079         /*
7080          * According to the spec the following bits should be
7081          * set in order to enable memory self-refresh and fbc:
7082          * The bit21 and bit22 of 0x42000
7083          * The bit21 and bit22 of 0x42004
7084          * The bit5 and bit7 of 0x42020
7085          * The bit14 of 0x70180
7086          * The bit14 of 0x71180
7087          *
7088          * WaFbcAsynchFlipDisableFbcQueue:snb
7089          */
7090         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7091                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7092                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7093         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7094                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7095                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7096         I915_WRITE(ILK_DSPCLK_GATE_D,
7097                    I915_READ(ILK_DSPCLK_GATE_D) |
7098                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7099                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7100
7101         g4x_disable_trickle_feed(dev);
7102
7103         cpt_init_clock_gating(dev);
7104
7105         gen6_check_mch_setup(dev);
7106 }
7107
7108 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7109 {
7110         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7111
7112         /*
7113          * WaVSThreadDispatchOverride:ivb,vlv
7114          *
7115          * This actually overrides the dispatch
7116          * mode for all thread types.
7117          */
7118         reg &= ~GEN7_FF_SCHED_MASK;
7119         reg |= GEN7_FF_TS_SCHED_HW;
7120         reg |= GEN7_FF_VS_SCHED_HW;
7121         reg |= GEN7_FF_DS_SCHED_HW;
7122
7123         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7124 }
7125
7126 static void lpt_init_clock_gating(struct drm_device *dev)
7127 {
7128         struct drm_i915_private *dev_priv = to_i915(dev);
7129
7130         /*
7131          * TODO: this bit should only be enabled when really needed, then
7132          * disabled when not needed anymore in order to save power.
7133          */
7134         if (HAS_PCH_LPT_LP(dev))
7135                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7136                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7137                            PCH_LP_PARTITION_LEVEL_DISABLE);
7138
7139         /* WADPOClockGatingDisable:hsw */
7140         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7141                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7142                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7143 }
7144
7145 static void lpt_suspend_hw(struct drm_device *dev)
7146 {
7147         struct drm_i915_private *dev_priv = to_i915(dev);
7148
7149         if (HAS_PCH_LPT_LP(dev)) {
7150                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7151
7152                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7153                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7154         }
7155 }
7156
7157 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7158                                    int general_prio_credits,
7159                                    int high_prio_credits)
7160 {
7161         u32 misccpctl;
7162
7163         /* WaTempDisableDOPClkGating:bdw */
7164         misccpctl = I915_READ(GEN7_MISCCPCTL);
7165         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7166
7167         I915_WRITE(GEN8_L3SQCREG1,
7168                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7169                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7170
7171         /*
7172          * Wait at least 100 clocks before re-enabling clock gating.
7173          * See the definition of L3SQCREG1 in BSpec.
7174          */
7175         POSTING_READ(GEN8_L3SQCREG1);
7176         udelay(1);
7177         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7178 }
7179
7180 static void kabylake_init_clock_gating(struct drm_device *dev)
7181 {
7182         struct drm_i915_private *dev_priv = dev->dev_private;
7183
7184         gen9_init_clock_gating(dev);
7185
7186         /* WaDisableSDEUnitClockGating:kbl */
7187         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7188                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7189                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7190
7191         /* WaDisableGamClockGating:kbl */
7192         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7193                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7194                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7195
7196         /* WaFbcNukeOnHostModify:kbl */
7197         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7198                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7199 }
7200
7201 static void skylake_init_clock_gating(struct drm_device *dev)
7202 {
7203         struct drm_i915_private *dev_priv = dev->dev_private;
7204
7205         gen9_init_clock_gating(dev);
7206
7207         /* WAC6entrylatency:skl */
7208         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7209                    FBC_LLC_FULLY_OPEN);
7210
7211         /* WaFbcNukeOnHostModify:skl */
7212         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7213                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7214 }
7215
7216 static void broadwell_init_clock_gating(struct drm_device *dev)
7217 {
7218         struct drm_i915_private *dev_priv = to_i915(dev);
7219         enum pipe pipe;
7220
7221         ilk_init_lp_watermarks(dev);
7222
7223         /* WaSwitchSolVfFArbitrationPriority:bdw */
7224         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7225
7226         /* WaPsrDPAMaskVBlankInSRD:bdw */
7227         I915_WRITE(CHICKEN_PAR1_1,
7228                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7229
7230         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7231         for_each_pipe(dev_priv, pipe) {
7232                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7233                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7234                            BDW_DPRS_MASK_VBLANK_SRD);
7235         }
7236
7237         /* WaVSRefCountFullforceMissDisable:bdw */
7238         /* WaDSRefCountFullforceMissDisable:bdw */
7239         I915_WRITE(GEN7_FF_THREAD_MODE,
7240                    I915_READ(GEN7_FF_THREAD_MODE) &
7241                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7242
7243         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7244                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7245
7246         /* WaDisableSDEUnitClockGating:bdw */
7247         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7248                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7249
7250         /* WaProgramL3SqcReg1Default:bdw */
7251         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7252
7253         /*
7254          * WaGttCachingOffByDefault:bdw
7255          * GTT cache may not work with big pages, so if those
7256          * are ever enabled GTT cache may need to be disabled.
7257          */
7258         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7259
7260         /* WaKVMNotificationOnConfigChange:bdw */
7261         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7262                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7263
7264         lpt_init_clock_gating(dev);
7265 }
7266
7267 static void haswell_init_clock_gating(struct drm_device *dev)
7268 {
7269         struct drm_i915_private *dev_priv = to_i915(dev);
7270
7271         ilk_init_lp_watermarks(dev);
7272
7273         /* L3 caching of data atomics doesn't work -- disable it. */
7274         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7275         I915_WRITE(HSW_ROW_CHICKEN3,
7276                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7277
7278         /* This is required by WaCatErrorRejectionIssue:hsw */
7279         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7280                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7281                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7282
7283         /* WaVSRefCountFullforceMissDisable:hsw */
7284         I915_WRITE(GEN7_FF_THREAD_MODE,
7285                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7286
7287         /* WaDisable_RenderCache_OperationalFlush:hsw */
7288         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7289
7290         /* enable HiZ Raw Stall Optimization */
7291         I915_WRITE(CACHE_MODE_0_GEN7,
7292                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7293
7294         /* WaDisable4x2SubspanOptimization:hsw */
7295         I915_WRITE(CACHE_MODE_1,
7296                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7297
7298         /*
7299          * BSpec recommends 8x4 when MSAA is used,
7300          * however in practice 16x4 seems fastest.
7301          *
7302          * Note that PS/WM thread counts depend on the WIZ hashing
7303          * disable bit, which we don't touch here, but it's good
7304          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7305          */
7306         I915_WRITE(GEN7_GT_MODE,
7307                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7308
7309         /* WaSampleCChickenBitEnable:hsw */
7310         I915_WRITE(HALF_SLICE_CHICKEN3,
7311                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7312
7313         /* WaSwitchSolVfFArbitrationPriority:hsw */
7314         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7315
7316         /* WaRsPkgCStateDisplayPMReq:hsw */
7317         I915_WRITE(CHICKEN_PAR1_1,
7318                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7319
7320         lpt_init_clock_gating(dev);
7321 }
7322
7323 static void ivybridge_init_clock_gating(struct drm_device *dev)
7324 {
7325         struct drm_i915_private *dev_priv = to_i915(dev);
7326         uint32_t snpcr;
7327
7328         ilk_init_lp_watermarks(dev);
7329
7330         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7331
7332         /* WaDisableEarlyCull:ivb */
7333         I915_WRITE(_3D_CHICKEN3,
7334                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7335
7336         /* WaDisableBackToBackFlipFix:ivb */
7337         I915_WRITE(IVB_CHICKEN3,
7338                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7339                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7340
7341         /* WaDisablePSDDualDispatchEnable:ivb */
7342         if (IS_IVB_GT1(dev))
7343                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7344                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7345
7346         /* WaDisable_RenderCache_OperationalFlush:ivb */
7347         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7348
7349         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7350         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7351                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7352
7353         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7354         I915_WRITE(GEN7_L3CNTLREG1,
7355                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7356         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7357                    GEN7_WA_L3_CHICKEN_MODE);
7358         if (IS_IVB_GT1(dev))
7359                 I915_WRITE(GEN7_ROW_CHICKEN2,
7360                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7361         else {
7362                 /* must write both registers */
7363                 I915_WRITE(GEN7_ROW_CHICKEN2,
7364                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7365                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7366                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7367         }
7368
7369         /* WaForceL3Serialization:ivb */
7370         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7371                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7372
7373         /*
7374          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7375          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7376          */
7377         I915_WRITE(GEN6_UCGCTL2,
7378                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7379
7380         /* This is required by WaCatErrorRejectionIssue:ivb */
7381         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7382                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7383                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7384
7385         g4x_disable_trickle_feed(dev);
7386
7387         gen7_setup_fixed_func_scheduler(dev_priv);
7388
7389         if (0) { /* causes HiZ corruption on ivb:gt1 */
7390                 /* enable HiZ Raw Stall Optimization */
7391                 I915_WRITE(CACHE_MODE_0_GEN7,
7392                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7393         }
7394
7395         /* WaDisable4x2SubspanOptimization:ivb */
7396         I915_WRITE(CACHE_MODE_1,
7397                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7398
7399         /*
7400          * BSpec recommends 8x4 when MSAA is used,
7401          * however in practice 16x4 seems fastest.
7402          *
7403          * Note that PS/WM thread counts depend on the WIZ hashing
7404          * disable bit, which we don't touch here, but it's good
7405          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7406          */
7407         I915_WRITE(GEN7_GT_MODE,
7408                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7409
7410         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7411         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7412         snpcr |= GEN6_MBC_SNPCR_MED;
7413         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7414
7415         if (!HAS_PCH_NOP(dev))
7416                 cpt_init_clock_gating(dev);
7417
7418         gen6_check_mch_setup(dev);
7419 }
7420
7421 static void valleyview_init_clock_gating(struct drm_device *dev)
7422 {
7423         struct drm_i915_private *dev_priv = to_i915(dev);
7424
7425         /* WaDisableEarlyCull:vlv */
7426         I915_WRITE(_3D_CHICKEN3,
7427                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7428
7429         /* WaDisableBackToBackFlipFix:vlv */
7430         I915_WRITE(IVB_CHICKEN3,
7431                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7432                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7433
7434         /* WaPsdDispatchEnable:vlv */
7435         /* WaDisablePSDDualDispatchEnable:vlv */
7436         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7437                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7438                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7439
7440         /* WaDisable_RenderCache_OperationalFlush:vlv */
7441         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7442
7443         /* WaForceL3Serialization:vlv */
7444         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7445                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7446
7447         /* WaDisableDopClockGating:vlv */
7448         I915_WRITE(GEN7_ROW_CHICKEN2,
7449                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7450
7451         /* This is required by WaCatErrorRejectionIssue:vlv */
7452         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7453                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7454                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7455
7456         gen7_setup_fixed_func_scheduler(dev_priv);
7457
7458         /*
7459          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7460          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7461          */
7462         I915_WRITE(GEN6_UCGCTL2,
7463                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7464
7465         /* WaDisableL3Bank2xClockGate:vlv
7466          * Disabling L3 clock gating- MMIO 940c[25] = 1
7467          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7468         I915_WRITE(GEN7_UCGCTL4,
7469                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7470
7471         /*
7472          * BSpec says this must be set, even though
7473          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7474          */
7475         I915_WRITE(CACHE_MODE_1,
7476                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7477
7478         /*
7479          * BSpec recommends 8x4 when MSAA is used,
7480          * however in practice 16x4 seems fastest.
7481          *
7482          * Note that PS/WM thread counts depend on the WIZ hashing
7483          * disable bit, which we don't touch here, but it's good
7484          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7485          */
7486         I915_WRITE(GEN7_GT_MODE,
7487                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7488
7489         /*
7490          * WaIncreaseL3CreditsForVLVB0:vlv
7491          * This is the hardware default actually.
7492          */
7493         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7494
7495         /*
7496          * WaDisableVLVClockGating_VBIIssue:vlv
7497          * Disable clock gating on th GCFG unit to prevent a delay
7498          * in the reporting of vblank events.
7499          */
7500         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7501 }
7502
7503 static void cherryview_init_clock_gating(struct drm_device *dev)
7504 {
7505         struct drm_i915_private *dev_priv = to_i915(dev);
7506
7507         /* WaVSRefCountFullforceMissDisable:chv */
7508         /* WaDSRefCountFullforceMissDisable:chv */
7509         I915_WRITE(GEN7_FF_THREAD_MODE,
7510                    I915_READ(GEN7_FF_THREAD_MODE) &
7511                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7512
7513         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7514         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7515                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7516
7517         /* WaDisableCSUnitClockGating:chv */
7518         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7519                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7520
7521         /* WaDisableSDEUnitClockGating:chv */
7522         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7523                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7524
7525         /*
7526          * WaProgramL3SqcReg1Default:chv
7527          * See gfxspecs/Related Documents/Performance Guide/
7528          * LSQC Setting Recommendations.
7529          */
7530         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7531
7532         /*
7533          * GTT cache may not work with big pages, so if those
7534          * are ever enabled GTT cache may need to be disabled.
7535          */
7536         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7537 }
7538
7539 static void g4x_init_clock_gating(struct drm_device *dev)
7540 {
7541         struct drm_i915_private *dev_priv = to_i915(dev);
7542         uint32_t dspclk_gate;
7543
7544         I915_WRITE(RENCLK_GATE_D1, 0);
7545         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7546                    GS_UNIT_CLOCK_GATE_DISABLE |
7547                    CL_UNIT_CLOCK_GATE_DISABLE);
7548         I915_WRITE(RAMCLK_GATE_D, 0);
7549         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7550                 OVRUNIT_CLOCK_GATE_DISABLE |
7551                 OVCUNIT_CLOCK_GATE_DISABLE;
7552         if (IS_GM45(dev))
7553                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7554         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7555
7556         /* WaDisableRenderCachePipelinedFlush */
7557         I915_WRITE(CACHE_MODE_0,
7558                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7559
7560         /* WaDisable_RenderCache_OperationalFlush:g4x */
7561         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7562
7563         g4x_disable_trickle_feed(dev);
7564 }
7565
7566 static void crestline_init_clock_gating(struct drm_device *dev)
7567 {
7568         struct drm_i915_private *dev_priv = to_i915(dev);
7569
7570         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7571         I915_WRITE(RENCLK_GATE_D2, 0);
7572         I915_WRITE(DSPCLK_GATE_D, 0);
7573         I915_WRITE(RAMCLK_GATE_D, 0);
7574         I915_WRITE16(DEUC, 0);
7575         I915_WRITE(MI_ARB_STATE,
7576                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7577
7578         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7579         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7580 }
7581
7582 static void broadwater_init_clock_gating(struct drm_device *dev)
7583 {
7584         struct drm_i915_private *dev_priv = to_i915(dev);
7585
7586         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7587                    I965_RCC_CLOCK_GATE_DISABLE |
7588                    I965_RCPB_CLOCK_GATE_DISABLE |
7589                    I965_ISC_CLOCK_GATE_DISABLE |
7590                    I965_FBC_CLOCK_GATE_DISABLE);
7591         I915_WRITE(RENCLK_GATE_D2, 0);
7592         I915_WRITE(MI_ARB_STATE,
7593                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7594
7595         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7596         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7597 }
7598
7599 static void gen3_init_clock_gating(struct drm_device *dev)
7600 {
7601         struct drm_i915_private *dev_priv = to_i915(dev);
7602         u32 dstate = I915_READ(D_STATE);
7603
7604         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7605                 DSTATE_DOT_CLOCK_GATING;
7606         I915_WRITE(D_STATE, dstate);
7607
7608         if (IS_PINEVIEW(dev))
7609                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7610
7611         /* IIR "flip pending" means done if this bit is set */
7612         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7613
7614         /* interrupts should cause a wake up from C3 */
7615         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7616
7617         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7618         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7619
7620         I915_WRITE(MI_ARB_STATE,
7621                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7622 }
7623
7624 static void i85x_init_clock_gating(struct drm_device *dev)
7625 {
7626         struct drm_i915_private *dev_priv = to_i915(dev);
7627
7628         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7629
7630         /* interrupts should cause a wake up from C3 */
7631         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7632                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7633
7634         I915_WRITE(MEM_MODE,
7635                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7636 }
7637
7638 static void i830_init_clock_gating(struct drm_device *dev)
7639 {
7640         struct drm_i915_private *dev_priv = to_i915(dev);
7641
7642         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7643
7644         I915_WRITE(MEM_MODE,
7645                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7646                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7647 }
7648
7649 void intel_init_clock_gating(struct drm_device *dev)
7650 {
7651         struct drm_i915_private *dev_priv = to_i915(dev);
7652
7653         dev_priv->display.init_clock_gating(dev);
7654 }
7655
7656 void intel_suspend_hw(struct drm_device *dev)
7657 {
7658         if (HAS_PCH_LPT(dev))
7659                 lpt_suspend_hw(dev);
7660 }
7661
7662 static void nop_init_clock_gating(struct drm_device *dev)
7663 {
7664         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7665 }
7666
7667 /**
7668  * intel_init_clock_gating_hooks - setup the clock gating hooks
7669  * @dev_priv: device private
7670  *
7671  * Setup the hooks that configure which clocks of a given platform can be
7672  * gated and also apply various GT and display specific workarounds for these
7673  * platforms. Note that some GT specific workarounds are applied separately
7674  * when GPU contexts or batchbuffers start their execution.
7675  */
7676 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7677 {
7678         if (IS_SKYLAKE(dev_priv))
7679                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7680         else if (IS_KABYLAKE(dev_priv))
7681                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7682         else if (IS_BROXTON(dev_priv))
7683                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7684         else if (IS_BROADWELL(dev_priv))
7685                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7686         else if (IS_CHERRYVIEW(dev_priv))
7687                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7688         else if (IS_HASWELL(dev_priv))
7689                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7690         else if (IS_IVYBRIDGE(dev_priv))
7691                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7692         else if (IS_VALLEYVIEW(dev_priv))
7693                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7694         else if (IS_GEN6(dev_priv))
7695                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7696         else if (IS_GEN5(dev_priv))
7697                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7698         else if (IS_G4X(dev_priv))
7699                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7700         else if (IS_CRESTLINE(dev_priv))
7701                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7702         else if (IS_BROADWATER(dev_priv))
7703                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7704         else if (IS_GEN3(dev_priv))
7705                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7706         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7707                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7708         else if (IS_GEN2(dev_priv))
7709                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7710         else {
7711                 MISSING_CASE(INTEL_DEVID(dev_priv));
7712                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7713         }
7714 }
7715
7716 /* Set up chip specific power management-related functions */
7717 void intel_init_pm(struct drm_device *dev)
7718 {
7719         struct drm_i915_private *dev_priv = to_i915(dev);
7720
7721         intel_fbc_init(dev_priv);
7722
7723         /* For cxsr */
7724         if (IS_PINEVIEW(dev))
7725                 i915_pineview_get_mem_freq(dev);
7726         else if (IS_GEN5(dev))
7727                 i915_ironlake_get_mem_freq(dev);
7728
7729         /* For FIFO watermark updates */
7730         if (INTEL_INFO(dev)->gen >= 9) {
7731                 skl_setup_wm_latency(dev);
7732                 dev_priv->display.update_wm = skl_update_wm;
7733                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7734         } else if (HAS_PCH_SPLIT(dev)) {
7735                 ilk_setup_wm_latency(dev);
7736
7737                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7738                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7739                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7740                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7741                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7742                         dev_priv->display.compute_intermediate_wm =
7743                                 ilk_compute_intermediate_wm;
7744                         dev_priv->display.initial_watermarks =
7745                                 ilk_initial_watermarks;
7746                         dev_priv->display.optimize_watermarks =
7747                                 ilk_optimize_watermarks;
7748                 } else {
7749                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7750                                       "Disable CxSR\n");
7751                 }
7752         } else if (IS_CHERRYVIEW(dev)) {
7753                 vlv_setup_wm_latency(dev);
7754                 dev_priv->display.update_wm = vlv_update_wm;
7755         } else if (IS_VALLEYVIEW(dev)) {
7756                 vlv_setup_wm_latency(dev);
7757                 dev_priv->display.update_wm = vlv_update_wm;
7758         } else if (IS_PINEVIEW(dev)) {
7759                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7760                                             dev_priv->is_ddr3,
7761                                             dev_priv->fsb_freq,
7762                                             dev_priv->mem_freq)) {
7763                         DRM_INFO("failed to find known CxSR latency "
7764                                  "(found ddr%s fsb freq %d, mem freq %d), "
7765                                  "disabling CxSR\n",
7766                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7767                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7768                         /* Disable CxSR and never update its watermark again */
7769                         intel_set_memory_cxsr(dev_priv, false);
7770                         dev_priv->display.update_wm = NULL;
7771                 } else
7772                         dev_priv->display.update_wm = pineview_update_wm;
7773         } else if (IS_G4X(dev)) {
7774                 dev_priv->display.update_wm = g4x_update_wm;
7775         } else if (IS_GEN4(dev)) {
7776                 dev_priv->display.update_wm = i965_update_wm;
7777         } else if (IS_GEN3(dev)) {
7778                 dev_priv->display.update_wm = i9xx_update_wm;
7779                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7780         } else if (IS_GEN2(dev)) {
7781                 if (INTEL_INFO(dev)->num_pipes == 1) {
7782                         dev_priv->display.update_wm = i845_update_wm;
7783                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7784                 } else {
7785                         dev_priv->display.update_wm = i9xx_update_wm;
7786                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7787                 }
7788         } else {
7789                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7790         }
7791 }
7792
7793 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7794 {
7795         uint32_t flags =
7796                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7797
7798         switch (flags) {
7799         case GEN6_PCODE_SUCCESS:
7800                 return 0;
7801         case GEN6_PCODE_UNIMPLEMENTED_CMD:
7802         case GEN6_PCODE_ILLEGAL_CMD:
7803                 return -ENXIO;
7804         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7805         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7806                 return -EOVERFLOW;
7807         case GEN6_PCODE_TIMEOUT:
7808                 return -ETIMEDOUT;
7809         default:
7810                 MISSING_CASE(flags)
7811                 return 0;
7812         }
7813 }
7814
7815 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7816 {
7817         uint32_t flags =
7818                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7819
7820         switch (flags) {
7821         case GEN6_PCODE_SUCCESS:
7822                 return 0;
7823         case GEN6_PCODE_ILLEGAL_CMD:
7824                 return -ENXIO;
7825         case GEN7_PCODE_TIMEOUT:
7826                 return -ETIMEDOUT;
7827         case GEN7_PCODE_ILLEGAL_DATA:
7828                 return -EINVAL;
7829         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7830                 return -EOVERFLOW;
7831         default:
7832                 MISSING_CASE(flags);
7833                 return 0;
7834         }
7835 }
7836
7837 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7838 {
7839         int status;
7840
7841         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7842
7843         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7844          * use te fw I915_READ variants to reduce the amount of work
7845          * required when reading/writing.
7846          */
7847
7848         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7849                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7850                 return -EAGAIN;
7851         }
7852
7853         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7854         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7855         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7856
7857         if (intel_wait_for_register_fw(dev_priv,
7858                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7859                                        500)) {
7860                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7861                 return -ETIMEDOUT;
7862         }
7863
7864         *val = I915_READ_FW(GEN6_PCODE_DATA);
7865         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7866
7867         if (INTEL_GEN(dev_priv) > 6)
7868                 status = gen7_check_mailbox_status(dev_priv);
7869         else
7870                 status = gen6_check_mailbox_status(dev_priv);
7871
7872         if (status) {
7873                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7874                                  status);
7875                 return status;
7876         }
7877
7878         return 0;
7879 }
7880
7881 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7882                             u32 mbox, u32 val)
7883 {
7884         int status;
7885
7886         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7887
7888         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7889          * use te fw I915_READ variants to reduce the amount of work
7890          * required when reading/writing.
7891          */
7892
7893         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7894                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7895                 return -EAGAIN;
7896         }
7897
7898         I915_WRITE_FW(GEN6_PCODE_DATA, val);
7899         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7900
7901         if (intel_wait_for_register_fw(dev_priv,
7902                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7903                                        500)) {
7904                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7905                 return -ETIMEDOUT;
7906         }
7907
7908         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7909
7910         if (INTEL_GEN(dev_priv) > 6)
7911                 status = gen7_check_mailbox_status(dev_priv);
7912         else
7913                 status = gen6_check_mailbox_status(dev_priv);
7914
7915         if (status) {
7916                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7917                                  status);
7918                 return status;
7919         }
7920
7921         return 0;
7922 }
7923
7924 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7925 {
7926         /*
7927          * N = val - 0xb7
7928          * Slow = Fast = GPLL ref * N
7929          */
7930         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7931 }
7932
7933 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7934 {
7935         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7936 }
7937
7938 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7939 {
7940         /*
7941          * N = val / 2
7942          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7943          */
7944         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7945 }
7946
7947 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7948 {
7949         /* CHV needs even values */
7950         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7951 }
7952
7953 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7954 {
7955         if (IS_GEN9(dev_priv))
7956                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7957                                          GEN9_FREQ_SCALER);
7958         else if (IS_CHERRYVIEW(dev_priv))
7959                 return chv_gpu_freq(dev_priv, val);
7960         else if (IS_VALLEYVIEW(dev_priv))
7961                 return byt_gpu_freq(dev_priv, val);
7962         else
7963                 return val * GT_FREQUENCY_MULTIPLIER;
7964 }
7965
7966 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7967 {
7968         if (IS_GEN9(dev_priv))
7969                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7970                                          GT_FREQUENCY_MULTIPLIER);
7971         else if (IS_CHERRYVIEW(dev_priv))
7972                 return chv_freq_opcode(dev_priv, val);
7973         else if (IS_VALLEYVIEW(dev_priv))
7974                 return byt_freq_opcode(dev_priv, val);
7975         else
7976                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7977 }
7978
7979 struct request_boost {
7980         struct work_struct work;
7981         struct drm_i915_gem_request *req;
7982 };
7983
7984 static void __intel_rps_boost_work(struct work_struct *work)
7985 {
7986         struct request_boost *boost = container_of(work, struct request_boost, work);
7987         struct drm_i915_gem_request *req = boost->req;
7988
7989         if (!i915_gem_request_completed(req))
7990                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7991
7992         i915_gem_request_put(req);
7993         kfree(boost);
7994 }
7995
7996 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7997 {
7998         struct request_boost *boost;
7999
8000         if (req == NULL || INTEL_GEN(req->i915) < 6)
8001                 return;
8002
8003         if (i915_gem_request_completed(req))
8004                 return;
8005
8006         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8007         if (boost == NULL)
8008                 return;
8009
8010         boost->req = i915_gem_request_get(req);
8011
8012         INIT_WORK(&boost->work, __intel_rps_boost_work);
8013         queue_work(req->i915->wq, &boost->work);
8014 }
8015
8016 void intel_pm_setup(struct drm_device *dev)
8017 {
8018         struct drm_i915_private *dev_priv = to_i915(dev);
8019
8020         mutex_init(&dev_priv->rps.hw_lock);
8021         spin_lock_init(&dev_priv->rps.client_lock);
8022
8023         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8024                           __intel_autoenable_gt_powersave);
8025         INIT_LIST_HEAD(&dev_priv->rps.clients);
8026
8027         dev_priv->pm.suspended = false;
8028         atomic_set(&dev_priv->pm.wakeref_count, 0);
8029         atomic_set(&dev_priv->pm.atomic_seq, 0);
8030 }