drivers/gpu/drm/i915/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Dave Airlie <airlied@linux.ie>
  27  *      Jesse Barnes <jesse.barnes@intel.com>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/dmi.h>
  32 #include <linux/i2c.h>
  33 #include <linux/slab.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <drm/drm_atomic_helper.h>
  36 #include <drm/drm_crtc.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41 #include <linux/acpi.h>
  42
  43 /* Private structure for the integrated LVDS support */
  44 struct intel_lvds_pps {
  45         /* 100us units */
  46         int t1_t2;
  47         int t3;
  48         int t4;
  49         int t5;
  50         int tx;
  51
  52         int divider;
  53
  54         int port;
  55         bool powerdown_on_reset;
  56 };
  57
  58 struct intel_lvds_encoder {
  59         struct intel_encoder base;
  60
  61         bool is_dual_link;
  62         i915_reg_t reg;
  63         u32 a3_power;
  64
  65         struct intel_lvds_pps init_pps;
  66         u32 init_lvds_val;
  67
  68         struct intel_connector *attached_connector;
  69 };
  70
  71 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  72 {
  73         return container_of(encoder, struct intel_lvds_encoder, base.base);
  74 }
  75
  76 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
  77                              i915_reg_t lvds_reg, enum pipe *pipe)
  78 {
  79         u32 val;
  80
  81         val = I915_READ(lvds_reg);
  82
  83         /* asserts want to know the pipe even if the port is disabled */
  84         if (HAS_PCH_CPT(dev_priv))
  85                 *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;
  86         else
  87                 *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;
  88
  89         return val & LVDS_PORT_EN;
  90 }
  91
  92 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
  93                                     enum pipe *pipe)
  94 {
  95         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  96         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  97         intel_wakeref_t wakeref;
  98         bool ret;
  99
 100         wakeref = intel_display_power_get_if_enabled(dev_priv,
 101                                                      encoder->power_domain);
 102         if (!wakeref)
 103                 return false;
 104
 105         ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);
 106
 107         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 108
 109         return ret;
 110 }
 111
 112 static void intel_lvds_get_config(struct intel_encoder *encoder,
 113                                   struct intel_crtc_state *pipe_config)
 114 {
 115         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 116         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 117         u32 tmp, flags = 0;
 118
 119         pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
 120
 121         tmp = I915_READ(lvds_encoder->reg);
 122         if (tmp & LVDS_HSYNC_POLARITY)
 123                 flags |= DRM_MODE_FLAG_NHSYNC;
 124         else
 125                 flags |= DRM_MODE_FLAG_PHSYNC;
 126         if (tmp & LVDS_VSYNC_POLARITY)
 127                 flags |= DRM_MODE_FLAG_NVSYNC;
 128         else
 129                 flags |= DRM_MODE_FLAG_PVSYNC;
 130
 131         pipe_config->base.adjusted_mode.flags |= flags;
 132
 133         if (INTEL_GEN(dev_priv) < 5)
 134                 pipe_config->gmch_pfit.lvds_border_bits =
 135                         tmp & LVDS_BORDER_ENABLE;
 136
 137         /* gen2/3 store dither state in pfit control, needs to match */
 138         if (INTEL_GEN(dev_priv) < 4) {
 139                 tmp = I915_READ(PFIT_CONTROL);
 140
 141                 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 142         }
 143
 144         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 145 }
 146
 147 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 148                                         struct intel_lvds_pps *pps)
 149 {
 150         u32 val;
 151
 152         pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
 153
 154         val = I915_READ(PP_ON_DELAYS(0));
 155         pps->port = (val & PANEL_PORT_SELECT_MASK) >>
 156                     PANEL_PORT_SELECT_SHIFT;
 157         pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
 158                      PANEL_POWER_UP_DELAY_SHIFT;
 159         pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
 160                   PANEL_LIGHT_ON_DELAY_SHIFT;
 161
 162         val = I915_READ(PP_OFF_DELAYS(0));
 163         pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
 164                   PANEL_POWER_DOWN_DELAY_SHIFT;
 165         pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
 166                   PANEL_LIGHT_OFF_DELAY_SHIFT;
 167
 168         val = I915_READ(PP_DIVISOR(0));
 169         pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
 170                        PP_REFERENCE_DIVIDER_SHIFT;
 171         val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
 172               PANEL_POWER_CYCLE_DELAY_SHIFT;
 173         /*
 174          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 175          * too short power-cycle delay due to the asynchronous programming of
 176          * the register.
 177          */
 178         if (val)
 179                 val--;
 180         /* Convert from 100ms to 100us units */
 181         pps->t4 = val * 1000;
 182
 183         if (INTEL_GEN(dev_priv) <= 4 &&
 184             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 185                 DRM_DEBUG_KMS("Panel power timings uninitialized, "
 186                               "setting defaults\n");
 187                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 188                 pps->t1_t2 = 40 * 10;
 189                 pps->t5 = 200 * 10;
 190                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 191                 pps->t3 = 35 * 10;
 192                 pps->tx = 200 * 10;
 193         }
 194
 195         DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 196                          "divider %d port %d powerdown_on_reset %d\n",
 197                          pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 198                          pps->divider, pps->port, pps->powerdown_on_reset);
 199 }
 200
 201 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 202                                    struct intel_lvds_pps *pps)
 203 {
 204         u32 val;
 205
 206         val = I915_READ(PP_CONTROL(0));
 207         WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 208         if (pps->powerdown_on_reset)
 209                 val |= PANEL_POWER_RESET;
 210         I915_WRITE(PP_CONTROL(0), val);
 211
 212         I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
 213                                     (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
 214                                     (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
 215         I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
 216                                      (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
 217
 218         val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
 219         val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
 220                PANEL_POWER_CYCLE_DELAY_SHIFT;
 221         I915_WRITE(PP_DIVISOR(0), val);
 222 }
 223
 224 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 225                                   const struct intel_crtc_state *pipe_config,
 226                                   const struct drm_connector_state *conn_state)
 227 {
 228         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 229         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 230         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 231         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 232         int pipe = crtc->pipe;
 233         u32 temp;
 234
 235         if (HAS_PCH_SPLIT(dev_priv)) {
 236                 assert_fdi_rx_pll_disabled(dev_priv, pipe);
 237                 assert_shared_dpll_disabled(dev_priv,
 238                                             pipe_config->shared_dpll);
 239         } else {
 240                 assert_pll_disabled(dev_priv, pipe);
 241         }
 242
 243         intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
 244
 245         temp = lvds_encoder->init_lvds_val;
 246         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 247
 248         if (HAS_PCH_CPT(dev_priv)) {
 249                 temp &= ~LVDS_PIPE_SEL_MASK_CPT;
 250                 temp |= LVDS_PIPE_SEL_CPT(pipe);
 251         } else {
 252                 temp &= ~LVDS_PIPE_SEL_MASK;
 253                 temp |= LVDS_PIPE_SEL(pipe);
 254         }
 255
 256         /* set the corresponsding LVDS_BORDER bit */
 257         temp &= ~LVDS_BORDER_ENABLE;
 258         temp |= pipe_config->gmch_pfit.lvds_border_bits;
 259
 260         /*
 261          * Set the B0-B3 data pairs corresponding to whether we're going to
 262          * set the DPLLs for dual-channel mode or not.
 263          */
 264         if (lvds_encoder->is_dual_link)
 265                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 266         else
 267                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 268
 269         /*
 270          * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 271          * appropriately here, but we need to look more thoroughly into how
 272          * panels behave in the two modes. For now, let's just maintain the
 273          * value we got from the BIOS.
 274          */
 275         temp &= ~LVDS_A3_POWER_MASK;
 276         temp |= lvds_encoder->a3_power;
 277
 278         /*
 279          * Set the dithering flag on LVDS as needed, note that there is no
 280          * special lvds dither control bit on pch-split platforms, dithering is
 281          * only controlled through the PIPECONF reg.
 282          */
 283         if (IS_GEN(dev_priv, 4)) {
 284                 /*
 285                  * Bspec wording suggests that LVDS port dithering only exists
 286                  * for 18bpp panels.
 287                  */
 288                 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
 289                         temp |= LVDS_ENABLE_DITHER;
 290                 else
 291                         temp &= ~LVDS_ENABLE_DITHER;
 292         }
 293         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 294         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 295                 temp |= LVDS_HSYNC_POLARITY;
 296         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 297                 temp |= LVDS_VSYNC_POLARITY;
 298
 299         I915_WRITE(lvds_encoder->reg, temp);
 300 }
 301
 302 /*
 303  * Sets the power state for the panel.
 304  */
 305 static void intel_enable_lvds(struct intel_encoder *encoder,
 306                               const struct intel_crtc_state *pipe_config,
 307                               const struct drm_connector_state *conn_state)
 308 {
 309         struct drm_device *dev = encoder->base.dev;
 310         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 311         struct drm_i915_private *dev_priv = to_i915(dev);
 312
 313         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
 314
 315         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
 316         POSTING_READ(lvds_encoder->reg);
 317
 318         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
 319                 DRM_ERROR("timed out waiting for panel to power on\n");
 320
 321         intel_panel_enable_backlight(pipe_config, conn_state);
 322 }
 323
 324 static void intel_disable_lvds(struct intel_encoder *encoder,
 325                                const struct intel_crtc_state *old_crtc_state,
 326                                const struct drm_connector_state *old_conn_state)
 327 {
 328         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 329         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 330
 331         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
 332         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
 333                 DRM_ERROR("timed out waiting for panel to power off\n");
 334
 335         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
 336         POSTING_READ(lvds_encoder->reg);
 337 }
 338
 339 static void gmch_disable_lvds(struct intel_encoder *encoder,
 340                               const struct intel_crtc_state *old_crtc_state,
 341                               const struct drm_connector_state *old_conn_state)
 342
 343 {
 344         intel_panel_disable_backlight(old_conn_state);
 345
 346         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 347 }
 348
 349 static void pch_disable_lvds(struct intel_encoder *encoder,
 350                              const struct intel_crtc_state *old_crtc_state,
 351                              const struct drm_connector_state *old_conn_state)
 352 {
 353         intel_panel_disable_backlight(old_conn_state);
 354 }
 355
 356 static void pch_post_disable_lvds(struct intel_encoder *encoder,
 357                                   const struct intel_crtc_state *old_crtc_state,
 358                                   const struct drm_connector_state *old_conn_state)
 359 {
 360         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 361 }
 362
 363 static enum drm_mode_status
 364 intel_lvds_mode_valid(struct drm_connector *connector,
 365                       struct drm_display_mode *mode)
 366 {
 367         struct intel_connector *intel_connector = to_intel_connector(connector);
 368         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 369         int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 370
 371         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 372                 return MODE_NO_DBLESCAN;
 373         if (mode->hdisplay > fixed_mode->hdisplay)
 374                 return MODE_PANEL;
 375         if (mode->vdisplay > fixed_mode->vdisplay)
 376                 return MODE_PANEL;
 377         if (fixed_mode->clock > max_pixclk)
 378                 return MODE_CLOCK_HIGH;
 379
 380         return MODE_OK;
 381 }
 382
 383 static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 384                                      struct intel_crtc_state *pipe_config,
 385                                      struct drm_connector_state *conn_state)
 386 {
 387         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 388         struct intel_lvds_encoder *lvds_encoder =
 389                 to_lvds_encoder(&intel_encoder->base);
 390         struct intel_connector *intel_connector =
 391                 lvds_encoder->attached_connector;
 392         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 393         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 394         unsigned int lvds_bpp;
 395
 396         /* Should never happen!! */
 397         if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
 398                 DRM_ERROR("Can't support LVDS on pipe A\n");
 399                 return -EINVAL;
 400         }
 401
 402         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 403                 lvds_bpp = 8*3;
 404         else
 405                 lvds_bpp = 6*3;
 406
 407         if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
 408                 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
 409                               pipe_config->pipe_bpp, lvds_bpp);
 410                 pipe_config->pipe_bpp = lvds_bpp;
 411         }
 412
 413         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 414
 415         /*
 416          * We have timings from the BIOS for the panel, put them in
 417          * to the adjusted mode.  The CRTC will be set up for this mode,
 418          * with the panel scaling set up to source from the H/VDisplay
 419          * of the original mode.
 420          */
 421         intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 422                                adjusted_mode);
 423
 424         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 425                 return -EINVAL;
 426
 427         if (HAS_PCH_SPLIT(dev_priv)) {
 428                 pipe_config->has_pch_encoder = true;
 429
 430                 intel_pch_panel_fitting(intel_crtc, pipe_config,
 431                                         conn_state->scaling_mode);
 432         } else {
 433                 intel_gmch_panel_fitting(intel_crtc, pipe_config,
 434                                          conn_state->scaling_mode);
 435
 436         }
 437
 438         /*
 439          * XXX: It would be nice to support lower refresh rates on the
 440          * panels to reduce power consumption, and perhaps match the
 441          * user's requested refresh rate.
 442          */
 443
 444         return 0;
 445 }
 446
 447 static enum drm_connector_status
 448 intel_lvds_detect(struct drm_connector *connector, bool force)
 449 {
 450         return connector_status_connected;
 451 }
 452
 453 /*
 454  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 455  */
 456 static int intel_lvds_get_modes(struct drm_connector *connector)
 457 {
 458         struct intel_connector *intel_connector = to_intel_connector(connector);
 459         struct drm_device *dev = connector->dev;
 460         struct drm_display_mode *mode;
 461
 462         /* use cached edid if we have one */
 463         if (!IS_ERR_OR_NULL(intel_connector->edid))
 464                 return drm_add_edid_modes(connector, intel_connector->edid);
 465
 466         mode = drm_mode_duplicate(dev, intel_connector->panel.fixed_mode);
 467         if (mode == NULL)
 468                 return 0;
 469
 470         drm_mode_probed_add(connector, mode);
 471         return 1;
 472 }
 473
 474 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 475         .get_modes = intel_lvds_get_modes,
 476         .mode_valid = intel_lvds_mode_valid,
 477         .atomic_check = intel_digital_connector_atomic_check,
 478 };
 479
 480 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 481         .detect = intel_lvds_detect,
 482         .fill_modes = drm_helper_probe_single_connector_modes,
 483         .atomic_get_property = intel_digital_connector_atomic_get_property,
 484         .atomic_set_property = intel_digital_connector_atomic_set_property,
 485         .late_register = intel_connector_register,
 486         .early_unregister = intel_connector_unregister,
 487         .destroy = intel_connector_destroy,
 488         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 489         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 490 };
 491
 492 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 493         .destroy = intel_encoder_destroy,
 494 };
 495
 496 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 497 {
 498         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 499         return 1;
 500 }
 501
 502 /* These systems claim to have LVDS, but really don't */
 503 static const struct dmi_system_id intel_no_lvds[] = {
 504         {
 505                 .callback = intel_no_lvds_dmi_callback,
 506                 .ident = "Apple Mac Mini (Core series)",
 507                 .matches = {
 508                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 509                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 510                 },
 511         },
 512         {
 513                 .callback = intel_no_lvds_dmi_callback,
 514                 .ident = "Apple Mac Mini (Core 2 series)",
 515                 .matches = {
 516                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 517                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 518                 },
 519         },
 520         {
 521                 .callback = intel_no_lvds_dmi_callback,
 522                 .ident = "MSI IM-945GSE-A",
 523                 .matches = {
 524                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 525                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 526                 },
 527         },
 528         {
 529                 .callback = intel_no_lvds_dmi_callback,
 530                 .ident = "Dell Studio Hybrid",
 531                 .matches = {
 532                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 533                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 534                 },
 535         },
 536         {
 537                 .callback = intel_no_lvds_dmi_callback,
 538                 .ident = "Dell OptiPlex FX170",
 539                 .matches = {
 540                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 541                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 542                 },
 543         },
 544         {
 545                 .callback = intel_no_lvds_dmi_callback,
 546                 .ident = "AOpen Mini PC",
 547                 .matches = {
 548                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 549                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 550                 },
 551         },
 552         {
 553                 .callback = intel_no_lvds_dmi_callback,
 554                 .ident = "AOpen Mini PC MP915",
 555                 .matches = {
 556                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 557                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 558                 },
 559         },
 560         {
 561                 .callback = intel_no_lvds_dmi_callback,
 562                 .ident = "AOpen i915GMm-HFS",
 563                 .matches = {
 564                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 565                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 566                 },
 567         },
 568         {
 569                 .callback = intel_no_lvds_dmi_callback,
 570                 .ident = "AOpen i45GMx-I",
 571                 .matches = {
 572                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 573                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 574                 },
 575         },
 576         {
 577                 .callback = intel_no_lvds_dmi_callback,
 578                 .ident = "Aopen i945GTt-VFA",
 579                 .matches = {
 580                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 581                 },
 582         },
 583         {
 584                 .callback = intel_no_lvds_dmi_callback,
 585                 .ident = "Clientron U800",
 586                 .matches = {
 587                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 588                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 589                 },
 590         },
 591         {
 592                 .callback = intel_no_lvds_dmi_callback,
 593                 .ident = "Clientron E830",
 594                 .matches = {
 595                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 596                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 597                 },
 598         },
 599         {
 600                 .callback = intel_no_lvds_dmi_callback,
 601                 .ident = "Asus EeeBox PC EB1007",
 602                 .matches = {
 603                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 604                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 605                 },
 606         },
 607         {
 608                 .callback = intel_no_lvds_dmi_callback,
 609                 .ident = "Asus AT5NM10T-I",
 610                 .matches = {
 611                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 612                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 613                 },
 614         },
 615         {
 616                 .callback = intel_no_lvds_dmi_callback,
 617                 .ident = "Hewlett-Packard HP t5740",
 618                 .matches = {
 619                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 620                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 621                 },
 622         },
 623         {
 624                 .callback = intel_no_lvds_dmi_callback,
 625                 .ident = "Hewlett-Packard t5745",
 626                 .matches = {
 627                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 628                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 629                 },
 630         },
 631         {
 632                 .callback = intel_no_lvds_dmi_callback,
 633                 .ident = "Hewlett-Packard st5747",
 634                 .matches = {
 635                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 636                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 637                 },
 638         },
 639         {
 640                 .callback = intel_no_lvds_dmi_callback,
 641                 .ident = "MSI Wind Box DC500",
 642                 .matches = {
 643                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 644                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 645                 },
 646         },
 647         {
 648                 .callback = intel_no_lvds_dmi_callback,
 649                 .ident = "Gigabyte GA-D525TUD",
 650                 .matches = {
 651                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 652                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 653                 },
 654         },
 655         {
 656                 .callback = intel_no_lvds_dmi_callback,
 657                 .ident = "Supermicro X7SPA-H",
 658                 .matches = {
 659                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 660                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 661                 },
 662         },
 663         {
 664                 .callback = intel_no_lvds_dmi_callback,
 665                 .ident = "Fujitsu Esprimo Q900",
 666                 .matches = {
 667                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 668                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 669                 },
 670         },
 671         {
 672                 .callback = intel_no_lvds_dmi_callback,
 673                 .ident = "Intel D410PT",
 674                 .matches = {
 675                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 676                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 677                 },
 678         },
 679         {
 680                 .callback = intel_no_lvds_dmi_callback,
 681                 .ident = "Intel D425KT",
 682                 .matches = {
 683                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 684                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 685                 },
 686         },
 687         {
 688                 .callback = intel_no_lvds_dmi_callback,
 689                 .ident = "Intel D510MO",
 690                 .matches = {
 691                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 692                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 693                 },
 694         },
 695         {
 696                 .callback = intel_no_lvds_dmi_callback,
 697                 .ident = "Intel D525MW",
 698                 .matches = {
 699                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 700                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 701                 },
 702         },
 703         {
 704                 .callback = intel_no_lvds_dmi_callback,
 705                 .ident = "Radiant P845",
 706                 .matches = {
 707                         DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
 708                         DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
 709                 },
 710         },
 711
 712         { }     /* terminating entry */
 713 };
 714
 715 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 716 {
 717         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 718         return 1;
 719 }
 720
 721 static const struct dmi_system_id intel_dual_link_lvds[] = {
 722         {
 723                 .callback = intel_dual_link_lvds_callback,
 724                 .ident = "Apple MacBook Pro 15\" (2010)",
 725                 .matches = {
 726                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 727                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 728                 },
 729         },
 730         {
 731                 .callback = intel_dual_link_lvds_callback,
 732                 .ident = "Apple MacBook Pro 15\" (2011)",
 733                 .matches = {
 734                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 735                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 736                 },
 737         },
 738         {
 739                 .callback = intel_dual_link_lvds_callback,
 740                 .ident = "Apple MacBook Pro 15\" (2012)",
 741                 .matches = {
 742                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 743                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 744                 },
 745         },
 746         { }     /* terminating entry */
 747 };
 748
 749 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev)
 750 {
 751         struct intel_encoder *intel_encoder;
 752
 753         for_each_intel_encoder(dev, intel_encoder)
 754                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
 755                         return intel_encoder;
 756
 757         return NULL;
 758 }
 759
 760 bool intel_is_dual_link_lvds(struct drm_device *dev)
 761 {
 762         struct intel_encoder *encoder = intel_get_lvds_encoder(dev);
 763
 764         return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
 765 }
 766
 767 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 768 {
 769         struct drm_device *dev = lvds_encoder->base.base.dev;
 770         unsigned int val;
 771         struct drm_i915_private *dev_priv = to_i915(dev);
 772
 773         /* use the module option value if specified */
 774         if (i915_modparams.lvds_channel_mode > 0)
 775                 return i915_modparams.lvds_channel_mode == 2;
 776
 777         /* single channel LVDS is limited to 112 MHz */
 778         if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999)
 779                 return true;
 780
 781         if (dmi_check_system(intel_dual_link_lvds))
 782                 return true;
 783
 784         /*
 785          * BIOS should set the proper LVDS register value at boot, but
 786          * in reality, it doesn't set the value when the lid is closed;
 787          * we need to check "the value to be set" in VBT when LVDS
 788          * register is uninitialized.
 789          */
 790         val = I915_READ(lvds_encoder->reg);
 791         if (HAS_PCH_CPT(dev_priv))
 792                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
 793         else
 794                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
 795         if (val == 0)
 796                 val = dev_priv->vbt.bios_lvds_val;
 797
 798         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 799 }
 800
 801 /**
 802  * intel_lvds_init - setup LVDS connectors on this device
 803  * @dev_priv: i915 device
 804  *
 805  * Create the connector, register the LVDS DDC bus, and try to figure out what
 806  * modes we can display on the LVDS panel (if present).
 807  */
 808 void intel_lvds_init(struct drm_i915_private *dev_priv)
 809 {
 810         struct drm_device *dev = &dev_priv->drm;
 811         struct intel_lvds_encoder *lvds_encoder;
 812         struct intel_encoder *intel_encoder;
 813         struct intel_connector *intel_connector;
 814         struct drm_connector *connector;
 815         struct drm_encoder *encoder;
 816         struct drm_display_mode *scan; /* *modes, *bios_mode; */
 817         struct drm_display_mode *fixed_mode = NULL;
 818         struct drm_display_mode *downclock_mode = NULL;
 819         struct edid *edid;
 820         i915_reg_t lvds_reg;
 821         u32 lvds;
 822         u8 pin;
 823         u32 allowed_scalers;
 824
 825         /* Skip init on machines we know falsely report LVDS */
 826         if (dmi_check_system(intel_no_lvds)) {
 827                 WARN(!dev_priv->vbt.int_lvds_support,
 828                      "Useless DMI match. Internal LVDS support disabled by VBT\n");
 829                 return;
 830         }
 831
 832         if (!dev_priv->vbt.int_lvds_support) {
 833                 DRM_DEBUG_KMS("Internal LVDS support disabled by VBT\n");
 834                 return;
 835         }
 836
 837         if (HAS_PCH_SPLIT(dev_priv))
 838                 lvds_reg = PCH_LVDS;
 839         else
 840                 lvds_reg = LVDS;
 841
 842         lvds = I915_READ(lvds_reg);
 843
 844         if (HAS_PCH_SPLIT(dev_priv)) {
 845                 if ((lvds & LVDS_DETECTED) == 0)
 846                         return;
 847         }
 848
 849         pin = GMBUS_PIN_PANEL;
 850         if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
 851                 if ((lvds & LVDS_PORT_EN) == 0) {
 852                         DRM_DEBUG_KMS("LVDS is not present in VBT\n");
 853                         return;
 854                 }
 855                 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
 856         }
 857
 858         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
 859         if (!lvds_encoder)
 860                 return;
 861
 862         intel_connector = intel_connector_alloc();
 863         if (!intel_connector) {
 864                 kfree(lvds_encoder);
 865                 return;
 866         }
 867
 868         lvds_encoder->attached_connector = intel_connector;
 869
 870         intel_encoder = &lvds_encoder->base;
 871         encoder = &intel_encoder->base;
 872         connector = &intel_connector->base;
 873         drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
 874                            DRM_MODE_CONNECTOR_LVDS);
 875
 876         drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
 877                          DRM_MODE_ENCODER_LVDS, "LVDS");
 878
 879         intel_encoder->enable = intel_enable_lvds;
 880         intel_encoder->pre_enable = intel_pre_enable_lvds;
 881         intel_encoder->compute_config = intel_lvds_compute_config;
 882         if (HAS_PCH_SPLIT(dev_priv)) {
 883                 intel_encoder->disable = pch_disable_lvds;
 884                 intel_encoder->post_disable = pch_post_disable_lvds;
 885         } else {
 886                 intel_encoder->disable = gmch_disable_lvds;
 887         }
 888         intel_encoder->get_hw_state = intel_lvds_get_hw_state;
 889         intel_encoder->get_config = intel_lvds_get_config;
 890         intel_encoder->update_pipe = intel_panel_update_backlight;
 891         intel_connector->get_hw_state = intel_connector_get_hw_state;
 892
 893         intel_connector_attach_encoder(intel_connector, intel_encoder);
 894
 895         intel_encoder->type = INTEL_OUTPUT_LVDS;
 896         intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
 897         intel_encoder->port = PORT_NONE;
 898         intel_encoder->cloneable = 0;
 899         if (HAS_PCH_SPLIT(dev_priv))
 900                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 901         else if (IS_GEN(dev_priv, 4))
 902                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
 903         else
 904                 intel_encoder->crtc_mask = (1 << 1);
 905
 906         drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
 907         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 908         connector->interlace_allowed = false;
 909         connector->doublescan_allowed = false;
 910
 911         lvds_encoder->reg = lvds_reg;
 912
 913         /* create the scaling mode property */
 914         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
 915         allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
 916         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
 917         drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
 918         connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
 919
 920         intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
 921         lvds_encoder->init_lvds_val = lvds;
 922
 923         /*
 924          * LVDS discovery:
 925          * 1) check for EDID on DDC
 926          * 2) check for VBT data
 927          * 3) check to see if LVDS is already on
 928          *    if none of the above, no panel
 929          */
 930
 931         /*
 932          * Attempt to get the fixed panel mode from DDC.  Assume that the
 933          * preferred mode is the right one.
 934          */
 935         mutex_lock(&dev->mode_config.mutex);
 936         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
 937                 edid = drm_get_edid_switcheroo(connector,
 938                                     intel_gmbus_get_adapter(dev_priv, pin));
 939         else
 940                 edid = drm_get_edid(connector,
 941                                     intel_gmbus_get_adapter(dev_priv, pin));
 942         if (edid) {
 943                 if (drm_add_edid_modes(connector, edid)) {
 944                         drm_connector_update_edid_property(connector,
 945                                                                 edid);
 946                 } else {
 947                         kfree(edid);
 948                         edid = ERR_PTR(-EINVAL);
 949                 }
 950         } else {
 951                 edid = ERR_PTR(-ENOENT);
 952         }
 953         intel_connector->edid = edid;
 954
 955         list_for_each_entry(scan, &connector->probed_modes, head) {
 956                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
 957                         DRM_DEBUG_KMS("using preferred mode from EDID: ");
 958                         drm_mode_debug_printmodeline(scan);
 959
 960                         fixed_mode = drm_mode_duplicate(dev, scan);
 961                         if (fixed_mode)
 962                                 goto out;
 963                 }
 964         }
 965
 966         /* Failed to get EDID, what about VBT? */
 967         if (dev_priv->vbt.lfp_lvds_vbt_mode) {
 968                 DRM_DEBUG_KMS("using mode from VBT: ");
 969                 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
 970
 971                 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
 972                 if (fixed_mode) {
 973                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 974                         connector->display_info.width_mm = fixed_mode->width_mm;
 975                         connector->display_info.height_mm = fixed_mode->height_mm;
 976                         goto out;
 977                 }
 978         }
 979
 980         /*
 981          * If we didn't get EDID, try checking if the panel is already turned
 982          * on.  If so, assume that whatever is currently programmed is the
 983          * correct mode.
 984          */
 985         fixed_mode = intel_encoder_current_mode(intel_encoder);
 986         if (fixed_mode) {
 987                 DRM_DEBUG_KMS("using current (BIOS) mode: ");
 988                 drm_mode_debug_printmodeline(fixed_mode);
 989                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 990         }
 991
 992         /* If we still don't have a mode after all that, give up. */
 993         if (!fixed_mode)
 994                 goto failed;
 995
 996 out:
 997         mutex_unlock(&dev->mode_config.mutex);
 998
 999         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
1000         intel_panel_setup_backlight(connector, INVALID_PIPE);
1001
1002         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1003         DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1004                       lvds_encoder->is_dual_link ? "dual" : "single");
1005
1006         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1007
1008         return;
1009
1010 failed:
1011         mutex_unlock(&dev->mode_config.mutex);
1012
1013         DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1014         drm_connector_cleanup(connector);
1015         drm_encoder_cleanup(encoder);
1016         kfree(lvds_encoder);
1017         intel_connector_free(intel_connector);
1018         return;
1019 }