drivers/gpu/drm/i915/intel_guc_loader.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Vinit Azad <vinit.azad@intel.com>
  25  *    Ben Widawsky <ben@bwidawsk.net>
  26  *    Dave Gordon <david.s.gordon@intel.com>
  27  *    Alex Dai <yu.dai@intel.com>
  28  */
  29 #include <linux/firmware.h>
  30 #include "i915_drv.h"
  31 #include "intel_guc.h"
  32
  33 /**
  34  * DOC: GuC
  35  *
  36  * intel_guc:
  37  * Top level structure of guc. It handles firmware loading and manages client
  38  * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
  39  * ExecList submission.
  40  *
  41  * Firmware versioning:
  42  * The firmware build process will generate a version header file with major and
  43  * minor version defined. The versions are built into CSS header of firmware.
  44  * i915 kernel driver set the minimal firmware version required per platform.
  45  * The firmware installation package will install (symbolic link) proper version
  46  * of firmware.
  47  *
  48  * GuC address space:
  49  * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
  50  * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
  51  * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
  52  * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
  53  *
  54  * Firmware log:
  55  * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
  56  * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
  57  * i915_guc_load_status will print out firmware loading status and scratch
  58  * registers value.
  59  *
  60  */
  61
  62 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
  63 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
  64
  65 /* User-friendly representation of an enum */
  66 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
  67 {
  68         switch (status) {
  69         case GUC_FIRMWARE_FAIL:
  70                 return "FAIL";
  71         case GUC_FIRMWARE_NONE:
  72                 return "NONE";
  73         case GUC_FIRMWARE_PENDING:
  74                 return "PENDING";
  75         case GUC_FIRMWARE_SUCCESS:
  76                 return "SUCCESS";
  77         default:
  78                 return "UNKNOWN!";
  79         }
  80 };
  81
  82 static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
  83 {
  84         struct intel_engine_cs *ring;
  85         int i, irqs;
  86
  87         /* tell all command streamers NOT to forward interrupts and vblank to GuC */
  88         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
  89         irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
  90         for_each_ring(ring, dev_priv, i)
  91                 I915_WRITE(RING_MODE_GEN7(ring), irqs);
  92
  93         /* tell DE to send nothing to GuC */
  94         I915_WRITE(DE_GUCRMR, ~0);
  95
  96         /* route all GT interrupts to the host */
  97         I915_WRITE(GUC_BCS_RCS_IER, 0);
  98         I915_WRITE(GUC_VCS2_VCS1_IER, 0);
  99         I915_WRITE(GUC_WD_VECS_IER, 0);
 100 }
 101
 102 static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 103 {
 104         struct intel_engine_cs *ring;
 105         int i, irqs;
 106
 107         /* tell all command streamers to forward interrupts and vblank to GuC */
 108         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS);
 109         irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
 110         for_each_ring(ring, dev_priv, i)
 111                 I915_WRITE(RING_MODE_GEN7(ring), irqs);
 112
 113         /* tell DE to send (all) flip_done to GuC */
 114         irqs = DERRMR_PIPEA_PRI_FLIP_DONE | DERRMR_PIPEA_SPR_FLIP_DONE |
 115                DERRMR_PIPEB_PRI_FLIP_DONE | DERRMR_PIPEB_SPR_FLIP_DONE |
 116                DERRMR_PIPEC_PRI_FLIP_DONE | DERRMR_PIPEC_SPR_FLIP_DONE;
 117         /* Unmasked bits will cause GuC response message to be sent */
 118         I915_WRITE(DE_GUCRMR, ~irqs);
 119
 120         /* route USER_INTERRUPT to Host, all others are sent to GuC. */
 121         irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
 122                GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
 123         /* These three registers have the same bit definitions */
 124         I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
 125         I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
 126         I915_WRITE(GUC_WD_VECS_IER, ~irqs);
 127 }
 128
 129 static u32 get_gttype(struct drm_i915_private *dev_priv)
 130 {
 131         /* XXX: GT type based on PCI device ID? field seems unused by fw */
 132         return 0;
 133 }
 134
 135 static u32 get_core_family(struct drm_i915_private *dev_priv)
 136 {
 137         switch (INTEL_INFO(dev_priv)->gen) {
 138         case 9:
 139                 return GFXCORE_FAMILY_GEN9;
 140
 141         default:
 142                 DRM_ERROR("GUC: unsupported core family\n");
 143                 return GFXCORE_FAMILY_UNKNOWN;
 144         }
 145 }
 146
 147 static void set_guc_init_params(struct drm_i915_private *dev_priv)
 148 {
 149         struct intel_guc *guc = &dev_priv->guc;
 150         u32 params[GUC_CTL_MAX_DWORDS];
 151         int i;
 152
 153         memset(&params, 0, sizeof(params));
 154
 155         params[GUC_CTL_DEVICE_INFO] |=
 156                 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
 157                 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
 158
 159         /*
 160          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 161          * second. This ARAR is calculated by:
 162          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
 163          */
 164         params[GUC_CTL_ARAT_HIGH] = 0;
 165         params[GUC_CTL_ARAT_LOW] = 100000000;
 166
 167         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
 168
 169         params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 170                         GUC_CTL_VCS2_ENABLED;
 171
 172         if (i915.guc_log_level >= 0) {
 173                 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 174                 params[GUC_CTL_DEBUG] =
 175                         i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
 176         }
 177
 178         /* If GuC submission is enabled, set up additional parameters here */
 179         if (i915.enable_guc_submission) {
 180                 u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
 181                 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
 182
 183                 pgs >>= PAGE_SHIFT;
 184                 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
 185                         (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
 186
 187                 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
 188
 189                 /* Unmask this bit to enable the GuC's internal scheduler */
 190                 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
 191         }
 192
 193         I915_WRITE(SOFT_SCRATCH(0), 0);
 194
 195         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 196                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 197 }
 198
 199 /*
 200  * Read the GuC status register (GUC_STATUS) and store it in the
 201  * specified location; then return a boolean indicating whether
 202  * the value matches either of two values representing completion
 203  * of the GuC boot process.
 204  *
 205  * This is used for polling the GuC status in a wait_for_atomic()
 206  * loop below.
 207  */
 208 static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
 209                                       u32 *status)
 210 {
 211         u32 val = I915_READ(GUC_STATUS);
 212         *status = val;
 213         return ((val & GS_UKERNEL_MASK) == GS_UKERNEL_READY ||
 214                 (val & GS_UKERNEL_MASK) == GS_UKERNEL_LAPIC_DONE);
 215 }
 216
 217 /*
 218  * Transfer the firmware image to RAM for execution by the microcontroller.
 219  *
 220  * GuC Firmware layout:
 221  * +-------------------------------+  ----
 222  * |          CSS header           |  128B
 223  * | contains major/minor version  |
 224  * +-------------------------------+  ----
 225  * |             uCode             |
 226  * +-------------------------------+  ----
 227  * |         RSA signature         |  256B
 228  * +-------------------------------+  ----
 229  *
 230  * Architecturally, the DMA engine is bidirectional, and can potentially even
 231  * transfer between GTT locations. This functionality is left out of the API
 232  * for now as there is no need for it.
 233  *
 234  * Note that GuC needs the CSS header plus uKernel code to be copied by the
 235  * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
 236  */
 237
 238 #define UOS_CSS_HEADER_OFFSET           0
 239 #define UOS_VER_MINOR_OFFSET            0x44
 240 #define UOS_VER_MAJOR_OFFSET            0x46
 241 #define UOS_CSS_HEADER_SIZE             0x80
 242 #define UOS_RSA_SIG_SIZE                0x100
 243
 244 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
 245 {
 246         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 247         struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
 248         unsigned long offset;
 249         struct sg_table *sg = fw_obj->pages;
 250         u32 status, ucode_size, rsa[UOS_RSA_SIG_SIZE / sizeof(u32)];
 251         int i, ret = 0;
 252
 253         /* uCode size, also is where RSA signature starts */
 254         offset = ucode_size = guc_fw->guc_fw_size - UOS_RSA_SIG_SIZE;
 255         I915_WRITE(DMA_COPY_SIZE, ucode_size);
 256
 257         /* Copy RSA signature from the fw image to HW for verification */
 258         sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, UOS_RSA_SIG_SIZE, offset);
 259         for (i = 0; i < UOS_RSA_SIG_SIZE / sizeof(u32); i++)
 260                 I915_WRITE(UOS_RSA_SCRATCH_0 + i * sizeof(u32), rsa[i]);
 261
 262         /* Set the source address for the new blob */
 263         offset = i915_gem_obj_ggtt_offset(fw_obj);
 264         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 265         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 266
 267         /*
 268          * Set the DMA destination. Current uCode expects the code to be
 269          * loaded at 8k; locations below this are used for the stack.
 270          */
 271         I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
 272         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 273
 274         /* Finally start the DMA */
 275         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
 276
 277         /*
 278          * Spin-wait for the DMA to complete & the GuC to start up.
 279          * NB: Docs recommend not using the interrupt for completion.
 280          * Measurements indicate this should take no more than 20ms, so a
 281          * timeout here indicates that the GuC has failed and is unusable.
 282          * (Higher levels of the driver will attempt to fall back to
 283          * execlist mode if this happens.)
 284          */
 285         ret = wait_for_atomic(guc_ucode_response(dev_priv, &status), 100);
 286
 287         DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
 288                         I915_READ(DMA_CTRL), status);
 289
 290         if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
 291                 DRM_ERROR("GuC firmware signature verification failed\n");
 292                 ret = -ENOEXEC;
 293         }
 294
 295         DRM_DEBUG_DRIVER("returning %d\n", ret);
 296
 297         return ret;
 298 }
 299
 300 /*
 301  * Load the GuC firmware blob into the MinuteIA.
 302  */
 303 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 304 {
 305         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 306         struct drm_device *dev = dev_priv->dev;
 307         int ret;
 308
 309         ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
 310         if (ret) {
 311                 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
 312                 return ret;
 313         }
 314
 315         ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
 316         if (ret) {
 317                 DRM_DEBUG_DRIVER("pin failed %d\n", ret);
 318                 return ret;
 319         }
 320
 321         /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
 322         I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 323
 324         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 325
 326         /* init WOPCM */
 327         I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
 328         I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 329
 330         /* Enable MIA caching. GuC clock gating is disabled. */
 331         I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 332
 333         /* WaC6DisallowByGfxPause*/
 334         I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
 335
 336         if (IS_BROXTON(dev))
 337                 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 338         else
 339                 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 340
 341         if (IS_GEN9(dev)) {
 342                 /* DOP Clock Gating Enable for GuC clocks */
 343                 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
 344                                             I915_READ(GEN7_MISCCPCTL)));
 345
 346                 /* allows for 5us before GT can go to RC6 */
 347                 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
 348         }
 349
 350         set_guc_init_params(dev_priv);
 351
 352         ret = guc_ucode_xfer_dma(dev_priv);
 353
 354         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 355
 356         /*
 357          * We keep the object pages for reuse during resume. But we can unpin it
 358          * now that DMA has completed, so it doesn't continue to take up space.
 359          */
 360         i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
 361
 362         return ret;
 363 }
 364
 365 /**
 366  * intel_guc_ucode_load() - load GuC uCode into the device
 367  * @dev:        drm device
 368  *
 369  * Called from gem_init_hw() during driver loading and also after a GPU reset.
 370  *
 371  * The firmware image should have already been fetched into memory by the
 372  * earlier call to intel_guc_ucode_init(), so here we need only check that
 373  * is succeeded, and then transfer the image to the h/w.
 374  *
 375  * Return:      non-zero code on error
 376  */
 377 int intel_guc_ucode_load(struct drm_device *dev)
 378 {
 379         struct drm_i915_private *dev_priv = dev->dev_private;
 380         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 381         int err = 0;
 382
 383         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 384                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 385                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 386
 387         direct_interrupts_to_host(dev_priv);
 388         i915_guc_submission_disable(dev);
 389
 390         if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE)
 391                 return 0;
 392
 393         if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS &&
 394             guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL)
 395                 return -ENOEXEC;
 396
 397         guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
 398
 399         DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
 400                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
 401
 402         switch (guc_fw->guc_fw_fetch_status) {
 403         case GUC_FIRMWARE_FAIL:
 404                 /* something went wrong :( */
 405                 err = -EIO;
 406                 goto fail;
 407
 408         case GUC_FIRMWARE_NONE:
 409         case GUC_FIRMWARE_PENDING:
 410         default:
 411                 /* "can't happen" */
 412                 WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
 413                         guc_fw->guc_fw_path,
 414                         intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 415                         guc_fw->guc_fw_fetch_status);
 416                 err = -ENXIO;
 417                 goto fail;
 418
 419         case GUC_FIRMWARE_SUCCESS:
 420                 break;
 421         }
 422
 423         err = i915_guc_submission_init(dev);
 424         if (err)
 425                 goto fail;
 426
 427         err = guc_ucode_xfer(dev_priv);
 428         if (err)
 429                 goto fail;
 430
 431         guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
 432
 433         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 434                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 435                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 436
 437         if (i915.enable_guc_submission) {
 438                 err = i915_guc_submission_enable(dev);
 439                 if (err)
 440                         goto fail;
 441                 direct_interrupts_to_guc(dev_priv);
 442         }
 443
 444         return 0;
 445
 446 fail:
 447         if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
 448                 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
 449
 450         direct_interrupts_to_host(dev_priv);
 451         i915_guc_submission_disable(dev);
 452
 453         return err;
 454 }
 455
 456 static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 457 {
 458         struct drm_i915_gem_object *obj;
 459         const struct firmware *fw;
 460         const u8 *css_header;
 461         const size_t minsize = UOS_CSS_HEADER_SIZE + UOS_RSA_SIG_SIZE;
 462         const size_t maxsize = GUC_WOPCM_SIZE_VALUE + UOS_RSA_SIG_SIZE
 463                         - 0x8000; /* 32k reserved (8K stack + 24k context) */
 464         int err;
 465
 466         DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
 467                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
 468
 469         err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
 470         if (err)
 471                 goto fail;
 472         if (!fw)
 473                 goto fail;
 474
 475         DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
 476                 guc_fw->guc_fw_path, fw);
 477         DRM_DEBUG_DRIVER("firmware file size %zu (minimum %zu, maximum %zu)\n",
 478                 fw->size, minsize, maxsize);
 479
 480         /* Check the size of the blob befoe examining buffer contents */
 481         if (fw->size < minsize || fw->size > maxsize)
 482                 goto fail;
 483
 484         /*
 485          * The GuC firmware image has the version number embedded at a well-known
 486          * offset within the firmware blob; note that major / minor version are
 487          * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 488          * in terms of bytes (u8).
 489          */
 490         css_header = fw->data + UOS_CSS_HEADER_OFFSET;
 491         guc_fw->guc_fw_major_found = *(u16 *)(css_header + UOS_VER_MAJOR_OFFSET);
 492         guc_fw->guc_fw_minor_found = *(u16 *)(css_header + UOS_VER_MINOR_OFFSET);
 493
 494         if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
 495             guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
 496                 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
 497                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 498                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 499                 err = -ENOEXEC;
 500                 goto fail;
 501         }
 502
 503         DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
 504                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 505                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 506
 507         obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
 508         if (IS_ERR_OR_NULL(obj)) {
 509                 err = obj ? PTR_ERR(obj) : -ENOMEM;
 510                 goto fail;
 511         }
 512
 513         guc_fw->guc_fw_obj = obj;
 514         guc_fw->guc_fw_size = fw->size;
 515
 516         DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
 517                         guc_fw->guc_fw_obj);
 518
 519         release_firmware(fw);
 520         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
 521         return;
 522
 523 fail:
 524         DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
 525                 err, fw, guc_fw->guc_fw_obj);
 526         DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
 527                   guc_fw->guc_fw_path, err);
 528
 529         obj = guc_fw->guc_fw_obj;
 530         if (obj)
 531                 drm_gem_object_unreference(&obj->base);
 532         guc_fw->guc_fw_obj = NULL;
 533
 534         release_firmware(fw);           /* OK even if fw is NULL */
 535         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
 536 }
 537
 538 /**
 539  * intel_guc_ucode_init() - define parameters and fetch firmware
 540  * @dev:        drm device
 541  *
 542  * Called early during driver load, but after GEM is initialised.
 543  * The device struct_mutex must be held by the caller, as we're
 544  * going to allocate a GEM object to hold the firmware image.
 545  *
 546  * The firmware will be transferred to the GuC's memory later,
 547  * when intel_guc_ucode_load() is called.
 548  */
 549 void intel_guc_ucode_init(struct drm_device *dev)
 550 {
 551         struct drm_i915_private *dev_priv = dev->dev_private;
 552         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 553         const char *fw_path;
 554
 555         if (!HAS_GUC_SCHED(dev))
 556                 i915.enable_guc_submission = false;
 557
 558         if (!HAS_GUC_UCODE(dev)) {
 559                 fw_path = NULL;
 560         } else if (IS_SKYLAKE(dev)) {
 561                 fw_path = I915_SKL_GUC_UCODE;
 562                 guc_fw->guc_fw_major_wanted = 4;
 563                 guc_fw->guc_fw_minor_wanted = 3;
 564         } else {
 565                 i915.enable_guc_submission = false;
 566                 fw_path = "";   /* unknown device */
 567         }
 568
 569         guc_fw->guc_dev = dev;
 570         guc_fw->guc_fw_path = fw_path;
 571         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 572         guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
 573
 574         if (fw_path == NULL)
 575                 return;
 576
 577         if (*fw_path == '\0') {
 578                 DRM_ERROR("No GuC firmware known for this platform\n");
 579                 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
 580                 return;
 581         }
 582
 583         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
 584         DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 585         guc_fw_fetch(dev, guc_fw);
 586         /* status must now be FAIL or SUCCESS */
 587 }
 588
 589 /**
 590  * intel_guc_ucode_fini() - clean up all allocated resources
 591  * @dev:        drm device
 592  */
 593 void intel_guc_ucode_fini(struct drm_device *dev)
 594 {
 595         struct drm_i915_private *dev_priv = dev->dev_private;
 596         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 597
 598         direct_interrupts_to_host(dev_priv);
 599         i915_guc_submission_fini(dev);
 600
 601         if (guc_fw->guc_fw_obj)
 602                 drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
 603         guc_fw->guc_fw_obj = NULL;
 604
 605         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 606 }