drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  45 {
  46         return HAS_FBC(dev_priv);
  47 }
  48
  49 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  50 {
  51         return INTEL_GEN(dev_priv) <= 3;
  52 }
  53
  54 /*
  55  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  56  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  57  * origin so the x and y offsets can actually fit the registers. As a
  58  * consequence, the fence doesn't really start exactly at the display plane
  59  * address we program because it starts at the real start of the buffer, so we
  60  * have to take this into consideration here.
  61  */
  62 static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
  63 {
  64         return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
  65 }
  66
  67 /*
  68  * For SKL+, the plane source size used by the hardware is based on the value we
  69  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  70  * we wrote to PIPESRC.
  71  */
  72 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  73                                             int *width, int *height)
  74 {
  75         if (width)
  76                 *width = cache->plane.src_w;
  77         if (height)
  78                 *height = cache->plane.src_h;
  79 }
  80
  81 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  82                                         struct intel_fbc_state_cache *cache)
  83 {
  84         int lines;
  85
  86         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  87         if (IS_GEN7(dev_priv))
  88                 lines = min(lines, 2048);
  89         else if (INTEL_GEN(dev_priv) >= 8)
  90                 lines = min(lines, 2560);
  91
  92         /* Hardware needs the full buffer stride, not just the active area. */
  93         return lines * cache->fb.stride;
  94 }
  95
  96 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
  97 {
  98         u32 fbc_ctl;
  99
 100         /* Disable compression */
 101         fbc_ctl = I915_READ(FBC_CONTROL);
 102         if ((fbc_ctl & FBC_CTL_EN) == 0)
 103                 return;
 104
 105         fbc_ctl &= ~FBC_CTL_EN;
 106         I915_WRITE(FBC_CONTROL, fbc_ctl);
 107
 108         /* Wait for compressing bit to clear */
 109         if (intel_wait_for_register(dev_priv,
 110                                     FBC_STATUS, FBC_STAT_COMPRESSING, 0,
 111                                     10)) {
 112                 DRM_DEBUG_KMS("FBC idle timed out\n");
 113                 return;
 114         }
 115 }
 116
 117 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 118 {
 119         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 120         int cfb_pitch;
 121         int i;
 122         u32 fbc_ctl;
 123
 124         /* Note: fbc.threshold == 1 for i8xx */
 125         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 126         if (params->fb.stride < cfb_pitch)
 127                 cfb_pitch = params->fb.stride;
 128
 129         /* FBC_CTL wants 32B or 64B units */
 130         if (IS_GEN2(dev_priv))
 131                 cfb_pitch = (cfb_pitch / 32) - 1;
 132         else
 133                 cfb_pitch = (cfb_pitch / 64) - 1;
 134
 135         /* Clear old tags */
 136         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 137                 I915_WRITE(FBC_TAG(i), 0);
 138
 139         if (IS_GEN4(dev_priv)) {
 140                 u32 fbc_ctl2;
 141
 142                 /* Set it up... */
 143                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 144                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
 145                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 146                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 147         }
 148
 149         /* enable it... */
 150         fbc_ctl = I915_READ(FBC_CONTROL);
 151         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 152         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 153         if (IS_I945GM(dev_priv))
 154                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 155         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 156         fbc_ctl |= params->vma->fence->id;
 157         I915_WRITE(FBC_CONTROL, fbc_ctl);
 158 }
 159
 160 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 161 {
 162         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 163 }
 164
 165 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 166 {
 167         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 168         u32 dpfc_ctl;
 169
 170         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
 171         if (params->fb.format->cpp[0] == 2)
 172                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 173         else
 174                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 175
 176         if (params->flags & PLANE_HAS_FENCE) {
 177                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
 178                 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 179         } else {
 180                 I915_WRITE(DPFC_FENCE_YOFF, 0);
 181         }
 182
 183         /* enable it... */
 184         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 185 }
 186
 187 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 188 {
 189         u32 dpfc_ctl;
 190
 191         /* Disable compression */
 192         dpfc_ctl = I915_READ(DPFC_CONTROL);
 193         if (dpfc_ctl & DPFC_CTL_EN) {
 194                 dpfc_ctl &= ~DPFC_CTL_EN;
 195                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 196         }
 197 }
 198
 199 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 200 {
 201         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 202 }
 203
 204 /* This function forces a CFB recompression through the nuke operation. */
 205 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 206 {
 207         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 208         POSTING_READ(MSG_FBC_REND_STATE);
 209 }
 210
 211 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 212 {
 213         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 214         u32 dpfc_ctl;
 215         int threshold = dev_priv->fbc.threshold;
 216
 217         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 218         if (params->fb.format->cpp[0] == 2)
 219                 threshold++;
 220
 221         switch (threshold) {
 222         case 4:
 223         case 3:
 224                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 225                 break;
 226         case 2:
 227                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 228                 break;
 229         case 1:
 230                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 231                 break;
 232         }
 233
 234         if (params->flags & PLANE_HAS_FENCE) {
 235                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 236                 if (IS_GEN5(dev_priv))
 237                         dpfc_ctl |= params->vma->fence->id;
 238                 if (IS_GEN6(dev_priv)) {
 239                         I915_WRITE(SNB_DPFC_CTL_SA,
 240                                    SNB_CPU_FENCE_ENABLE |
 241                                    params->vma->fence->id);
 242                         I915_WRITE(DPFC_CPU_FENCE_OFFSET,
 243                                    params->crtc.fence_y_offset);
 244                 }
 245         } else {
 246                 if (IS_GEN6(dev_priv)) {
 247                         I915_WRITE(SNB_DPFC_CTL_SA, 0);
 248                         I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 249                 }
 250         }
 251
 252         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 253         I915_WRITE(ILK_FBC_RT_BASE,
 254                    i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);
 255         /* enable it... */
 256         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 257
 258         intel_fbc_recompress(dev_priv);
 259 }
 260
 261 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 262 {
 263         u32 dpfc_ctl;
 264
 265         /* Disable compression */
 266         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 267         if (dpfc_ctl & DPFC_CTL_EN) {
 268                 dpfc_ctl &= ~DPFC_CTL_EN;
 269                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 270         }
 271 }
 272
 273 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 274 {
 275         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 276 }
 277
 278 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 279 {
 280         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 281         u32 dpfc_ctl;
 282         int threshold = dev_priv->fbc.threshold;
 283
 284         /* Display WA #0529: skl, kbl, bxt. */
 285         if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
 286                 u32 val = I915_READ(CHICKEN_MISC_4);
 287
 288                 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 289
 290                 if (i915_gem_object_get_tiling(params->vma->obj) !=
 291                     I915_TILING_X)
 292                         val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 293
 294                 I915_WRITE(CHICKEN_MISC_4, val);
 295         }
 296
 297         dpfc_ctl = 0;
 298         if (IS_IVYBRIDGE(dev_priv))
 299                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 300
 301         if (params->fb.format->cpp[0] == 2)
 302                 threshold++;
 303
 304         switch (threshold) {
 305         case 4:
 306         case 3:
 307                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 308                 break;
 309         case 2:
 310                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 311                 break;
 312         case 1:
 313                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 314                 break;
 315         }
 316
 317         if (params->flags & PLANE_HAS_FENCE) {
 318                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 319                 I915_WRITE(SNB_DPFC_CTL_SA,
 320                            SNB_CPU_FENCE_ENABLE |
 321                            params->vma->fence->id);
 322                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 323         } else {
 324                 I915_WRITE(SNB_DPFC_CTL_SA,0);
 325                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 326         }
 327
 328         if (dev_priv->fbc.false_color)
 329                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 330
 331         if (IS_IVYBRIDGE(dev_priv)) {
 332                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 333                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 334                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 335                            ILK_FBCQ_DIS);
 336         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 337                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 338                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 339                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 340                            HSW_FBCQ_DIS);
 341         }
 342
 343         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 344
 345         intel_fbc_recompress(dev_priv);
 346 }
 347
 348 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 349 {
 350         if (INTEL_GEN(dev_priv) >= 5)
 351                 return ilk_fbc_is_active(dev_priv);
 352         else if (IS_GM45(dev_priv))
 353                 return g4x_fbc_is_active(dev_priv);
 354         else
 355                 return i8xx_fbc_is_active(dev_priv);
 356 }
 357
 358 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 359 {
 360         struct intel_fbc *fbc = &dev_priv->fbc;
 361
 362         fbc->active = true;
 363
 364         if (INTEL_GEN(dev_priv) >= 7)
 365                 gen7_fbc_activate(dev_priv);
 366         else if (INTEL_GEN(dev_priv) >= 5)
 367                 ilk_fbc_activate(dev_priv);
 368         else if (IS_GM45(dev_priv))
 369                 g4x_fbc_activate(dev_priv);
 370         else
 371                 i8xx_fbc_activate(dev_priv);
 372 }
 373
 374 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 375 {
 376         struct intel_fbc *fbc = &dev_priv->fbc;
 377
 378         fbc->active = false;
 379
 380         if (INTEL_GEN(dev_priv) >= 5)
 381                 ilk_fbc_deactivate(dev_priv);
 382         else if (IS_GM45(dev_priv))
 383                 g4x_fbc_deactivate(dev_priv);
 384         else
 385                 i8xx_fbc_deactivate(dev_priv);
 386 }
 387
 388 /**
 389  * intel_fbc_is_active - Is FBC active?
 390  * @dev_priv: i915 device instance
 391  *
 392  * This function is used to verify the current state of FBC.
 393  *
 394  * FIXME: This should be tracked in the plane config eventually
 395  * instead of queried at runtime for most callers.
 396  */
 397 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 398 {
 399         return dev_priv->fbc.active;
 400 }
 401
 402 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 403                                  const char *reason)
 404 {
 405         struct intel_fbc *fbc = &dev_priv->fbc;
 406
 407         WARN_ON(!mutex_is_locked(&fbc->lock));
 408
 409         if (fbc->active)
 410                 intel_fbc_hw_deactivate(dev_priv);
 411
 412         fbc->no_fbc_reason = reason;
 413 }
 414
 415 static bool multiple_pipes_ok(struct intel_crtc *crtc,
 416                               struct intel_plane_state *plane_state)
 417 {
 418         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 419         struct intel_fbc *fbc = &dev_priv->fbc;
 420         enum pipe pipe = crtc->pipe;
 421
 422         /* Don't even bother tracking anything we don't need. */
 423         if (!no_fbc_on_multiple_pipes(dev_priv))
 424                 return true;
 425
 426         if (plane_state->base.visible)
 427                 fbc->visible_pipes_mask |= (1 << pipe);
 428         else
 429                 fbc->visible_pipes_mask &= ~(1 << pipe);
 430
 431         return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
 432 }
 433
 434 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 435                                       struct drm_mm_node *node,
 436                                       int size,
 437                                       int fb_cpp)
 438 {
 439         int compression_threshold = 1;
 440         int ret;
 441         u64 end;
 442
 443         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 444          * reserved range size, so it always assumes the maximum (8mb) is used.
 445          * If we enable FBC using a CFB on that memory range we'll get FIFO
 446          * underruns, even if that range is not reserved by the BIOS. */
 447         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 448                 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
 449         else
 450                 end = U64_MAX;
 451
 452         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 453          * code changes, this code needs to change as well.
 454          *
 455          * The enable_fbc code will attempt to use one of our 2 compression
 456          * thresholds, therefore, in that case, we only have 1 resort.
 457          */
 458
 459         /* Try to over-allocate to reduce reallocations and fragmentation. */
 460         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 461                                                    4096, 0, end);
 462         if (ret == 0)
 463                 return compression_threshold;
 464
 465 again:
 466         /* HW's ability to limit the CFB is 1:4 */
 467         if (compression_threshold > 4 ||
 468             (fb_cpp == 2 && compression_threshold == 2))
 469                 return 0;
 470
 471         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 472                                                    4096, 0, end);
 473         if (ret && INTEL_GEN(dev_priv) <= 4) {
 474                 return 0;
 475         } else if (ret) {
 476                 compression_threshold <<= 1;
 477                 goto again;
 478         } else {
 479                 return compression_threshold;
 480         }
 481 }
 482
 483 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 484 {
 485         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 486         struct intel_fbc *fbc = &dev_priv->fbc;
 487         struct drm_mm_node *uninitialized_var(compressed_llb);
 488         int size, fb_cpp, ret;
 489
 490         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 491
 492         size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
 493         fb_cpp = fbc->state_cache.fb.format->cpp[0];
 494
 495         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 496                                          size, fb_cpp);
 497         if (!ret)
 498                 goto err_llb;
 499         else if (ret > 1) {
 500                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 501
 502         }
 503
 504         fbc->threshold = ret;
 505
 506         if (INTEL_GEN(dev_priv) >= 5)
 507                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 508         else if (IS_GM45(dev_priv)) {
 509                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 510         } else {
 511                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 512                 if (!compressed_llb)
 513                         goto err_fb;
 514
 515                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 516                                                   4096, 4096);
 517                 if (ret)
 518                         goto err_fb;
 519
 520                 fbc->compressed_llb = compressed_llb;
 521
 522                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 523                                              fbc->compressed_fb.start,
 524                                              U32_MAX));
 525                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 526                                              fbc->compressed_llb->start,
 527                                              U32_MAX));
 528                 I915_WRITE(FBC_CFB_BASE,
 529                            dev_priv->dsm.start + fbc->compressed_fb.start);
 530                 I915_WRITE(FBC_LL_BASE,
 531                            dev_priv->dsm.start + compressed_llb->start);
 532         }
 533
 534         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 535                       fbc->compressed_fb.size, fbc->threshold);
 536
 537         return 0;
 538
 539 err_fb:
 540         kfree(compressed_llb);
 541         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 542 err_llb:
 543         if (drm_mm_initialized(&dev_priv->mm.stolen))
 544                 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 545         return -ENOSPC;
 546 }
 547
 548 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 549 {
 550         struct intel_fbc *fbc = &dev_priv->fbc;
 551
 552         if (drm_mm_node_allocated(&fbc->compressed_fb))
 553                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 554
 555         if (fbc->compressed_llb) {
 556                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 557                 kfree(fbc->compressed_llb);
 558         }
 559 }
 560
 561 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 562 {
 563         struct intel_fbc *fbc = &dev_priv->fbc;
 564
 565         if (!fbc_supported(dev_priv))
 566                 return;
 567
 568         mutex_lock(&fbc->lock);
 569         __intel_fbc_cleanup_cfb(dev_priv);
 570         mutex_unlock(&fbc->lock);
 571 }
 572
 573 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 574                             unsigned int stride)
 575 {
 576         /* This should have been caught earlier. */
 577         if (WARN_ON_ONCE((stride & (64 - 1)) != 0))
 578                 return false;
 579
 580         /* Below are the additional FBC restrictions. */
 581         if (stride < 512)
 582                 return false;
 583
 584         if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
 585                 return stride == 4096 || stride == 8192;
 586
 587         if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
 588                 return false;
 589
 590         if (stride > 16384)
 591                 return false;
 592
 593         return true;
 594 }
 595
 596 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 597                                   uint32_t pixel_format)
 598 {
 599         switch (pixel_format) {
 600         case DRM_FORMAT_XRGB8888:
 601         case DRM_FORMAT_XBGR8888:
 602                 return true;
 603         case DRM_FORMAT_XRGB1555:
 604         case DRM_FORMAT_RGB565:
 605                 /* 16bpp not supported on gen2 */
 606                 if (IS_GEN2(dev_priv))
 607                         return false;
 608                 /* WaFbcOnly1to1Ratio:ctg */
 609                 if (IS_G4X(dev_priv))
 610                         return false;
 611                 return true;
 612         default:
 613                 return false;
 614         }
 615 }
 616
 617 /*
 618  * For some reason, the hardware tracking starts looking at whatever we
 619  * programmed as the display plane base address register. It does not look at
 620  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 621  * variables instead of just looking at the pipe/plane size.
 622  */
 623 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 624 {
 625         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 626         struct intel_fbc *fbc = &dev_priv->fbc;
 627         unsigned int effective_w, effective_h, max_w, max_h;
 628
 629         if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 630                 max_w = 4096;
 631                 max_h = 4096;
 632         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 633                 max_w = 4096;
 634                 max_h = 2048;
 635         } else {
 636                 max_w = 2048;
 637                 max_h = 1536;
 638         }
 639
 640         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 641                                         &effective_h);
 642         effective_w += fbc->state_cache.plane.adjusted_x;
 643         effective_h += fbc->state_cache.plane.adjusted_y;
 644
 645         return effective_w <= max_w && effective_h <= max_h;
 646 }
 647
 648 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 649                                          struct intel_crtc_state *crtc_state,
 650                                          struct intel_plane_state *plane_state)
 651 {
 652         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 653         struct intel_fbc *fbc = &dev_priv->fbc;
 654         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 655         struct drm_framebuffer *fb = plane_state->base.fb;
 656
 657         cache->vma = NULL;
 658         cache->flags = 0;
 659
 660         cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
 661         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 662                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 663
 664         cache->plane.rotation = plane_state->base.rotation;
 665         /*
 666          * Src coordinates are already rotated by 270 degrees for
 667          * the 90/270 degree plane rotation cases (to match the
 668          * GTT mapping), hence no need to account for rotation here.
 669          */
 670         cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 671         cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 672         cache->plane.visible = plane_state->base.visible;
 673         cache->plane.adjusted_x = plane_state->color_plane[0].x;
 674         cache->plane.adjusted_y = plane_state->color_plane[0].y;
 675         cache->plane.y = plane_state->base.src.y1 >> 16;
 676
 677         cache->plane.pixel_blend_mode = plane_state->base.pixel_blend_mode;
 678
 679         if (!cache->plane.visible)
 680                 return;
 681
 682         cache->fb.format = fb->format;
 683         cache->fb.stride = fb->pitches[0];
 684
 685         cache->vma = plane_state->vma;
 686         cache->flags = plane_state->flags;
 687         if (WARN_ON(cache->flags & PLANE_HAS_FENCE && !cache->vma->fence))
 688                 cache->flags &= ~PLANE_HAS_FENCE;
 689 }
 690
 691 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 692 {
 693         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 694         struct intel_fbc *fbc = &dev_priv->fbc;
 695         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 696
 697         /* We don't need to use a state cache here since this information is
 698          * global for all CRTC.
 699          */
 700         if (fbc->underrun_detected) {
 701                 fbc->no_fbc_reason = "underrun detected";
 702                 return false;
 703         }
 704
 705         if (!cache->vma) {
 706                 fbc->no_fbc_reason = "primary plane not visible";
 707                 return false;
 708         }
 709
 710         if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
 711                 fbc->no_fbc_reason = "incompatible mode";
 712                 return false;
 713         }
 714
 715         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 716                 fbc->no_fbc_reason = "mode too large for compression";
 717                 return false;
 718         }
 719
 720         /* The use of a CPU fence is mandatory in order to detect writes
 721          * by the CPU to the scanout and trigger updates to the FBC.
 722          *
 723          * Note that is possible for a tiled surface to be unmappable (and
 724          * so have no fence associated with it) due to aperture constaints
 725          * at the time of pinning.
 726          *
 727          * FIXME with 90/270 degree rotation we should use the fence on
 728          * the normal GTT view (the rotated view doesn't even have a
 729          * fence). Would need changes to the FBC fence Y offset as well.
 730          * For now this will effecively disable FBC with 90/270 degree
 731          * rotation.
 732          */
 733         if (!(cache->flags & PLANE_HAS_FENCE)) {
 734                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 735                 return false;
 736         }
 737         if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 738             cache->plane.rotation != DRM_MODE_ROTATE_0) {
 739                 fbc->no_fbc_reason = "rotation unsupported";
 740                 return false;
 741         }
 742
 743         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 744                 fbc->no_fbc_reason = "framebuffer stride not supported";
 745                 return false;
 746         }
 747
 748         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 749                 fbc->no_fbc_reason = "pixel format is invalid";
 750                 return false;
 751         }
 752
 753         if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
 754             cache->fb.format->has_alpha) {
 755                 fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
 756                 return false;
 757         }
 758
 759         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 760         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 761             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 762                 fbc->no_fbc_reason = "pixel rate is too big";
 763                 return false;
 764         }
 765
 766         /* It is possible for the required CFB size change without a
 767          * crtc->disable + crtc->enable since it is possible to change the
 768          * stride without triggering a full modeset. Since we try to
 769          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 770          * if this happens, but if we exceed the current CFB size we'll have to
 771          * disable FBC. Notice that it would be possible to disable FBC, wait
 772          * for a frame, free the stolen node, then try to reenable FBC in case
 773          * we didn't get any invalidate/deactivate calls, but this would require
 774          * a lot of tracking just for a specific case. If we conclude it's an
 775          * important case, we can implement it later. */
 776         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 777             fbc->compressed_fb.size * fbc->threshold) {
 778                 fbc->no_fbc_reason = "CFB requirements changed";
 779                 return false;
 780         }
 781
 782         /*
 783          * Work around a problem on GEN9+ HW, where enabling FBC on a plane
 784          * having a Y offset that isn't divisible by 4 causes FIFO underrun
 785          * and screen flicker.
 786          */
 787         if (IS_GEN(dev_priv, 9, 10) &&
 788             (fbc->state_cache.plane.adjusted_y & 3)) {
 789                 fbc->no_fbc_reason = "plane Y offset is misaligned";
 790                 return false;
 791         }
 792
 793         return true;
 794 }
 795
 796 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 797 {
 798         struct intel_fbc *fbc = &dev_priv->fbc;
 799
 800         if (intel_vgpu_active(dev_priv)) {
 801                 fbc->no_fbc_reason = "VGPU is active";
 802                 return false;
 803         }
 804
 805         if (!i915_modparams.enable_fbc) {
 806                 fbc->no_fbc_reason = "disabled per module param or by default";
 807                 return false;
 808         }
 809
 810         if (fbc->underrun_detected) {
 811                 fbc->no_fbc_reason = "underrun detected";
 812                 return false;
 813         }
 814
 815         return true;
 816 }
 817
 818 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 819                                      struct intel_fbc_reg_params *params)
 820 {
 821         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 822         struct intel_fbc *fbc = &dev_priv->fbc;
 823         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 824
 825         /* Since all our fields are integer types, use memset here so the
 826          * comparison function can rely on memcmp because the padding will be
 827          * zero. */
 828         memset(params, 0, sizeof(*params));
 829
 830         params->vma = cache->vma;
 831         params->flags = cache->flags;
 832
 833         params->crtc.pipe = crtc->pipe;
 834         params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
 835         params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
 836
 837         params->fb.format = cache->fb.format;
 838         params->fb.stride = cache->fb.stride;
 839
 840         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 841
 842         if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
 843                 params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
 844                                                 32 * fbc->threshold) * 8;
 845 }
 846
 847 void intel_fbc_pre_update(struct intel_crtc *crtc,
 848                           struct intel_crtc_state *crtc_state,
 849                           struct intel_plane_state *plane_state)
 850 {
 851         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 852         struct intel_fbc *fbc = &dev_priv->fbc;
 853         const char *reason = "update pending";
 854
 855         if (!fbc_supported(dev_priv))
 856                 return;
 857
 858         mutex_lock(&fbc->lock);
 859
 860         if (!multiple_pipes_ok(crtc, plane_state)) {
 861                 reason = "more than one pipe active";
 862                 goto deactivate;
 863         }
 864
 865         if (!fbc->enabled || fbc->crtc != crtc)
 866                 goto unlock;
 867
 868         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 869         fbc->flip_pending = true;
 870
 871 deactivate:
 872         intel_fbc_deactivate(dev_priv, reason);
 873 unlock:
 874         mutex_unlock(&fbc->lock);
 875 }
 876
 877 /**
 878  * __intel_fbc_disable - disable FBC
 879  * @dev_priv: i915 device instance
 880  *
 881  * This is the low level function that actually disables FBC. Callers should
 882  * grab the FBC lock.
 883  */
 884 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
 885 {
 886         struct intel_fbc *fbc = &dev_priv->fbc;
 887         struct intel_crtc *crtc = fbc->crtc;
 888
 889         WARN_ON(!mutex_is_locked(&fbc->lock));
 890         WARN_ON(!fbc->enabled);
 891         WARN_ON(fbc->active);
 892
 893         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
 894
 895         __intel_fbc_cleanup_cfb(dev_priv);
 896
 897         fbc->enabled = false;
 898         fbc->crtc = NULL;
 899 }
 900
 901 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 902 {
 903         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 904         struct intel_fbc *fbc = &dev_priv->fbc;
 905
 906         WARN_ON(!mutex_is_locked(&fbc->lock));
 907
 908         if (!fbc->enabled || fbc->crtc != crtc)
 909                 return;
 910
 911         fbc->flip_pending = false;
 912         WARN_ON(fbc->active);
 913
 914         if (!i915_modparams.enable_fbc) {
 915                 intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
 916                 __intel_fbc_disable(dev_priv);
 917
 918                 return;
 919         }
 920
 921         intel_fbc_get_reg_params(crtc, &fbc->params);
 922
 923         if (!intel_fbc_can_activate(crtc))
 924                 return;
 925
 926         if (!fbc->busy_bits) {
 927                 intel_fbc_deactivate(dev_priv, "FBC enabled (active or scheduled)");
 928                 intel_fbc_hw_activate(dev_priv);
 929         } else
 930                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
 931 }
 932
 933 void intel_fbc_post_update(struct intel_crtc *crtc)
 934 {
 935         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 936         struct intel_fbc *fbc = &dev_priv->fbc;
 937
 938         if (!fbc_supported(dev_priv))
 939                 return;
 940
 941         mutex_lock(&fbc->lock);
 942         __intel_fbc_post_update(crtc);
 943         mutex_unlock(&fbc->lock);
 944 }
 945
 946 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
 947 {
 948         if (fbc->enabled)
 949                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
 950         else
 951                 return fbc->possible_framebuffer_bits;
 952 }
 953
 954 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
 955                           unsigned int frontbuffer_bits,
 956                           enum fb_op_origin origin)
 957 {
 958         struct intel_fbc *fbc = &dev_priv->fbc;
 959
 960         if (!fbc_supported(dev_priv))
 961                 return;
 962
 963         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 964                 return;
 965
 966         mutex_lock(&fbc->lock);
 967
 968         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
 969
 970         if (fbc->enabled && fbc->busy_bits)
 971                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
 972
 973         mutex_unlock(&fbc->lock);
 974 }
 975
 976 void intel_fbc_flush(struct drm_i915_private *dev_priv,
 977                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
 978 {
 979         struct intel_fbc *fbc = &dev_priv->fbc;
 980
 981         if (!fbc_supported(dev_priv))
 982                 return;
 983
 984         mutex_lock(&fbc->lock);
 985
 986         fbc->busy_bits &= ~frontbuffer_bits;
 987
 988         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 989                 goto out;
 990
 991         if (!fbc->busy_bits && fbc->enabled &&
 992             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
 993                 if (fbc->active)
 994                         intel_fbc_recompress(dev_priv);
 995                 else if (!fbc->flip_pending)
 996                         __intel_fbc_post_update(fbc->crtc);
 997         }
 998
 999 out:
1000         mutex_unlock(&fbc->lock);
1001 }
1002
1003 /**
1004  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1005  * @dev_priv: i915 device instance
1006  * @state: the atomic state structure
1007  *
1008  * This function looks at the proposed state for CRTCs and planes, then chooses
1009  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1010  * true.
1011  *
1012  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1013  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1014  */
1015 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1016                            struct intel_atomic_state *state)
1017 {
1018         struct intel_fbc *fbc = &dev_priv->fbc;
1019         struct intel_plane *plane;
1020         struct intel_plane_state *plane_state;
1021         bool crtc_chosen = false;
1022         int i;
1023
1024         mutex_lock(&fbc->lock);
1025
1026         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1027         if (fbc->crtc &&
1028             !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1029                 goto out;
1030
1031         if (!intel_fbc_can_enable(dev_priv))
1032                 goto out;
1033
1034         /* Simply choose the first CRTC that is compatible and has a visible
1035          * plane. We could go for fancier schemes such as checking the plane
1036          * size, but this would just affect the few platforms that don't tie FBC
1037          * to pipe or plane A. */
1038         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1039                 struct intel_crtc_state *crtc_state;
1040                 struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
1041
1042                 if (!plane->has_fbc)
1043                         continue;
1044
1045                 if (!plane_state->base.visible)
1046                         continue;
1047
1048                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1049
1050                 crtc_state->enable_fbc = true;
1051                 crtc_chosen = true;
1052                 break;
1053         }
1054
1055         if (!crtc_chosen)
1056                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1057
1058 out:
1059         mutex_unlock(&fbc->lock);
1060 }
1061
1062 /**
1063  * intel_fbc_enable: tries to enable FBC on the CRTC
1064  * @crtc: the CRTC
1065  * @crtc_state: corresponding &drm_crtc_state for @crtc
1066  * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1067  *
1068  * This function checks if the given CRTC was chosen for FBC, then enables it if
1069  * possible. Notice that it doesn't activate FBC. It is valid to call
1070  * intel_fbc_enable multiple times for the same pipe without an
1071  * intel_fbc_disable in the middle, as long as it is deactivated.
1072  */
1073 void intel_fbc_enable(struct intel_crtc *crtc,
1074                       struct intel_crtc_state *crtc_state,
1075                       struct intel_plane_state *plane_state)
1076 {
1077         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1078         struct intel_fbc *fbc = &dev_priv->fbc;
1079
1080         if (!fbc_supported(dev_priv))
1081                 return;
1082
1083         mutex_lock(&fbc->lock);
1084
1085         if (fbc->enabled) {
1086                 WARN_ON(fbc->crtc == NULL);
1087                 if (fbc->crtc == crtc) {
1088                         WARN_ON(!crtc_state->enable_fbc);
1089                         WARN_ON(fbc->active);
1090                 }
1091                 goto out;
1092         }
1093
1094         if (!crtc_state->enable_fbc)
1095                 goto out;
1096
1097         WARN_ON(fbc->active);
1098         WARN_ON(fbc->crtc != NULL);
1099
1100         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1101         if (intel_fbc_alloc_cfb(crtc)) {
1102                 fbc->no_fbc_reason = "not enough stolen memory";
1103                 goto out;
1104         }
1105
1106         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1107         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1108
1109         fbc->enabled = true;
1110         fbc->crtc = crtc;
1111 out:
1112         mutex_unlock(&fbc->lock);
1113 }
1114
1115 /**
1116  * intel_fbc_disable - disable FBC if it's associated with crtc
1117  * @crtc: the CRTC
1118  *
1119  * This function disables FBC if it's associated with the provided CRTC.
1120  */
1121 void intel_fbc_disable(struct intel_crtc *crtc)
1122 {
1123         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1124         struct intel_fbc *fbc = &dev_priv->fbc;
1125
1126         if (!fbc_supported(dev_priv))
1127                 return;
1128
1129         WARN_ON(crtc->active);
1130
1131         mutex_lock(&fbc->lock);
1132         if (fbc->crtc == crtc)
1133                 __intel_fbc_disable(dev_priv);
1134         mutex_unlock(&fbc->lock);
1135 }
1136
1137 /**
1138  * intel_fbc_global_disable - globally disable FBC
1139  * @dev_priv: i915 device instance
1140  *
1141  * This function disables FBC regardless of which CRTC is associated with it.
1142  */
1143 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1144 {
1145         struct intel_fbc *fbc = &dev_priv->fbc;
1146
1147         if (!fbc_supported(dev_priv))
1148                 return;
1149
1150         mutex_lock(&fbc->lock);
1151         if (fbc->enabled) {
1152                 WARN_ON(fbc->crtc->active);
1153                 __intel_fbc_disable(dev_priv);
1154         }
1155         mutex_unlock(&fbc->lock);
1156 }
1157
1158 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1159 {
1160         struct drm_i915_private *dev_priv =
1161                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1162         struct intel_fbc *fbc = &dev_priv->fbc;
1163
1164         mutex_lock(&fbc->lock);
1165
1166         /* Maybe we were scheduled twice. */
1167         if (fbc->underrun_detected || !fbc->enabled)
1168                 goto out;
1169
1170         DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1171         fbc->underrun_detected = true;
1172
1173         intel_fbc_deactivate(dev_priv, "FIFO underrun");
1174 out:
1175         mutex_unlock(&fbc->lock);
1176 }
1177
1178 /*
1179  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1180  * @dev_priv: i915 device instance
1181  *
1182  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1183  * want to re-enable FBC after an underrun to increase test coverage.
1184  */
1185 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1186 {
1187         int ret;
1188
1189         cancel_work_sync(&dev_priv->fbc.underrun_work);
1190
1191         ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1192         if (ret)
1193                 return ret;
1194
1195         if (dev_priv->fbc.underrun_detected) {
1196                 DRM_DEBUG_KMS("Re-allowing FBC after fifo underrun\n");
1197                 dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1198         }
1199
1200         dev_priv->fbc.underrun_detected = false;
1201         mutex_unlock(&dev_priv->fbc.lock);
1202
1203         return 0;
1204 }
1205
1206 /**
1207  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1208  * @dev_priv: i915 device instance
1209  *
1210  * Without FBC, most underruns are harmless and don't really cause too many
1211  * problems, except for an annoying message on dmesg. With FBC, underruns can
1212  * become black screens or even worse, especially when paired with bad
1213  * watermarks. So in order for us to be on the safe side, completely disable FBC
1214  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1215  * already suggests that watermarks may be bad, so try to be as safe as
1216  * possible.
1217  *
1218  * This function is called from the IRQ handler.
1219  */
1220 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1221 {
1222         struct intel_fbc *fbc = &dev_priv->fbc;
1223
1224         if (!fbc_supported(dev_priv))
1225                 return;
1226
1227         /* There's no guarantee that underrun_detected won't be set to true
1228          * right after this check and before the work is scheduled, but that's
1229          * not a problem since we'll check it again under the work function
1230          * while FBC is locked. This check here is just to prevent us from
1231          * unnecessarily scheduling the work, and it relies on the fact that we
1232          * never switch underrun_detect back to false after it's true. */
1233         if (READ_ONCE(fbc->underrun_detected))
1234                 return;
1235
1236         schedule_work(&fbc->underrun_work);
1237 }
1238
1239 /**
1240  * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1241  * @dev_priv: i915 device instance
1242  *
1243  * The FBC code needs to track CRTC visibility since the older platforms can't
1244  * have FBC enabled while multiple pipes are used. This function does the
1245  * initial setup at driver load to make sure FBC is matching the real hardware.
1246  */
1247 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1248 {
1249         struct intel_crtc *crtc;
1250
1251         /* Don't even bother tracking anything if we don't need. */
1252         if (!no_fbc_on_multiple_pipes(dev_priv))
1253                 return;
1254
1255         for_each_intel_crtc(&dev_priv->drm, crtc)
1256                 if (intel_crtc_active(crtc) &&
1257                     crtc->base.primary->state->visible)
1258                         dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1259 }
1260
1261 /*
1262  * The DDX driver changes its behavior depending on the value it reads from
1263  * i915.enable_fbc, so sanitize it by translating the default value into either
1264  * 0 or 1 in order to allow it to know what's going on.
1265  *
1266  * Notice that this is done at driver initialization and we still allow user
1267  * space to change the value during runtime without sanitizing it again. IGT
1268  * relies on being able to change i915.enable_fbc at runtime.
1269  */
1270 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1271 {
1272         if (i915_modparams.enable_fbc >= 0)
1273                 return !!i915_modparams.enable_fbc;
1274
1275         if (!HAS_FBC(dev_priv))
1276                 return 0;
1277
1278         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1279                 return 1;
1280
1281         return 0;
1282 }
1283
1284 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1285 {
1286         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1287         if (intel_vtd_active() &&
1288             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1289                 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1290                 return true;
1291         }
1292
1293         return false;
1294 }
1295
1296 /**
1297  * intel_fbc_init - Initialize FBC
1298  * @dev_priv: the i915 device
1299  *
1300  * This function might be called during PM init process.
1301  */
1302 void intel_fbc_init(struct drm_i915_private *dev_priv)
1303 {
1304         struct intel_fbc *fbc = &dev_priv->fbc;
1305
1306         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1307         mutex_init(&fbc->lock);
1308         fbc->enabled = false;
1309         fbc->active = false;
1310
1311         if (need_fbc_vtd_wa(dev_priv))
1312                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1313
1314         i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1315         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
1316                       i915_modparams.enable_fbc);
1317
1318         if (!HAS_FBC(dev_priv)) {
1319                 fbc->no_fbc_reason = "unsupported by this chipset";
1320                 return;
1321         }
1322
1323         /* This value was pulled out of someone's hat */
1324         if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
1325                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1326
1327         /* We still don't have any sort of hardware state readout for FBC, so
1328          * deactivate it in case the BIOS activated it to make sure software
1329          * matches the hardware state. */
1330         if (intel_fbc_hw_is_active(dev_priv))
1331                 intel_fbc_hw_deactivate(dev_priv);
1332 }