drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_mipi_dsi.h>
  32 #include <linux/slab.h>
  33 #include <linux/gpio/consumer.h>
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36 #include "intel_dsi.h"
  37
  38 /* return pixels in terms of txbyteclkhs */
  39 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  40                        u16 burst_mode_ratio)
  41 {
  42         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  43                                          8 * 100), lane_count);
  44 }
  45
  46 /* return pixels equvalent to txbyteclkhs */
  47 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  48                         u16 burst_mode_ratio)
  49 {
  50         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  51                                                 (bpp * burst_mode_ratio));
  52 }
  53
  54 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  55 {
  56         /* It just so happens the VBT matches register contents. */
  57         switch (fmt) {
  58         case VID_MODE_FORMAT_RGB888:
  59                 return MIPI_DSI_FMT_RGB888;
  60         case VID_MODE_FORMAT_RGB666:
  61                 return MIPI_DSI_FMT_RGB666;
  62         case VID_MODE_FORMAT_RGB666_PACKED:
  63                 return MIPI_DSI_FMT_RGB666_PACKED;
  64         case VID_MODE_FORMAT_RGB565:
  65                 return MIPI_DSI_FMT_RGB565;
  66         default:
  67                 MISSING_CASE(fmt);
  68                 return MIPI_DSI_FMT_RGB666;
  69         }
  70 }
  71
  72 void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  73 {
  74         struct drm_encoder *encoder = &intel_dsi->base.base;
  75         struct drm_device *dev = encoder->dev;
  76         struct drm_i915_private *dev_priv = to_i915(dev);
  77         u32 mask;
  78
  79         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  80                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  81
  82         if (intel_wait_for_register(dev_priv,
  83                                     MIPI_GEN_FIFO_STAT(port), mask, mask,
  84                                     100))
  85                 DRM_ERROR("DPI FIFOs are not empty\n");
  86 }
  87
  88 static void write_data(struct drm_i915_private *dev_priv,
  89                        i915_reg_t reg,
  90                        const u8 *data, u32 len)
  91 {
  92         u32 i, j;
  93
  94         for (i = 0; i < len; i += 4) {
  95                 u32 val = 0;
  96
  97                 for (j = 0; j < min_t(u32, len - i, 4); j++)
  98                         val |= *data++ << 8 * j;
  99
 100                 I915_WRITE(reg, val);
 101         }
 102 }
 103
 104 static void read_data(struct drm_i915_private *dev_priv,
 105                       i915_reg_t reg,
 106                       u8 *data, u32 len)
 107 {
 108         u32 i, j;
 109
 110         for (i = 0; i < len; i += 4) {
 111                 u32 val = I915_READ(reg);
 112
 113                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 114                         *data++ = val >> 8 * j;
 115         }
 116 }
 117
 118 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 119                                        const struct mipi_dsi_msg *msg)
 120 {
 121         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 122         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 123         struct drm_i915_private *dev_priv = to_i915(dev);
 124         enum port port = intel_dsi_host->port;
 125         struct mipi_dsi_packet packet;
 126         ssize_t ret;
 127         const u8 *header, *data;
 128         i915_reg_t data_reg, ctrl_reg;
 129         u32 data_mask, ctrl_mask;
 130
 131         ret = mipi_dsi_create_packet(&packet, msg);
 132         if (ret < 0)
 133                 return ret;
 134
 135         header = packet.header;
 136         data = packet.payload;
 137
 138         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 139                 data_reg = MIPI_LP_GEN_DATA(port);
 140                 data_mask = LP_DATA_FIFO_FULL;
 141                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 142                 ctrl_mask = LP_CTRL_FIFO_FULL;
 143         } else {
 144                 data_reg = MIPI_HS_GEN_DATA(port);
 145                 data_mask = HS_DATA_FIFO_FULL;
 146                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 147                 ctrl_mask = HS_CTRL_FIFO_FULL;
 148         }
 149
 150         /* note: this is never true for reads */
 151         if (packet.payload_length) {
 152                 if (intel_wait_for_register(dev_priv,
 153                                             MIPI_GEN_FIFO_STAT(port),
 154                                             data_mask, 0,
 155                                             50))
 156                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 157
 158                 write_data(dev_priv, data_reg, packet.payload,
 159                            packet.payload_length);
 160         }
 161
 162         if (msg->rx_len) {
 163                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 164         }
 165
 166         if (intel_wait_for_register(dev_priv,
 167                                     MIPI_GEN_FIFO_STAT(port),
 168                                     ctrl_mask, 0,
 169                                     50)) {
 170                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 171         }
 172
 173         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 174
 175         /* ->rx_len is set only for reads */
 176         if (msg->rx_len) {
 177                 data_mask = GEN_READ_DATA_AVAIL;
 178                 if (intel_wait_for_register(dev_priv,
 179                                             MIPI_INTR_STAT(port),
 180                                             data_mask, data_mask,
 181                                             50))
 182                         DRM_ERROR("Timeout waiting for read data.\n");
 183
 184                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 185         }
 186
 187         /* XXX: fix for reads and writes */
 188         return 4 + packet.payload_length;
 189 }
 190
 191 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 192                                  struct mipi_dsi_device *dsi)
 193 {
 194         return 0;
 195 }
 196
 197 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 198                                  struct mipi_dsi_device *dsi)
 199 {
 200         return 0;
 201 }
 202
 203 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 204         .attach = intel_dsi_host_attach,
 205         .detach = intel_dsi_host_detach,
 206         .transfer = intel_dsi_host_transfer,
 207 };
 208
 209 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
 210                                                   enum port port)
 211 {
 212         struct intel_dsi_host *host;
 213         struct mipi_dsi_device *device;
 214
 215         host = kzalloc(sizeof(*host), GFP_KERNEL);
 216         if (!host)
 217                 return NULL;
 218
 219         host->base.ops = &intel_dsi_host_ops;
 220         host->intel_dsi = intel_dsi;
 221         host->port = port;
 222
 223         /*
 224          * We should call mipi_dsi_host_register(&host->base) here, but we don't
 225          * have a host->dev, and we don't have OF stuff either. So just use the
 226          * dsi framework as a library and hope for the best. Create the dsi
 227          * devices by ourselves here too. Need to be careful though, because we
 228          * don't initialize any of the driver model devices here.
 229          */
 230         device = kzalloc(sizeof(*device), GFP_KERNEL);
 231         if (!device) {
 232                 kfree(host);
 233                 return NULL;
 234         }
 235
 236         device->host = &host->base;
 237         host->device = device;
 238
 239         return host;
 240 }
 241
 242 /*
 243  * send a video mode command
 244  *
 245  * XXX: commands with data in MIPI_DPI_DATA?
 246  */
 247 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 248                         enum port port)
 249 {
 250         struct drm_encoder *encoder = &intel_dsi->base.base;
 251         struct drm_device *dev = encoder->dev;
 252         struct drm_i915_private *dev_priv = to_i915(dev);
 253         u32 mask;
 254
 255         /* XXX: pipe, hs */
 256         if (hs)
 257                 cmd &= ~DPI_LP_MODE;
 258         else
 259                 cmd |= DPI_LP_MODE;
 260
 261         /* clear bit */
 262         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 263
 264         /* XXX: old code skips write if control unchanged */
 265         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 266                 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
 267
 268         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 269
 270         mask = SPL_PKT_SENT_INTERRUPT;
 271         if (intel_wait_for_register(dev_priv,
 272                                     MIPI_INTR_STAT(port), mask, mask,
 273                                     100))
 274                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 275
 276         return 0;
 277 }
 278
 279 static void band_gap_reset(struct drm_i915_private *dev_priv)
 280 {
 281         mutex_lock(&dev_priv->sb_lock);
 282
 283         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 284         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 285         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 286         udelay(150);
 287         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 288         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 289
 290         mutex_unlock(&dev_priv->sb_lock);
 291 }
 292
 293 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
 294 {
 295         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
 296 }
 297
 298 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
 299 {
 300         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
 301 }
 302
 303 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 304                                      struct intel_crtc_state *pipe_config,
 305                                      struct drm_connector_state *conn_state)
 306 {
 307         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 308         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 309                                                    base);
 310         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 311         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 312         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 313         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 314         int ret;
 315
 316         DRM_DEBUG_KMS("\n");
 317
 318         if (fixed_mode) {
 319                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 320
 321                 if (HAS_GMCH_DISPLAY(dev_priv))
 322                         intel_gmch_panel_fitting(crtc, pipe_config,
 323                                                  conn_state->scaling_mode);
 324                 else
 325                         intel_pch_panel_fitting(crtc, pipe_config,
 326                                                 conn_state->scaling_mode);
 327         }
 328
 329         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 330         adjusted_mode->flags = 0;
 331
 332         if (IS_GEN9_LP(dev_priv)) {
 333                 /* Dual link goes to DSI transcoder A. */
 334                 if (intel_dsi->ports == BIT(PORT_C))
 335                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 336                 else
 337                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 338         }
 339
 340         ret = intel_compute_dsi_pll(encoder, pipe_config);
 341         if (ret)
 342                 return false;
 343
 344         pipe_config->clock_set = true;
 345
 346         return true;
 347 }
 348
 349 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 350 {
 351         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 352         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 353         enum port port;
 354         u32 tmp;
 355         bool cold_boot = false;
 356
 357         /* Set the MIPI mode
 358          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 359          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 360          */
 361         for_each_dsi_port(port, intel_dsi->ports) {
 362                 tmp = I915_READ(MIPI_CTRL(port));
 363                 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
 364         }
 365
 366         /* Put the IO into reset */
 367         tmp = I915_READ(MIPI_CTRL(PORT_A));
 368         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 369         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 370
 371         /* Program LP Wake */
 372         for_each_dsi_port(port, intel_dsi->ports) {
 373                 tmp = I915_READ(MIPI_CTRL(port));
 374                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
 375                         tmp &= ~GLK_LP_WAKE;
 376                 else
 377                         tmp |= GLK_LP_WAKE;
 378                 I915_WRITE(MIPI_CTRL(port), tmp);
 379         }
 380
 381         /* Wait for Pwr ACK */
 382         for_each_dsi_port(port, intel_dsi->ports) {
 383                 if (intel_wait_for_register(dev_priv,
 384                                 MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
 385                                 GLK_MIPIIO_PORT_POWERED, 20))
 386                         DRM_ERROR("MIPIO port is powergated\n");
 387         }
 388
 389         /* Check for cold boot scenario */
 390         for_each_dsi_port(port, intel_dsi->ports) {
 391                 cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &
 392                                                         DEVICE_READY);
 393         }
 394
 395         return cold_boot;
 396 }
 397
 398 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 399 {
 400         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 401         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 402         enum port port;
 403         u32 val;
 404
 405         /* Wait for MIPI PHY status bit to set */
 406         for_each_dsi_port(port, intel_dsi->ports) {
 407                 if (intel_wait_for_register(dev_priv,
 408                                 MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
 409                                 GLK_PHY_STATUS_PORT_READY, 20))
 410                         DRM_ERROR("PHY is not ON\n");
 411         }
 412
 413         /* Get IO out of reset */
 414         val = I915_READ(MIPI_CTRL(PORT_A));
 415         I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
 416
 417         /* Get IO out of Low power state*/
 418         for_each_dsi_port(port, intel_dsi->ports) {
 419                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 420                         val = I915_READ(MIPI_DEVICE_READY(port));
 421                         val &= ~ULPS_STATE_MASK;
 422                         val |= DEVICE_READY;
 423                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 424                         usleep_range(10, 15);
 425                 } else {
 426                         /* Enter ULPS */
 427                         val = I915_READ(MIPI_DEVICE_READY(port));
 428                         val &= ~ULPS_STATE_MASK;
 429                         val |= (ULPS_STATE_ENTER | DEVICE_READY);
 430                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 431
 432                         /* Wait for ULPS active */
 433                         if (intel_wait_for_register(dev_priv,
 434                                 MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
 435                                 DRM_ERROR("ULPS not active\n");
 436
 437                         /* Exit ULPS */
 438                         val = I915_READ(MIPI_DEVICE_READY(port));
 439                         val &= ~ULPS_STATE_MASK;
 440                         val |= (ULPS_STATE_EXIT | DEVICE_READY);
 441                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 442
 443                         /* Enter Normal Mode */
 444                         val = I915_READ(MIPI_DEVICE_READY(port));
 445                         val &= ~ULPS_STATE_MASK;
 446                         val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 447                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 448
 449                         val = I915_READ(MIPI_CTRL(port));
 450                         val &= ~GLK_LP_WAKE;
 451                         I915_WRITE(MIPI_CTRL(port), val);
 452                 }
 453         }
 454
 455         /* Wait for Stop state */
 456         for_each_dsi_port(port, intel_dsi->ports) {
 457                 if (intel_wait_for_register(dev_priv,
 458                                 MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
 459                                 GLK_DATA_LANE_STOP_STATE, 20))
 460                         DRM_ERROR("Date lane not in STOP state\n");
 461         }
 462
 463         /* Wait for AFE LATCH */
 464         for_each_dsi_port(port, intel_dsi->ports) {
 465                 if (intel_wait_for_register(dev_priv,
 466                                 BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
 467                                 AFE_LATCHOUT, 20))
 468                         DRM_ERROR("D-PHY not entering LP-11 state\n");
 469         }
 470 }
 471
 472 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 473 {
 474         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 475         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 476         enum port port;
 477         u32 val;
 478
 479         DRM_DEBUG_KMS("\n");
 480
 481         /* Enable MIPI PHY transparent latch */
 482         for_each_dsi_port(port, intel_dsi->ports) {
 483                 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 484                 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 485                 usleep_range(2000, 2500);
 486         }
 487
 488         /* Clear ULPS and set device ready */
 489         for_each_dsi_port(port, intel_dsi->ports) {
 490                 val = I915_READ(MIPI_DEVICE_READY(port));
 491                 val &= ~ULPS_STATE_MASK;
 492                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 493                 usleep_range(2000, 2500);
 494                 val |= DEVICE_READY;
 495                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 496         }
 497 }
 498
 499 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 500 {
 501         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 502         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 503         enum port port;
 504         u32 val;
 505
 506         DRM_DEBUG_KMS("\n");
 507
 508         mutex_lock(&dev_priv->sb_lock);
 509         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 510          * needed everytime after power gate */
 511         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 512         mutex_unlock(&dev_priv->sb_lock);
 513
 514         /* bandgap reset is needed after everytime we do power gate */
 515         band_gap_reset(dev_priv);
 516
 517         for_each_dsi_port(port, intel_dsi->ports) {
 518
 519                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 520                 usleep_range(2500, 3000);
 521
 522                 /* Enable MIPI PHY transparent latch
 523                  * Common bit for both MIPI Port A & MIPI Port C
 524                  * No similar bit in MIPI Port C reg
 525                  */
 526                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 527                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 528                 usleep_range(1000, 1500);
 529
 530                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 531                 usleep_range(2500, 3000);
 532
 533                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 534                 usleep_range(2500, 3000);
 535         }
 536 }
 537
 538 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 539 {
 540         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 541
 542         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 543                 vlv_dsi_device_ready(encoder);
 544         else if (IS_BROXTON(dev_priv))
 545                 bxt_dsi_device_ready(encoder);
 546         else if (IS_GEMINILAKE(dev_priv))
 547                 glk_dsi_device_ready(encoder);
 548 }
 549
 550 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 551 {
 552         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 553         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 554         enum port port;
 555         u32 val;
 556
 557         /* Enter ULPS */
 558         for_each_dsi_port(port, intel_dsi->ports) {
 559                 val = I915_READ(MIPI_DEVICE_READY(port));
 560                 val &= ~ULPS_STATE_MASK;
 561                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 562                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 563         }
 564
 565         /* Wait for MIPI PHY status bit to unset */
 566         for_each_dsi_port(port, intel_dsi->ports) {
 567                 if (intel_wait_for_register(dev_priv,
 568                                             MIPI_CTRL(port),
 569                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 570                         DRM_ERROR("PHY is not turning OFF\n");
 571         }
 572
 573         /* Wait for Pwr ACK bit to unset */
 574         for_each_dsi_port(port, intel_dsi->ports) {
 575                 if (intel_wait_for_register(dev_priv,
 576                                             MIPI_CTRL(port),
 577                                             GLK_MIPIIO_PORT_POWERED, 0, 20))
 578                         DRM_ERROR("MIPI IO Port is not powergated\n");
 579         }
 580 }
 581
 582 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 583 {
 584         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 585         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 586         enum port port;
 587         u32 tmp;
 588
 589         /* Put the IO into reset */
 590         tmp = I915_READ(MIPI_CTRL(PORT_A));
 591         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 592         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 593
 594         /* Wait for MIPI PHY status bit to unset */
 595         for_each_dsi_port(port, intel_dsi->ports) {
 596                 if (intel_wait_for_register(dev_priv,
 597                                             MIPI_CTRL(port),
 598                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 599                         DRM_ERROR("PHY is not turning OFF\n");
 600         }
 601
 602         /* Clear MIPI mode */
 603         for_each_dsi_port(port, intel_dsi->ports) {
 604                 tmp = I915_READ(MIPI_CTRL(port));
 605                 tmp &= ~GLK_MIPIIO_ENABLE;
 606                 I915_WRITE(MIPI_CTRL(port), tmp);
 607         }
 608 }
 609
 610 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 611 {
 612         glk_dsi_enter_low_power_mode(encoder);
 613         glk_dsi_disable_mipi_io(encoder);
 614 }
 615
 616 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 617 {
 618         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 619         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 620         enum port port;
 621
 622         DRM_DEBUG_KMS("\n");
 623         for_each_dsi_port(port, intel_dsi->ports) {
 624                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 625                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 626                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 627                 u32 val;
 628
 629                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 630                                                         ULPS_STATE_ENTER);
 631                 usleep_range(2000, 2500);
 632
 633                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 634                                                         ULPS_STATE_EXIT);
 635                 usleep_range(2000, 2500);
 636
 637                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 638                                                         ULPS_STATE_ENTER);
 639                 usleep_range(2000, 2500);
 640
 641                 /*
 642                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 643                  * Port A only. MIPI Port C has no similar bit for checking.
 644                  */
 645                 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
 646                     intel_wait_for_register(dev_priv,
 647                                             port_ctrl, AFE_LATCHOUT, 0,
 648                                             30))
 649                         DRM_ERROR("DSI LP not going Low\n");
 650
 651                 /* Disable MIPI PHY transparent latch */
 652                 val = I915_READ(port_ctrl);
 653                 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 654                 usleep_range(1000, 1500);
 655
 656                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 657                 usleep_range(2000, 2500);
 658         }
 659 }
 660
 661 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 662 {
 663         struct drm_device *dev = encoder->base.dev;
 664         struct drm_i915_private *dev_priv = to_i915(dev);
 665         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 666         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 667         enum port port;
 668
 669         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 670                 u32 temp;
 671                 if (IS_GEN9_LP(dev_priv)) {
 672                         for_each_dsi_port(port, intel_dsi->ports) {
 673                                 temp = I915_READ(MIPI_CTRL(port));
 674                                 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 675                                         intel_dsi->pixel_overlap <<
 676                                         BXT_PIXEL_OVERLAP_CNT_SHIFT;
 677                                 I915_WRITE(MIPI_CTRL(port), temp);
 678                         }
 679                 } else {
 680                         temp = I915_READ(VLV_CHICKEN_3);
 681                         temp &= ~PIXEL_OVERLAP_CNT_MASK |
 682                                         intel_dsi->pixel_overlap <<
 683                                         PIXEL_OVERLAP_CNT_SHIFT;
 684                         I915_WRITE(VLV_CHICKEN_3, temp);
 685                 }
 686         }
 687
 688         for_each_dsi_port(port, intel_dsi->ports) {
 689                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 690                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 691                 u32 temp;
 692
 693                 temp = I915_READ(port_ctrl);
 694
 695                 temp &= ~LANE_CONFIGURATION_MASK;
 696                 temp &= ~DUAL_LINK_MODE_MASK;
 697
 698                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 699                         temp |= (intel_dsi->dual_link - 1)
 700                                                 << DUAL_LINK_MODE_SHIFT;
 701                         if (IS_BROXTON(dev_priv))
 702                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 703                         else
 704                                 temp |= intel_crtc->pipe ?
 705                                         LANE_CONFIGURATION_DUAL_LINK_B :
 706                                         LANE_CONFIGURATION_DUAL_LINK_A;
 707                 }
 708                 /* assert ip_tg_enable signal */
 709                 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 710                 POSTING_READ(port_ctrl);
 711         }
 712 }
 713
 714 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 715 {
 716         struct drm_device *dev = encoder->base.dev;
 717         struct drm_i915_private *dev_priv = to_i915(dev);
 718         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 719         enum port port;
 720
 721         for_each_dsi_port(port, intel_dsi->ports) {
 722                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 723                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 724                 u32 temp;
 725
 726                 /* de-assert ip_tg_enable signal */
 727                 temp = I915_READ(port_ctrl);
 728                 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 729                 POSTING_READ(port_ctrl);
 730         }
 731 }
 732
 733 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 734                               struct intel_crtc_state *pipe_config);
 735 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 736
 737 static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
 738 {
 739         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 740
 741         /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
 742         if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
 743                 return;
 744
 745         msleep(msec);
 746 }
 747
 748 /*
 749  * Panel enable/disable sequences from the VBT spec.
 750  *
 751  * Note the spec has AssertReset / DeassertReset swapped from their
 752  * usual naming. We use the normal names to avoid confusion (so below
 753  * they are swapped compared to the spec).
 754  *
 755  * Steps starting with MIPI refer to VBT sequences, note that for v2
 756  * VBTs several steps which have a VBT in v2 are expected to be handled
 757  * directly by the driver, by directly driving gpios for example.
 758  *
 759  * v2 video mode seq         v3 video mode seq         command mode seq
 760  * - power on                - MIPIPanelPowerOn        - power on
 761  * - wait t1+t2                                        - wait t1+t2
 762  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 763  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 764  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 765  *                                                     - MIPITearOn
 766  *                                                     - MIPIDisplayOn
 767  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 768  * - MIPIDisplayOn           - MIPIDisplayOn
 769  * - wait t5                                           - wait t5
 770  * - backlight on            - MIPIBacklightOn         - backlight on
 771  * ...                       ...                       ... issue mem cmds ...
 772  * - backlight off           - MIPIBacklightOff        - backlight off
 773  * - wait t6                                           - wait t6
 774  * - MIPIDisplayOff
 775  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 776  *                                                     - MIPITearOff
 777  *                           - MIPIDisplayOff          - MIPIDisplayOff
 778  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 779  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 780  * - wait t3                                           - wait t3
 781  * - power off               - MIPIPanelPowerOff       - power off
 782  * - wait t4                                           - wait t4
 783  */
 784
 785 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 786                                  struct intel_crtc_state *pipe_config,
 787                                  struct drm_connector_state *conn_state)
 788 {
 789         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 790         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 791         enum port port;
 792         u32 val;
 793         bool glk_cold_boot = false;
 794
 795         DRM_DEBUG_KMS("\n");
 796
 797         /*
 798          * The BIOS may leave the PLL in a wonky state where it doesn't
 799          * lock. It needs to be fully powered down to fix it.
 800          */
 801         intel_disable_dsi_pll(encoder);
 802         intel_enable_dsi_pll(encoder, pipe_config);
 803
 804         if (IS_BROXTON(dev_priv)) {
 805                 /* Add MIPI IO reset programming for modeset */
 806                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 807                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 808                                         val | MIPIO_RST_CTRL);
 809
 810                 /* Power up DSI regulator */
 811                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 812                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 813         }
 814
 815         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 816                 u32 val;
 817
 818                 /* Disable DPOunit clock gating, can stall pipe */
 819                 val = I915_READ(DSPCLK_GATE_D);
 820                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 821                 I915_WRITE(DSPCLK_GATE_D, val);
 822         }
 823
 824         if (!IS_GEMINILAKE(dev_priv))
 825                 intel_dsi_prepare(encoder, pipe_config);
 826
 827         /* Power on, try both CRC pmic gpio and VBT */
 828         if (intel_dsi->gpio_panel)
 829                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 830         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 831         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 832
 833         /* Deassert reset */
 834         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 835
 836         if (IS_GEMINILAKE(dev_priv)) {
 837                 glk_cold_boot = glk_dsi_enable_io(encoder);
 838
 839                 /* Prepare port in cold boot(s3/s4) scenario */
 840                 if (glk_cold_boot)
 841                         intel_dsi_prepare(encoder, pipe_config);
 842         }
 843
 844         /* Put device in ready state (LP-11) */
 845         intel_dsi_device_ready(encoder);
 846
 847         /* Prepare port in normal boot scenario */
 848         if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
 849                 intel_dsi_prepare(encoder, pipe_config);
 850
 851         /* Send initialization commands in LP mode */
 852         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 853
 854         /* Enable port in pre-enable phase itself because as per hw team
 855          * recommendation, port should be enabled befor plane & pipe */
 856         if (is_cmd_mode(intel_dsi)) {
 857                 for_each_dsi_port(port, intel_dsi->ports)
 858                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 859                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 860                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 861         } else {
 862                 msleep(20); /* XXX */
 863                 for_each_dsi_port(port, intel_dsi->ports)
 864                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 865                 intel_dsi_msleep(intel_dsi, 100);
 866
 867                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 868
 869                 intel_dsi_port_enable(encoder);
 870         }
 871
 872         intel_panel_enable_backlight(pipe_config, conn_state);
 873         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 874 }
 875
 876 /*
 877  * DSI port enable has to be done before pipe and plane enable, so we do it in
 878  * the pre_enable hook.
 879  */
 880 static void intel_dsi_enable_nop(struct intel_encoder *encoder,
 881                                  struct intel_crtc_state *pipe_config,
 882                                  struct drm_connector_state *conn_state)
 883 {
 884         DRM_DEBUG_KMS("\n");
 885 }
 886
 887 /*
 888  * DSI port disable has to be done after pipe and plane disable, so we do it in
 889  * the post_disable hook.
 890  */
 891 static void intel_dsi_disable(struct intel_encoder *encoder,
 892                               struct intel_crtc_state *old_crtc_state,
 893                               struct drm_connector_state *old_conn_state)
 894 {
 895         struct drm_device *dev = encoder->base.dev;
 896         struct drm_i915_private *dev_priv = dev->dev_private;
 897         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 898         enum port port;
 899
 900         DRM_DEBUG_KMS("\n");
 901
 902         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 903         intel_panel_disable_backlight(old_conn_state);
 904
 905         /*
 906          * Disable Device ready before the port shutdown in order
 907          * to avoid split screen
 908          */
 909         if (IS_BROXTON(dev_priv)) {
 910                 for_each_dsi_port(port, intel_dsi->ports)
 911                         I915_WRITE(MIPI_DEVICE_READY(port), 0);
 912         }
 913
 914         /*
 915          * According to the spec we should send SHUTDOWN before
 916          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 917          * has shown that the v3 sequence works for v2 VBTs too
 918          */
 919         if (is_vid_mode(intel_dsi)) {
 920                 /* Send Shutdown command to the panel in LP mode */
 921                 for_each_dsi_port(port, intel_dsi->ports)
 922                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 923                 msleep(10);
 924         }
 925 }
 926
 927 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 928 {
 929         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 930
 931         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
 932             IS_BROXTON(dev_priv))
 933                 vlv_dsi_clear_device_ready(encoder);
 934         else if (IS_GEMINILAKE(dev_priv))
 935                 glk_dsi_clear_device_ready(encoder);
 936 }
 937
 938 static void intel_dsi_post_disable(struct intel_encoder *encoder,
 939                                    struct intel_crtc_state *pipe_config,
 940                                    struct drm_connector_state *conn_state)
 941 {
 942         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 943         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 944         enum port port;
 945         u32 val;
 946
 947         DRM_DEBUG_KMS("\n");
 948
 949         if (is_vid_mode(intel_dsi)) {
 950                 for_each_dsi_port(port, intel_dsi->ports)
 951                         wait_for_dsi_fifo_empty(intel_dsi, port);
 952
 953                 intel_dsi_port_disable(encoder);
 954                 usleep_range(2000, 5000);
 955         }
 956
 957         intel_dsi_unprepare(encoder);
 958
 959         /*
 960          * if disable packets are sent before sending shutdown packet then in
 961          * some next enable sequence send turn on packet error is observed
 962          */
 963         if (is_cmd_mode(intel_dsi))
 964                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 965         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 966
 967         /* Transition to LP-00 */
 968         intel_dsi_clear_device_ready(encoder);
 969
 970         if (IS_BROXTON(dev_priv)) {
 971                 /* Power down DSI regulator to save power */
 972                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 973                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
 974
 975                 /* Add MIPI IO reset programming for modeset */
 976                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 977                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 978                                 val & ~MIPIO_RST_CTRL);
 979         }
 980
 981         intel_disable_dsi_pll(encoder);
 982
 983         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 984                 u32 val;
 985
 986                 val = I915_READ(DSPCLK_GATE_D);
 987                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 988                 I915_WRITE(DSPCLK_GATE_D, val);
 989         }
 990
 991         /* Assert reset */
 992         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 993
 994         /* Power off, try both CRC pmic gpio and VBT */
 995         intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
 996         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 997         if (intel_dsi->gpio_panel)
 998                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 999
1000         /*
1001          * FIXME As we do with eDP, just make a note of the time here
1002          * and perform the wait before the next panel power on.
1003          */
1004         intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
1005 }
1006
1007 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
1008                                    enum pipe *pipe)
1009 {
1010         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1011         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1012         enum port port;
1013         bool active = false;
1014
1015         DRM_DEBUG_KMS("\n");
1016
1017         if (!intel_display_power_get_if_enabled(dev_priv,
1018                                                 encoder->power_domain))
1019                 return false;
1020
1021         /*
1022          * On Broxton the PLL needs to be enabled with a valid divider
1023          * configuration, otherwise accessing DSI registers will hang the
1024          * machine. See BSpec North Display Engine registers/MIPI[BXT].
1025          */
1026         if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
1027                 goto out_put_power;
1028
1029         /* XXX: this only works for one DSI output */
1030         for_each_dsi_port(port, intel_dsi->ports) {
1031                 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
1032                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
1033                 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
1034
1035                 /*
1036                  * Due to some hardware limitations on VLV/CHV, the DPI enable
1037                  * bit in port C control register does not get set. As a
1038                  * workaround, check pipe B conf instead.
1039                  */
1040                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1041                     port == PORT_C)
1042                         enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1043
1044                 /* Try command mode if video mode not enabled */
1045                 if (!enabled) {
1046                         u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
1047                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1048                 }
1049
1050                 if (!enabled)
1051                         continue;
1052
1053                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
1054                         continue;
1055
1056                 if (IS_GEN9_LP(dev_priv)) {
1057                         u32 tmp = I915_READ(MIPI_CTRL(port));
1058                         tmp &= BXT_PIPE_SELECT_MASK;
1059                         tmp >>= BXT_PIPE_SELECT_SHIFT;
1060
1061                         if (WARN_ON(tmp > PIPE_C))
1062                                 continue;
1063
1064                         *pipe = tmp;
1065                 } else {
1066                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1067                 }
1068
1069                 active = true;
1070                 break;
1071         }
1072
1073 out_put_power:
1074         intel_display_power_put(dev_priv, encoder->power_domain);
1075
1076         return active;
1077 }
1078
1079 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1080                                  struct intel_crtc_state *pipe_config)
1081 {
1082         struct drm_device *dev = encoder->base.dev;
1083         struct drm_i915_private *dev_priv = to_i915(dev);
1084         struct drm_display_mode *adjusted_mode =
1085                                         &pipe_config->base.adjusted_mode;
1086         struct drm_display_mode *adjusted_mode_sw;
1087         struct intel_crtc *intel_crtc;
1088         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1089         unsigned int lane_count = intel_dsi->lane_count;
1090         unsigned int bpp, fmt;
1091         enum port port;
1092         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1093         u16 hfp_sw, hsync_sw, hbp_sw;
1094         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1095                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1096
1097         /* FIXME: hw readout should not depend on SW state */
1098         intel_crtc = to_intel_crtc(encoder->base.crtc);
1099         adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode;
1100
1101         /*
1102          * Atleast one port is active as encoder->get_config called only if
1103          * encoder->get_hw_state() returns true.
1104          */
1105         for_each_dsi_port(port, intel_dsi->ports) {
1106                 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1107                         break;
1108         }
1109
1110         fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1111         pipe_config->pipe_bpp =
1112                         mipi_dsi_pixel_format_to_bpp(
1113                                 pixel_format_from_register_bits(fmt));
1114         bpp = pipe_config->pipe_bpp;
1115
1116         /* In terms of pixels */
1117         adjusted_mode->crtc_hdisplay =
1118                                 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
1119         adjusted_mode->crtc_vdisplay =
1120                                 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
1121         adjusted_mode->crtc_vtotal =
1122                                 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
1123
1124         hactive = adjusted_mode->crtc_hdisplay;
1125         hfp = I915_READ(MIPI_HFP_COUNT(port));
1126
1127         /*
1128          * Meaningful for video mode non-burst sync pulse mode only,
1129          * can be zero for non-burst sync events and burst modes
1130          */
1131         hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
1132         hbp = I915_READ(MIPI_HBP_COUNT(port));
1133
1134         /* harizontal values are in terms of high speed byte clock */
1135         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1136                                                 intel_dsi->burst_mode_ratio);
1137         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1138                                                 intel_dsi->burst_mode_ratio);
1139         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1140                                                 intel_dsi->burst_mode_ratio);
1141
1142         if (intel_dsi->dual_link) {
1143                 hfp *= 2;
1144                 hsync *= 2;
1145                 hbp *= 2;
1146         }
1147
1148         /* vertical values are in terms of lines */
1149         vfp = I915_READ(MIPI_VFP_COUNT(port));
1150         vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
1151         vbp = I915_READ(MIPI_VBP_COUNT(port));
1152
1153         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1154         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1155         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1156         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1157         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1158
1159         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1160         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1161         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1162         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1163
1164         /*
1165          * In BXT DSI there is no regs programmed with few horizontal timings
1166          * in Pixels but txbyteclkhs.. So retrieval process adds some
1167          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1168          * Actually here for the given adjusted_mode, we are calculating the
1169          * value programmed to the port and then back to the horizontal timing
1170          * param in pixels. This is the expected value, including roundup errors
1171          * And if that is same as retrieved value from port, then
1172          * (HW state) adjusted_mode's horizontal timings are corrected to
1173          * match with SW state to nullify the errors.
1174          */
1175         /* Calculating the value programmed to the Port register */
1176         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1177                                         adjusted_mode_sw->crtc_hdisplay;
1178         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1179                                         adjusted_mode_sw->crtc_hsync_start;
1180         hbp_sw = adjusted_mode_sw->crtc_htotal -
1181                                         adjusted_mode_sw->crtc_hsync_end;
1182
1183         if (intel_dsi->dual_link) {
1184                 hfp_sw /= 2;
1185                 hsync_sw /= 2;
1186                 hbp_sw /= 2;
1187         }
1188
1189         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1190                                                 intel_dsi->burst_mode_ratio);
1191         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1192                             intel_dsi->burst_mode_ratio);
1193         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1194                                                 intel_dsi->burst_mode_ratio);
1195
1196         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1197         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1198                                                 intel_dsi->burst_mode_ratio);
1199         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1200                                                 intel_dsi->burst_mode_ratio);
1201         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1202                                                 intel_dsi->burst_mode_ratio);
1203
1204         if (intel_dsi->dual_link) {
1205                 hfp_sw *= 2;
1206                 hsync_sw *= 2;
1207                 hbp_sw *= 2;
1208         }
1209
1210         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1211                                                         hsync_sw + hbp_sw;
1212         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1213         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1214         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1215         crtc_hblank_end_sw = crtc_htotal_sw;
1216
1217         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1218                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1219
1220         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1221                 adjusted_mode->crtc_hsync_start =
1222                                         adjusted_mode_sw->crtc_hsync_start;
1223
1224         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1225                 adjusted_mode->crtc_hsync_end =
1226                                         adjusted_mode_sw->crtc_hsync_end;
1227
1228         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1229                 adjusted_mode->crtc_hblank_start =
1230                                         adjusted_mode_sw->crtc_hblank_start;
1231
1232         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1233                 adjusted_mode->crtc_hblank_end =
1234                                         adjusted_mode_sw->crtc_hblank_end;
1235 }
1236
1237 static void intel_dsi_get_config(struct intel_encoder *encoder,
1238                                  struct intel_crtc_state *pipe_config)
1239 {
1240         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1241         u32 pclk;
1242         DRM_DEBUG_KMS("\n");
1243
1244         if (IS_GEN9_LP(dev_priv))
1245                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1246
1247         pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
1248                                   pipe_config);
1249         if (!pclk)
1250                 return;
1251
1252         pipe_config->base.adjusted_mode.crtc_clock = pclk;
1253         pipe_config->port_clock = pclk;
1254 }
1255
1256 static enum drm_mode_status
1257 intel_dsi_mode_valid(struct drm_connector *connector,
1258                      struct drm_display_mode *mode)
1259 {
1260         struct intel_connector *intel_connector = to_intel_connector(connector);
1261         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
1262         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1263
1264         DRM_DEBUG_KMS("\n");
1265
1266         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
1267                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
1268                 return MODE_NO_DBLESCAN;
1269         }
1270
1271         if (fixed_mode) {
1272                 if (mode->hdisplay > fixed_mode->hdisplay)
1273                         return MODE_PANEL;
1274                 if (mode->vdisplay > fixed_mode->vdisplay)
1275                         return MODE_PANEL;
1276                 if (fixed_mode->clock > max_dotclk)
1277                         return MODE_CLOCK_HIGH;
1278         }
1279
1280         return MODE_OK;
1281 }
1282
1283 /* return txclkesc cycles in terms of divider and duration in us */
1284 static u16 txclkesc(u32 divider, unsigned int us)
1285 {
1286         switch (divider) {
1287         case ESCAPE_CLOCK_DIVIDER_1:
1288         default:
1289                 return 20 * us;
1290         case ESCAPE_CLOCK_DIVIDER_2:
1291                 return 10 * us;
1292         case ESCAPE_CLOCK_DIVIDER_4:
1293                 return 5 * us;
1294         }
1295 }
1296
1297 static void set_dsi_timings(struct drm_encoder *encoder,
1298                             const struct drm_display_mode *adjusted_mode)
1299 {
1300         struct drm_device *dev = encoder->dev;
1301         struct drm_i915_private *dev_priv = to_i915(dev);
1302         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1303         enum port port;
1304         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1305         unsigned int lane_count = intel_dsi->lane_count;
1306
1307         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1308
1309         hactive = adjusted_mode->crtc_hdisplay;
1310         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1311         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1312         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1313
1314         if (intel_dsi->dual_link) {
1315                 hactive /= 2;
1316                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1317                         hactive += intel_dsi->pixel_overlap;
1318                 hfp /= 2;
1319                 hsync /= 2;
1320                 hbp /= 2;
1321         }
1322
1323         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1324         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1325         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1326
1327         /* horizontal values are in terms of high speed byte clock */
1328         hactive = txbyteclkhs(hactive, bpp, lane_count,
1329                               intel_dsi->burst_mode_ratio);
1330         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1331         hsync = txbyteclkhs(hsync, bpp, lane_count,
1332                             intel_dsi->burst_mode_ratio);
1333         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1334
1335         for_each_dsi_port(port, intel_dsi->ports) {
1336                 if (IS_GEN9_LP(dev_priv)) {
1337                         /*
1338                          * Program hdisplay and vdisplay on MIPI transcoder.
1339                          * This is different from calculated hactive and
1340                          * vactive, as they are calculated per channel basis,
1341                          * whereas these values should be based on resolution.
1342                          */
1343                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1344                                    adjusted_mode->crtc_hdisplay);
1345                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1346                                    adjusted_mode->crtc_vdisplay);
1347                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1348                                    adjusted_mode->crtc_vtotal);
1349                 }
1350
1351                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1352                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1353
1354                 /* meaningful for video mode non-burst sync pulse mode only,
1355                  * can be zero for non-burst sync events and burst modes */
1356                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1357                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1358
1359                 /* vertical values are in terms of lines */
1360                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1361                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1362                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1363         }
1364 }
1365
1366 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1367 {
1368         switch (fmt) {
1369         case MIPI_DSI_FMT_RGB888:
1370                 return VID_MODE_FORMAT_RGB888;
1371         case MIPI_DSI_FMT_RGB666:
1372                 return VID_MODE_FORMAT_RGB666;
1373         case MIPI_DSI_FMT_RGB666_PACKED:
1374                 return VID_MODE_FORMAT_RGB666_PACKED;
1375         case MIPI_DSI_FMT_RGB565:
1376                 return VID_MODE_FORMAT_RGB565;
1377         default:
1378                 MISSING_CASE(fmt);
1379                 return VID_MODE_FORMAT_RGB666;
1380         }
1381 }
1382
1383 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1384                               struct intel_crtc_state *pipe_config)
1385 {
1386         struct drm_encoder *encoder = &intel_encoder->base;
1387         struct drm_device *dev = encoder->dev;
1388         struct drm_i915_private *dev_priv = to_i915(dev);
1389         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1390         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1391         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1392         enum port port;
1393         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1394         u32 val, tmp;
1395         u16 mode_hdisplay;
1396
1397         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1398
1399         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1400
1401         if (intel_dsi->dual_link) {
1402                 mode_hdisplay /= 2;
1403                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1404                         mode_hdisplay += intel_dsi->pixel_overlap;
1405         }
1406
1407         for_each_dsi_port(port, intel_dsi->ports) {
1408                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1409                         /*
1410                          * escape clock divider, 20MHz, shared for A and C.
1411                          * device ready must be off when doing this! txclkesc?
1412                          */
1413                         tmp = I915_READ(MIPI_CTRL(PORT_A));
1414                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1415                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1416                                         ESCAPE_CLOCK_DIVIDER_1);
1417
1418                         /* read request priority is per pipe */
1419                         tmp = I915_READ(MIPI_CTRL(port));
1420                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1421                         I915_WRITE(MIPI_CTRL(port), tmp |
1422                                         READ_REQUEST_PRIORITY_HIGH);
1423                 } else if (IS_GEN9_LP(dev_priv)) {
1424                         enum pipe pipe = intel_crtc->pipe;
1425
1426                         tmp = I915_READ(MIPI_CTRL(port));
1427                         tmp &= ~BXT_PIPE_SELECT_MASK;
1428
1429                         tmp |= BXT_PIPE_SELECT(pipe);
1430                         I915_WRITE(MIPI_CTRL(port), tmp);
1431                 }
1432
1433                 /* XXX: why here, why like this? handling in irq handler?! */
1434                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1435                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1436
1437                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1438
1439                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1440                         adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1441                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1442         }
1443
1444         set_dsi_timings(encoder, adjusted_mode);
1445
1446         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1447         if (is_cmd_mode(intel_dsi)) {
1448                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1449                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1450         } else {
1451                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1452                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1453         }
1454
1455         tmp = 0;
1456         if (intel_dsi->eotp_pkt == 0)
1457                 tmp |= EOT_DISABLE;
1458         if (intel_dsi->clock_stop)
1459                 tmp |= CLOCKSTOP;
1460
1461         if (IS_GEN9_LP(dev_priv)) {
1462                 tmp |= BXT_DPHY_DEFEATURE_EN;
1463                 if (!is_cmd_mode(intel_dsi))
1464                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1465         }
1466
1467         for_each_dsi_port(port, intel_dsi->ports) {
1468                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1469
1470                 /* timeouts for recovery. one frame IIUC. if counter expires,
1471                  * EOT and stop state. */
1472
1473                 /*
1474                  * In burst mode, value greater than one DPI line Time in byte
1475                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1476                  * said value is recommended.
1477                  *
1478                  * In non-burst mode, Value greater than one DPI frame time in
1479                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1480                  * said value is recommended.
1481                  *
1482                  * In DBI only mode, value greater than one DBI frame time in
1483                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1484                  * said value is recommended.
1485                  */
1486
1487                 if (is_vid_mode(intel_dsi) &&
1488                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1489                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1490                                 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1491                                             intel_dsi->lane_count,
1492                                             intel_dsi->burst_mode_ratio) + 1);
1493                 } else {
1494                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1495                                 txbyteclkhs(adjusted_mode->crtc_vtotal *
1496                                             adjusted_mode->crtc_htotal,
1497                                             bpp, intel_dsi->lane_count,
1498                                             intel_dsi->burst_mode_ratio) + 1);
1499                 }
1500                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1501                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1502                                                 intel_dsi->turn_arnd_val);
1503                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1504                                                 intel_dsi->rst_timer_val);
1505
1506                 /* dphy stuff */
1507
1508                 /* in terms of low power clock */
1509                 I915_WRITE(MIPI_INIT_COUNT(port),
1510                                 txclkesc(intel_dsi->escape_clk_div, 100));
1511
1512                 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1513                         /*
1514                          * BXT spec says write MIPI_INIT_COUNT for
1515                          * both the ports, even if only one is
1516                          * getting used. So write the other port
1517                          * if not in dual link mode.
1518                          */
1519                         I915_WRITE(MIPI_INIT_COUNT(port ==
1520                                                 PORT_A ? PORT_C : PORT_A),
1521                                         intel_dsi->init_count);
1522                 }
1523
1524                 /* recovery disables */
1525                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1526
1527                 /* in terms of low power clock */
1528                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1529
1530                 /* in terms of txbyteclkhs. actual high to low switch +
1531                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1532                  *
1533                  * XXX: write MIPI_STOP_STATE_STALL?
1534                  */
1535                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1536                                                 intel_dsi->hs_to_lp_count);
1537
1538                 /* XXX: low power clock equivalence in terms of byte clock.
1539                  * the number of byte clocks occupied in one low power clock.
1540                  * based on txbyteclkhs and txclkesc.
1541                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1542                  * ) / 105.???
1543                  */
1544                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1545
1546                 if (IS_GEMINILAKE(dev_priv)) {
1547                         I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1548                                         intel_dsi->lp_byte_clk);
1549                         /* Shadow of DPHY reg */
1550                         I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1551                                         intel_dsi->dphy_reg);
1552                 }
1553
1554                 /* the bw essential for transmitting 16 long packets containing
1555                  * 252 bytes meant for dcs write memory command is programmed in
1556                  * this register in terms of byte clocks. based on dsi transfer
1557                  * rate and the number of lanes configured the time taken to
1558                  * transmit 16 long packets in a dsi stream varies. */
1559                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1560
1561                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1562                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1563                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1564
1565                 if (is_vid_mode(intel_dsi))
1566                         /* Some panels might have resolution which is not a
1567                          * multiple of 64 like 1366 x 768. Enable RANDOM
1568                          * resolution support for such panels by default */
1569                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1570                                 intel_dsi->video_frmt_cfg_bits |
1571                                 intel_dsi->video_mode_format |
1572                                 IP_TG_CONFIG |
1573                                 RANDOM_DPI_DISPLAY_RESOLUTION);
1574         }
1575 }
1576
1577 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1578 {
1579         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1580         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1581         enum port port;
1582         u32 val;
1583
1584         if (!IS_GEMINILAKE(dev_priv)) {
1585                 for_each_dsi_port(port, intel_dsi->ports) {
1586                         /* Panel commands can be sent when clock is in LP11 */
1587                         I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1588
1589                         intel_dsi_reset_clocks(encoder, port);
1590                         I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1591
1592                         val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1593                         val &= ~VID_MODE_FORMAT_MASK;
1594                         I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1595
1596                         I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1597                 }
1598         }
1599 }
1600
1601 static int intel_dsi_get_modes(struct drm_connector *connector)
1602 {
1603         struct intel_connector *intel_connector = to_intel_connector(connector);
1604         struct drm_display_mode *mode;
1605
1606         DRM_DEBUG_KMS("\n");
1607
1608         if (!intel_connector->panel.fixed_mode) {
1609                 DRM_DEBUG_KMS("no fixed mode\n");
1610                 return 0;
1611         }
1612
1613         mode = drm_mode_duplicate(connector->dev,
1614                                   intel_connector->panel.fixed_mode);
1615         if (!mode) {
1616                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1617                 return 0;
1618         }
1619
1620         drm_mode_probed_add(connector, mode);
1621         return 1;
1622 }
1623
1624 static void intel_dsi_connector_destroy(struct drm_connector *connector)
1625 {
1626         struct intel_connector *intel_connector = to_intel_connector(connector);
1627
1628         DRM_DEBUG_KMS("\n");
1629         intel_panel_fini(&intel_connector->panel);
1630         drm_connector_cleanup(connector);
1631         kfree(connector);
1632 }
1633
1634 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1635 {
1636         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1637
1638         /* dispose of the gpios */
1639         if (intel_dsi->gpio_panel)
1640                 gpiod_put(intel_dsi->gpio_panel);
1641
1642         intel_encoder_destroy(encoder);
1643 }
1644
1645 static const struct drm_encoder_funcs intel_dsi_funcs = {
1646         .destroy = intel_dsi_encoder_destroy,
1647 };
1648
1649 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1650         .get_modes = intel_dsi_get_modes,
1651         .mode_valid = intel_dsi_mode_valid,
1652         .atomic_check = intel_digital_connector_atomic_check,
1653 };
1654
1655 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1656         .late_register = intel_connector_register,
1657         .early_unregister = intel_connector_unregister,
1658         .destroy = intel_dsi_connector_destroy,
1659         .fill_modes = drm_helper_probe_single_connector_modes,
1660         .atomic_get_property = intel_digital_connector_atomic_get_property,
1661         .atomic_set_property = intel_digital_connector_atomic_set_property,
1662         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1663         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1664 };
1665
1666 static void intel_dsi_add_properties(struct intel_connector *connector)
1667 {
1668         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1669
1670         if (connector->panel.fixed_mode) {
1671                 u32 allowed_scalers;
1672
1673                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1674                 if (!HAS_GMCH_DISPLAY(dev_priv))
1675                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1676
1677                 drm_connector_attach_scaling_mode_property(&connector->base,
1678                                                                 allowed_scalers);
1679
1680                 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1681         }
1682 }
1683
1684 void intel_dsi_init(struct drm_i915_private *dev_priv)
1685 {
1686         struct drm_device *dev = &dev_priv->drm;
1687         struct intel_dsi *intel_dsi;
1688         struct intel_encoder *intel_encoder;
1689         struct drm_encoder *encoder;
1690         struct intel_connector *intel_connector;
1691         struct drm_connector *connector;
1692         struct drm_display_mode *scan, *fixed_mode = NULL;
1693         enum port port;
1694
1695         DRM_DEBUG_KMS("\n");
1696
1697         /* There is no detection method for MIPI so rely on VBT */
1698         if (!intel_bios_is_dsi_present(dev_priv, &port))
1699                 return;
1700
1701         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1702                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1703         } else if (IS_GEN9_LP(dev_priv)) {
1704                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1705         } else {
1706                 DRM_ERROR("Unsupported Mipi device to reg base");
1707                 return;
1708         }
1709
1710         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1711         if (!intel_dsi)
1712                 return;
1713
1714         intel_connector = intel_connector_alloc();
1715         if (!intel_connector) {
1716                 kfree(intel_dsi);
1717                 return;
1718         }
1719
1720         intel_encoder = &intel_dsi->base;
1721         encoder = &intel_encoder->base;
1722         intel_dsi->attached_connector = intel_connector;
1723
1724         connector = &intel_connector->base;
1725
1726         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1727                          "DSI %c", port_name(port));
1728
1729         intel_encoder->compute_config = intel_dsi_compute_config;
1730         intel_encoder->pre_enable = intel_dsi_pre_enable;
1731         intel_encoder->enable = intel_dsi_enable_nop;
1732         intel_encoder->disable = intel_dsi_disable;
1733         intel_encoder->post_disable = intel_dsi_post_disable;
1734         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1735         intel_encoder->get_config = intel_dsi_get_config;
1736
1737         intel_connector->get_hw_state = intel_connector_get_hw_state;
1738
1739         intel_encoder->port = port;
1740
1741         /*
1742          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1743          * port C. BXT isn't limited like this.
1744          */
1745         if (IS_GEN9_LP(dev_priv))
1746                 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1747         else if (port == PORT_A)
1748                 intel_encoder->crtc_mask = BIT(PIPE_A);
1749         else
1750                 intel_encoder->crtc_mask = BIT(PIPE_B);
1751
1752         if (dev_priv->vbt.dsi.config->dual_link) {
1753                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1754
1755                 switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
1756                 case DL_DCS_PORT_A:
1757                         intel_dsi->dcs_backlight_ports = BIT(PORT_A);
1758                         break;
1759                 case DL_DCS_PORT_C:
1760                         intel_dsi->dcs_backlight_ports = BIT(PORT_C);
1761                         break;
1762                 default:
1763                 case DL_DCS_PORT_A_AND_C:
1764                         intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C);
1765                         break;
1766                 }
1767
1768                 switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
1769                 case DL_DCS_PORT_A:
1770                         intel_dsi->dcs_cabc_ports = BIT(PORT_A);
1771                         break;
1772                 case DL_DCS_PORT_C:
1773                         intel_dsi->dcs_cabc_ports = BIT(PORT_C);
1774                         break;
1775                 default:
1776                 case DL_DCS_PORT_A_AND_C:
1777                         intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C);
1778                         break;
1779                 }
1780         } else {
1781                 intel_dsi->ports = BIT(port);
1782                 intel_dsi->dcs_backlight_ports = BIT(port);
1783                 intel_dsi->dcs_cabc_ports = BIT(port);
1784         }
1785
1786         if (!dev_priv->vbt.dsi.config->cabc_supported)
1787                 intel_dsi->dcs_cabc_ports = 0;
1788
1789         /* Create a DSI host (and a device) for each port. */
1790         for_each_dsi_port(port, intel_dsi->ports) {
1791                 struct intel_dsi_host *host;
1792
1793                 host = intel_dsi_host_init(intel_dsi, port);
1794                 if (!host)
1795                         goto err;
1796
1797                 intel_dsi->dsi_hosts[port] = host;
1798         }
1799
1800         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1801                 DRM_DEBUG_KMS("no device found\n");
1802                 goto err;
1803         }
1804
1805         /*
1806          * In case of BYT with CRC PMIC, we need to use GPIO for
1807          * Panel control.
1808          */
1809         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1810             (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
1811                 intel_dsi->gpio_panel =
1812                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1813
1814                 if (IS_ERR(intel_dsi->gpio_panel)) {
1815                         DRM_ERROR("Failed to own gpio for panel control\n");
1816                         intel_dsi->gpio_panel = NULL;
1817                 }
1818         }
1819
1820         intel_encoder->type = INTEL_OUTPUT_DSI;
1821         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1822         intel_encoder->cloneable = 0;
1823         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1824                            DRM_MODE_CONNECTOR_DSI);
1825
1826         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1827
1828         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1829         connector->interlace_allowed = false;
1830         connector->doublescan_allowed = false;
1831
1832         intel_connector_attach_encoder(intel_connector, intel_encoder);
1833
1834         mutex_lock(&dev->mode_config.mutex);
1835         intel_dsi_vbt_get_modes(intel_dsi);
1836         list_for_each_entry(scan, &connector->probed_modes, head) {
1837                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1838                         fixed_mode = drm_mode_duplicate(dev, scan);
1839                         break;
1840                 }
1841         }
1842         mutex_unlock(&dev->mode_config.mutex);
1843
1844         if (!fixed_mode) {
1845                 DRM_DEBUG_KMS("no fixed mode\n");
1846                 goto err;
1847         }
1848
1849         connector->display_info.width_mm = fixed_mode->width_mm;
1850         connector->display_info.height_mm = fixed_mode->height_mm;
1851
1852         intel_panel_init(&intel_connector->panel, fixed_mode, NULL, NULL);
1853         intel_panel_setup_backlight(connector, INVALID_PIPE);
1854
1855         intel_dsi_add_properties(intel_connector);
1856
1857         return;
1858
1859 err:
1860         drm_encoder_cleanup(&intel_encoder->base);
1861         kfree(intel_dsi);
1862         kfree(intel_connector);
1863 }