drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * __wait_for - magic wait macro
  45  *
  46  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  47  * important that we check the condition again after having timed out, since the
  48  * timeout could be due to preemption or similar and we've never had a chance to
  49  * check the condition before the timeout.
  50  */
  51 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  52         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  53         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  54         int ret__;                                                      \
  55         might_sleep();                                                  \
  56         for (;;) {                                                      \
  57                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  58                 OP;                                                     \
  59                 /* Guarantee COND check prior to timeout */             \
  60                 barrier();                                              \
  61                 if (COND) {                                             \
  62                         ret__ = 0;                                      \
  63                         break;                                          \
  64                 }                                                       \
  65                 if (expired__) {                                        \
  66                         ret__ = -ETIMEDOUT;                             \
  67                         break;                                          \
  68                 }                                                       \
  69                 usleep_range(wait__, wait__ * 2);                       \
  70                 if (wait__ < (Wmax))                                    \
  71                         wait__ <<= 1;                                   \
  72         }                                                               \
  73         ret__;                                                          \
  74 })
  75
  76 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  77                                                    (Wmax))
  78 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  79
  80 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  81 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  82 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  83 #else
  84 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  85 #endif
  86
  87 #define _wait_for_atomic(COND, US, ATOMIC) \
  88 ({ \
  89         int cpu, ret, timeout = (US) * 1000; \
  90         u64 base; \
  91         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  92         if (!(ATOMIC)) { \
  93                 preempt_disable(); \
  94                 cpu = smp_processor_id(); \
  95         } \
  96         base = local_clock(); \
  97         for (;;) { \
  98                 u64 now = local_clock(); \
  99                 if (!(ATOMIC)) \
 100                         preempt_enable(); \
 101                 /* Guarantee COND check prior to timeout */ \
 102                 barrier(); \
 103                 if (COND) { \
 104                         ret = 0; \
 105                         break; \
 106                 } \
 107                 if (now - base >= timeout) { \
 108                         ret = -ETIMEDOUT; \
 109                         break; \
 110                 } \
 111                 cpu_relax(); \
 112                 if (!(ATOMIC)) { \
 113                         preempt_disable(); \
 114                         if (unlikely(cpu != smp_processor_id())) { \
 115                                 timeout -= now - base; \
 116                                 cpu = smp_processor_id(); \
 117                                 base = local_clock(); \
 118                         } \
 119                 } \
 120         } \
 121         ret; \
 122 })
 123
 124 #define wait_for_us(COND, US) \
 125 ({ \
 126         int ret__; \
 127         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 128         if ((US) > 10) \
 129                 ret__ = _wait_for((COND), (US), 10, 10); \
 130         else \
 131                 ret__ = _wait_for_atomic((COND), (US), 0); \
 132         ret__; \
 133 })
 134
 135 #define wait_for_atomic_us(COND, US) \
 136 ({ \
 137         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 138         BUILD_BUG_ON((US) > 50000); \
 139         _wait_for_atomic((COND), (US), 1); \
 140 })
 141
 142 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 143
 144 #define KHz(x) (1000 * (x))
 145 #define MHz(x) KHz(1000 * (x))
 146
 147 #define KBps(x) (1000 * (x))
 148 #define MBps(x) KBps(1000 * (x))
 149 #define GBps(x) ((u64)1000 * MBps((x)))
 150
 151 /*
 152  * Display related stuff
 153  */
 154
 155 /* store information about an Ixxx DVO */
 156 /* The i830->i865 use multiple DVOs with multiple i2cs */
 157 /* the i915, i945 have a single sDVO i2c bus - which is different */
 158 #define MAX_OUTPUTS 6
 159 /* maximum connectors per crtcs in the mode set */
 160
 161 /* Maximum cursor sizes */
 162 #define GEN2_CURSOR_WIDTH 64
 163 #define GEN2_CURSOR_HEIGHT 64
 164 #define MAX_CURSOR_WIDTH 256
 165 #define MAX_CURSOR_HEIGHT 256
 166
 167 #define INTEL_I2C_BUS_DVO 1
 168 #define INTEL_I2C_BUS_SDVO 2
 169
 170 /* these are outputs from the chip - integrated only
 171    external chips are via DVO or SDVO output */
 172 enum intel_output_type {
 173         INTEL_OUTPUT_UNUSED = 0,
 174         INTEL_OUTPUT_ANALOG = 1,
 175         INTEL_OUTPUT_DVO = 2,
 176         INTEL_OUTPUT_SDVO = 3,
 177         INTEL_OUTPUT_LVDS = 4,
 178         INTEL_OUTPUT_TVOUT = 5,
 179         INTEL_OUTPUT_HDMI = 6,
 180         INTEL_OUTPUT_DP = 7,
 181         INTEL_OUTPUT_EDP = 8,
 182         INTEL_OUTPUT_DSI = 9,
 183         INTEL_OUTPUT_DDI = 10,
 184         INTEL_OUTPUT_DP_MST = 11,
 185 };
 186
 187 #define INTEL_DVO_CHIP_NONE 0
 188 #define INTEL_DVO_CHIP_LVDS 1
 189 #define INTEL_DVO_CHIP_TMDS 2
 190 #define INTEL_DVO_CHIP_TVOUT 4
 191
 192 #define INTEL_DSI_VIDEO_MODE    0
 193 #define INTEL_DSI_COMMAND_MODE  1
 194
 195 struct intel_framebuffer {
 196         struct drm_framebuffer base;
 197         struct drm_i915_gem_object *obj;
 198         struct intel_rotation_info rot_info;
 199
 200         /* for each plane in the normal GTT view */
 201         struct {
 202                 unsigned int x, y;
 203         } normal[2];
 204         /* for each plane in the rotated GTT view */
 205         struct {
 206                 unsigned int x, y;
 207                 unsigned int pitch; /* pixels */
 208         } rotated[2];
 209 };
 210
 211 struct intel_fbdev {
 212         struct drm_fb_helper helper;
 213         struct intel_framebuffer *fb;
 214         struct i915_vma *vma;
 215         unsigned long vma_flags;
 216         async_cookie_t cookie;
 217         int preferred_bpp;
 218 };
 219
 220 struct intel_encoder {
 221         struct drm_encoder base;
 222
 223         enum intel_output_type type;
 224         enum port port;
 225         unsigned int cloneable;
 226         bool (*hotplug)(struct intel_encoder *encoder,
 227                         struct intel_connector *connector);
 228         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 229                                                       struct intel_crtc_state *,
 230                                                       struct drm_connector_state *);
 231         bool (*compute_config)(struct intel_encoder *,
 232                                struct intel_crtc_state *,
 233                                struct drm_connector_state *);
 234         void (*pre_pll_enable)(struct intel_encoder *,
 235                                const struct intel_crtc_state *,
 236                                const struct drm_connector_state *);
 237         void (*pre_enable)(struct intel_encoder *,
 238                            const struct intel_crtc_state *,
 239                            const struct drm_connector_state *);
 240         void (*enable)(struct intel_encoder *,
 241                        const struct intel_crtc_state *,
 242                        const struct drm_connector_state *);
 243         void (*disable)(struct intel_encoder *,
 244                         const struct intel_crtc_state *,
 245                         const struct drm_connector_state *);
 246         void (*post_disable)(struct intel_encoder *,
 247                              const struct intel_crtc_state *,
 248                              const struct drm_connector_state *);
 249         void (*post_pll_disable)(struct intel_encoder *,
 250                                  const struct intel_crtc_state *,
 251                                  const struct drm_connector_state *);
 252         /* Read out the current hw state of this connector, returning true if
 253          * the encoder is active. If the encoder is enabled it also set the pipe
 254          * it is connected to in the pipe parameter. */
 255         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 256         /* Reconstructs the equivalent mode flags for the current hardware
 257          * state. This must be called _after_ display->get_pipe_config has
 258          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 259          * be set correctly before calling this function. */
 260         void (*get_config)(struct intel_encoder *,
 261                            struct intel_crtc_state *pipe_config);
 262         /* Returns a mask of power domains that need to be referenced as part
 263          * of the hardware state readout code. */
 264         u64 (*get_power_domains)(struct intel_encoder *encoder);
 265         /*
 266          * Called during system suspend after all pending requests for the
 267          * encoder are flushed (for example for DP AUX transactions) and
 268          * device interrupts are disabled.
 269          */
 270         void (*suspend)(struct intel_encoder *);
 271         int crtc_mask;
 272         enum hpd_pin hpd_pin;
 273         enum intel_display_power_domain power_domain;
 274         /* for communication with audio component; protected by av_mutex */
 275         const struct drm_connector *audio_connector;
 276 };
 277
 278 struct intel_panel {
 279         struct drm_display_mode *fixed_mode;
 280         struct drm_display_mode *alt_fixed_mode;
 281         struct drm_display_mode *downclock_mode;
 282
 283         /* backlight */
 284         struct {
 285                 bool present;
 286                 u32 level;
 287                 u32 min;
 288                 u32 max;
 289                 bool enabled;
 290                 bool combination_mode;  /* gen 2/4 only */
 291                 bool active_low_pwm;
 292                 bool alternate_pwm_increment;   /* lpt+ */
 293
 294                 /* PWM chip */
 295                 bool util_pin_active_low;       /* bxt+ */
 296                 u8 controller;          /* bxt+ only */
 297                 struct pwm_device *pwm;
 298
 299                 struct backlight_device *device;
 300
 301                 /* Connector and platform specific backlight functions */
 302                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 303                 uint32_t (*get)(struct intel_connector *connector);
 304                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 305                 void (*disable)(const struct drm_connector_state *conn_state);
 306                 void (*enable)(const struct intel_crtc_state *crtc_state,
 307                                const struct drm_connector_state *conn_state);
 308                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 309                                       uint32_t hz);
 310                 void (*power)(struct intel_connector *, bool enable);
 311         } backlight;
 312 };
 313
 314 /*
 315  * This structure serves as a translation layer between the generic HDCP code
 316  * and the bus-specific code. What that means is that HDCP over HDMI differs
 317  * from HDCP over DP, so to account for these differences, we need to
 318  * communicate with the receiver through this shim.
 319  *
 320  * For completeness, the 2 buses differ in the following ways:
 321  *      - DP AUX vs. DDC
 322  *              HDCP registers on the receiver are set via DP AUX for DP, and
 323  *              they are set via DDC for HDMI.
 324  *      - Receiver register offsets
 325  *              The offsets of the registers are different for DP vs. HDMI
 326  *      - Receiver register masks/offsets
 327  *              For instance, the ready bit for the KSV fifo is in a different
 328  *              place on DP vs HDMI
 329  *      - Receiver register names
 330  *              Seriously. In the DP spec, the 16-bit register containing
 331  *              downstream information is called BINFO, on HDMI it's called
 332  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 333  *              with a completely different definition.
 334  *      - KSV FIFO
 335  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 336  *              be read 3 keys at a time
 337  *      - Aksv output
 338  *              Since Aksv is hidden in hardware, there's different procedures
 339  *              to send it over DP AUX vs DDC
 340  */
 341 struct intel_hdcp_shim {
 342         /* Outputs the transmitter's An and Aksv values to the receiver. */
 343         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 344
 345         /* Reads the receiver's key selection vector */
 346         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 347
 348         /*
 349          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 350          * definitions are the same in the respective specs, but the names are
 351          * different. Call it BSTATUS since that's the name the HDMI spec
 352          * uses and it was there first.
 353          */
 354         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 355                             u8 *bstatus);
 356
 357         /* Determines whether a repeater is present downstream */
 358         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 359                                 bool *repeater_present);
 360
 361         /* Reads the receiver's Ri' value */
 362         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 363
 364         /* Determines if the receiver's KSV FIFO is ready for consumption */
 365         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 366                               bool *ksv_ready);
 367
 368         /* Reads the ksv fifo for num_downstream devices */
 369         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 370                              int num_downstream, u8 *ksv_fifo);
 371
 372         /* Reads a 32-bit part of V' from the receiver */
 373         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 374                                  int i, u32 *part);
 375
 376         /* Enables HDCP signalling on the port */
 377         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 378                                  bool enable);
 379
 380         /* Ensures the link is still protected */
 381         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 382
 383         /* Detects panel's hdcp capability. This is optional for HDMI. */
 384         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 385                             bool *hdcp_capable);
 386 };
 387
 388 struct intel_connector {
 389         struct drm_connector base;
 390         /*
 391          * The fixed encoder this connector is connected to.
 392          */
 393         struct intel_encoder *encoder;
 394
 395         /* ACPI device id for ACPI and driver cooperation */
 396         u32 acpi_device_id;
 397
 398         /* Reads out the current hw, returning true if the connector is enabled
 399          * and active (i.e. dpms ON state). */
 400         bool (*get_hw_state)(struct intel_connector *);
 401
 402         /* Panel info for eDP and LVDS */
 403         struct intel_panel panel;
 404
 405         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 406         struct edid *edid;
 407         struct edid *detect_edid;
 408
 409         /* since POLL and HPD connectors may use the same HPD line keep the native
 410            state of connector->polled in case hotplug storm detection changes it */
 411         u8 polled;
 412
 413         void *port; /* store this opaque as its illegal to dereference it */
 414
 415         struct intel_dp *mst_port;
 416
 417         /* Work struct to schedule a uevent on link train failure */
 418         struct work_struct modeset_retry_work;
 419
 420         const struct intel_hdcp_shim *hdcp_shim;
 421         struct mutex hdcp_mutex;
 422         uint64_t hdcp_value; /* protected by hdcp_mutex */
 423         struct delayed_work hdcp_check_work;
 424         struct work_struct hdcp_prop_work;
 425 };
 426
 427 struct intel_digital_connector_state {
 428         struct drm_connector_state base;
 429
 430         enum hdmi_force_audio force_audio;
 431         int broadcast_rgb;
 432 };
 433
 434 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 435
 436 struct dpll {
 437         /* given values */
 438         int n;
 439         int m1, m2;
 440         int p1, p2;
 441         /* derived values */
 442         int     dot;
 443         int     vco;
 444         int     m;
 445         int     p;
 446 };
 447
 448 struct intel_atomic_state {
 449         struct drm_atomic_state base;
 450
 451         struct {
 452                 /*
 453                  * Logical state of cdclk (used for all scaling, watermark,
 454                  * etc. calculations and checks). This is computed as if all
 455                  * enabled crtcs were active.
 456                  */
 457                 struct intel_cdclk_state logical;
 458
 459                 /*
 460                  * Actual state of cdclk, can be different from the logical
 461                  * state only when all crtc's are DPMS off.
 462                  */
 463                 struct intel_cdclk_state actual;
 464         } cdclk;
 465
 466         bool dpll_set, modeset;
 467
 468         /*
 469          * Does this transaction change the pipes that are active?  This mask
 470          * tracks which CRTC's have changed their active state at the end of
 471          * the transaction (not counting the temporary disable during modesets).
 472          * This mask should only be non-zero when intel_state->modeset is true,
 473          * but the converse is not necessarily true; simply changing a mode may
 474          * not flip the final active status of any CRTC's
 475          */
 476         unsigned int active_pipe_changes;
 477
 478         unsigned int active_crtcs;
 479         /* minimum acceptable cdclk for each pipe */
 480         int min_cdclk[I915_MAX_PIPES];
 481         /* minimum acceptable voltage level for each pipe */
 482         u8 min_voltage_level[I915_MAX_PIPES];
 483
 484         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 485
 486         /*
 487          * Current watermarks can't be trusted during hardware readout, so
 488          * don't bother calculating intermediate watermarks.
 489          */
 490         bool skip_intermediate_wm;
 491
 492         /* Gen9+ only */
 493         struct skl_ddb_values wm_results;
 494
 495         struct i915_sw_fence commit_ready;
 496
 497         struct llist_node freed;
 498 };
 499
 500 struct intel_plane_state {
 501         struct drm_plane_state base;
 502         struct i915_vma *vma;
 503         unsigned long flags;
 504 #define PLANE_HAS_FENCE BIT(0)
 505
 506         struct {
 507                 u32 offset;
 508                 int x, y;
 509         } main;
 510         struct {
 511                 u32 offset;
 512                 int x, y;
 513         } aux;
 514
 515         /* plane control register */
 516         u32 ctl;
 517
 518         /* plane color control register */
 519         u32 color_ctl;
 520
 521         /*
 522          * scaler_id
 523          *    = -1 : not using a scaler
 524          *    >=  0 : using a scalers
 525          *
 526          * plane requiring a scaler:
 527          *   - During check_plane, its bit is set in
 528          *     crtc_state->scaler_state.scaler_users by calling helper function
 529          *     update_scaler_plane.
 530          *   - scaler_id indicates the scaler it got assigned.
 531          *
 532          * plane doesn't require a scaler:
 533          *   - this can happen when scaling is no more required or plane simply
 534          *     got disabled.
 535          *   - During check_plane, corresponding bit is reset in
 536          *     crtc_state->scaler_state.scaler_users by calling helper function
 537          *     update_scaler_plane.
 538          */
 539         int scaler_id;
 540
 541         struct drm_intel_sprite_colorkey ckey;
 542 };
 543
 544 struct intel_initial_plane_config {
 545         struct intel_framebuffer *fb;
 546         unsigned int tiling;
 547         int size;
 548         u32 base;
 549 };
 550
 551 #define SKL_MIN_SRC_W 8
 552 #define SKL_MAX_SRC_W 4096
 553 #define SKL_MIN_SRC_H 8
 554 #define SKL_MAX_SRC_H 4096
 555 #define SKL_MIN_DST_W 8
 556 #define SKL_MAX_DST_W 4096
 557 #define SKL_MIN_DST_H 8
 558 #define SKL_MAX_DST_H 4096
 559 #define ICL_MAX_SRC_W 5120
 560 #define ICL_MAX_SRC_H 4096
 561 #define ICL_MAX_DST_W 5120
 562 #define ICL_MAX_DST_H 4096
 563 #define SKL_MIN_YUV_420_SRC_W 16
 564 #define SKL_MIN_YUV_420_SRC_H 16
 565
 566 struct intel_scaler {
 567         int in_use;
 568         uint32_t mode;
 569 };
 570
 571 struct intel_crtc_scaler_state {
 572 #define SKL_NUM_SCALERS 2
 573         struct intel_scaler scalers[SKL_NUM_SCALERS];
 574
 575         /*
 576          * scaler_users: keeps track of users requesting scalers on this crtc.
 577          *
 578          *     If a bit is set, a user is using a scaler.
 579          *     Here user can be a plane or crtc as defined below:
 580          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 581          *       bit 31    - crtc
 582          *
 583          * Instead of creating a new index to cover planes and crtc, using
 584          * existing drm_plane_index for planes which is well less than 31
 585          * planes and bit 31 for crtc. This should be fine to cover all
 586          * our platforms.
 587          *
 588          * intel_atomic_setup_scalers will setup available scalers to users
 589          * requesting scalers. It will gracefully fail if request exceeds
 590          * avilability.
 591          */
 592 #define SKL_CRTC_INDEX 31
 593         unsigned scaler_users;
 594
 595         /* scaler used by crtc for panel fitting purpose */
 596         int scaler_id;
 597 };
 598
 599 /* drm_mode->private_flags */
 600 #define I915_MODE_FLAG_INHERITED 1
 601 /* Flag to get scanline using frame time stamps */
 602 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 603
 604 struct intel_pipe_wm {
 605         struct intel_wm_level wm[5];
 606         uint32_t linetime;
 607         bool fbc_wm_enabled;
 608         bool pipe_enabled;
 609         bool sprites_enabled;
 610         bool sprites_scaled;
 611 };
 612
 613 struct skl_plane_wm {
 614         struct skl_wm_level wm[8];
 615         struct skl_wm_level uv_wm[8];
 616         struct skl_wm_level trans_wm;
 617         bool is_planar;
 618 };
 619
 620 struct skl_pipe_wm {
 621         struct skl_plane_wm planes[I915_MAX_PLANES];
 622         uint32_t linetime;
 623 };
 624
 625 enum vlv_wm_level {
 626         VLV_WM_LEVEL_PM2,
 627         VLV_WM_LEVEL_PM5,
 628         VLV_WM_LEVEL_DDR_DVFS,
 629         NUM_VLV_WM_LEVELS,
 630 };
 631
 632 struct vlv_wm_state {
 633         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 634         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 635         uint8_t num_levels;
 636         bool cxsr;
 637 };
 638
 639 struct vlv_fifo_state {
 640         u16 plane[I915_MAX_PLANES];
 641 };
 642
 643 enum g4x_wm_level {
 644         G4X_WM_LEVEL_NORMAL,
 645         G4X_WM_LEVEL_SR,
 646         G4X_WM_LEVEL_HPLL,
 647         NUM_G4X_WM_LEVELS,
 648 };
 649
 650 struct g4x_wm_state {
 651         struct g4x_pipe_wm wm;
 652         struct g4x_sr_wm sr;
 653         struct g4x_sr_wm hpll;
 654         bool cxsr;
 655         bool hpll_en;
 656         bool fbc_en;
 657 };
 658
 659 struct intel_crtc_wm_state {
 660         union {
 661                 struct {
 662                         /*
 663                          * Intermediate watermarks; these can be
 664                          * programmed immediately since they satisfy
 665                          * both the current configuration we're
 666                          * switching away from and the new
 667                          * configuration we're switching to.
 668                          */
 669                         struct intel_pipe_wm intermediate;
 670
 671                         /*
 672                          * Optimal watermarks, programmed post-vblank
 673                          * when this state is committed.
 674                          */
 675                         struct intel_pipe_wm optimal;
 676                 } ilk;
 677
 678                 struct {
 679                         /* gen9+ only needs 1-step wm programming */
 680                         struct skl_pipe_wm optimal;
 681                         struct skl_ddb_entry ddb;
 682                 } skl;
 683
 684                 struct {
 685                         /* "raw" watermarks (not inverted) */
 686                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 687                         /* intermediate watermarks (inverted) */
 688                         struct vlv_wm_state intermediate;
 689                         /* optimal watermarks (inverted) */
 690                         struct vlv_wm_state optimal;
 691                         /* display FIFO split */
 692                         struct vlv_fifo_state fifo_state;
 693                 } vlv;
 694
 695                 struct {
 696                         /* "raw" watermarks */
 697                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 698                         /* intermediate watermarks */
 699                         struct g4x_wm_state intermediate;
 700                         /* optimal watermarks */
 701                         struct g4x_wm_state optimal;
 702                 } g4x;
 703         };
 704
 705         /*
 706          * Platforms with two-step watermark programming will need to
 707          * update watermark programming post-vblank to switch from the
 708          * safe intermediate watermarks to the optimal final
 709          * watermarks.
 710          */
 711         bool need_postvbl_update;
 712 };
 713
 714 struct intel_crtc_state {
 715         struct drm_crtc_state base;
 716
 717         /**
 718          * quirks - bitfield with hw state readout quirks
 719          *
 720          * For various reasons the hw state readout code might not be able to
 721          * completely faithfully read out the current state. These cases are
 722          * tracked with quirk flags so that fastboot and state checker can act
 723          * accordingly.
 724          */
 725 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 726         unsigned long quirks;
 727
 728         unsigned fb_bits; /* framebuffers to flip */
 729         bool update_pipe; /* can a fast modeset be performed? */
 730         bool disable_cxsr;
 731         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 732         bool fb_changed; /* fb on any of the planes is changed */
 733         bool fifo_changed; /* FIFO split is changed */
 734
 735         /* Pipe source size (ie. panel fitter input size)
 736          * All planes will be positioned inside this space,
 737          * and get clipped at the edges. */
 738         int pipe_src_w, pipe_src_h;
 739
 740         /*
 741          * Pipe pixel rate, adjusted for
 742          * panel fitter/pipe scaler downscaling.
 743          */
 744         unsigned int pixel_rate;
 745
 746         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 747          * between pch encoders and cpu encoders. */
 748         bool has_pch_encoder;
 749
 750         /* Are we sending infoframes on the attached port */
 751         bool has_infoframe;
 752
 753         /* CPU Transcoder for the pipe. Currently this can only differ from the
 754          * pipe on Haswell and later (where we have a special eDP transcoder)
 755          * and Broxton (where we have special DSI transcoders). */
 756         enum transcoder cpu_transcoder;
 757
 758         /*
 759          * Use reduced/limited/broadcast rbg range, compressing from the full
 760          * range fed into the crtcs.
 761          */
 762         bool limited_color_range;
 763
 764         /* Bitmask of encoder types (enum intel_output_type)
 765          * driven by the pipe.
 766          */
 767         unsigned int output_types;
 768
 769         /* Whether we should send NULL infoframes. Required for audio. */
 770         bool has_hdmi_sink;
 771
 772         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 773          * has_dp_encoder is set. */
 774         bool has_audio;
 775
 776         /*
 777          * Enable dithering, used when the selected pipe bpp doesn't match the
 778          * plane bpp.
 779          */
 780         bool dither;
 781
 782         /*
 783          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 784          * compliance video pattern tests.
 785          * Disable dither only if it is a compliance test request for
 786          * 18bpp.
 787          */
 788         bool dither_force_disable;
 789
 790         /* Controls for the clock computation, to override various stages. */
 791         bool clock_set;
 792
 793         /* SDVO TV has a bunch of special case. To make multifunction encoders
 794          * work correctly, we need to track this at runtime.*/
 795         bool sdvo_tv_clock;
 796
 797         /*
 798          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 799          * required. This is set in the 2nd loop of calling encoder's
 800          * ->compute_config if the first pick doesn't work out.
 801          */
 802         bool bw_constrained;
 803
 804         /* Settings for the intel dpll used on pretty much everything but
 805          * haswell. */
 806         struct dpll dpll;
 807
 808         /* Selected dpll when shared or NULL. */
 809         struct intel_shared_dpll *shared_dpll;
 810
 811         /* Actual register state of the dpll, for shared dpll cross-checking. */
 812         struct intel_dpll_hw_state dpll_hw_state;
 813
 814         /* DSI PLL registers */
 815         struct {
 816                 u32 ctrl, div;
 817         } dsi_pll;
 818
 819         int pipe_bpp;
 820         struct intel_link_m_n dp_m_n;
 821
 822         /* m2_n2 for eDP downclock */
 823         struct intel_link_m_n dp_m2_n2;
 824         bool has_drrs;
 825
 826         bool has_psr;
 827         bool has_psr2;
 828
 829         /*
 830          * Frequence the dpll for the port should run at. Differs from the
 831          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 832          * already multiplied by pixel_multiplier.
 833          */
 834         int port_clock;
 835
 836         /* Used by SDVO (and if we ever fix it, HDMI). */
 837         unsigned pixel_multiplier;
 838
 839         uint8_t lane_count;
 840
 841         /*
 842          * Used by platforms having DP/HDMI PHY with programmable lane
 843          * latency optimization.
 844          */
 845         uint8_t lane_lat_optim_mask;
 846
 847         /* minimum acceptable voltage level */
 848         u8 min_voltage_level;
 849
 850         /* Panel fitter controls for gen2-gen4 + VLV */
 851         struct {
 852                 u32 control;
 853                 u32 pgm_ratios;
 854                 u32 lvds_border_bits;
 855         } gmch_pfit;
 856
 857         /* Panel fitter placement and size for Ironlake+ */
 858         struct {
 859                 u32 pos;
 860                 u32 size;
 861                 bool enabled;
 862                 bool force_thru;
 863         } pch_pfit;
 864
 865         /* FDI configuration, only valid if has_pch_encoder is set. */
 866         int fdi_lanes;
 867         struct intel_link_m_n fdi_m_n;
 868
 869         bool ips_enabled;
 870         bool ips_force_disable;
 871
 872         bool enable_fbc;
 873
 874         bool double_wide;
 875
 876         int pbn;
 877
 878         struct intel_crtc_scaler_state scaler_state;
 879
 880         /* w/a for waiting 2 vblanks during crtc enable */
 881         enum pipe hsw_workaround_pipe;
 882
 883         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 884         bool disable_lp_wm;
 885
 886         struct intel_crtc_wm_state wm;
 887
 888         /* Gamma mode programmed on the pipe */
 889         uint32_t gamma_mode;
 890
 891         /* bitmask of visible planes (enum plane_id) */
 892         u8 active_planes;
 893         u8 nv12_planes;
 894
 895         /* HDMI scrambling status */
 896         bool hdmi_scrambling;
 897
 898         /* HDMI High TMDS char rate ratio */
 899         bool hdmi_high_tmds_clock_ratio;
 900
 901         /* output format is YCBCR 4:2:0 */
 902         bool ycbcr420;
 903 };
 904
 905 struct intel_crtc {
 906         struct drm_crtc base;
 907         enum pipe pipe;
 908         /*
 909          * Whether the crtc and the connected output pipeline is active. Implies
 910          * that crtc->enabled is set, i.e. the current mode configuration has
 911          * some outputs connected to this crtc.
 912          */
 913         bool active;
 914         u8 plane_ids_mask;
 915         unsigned long long enabled_power_domains;
 916         struct intel_overlay *overlay;
 917
 918         struct intel_crtc_state *config;
 919
 920         /* global reset count when the last flip was submitted */
 921         unsigned int reset_count;
 922
 923         /* Access to these should be protected by dev_priv->irq_lock. */
 924         bool cpu_fifo_underrun_disabled;
 925         bool pch_fifo_underrun_disabled;
 926
 927         /* per-pipe watermark state */
 928         struct {
 929                 /* watermarks currently being used  */
 930                 union {
 931                         struct intel_pipe_wm ilk;
 932                         struct vlv_wm_state vlv;
 933                         struct g4x_wm_state g4x;
 934                 } active;
 935         } wm;
 936
 937         int scanline_offset;
 938
 939         struct {
 940                 unsigned start_vbl_count;
 941                 ktime_t start_vbl_time;
 942                 int min_vbl, max_vbl;
 943                 int scanline_start;
 944         } debug;
 945
 946         /* scalers available on this crtc */
 947         int num_scalers;
 948 };
 949
 950 struct intel_plane {
 951         struct drm_plane base;
 952         enum i9xx_plane_id i9xx_plane;
 953         enum plane_id id;
 954         enum pipe pipe;
 955         bool can_scale;
 956         bool has_fbc;
 957         int max_downscale;
 958         uint32_t frontbuffer_bit;
 959
 960         struct {
 961                 u32 base, cntl, size;
 962         } cursor;
 963
 964         /*
 965          * NOTE: Do not place new plane state fields here (e.g., when adding
 966          * new plane properties).  New runtime state should now be placed in
 967          * the intel_plane_state structure and accessed via plane_state.
 968          */
 969
 970         void (*update_plane)(struct intel_plane *plane,
 971                              const struct intel_crtc_state *crtc_state,
 972                              const struct intel_plane_state *plane_state);
 973         void (*disable_plane)(struct intel_plane *plane,
 974                               struct intel_crtc *crtc);
 975         bool (*get_hw_state)(struct intel_plane *plane);
 976         int (*check_plane)(struct intel_plane *plane,
 977                            struct intel_crtc_state *crtc_state,
 978                            struct intel_plane_state *state);
 979 };
 980
 981 struct intel_watermark_params {
 982         u16 fifo_size;
 983         u16 max_wm;
 984         u8 default_wm;
 985         u8 guard_size;
 986         u8 cacheline_size;
 987 };
 988
 989 struct cxsr_latency {
 990         bool is_desktop : 1;
 991         bool is_ddr3 : 1;
 992         u16 fsb_freq;
 993         u16 mem_freq;
 994         u16 display_sr;
 995         u16 display_hpll_disable;
 996         u16 cursor_sr;
 997         u16 cursor_hpll_disable;
 998 };
 999
1000 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1001 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1002 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1003 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1004 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1005 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1006 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1007 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1008 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
1009
1010 struct intel_hdmi {
1011         i915_reg_t hdmi_reg;
1012         int ddc_bus;
1013         struct {
1014                 enum drm_dp_dual_mode_type type;
1015                 int max_tmds_clock;
1016         } dp_dual_mode;
1017         bool has_hdmi_sink;
1018         bool has_audio;
1019         bool rgb_quant_range_selectable;
1020         struct intel_connector *attached_connector;
1021 };
1022
1023 struct intel_dp_mst_encoder;
1024 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1025
1026 /*
1027  * enum link_m_n_set:
1028  *      When platform provides two set of M_N registers for dp, we can
1029  *      program them and switch between them incase of DRRS.
1030  *      But When only one such register is provided, we have to program the
1031  *      required divider value on that registers itself based on the DRRS state.
1032  *
1033  * M1_N1        : Program dp_m_n on M1_N1 registers
1034  *                        dp_m2_n2 on M2_N2 registers (If supported)
1035  *
1036  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1037  *                        M2_N2 registers are not supported
1038  */
1039
1040 enum link_m_n_set {
1041         /* Sets the m1_n1 and m2_n2 */
1042         M1_N1 = 0,
1043         M2_N2
1044 };
1045
1046 struct intel_dp_compliance_data {
1047         unsigned long edid;
1048         uint8_t video_pattern;
1049         uint16_t hdisplay, vdisplay;
1050         uint8_t bpc;
1051 };
1052
1053 struct intel_dp_compliance {
1054         unsigned long test_type;
1055         struct intel_dp_compliance_data test_data;
1056         bool test_active;
1057         int test_link_rate;
1058         u8 test_lane_count;
1059 };
1060
1061 struct intel_dp {
1062         i915_reg_t output_reg;
1063         uint32_t DP;
1064         int link_rate;
1065         uint8_t lane_count;
1066         uint8_t sink_count;
1067         bool link_mst;
1068         bool link_trained;
1069         bool has_audio;
1070         bool detect_done;
1071         bool reset_link_params;
1072         enum aux_ch aux_ch;
1073         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1074         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1075         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1076         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1077         /* source rates */
1078         int num_source_rates;
1079         const int *source_rates;
1080         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1081         int num_sink_rates;
1082         int sink_rates[DP_MAX_SUPPORTED_RATES];
1083         bool use_rate_select;
1084         /* intersection of source and sink rates */
1085         int num_common_rates;
1086         int common_rates[DP_MAX_SUPPORTED_RATES];
1087         /* Max lane count for the current link */
1088         int max_link_lane_count;
1089         /* Max rate for the current link */
1090         int max_link_rate;
1091         /* sink or branch descriptor */
1092         struct drm_dp_desc desc;
1093         struct drm_dp_aux aux;
1094         enum intel_display_power_domain aux_power_domain;
1095         uint8_t train_set[4];
1096         int panel_power_up_delay;
1097         int panel_power_down_delay;
1098         int panel_power_cycle_delay;
1099         int backlight_on_delay;
1100         int backlight_off_delay;
1101         struct delayed_work panel_vdd_work;
1102         bool want_panel_vdd;
1103         unsigned long last_power_on;
1104         unsigned long last_backlight_off;
1105         ktime_t panel_power_off_time;
1106
1107         struct notifier_block edp_notifier;
1108
1109         /*
1110          * Pipe whose power sequencer is currently locked into
1111          * this port. Only relevant on VLV/CHV.
1112          */
1113         enum pipe pps_pipe;
1114         /*
1115          * Pipe currently driving the port. Used for preventing
1116          * the use of the PPS for any pipe currentrly driving
1117          * external DP as that will mess things up on VLV.
1118          */
1119         enum pipe active_pipe;
1120         /*
1121          * Set if the sequencer may be reset due to a power transition,
1122          * requiring a reinitialization. Only relevant on BXT.
1123          */
1124         bool pps_reset;
1125         struct edp_power_seq pps_delays;
1126
1127         bool can_mst; /* this port supports mst */
1128         bool is_mst;
1129         int active_mst_links;
1130         /* connector directly attached - won't be use for modeset in mst world */
1131         struct intel_connector *attached_connector;
1132
1133         /* mst connector list */
1134         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1135         struct drm_dp_mst_topology_mgr mst_mgr;
1136
1137         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1138         /*
1139          * This function returns the value we have to program the AUX_CTL
1140          * register with to kick off an AUX transaction.
1141          */
1142         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1143                                      bool has_aux_irq,
1144                                      int send_bytes,
1145                                      uint32_t aux_clock_divider);
1146
1147         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1148         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1149
1150         /* This is called before a link training is starterd */
1151         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1152
1153         /* Displayport compliance testing */
1154         struct intel_dp_compliance compliance;
1155 };
1156
1157 struct intel_lspcon {
1158         bool active;
1159         enum drm_lspcon_mode mode;
1160 };
1161
1162 struct intel_digital_port {
1163         struct intel_encoder base;
1164         u32 saved_port_bits;
1165         struct intel_dp dp;
1166         struct intel_hdmi hdmi;
1167         struct intel_lspcon lspcon;
1168         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1169         bool release_cl2_override;
1170         uint8_t max_lanes;
1171         enum intel_display_power_domain ddi_io_power_domain;
1172
1173         void (*write_infoframe)(struct drm_encoder *encoder,
1174                                 const struct intel_crtc_state *crtc_state,
1175                                 unsigned int type,
1176                                 const void *frame, ssize_t len);
1177         void (*set_infoframes)(struct drm_encoder *encoder,
1178                                bool enable,
1179                                const struct intel_crtc_state *crtc_state,
1180                                const struct drm_connector_state *conn_state);
1181         bool (*infoframe_enabled)(struct drm_encoder *encoder,
1182                                   const struct intel_crtc_state *pipe_config);
1183 };
1184
1185 struct intel_dp_mst_encoder {
1186         struct intel_encoder base;
1187         enum pipe pipe;
1188         struct intel_digital_port *primary;
1189         struct intel_connector *connector;
1190 };
1191
1192 static inline enum dpio_channel
1193 vlv_dport_to_channel(struct intel_digital_port *dport)
1194 {
1195         switch (dport->base.port) {
1196         case PORT_B:
1197         case PORT_D:
1198                 return DPIO_CH0;
1199         case PORT_C:
1200                 return DPIO_CH1;
1201         default:
1202                 BUG();
1203         }
1204 }
1205
1206 static inline enum dpio_phy
1207 vlv_dport_to_phy(struct intel_digital_port *dport)
1208 {
1209         switch (dport->base.port) {
1210         case PORT_B:
1211         case PORT_C:
1212                 return DPIO_PHY0;
1213         case PORT_D:
1214                 return DPIO_PHY1;
1215         default:
1216                 BUG();
1217         }
1218 }
1219
1220 static inline enum dpio_channel
1221 vlv_pipe_to_channel(enum pipe pipe)
1222 {
1223         switch (pipe) {
1224         case PIPE_A:
1225         case PIPE_C:
1226                 return DPIO_CH0;
1227         case PIPE_B:
1228                 return DPIO_CH1;
1229         default:
1230                 BUG();
1231         }
1232 }
1233
1234 static inline struct intel_crtc *
1235 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1236 {
1237         return dev_priv->pipe_to_crtc_mapping[pipe];
1238 }
1239
1240 static inline struct intel_crtc *
1241 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1242 {
1243         return dev_priv->plane_to_crtc_mapping[plane];
1244 }
1245
1246 struct intel_load_detect_pipe {
1247         struct drm_atomic_state *restore_state;
1248 };
1249
1250 static inline struct intel_encoder *
1251 intel_attached_encoder(struct drm_connector *connector)
1252 {
1253         return to_intel_connector(connector)->encoder;
1254 }
1255
1256 static inline struct intel_digital_port *
1257 enc_to_dig_port(struct drm_encoder *encoder)
1258 {
1259         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1260
1261         switch (intel_encoder->type) {
1262         case INTEL_OUTPUT_DDI:
1263                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1264         case INTEL_OUTPUT_DP:
1265         case INTEL_OUTPUT_EDP:
1266         case INTEL_OUTPUT_HDMI:
1267                 return container_of(encoder, struct intel_digital_port,
1268                                     base.base);
1269         default:
1270                 return NULL;
1271         }
1272 }
1273
1274 static inline struct intel_dp_mst_encoder *
1275 enc_to_mst(struct drm_encoder *encoder)
1276 {
1277         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1278 }
1279
1280 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1281 {
1282         return &enc_to_dig_port(encoder)->dp;
1283 }
1284
1285 static inline struct intel_digital_port *
1286 dp_to_dig_port(struct intel_dp *intel_dp)
1287 {
1288         return container_of(intel_dp, struct intel_digital_port, dp);
1289 }
1290
1291 static inline struct intel_lspcon *
1292 dp_to_lspcon(struct intel_dp *intel_dp)
1293 {
1294         return &dp_to_dig_port(intel_dp)->lspcon;
1295 }
1296
1297 static inline struct intel_digital_port *
1298 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1299 {
1300         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1301 }
1302
1303 static inline struct intel_plane_state *
1304 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1305                                  struct intel_plane *plane)
1306 {
1307         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1308                                                                    &plane->base));
1309 }
1310
1311 static inline struct intel_crtc_state *
1312 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1313                                 struct intel_crtc *crtc)
1314 {
1315         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1316                                                                  &crtc->base));
1317 }
1318
1319 static inline struct intel_crtc_state *
1320 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1321                                 struct intel_crtc *crtc)
1322 {
1323         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1324                                                                  &crtc->base));
1325 }
1326
1327 /* intel_fifo_underrun.c */
1328 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1329                                            enum pipe pipe, bool enable);
1330 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1331                                            enum pipe pch_transcoder,
1332                                            bool enable);
1333 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1334                                          enum pipe pipe);
1335 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1336                                          enum pipe pch_transcoder);
1337 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1338 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1339
1340 /* i915_irq.c */
1341 bool gen11_reset_one_iir(struct drm_i915_private * const i915,
1342                          const unsigned int bank,
1343                          const unsigned int bit);
1344 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1345 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1346 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1347 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1348 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1349 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1350 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1351 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1352
1353 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1354                                             u32 mask)
1355 {
1356         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1357 }
1358
1359 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1360 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1361 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1362 {
1363         /*
1364          * We only use drm_irq_uninstall() at unload and VT switch, so
1365          * this is the only thing we need to check.
1366          */
1367         return dev_priv->runtime_pm.irqs_enabled;
1368 }
1369
1370 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1371 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1372                                      u8 pipe_mask);
1373 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1374                                      u8 pipe_mask);
1375 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1376 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1377 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1378
1379 /* intel_crt.c */
1380 void intel_crt_init(struct drm_i915_private *dev_priv);
1381 void intel_crt_reset(struct drm_encoder *encoder);
1382
1383 /* intel_ddi.c */
1384 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1385                                 const struct intel_crtc_state *old_crtc_state,
1386                                 const struct drm_connector_state *old_conn_state);
1387 void hsw_fdi_link_train(struct intel_crtc *crtc,
1388                         const struct intel_crtc_state *crtc_state);
1389 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1390 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1391 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1392 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1393                                        enum transcoder cpu_transcoder);
1394 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1395 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1396 struct intel_encoder *
1397 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1398 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1399 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1400 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1401 void intel_ddi_get_config(struct intel_encoder *encoder,
1402                           struct intel_crtc_state *pipe_config);
1403
1404 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1405                                     bool state);
1406 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1407                                          struct intel_crtc_state *crtc_state);
1408 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1409 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1410 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1411 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1412                                      bool enable);
1413 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1414                            struct intel_crtc_state *crtc_state,
1415                            struct drm_atomic_state *old_state);
1416 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1417                              struct intel_crtc_state *crtc_state,
1418                              struct drm_atomic_state *old_state);
1419
1420 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1421                                    int plane, unsigned int height);
1422
1423 /* intel_audio.c */
1424 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1425 void intel_audio_codec_enable(struct intel_encoder *encoder,
1426                               const struct intel_crtc_state *crtc_state,
1427                               const struct drm_connector_state *conn_state);
1428 void intel_audio_codec_disable(struct intel_encoder *encoder,
1429                                const struct intel_crtc_state *old_crtc_state,
1430                                const struct drm_connector_state *old_conn_state);
1431 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1432 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1433 void intel_audio_init(struct drm_i915_private *dev_priv);
1434 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1435
1436 /* intel_cdclk.c */
1437 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1438 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1439 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1440 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1441 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1442 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1443 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1444 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1445 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1446 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1447 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1448 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1449 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1450 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1451                                const struct intel_cdclk_state *b);
1452 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1453                          const struct intel_cdclk_state *b);
1454 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1455                      const struct intel_cdclk_state *cdclk_state);
1456 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1457                             const char *context);
1458
1459 /* intel_display.c */
1460 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1461 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1462 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1463 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1464 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1465 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1466                       const char *name, u32 reg, int ref_freq);
1467 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1468                            const char *name, u32 reg);
1469 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1470 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1471 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1472 unsigned int intel_fb_xy_to_linear(int x, int y,
1473                                    const struct intel_plane_state *state,
1474                                    int plane);
1475 void intel_add_fb_offsets(int *x, int *y,
1476                           const struct intel_plane_state *state, int plane);
1477 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1478 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1479 void intel_mark_busy(struct drm_i915_private *dev_priv);
1480 void intel_mark_idle(struct drm_i915_private *dev_priv);
1481 int intel_display_suspend(struct drm_device *dev);
1482 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1483 void intel_encoder_destroy(struct drm_encoder *encoder);
1484 int intel_connector_init(struct intel_connector *);
1485 struct intel_connector *intel_connector_alloc(void);
1486 void intel_connector_free(struct intel_connector *connector);
1487 bool intel_connector_get_hw_state(struct intel_connector *connector);
1488 void intel_connector_attach_encoder(struct intel_connector *connector,
1489                                     struct intel_encoder *encoder);
1490 struct drm_display_mode *
1491 intel_encoder_current_mode(struct intel_encoder *encoder);
1492
1493 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1494 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1495                                       struct drm_file *file_priv);
1496 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1497                                              enum pipe pipe);
1498 static inline bool
1499 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1500                     enum intel_output_type type)
1501 {
1502         return crtc_state->output_types & (1 << type);
1503 }
1504 static inline bool
1505 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1506 {
1507         return crtc_state->output_types &
1508                 ((1 << INTEL_OUTPUT_DP) |
1509                  (1 << INTEL_OUTPUT_DP_MST) |
1510                  (1 << INTEL_OUTPUT_EDP));
1511 }
1512 static inline void
1513 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1514 {
1515         drm_wait_one_vblank(&dev_priv->drm, pipe);
1516 }
1517 static inline void
1518 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1519 {
1520         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1521
1522         if (crtc->active)
1523                 intel_wait_for_vblank(dev_priv, pipe);
1524 }
1525
1526 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1527
1528 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1529 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1530                          struct intel_digital_port *dport,
1531                          unsigned int expected_mask);
1532 int intel_get_load_detect_pipe(struct drm_connector *connector,
1533                                const struct drm_display_mode *mode,
1534                                struct intel_load_detect_pipe *old,
1535                                struct drm_modeset_acquire_ctx *ctx);
1536 void intel_release_load_detect_pipe(struct drm_connector *connector,
1537                                     struct intel_load_detect_pipe *old,
1538                                     struct drm_modeset_acquire_ctx *ctx);
1539 struct i915_vma *
1540 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1541                            unsigned int rotation,
1542                            bool uses_fence,
1543                            unsigned long *out_flags);
1544 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1545 struct drm_framebuffer *
1546 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1547                          struct drm_mode_fb_cmd2 *mode_cmd);
1548 int intel_prepare_plane_fb(struct drm_plane *plane,
1549                            struct drm_plane_state *new_state);
1550 void intel_cleanup_plane_fb(struct drm_plane *plane,
1551                             struct drm_plane_state *old_state);
1552 int intel_plane_atomic_get_property(struct drm_plane *plane,
1553                                     const struct drm_plane_state *state,
1554                                     struct drm_property *property,
1555                                     uint64_t *val);
1556 int intel_plane_atomic_set_property(struct drm_plane *plane,
1557                                     struct drm_plane_state *state,
1558                                     struct drm_property *property,
1559                                     uint64_t val);
1560 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1561                                     struct drm_crtc_state *crtc_state,
1562                                     const struct intel_plane_state *old_plane_state,
1563                                     struct drm_plane_state *plane_state);
1564
1565 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1566                                     enum pipe pipe);
1567
1568 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1569                      const struct dpll *dpll);
1570 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1571 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1572
1573 /* modesetting asserts */
1574 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1575                            enum pipe pipe);
1576 void assert_pll(struct drm_i915_private *dev_priv,
1577                 enum pipe pipe, bool state);
1578 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1579 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1580 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1581 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1582 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1583 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1584                        enum pipe pipe, bool state);
1585 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1586 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1587 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1588 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1589 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1590 u32 intel_compute_tile_offset(int *x, int *y,
1591                               const struct intel_plane_state *state, int plane);
1592 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1593 void intel_finish_reset(struct drm_i915_private *dev_priv);
1594 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1595 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1596 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1597 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1598 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1599 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1600 unsigned int skl_cdclk_get_vco(unsigned int freq);
1601 void intel_dp_get_m_n(struct intel_crtc *crtc,
1602                       struct intel_crtc_state *pipe_config);
1603 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1604 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1605 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1606                         struct dpll *best_clock);
1607 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1608
1609 bool intel_crtc_active(struct intel_crtc *crtc);
1610 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1611 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1612 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1613 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1614 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1615                                  struct intel_crtc_state *pipe_config);
1616 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1617                                   struct intel_crtc_state *crtc_state);
1618
1619 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1620 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1621                   uint32_t pixel_format);
1622
1623 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1624 {
1625         return i915_ggtt_offset(state->vma);
1626 }
1627
1628 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1629                         const struct intel_plane_state *plane_state);
1630 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1631                   const struct intel_plane_state *plane_state);
1632 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1633 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1634                      unsigned int rotation);
1635 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
1636                             struct intel_plane_state *plane_state);
1637 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1638 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1639
1640 /* intel_csr.c */
1641 void intel_csr_ucode_init(struct drm_i915_private *);
1642 void intel_csr_load_program(struct drm_i915_private *);
1643 void intel_csr_ucode_fini(struct drm_i915_private *);
1644 void intel_csr_ucode_suspend(struct drm_i915_private *);
1645 void intel_csr_ucode_resume(struct drm_i915_private *);
1646
1647 /* intel_dp.c */
1648 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1649                    enum port port);
1650 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1651                              struct intel_connector *intel_connector);
1652 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1653                               int link_rate, uint8_t lane_count,
1654                               bool link_mst);
1655 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1656                                             int link_rate, uint8_t lane_count);
1657 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1658 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1659 int intel_dp_retrain_link(struct intel_encoder *encoder,
1660                           struct drm_modeset_acquire_ctx *ctx);
1661 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1662 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1663 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1664 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1665 int intel_dp_sink_crc(struct intel_dp *intel_dp,
1666                       struct intel_crtc_state *crtc_state, u8 *crc);
1667 bool intel_dp_compute_config(struct intel_encoder *encoder,
1668                              struct intel_crtc_state *pipe_config,
1669                              struct drm_connector_state *conn_state);
1670 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1671 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1672 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1673                                   bool long_hpd);
1674 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1675                             const struct drm_connector_state *conn_state);
1676 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1677 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1678 void intel_edp_panel_on(struct intel_dp *intel_dp);
1679 void intel_edp_panel_off(struct intel_dp *intel_dp);
1680 void intel_dp_mst_suspend(struct drm_device *dev);
1681 void intel_dp_mst_resume(struct drm_device *dev);
1682 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1683 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1684 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1685 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1686 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1687 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1688 void intel_plane_destroy(struct drm_plane *plane);
1689 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1690                            const struct intel_crtc_state *crtc_state);
1691 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1692                             const struct intel_crtc_state *crtc_state);
1693 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1694                                unsigned int frontbuffer_bits);
1695 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1696                           unsigned int frontbuffer_bits);
1697
1698 void
1699 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1700                                        uint8_t dp_train_pat);
1701 void
1702 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1703 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1704 uint8_t
1705 intel_dp_voltage_max(struct intel_dp *intel_dp);
1706 uint8_t
1707 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1708 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1709                            uint8_t *link_bw, uint8_t *rate_select);
1710 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1711 bool
1712 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1713
1714 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1715 {
1716         return ~((1 << lane_count) - 1) & 0xf;
1717 }
1718
1719 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1720 int intel_dp_link_required(int pixel_clock, int bpp);
1721 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1722 bool intel_digital_port_connected(struct intel_encoder *encoder);
1723
1724 /* intel_dp_aux_backlight.c */
1725 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1726
1727 /* intel_dp_mst.c */
1728 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1729 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1730 /* intel_dsi.c */
1731 void intel_dsi_init(struct drm_i915_private *dev_priv);
1732
1733 /* intel_dsi_dcs_backlight.c */
1734 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1735
1736 /* intel_dvo.c */
1737 void intel_dvo_init(struct drm_i915_private *dev_priv);
1738 /* intel_hotplug.c */
1739 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1740 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1741                            struct intel_connector *connector);
1742
1743 /* legacy fbdev emulation in intel_fbdev.c */
1744 #ifdef CONFIG_DRM_FBDEV_EMULATION
1745 extern int intel_fbdev_init(struct drm_device *dev);
1746 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1747 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1748 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1749 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1750 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1751 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1752 #else
1753 static inline int intel_fbdev_init(struct drm_device *dev)
1754 {
1755         return 0;
1756 }
1757
1758 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1759 {
1760 }
1761
1762 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1763 {
1764 }
1765
1766 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1767 {
1768 }
1769
1770 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1771 {
1772 }
1773
1774 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1775 {
1776 }
1777
1778 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1779 {
1780 }
1781 #endif
1782
1783 /* intel_fbc.c */
1784 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1785                            struct intel_atomic_state *state);
1786 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1787 void intel_fbc_pre_update(struct intel_crtc *crtc,
1788                           struct intel_crtc_state *crtc_state,
1789                           struct intel_plane_state *plane_state);
1790 void intel_fbc_post_update(struct intel_crtc *crtc);
1791 void intel_fbc_init(struct drm_i915_private *dev_priv);
1792 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1793 void intel_fbc_enable(struct intel_crtc *crtc,
1794                       struct intel_crtc_state *crtc_state,
1795                       struct intel_plane_state *plane_state);
1796 void intel_fbc_disable(struct intel_crtc *crtc);
1797 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1798 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1799                           unsigned int frontbuffer_bits,
1800                           enum fb_op_origin origin);
1801 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1802                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1803 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1804 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1805 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1806
1807 /* intel_hdmi.c */
1808 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1809                      enum port port);
1810 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1811                                struct intel_connector *intel_connector);
1812 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1813 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1814                                struct intel_crtc_state *pipe_config,
1815                                struct drm_connector_state *conn_state);
1816 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1817                                        struct drm_connector *connector,
1818                                        bool high_tmds_clock_ratio,
1819                                        bool scrambling);
1820 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1821 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1822
1823
1824 /* intel_lvds.c */
1825 void intel_lvds_init(struct drm_i915_private *dev_priv);
1826 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1827 bool intel_is_dual_link_lvds(struct drm_device *dev);
1828
1829
1830 /* intel_modes.c */
1831 int intel_connector_update_modes(struct drm_connector *connector,
1832                                  struct edid *edid);
1833 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1834 void intel_attach_force_audio_property(struct drm_connector *connector);
1835 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1836 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1837
1838
1839 /* intel_overlay.c */
1840 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1841 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1842 int intel_overlay_switch_off(struct intel_overlay *overlay);
1843 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1844                                   struct drm_file *file_priv);
1845 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1846                               struct drm_file *file_priv);
1847 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1848
1849
1850 /* intel_panel.c */
1851 int intel_panel_init(struct intel_panel *panel,
1852                      struct drm_display_mode *fixed_mode,
1853                      struct drm_display_mode *alt_fixed_mode,
1854                      struct drm_display_mode *downclock_mode);
1855 void intel_panel_fini(struct intel_panel *panel);
1856 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1857                             struct drm_display_mode *adjusted_mode);
1858 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1859                              struct intel_crtc_state *pipe_config,
1860                              int fitting_mode);
1861 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1862                               struct intel_crtc_state *pipe_config,
1863                               int fitting_mode);
1864 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1865                                     u32 level, u32 max);
1866 int intel_panel_setup_backlight(struct drm_connector *connector,
1867                                 enum pipe pipe);
1868 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1869                                   const struct drm_connector_state *conn_state);
1870 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1871 void intel_panel_destroy_backlight(struct drm_connector *connector);
1872 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1873 extern struct drm_display_mode *intel_find_panel_downclock(
1874                                 struct drm_i915_private *dev_priv,
1875                                 struct drm_display_mode *fixed_mode,
1876                                 struct drm_connector *connector);
1877
1878 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1879 int intel_backlight_device_register(struct intel_connector *connector);
1880 void intel_backlight_device_unregister(struct intel_connector *connector);
1881 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1882 static inline int intel_backlight_device_register(struct intel_connector *connector)
1883 {
1884         return 0;
1885 }
1886 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1887 {
1888 }
1889 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1890
1891 /* intel_hdcp.c */
1892 void intel_hdcp_atomic_check(struct drm_connector *connector,
1893                              struct drm_connector_state *old_state,
1894                              struct drm_connector_state *new_state);
1895 int intel_hdcp_init(struct intel_connector *connector,
1896                     const struct intel_hdcp_shim *hdcp_shim);
1897 int intel_hdcp_enable(struct intel_connector *connector);
1898 int intel_hdcp_disable(struct intel_connector *connector);
1899 int intel_hdcp_check_link(struct intel_connector *connector);
1900 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
1901
1902 /* intel_psr.c */
1903 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1904 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
1905 void intel_psr_enable(struct intel_dp *intel_dp,
1906                       const struct intel_crtc_state *crtc_state);
1907 void intel_psr_disable(struct intel_dp *intel_dp,
1908                       const struct intel_crtc_state *old_crtc_state);
1909 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1910                           unsigned frontbuffer_bits,
1911                           enum fb_op_origin origin);
1912 void intel_psr_flush(struct drm_i915_private *dev_priv,
1913                      unsigned frontbuffer_bits,
1914                      enum fb_op_origin origin);
1915 void intel_psr_init(struct drm_i915_private *dev_priv);
1916 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1917                                    unsigned frontbuffer_bits);
1918 void intel_psr_compute_config(struct intel_dp *intel_dp,
1919                               struct intel_crtc_state *crtc_state);
1920 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
1921 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
1922
1923 /* intel_runtime_pm.c */
1924 int intel_power_domains_init(struct drm_i915_private *);
1925 void intel_power_domains_fini(struct drm_i915_private *);
1926 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1927 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1928 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1929 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1930 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1931 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1932 const char *
1933 intel_display_power_domain_str(enum intel_display_power_domain domain);
1934
1935 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1936                                     enum intel_display_power_domain domain);
1937 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1938                                       enum intel_display_power_domain domain);
1939 void intel_display_power_get(struct drm_i915_private *dev_priv,
1940                              enum intel_display_power_domain domain);
1941 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1942                                         enum intel_display_power_domain domain);
1943 void intel_display_power_put(struct drm_i915_private *dev_priv,
1944                              enum intel_display_power_domain domain);
1945 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
1946                             u8 req_slices);
1947
1948 static inline void
1949 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1950 {
1951         WARN_ONCE(dev_priv->runtime_pm.suspended,
1952                   "Device suspended during HW access\n");
1953 }
1954
1955 static inline void
1956 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1957 {
1958         assert_rpm_device_not_suspended(dev_priv);
1959         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1960                   "RPM wakelock ref not held during HW access");
1961 }
1962
1963 /**
1964  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1965  * @dev_priv: i915 device instance
1966  *
1967  * This function disable asserts that check if we hold an RPM wakelock
1968  * reference, while keeping the device-not-suspended checks still enabled.
1969  * It's meant to be used only in special circumstances where our rule about
1970  * the wakelock refcount wrt. the device power state doesn't hold. According
1971  * to this rule at any point where we access the HW or want to keep the HW in
1972  * an active state we must hold an RPM wakelock reference acquired via one of
1973  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1974  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1975  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1976  * users should avoid using this function.
1977  *
1978  * Any calls to this function must have a symmetric call to
1979  * enable_rpm_wakeref_asserts().
1980  */
1981 static inline void
1982 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1983 {
1984         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
1985 }
1986
1987 /**
1988  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1989  * @dev_priv: i915 device instance
1990  *
1991  * This function re-enables the RPM assert checks after disabling them with
1992  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1993  * circumstances otherwise its use should be avoided.
1994  *
1995  * Any calls to this function must have a symmetric call to
1996  * disable_rpm_wakeref_asserts().
1997  */
1998 static inline void
1999 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2000 {
2001         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2002 }
2003
2004 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2005 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2006 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2007 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2008
2009 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
2010
2011 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2012                              bool override, unsigned int mask);
2013 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2014                           enum dpio_channel ch, bool override);
2015
2016
2017 /* intel_pm.c */
2018 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2019 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2020 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2021 void intel_update_watermarks(struct intel_crtc *crtc);
2022 void intel_init_pm(struct drm_i915_private *dev_priv);
2023 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2024 void intel_pm_setup(struct drm_i915_private *dev_priv);
2025 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2026 void intel_gpu_ips_teardown(void);
2027 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2028 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2029 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2030 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2031 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2032 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2033 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2034 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2035 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2036 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2037 void g4x_wm_get_hw_state(struct drm_device *dev);
2038 void vlv_wm_get_hw_state(struct drm_device *dev);
2039 void ilk_wm_get_hw_state(struct drm_device *dev);
2040 void skl_wm_get_hw_state(struct drm_device *dev);
2041 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2042                           struct skl_ddb_allocation *ddb /* out */);
2043 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2044                               struct skl_pipe_wm *out);
2045 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2046 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2047 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2048 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2049 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2050 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2051                          const struct skl_wm_level *l2);
2052 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2053                                  const struct skl_ddb_entry **entries,
2054                                  const struct skl_ddb_entry *ddb,
2055                                  int ignore);
2056 bool ilk_disable_lp_wm(struct drm_device *dev);
2057 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2058                                   struct intel_crtc_state *cstate);
2059 void intel_init_ipc(struct drm_i915_private *dev_priv);
2060 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2061
2062 /* intel_sdvo.c */
2063 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2064                      i915_reg_t reg, enum port port);
2065
2066
2067 /* intel_sprite.c */
2068 bool intel_format_is_yuv(u32 format);
2069 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2070                              int usecs);
2071 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2072                                               enum pipe pipe, int plane);
2073 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2074                                     struct drm_file *file_priv);
2075 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2076 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2077 void skl_update_plane(struct intel_plane *plane,
2078                       const struct intel_crtc_state *crtc_state,
2079                       const struct intel_plane_state *plane_state);
2080 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
2081 bool skl_plane_get_hw_state(struct intel_plane *plane);
2082 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2083                        enum pipe pipe, enum plane_id plane_id);
2084 bool intel_format_is_yuv(uint32_t format);
2085 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2086                           enum pipe pipe, enum plane_id plane_id);
2087
2088 /* intel_tv.c */
2089 void intel_tv_init(struct drm_i915_private *dev_priv);
2090
2091 /* intel_atomic.c */
2092 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2093                                                 const struct drm_connector_state *state,
2094                                                 struct drm_property *property,
2095                                                 uint64_t *val);
2096 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2097                                                 struct drm_connector_state *state,
2098                                                 struct drm_property *property,
2099                                                 uint64_t val);
2100 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2101                                          struct drm_connector_state *new_state);
2102 struct drm_connector_state *
2103 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2104
2105 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2106 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2107                                struct drm_crtc_state *state);
2108 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2109 void intel_atomic_state_clear(struct drm_atomic_state *);
2110
2111 static inline struct intel_crtc_state *
2112 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2113                             struct intel_crtc *crtc)
2114 {
2115         struct drm_crtc_state *crtc_state;
2116         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2117         if (IS_ERR(crtc_state))
2118                 return ERR_CAST(crtc_state);
2119
2120         return to_intel_crtc_state(crtc_state);
2121 }
2122
2123 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2124                                struct intel_crtc *intel_crtc,
2125                                struct intel_crtc_state *crtc_state);
2126
2127 /* intel_atomic_plane.c */
2128 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2129 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2130 void intel_plane_destroy_state(struct drm_plane *plane,
2131                                struct drm_plane_state *state);
2132 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2133 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2134                                         struct intel_crtc_state *crtc_state,
2135                                         const struct intel_plane_state *old_plane_state,
2136                                         struct intel_plane_state *intel_state);
2137
2138 /* intel_color.c */
2139 void intel_color_init(struct drm_crtc *crtc);
2140 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2141 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2142 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2143
2144 /* intel_lspcon.c */
2145 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2146 void lspcon_resume(struct intel_lspcon *lspcon);
2147 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2148
2149 /* intel_pipe_crc.c */
2150 int intel_pipe_crc_create(struct drm_minor *minor);
2151 #ifdef CONFIG_DEBUG_FS
2152 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2153                               size_t *values_cnt);
2154 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2155 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2156 #else
2157 #define intel_crtc_set_crc_source NULL
2158 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2159 {
2160 }
2161
2162 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2163 {
2164 }
2165 #endif
2166 extern const struct file_operations i915_display_crc_ctl_fops;
2167 #endif /* __INTEL_DRV_H__ */