drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_encoder.h>
  36 #include <drm/drm_fb_helper.h>
  37 #include <drm/drm_dp_dual_mode_helper.h>
  38 #include <drm/drm_dp_mst_helper.h>
  39 #include <drm/drm_rect.h>
  40 #include <drm/drm_atomic.h>
  41
  42 /**
  43  * _wait_for - magic (register) wait macro
  44  *
  45  * Does the right thing for modeset paths when run under kdgb or similar atomic
  46  * contexts. Note that it's important that we check the condition again after
  47  * having timed out, since the timeout could be due to preemption or similar and
  48  * we've never had a chance to check the condition before the timeout.
  49  *
  50  * TODO: When modesetting has fully transitioned to atomic, the below
  51  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  52  * added.
  53  */
  54 #define _wait_for(COND, US, W) ({ \
  55         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  56         int ret__;                                                      \
  57         for (;;) {                                                      \
  58                 bool expired__ = time_after(jiffies, timeout__);        \
  59                 if (COND) {                                             \
  60                         ret__ = 0;                                      \
  61                         break;                                          \
  62                 }                                                       \
  63                 if (expired__) {                                        \
  64                         ret__ = -ETIMEDOUT;                             \
  65                         break;                                          \
  66                 }                                                       \
  67                 if ((W) && drm_can_sleep()) {                           \
  68                         usleep_range((W), (W)*2);                       \
  69                 } else {                                                \
  70                         cpu_relax();                                    \
  71                 }                                                       \
  72         }                                                               \
  73         ret__;                                                          \
  74 })
  75
  76 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  77
  78 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  79 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  80 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  81 #else
  82 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  83 #endif
  84
  85 #define _wait_for_atomic(COND, US, ATOMIC) \
  86 ({ \
  87         int cpu, ret, timeout = (US) * 1000; \
  88         u64 base; \
  89         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  90         BUILD_BUG_ON((US) > 50000); \
  91         if (!(ATOMIC)) { \
  92                 preempt_disable(); \
  93                 cpu = smp_processor_id(); \
  94         } \
  95         base = local_clock(); \
  96         for (;;) { \
  97                 u64 now = local_clock(); \
  98                 if (!(ATOMIC)) \
  99                         preempt_enable(); \
 100                 if (COND) { \
 101                         ret = 0; \
 102                         break; \
 103                 } \
 104                 if (now - base >= timeout) { \
 105                         ret = -ETIMEDOUT; \
 106                         break; \
 107                 } \
 108                 cpu_relax(); \
 109                 if (!(ATOMIC)) { \
 110                         preempt_disable(); \
 111                         if (unlikely(cpu != smp_processor_id())) { \
 112                                 timeout -= now - base; \
 113                                 cpu = smp_processor_id(); \
 114                                 base = local_clock(); \
 115                         } \
 116                 } \
 117         } \
 118         ret; \
 119 })
 120
 121 #define wait_for_us(COND, US) \
 122 ({ \
 123         int ret__; \
 124         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 125         if ((US) > 10) \
 126                 ret__ = _wait_for((COND), (US), 10); \
 127         else \
 128                 ret__ = _wait_for_atomic((COND), (US), 0); \
 129         ret__; \
 130 })
 131
 132 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 133 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 134
 135 #define KHz(x) (1000 * (x))
 136 #define MHz(x) KHz(1000 * (x))
 137
 138 /*
 139  * Display related stuff
 140  */
 141
 142 /* store information about an Ixxx DVO */
 143 /* The i830->i865 use multiple DVOs with multiple i2cs */
 144 /* the i915, i945 have a single sDVO i2c bus - which is different */
 145 #define MAX_OUTPUTS 6
 146 /* maximum connectors per crtcs in the mode set */
 147
 148 /* Maximum cursor sizes */
 149 #define GEN2_CURSOR_WIDTH 64
 150 #define GEN2_CURSOR_HEIGHT 64
 151 #define MAX_CURSOR_WIDTH 256
 152 #define MAX_CURSOR_HEIGHT 256
 153
 154 #define INTEL_I2C_BUS_DVO 1
 155 #define INTEL_I2C_BUS_SDVO 2
 156
 157 /* these are outputs from the chip - integrated only
 158    external chips are via DVO or SDVO output */
 159 enum intel_output_type {
 160         INTEL_OUTPUT_UNUSED = 0,
 161         INTEL_OUTPUT_ANALOG = 1,
 162         INTEL_OUTPUT_DVO = 2,
 163         INTEL_OUTPUT_SDVO = 3,
 164         INTEL_OUTPUT_LVDS = 4,
 165         INTEL_OUTPUT_TVOUT = 5,
 166         INTEL_OUTPUT_HDMI = 6,
 167         INTEL_OUTPUT_DP = 7,
 168         INTEL_OUTPUT_EDP = 8,
 169         INTEL_OUTPUT_DSI = 9,
 170         INTEL_OUTPUT_UNKNOWN = 10,
 171         INTEL_OUTPUT_DP_MST = 11,
 172 };
 173
 174 #define INTEL_DVO_CHIP_NONE 0
 175 #define INTEL_DVO_CHIP_LVDS 1
 176 #define INTEL_DVO_CHIP_TMDS 2
 177 #define INTEL_DVO_CHIP_TVOUT 4
 178
 179 #define INTEL_DSI_VIDEO_MODE    0
 180 #define INTEL_DSI_COMMAND_MODE  1
 181
 182 struct intel_framebuffer {
 183         struct drm_framebuffer base;
 184         struct drm_i915_gem_object *obj;
 185         struct intel_rotation_info rot_info;
 186
 187         /* for each plane in the normal GTT view */
 188         struct {
 189                 unsigned int x, y;
 190         } normal[2];
 191         /* for each plane in the rotated GTT view */
 192         struct {
 193                 unsigned int x, y;
 194                 unsigned int pitch; /* pixels */
 195         } rotated[2];
 196 };
 197
 198 struct intel_fbdev {
 199         struct drm_fb_helper helper;
 200         struct intel_framebuffer *fb;
 201         struct i915_vma *vma;
 202         async_cookie_t cookie;
 203         int preferred_bpp;
 204 };
 205
 206 struct intel_encoder {
 207         struct drm_encoder base;
 208
 209         enum intel_output_type type;
 210         enum port port;
 211         unsigned int cloneable;
 212         void (*hot_plug)(struct intel_encoder *);
 213         bool (*compute_config)(struct intel_encoder *,
 214                                struct intel_crtc_state *,
 215                                struct drm_connector_state *);
 216         void (*pre_pll_enable)(struct intel_encoder *,
 217                                struct intel_crtc_state *,
 218                                struct drm_connector_state *);
 219         void (*pre_enable)(struct intel_encoder *,
 220                            struct intel_crtc_state *,
 221                            struct drm_connector_state *);
 222         void (*enable)(struct intel_encoder *,
 223                        struct intel_crtc_state *,
 224                        struct drm_connector_state *);
 225         void (*disable)(struct intel_encoder *,
 226                         struct intel_crtc_state *,
 227                         struct drm_connector_state *);
 228         void (*post_disable)(struct intel_encoder *,
 229                              struct intel_crtc_state *,
 230                              struct drm_connector_state *);
 231         void (*post_pll_disable)(struct intel_encoder *,
 232                                  struct intel_crtc_state *,
 233                                  struct drm_connector_state *);
 234         /* Read out the current hw state of this connector, returning true if
 235          * the encoder is active. If the encoder is enabled it also set the pipe
 236          * it is connected to in the pipe parameter. */
 237         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 238         /* Reconstructs the equivalent mode flags for the current hardware
 239          * state. This must be called _after_ display->get_pipe_config has
 240          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 241          * be set correctly before calling this function. */
 242         void (*get_config)(struct intel_encoder *,
 243                            struct intel_crtc_state *pipe_config);
 244         /*
 245          * Called during system suspend after all pending requests for the
 246          * encoder are flushed (for example for DP AUX transactions) and
 247          * device interrupts are disabled.
 248          */
 249         void (*suspend)(struct intel_encoder *);
 250         int crtc_mask;
 251         enum hpd_pin hpd_pin;
 252         /* for communication with audio component; protected by av_mutex */
 253         const struct drm_connector *audio_connector;
 254 };
 255
 256 struct intel_panel {
 257         struct drm_display_mode *fixed_mode;
 258         struct drm_display_mode *downclock_mode;
 259         int fitting_mode;
 260
 261         /* backlight */
 262         struct {
 263                 bool present;
 264                 u32 level;
 265                 u32 min;
 266                 u32 max;
 267                 bool enabled;
 268                 bool combination_mode;  /* gen 2/4 only */
 269                 bool active_low_pwm;
 270                 bool alternate_pwm_increment;   /* lpt+ */
 271
 272                 /* PWM chip */
 273                 bool util_pin_active_low;       /* bxt+ */
 274                 u8 controller;          /* bxt+ only */
 275                 struct pwm_device *pwm;
 276
 277                 struct backlight_device *device;
 278
 279                 /* Connector and platform specific backlight functions */
 280                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 281                 uint32_t (*get)(struct intel_connector *connector);
 282                 void (*set)(struct intel_connector *connector, uint32_t level);
 283                 void (*disable)(struct intel_connector *connector);
 284                 void (*enable)(struct intel_connector *connector);
 285                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 286                                       uint32_t hz);
 287                 void (*power)(struct intel_connector *, bool enable);
 288         } backlight;
 289 };
 290
 291 struct intel_connector {
 292         struct drm_connector base;
 293         /*
 294          * The fixed encoder this connector is connected to.
 295          */
 296         struct intel_encoder *encoder;
 297
 298         /* ACPI device id for ACPI and driver cooperation */
 299         u32 acpi_device_id;
 300
 301         /* Reads out the current hw, returning true if the connector is enabled
 302          * and active (i.e. dpms ON state). */
 303         bool (*get_hw_state)(struct intel_connector *);
 304
 305         /* Panel info for eDP and LVDS */
 306         struct intel_panel panel;
 307
 308         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 309         struct edid *edid;
 310         struct edid *detect_edid;
 311
 312         /* since POLL and HPD connectors may use the same HPD line keep the native
 313            state of connector->polled in case hotplug storm detection changes it */
 314         u8 polled;
 315
 316         void *port; /* store this opaque as its illegal to dereference it */
 317
 318         struct intel_dp *mst_port;
 319 };
 320
 321 struct dpll {
 322         /* given values */
 323         int n;
 324         int m1, m2;
 325         int p1, p2;
 326         /* derived values */
 327         int     dot;
 328         int     vco;
 329         int     m;
 330         int     p;
 331 };
 332
 333 struct intel_atomic_state {
 334         struct drm_atomic_state base;
 335
 336         unsigned int cdclk;
 337
 338         /*
 339          * Calculated device cdclk, can be different from cdclk
 340          * only when all crtc's are DPMS off.
 341          */
 342         unsigned int dev_cdclk;
 343
 344         bool dpll_set, modeset;
 345
 346         /*
 347          * Does this transaction change the pipes that are active?  This mask
 348          * tracks which CRTC's have changed their active state at the end of
 349          * the transaction (not counting the temporary disable during modesets).
 350          * This mask should only be non-zero when intel_state->modeset is true,
 351          * but the converse is not necessarily true; simply changing a mode may
 352          * not flip the final active status of any CRTC's
 353          */
 354         unsigned int active_pipe_changes;
 355
 356         unsigned int active_crtcs;
 357         unsigned int min_pixclk[I915_MAX_PIPES];
 358
 359         /* SKL/KBL Only */
 360         unsigned int cdclk_pll_vco;
 361
 362         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 363
 364         /*
 365          * Current watermarks can't be trusted during hardware readout, so
 366          * don't bother calculating intermediate watermarks.
 367          */
 368         bool skip_intermediate_wm;
 369
 370         /* Gen9+ only */
 371         struct skl_wm_values wm_results;
 372
 373         struct i915_sw_fence commit_ready;
 374
 375         struct llist_node freed;
 376 };
 377
 378 struct intel_plane_state {
 379         struct drm_plane_state base;
 380         struct drm_rect clip;
 381         struct i915_vma *vma;
 382
 383         struct {
 384                 u32 offset;
 385                 int x, y;
 386         } main;
 387         struct {
 388                 u32 offset;
 389                 int x, y;
 390         } aux;
 391
 392         /*
 393          * scaler_id
 394          *    = -1 : not using a scaler
 395          *    >=  0 : using a scalers
 396          *
 397          * plane requiring a scaler:
 398          *   - During check_plane, its bit is set in
 399          *     crtc_state->scaler_state.scaler_users by calling helper function
 400          *     update_scaler_plane.
 401          *   - scaler_id indicates the scaler it got assigned.
 402          *
 403          * plane doesn't require a scaler:
 404          *   - this can happen when scaling is no more required or plane simply
 405          *     got disabled.
 406          *   - During check_plane, corresponding bit is reset in
 407          *     crtc_state->scaler_state.scaler_users by calling helper function
 408          *     update_scaler_plane.
 409          */
 410         int scaler_id;
 411
 412         struct drm_intel_sprite_colorkey ckey;
 413 };
 414
 415 struct intel_initial_plane_config {
 416         struct intel_framebuffer *fb;
 417         unsigned int tiling;
 418         int size;
 419         u32 base;
 420 };
 421
 422 #define SKL_MIN_SRC_W 8
 423 #define SKL_MAX_SRC_W 4096
 424 #define SKL_MIN_SRC_H 8
 425 #define SKL_MAX_SRC_H 4096
 426 #define SKL_MIN_DST_W 8
 427 #define SKL_MAX_DST_W 4096
 428 #define SKL_MIN_DST_H 8
 429 #define SKL_MAX_DST_H 4096
 430
 431 struct intel_scaler {
 432         int in_use;
 433         uint32_t mode;
 434 };
 435
 436 struct intel_crtc_scaler_state {
 437 #define SKL_NUM_SCALERS 2
 438         struct intel_scaler scalers[SKL_NUM_SCALERS];
 439
 440         /*
 441          * scaler_users: keeps track of users requesting scalers on this crtc.
 442          *
 443          *     If a bit is set, a user is using a scaler.
 444          *     Here user can be a plane or crtc as defined below:
 445          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 446          *       bit 31    - crtc
 447          *
 448          * Instead of creating a new index to cover planes and crtc, using
 449          * existing drm_plane_index for planes which is well less than 31
 450          * planes and bit 31 for crtc. This should be fine to cover all
 451          * our platforms.
 452          *
 453          * intel_atomic_setup_scalers will setup available scalers to users
 454          * requesting scalers. It will gracefully fail if request exceeds
 455          * avilability.
 456          */
 457 #define SKL_CRTC_INDEX 31
 458         unsigned scaler_users;
 459
 460         /* scaler used by crtc for panel fitting purpose */
 461         int scaler_id;
 462 };
 463
 464 /* drm_mode->private_flags */
 465 #define I915_MODE_FLAG_INHERITED 1
 466
 467 struct intel_pipe_wm {
 468         struct intel_wm_level wm[5];
 469         struct intel_wm_level raw_wm[5];
 470         uint32_t linetime;
 471         bool fbc_wm_enabled;
 472         bool pipe_enabled;
 473         bool sprites_enabled;
 474         bool sprites_scaled;
 475 };
 476
 477 struct skl_plane_wm {
 478         struct skl_wm_level wm[8];
 479         struct skl_wm_level trans_wm;
 480 };
 481
 482 struct skl_pipe_wm {
 483         struct skl_plane_wm planes[I915_MAX_PLANES];
 484         uint32_t linetime;
 485 };
 486
 487 struct intel_crtc_wm_state {
 488         union {
 489                 struct {
 490                         /*
 491                          * Intermediate watermarks; these can be
 492                          * programmed immediately since they satisfy
 493                          * both the current configuration we're
 494                          * switching away from and the new
 495                          * configuration we're switching to.
 496                          */
 497                         struct intel_pipe_wm intermediate;
 498
 499                         /*
 500                          * Optimal watermarks, programmed post-vblank
 501                          * when this state is committed.
 502                          */
 503                         struct intel_pipe_wm optimal;
 504                 } ilk;
 505
 506                 struct {
 507                         /* gen9+ only needs 1-step wm programming */
 508                         struct skl_pipe_wm optimal;
 509                         struct skl_ddb_entry ddb;
 510                 } skl;
 511         };
 512
 513         /*
 514          * Platforms with two-step watermark programming will need to
 515          * update watermark programming post-vblank to switch from the
 516          * safe intermediate watermarks to the optimal final
 517          * watermarks.
 518          */
 519         bool need_postvbl_update;
 520 };
 521
 522 struct intel_crtc_state {
 523         struct drm_crtc_state base;
 524
 525         /**
 526          * quirks - bitfield with hw state readout quirks
 527          *
 528          * For various reasons the hw state readout code might not be able to
 529          * completely faithfully read out the current state. These cases are
 530          * tracked with quirk flags so that fastboot and state checker can act
 531          * accordingly.
 532          */
 533 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 534         unsigned long quirks;
 535
 536         unsigned fb_bits; /* framebuffers to flip */
 537         bool update_pipe; /* can a fast modeset be performed? */
 538         bool disable_cxsr;
 539         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 540         bool fb_changed; /* fb on any of the planes is changed */
 541
 542         /* Pipe source size (ie. panel fitter input size)
 543          * All planes will be positioned inside this space,
 544          * and get clipped at the edges. */
 545         int pipe_src_w, pipe_src_h;
 546
 547         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 548          * between pch encoders and cpu encoders. */
 549         bool has_pch_encoder;
 550
 551         /* Are we sending infoframes on the attached port */
 552         bool has_infoframe;
 553
 554         /* CPU Transcoder for the pipe. Currently this can only differ from the
 555          * pipe on Haswell and later (where we have a special eDP transcoder)
 556          * and Broxton (where we have special DSI transcoders). */
 557         enum transcoder cpu_transcoder;
 558
 559         /*
 560          * Use reduced/limited/broadcast rbg range, compressing from the full
 561          * range fed into the crtcs.
 562          */
 563         bool limited_color_range;
 564
 565         /* Bitmask of encoder types (enum intel_output_type)
 566          * driven by the pipe.
 567          */
 568         unsigned int output_types;
 569
 570         /* Whether we should send NULL infoframes. Required for audio. */
 571         bool has_hdmi_sink;
 572
 573         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 574          * has_dp_encoder is set. */
 575         bool has_audio;
 576
 577         /*
 578          * Enable dithering, used when the selected pipe bpp doesn't match the
 579          * plane bpp.
 580          */
 581         bool dither;
 582
 583         /* Controls for the clock computation, to override various stages. */
 584         bool clock_set;
 585
 586         /* SDVO TV has a bunch of special case. To make multifunction encoders
 587          * work correctly, we need to track this at runtime.*/
 588         bool sdvo_tv_clock;
 589
 590         /*
 591          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 592          * required. This is set in the 2nd loop of calling encoder's
 593          * ->compute_config if the first pick doesn't work out.
 594          */
 595         bool bw_constrained;
 596
 597         /* Settings for the intel dpll used on pretty much everything but
 598          * haswell. */
 599         struct dpll dpll;
 600
 601         /* Selected dpll when shared or NULL. */
 602         struct intel_shared_dpll *shared_dpll;
 603
 604         /* Actual register state of the dpll, for shared dpll cross-checking. */
 605         struct intel_dpll_hw_state dpll_hw_state;
 606
 607         /* DSI PLL registers */
 608         struct {
 609                 u32 ctrl, div;
 610         } dsi_pll;
 611
 612         int pipe_bpp;
 613         struct intel_link_m_n dp_m_n;
 614
 615         /* m2_n2 for eDP downclock */
 616         struct intel_link_m_n dp_m2_n2;
 617         bool has_drrs;
 618
 619         /*
 620          * Frequence the dpll for the port should run at. Differs from the
 621          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 622          * already multiplied by pixel_multiplier.
 623          */
 624         int port_clock;
 625
 626         /* Used by SDVO (and if we ever fix it, HDMI). */
 627         unsigned pixel_multiplier;
 628
 629         uint8_t lane_count;
 630
 631         /*
 632          * Used by platforms having DP/HDMI PHY with programmable lane
 633          * latency optimization.
 634          */
 635         uint8_t lane_lat_optim_mask;
 636
 637         /* Panel fitter controls for gen2-gen4 + VLV */
 638         struct {
 639                 u32 control;
 640                 u32 pgm_ratios;
 641                 u32 lvds_border_bits;
 642         } gmch_pfit;
 643
 644         /* Panel fitter placement and size for Ironlake+ */
 645         struct {
 646                 u32 pos;
 647                 u32 size;
 648                 bool enabled;
 649                 bool force_thru;
 650         } pch_pfit;
 651
 652         /* FDI configuration, only valid if has_pch_encoder is set. */
 653         int fdi_lanes;
 654         struct intel_link_m_n fdi_m_n;
 655
 656         bool ips_enabled;
 657
 658         bool enable_fbc;
 659
 660         bool double_wide;
 661
 662         int pbn;
 663
 664         struct intel_crtc_scaler_state scaler_state;
 665
 666         /* w/a for waiting 2 vblanks during crtc enable */
 667         enum pipe hsw_workaround_pipe;
 668
 669         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 670         bool disable_lp_wm;
 671
 672         struct intel_crtc_wm_state wm;
 673
 674         /* Gamma mode programmed on the pipe */
 675         uint32_t gamma_mode;
 676 };
 677
 678 struct vlv_wm_state {
 679         struct vlv_pipe_wm wm[3];
 680         struct vlv_sr_wm sr[3];
 681         uint8_t num_active_planes;
 682         uint8_t num_levels;
 683         uint8_t level;
 684         bool cxsr;
 685 };
 686
 687 struct intel_crtc {
 688         struct drm_crtc base;
 689         enum pipe pipe;
 690         enum plane plane;
 691         u8 lut_r[256], lut_g[256], lut_b[256];
 692         /*
 693          * Whether the crtc and the connected output pipeline is active. Implies
 694          * that crtc->enabled is set, i.e. the current mode configuration has
 695          * some outputs connected to this crtc.
 696          */
 697         bool active;
 698         bool lowfreq_avail;
 699         u8 plane_ids_mask;
 700         unsigned long enabled_power_domains;
 701         struct intel_overlay *overlay;
 702         struct intel_flip_work *flip_work;
 703
 704         atomic_t unpin_work_count;
 705
 706         /* Display surface base address adjustement for pageflips. Note that on
 707          * gen4+ this only adjusts up to a tile, offsets within a tile are
 708          * handled in the hw itself (with the TILEOFF register). */
 709         u32 dspaddr_offset;
 710         int adjusted_x;
 711         int adjusted_y;
 712
 713         uint32_t cursor_addr;
 714         uint32_t cursor_cntl;
 715         uint32_t cursor_size;
 716         uint32_t cursor_base;
 717
 718         struct intel_crtc_state *config;
 719
 720         /* global reset count when the last flip was submitted */
 721         unsigned int reset_count;
 722
 723         /* Access to these should be protected by dev_priv->irq_lock. */
 724         bool cpu_fifo_underrun_disabled;
 725         bool pch_fifo_underrun_disabled;
 726
 727         /* per-pipe watermark state */
 728         struct {
 729                 /* watermarks currently being used  */
 730                 union {
 731                         struct intel_pipe_wm ilk;
 732                 } active;
 733
 734                 /* allow CxSR on this pipe */
 735                 bool cxsr_allowed;
 736         } wm;
 737
 738         int scanline_offset;
 739
 740         struct {
 741                 unsigned start_vbl_count;
 742                 ktime_t start_vbl_time;
 743                 int min_vbl, max_vbl;
 744                 int scanline_start;
 745         } debug;
 746
 747         /* scalers available on this crtc */
 748         int num_scalers;
 749
 750         struct vlv_wm_state wm_state;
 751 };
 752
 753 struct intel_plane_wm_parameters {
 754         uint32_t horiz_pixels;
 755         uint32_t vert_pixels;
 756         /*
 757          *   For packed pixel formats:
 758          *     bytes_per_pixel - holds bytes per pixel
 759          *   For planar pixel formats:
 760          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 761          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 762          */
 763         uint8_t bytes_per_pixel;
 764         uint8_t y_bytes_per_pixel;
 765         bool enabled;
 766         bool scaled;
 767         u64 tiling;
 768         unsigned int rotation;
 769         uint16_t fifo_size;
 770 };
 771
 772 struct intel_plane {
 773         struct drm_plane base;
 774         u8 plane;
 775         enum plane_id id;
 776         enum pipe pipe;
 777         bool can_scale;
 778         int max_downscale;
 779         uint32_t frontbuffer_bit;
 780
 781         /* Since we need to change the watermarks before/after
 782          * enabling/disabling the planes, we need to store the parameters here
 783          * as the other pieces of the struct may not reflect the values we want
 784          * for the watermark calculations. Currently only Haswell uses this.
 785          */
 786         struct intel_plane_wm_parameters wm;
 787
 788         /*
 789          * NOTE: Do not place new plane state fields here (e.g., when adding
 790          * new plane properties).  New runtime state should now be placed in
 791          * the intel_plane_state structure and accessed via plane_state.
 792          */
 793
 794         void (*update_plane)(struct drm_plane *plane,
 795                              const struct intel_crtc_state *crtc_state,
 796                              const struct intel_plane_state *plane_state);
 797         void (*disable_plane)(struct drm_plane *plane,
 798                               struct drm_crtc *crtc);
 799         int (*check_plane)(struct drm_plane *plane,
 800                            struct intel_crtc_state *crtc_state,
 801                            struct intel_plane_state *state);
 802 };
 803
 804 struct intel_watermark_params {
 805         u16 fifo_size;
 806         u16 max_wm;
 807         u8 default_wm;
 808         u8 guard_size;
 809         u8 cacheline_size;
 810 };
 811
 812 struct cxsr_latency {
 813         bool is_desktop : 1;
 814         bool is_ddr3 : 1;
 815         u16 fsb_freq;
 816         u16 mem_freq;
 817         u16 display_sr;
 818         u16 display_hpll_disable;
 819         u16 cursor_sr;
 820         u16 cursor_hpll_disable;
 821 };
 822
 823 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 824 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 825 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 826 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 827 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 828 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 829 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 830 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 831 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 832
 833 struct intel_hdmi {
 834         i915_reg_t hdmi_reg;
 835         int ddc_bus;
 836         struct {
 837                 enum drm_dp_dual_mode_type type;
 838                 int max_tmds_clock;
 839         } dp_dual_mode;
 840         bool limited_color_range;
 841         bool color_range_auto;
 842         bool has_hdmi_sink;
 843         bool has_audio;
 844         enum hdmi_force_audio force_audio;
 845         bool rgb_quant_range_selectable;
 846         enum hdmi_picture_aspect aspect_ratio;
 847         struct intel_connector *attached_connector;
 848         void (*write_infoframe)(struct drm_encoder *encoder,
 849                                 const struct intel_crtc_state *crtc_state,
 850                                 enum hdmi_infoframe_type type,
 851                                 const void *frame, ssize_t len);
 852         void (*set_infoframes)(struct drm_encoder *encoder,
 853                                bool enable,
 854                                const struct intel_crtc_state *crtc_state,
 855                                const struct drm_connector_state *conn_state);
 856         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 857                                   const struct intel_crtc_state *pipe_config);
 858 };
 859
 860 struct intel_dp_mst_encoder;
 861 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 862
 863 /*
 864  * enum link_m_n_set:
 865  *      When platform provides two set of M_N registers for dp, we can
 866  *      program them and switch between them incase of DRRS.
 867  *      But When only one such register is provided, we have to program the
 868  *      required divider value on that registers itself based on the DRRS state.
 869  *
 870  * M1_N1        : Program dp_m_n on M1_N1 registers
 871  *                        dp_m2_n2 on M2_N2 registers (If supported)
 872  *
 873  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 874  *                        M2_N2 registers are not supported
 875  */
 876
 877 enum link_m_n_set {
 878         /* Sets the m1_n1 and m2_n2 */
 879         M1_N1 = 0,
 880         M2_N2
 881 };
 882
 883 struct intel_dp_desc {
 884         u8 oui[3];
 885         u8 device_id[6];
 886         u8 hw_rev;
 887         u8 sw_major_rev;
 888         u8 sw_minor_rev;
 889 } __packed;
 890
 891 struct intel_dp_compliance_data {
 892         unsigned long edid;
 893 };
 894
 895 struct intel_dp_compliance {
 896         unsigned long test_type;
 897         struct intel_dp_compliance_data test_data;
 898         bool test_active;
 899 };
 900
 901 struct intel_dp {
 902         i915_reg_t output_reg;
 903         i915_reg_t aux_ch_ctl_reg;
 904         i915_reg_t aux_ch_data_reg[5];
 905         uint32_t DP;
 906         int link_rate;
 907         uint8_t lane_count;
 908         uint8_t sink_count;
 909         bool link_mst;
 910         bool has_audio;
 911         bool detect_done;
 912         bool channel_eq_status;
 913         enum hdmi_force_audio force_audio;
 914         bool limited_color_range;
 915         bool color_range_auto;
 916         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 917         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 918         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 919         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 920         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 921         uint8_t num_sink_rates;
 922         int sink_rates[DP_MAX_SUPPORTED_RATES];
 923         /* Max lane count for the sink as per DPCD registers */
 924         uint8_t max_sink_lane_count;
 925         /* Max link BW for the sink as per DPCD registers */
 926         int max_sink_link_bw;
 927         /* sink or branch descriptor */
 928         struct intel_dp_desc desc;
 929         struct drm_dp_aux aux;
 930         uint8_t train_set[4];
 931         int panel_power_up_delay;
 932         int panel_power_down_delay;
 933         int panel_power_cycle_delay;
 934         int backlight_on_delay;
 935         int backlight_off_delay;
 936         struct delayed_work panel_vdd_work;
 937         bool want_panel_vdd;
 938         unsigned long last_power_on;
 939         unsigned long last_backlight_off;
 940         ktime_t panel_power_off_time;
 941
 942         struct notifier_block edp_notifier;
 943
 944         /*
 945          * Pipe whose power sequencer is currently locked into
 946          * this port. Only relevant on VLV/CHV.
 947          */
 948         enum pipe pps_pipe;
 949         /*
 950          * Pipe currently driving the port. Used for preventing
 951          * the use of the PPS for any pipe currentrly driving
 952          * external DP as that will mess things up on VLV.
 953          */
 954         enum pipe active_pipe;
 955         /*
 956          * Set if the sequencer may be reset due to a power transition,
 957          * requiring a reinitialization. Only relevant on BXT.
 958          */
 959         bool pps_reset;
 960         struct edp_power_seq pps_delays;
 961
 962         bool can_mst; /* this port supports mst */
 963         bool is_mst;
 964         int active_mst_links;
 965         /* connector directly attached - won't be use for modeset in mst world */
 966         struct intel_connector *attached_connector;
 967
 968         /* mst connector list */
 969         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 970         struct drm_dp_mst_topology_mgr mst_mgr;
 971
 972         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 973         /*
 974          * This function returns the value we have to program the AUX_CTL
 975          * register with to kick off an AUX transaction.
 976          */
 977         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 978                                      bool has_aux_irq,
 979                                      int send_bytes,
 980                                      uint32_t aux_clock_divider);
 981
 982         /* This is called before a link training is starterd */
 983         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 984
 985         /* Displayport compliance testing */
 986         struct intel_dp_compliance compliance;
 987 };
 988
 989 struct intel_lspcon {
 990         bool active;
 991         enum drm_lspcon_mode mode;
 992         bool desc_valid;
 993 };
 994
 995 struct intel_digital_port {
 996         struct intel_encoder base;
 997         enum port port;
 998         u32 saved_port_bits;
 999         struct intel_dp dp;
1000         struct intel_hdmi hdmi;
1001         struct intel_lspcon lspcon;
1002         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1003         bool release_cl2_override;
1004         uint8_t max_lanes;
1005 };
1006
1007 struct intel_dp_mst_encoder {
1008         struct intel_encoder base;
1009         enum pipe pipe;
1010         struct intel_digital_port *primary;
1011         struct intel_connector *connector;
1012 };
1013
1014 static inline enum dpio_channel
1015 vlv_dport_to_channel(struct intel_digital_port *dport)
1016 {
1017         switch (dport->port) {
1018         case PORT_B:
1019         case PORT_D:
1020                 return DPIO_CH0;
1021         case PORT_C:
1022                 return DPIO_CH1;
1023         default:
1024                 BUG();
1025         }
1026 }
1027
1028 static inline enum dpio_phy
1029 vlv_dport_to_phy(struct intel_digital_port *dport)
1030 {
1031         switch (dport->port) {
1032         case PORT_B:
1033         case PORT_C:
1034                 return DPIO_PHY0;
1035         case PORT_D:
1036                 return DPIO_PHY1;
1037         default:
1038                 BUG();
1039         }
1040 }
1041
1042 static inline enum dpio_channel
1043 vlv_pipe_to_channel(enum pipe pipe)
1044 {
1045         switch (pipe) {
1046         case PIPE_A:
1047         case PIPE_C:
1048                 return DPIO_CH0;
1049         case PIPE_B:
1050                 return DPIO_CH1;
1051         default:
1052                 BUG();
1053         }
1054 }
1055
1056 static inline struct intel_crtc *
1057 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1058 {
1059         return dev_priv->pipe_to_crtc_mapping[pipe];
1060 }
1061
1062 static inline struct intel_crtc *
1063 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1064 {
1065         return dev_priv->plane_to_crtc_mapping[plane];
1066 }
1067
1068 struct intel_flip_work {
1069         struct work_struct unpin_work;
1070         struct work_struct mmio_work;
1071
1072         struct drm_crtc *crtc;
1073         struct i915_vma *old_vma;
1074         struct drm_framebuffer *old_fb;
1075         struct drm_i915_gem_object *pending_flip_obj;
1076         struct drm_pending_vblank_event *event;
1077         atomic_t pending;
1078         u32 flip_count;
1079         u32 gtt_offset;
1080         struct drm_i915_gem_request *flip_queued_req;
1081         u32 flip_queued_vblank;
1082         u32 flip_ready_vblank;
1083         unsigned int rotation;
1084 };
1085
1086 struct intel_load_detect_pipe {
1087         struct drm_atomic_state *restore_state;
1088 };
1089
1090 static inline struct intel_encoder *
1091 intel_attached_encoder(struct drm_connector *connector)
1092 {
1093         return to_intel_connector(connector)->encoder;
1094 }
1095
1096 static inline struct intel_digital_port *
1097 enc_to_dig_port(struct drm_encoder *encoder)
1098 {
1099         return container_of(encoder, struct intel_digital_port, base.base);
1100 }
1101
1102 static inline struct intel_dp_mst_encoder *
1103 enc_to_mst(struct drm_encoder *encoder)
1104 {
1105         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1106 }
1107
1108 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1109 {
1110         return &enc_to_dig_port(encoder)->dp;
1111 }
1112
1113 static inline struct intel_digital_port *
1114 dp_to_dig_port(struct intel_dp *intel_dp)
1115 {
1116         return container_of(intel_dp, struct intel_digital_port, dp);
1117 }
1118
1119 static inline struct intel_lspcon *
1120 dp_to_lspcon(struct intel_dp *intel_dp)
1121 {
1122         return &dp_to_dig_port(intel_dp)->lspcon;
1123 }
1124
1125 static inline struct intel_digital_port *
1126 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1127 {
1128         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1129 }
1130
1131 /* intel_fifo_underrun.c */
1132 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1133                                            enum pipe pipe, bool enable);
1134 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1135                                            enum transcoder pch_transcoder,
1136                                            bool enable);
1137 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1138                                          enum pipe pipe);
1139 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1140                                          enum transcoder pch_transcoder);
1141 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1142 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1143
1144 /* i915_irq.c */
1145 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1146 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1147 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1148 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1149 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1150 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1151 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1152 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1153 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1154 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1155 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1156 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1157 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1158 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1159 {
1160         /*
1161          * We only use drm_irq_uninstall() at unload and VT switch, so
1162          * this is the only thing we need to check.
1163          */
1164         return dev_priv->pm.irqs_enabled;
1165 }
1166
1167 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1168 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1169                                      unsigned int pipe_mask);
1170 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1171                                      unsigned int pipe_mask);
1172 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1173 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1174 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1175
1176 /* intel_crt.c */
1177 void intel_crt_init(struct drm_i915_private *dev_priv);
1178 void intel_crt_reset(struct drm_encoder *encoder);
1179
1180 /* intel_ddi.c */
1181 void intel_ddi_clk_select(struct intel_encoder *encoder,
1182                           struct intel_shared_dpll *pll);
1183 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1184                                 struct intel_crtc_state *old_crtc_state,
1185                                 struct drm_connector_state *old_conn_state);
1186 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1187 void hsw_fdi_link_train(struct drm_crtc *crtc);
1188 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1189 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1190 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1191 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1192 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1193                                        enum transcoder cpu_transcoder);
1194 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1195 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1196 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1197                           struct intel_crtc_state *crtc_state);
1198 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1199 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1200 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1201 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1202                                  struct intel_crtc *intel_crtc);
1203 void intel_ddi_get_config(struct intel_encoder *encoder,
1204                           struct intel_crtc_state *pipe_config);
1205 struct intel_encoder *
1206 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1207
1208 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1209 void intel_ddi_clock_get(struct intel_encoder *encoder,
1210                          struct intel_crtc_state *pipe_config);
1211 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1212 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1213 struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
1214                                                   int clock);
1215 unsigned int intel_fb_align_height(struct drm_device *dev,
1216                                    unsigned int height,
1217                                    uint32_t pixel_format,
1218                                    uint64_t fb_format_modifier);
1219 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1220                               uint64_t fb_modifier, uint32_t pixel_format);
1221
1222 /* intel_audio.c */
1223 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1224 void intel_audio_codec_enable(struct intel_encoder *encoder,
1225                               const struct intel_crtc_state *crtc_state,
1226                               const struct drm_connector_state *conn_state);
1227 void intel_audio_codec_disable(struct intel_encoder *encoder);
1228 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1229 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1230 void intel_audio_init(struct drm_i915_private *dev_priv);
1231 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1232
1233 /* intel_display.c */
1234 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1235 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1236 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1237 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1238                       const char *name, u32 reg, int ref_freq);
1239 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1240 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1241 extern const struct drm_plane_funcs intel_plane_funcs;
1242 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1243 unsigned int intel_fb_xy_to_linear(int x, int y,
1244                                    const struct intel_plane_state *state,
1245                                    int plane);
1246 void intel_add_fb_offsets(int *x, int *y,
1247                           const struct intel_plane_state *state, int plane);
1248 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1249 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1250 void intel_mark_busy(struct drm_i915_private *dev_priv);
1251 void intel_mark_idle(struct drm_i915_private *dev_priv);
1252 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1253 int intel_display_suspend(struct drm_device *dev);
1254 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1255 void intel_encoder_destroy(struct drm_encoder *encoder);
1256 int intel_connector_init(struct intel_connector *);
1257 struct intel_connector *intel_connector_alloc(void);
1258 bool intel_connector_get_hw_state(struct intel_connector *connector);
1259 void intel_connector_attach_encoder(struct intel_connector *connector,
1260                                     struct intel_encoder *encoder);
1261 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1262                                              struct drm_crtc *crtc);
1263 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1264 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1265                                 struct drm_file *file_priv);
1266 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1267                                              enum pipe pipe);
1268 static inline bool
1269 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1270                     enum intel_output_type type)
1271 {
1272         return crtc_state->output_types & (1 << type);
1273 }
1274 static inline bool
1275 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1276 {
1277         return crtc_state->output_types &
1278                 ((1 << INTEL_OUTPUT_DP) |
1279                  (1 << INTEL_OUTPUT_DP_MST) |
1280                  (1 << INTEL_OUTPUT_EDP));
1281 }
1282 static inline void
1283 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1284 {
1285         drm_wait_one_vblank(&dev_priv->drm, pipe);
1286 }
1287 static inline void
1288 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1289 {
1290         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1291
1292         if (crtc->active)
1293                 intel_wait_for_vblank(dev_priv, pipe);
1294 }
1295
1296 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1297
1298 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1299 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1300                          struct intel_digital_port *dport,
1301                          unsigned int expected_mask);
1302 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1303                                 struct drm_display_mode *mode,
1304                                 struct intel_load_detect_pipe *old,
1305                                 struct drm_modeset_acquire_ctx *ctx);
1306 void intel_release_load_detect_pipe(struct drm_connector *connector,
1307                                     struct intel_load_detect_pipe *old,
1308                                     struct drm_modeset_acquire_ctx *ctx);
1309 struct i915_vma *
1310 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1311 void intel_unpin_fb_vma(struct i915_vma *vma);
1312 struct drm_framebuffer *
1313 __intel_framebuffer_create(struct drm_device *dev,
1314                            struct drm_mode_fb_cmd2 *mode_cmd,
1315                            struct drm_i915_gem_object *obj);
1316 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1317 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1318 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1319 int intel_prepare_plane_fb(struct drm_plane *plane,
1320                            struct drm_plane_state *new_state);
1321 void intel_cleanup_plane_fb(struct drm_plane *plane,
1322                             struct drm_plane_state *old_state);
1323 int intel_plane_atomic_get_property(struct drm_plane *plane,
1324                                     const struct drm_plane_state *state,
1325                                     struct drm_property *property,
1326                                     uint64_t *val);
1327 int intel_plane_atomic_set_property(struct drm_plane *plane,
1328                                     struct drm_plane_state *state,
1329                                     struct drm_property *property,
1330                                     uint64_t val);
1331 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1332                                     struct drm_plane_state *plane_state);
1333
1334 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1335                                uint64_t fb_modifier, unsigned int cpp);
1336
1337 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1338                                     enum pipe pipe);
1339
1340 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1341                      const struct dpll *dpll);
1342 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1343 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1344
1345 /* modesetting asserts */
1346 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1347                            enum pipe pipe);
1348 void assert_pll(struct drm_i915_private *dev_priv,
1349                 enum pipe pipe, bool state);
1350 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1351 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1352 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1353 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1354 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1355 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1356                        enum pipe pipe, bool state);
1357 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1358 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1359 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1360 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1361 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1362 u32 intel_compute_tile_offset(int *x, int *y,
1363                               const struct intel_plane_state *state, int plane);
1364 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1365 void intel_finish_reset(struct drm_i915_private *dev_priv);
1366 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1367 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1368 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1369 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1370 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1371 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1372 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1373 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1374 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1375 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1376 unsigned int skl_cdclk_get_vco(unsigned int freq);
1377 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1378 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1379 void intel_dp_get_m_n(struct intel_crtc *crtc,
1380                       struct intel_crtc_state *pipe_config);
1381 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1382 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1383 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1384                         struct dpll *best_clock);
1385 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1386
1387 bool intel_crtc_active(struct intel_crtc *crtc);
1388 void hsw_enable_ips(struct intel_crtc *crtc);
1389 void hsw_disable_ips(struct intel_crtc *crtc);
1390 enum intel_display_power_domain
1391 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1392 enum intel_display_power_domain
1393 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1394 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1395                                  struct intel_crtc_state *pipe_config);
1396
1397 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1398 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1399
1400 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1401 {
1402         return i915_ggtt_offset(state->vma);
1403 }
1404
1405 u32 skl_plane_ctl_format(uint32_t pixel_format);
1406 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1407 u32 skl_plane_ctl_rotation(unsigned int rotation);
1408 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1409                      unsigned int rotation);
1410 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1411
1412 /* intel_csr.c */
1413 void intel_csr_ucode_init(struct drm_i915_private *);
1414 void intel_csr_load_program(struct drm_i915_private *);
1415 void intel_csr_ucode_fini(struct drm_i915_private *);
1416 void intel_csr_ucode_suspend(struct drm_i915_private *);
1417 void intel_csr_ucode_resume(struct drm_i915_private *);
1418
1419 /* intel_dp.c */
1420 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1421                    enum port port);
1422 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1423                              struct intel_connector *intel_connector);
1424 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1425                               int link_rate, uint8_t lane_count,
1426                               bool link_mst);
1427 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1428                                             int link_rate, uint8_t lane_count);
1429 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1430 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1431 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1432 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1433 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1434 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1435 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1436 bool intel_dp_compute_config(struct intel_encoder *encoder,
1437                              struct intel_crtc_state *pipe_config,
1438                              struct drm_connector_state *conn_state);
1439 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1440 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1441                                   bool long_hpd);
1442 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1443 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1444 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1445 void intel_edp_panel_on(struct intel_dp *intel_dp);
1446 void intel_edp_panel_off(struct intel_dp *intel_dp);
1447 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1448 void intel_dp_mst_suspend(struct drm_device *dev);
1449 void intel_dp_mst_resume(struct drm_device *dev);
1450 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1451 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1452 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1453 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1454 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1455 void intel_plane_destroy(struct drm_plane *plane);
1456 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1457                            struct intel_crtc_state *crtc_state);
1458 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1459                            struct intel_crtc_state *crtc_state);
1460 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1461                                unsigned int frontbuffer_bits);
1462 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1463                           unsigned int frontbuffer_bits);
1464
1465 void
1466 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1467                                        uint8_t dp_train_pat);
1468 void
1469 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1470 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1471 uint8_t
1472 intel_dp_voltage_max(struct intel_dp *intel_dp);
1473 uint8_t
1474 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1475 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1476                            uint8_t *link_bw, uint8_t *rate_select);
1477 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1478 bool
1479 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1480
1481 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1482 {
1483         return ~((1 << lane_count) - 1) & 0xf;
1484 }
1485
1486 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1487 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1488                           struct intel_dp_desc *desc);
1489 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1490 int intel_dp_link_required(int pixel_clock, int bpp);
1491 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1492 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1493                                   struct intel_digital_port *port);
1494
1495 /* intel_dp_aux_backlight.c */
1496 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1497
1498 /* intel_dp_mst.c */
1499 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1500 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1501 /* intel_dsi.c */
1502 void intel_dsi_init(struct drm_i915_private *dev_priv);
1503
1504 /* intel_dsi_dcs_backlight.c */
1505 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1506
1507 /* intel_dvo.c */
1508 void intel_dvo_init(struct drm_i915_private *dev_priv);
1509 /* intel_hotplug.c */
1510 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1511
1512
1513 /* legacy fbdev emulation in intel_fbdev.c */
1514 #ifdef CONFIG_DRM_FBDEV_EMULATION
1515 extern int intel_fbdev_init(struct drm_device *dev);
1516 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1517 extern void intel_fbdev_fini(struct drm_device *dev);
1518 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1519 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1520 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1521 #else
1522 static inline int intel_fbdev_init(struct drm_device *dev)
1523 {
1524         return 0;
1525 }
1526
1527 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1528 {
1529 }
1530
1531 static inline void intel_fbdev_fini(struct drm_device *dev)
1532 {
1533 }
1534
1535 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1536 {
1537 }
1538
1539 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1540 {
1541 }
1542
1543 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1544 {
1545 }
1546 #endif
1547
1548 /* intel_fbc.c */
1549 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1550                            struct drm_atomic_state *state);
1551 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1552 void intel_fbc_pre_update(struct intel_crtc *crtc,
1553                           struct intel_crtc_state *crtc_state,
1554                           struct intel_plane_state *plane_state);
1555 void intel_fbc_post_update(struct intel_crtc *crtc);
1556 void intel_fbc_init(struct drm_i915_private *dev_priv);
1557 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1558 void intel_fbc_enable(struct intel_crtc *crtc,
1559                       struct intel_crtc_state *crtc_state,
1560                       struct intel_plane_state *plane_state);
1561 void intel_fbc_disable(struct intel_crtc *crtc);
1562 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1563 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1564                           unsigned int frontbuffer_bits,
1565                           enum fb_op_origin origin);
1566 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1567                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1568 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1569 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1570
1571 /* intel_hdmi.c */
1572 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1573                      enum port port);
1574 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1575                                struct intel_connector *intel_connector);
1576 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1577 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1578                                struct intel_crtc_state *pipe_config,
1579                                struct drm_connector_state *conn_state);
1580 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1581
1582
1583 /* intel_lvds.c */
1584 void intel_lvds_init(struct drm_i915_private *dev_priv);
1585 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1586 bool intel_is_dual_link_lvds(struct drm_device *dev);
1587
1588
1589 /* intel_modes.c */
1590 int intel_connector_update_modes(struct drm_connector *connector,
1591                                  struct edid *edid);
1592 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1593 void intel_attach_force_audio_property(struct drm_connector *connector);
1594 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1595 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1596
1597
1598 /* intel_overlay.c */
1599 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1600 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1601 int intel_overlay_switch_off(struct intel_overlay *overlay);
1602 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1603                                   struct drm_file *file_priv);
1604 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1605                               struct drm_file *file_priv);
1606 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1607
1608
1609 /* intel_panel.c */
1610 int intel_panel_init(struct intel_panel *panel,
1611                      struct drm_display_mode *fixed_mode,
1612                      struct drm_display_mode *downclock_mode);
1613 void intel_panel_fini(struct intel_panel *panel);
1614 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1615                             struct drm_display_mode *adjusted_mode);
1616 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1617                              struct intel_crtc_state *pipe_config,
1618                              int fitting_mode);
1619 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1620                               struct intel_crtc_state *pipe_config,
1621                               int fitting_mode);
1622 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1623                                     u32 level, u32 max);
1624 int intel_panel_setup_backlight(struct drm_connector *connector,
1625                                 enum pipe pipe);
1626 void intel_panel_enable_backlight(struct intel_connector *connector);
1627 void intel_panel_disable_backlight(struct intel_connector *connector);
1628 void intel_panel_destroy_backlight(struct drm_connector *connector);
1629 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1630 extern struct drm_display_mode *intel_find_panel_downclock(
1631                                 struct drm_i915_private *dev_priv,
1632                                 struct drm_display_mode *fixed_mode,
1633                                 struct drm_connector *connector);
1634
1635 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1636 int intel_backlight_device_register(struct intel_connector *connector);
1637 void intel_backlight_device_unregister(struct intel_connector *connector);
1638 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1639 static int intel_backlight_device_register(struct intel_connector *connector)
1640 {
1641         return 0;
1642 }
1643 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1644 {
1645 }
1646 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1647
1648
1649 /* intel_psr.c */
1650 void intel_psr_enable(struct intel_dp *intel_dp);
1651 void intel_psr_disable(struct intel_dp *intel_dp);
1652 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1653                           unsigned frontbuffer_bits);
1654 void intel_psr_flush(struct drm_i915_private *dev_priv,
1655                      unsigned frontbuffer_bits,
1656                      enum fb_op_origin origin);
1657 void intel_psr_init(struct drm_i915_private *dev_priv);
1658 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1659                                    unsigned frontbuffer_bits);
1660
1661 /* intel_runtime_pm.c */
1662 int intel_power_domains_init(struct drm_i915_private *);
1663 void intel_power_domains_fini(struct drm_i915_private *);
1664 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1665 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1666 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1667 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1668 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1669 const char *
1670 intel_display_power_domain_str(enum intel_display_power_domain domain);
1671
1672 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1673                                     enum intel_display_power_domain domain);
1674 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1675                                       enum intel_display_power_domain domain);
1676 void intel_display_power_get(struct drm_i915_private *dev_priv,
1677                              enum intel_display_power_domain domain);
1678 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1679                                         enum intel_display_power_domain domain);
1680 void intel_display_power_put(struct drm_i915_private *dev_priv,
1681                              enum intel_display_power_domain domain);
1682
1683 static inline void
1684 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1685 {
1686         WARN_ONCE(dev_priv->pm.suspended,
1687                   "Device suspended during HW access\n");
1688 }
1689
1690 static inline void
1691 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1692 {
1693         assert_rpm_device_not_suspended(dev_priv);
1694         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1695          * too much noise. */
1696         if (!atomic_read(&dev_priv->pm.wakeref_count))
1697                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1698 }
1699
1700 /**
1701  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1702  * @dev_priv: i915 device instance
1703  *
1704  * This function disable asserts that check if we hold an RPM wakelock
1705  * reference, while keeping the device-not-suspended checks still enabled.
1706  * It's meant to be used only in special circumstances where our rule about
1707  * the wakelock refcount wrt. the device power state doesn't hold. According
1708  * to this rule at any point where we access the HW or want to keep the HW in
1709  * an active state we must hold an RPM wakelock reference acquired via one of
1710  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1711  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1712  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1713  * users should avoid using this function.
1714  *
1715  * Any calls to this function must have a symmetric call to
1716  * enable_rpm_wakeref_asserts().
1717  */
1718 static inline void
1719 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1720 {
1721         atomic_inc(&dev_priv->pm.wakeref_count);
1722 }
1723
1724 /**
1725  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1726  * @dev_priv: i915 device instance
1727  *
1728  * This function re-enables the RPM assert checks after disabling them with
1729  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1730  * circumstances otherwise its use should be avoided.
1731  *
1732  * Any calls to this function must have a symmetric call to
1733  * disable_rpm_wakeref_asserts().
1734  */
1735 static inline void
1736 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1737 {
1738         atomic_dec(&dev_priv->pm.wakeref_count);
1739 }
1740
1741 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1742 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1743 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1744 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1745
1746 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1747
1748 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1749                              bool override, unsigned int mask);
1750 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1751                           enum dpio_channel ch, bool override);
1752
1753
1754 /* intel_pm.c */
1755 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1756 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1757 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1758 void intel_update_watermarks(struct intel_crtc *crtc);
1759 void intel_init_pm(struct drm_i915_private *dev_priv);
1760 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1761 void intel_pm_setup(struct drm_i915_private *dev_priv);
1762 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1763 void intel_gpu_ips_teardown(void);
1764 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1765 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1766 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1767 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1768 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1769 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1770 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1771 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1772 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1773 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1774 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1775                     struct intel_rps_client *rps,
1776                     unsigned long submitted);
1777 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1778 void vlv_wm_get_hw_state(struct drm_device *dev);
1779 void ilk_wm_get_hw_state(struct drm_device *dev);
1780 void skl_wm_get_hw_state(struct drm_device *dev);
1781 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1782                           struct skl_ddb_allocation *ddb /* out */);
1783 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1784                               struct skl_pipe_wm *out);
1785 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1786 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1787 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1788 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1789                          const struct skl_wm_level *l2);
1790 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1791                                  const struct skl_ddb_entry *ddb,
1792                                  int ignore);
1793 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1794 bool ilk_disable_lp_wm(struct drm_device *dev);
1795 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1796 static inline int intel_enable_rc6(void)
1797 {
1798         return i915.enable_rc6;
1799 }
1800
1801 /* intel_sdvo.c */
1802 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1803                      i915_reg_t reg, enum port port);
1804
1805
1806 /* intel_sprite.c */
1807 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1808                              int usecs);
1809 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1810                                               enum pipe pipe, int plane);
1811 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1812                               struct drm_file *file_priv);
1813 void intel_pipe_update_start(struct intel_crtc *crtc);
1814 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1815
1816 /* intel_tv.c */
1817 void intel_tv_init(struct drm_i915_private *dev_priv);
1818
1819 /* intel_atomic.c */
1820 int intel_connector_atomic_get_property(struct drm_connector *connector,
1821                                         const struct drm_connector_state *state,
1822                                         struct drm_property *property,
1823                                         uint64_t *val);
1824 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1825 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1826                                struct drm_crtc_state *state);
1827 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1828 void intel_atomic_state_clear(struct drm_atomic_state *);
1829
1830 static inline struct intel_crtc_state *
1831 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1832                             struct intel_crtc *crtc)
1833 {
1834         struct drm_crtc_state *crtc_state;
1835         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1836         if (IS_ERR(crtc_state))
1837                 return ERR_CAST(crtc_state);
1838
1839         return to_intel_crtc_state(crtc_state);
1840 }
1841
1842 static inline struct intel_crtc_state *
1843 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1844                                      struct intel_crtc *crtc)
1845 {
1846         struct drm_crtc_state *crtc_state;
1847
1848         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1849
1850         if (crtc_state)
1851                 return to_intel_crtc_state(crtc_state);
1852         else
1853                 return NULL;
1854 }
1855
1856 static inline struct intel_plane_state *
1857 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1858                                       struct intel_plane *plane)
1859 {
1860         struct drm_plane_state *plane_state;
1861
1862         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1863
1864         return to_intel_plane_state(plane_state);
1865 }
1866
1867 int intel_atomic_setup_scalers(struct drm_device *dev,
1868         struct intel_crtc *intel_crtc,
1869         struct intel_crtc_state *crtc_state);
1870
1871 /* intel_atomic_plane.c */
1872 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1873 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1874 void intel_plane_destroy_state(struct drm_plane *plane,
1875                                struct drm_plane_state *state);
1876 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1877 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1878                                         struct intel_plane_state *intel_state);
1879
1880 /* intel_color.c */
1881 void intel_color_init(struct drm_crtc *crtc);
1882 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1883 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1884 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1885
1886 /* intel_lspcon.c */
1887 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1888 void lspcon_resume(struct intel_lspcon *lspcon);
1889 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
1890
1891 /* intel_pipe_crc.c */
1892 int intel_pipe_crc_create(struct drm_minor *minor);
1893 void intel_pipe_crc_cleanup(struct drm_minor *minor);
1894 #ifdef CONFIG_DEBUG_FS
1895 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
1896                               size_t *values_cnt);
1897 #else
1898 #define intel_crtc_set_crc_source NULL
1899 #endif
1900 extern const struct file_operations i915_display_crc_ctl_fops;
1901 #endif /* __INTEL_DRV_H__ */