drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * __wait_for - magic wait macro
  45  *
  46  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  47  * important that we check the condition again after having timed out, since the
  48  * timeout could be due to preemption or similar and we've never had a chance to
  49  * check the condition before the timeout.
  50  */
  51 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  52         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  53         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  54         int ret__;                                                      \
  55         might_sleep();                                                  \
  56         for (;;) {                                                      \
  57                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  58                 OP;                                                     \
  59                 /* Guarantee COND check prior to timeout */             \
  60                 barrier();                                              \
  61                 if (COND) {                                             \
  62                         ret__ = 0;                                      \
  63                         break;                                          \
  64                 }                                                       \
  65                 if (expired__) {                                        \
  66                         ret__ = -ETIMEDOUT;                             \
  67                         break;                                          \
  68                 }                                                       \
  69                 usleep_range(wait__, wait__ * 2);                       \
  70                 if (wait__ < (Wmax))                                    \
  71                         wait__ <<= 1;                                   \
  72         }                                                               \
  73         ret__;                                                          \
  74 })
  75
  76 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  77                                                    (Wmax))
  78 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  79
  80 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  81 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  82 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  83 #else
  84 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  85 #endif
  86
  87 #define _wait_for_atomic(COND, US, ATOMIC) \
  88 ({ \
  89         int cpu, ret, timeout = (US) * 1000; \
  90         u64 base; \
  91         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  92         if (!(ATOMIC)) { \
  93                 preempt_disable(); \
  94                 cpu = smp_processor_id(); \
  95         } \
  96         base = local_clock(); \
  97         for (;;) { \
  98                 u64 now = local_clock(); \
  99                 if (!(ATOMIC)) \
 100                         preempt_enable(); \
 101                 /* Guarantee COND check prior to timeout */ \
 102                 barrier(); \
 103                 if (COND) { \
 104                         ret = 0; \
 105                         break; \
 106                 } \
 107                 if (now - base >= timeout) { \
 108                         ret = -ETIMEDOUT; \
 109                         break; \
 110                 } \
 111                 cpu_relax(); \
 112                 if (!(ATOMIC)) { \
 113                         preempt_disable(); \
 114                         if (unlikely(cpu != smp_processor_id())) { \
 115                                 timeout -= now - base; \
 116                                 cpu = smp_processor_id(); \
 117                                 base = local_clock(); \
 118                         } \
 119                 } \
 120         } \
 121         ret; \
 122 })
 123
 124 #define wait_for_us(COND, US) \
 125 ({ \
 126         int ret__; \
 127         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 128         if ((US) > 10) \
 129                 ret__ = _wait_for((COND), (US), 10, 10); \
 130         else \
 131                 ret__ = _wait_for_atomic((COND), (US), 0); \
 132         ret__; \
 133 })
 134
 135 #define wait_for_atomic_us(COND, US) \
 136 ({ \
 137         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 138         BUILD_BUG_ON((US) > 50000); \
 139         _wait_for_atomic((COND), (US), 1); \
 140 })
 141
 142 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 143
 144 #define KHz(x) (1000 * (x))
 145 #define MHz(x) KHz(1000 * (x))
 146
 147 #define KBps(x) (1000 * (x))
 148 #define MBps(x) KBps(1000 * (x))
 149 #define GBps(x) ((u64)1000 * MBps((x)))
 150
 151 /*
 152  * Display related stuff
 153  */
 154
 155 /* store information about an Ixxx DVO */
 156 /* The i830->i865 use multiple DVOs with multiple i2cs */
 157 /* the i915, i945 have a single sDVO i2c bus - which is different */
 158 #define MAX_OUTPUTS 6
 159 /* maximum connectors per crtcs in the mode set */
 160
 161 /* Maximum cursor sizes */
 162 #define GEN2_CURSOR_WIDTH 64
 163 #define GEN2_CURSOR_HEIGHT 64
 164 #define MAX_CURSOR_WIDTH 256
 165 #define MAX_CURSOR_HEIGHT 256
 166
 167 #define INTEL_I2C_BUS_DVO 1
 168 #define INTEL_I2C_BUS_SDVO 2
 169
 170 /* these are outputs from the chip - integrated only
 171    external chips are via DVO or SDVO output */
 172 enum intel_output_type {
 173         INTEL_OUTPUT_UNUSED = 0,
 174         INTEL_OUTPUT_ANALOG = 1,
 175         INTEL_OUTPUT_DVO = 2,
 176         INTEL_OUTPUT_SDVO = 3,
 177         INTEL_OUTPUT_LVDS = 4,
 178         INTEL_OUTPUT_TVOUT = 5,
 179         INTEL_OUTPUT_HDMI = 6,
 180         INTEL_OUTPUT_DP = 7,
 181         INTEL_OUTPUT_EDP = 8,
 182         INTEL_OUTPUT_DSI = 9,
 183         INTEL_OUTPUT_DDI = 10,
 184         INTEL_OUTPUT_DP_MST = 11,
 185 };
 186
 187 #define INTEL_DVO_CHIP_NONE 0
 188 #define INTEL_DVO_CHIP_LVDS 1
 189 #define INTEL_DVO_CHIP_TMDS 2
 190 #define INTEL_DVO_CHIP_TVOUT 4
 191
 192 #define INTEL_DSI_VIDEO_MODE    0
 193 #define INTEL_DSI_COMMAND_MODE  1
 194
 195 struct intel_framebuffer {
 196         struct drm_framebuffer base;
 197         struct drm_i915_gem_object *obj;
 198         struct intel_rotation_info rot_info;
 199
 200         /* for each plane in the normal GTT view */
 201         struct {
 202                 unsigned int x, y;
 203         } normal[2];
 204         /* for each plane in the rotated GTT view */
 205         struct {
 206                 unsigned int x, y;
 207                 unsigned int pitch; /* pixels */
 208         } rotated[2];
 209 };
 210
 211 struct intel_fbdev {
 212         struct drm_fb_helper helper;
 213         struct intel_framebuffer *fb;
 214         struct i915_vma *vma;
 215         unsigned long vma_flags;
 216         async_cookie_t cookie;
 217         int preferred_bpp;
 218 };
 219
 220 struct intel_encoder {
 221         struct drm_encoder base;
 222
 223         enum intel_output_type type;
 224         enum port port;
 225         unsigned int cloneable;
 226         bool (*hotplug)(struct intel_encoder *encoder,
 227                         struct intel_connector *connector);
 228         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 229                                                       struct intel_crtc_state *,
 230                                                       struct drm_connector_state *);
 231         bool (*compute_config)(struct intel_encoder *,
 232                                struct intel_crtc_state *,
 233                                struct drm_connector_state *);
 234         void (*pre_pll_enable)(struct intel_encoder *,
 235                                const struct intel_crtc_state *,
 236                                const struct drm_connector_state *);
 237         void (*pre_enable)(struct intel_encoder *,
 238                            const struct intel_crtc_state *,
 239                            const struct drm_connector_state *);
 240         void (*enable)(struct intel_encoder *,
 241                        const struct intel_crtc_state *,
 242                        const struct drm_connector_state *);
 243         void (*disable)(struct intel_encoder *,
 244                         const struct intel_crtc_state *,
 245                         const struct drm_connector_state *);
 246         void (*post_disable)(struct intel_encoder *,
 247                              const struct intel_crtc_state *,
 248                              const struct drm_connector_state *);
 249         void (*post_pll_disable)(struct intel_encoder *,
 250                                  const struct intel_crtc_state *,
 251                                  const struct drm_connector_state *);
 252         /* Read out the current hw state of this connector, returning true if
 253          * the encoder is active. If the encoder is enabled it also set the pipe
 254          * it is connected to in the pipe parameter. */
 255         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 256         /* Reconstructs the equivalent mode flags for the current hardware
 257          * state. This must be called _after_ display->get_pipe_config has
 258          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 259          * be set correctly before calling this function. */
 260         void (*get_config)(struct intel_encoder *,
 261                            struct intel_crtc_state *pipe_config);
 262         /* Returns a mask of power domains that need to be referenced as part
 263          * of the hardware state readout code. */
 264         u64 (*get_power_domains)(struct intel_encoder *encoder);
 265         /*
 266          * Called during system suspend after all pending requests for the
 267          * encoder are flushed (for example for DP AUX transactions) and
 268          * device interrupts are disabled.
 269          */
 270         void (*suspend)(struct intel_encoder *);
 271         int crtc_mask;
 272         enum hpd_pin hpd_pin;
 273         enum intel_display_power_domain power_domain;
 274         /* for communication with audio component; protected by av_mutex */
 275         const struct drm_connector *audio_connector;
 276 };
 277
 278 struct intel_panel {
 279         struct drm_display_mode *fixed_mode;
 280         struct drm_display_mode *downclock_mode;
 281
 282         /* backlight */
 283         struct {
 284                 bool present;
 285                 u32 level;
 286                 u32 min;
 287                 u32 max;
 288                 bool enabled;
 289                 bool combination_mode;  /* gen 2/4 only */
 290                 bool active_low_pwm;
 291                 bool alternate_pwm_increment;   /* lpt+ */
 292
 293                 /* PWM chip */
 294                 bool util_pin_active_low;       /* bxt+ */
 295                 u8 controller;          /* bxt+ only */
 296                 struct pwm_device *pwm;
 297
 298                 struct backlight_device *device;
 299
 300                 /* Connector and platform specific backlight functions */
 301                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 302                 uint32_t (*get)(struct intel_connector *connector);
 303                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 304                 void (*disable)(const struct drm_connector_state *conn_state);
 305                 void (*enable)(const struct intel_crtc_state *crtc_state,
 306                                const struct drm_connector_state *conn_state);
 307                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 308                                       uint32_t hz);
 309                 void (*power)(struct intel_connector *, bool enable);
 310         } backlight;
 311 };
 312
 313 /*
 314  * This structure serves as a translation layer between the generic HDCP code
 315  * and the bus-specific code. What that means is that HDCP over HDMI differs
 316  * from HDCP over DP, so to account for these differences, we need to
 317  * communicate with the receiver through this shim.
 318  *
 319  * For completeness, the 2 buses differ in the following ways:
 320  *      - DP AUX vs. DDC
 321  *              HDCP registers on the receiver are set via DP AUX for DP, and
 322  *              they are set via DDC for HDMI.
 323  *      - Receiver register offsets
 324  *              The offsets of the registers are different for DP vs. HDMI
 325  *      - Receiver register masks/offsets
 326  *              For instance, the ready bit for the KSV fifo is in a different
 327  *              place on DP vs HDMI
 328  *      - Receiver register names
 329  *              Seriously. In the DP spec, the 16-bit register containing
 330  *              downstream information is called BINFO, on HDMI it's called
 331  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 332  *              with a completely different definition.
 333  *      - KSV FIFO
 334  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 335  *              be read 3 keys at a time
 336  *      - Aksv output
 337  *              Since Aksv is hidden in hardware, there's different procedures
 338  *              to send it over DP AUX vs DDC
 339  */
 340 struct intel_hdcp_shim {
 341         /* Outputs the transmitter's An and Aksv values to the receiver. */
 342         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 343
 344         /* Reads the receiver's key selection vector */
 345         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 346
 347         /*
 348          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 349          * definitions are the same in the respective specs, but the names are
 350          * different. Call it BSTATUS since that's the name the HDMI spec
 351          * uses and it was there first.
 352          */
 353         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 354                             u8 *bstatus);
 355
 356         /* Determines whether a repeater is present downstream */
 357         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 358                                 bool *repeater_present);
 359
 360         /* Reads the receiver's Ri' value */
 361         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 362
 363         /* Determines if the receiver's KSV FIFO is ready for consumption */
 364         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 365                               bool *ksv_ready);
 366
 367         /* Reads the ksv fifo for num_downstream devices */
 368         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 369                              int num_downstream, u8 *ksv_fifo);
 370
 371         /* Reads a 32-bit part of V' from the receiver */
 372         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 373                                  int i, u32 *part);
 374
 375         /* Enables HDCP signalling on the port */
 376         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 377                                  bool enable);
 378
 379         /* Ensures the link is still protected */
 380         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 381
 382         /* Detects panel's hdcp capability. This is optional for HDMI. */
 383         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 384                             bool *hdcp_capable);
 385 };
 386
 387 struct intel_connector {
 388         struct drm_connector base;
 389         /*
 390          * The fixed encoder this connector is connected to.
 391          */
 392         struct intel_encoder *encoder;
 393
 394         /* ACPI device id for ACPI and driver cooperation */
 395         u32 acpi_device_id;
 396
 397         /* Reads out the current hw, returning true if the connector is enabled
 398          * and active (i.e. dpms ON state). */
 399         bool (*get_hw_state)(struct intel_connector *);
 400
 401         /* Panel info for eDP and LVDS */
 402         struct intel_panel panel;
 403
 404         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 405         struct edid *edid;
 406         struct edid *detect_edid;
 407
 408         /* since POLL and HPD connectors may use the same HPD line keep the native
 409            state of connector->polled in case hotplug storm detection changes it */
 410         u8 polled;
 411
 412         void *port; /* store this opaque as its illegal to dereference it */
 413
 414         struct intel_dp *mst_port;
 415
 416         /* Work struct to schedule a uevent on link train failure */
 417         struct work_struct modeset_retry_work;
 418
 419         const struct intel_hdcp_shim *hdcp_shim;
 420         struct mutex hdcp_mutex;
 421         uint64_t hdcp_value; /* protected by hdcp_mutex */
 422         struct delayed_work hdcp_check_work;
 423         struct work_struct hdcp_prop_work;
 424 };
 425
 426 struct intel_digital_connector_state {
 427         struct drm_connector_state base;
 428
 429         enum hdmi_force_audio force_audio;
 430         int broadcast_rgb;
 431 };
 432
 433 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 434
 435 struct dpll {
 436         /* given values */
 437         int n;
 438         int m1, m2;
 439         int p1, p2;
 440         /* derived values */
 441         int     dot;
 442         int     vco;
 443         int     m;
 444         int     p;
 445 };
 446
 447 struct intel_atomic_state {
 448         struct drm_atomic_state base;
 449
 450         struct {
 451                 /*
 452                  * Logical state of cdclk (used for all scaling, watermark,
 453                  * etc. calculations and checks). This is computed as if all
 454                  * enabled crtcs were active.
 455                  */
 456                 struct intel_cdclk_state logical;
 457
 458                 /*
 459                  * Actual state of cdclk, can be different from the logical
 460                  * state only when all crtc's are DPMS off.
 461                  */
 462                 struct intel_cdclk_state actual;
 463         } cdclk;
 464
 465         bool dpll_set, modeset;
 466
 467         /*
 468          * Does this transaction change the pipes that are active?  This mask
 469          * tracks which CRTC's have changed their active state at the end of
 470          * the transaction (not counting the temporary disable during modesets).
 471          * This mask should only be non-zero when intel_state->modeset is true,
 472          * but the converse is not necessarily true; simply changing a mode may
 473          * not flip the final active status of any CRTC's
 474          */
 475         unsigned int active_pipe_changes;
 476
 477         unsigned int active_crtcs;
 478         /* minimum acceptable cdclk for each pipe */
 479         int min_cdclk[I915_MAX_PIPES];
 480         /* minimum acceptable voltage level for each pipe */
 481         u8 min_voltage_level[I915_MAX_PIPES];
 482
 483         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 484
 485         /*
 486          * Current watermarks can't be trusted during hardware readout, so
 487          * don't bother calculating intermediate watermarks.
 488          */
 489         bool skip_intermediate_wm;
 490
 491         /* Gen9+ only */
 492         struct skl_ddb_values wm_results;
 493
 494         struct i915_sw_fence commit_ready;
 495
 496         struct llist_node freed;
 497 };
 498
 499 struct intel_plane_state {
 500         struct drm_plane_state base;
 501         struct i915_vma *vma;
 502         unsigned long flags;
 503 #define PLANE_HAS_FENCE BIT(0)
 504
 505         struct {
 506                 u32 offset;
 507                 int x, y;
 508         } main;
 509         struct {
 510                 u32 offset;
 511                 int x, y;
 512         } aux;
 513
 514         /* plane control register */
 515         u32 ctl;
 516
 517         /* plane color control register */
 518         u32 color_ctl;
 519
 520         /*
 521          * scaler_id
 522          *    = -1 : not using a scaler
 523          *    >=  0 : using a scalers
 524          *
 525          * plane requiring a scaler:
 526          *   - During check_plane, its bit is set in
 527          *     crtc_state->scaler_state.scaler_users by calling helper function
 528          *     update_scaler_plane.
 529          *   - scaler_id indicates the scaler it got assigned.
 530          *
 531          * plane doesn't require a scaler:
 532          *   - this can happen when scaling is no more required or plane simply
 533          *     got disabled.
 534          *   - During check_plane, corresponding bit is reset in
 535          *     crtc_state->scaler_state.scaler_users by calling helper function
 536          *     update_scaler_plane.
 537          */
 538         int scaler_id;
 539
 540         struct drm_intel_sprite_colorkey ckey;
 541 };
 542
 543 struct intel_initial_plane_config {
 544         struct intel_framebuffer *fb;
 545         unsigned int tiling;
 546         int size;
 547         u32 base;
 548 };
 549
 550 #define SKL_MIN_SRC_W 8
 551 #define SKL_MAX_SRC_W 4096
 552 #define SKL_MIN_SRC_H 8
 553 #define SKL_MAX_SRC_H 4096
 554 #define SKL_MIN_DST_W 8
 555 #define SKL_MAX_DST_W 4096
 556 #define SKL_MIN_DST_H 8
 557 #define SKL_MAX_DST_H 4096
 558 #define ICL_MAX_SRC_W 5120
 559 #define ICL_MAX_SRC_H 4096
 560 #define ICL_MAX_DST_W 5120
 561 #define ICL_MAX_DST_H 4096
 562 #define SKL_MIN_YUV_420_SRC_W 16
 563 #define SKL_MIN_YUV_420_SRC_H 16
 564
 565 struct intel_scaler {
 566         int in_use;
 567         uint32_t mode;
 568 };
 569
 570 struct intel_crtc_scaler_state {
 571 #define SKL_NUM_SCALERS 2
 572         struct intel_scaler scalers[SKL_NUM_SCALERS];
 573
 574         /*
 575          * scaler_users: keeps track of users requesting scalers on this crtc.
 576          *
 577          *     If a bit is set, a user is using a scaler.
 578          *     Here user can be a plane or crtc as defined below:
 579          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 580          *       bit 31    - crtc
 581          *
 582          * Instead of creating a new index to cover planes and crtc, using
 583          * existing drm_plane_index for planes which is well less than 31
 584          * planes and bit 31 for crtc. This should be fine to cover all
 585          * our platforms.
 586          *
 587          * intel_atomic_setup_scalers will setup available scalers to users
 588          * requesting scalers. It will gracefully fail if request exceeds
 589          * avilability.
 590          */
 591 #define SKL_CRTC_INDEX 31
 592         unsigned scaler_users;
 593
 594         /* scaler used by crtc for panel fitting purpose */
 595         int scaler_id;
 596 };
 597
 598 /* drm_mode->private_flags */
 599 #define I915_MODE_FLAG_INHERITED 1
 600 /* Flag to get scanline using frame time stamps */
 601 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 602
 603 struct intel_pipe_wm {
 604         struct intel_wm_level wm[5];
 605         uint32_t linetime;
 606         bool fbc_wm_enabled;
 607         bool pipe_enabled;
 608         bool sprites_enabled;
 609         bool sprites_scaled;
 610 };
 611
 612 struct skl_plane_wm {
 613         struct skl_wm_level wm[8];
 614         struct skl_wm_level uv_wm[8];
 615         struct skl_wm_level trans_wm;
 616         bool is_planar;
 617 };
 618
 619 struct skl_pipe_wm {
 620         struct skl_plane_wm planes[I915_MAX_PLANES];
 621         uint32_t linetime;
 622 };
 623
 624 enum vlv_wm_level {
 625         VLV_WM_LEVEL_PM2,
 626         VLV_WM_LEVEL_PM5,
 627         VLV_WM_LEVEL_DDR_DVFS,
 628         NUM_VLV_WM_LEVELS,
 629 };
 630
 631 struct vlv_wm_state {
 632         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 633         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 634         uint8_t num_levels;
 635         bool cxsr;
 636 };
 637
 638 struct vlv_fifo_state {
 639         u16 plane[I915_MAX_PLANES];
 640 };
 641
 642 enum g4x_wm_level {
 643         G4X_WM_LEVEL_NORMAL,
 644         G4X_WM_LEVEL_SR,
 645         G4X_WM_LEVEL_HPLL,
 646         NUM_G4X_WM_LEVELS,
 647 };
 648
 649 struct g4x_wm_state {
 650         struct g4x_pipe_wm wm;
 651         struct g4x_sr_wm sr;
 652         struct g4x_sr_wm hpll;
 653         bool cxsr;
 654         bool hpll_en;
 655         bool fbc_en;
 656 };
 657
 658 struct intel_crtc_wm_state {
 659         union {
 660                 struct {
 661                         /*
 662                          * Intermediate watermarks; these can be
 663                          * programmed immediately since they satisfy
 664                          * both the current configuration we're
 665                          * switching away from and the new
 666                          * configuration we're switching to.
 667                          */
 668                         struct intel_pipe_wm intermediate;
 669
 670                         /*
 671                          * Optimal watermarks, programmed post-vblank
 672                          * when this state is committed.
 673                          */
 674                         struct intel_pipe_wm optimal;
 675                 } ilk;
 676
 677                 struct {
 678                         /* gen9+ only needs 1-step wm programming */
 679                         struct skl_pipe_wm optimal;
 680                         struct skl_ddb_entry ddb;
 681                 } skl;
 682
 683                 struct {
 684                         /* "raw" watermarks (not inverted) */
 685                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 686                         /* intermediate watermarks (inverted) */
 687                         struct vlv_wm_state intermediate;
 688                         /* optimal watermarks (inverted) */
 689                         struct vlv_wm_state optimal;
 690                         /* display FIFO split */
 691                         struct vlv_fifo_state fifo_state;
 692                 } vlv;
 693
 694                 struct {
 695                         /* "raw" watermarks */
 696                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 697                         /* intermediate watermarks */
 698                         struct g4x_wm_state intermediate;
 699                         /* optimal watermarks */
 700                         struct g4x_wm_state optimal;
 701                 } g4x;
 702         };
 703
 704         /*
 705          * Platforms with two-step watermark programming will need to
 706          * update watermark programming post-vblank to switch from the
 707          * safe intermediate watermarks to the optimal final
 708          * watermarks.
 709          */
 710         bool need_postvbl_update;
 711 };
 712
 713 struct intel_crtc_state {
 714         struct drm_crtc_state base;
 715
 716         /**
 717          * quirks - bitfield with hw state readout quirks
 718          *
 719          * For various reasons the hw state readout code might not be able to
 720          * completely faithfully read out the current state. These cases are
 721          * tracked with quirk flags so that fastboot and state checker can act
 722          * accordingly.
 723          */
 724 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 725         unsigned long quirks;
 726
 727         unsigned fb_bits; /* framebuffers to flip */
 728         bool update_pipe; /* can a fast modeset be performed? */
 729         bool disable_cxsr;
 730         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 731         bool fb_changed; /* fb on any of the planes is changed */
 732         bool fifo_changed; /* FIFO split is changed */
 733
 734         /* Pipe source size (ie. panel fitter input size)
 735          * All planes will be positioned inside this space,
 736          * and get clipped at the edges. */
 737         int pipe_src_w, pipe_src_h;
 738
 739         /*
 740          * Pipe pixel rate, adjusted for
 741          * panel fitter/pipe scaler downscaling.
 742          */
 743         unsigned int pixel_rate;
 744
 745         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 746          * between pch encoders and cpu encoders. */
 747         bool has_pch_encoder;
 748
 749         /* Are we sending infoframes on the attached port */
 750         bool has_infoframe;
 751
 752         /* CPU Transcoder for the pipe. Currently this can only differ from the
 753          * pipe on Haswell and later (where we have a special eDP transcoder)
 754          * and Broxton (where we have special DSI transcoders). */
 755         enum transcoder cpu_transcoder;
 756
 757         /*
 758          * Use reduced/limited/broadcast rbg range, compressing from the full
 759          * range fed into the crtcs.
 760          */
 761         bool limited_color_range;
 762
 763         /* Bitmask of encoder types (enum intel_output_type)
 764          * driven by the pipe.
 765          */
 766         unsigned int output_types;
 767
 768         /* Whether we should send NULL infoframes. Required for audio. */
 769         bool has_hdmi_sink;
 770
 771         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 772          * has_dp_encoder is set. */
 773         bool has_audio;
 774
 775         /*
 776          * Enable dithering, used when the selected pipe bpp doesn't match the
 777          * plane bpp.
 778          */
 779         bool dither;
 780
 781         /*
 782          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 783          * compliance video pattern tests.
 784          * Disable dither only if it is a compliance test request for
 785          * 18bpp.
 786          */
 787         bool dither_force_disable;
 788
 789         /* Controls for the clock computation, to override various stages. */
 790         bool clock_set;
 791
 792         /* SDVO TV has a bunch of special case. To make multifunction encoders
 793          * work correctly, we need to track this at runtime.*/
 794         bool sdvo_tv_clock;
 795
 796         /*
 797          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 798          * required. This is set in the 2nd loop of calling encoder's
 799          * ->compute_config if the first pick doesn't work out.
 800          */
 801         bool bw_constrained;
 802
 803         /* Settings for the intel dpll used on pretty much everything but
 804          * haswell. */
 805         struct dpll dpll;
 806
 807         /* Selected dpll when shared or NULL. */
 808         struct intel_shared_dpll *shared_dpll;
 809
 810         /* Actual register state of the dpll, for shared dpll cross-checking. */
 811         struct intel_dpll_hw_state dpll_hw_state;
 812
 813         /* DSI PLL registers */
 814         struct {
 815                 u32 ctrl, div;
 816         } dsi_pll;
 817
 818         int pipe_bpp;
 819         struct intel_link_m_n dp_m_n;
 820
 821         /* m2_n2 for eDP downclock */
 822         struct intel_link_m_n dp_m2_n2;
 823         bool has_drrs;
 824
 825         bool has_psr;
 826         bool has_psr2;
 827
 828         /*
 829          * Frequence the dpll for the port should run at. Differs from the
 830          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 831          * already multiplied by pixel_multiplier.
 832          */
 833         int port_clock;
 834
 835         /* Used by SDVO (and if we ever fix it, HDMI). */
 836         unsigned pixel_multiplier;
 837
 838         uint8_t lane_count;
 839
 840         /*
 841          * Used by platforms having DP/HDMI PHY with programmable lane
 842          * latency optimization.
 843          */
 844         uint8_t lane_lat_optim_mask;
 845
 846         /* minimum acceptable voltage level */
 847         u8 min_voltage_level;
 848
 849         /* Panel fitter controls for gen2-gen4 + VLV */
 850         struct {
 851                 u32 control;
 852                 u32 pgm_ratios;
 853                 u32 lvds_border_bits;
 854         } gmch_pfit;
 855
 856         /* Panel fitter placement and size for Ironlake+ */
 857         struct {
 858                 u32 pos;
 859                 u32 size;
 860                 bool enabled;
 861                 bool force_thru;
 862         } pch_pfit;
 863
 864         /* FDI configuration, only valid if has_pch_encoder is set. */
 865         int fdi_lanes;
 866         struct intel_link_m_n fdi_m_n;
 867
 868         bool ips_enabled;
 869         bool ips_force_disable;
 870
 871         bool enable_fbc;
 872
 873         bool double_wide;
 874
 875         int pbn;
 876
 877         struct intel_crtc_scaler_state scaler_state;
 878
 879         /* w/a for waiting 2 vblanks during crtc enable */
 880         enum pipe hsw_workaround_pipe;
 881
 882         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 883         bool disable_lp_wm;
 884
 885         struct intel_crtc_wm_state wm;
 886
 887         /* Gamma mode programmed on the pipe */
 888         uint32_t gamma_mode;
 889
 890         /* bitmask of visible planes (enum plane_id) */
 891         u8 active_planes;
 892         u8 nv12_planes;
 893
 894         /* HDMI scrambling status */
 895         bool hdmi_scrambling;
 896
 897         /* HDMI High TMDS char rate ratio */
 898         bool hdmi_high_tmds_clock_ratio;
 899
 900         /* output format is YCBCR 4:2:0 */
 901         bool ycbcr420;
 902 };
 903
 904 struct intel_crtc {
 905         struct drm_crtc base;
 906         enum pipe pipe;
 907         /*
 908          * Whether the crtc and the connected output pipeline is active. Implies
 909          * that crtc->enabled is set, i.e. the current mode configuration has
 910          * some outputs connected to this crtc.
 911          */
 912         bool active;
 913         u8 plane_ids_mask;
 914         unsigned long long enabled_power_domains;
 915         struct intel_overlay *overlay;
 916
 917         struct intel_crtc_state *config;
 918
 919         /* global reset count when the last flip was submitted */
 920         unsigned int reset_count;
 921
 922         /* Access to these should be protected by dev_priv->irq_lock. */
 923         bool cpu_fifo_underrun_disabled;
 924         bool pch_fifo_underrun_disabled;
 925
 926         /* per-pipe watermark state */
 927         struct {
 928                 /* watermarks currently being used  */
 929                 union {
 930                         struct intel_pipe_wm ilk;
 931                         struct vlv_wm_state vlv;
 932                         struct g4x_wm_state g4x;
 933                 } active;
 934         } wm;
 935
 936         int scanline_offset;
 937
 938         struct {
 939                 unsigned start_vbl_count;
 940                 ktime_t start_vbl_time;
 941                 int min_vbl, max_vbl;
 942                 int scanline_start;
 943         } debug;
 944
 945         /* scalers available on this crtc */
 946         int num_scalers;
 947 };
 948
 949 struct intel_plane {
 950         struct drm_plane base;
 951         enum i9xx_plane_id i9xx_plane;
 952         enum plane_id id;
 953         enum pipe pipe;
 954         bool can_scale;
 955         bool has_fbc;
 956         int max_downscale;
 957         uint32_t frontbuffer_bit;
 958
 959         struct {
 960                 u32 base, cntl, size;
 961         } cursor;
 962
 963         /*
 964          * NOTE: Do not place new plane state fields here (e.g., when adding
 965          * new plane properties).  New runtime state should now be placed in
 966          * the intel_plane_state structure and accessed via plane_state.
 967          */
 968
 969         void (*update_plane)(struct intel_plane *plane,
 970                              const struct intel_crtc_state *crtc_state,
 971                              const struct intel_plane_state *plane_state);
 972         void (*disable_plane)(struct intel_plane *plane,
 973                               struct intel_crtc *crtc);
 974         bool (*get_hw_state)(struct intel_plane *plane);
 975         int (*check_plane)(struct intel_plane *plane,
 976                            struct intel_crtc_state *crtc_state,
 977                            struct intel_plane_state *state);
 978 };
 979
 980 struct intel_watermark_params {
 981         u16 fifo_size;
 982         u16 max_wm;
 983         u8 default_wm;
 984         u8 guard_size;
 985         u8 cacheline_size;
 986 };
 987
 988 struct cxsr_latency {
 989         bool is_desktop : 1;
 990         bool is_ddr3 : 1;
 991         u16 fsb_freq;
 992         u16 mem_freq;
 993         u16 display_sr;
 994         u16 display_hpll_disable;
 995         u16 cursor_sr;
 996         u16 cursor_hpll_disable;
 997 };
 998
 999 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1000 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1001 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1002 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1003 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1004 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1005 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1006 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1007 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
1008
1009 struct intel_hdmi {
1010         i915_reg_t hdmi_reg;
1011         int ddc_bus;
1012         struct {
1013                 enum drm_dp_dual_mode_type type;
1014                 int max_tmds_clock;
1015         } dp_dual_mode;
1016         bool has_hdmi_sink;
1017         bool has_audio;
1018         bool rgb_quant_range_selectable;
1019         struct intel_connector *attached_connector;
1020 };
1021
1022 struct intel_dp_mst_encoder;
1023 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1024
1025 /*
1026  * enum link_m_n_set:
1027  *      When platform provides two set of M_N registers for dp, we can
1028  *      program them and switch between them incase of DRRS.
1029  *      But When only one such register is provided, we have to program the
1030  *      required divider value on that registers itself based on the DRRS state.
1031  *
1032  * M1_N1        : Program dp_m_n on M1_N1 registers
1033  *                        dp_m2_n2 on M2_N2 registers (If supported)
1034  *
1035  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1036  *                        M2_N2 registers are not supported
1037  */
1038
1039 enum link_m_n_set {
1040         /* Sets the m1_n1 and m2_n2 */
1041         M1_N1 = 0,
1042         M2_N2
1043 };
1044
1045 struct intel_dp_compliance_data {
1046         unsigned long edid;
1047         uint8_t video_pattern;
1048         uint16_t hdisplay, vdisplay;
1049         uint8_t bpc;
1050 };
1051
1052 struct intel_dp_compliance {
1053         unsigned long test_type;
1054         struct intel_dp_compliance_data test_data;
1055         bool test_active;
1056         int test_link_rate;
1057         u8 test_lane_count;
1058 };
1059
1060 struct intel_dp {
1061         i915_reg_t output_reg;
1062         uint32_t DP;
1063         int link_rate;
1064         uint8_t lane_count;
1065         uint8_t sink_count;
1066         bool link_mst;
1067         bool link_trained;
1068         bool has_audio;
1069         bool detect_done;
1070         bool reset_link_params;
1071         enum aux_ch aux_ch;
1072         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1073         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1074         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1075         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1076         /* source rates */
1077         int num_source_rates;
1078         const int *source_rates;
1079         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1080         int num_sink_rates;
1081         int sink_rates[DP_MAX_SUPPORTED_RATES];
1082         bool use_rate_select;
1083         /* intersection of source and sink rates */
1084         int num_common_rates;
1085         int common_rates[DP_MAX_SUPPORTED_RATES];
1086         /* Max lane count for the current link */
1087         int max_link_lane_count;
1088         /* Max rate for the current link */
1089         int max_link_rate;
1090         /* sink or branch descriptor */
1091         struct drm_dp_desc desc;
1092         struct drm_dp_aux aux;
1093         enum intel_display_power_domain aux_power_domain;
1094         uint8_t train_set[4];
1095         int panel_power_up_delay;
1096         int panel_power_down_delay;
1097         int panel_power_cycle_delay;
1098         int backlight_on_delay;
1099         int backlight_off_delay;
1100         struct delayed_work panel_vdd_work;
1101         bool want_panel_vdd;
1102         unsigned long last_power_on;
1103         unsigned long last_backlight_off;
1104         ktime_t panel_power_off_time;
1105
1106         struct notifier_block edp_notifier;
1107
1108         /*
1109          * Pipe whose power sequencer is currently locked into
1110          * this port. Only relevant on VLV/CHV.
1111          */
1112         enum pipe pps_pipe;
1113         /*
1114          * Pipe currently driving the port. Used for preventing
1115          * the use of the PPS for any pipe currentrly driving
1116          * external DP as that will mess things up on VLV.
1117          */
1118         enum pipe active_pipe;
1119         /*
1120          * Set if the sequencer may be reset due to a power transition,
1121          * requiring a reinitialization. Only relevant on BXT.
1122          */
1123         bool pps_reset;
1124         struct edp_power_seq pps_delays;
1125
1126         bool can_mst; /* this port supports mst */
1127         bool is_mst;
1128         int active_mst_links;
1129         /* connector directly attached - won't be use for modeset in mst world */
1130         struct intel_connector *attached_connector;
1131
1132         /* mst connector list */
1133         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1134         struct drm_dp_mst_topology_mgr mst_mgr;
1135
1136         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1137         /*
1138          * This function returns the value we have to program the AUX_CTL
1139          * register with to kick off an AUX transaction.
1140          */
1141         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1142                                      bool has_aux_irq,
1143                                      int send_bytes,
1144                                      uint32_t aux_clock_divider);
1145
1146         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1147         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1148
1149         /* This is called before a link training is starterd */
1150         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1151
1152         /* Displayport compliance testing */
1153         struct intel_dp_compliance compliance;
1154 };
1155
1156 struct intel_lspcon {
1157         bool active;
1158         enum drm_lspcon_mode mode;
1159 };
1160
1161 struct intel_digital_port {
1162         struct intel_encoder base;
1163         u32 saved_port_bits;
1164         struct intel_dp dp;
1165         struct intel_hdmi hdmi;
1166         struct intel_lspcon lspcon;
1167         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1168         bool release_cl2_override;
1169         uint8_t max_lanes;
1170         enum intel_display_power_domain ddi_io_power_domain;
1171
1172         void (*write_infoframe)(struct drm_encoder *encoder,
1173                                 const struct intel_crtc_state *crtc_state,
1174                                 unsigned int type,
1175                                 const void *frame, ssize_t len);
1176         void (*set_infoframes)(struct drm_encoder *encoder,
1177                                bool enable,
1178                                const struct intel_crtc_state *crtc_state,
1179                                const struct drm_connector_state *conn_state);
1180         bool (*infoframe_enabled)(struct drm_encoder *encoder,
1181                                   const struct intel_crtc_state *pipe_config);
1182 };
1183
1184 struct intel_dp_mst_encoder {
1185         struct intel_encoder base;
1186         enum pipe pipe;
1187         struct intel_digital_port *primary;
1188         struct intel_connector *connector;
1189 };
1190
1191 static inline enum dpio_channel
1192 vlv_dport_to_channel(struct intel_digital_port *dport)
1193 {
1194         switch (dport->base.port) {
1195         case PORT_B:
1196         case PORT_D:
1197                 return DPIO_CH0;
1198         case PORT_C:
1199                 return DPIO_CH1;
1200         default:
1201                 BUG();
1202         }
1203 }
1204
1205 static inline enum dpio_phy
1206 vlv_dport_to_phy(struct intel_digital_port *dport)
1207 {
1208         switch (dport->base.port) {
1209         case PORT_B:
1210         case PORT_C:
1211                 return DPIO_PHY0;
1212         case PORT_D:
1213                 return DPIO_PHY1;
1214         default:
1215                 BUG();
1216         }
1217 }
1218
1219 static inline enum dpio_channel
1220 vlv_pipe_to_channel(enum pipe pipe)
1221 {
1222         switch (pipe) {
1223         case PIPE_A:
1224         case PIPE_C:
1225                 return DPIO_CH0;
1226         case PIPE_B:
1227                 return DPIO_CH1;
1228         default:
1229                 BUG();
1230         }
1231 }
1232
1233 static inline struct intel_crtc *
1234 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1235 {
1236         return dev_priv->pipe_to_crtc_mapping[pipe];
1237 }
1238
1239 static inline struct intel_crtc *
1240 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1241 {
1242         return dev_priv->plane_to_crtc_mapping[plane];
1243 }
1244
1245 struct intel_load_detect_pipe {
1246         struct drm_atomic_state *restore_state;
1247 };
1248
1249 static inline struct intel_encoder *
1250 intel_attached_encoder(struct drm_connector *connector)
1251 {
1252         return to_intel_connector(connector)->encoder;
1253 }
1254
1255 static inline struct intel_digital_port *
1256 enc_to_dig_port(struct drm_encoder *encoder)
1257 {
1258         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1259
1260         switch (intel_encoder->type) {
1261         case INTEL_OUTPUT_DDI:
1262                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1263         case INTEL_OUTPUT_DP:
1264         case INTEL_OUTPUT_EDP:
1265         case INTEL_OUTPUT_HDMI:
1266                 return container_of(encoder, struct intel_digital_port,
1267                                     base.base);
1268         default:
1269                 return NULL;
1270         }
1271 }
1272
1273 static inline struct intel_dp_mst_encoder *
1274 enc_to_mst(struct drm_encoder *encoder)
1275 {
1276         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1277 }
1278
1279 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1280 {
1281         return &enc_to_dig_port(encoder)->dp;
1282 }
1283
1284 static inline struct intel_digital_port *
1285 dp_to_dig_port(struct intel_dp *intel_dp)
1286 {
1287         return container_of(intel_dp, struct intel_digital_port, dp);
1288 }
1289
1290 static inline struct intel_lspcon *
1291 dp_to_lspcon(struct intel_dp *intel_dp)
1292 {
1293         return &dp_to_dig_port(intel_dp)->lspcon;
1294 }
1295
1296 static inline struct intel_digital_port *
1297 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1298 {
1299         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1300 }
1301
1302 static inline struct intel_plane_state *
1303 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1304                                  struct intel_plane *plane)
1305 {
1306         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1307                                                                    &plane->base));
1308 }
1309
1310 static inline struct intel_crtc_state *
1311 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1312                                 struct intel_crtc *crtc)
1313 {
1314         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1315                                                                  &crtc->base));
1316 }
1317
1318 static inline struct intel_crtc_state *
1319 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1320                                 struct intel_crtc *crtc)
1321 {
1322         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1323                                                                  &crtc->base));
1324 }
1325
1326 /* intel_fifo_underrun.c */
1327 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1328                                            enum pipe pipe, bool enable);
1329 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1330                                            enum pipe pch_transcoder,
1331                                            bool enable);
1332 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1333                                          enum pipe pipe);
1334 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1335                                          enum pipe pch_transcoder);
1336 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1337 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1338
1339 /* i915_irq.c */
1340 bool gen11_reset_one_iir(struct drm_i915_private * const i915,
1341                          const unsigned int bank,
1342                          const unsigned int bit);
1343 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1344 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1345 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1346 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1347 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1348 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1349 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1350 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1351
1352 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1353                                             u32 mask)
1354 {
1355         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1356 }
1357
1358 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1359 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1360 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1361 {
1362         /*
1363          * We only use drm_irq_uninstall() at unload and VT switch, so
1364          * this is the only thing we need to check.
1365          */
1366         return dev_priv->runtime_pm.irqs_enabled;
1367 }
1368
1369 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1370 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1371                                      u8 pipe_mask);
1372 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1373                                      u8 pipe_mask);
1374 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1375 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1376 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1377
1378 /* intel_crt.c */
1379 void intel_crt_init(struct drm_i915_private *dev_priv);
1380 void intel_crt_reset(struct drm_encoder *encoder);
1381
1382 /* intel_ddi.c */
1383 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1384                                 const struct intel_crtc_state *old_crtc_state,
1385                                 const struct drm_connector_state *old_conn_state);
1386 void hsw_fdi_link_train(struct intel_crtc *crtc,
1387                         const struct intel_crtc_state *crtc_state);
1388 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1389 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1390 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1391 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1392 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1393 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1394 struct intel_encoder *
1395 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1396 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1397 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1398 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1399 void intel_ddi_get_config(struct intel_encoder *encoder,
1400                           struct intel_crtc_state *pipe_config);
1401
1402 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1403                                     bool state);
1404 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1405                                          struct intel_crtc_state *crtc_state);
1406 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1407 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1408 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1409 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1410                                      bool enable);
1411 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1412                            struct intel_crtc_state *crtc_state,
1413                            struct drm_atomic_state *old_state);
1414 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1415                              struct intel_crtc_state *crtc_state,
1416                              struct drm_atomic_state *old_state);
1417
1418 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1419                                    int plane, unsigned int height);
1420
1421 /* intel_audio.c */
1422 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1423 void intel_audio_codec_enable(struct intel_encoder *encoder,
1424                               const struct intel_crtc_state *crtc_state,
1425                               const struct drm_connector_state *conn_state);
1426 void intel_audio_codec_disable(struct intel_encoder *encoder,
1427                                const struct intel_crtc_state *old_crtc_state,
1428                                const struct drm_connector_state *old_conn_state);
1429 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1430 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1431 void intel_audio_init(struct drm_i915_private *dev_priv);
1432 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1433
1434 /* intel_cdclk.c */
1435 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1436 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1437 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1438 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1439 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1440 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1441 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1442 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1443 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1444 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1445 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1446 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1447 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1448 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1449                                const struct intel_cdclk_state *b);
1450 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1451                          const struct intel_cdclk_state *b);
1452 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1453                      const struct intel_cdclk_state *cdclk_state);
1454 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1455                             const char *context);
1456
1457 /* intel_display.c */
1458 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1459 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1460 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1461 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1462 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1463 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1464                       const char *name, u32 reg, int ref_freq);
1465 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1466                            const char *name, u32 reg);
1467 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1468 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1469 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1470 unsigned int intel_fb_xy_to_linear(int x, int y,
1471                                    const struct intel_plane_state *state,
1472                                    int plane);
1473 void intel_add_fb_offsets(int *x, int *y,
1474                           const struct intel_plane_state *state, int plane);
1475 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1476 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1477 void intel_mark_busy(struct drm_i915_private *dev_priv);
1478 void intel_mark_idle(struct drm_i915_private *dev_priv);
1479 int intel_display_suspend(struct drm_device *dev);
1480 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1481 void intel_encoder_destroy(struct drm_encoder *encoder);
1482 int intel_connector_init(struct intel_connector *);
1483 struct intel_connector *intel_connector_alloc(void);
1484 void intel_connector_free(struct intel_connector *connector);
1485 bool intel_connector_get_hw_state(struct intel_connector *connector);
1486 void intel_connector_attach_encoder(struct intel_connector *connector,
1487                                     struct intel_encoder *encoder);
1488 struct drm_display_mode *
1489 intel_encoder_current_mode(struct intel_encoder *encoder);
1490
1491 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1492 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1493                                       struct drm_file *file_priv);
1494 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1495                                              enum pipe pipe);
1496 static inline bool
1497 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1498                     enum intel_output_type type)
1499 {
1500         return crtc_state->output_types & (1 << type);
1501 }
1502 static inline bool
1503 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1504 {
1505         return crtc_state->output_types &
1506                 ((1 << INTEL_OUTPUT_DP) |
1507                  (1 << INTEL_OUTPUT_DP_MST) |
1508                  (1 << INTEL_OUTPUT_EDP));
1509 }
1510 static inline void
1511 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1512 {
1513         drm_wait_one_vblank(&dev_priv->drm, pipe);
1514 }
1515 static inline void
1516 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1517 {
1518         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1519
1520         if (crtc->active)
1521                 intel_wait_for_vblank(dev_priv, pipe);
1522 }
1523
1524 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1525
1526 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1527 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1528                          struct intel_digital_port *dport,
1529                          unsigned int expected_mask);
1530 int intel_get_load_detect_pipe(struct drm_connector *connector,
1531                                const struct drm_display_mode *mode,
1532                                struct intel_load_detect_pipe *old,
1533                                struct drm_modeset_acquire_ctx *ctx);
1534 void intel_release_load_detect_pipe(struct drm_connector *connector,
1535                                     struct intel_load_detect_pipe *old,
1536                                     struct drm_modeset_acquire_ctx *ctx);
1537 struct i915_vma *
1538 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1539                            unsigned int rotation,
1540                            bool uses_fence,
1541                            unsigned long *out_flags);
1542 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1543 struct drm_framebuffer *
1544 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1545                          struct drm_mode_fb_cmd2 *mode_cmd);
1546 int intel_prepare_plane_fb(struct drm_plane *plane,
1547                            struct drm_plane_state *new_state);
1548 void intel_cleanup_plane_fb(struct drm_plane *plane,
1549                             struct drm_plane_state *old_state);
1550 int intel_plane_atomic_get_property(struct drm_plane *plane,
1551                                     const struct drm_plane_state *state,
1552                                     struct drm_property *property,
1553                                     uint64_t *val);
1554 int intel_plane_atomic_set_property(struct drm_plane *plane,
1555                                     struct drm_plane_state *state,
1556                                     struct drm_property *property,
1557                                     uint64_t val);
1558 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1559                                     struct drm_crtc_state *crtc_state,
1560                                     const struct intel_plane_state *old_plane_state,
1561                                     struct drm_plane_state *plane_state);
1562
1563 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1564                                     enum pipe pipe);
1565
1566 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1567                      const struct dpll *dpll);
1568 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1569 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1570
1571 /* modesetting asserts */
1572 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1573                            enum pipe pipe);
1574 void assert_pll(struct drm_i915_private *dev_priv,
1575                 enum pipe pipe, bool state);
1576 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1577 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1578 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1579 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1580 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1581 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1582                        enum pipe pipe, bool state);
1583 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1584 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1585 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1586 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1587 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1588 u32 intel_compute_tile_offset(int *x, int *y,
1589                               const struct intel_plane_state *state, int plane);
1590 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1591 void intel_finish_reset(struct drm_i915_private *dev_priv);
1592 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1593 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1594 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1595 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1596 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1597 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1598 unsigned int skl_cdclk_get_vco(unsigned int freq);
1599 void intel_dp_get_m_n(struct intel_crtc *crtc,
1600                       struct intel_crtc_state *pipe_config);
1601 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1602 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1603 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1604                         struct dpll *best_clock);
1605 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1606
1607 bool intel_crtc_active(struct intel_crtc *crtc);
1608 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1609 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1610 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1611 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1612 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1613                                  struct intel_crtc_state *pipe_config);
1614 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1615                                   struct intel_crtc_state *crtc_state);
1616
1617 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1618 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1619                   uint32_t pixel_format);
1620
1621 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1622 {
1623         return i915_ggtt_offset(state->vma);
1624 }
1625
1626 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1627                         const struct intel_plane_state *plane_state);
1628 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1629                   const struct intel_plane_state *plane_state);
1630 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1631 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1632                      unsigned int rotation);
1633 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
1634                             struct intel_plane_state *plane_state);
1635 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1636 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1637
1638 /* intel_csr.c */
1639 void intel_csr_ucode_init(struct drm_i915_private *);
1640 void intel_csr_load_program(struct drm_i915_private *);
1641 void intel_csr_ucode_fini(struct drm_i915_private *);
1642 void intel_csr_ucode_suspend(struct drm_i915_private *);
1643 void intel_csr_ucode_resume(struct drm_i915_private *);
1644
1645 /* intel_dp.c */
1646 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1647                    enum port port);
1648 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1649                              struct intel_connector *intel_connector);
1650 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1651                               int link_rate, uint8_t lane_count,
1652                               bool link_mst);
1653 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1654                                             int link_rate, uint8_t lane_count);
1655 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1656 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1657 int intel_dp_retrain_link(struct intel_encoder *encoder,
1658                           struct drm_modeset_acquire_ctx *ctx);
1659 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1660 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1661 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1662 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1663 int intel_dp_sink_crc(struct intel_dp *intel_dp,
1664                       struct intel_crtc_state *crtc_state, u8 *crc);
1665 bool intel_dp_compute_config(struct intel_encoder *encoder,
1666                              struct intel_crtc_state *pipe_config,
1667                              struct drm_connector_state *conn_state);
1668 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1669 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1670 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1671                                   bool long_hpd);
1672 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1673                             const struct drm_connector_state *conn_state);
1674 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1675 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1676 void intel_edp_panel_on(struct intel_dp *intel_dp);
1677 void intel_edp_panel_off(struct intel_dp *intel_dp);
1678 void intel_dp_mst_suspend(struct drm_device *dev);
1679 void intel_dp_mst_resume(struct drm_device *dev);
1680 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1681 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1682 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1683 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1684 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1685 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1686 void intel_plane_destroy(struct drm_plane *plane);
1687 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1688                            const struct intel_crtc_state *crtc_state);
1689 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1690                             const struct intel_crtc_state *crtc_state);
1691 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1692                                unsigned int frontbuffer_bits);
1693 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1694                           unsigned int frontbuffer_bits);
1695
1696 void
1697 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1698                                        uint8_t dp_train_pat);
1699 void
1700 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1701 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1702 uint8_t
1703 intel_dp_voltage_max(struct intel_dp *intel_dp);
1704 uint8_t
1705 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1706 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1707                            uint8_t *link_bw, uint8_t *rate_select);
1708 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1709 bool
1710 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1711
1712 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1713 {
1714         return ~((1 << lane_count) - 1) & 0xf;
1715 }
1716
1717 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1718 int intel_dp_link_required(int pixel_clock, int bpp);
1719 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1720 bool intel_digital_port_connected(struct intel_encoder *encoder);
1721
1722 /* intel_dp_aux_backlight.c */
1723 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1724
1725 /* intel_dp_mst.c */
1726 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1727 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1728 /* intel_dsi.c */
1729 void intel_dsi_init(struct drm_i915_private *dev_priv);
1730
1731 /* intel_dsi_dcs_backlight.c */
1732 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1733
1734 /* intel_dvo.c */
1735 void intel_dvo_init(struct drm_i915_private *dev_priv);
1736 /* intel_hotplug.c */
1737 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1738 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1739                            struct intel_connector *connector);
1740
1741 /* legacy fbdev emulation in intel_fbdev.c */
1742 #ifdef CONFIG_DRM_FBDEV_EMULATION
1743 extern int intel_fbdev_init(struct drm_device *dev);
1744 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1745 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1746 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1747 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1748 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1749 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1750 #else
1751 static inline int intel_fbdev_init(struct drm_device *dev)
1752 {
1753         return 0;
1754 }
1755
1756 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1757 {
1758 }
1759
1760 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1761 {
1762 }
1763
1764 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1765 {
1766 }
1767
1768 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1769 {
1770 }
1771
1772 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1773 {
1774 }
1775
1776 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1777 {
1778 }
1779 #endif
1780
1781 /* intel_fbc.c */
1782 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1783                            struct intel_atomic_state *state);
1784 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1785 void intel_fbc_pre_update(struct intel_crtc *crtc,
1786                           struct intel_crtc_state *crtc_state,
1787                           struct intel_plane_state *plane_state);
1788 void intel_fbc_post_update(struct intel_crtc *crtc);
1789 void intel_fbc_init(struct drm_i915_private *dev_priv);
1790 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1791 void intel_fbc_enable(struct intel_crtc *crtc,
1792                       struct intel_crtc_state *crtc_state,
1793                       struct intel_plane_state *plane_state);
1794 void intel_fbc_disable(struct intel_crtc *crtc);
1795 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1796 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1797                           unsigned int frontbuffer_bits,
1798                           enum fb_op_origin origin);
1799 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1800                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1801 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1802 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1803 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1804
1805 /* intel_hdmi.c */
1806 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1807                      enum port port);
1808 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1809                                struct intel_connector *intel_connector);
1810 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1811 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1812                                struct intel_crtc_state *pipe_config,
1813                                struct drm_connector_state *conn_state);
1814 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1815                                        struct drm_connector *connector,
1816                                        bool high_tmds_clock_ratio,
1817                                        bool scrambling);
1818 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1819 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1820
1821
1822 /* intel_lvds.c */
1823 void intel_lvds_init(struct drm_i915_private *dev_priv);
1824 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1825 bool intel_is_dual_link_lvds(struct drm_device *dev);
1826
1827
1828 /* intel_modes.c */
1829 int intel_connector_update_modes(struct drm_connector *connector,
1830                                  struct edid *edid);
1831 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1832 void intel_attach_force_audio_property(struct drm_connector *connector);
1833 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1834 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1835
1836
1837 /* intel_overlay.c */
1838 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1839 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1840 int intel_overlay_switch_off(struct intel_overlay *overlay);
1841 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1842                                   struct drm_file *file_priv);
1843 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1844                               struct drm_file *file_priv);
1845 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1846
1847
1848 /* intel_panel.c */
1849 int intel_panel_init(struct intel_panel *panel,
1850                      struct drm_display_mode *fixed_mode,
1851                      struct drm_display_mode *downclock_mode);
1852 void intel_panel_fini(struct intel_panel *panel);
1853 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1854                             struct drm_display_mode *adjusted_mode);
1855 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1856                              struct intel_crtc_state *pipe_config,
1857                              int fitting_mode);
1858 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1859                               struct intel_crtc_state *pipe_config,
1860                               int fitting_mode);
1861 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1862                                     u32 level, u32 max);
1863 int intel_panel_setup_backlight(struct drm_connector *connector,
1864                                 enum pipe pipe);
1865 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1866                                   const struct drm_connector_state *conn_state);
1867 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1868 void intel_panel_destroy_backlight(struct drm_connector *connector);
1869 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1870 extern struct drm_display_mode *intel_find_panel_downclock(
1871                                 struct drm_i915_private *dev_priv,
1872                                 struct drm_display_mode *fixed_mode,
1873                                 struct drm_connector *connector);
1874
1875 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1876 int intel_backlight_device_register(struct intel_connector *connector);
1877 void intel_backlight_device_unregister(struct intel_connector *connector);
1878 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1879 static inline int intel_backlight_device_register(struct intel_connector *connector)
1880 {
1881         return 0;
1882 }
1883 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1884 {
1885 }
1886 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1887
1888 /* intel_hdcp.c */
1889 void intel_hdcp_atomic_check(struct drm_connector *connector,
1890                              struct drm_connector_state *old_state,
1891                              struct drm_connector_state *new_state);
1892 int intel_hdcp_init(struct intel_connector *connector,
1893                     const struct intel_hdcp_shim *hdcp_shim);
1894 int intel_hdcp_enable(struct intel_connector *connector);
1895 int intel_hdcp_disable(struct intel_connector *connector);
1896 int intel_hdcp_check_link(struct intel_connector *connector);
1897 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
1898
1899 /* intel_psr.c */
1900 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1901 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
1902 void intel_psr_enable(struct intel_dp *intel_dp,
1903                       const struct intel_crtc_state *crtc_state);
1904 void intel_psr_disable(struct intel_dp *intel_dp,
1905                       const struct intel_crtc_state *old_crtc_state);
1906 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1907                           unsigned frontbuffer_bits,
1908                           enum fb_op_origin origin);
1909 void intel_psr_flush(struct drm_i915_private *dev_priv,
1910                      unsigned frontbuffer_bits,
1911                      enum fb_op_origin origin);
1912 void intel_psr_init(struct drm_i915_private *dev_priv);
1913 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1914                                    unsigned frontbuffer_bits);
1915 void intel_psr_compute_config(struct intel_dp *intel_dp,
1916                               struct intel_crtc_state *crtc_state);
1917 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
1918 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
1919
1920 /* intel_runtime_pm.c */
1921 int intel_power_domains_init(struct drm_i915_private *);
1922 void intel_power_domains_fini(struct drm_i915_private *);
1923 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1924 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1925 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1926 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1927 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1928 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1929 const char *
1930 intel_display_power_domain_str(enum intel_display_power_domain domain);
1931
1932 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1933                                     enum intel_display_power_domain domain);
1934 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1935                                       enum intel_display_power_domain domain);
1936 void intel_display_power_get(struct drm_i915_private *dev_priv,
1937                              enum intel_display_power_domain domain);
1938 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1939                                         enum intel_display_power_domain domain);
1940 void intel_display_power_put(struct drm_i915_private *dev_priv,
1941                              enum intel_display_power_domain domain);
1942 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
1943                             u8 req_slices);
1944
1945 static inline void
1946 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1947 {
1948         WARN_ONCE(dev_priv->runtime_pm.suspended,
1949                   "Device suspended during HW access\n");
1950 }
1951
1952 static inline void
1953 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1954 {
1955         assert_rpm_device_not_suspended(dev_priv);
1956         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1957                   "RPM wakelock ref not held during HW access");
1958 }
1959
1960 /**
1961  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1962  * @dev_priv: i915 device instance
1963  *
1964  * This function disable asserts that check if we hold an RPM wakelock
1965  * reference, while keeping the device-not-suspended checks still enabled.
1966  * It's meant to be used only in special circumstances where our rule about
1967  * the wakelock refcount wrt. the device power state doesn't hold. According
1968  * to this rule at any point where we access the HW or want to keep the HW in
1969  * an active state we must hold an RPM wakelock reference acquired via one of
1970  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1971  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1972  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1973  * users should avoid using this function.
1974  *
1975  * Any calls to this function must have a symmetric call to
1976  * enable_rpm_wakeref_asserts().
1977  */
1978 static inline void
1979 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1980 {
1981         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
1982 }
1983
1984 /**
1985  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1986  * @dev_priv: i915 device instance
1987  *
1988  * This function re-enables the RPM assert checks after disabling them with
1989  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1990  * circumstances otherwise its use should be avoided.
1991  *
1992  * Any calls to this function must have a symmetric call to
1993  * disable_rpm_wakeref_asserts().
1994  */
1995 static inline void
1996 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1997 {
1998         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
1999 }
2000
2001 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2002 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2003 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2004 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2005
2006 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
2007
2008 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2009                              bool override, unsigned int mask);
2010 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2011                           enum dpio_channel ch, bool override);
2012
2013
2014 /* intel_pm.c */
2015 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2016 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2017 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2018 void intel_update_watermarks(struct intel_crtc *crtc);
2019 void intel_init_pm(struct drm_i915_private *dev_priv);
2020 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2021 void intel_pm_setup(struct drm_i915_private *dev_priv);
2022 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2023 void intel_gpu_ips_teardown(void);
2024 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2025 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2026 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2027 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2028 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2029 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2030 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2031 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2032 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2033 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2034 void g4x_wm_get_hw_state(struct drm_device *dev);
2035 void vlv_wm_get_hw_state(struct drm_device *dev);
2036 void ilk_wm_get_hw_state(struct drm_device *dev);
2037 void skl_wm_get_hw_state(struct drm_device *dev);
2038 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2039                           struct skl_ddb_allocation *ddb /* out */);
2040 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2041                               struct skl_pipe_wm *out);
2042 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2043 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2044 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2045 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2046 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2047 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2048                          const struct skl_wm_level *l2);
2049 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2050                                  const struct skl_ddb_entry **entries,
2051                                  const struct skl_ddb_entry *ddb,
2052                                  int ignore);
2053 bool ilk_disable_lp_wm(struct drm_device *dev);
2054 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2055                                   struct intel_crtc_state *cstate);
2056 void intel_init_ipc(struct drm_i915_private *dev_priv);
2057 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2058
2059 /* intel_sdvo.c */
2060 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2061                      i915_reg_t reg, enum port port);
2062
2063
2064 /* intel_sprite.c */
2065 bool intel_format_is_yuv(u32 format);
2066 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2067                              int usecs);
2068 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2069                                               enum pipe pipe, int plane);
2070 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2071                                     struct drm_file *file_priv);
2072 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2073 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2074 void skl_update_plane(struct intel_plane *plane,
2075                       const struct intel_crtc_state *crtc_state,
2076                       const struct intel_plane_state *plane_state);
2077 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
2078 bool skl_plane_get_hw_state(struct intel_plane *plane);
2079 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2080                        enum pipe pipe, enum plane_id plane_id);
2081 bool intel_format_is_yuv(uint32_t format);
2082 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2083                           enum pipe pipe, enum plane_id plane_id);
2084
2085 /* intel_tv.c */
2086 void intel_tv_init(struct drm_i915_private *dev_priv);
2087
2088 /* intel_atomic.c */
2089 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2090                                                 const struct drm_connector_state *state,
2091                                                 struct drm_property *property,
2092                                                 uint64_t *val);
2093 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2094                                                 struct drm_connector_state *state,
2095                                                 struct drm_property *property,
2096                                                 uint64_t val);
2097 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2098                                          struct drm_connector_state *new_state);
2099 struct drm_connector_state *
2100 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2101
2102 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2103 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2104                                struct drm_crtc_state *state);
2105 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2106 void intel_atomic_state_clear(struct drm_atomic_state *);
2107
2108 static inline struct intel_crtc_state *
2109 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2110                             struct intel_crtc *crtc)
2111 {
2112         struct drm_crtc_state *crtc_state;
2113         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2114         if (IS_ERR(crtc_state))
2115                 return ERR_CAST(crtc_state);
2116
2117         return to_intel_crtc_state(crtc_state);
2118 }
2119
2120 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2121                                struct intel_crtc *intel_crtc,
2122                                struct intel_crtc_state *crtc_state);
2123
2124 /* intel_atomic_plane.c */
2125 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2126 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2127 void intel_plane_destroy_state(struct drm_plane *plane,
2128                                struct drm_plane_state *state);
2129 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2130 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2131                                         struct intel_crtc_state *crtc_state,
2132                                         const struct intel_plane_state *old_plane_state,
2133                                         struct intel_plane_state *intel_state);
2134
2135 /* intel_color.c */
2136 void intel_color_init(struct drm_crtc *crtc);
2137 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2138 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2139 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2140
2141 /* intel_lspcon.c */
2142 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2143 void lspcon_resume(struct intel_lspcon *lspcon);
2144 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2145
2146 /* intel_pipe_crc.c */
2147 int intel_pipe_crc_create(struct drm_minor *minor);
2148 #ifdef CONFIG_DEBUG_FS
2149 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2150                               size_t *values_cnt);
2151 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2152 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2153 #else
2154 #define intel_crtc_set_crc_source NULL
2155 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2156 {
2157 }
2158
2159 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2160 {
2161 }
2162 #endif
2163 extern const struct file_operations i915_display_crc_ctl_fops;
2164 #endif /* __INTEL_DRV_H__ */