drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * __wait_for - magic wait macro
  45  *
  46  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  47  * important that we check the condition again after having timed out, since the
  48  * timeout could be due to preemption or similar and we've never had a chance to
  49  * check the condition before the timeout.
  50  */
  51 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  52         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  53         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  54         int ret__;                                                      \
  55         might_sleep();                                                  \
  56         for (;;) {                                                      \
  57                 bool expired__ = time_after(jiffies, timeout__);        \
  58                 OP;                                                     \
  59                 if (COND) {                                             \
  60                         ret__ = 0;                                      \
  61                         break;                                          \
  62                 }                                                       \
  63                 if (expired__) {                                        \
  64                         ret__ = -ETIMEDOUT;                             \
  65                         break;                                          \
  66                 }                                                       \
  67                 usleep_range(wait__, wait__ * 2);                       \
  68                 if (wait__ < (Wmax))                                    \
  69                         wait__ <<= 1;                                   \
  70         }                                                               \
  71         ret__;                                                          \
  72 })
  73
  74 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  75                                                    (Wmax))
  76 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  77
  78 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  79 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  80 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  81 #else
  82 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  83 #endif
  84
  85 #define _wait_for_atomic(COND, US, ATOMIC) \
  86 ({ \
  87         int cpu, ret, timeout = (US) * 1000; \
  88         u64 base; \
  89         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  90         if (!(ATOMIC)) { \
  91                 preempt_disable(); \
  92                 cpu = smp_processor_id(); \
  93         } \
  94         base = local_clock(); \
  95         for (;;) { \
  96                 u64 now = local_clock(); \
  97                 if (!(ATOMIC)) \
  98                         preempt_enable(); \
  99                 if (COND) { \
 100                         ret = 0; \
 101                         break; \
 102                 } \
 103                 if (now - base >= timeout) { \
 104                         ret = -ETIMEDOUT; \
 105                         break; \
 106                 } \
 107                 cpu_relax(); \
 108                 if (!(ATOMIC)) { \
 109                         preempt_disable(); \
 110                         if (unlikely(cpu != smp_processor_id())) { \
 111                                 timeout -= now - base; \
 112                                 cpu = smp_processor_id(); \
 113                                 base = local_clock(); \
 114                         } \
 115                 } \
 116         } \
 117         ret; \
 118 })
 119
 120 #define wait_for_us(COND, US) \
 121 ({ \
 122         int ret__; \
 123         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 124         if ((US) > 10) \
 125                 ret__ = _wait_for((COND), (US), 10, 10); \
 126         else \
 127                 ret__ = _wait_for_atomic((COND), (US), 0); \
 128         ret__; \
 129 })
 130
 131 #define wait_for_atomic_us(COND, US) \
 132 ({ \
 133         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 134         BUILD_BUG_ON((US) > 50000); \
 135         _wait_for_atomic((COND), (US), 1); \
 136 })
 137
 138 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 139
 140 #define KHz(x) (1000 * (x))
 141 #define MHz(x) KHz(1000 * (x))
 142
 143 /*
 144  * Display related stuff
 145  */
 146
 147 /* store information about an Ixxx DVO */
 148 /* The i830->i865 use multiple DVOs with multiple i2cs */
 149 /* the i915, i945 have a single sDVO i2c bus - which is different */
 150 #define MAX_OUTPUTS 6
 151 /* maximum connectors per crtcs in the mode set */
 152
 153 /* Maximum cursor sizes */
 154 #define GEN2_CURSOR_WIDTH 64
 155 #define GEN2_CURSOR_HEIGHT 64
 156 #define MAX_CURSOR_WIDTH 256
 157 #define MAX_CURSOR_HEIGHT 256
 158
 159 #define INTEL_I2C_BUS_DVO 1
 160 #define INTEL_I2C_BUS_SDVO 2
 161
 162 /* these are outputs from the chip - integrated only
 163    external chips are via DVO or SDVO output */
 164 enum intel_output_type {
 165         INTEL_OUTPUT_UNUSED = 0,
 166         INTEL_OUTPUT_ANALOG = 1,
 167         INTEL_OUTPUT_DVO = 2,
 168         INTEL_OUTPUT_SDVO = 3,
 169         INTEL_OUTPUT_LVDS = 4,
 170         INTEL_OUTPUT_TVOUT = 5,
 171         INTEL_OUTPUT_HDMI = 6,
 172         INTEL_OUTPUT_DP = 7,
 173         INTEL_OUTPUT_EDP = 8,
 174         INTEL_OUTPUT_DSI = 9,
 175         INTEL_OUTPUT_DDI = 10,
 176         INTEL_OUTPUT_DP_MST = 11,
 177 };
 178
 179 #define INTEL_DVO_CHIP_NONE 0
 180 #define INTEL_DVO_CHIP_LVDS 1
 181 #define INTEL_DVO_CHIP_TMDS 2
 182 #define INTEL_DVO_CHIP_TVOUT 4
 183
 184 #define INTEL_DSI_VIDEO_MODE    0
 185 #define INTEL_DSI_COMMAND_MODE  1
 186
 187 struct intel_framebuffer {
 188         struct drm_framebuffer base;
 189         struct drm_i915_gem_object *obj;
 190         struct intel_rotation_info rot_info;
 191
 192         /* for each plane in the normal GTT view */
 193         struct {
 194                 unsigned int x, y;
 195         } normal[2];
 196         /* for each plane in the rotated GTT view */
 197         struct {
 198                 unsigned int x, y;
 199                 unsigned int pitch; /* pixels */
 200         } rotated[2];
 201 };
 202
 203 struct intel_fbdev {
 204         struct drm_fb_helper helper;
 205         struct intel_framebuffer *fb;
 206         struct i915_vma *vma;
 207         unsigned long vma_flags;
 208         async_cookie_t cookie;
 209         int preferred_bpp;
 210 };
 211
 212 struct intel_encoder {
 213         struct drm_encoder base;
 214
 215         enum intel_output_type type;
 216         enum port port;
 217         unsigned int cloneable;
 218         bool (*hotplug)(struct intel_encoder *encoder,
 219                         struct intel_connector *connector);
 220         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 221                                                       struct intel_crtc_state *,
 222                                                       struct drm_connector_state *);
 223         bool (*compute_config)(struct intel_encoder *,
 224                                struct intel_crtc_state *,
 225                                struct drm_connector_state *);
 226         void (*pre_pll_enable)(struct intel_encoder *,
 227                                const struct intel_crtc_state *,
 228                                const struct drm_connector_state *);
 229         void (*pre_enable)(struct intel_encoder *,
 230                            const struct intel_crtc_state *,
 231                            const struct drm_connector_state *);
 232         void (*enable)(struct intel_encoder *,
 233                        const struct intel_crtc_state *,
 234                        const struct drm_connector_state *);
 235         void (*disable)(struct intel_encoder *,
 236                         const struct intel_crtc_state *,
 237                         const struct drm_connector_state *);
 238         void (*post_disable)(struct intel_encoder *,
 239                              const struct intel_crtc_state *,
 240                              const struct drm_connector_state *);
 241         void (*post_pll_disable)(struct intel_encoder *,
 242                                  const struct intel_crtc_state *,
 243                                  const struct drm_connector_state *);
 244         /* Read out the current hw state of this connector, returning true if
 245          * the encoder is active. If the encoder is enabled it also set the pipe
 246          * it is connected to in the pipe parameter. */
 247         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 248         /* Reconstructs the equivalent mode flags for the current hardware
 249          * state. This must be called _after_ display->get_pipe_config has
 250          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 251          * be set correctly before calling this function. */
 252         void (*get_config)(struct intel_encoder *,
 253                            struct intel_crtc_state *pipe_config);
 254         /* Returns a mask of power domains that need to be referenced as part
 255          * of the hardware state readout code. */
 256         u64 (*get_power_domains)(struct intel_encoder *encoder);
 257         /*
 258          * Called during system suspend after all pending requests for the
 259          * encoder are flushed (for example for DP AUX transactions) and
 260          * device interrupts are disabled.
 261          */
 262         void (*suspend)(struct intel_encoder *);
 263         int crtc_mask;
 264         enum hpd_pin hpd_pin;
 265         enum intel_display_power_domain power_domain;
 266         /* for communication with audio component; protected by av_mutex */
 267         const struct drm_connector *audio_connector;
 268 };
 269
 270 struct intel_panel {
 271         struct drm_display_mode *fixed_mode;
 272         struct drm_display_mode *alt_fixed_mode;
 273         struct drm_display_mode *downclock_mode;
 274
 275         /* backlight */
 276         struct {
 277                 bool present;
 278                 u32 level;
 279                 u32 min;
 280                 u32 max;
 281                 bool enabled;
 282                 bool combination_mode;  /* gen 2/4 only */
 283                 bool active_low_pwm;
 284                 bool alternate_pwm_increment;   /* lpt+ */
 285
 286                 /* PWM chip */
 287                 bool util_pin_active_low;       /* bxt+ */
 288                 u8 controller;          /* bxt+ only */
 289                 struct pwm_device *pwm;
 290
 291                 struct backlight_device *device;
 292
 293                 /* Connector and platform specific backlight functions */
 294                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 295                 uint32_t (*get)(struct intel_connector *connector);
 296                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 297                 void (*disable)(const struct drm_connector_state *conn_state);
 298                 void (*enable)(const struct intel_crtc_state *crtc_state,
 299                                const struct drm_connector_state *conn_state);
 300                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 301                                       uint32_t hz);
 302                 void (*power)(struct intel_connector *, bool enable);
 303         } backlight;
 304 };
 305
 306 /*
 307  * This structure serves as a translation layer between the generic HDCP code
 308  * and the bus-specific code. What that means is that HDCP over HDMI differs
 309  * from HDCP over DP, so to account for these differences, we need to
 310  * communicate with the receiver through this shim.
 311  *
 312  * For completeness, the 2 buses differ in the following ways:
 313  *      - DP AUX vs. DDC
 314  *              HDCP registers on the receiver are set via DP AUX for DP, and
 315  *              they are set via DDC for HDMI.
 316  *      - Receiver register offsets
 317  *              The offsets of the registers are different for DP vs. HDMI
 318  *      - Receiver register masks/offsets
 319  *              For instance, the ready bit for the KSV fifo is in a different
 320  *              place on DP vs HDMI
 321  *      - Receiver register names
 322  *              Seriously. In the DP spec, the 16-bit register containing
 323  *              downstream information is called BINFO, on HDMI it's called
 324  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 325  *              with a completely different definition.
 326  *      - KSV FIFO
 327  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 328  *              be read 3 keys at a time
 329  *      - Aksv output
 330  *              Since Aksv is hidden in hardware, there's different procedures
 331  *              to send it over DP AUX vs DDC
 332  */
 333 struct intel_hdcp_shim {
 334         /* Outputs the transmitter's An and Aksv values to the receiver. */
 335         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 336
 337         /* Reads the receiver's key selection vector */
 338         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 339
 340         /*
 341          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 342          * definitions are the same in the respective specs, but the names are
 343          * different. Call it BSTATUS since that's the name the HDMI spec
 344          * uses and it was there first.
 345          */
 346         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 347                             u8 *bstatus);
 348
 349         /* Determines whether a repeater is present downstream */
 350         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 351                                 bool *repeater_present);
 352
 353         /* Reads the receiver's Ri' value */
 354         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 355
 356         /* Determines if the receiver's KSV FIFO is ready for consumption */
 357         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 358                               bool *ksv_ready);
 359
 360         /* Reads the ksv fifo for num_downstream devices */
 361         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 362                              int num_downstream, u8 *ksv_fifo);
 363
 364         /* Reads a 32-bit part of V' from the receiver */
 365         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 366                                  int i, u32 *part);
 367
 368         /* Enables HDCP signalling on the port */
 369         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 370                                  bool enable);
 371
 372         /* Ensures the link is still protected */
 373         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 374
 375         /* Detects panel's hdcp capability. This is optional for HDMI. */
 376         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 377                             bool *hdcp_capable);
 378 };
 379
 380 struct intel_connector {
 381         struct drm_connector base;
 382         /*
 383          * The fixed encoder this connector is connected to.
 384          */
 385         struct intel_encoder *encoder;
 386
 387         /* ACPI device id for ACPI and driver cooperation */
 388         u32 acpi_device_id;
 389
 390         /* Reads out the current hw, returning true if the connector is enabled
 391          * and active (i.e. dpms ON state). */
 392         bool (*get_hw_state)(struct intel_connector *);
 393
 394         /* Panel info for eDP and LVDS */
 395         struct intel_panel panel;
 396
 397         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 398         struct edid *edid;
 399         struct edid *detect_edid;
 400
 401         /* since POLL and HPD connectors may use the same HPD line keep the native
 402            state of connector->polled in case hotplug storm detection changes it */
 403         u8 polled;
 404
 405         void *port; /* store this opaque as its illegal to dereference it */
 406
 407         struct intel_dp *mst_port;
 408
 409         /* Work struct to schedule a uevent on link train failure */
 410         struct work_struct modeset_retry_work;
 411
 412         const struct intel_hdcp_shim *hdcp_shim;
 413         struct mutex hdcp_mutex;
 414         uint64_t hdcp_value; /* protected by hdcp_mutex */
 415         struct delayed_work hdcp_check_work;
 416         struct work_struct hdcp_prop_work;
 417 };
 418
 419 struct intel_digital_connector_state {
 420         struct drm_connector_state base;
 421
 422         enum hdmi_force_audio force_audio;
 423         int broadcast_rgb;
 424 };
 425
 426 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 427
 428 struct dpll {
 429         /* given values */
 430         int n;
 431         int m1, m2;
 432         int p1, p2;
 433         /* derived values */
 434         int     dot;
 435         int     vco;
 436         int     m;
 437         int     p;
 438 };
 439
 440 struct intel_atomic_state {
 441         struct drm_atomic_state base;
 442
 443         struct {
 444                 /*
 445                  * Logical state of cdclk (used for all scaling, watermark,
 446                  * etc. calculations and checks). This is computed as if all
 447                  * enabled crtcs were active.
 448                  */
 449                 struct intel_cdclk_state logical;
 450
 451                 /*
 452                  * Actual state of cdclk, can be different from the logical
 453                  * state only when all crtc's are DPMS off.
 454                  */
 455                 struct intel_cdclk_state actual;
 456         } cdclk;
 457
 458         bool dpll_set, modeset;
 459
 460         /*
 461          * Does this transaction change the pipes that are active?  This mask
 462          * tracks which CRTC's have changed their active state at the end of
 463          * the transaction (not counting the temporary disable during modesets).
 464          * This mask should only be non-zero when intel_state->modeset is true,
 465          * but the converse is not necessarily true; simply changing a mode may
 466          * not flip the final active status of any CRTC's
 467          */
 468         unsigned int active_pipe_changes;
 469
 470         unsigned int active_crtcs;
 471         /* minimum acceptable cdclk for each pipe */
 472         int min_cdclk[I915_MAX_PIPES];
 473         /* minimum acceptable voltage level for each pipe */
 474         u8 min_voltage_level[I915_MAX_PIPES];
 475
 476         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 477
 478         /*
 479          * Current watermarks can't be trusted during hardware readout, so
 480          * don't bother calculating intermediate watermarks.
 481          */
 482         bool skip_intermediate_wm;
 483
 484         /* Gen9+ only */
 485         struct skl_ddb_values wm_results;
 486
 487         struct i915_sw_fence commit_ready;
 488
 489         struct llist_node freed;
 490 };
 491
 492 struct intel_plane_state {
 493         struct drm_plane_state base;
 494         struct i915_vma *vma;
 495         unsigned long flags;
 496 #define PLANE_HAS_FENCE BIT(0)
 497
 498         struct {
 499                 u32 offset;
 500                 int x, y;
 501         } main;
 502         struct {
 503                 u32 offset;
 504                 int x, y;
 505         } aux;
 506
 507         /* plane control register */
 508         u32 ctl;
 509
 510         /* plane color control register */
 511         u32 color_ctl;
 512
 513         /*
 514          * scaler_id
 515          *    = -1 : not using a scaler
 516          *    >=  0 : using a scalers
 517          *
 518          * plane requiring a scaler:
 519          *   - During check_plane, its bit is set in
 520          *     crtc_state->scaler_state.scaler_users by calling helper function
 521          *     update_scaler_plane.
 522          *   - scaler_id indicates the scaler it got assigned.
 523          *
 524          * plane doesn't require a scaler:
 525          *   - this can happen when scaling is no more required or plane simply
 526          *     got disabled.
 527          *   - During check_plane, corresponding bit is reset in
 528          *     crtc_state->scaler_state.scaler_users by calling helper function
 529          *     update_scaler_plane.
 530          */
 531         int scaler_id;
 532
 533         struct drm_intel_sprite_colorkey ckey;
 534 };
 535
 536 struct intel_initial_plane_config {
 537         struct intel_framebuffer *fb;
 538         unsigned int tiling;
 539         int size;
 540         u32 base;
 541 };
 542
 543 #define SKL_MIN_SRC_W 8
 544 #define SKL_MAX_SRC_W 4096
 545 #define SKL_MIN_SRC_H 8
 546 #define SKL_MAX_SRC_H 4096
 547 #define SKL_MIN_DST_W 8
 548 #define SKL_MAX_DST_W 4096
 549 #define SKL_MIN_DST_H 8
 550 #define SKL_MAX_DST_H 4096
 551 #define ICL_MAX_SRC_W 5120
 552 #define ICL_MAX_SRC_H 4096
 553 #define ICL_MAX_DST_W 5120
 554 #define ICL_MAX_DST_H 4096
 555
 556 struct intel_scaler {
 557         int in_use;
 558         uint32_t mode;
 559 };
 560
 561 struct intel_crtc_scaler_state {
 562 #define SKL_NUM_SCALERS 2
 563         struct intel_scaler scalers[SKL_NUM_SCALERS];
 564
 565         /*
 566          * scaler_users: keeps track of users requesting scalers on this crtc.
 567          *
 568          *     If a bit is set, a user is using a scaler.
 569          *     Here user can be a plane or crtc as defined below:
 570          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 571          *       bit 31    - crtc
 572          *
 573          * Instead of creating a new index to cover planes and crtc, using
 574          * existing drm_plane_index for planes which is well less than 31
 575          * planes and bit 31 for crtc. This should be fine to cover all
 576          * our platforms.
 577          *
 578          * intel_atomic_setup_scalers will setup available scalers to users
 579          * requesting scalers. It will gracefully fail if request exceeds
 580          * avilability.
 581          */
 582 #define SKL_CRTC_INDEX 31
 583         unsigned scaler_users;
 584
 585         /* scaler used by crtc for panel fitting purpose */
 586         int scaler_id;
 587 };
 588
 589 /* drm_mode->private_flags */
 590 #define I915_MODE_FLAG_INHERITED 1
 591 /* Flag to get scanline using frame time stamps */
 592 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 593
 594 struct intel_pipe_wm {
 595         struct intel_wm_level wm[5];
 596         uint32_t linetime;
 597         bool fbc_wm_enabled;
 598         bool pipe_enabled;
 599         bool sprites_enabled;
 600         bool sprites_scaled;
 601 };
 602
 603 struct skl_plane_wm {
 604         struct skl_wm_level wm[8];
 605         struct skl_wm_level trans_wm;
 606         bool is_planar;
 607 };
 608
 609 struct skl_pipe_wm {
 610         struct skl_plane_wm planes[I915_MAX_PLANES];
 611         uint32_t linetime;
 612 };
 613
 614 enum vlv_wm_level {
 615         VLV_WM_LEVEL_PM2,
 616         VLV_WM_LEVEL_PM5,
 617         VLV_WM_LEVEL_DDR_DVFS,
 618         NUM_VLV_WM_LEVELS,
 619 };
 620
 621 struct vlv_wm_state {
 622         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 623         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 624         uint8_t num_levels;
 625         bool cxsr;
 626 };
 627
 628 struct vlv_fifo_state {
 629         u16 plane[I915_MAX_PLANES];
 630 };
 631
 632 enum g4x_wm_level {
 633         G4X_WM_LEVEL_NORMAL,
 634         G4X_WM_LEVEL_SR,
 635         G4X_WM_LEVEL_HPLL,
 636         NUM_G4X_WM_LEVELS,
 637 };
 638
 639 struct g4x_wm_state {
 640         struct g4x_pipe_wm wm;
 641         struct g4x_sr_wm sr;
 642         struct g4x_sr_wm hpll;
 643         bool cxsr;
 644         bool hpll_en;
 645         bool fbc_en;
 646 };
 647
 648 struct intel_crtc_wm_state {
 649         union {
 650                 struct {
 651                         /*
 652                          * Intermediate watermarks; these can be
 653                          * programmed immediately since they satisfy
 654                          * both the current configuration we're
 655                          * switching away from and the new
 656                          * configuration we're switching to.
 657                          */
 658                         struct intel_pipe_wm intermediate;
 659
 660                         /*
 661                          * Optimal watermarks, programmed post-vblank
 662                          * when this state is committed.
 663                          */
 664                         struct intel_pipe_wm optimal;
 665                 } ilk;
 666
 667                 struct {
 668                         /* gen9+ only needs 1-step wm programming */
 669                         struct skl_pipe_wm optimal;
 670                         struct skl_ddb_entry ddb;
 671                 } skl;
 672
 673                 struct {
 674                         /* "raw" watermarks (not inverted) */
 675                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 676                         /* intermediate watermarks (inverted) */
 677                         struct vlv_wm_state intermediate;
 678                         /* optimal watermarks (inverted) */
 679                         struct vlv_wm_state optimal;
 680                         /* display FIFO split */
 681                         struct vlv_fifo_state fifo_state;
 682                 } vlv;
 683
 684                 struct {
 685                         /* "raw" watermarks */
 686                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 687                         /* intermediate watermarks */
 688                         struct g4x_wm_state intermediate;
 689                         /* optimal watermarks */
 690                         struct g4x_wm_state optimal;
 691                 } g4x;
 692         };
 693
 694         /*
 695          * Platforms with two-step watermark programming will need to
 696          * update watermark programming post-vblank to switch from the
 697          * safe intermediate watermarks to the optimal final
 698          * watermarks.
 699          */
 700         bool need_postvbl_update;
 701 };
 702
 703 struct intel_crtc_state {
 704         struct drm_crtc_state base;
 705
 706         /**
 707          * quirks - bitfield with hw state readout quirks
 708          *
 709          * For various reasons the hw state readout code might not be able to
 710          * completely faithfully read out the current state. These cases are
 711          * tracked with quirk flags so that fastboot and state checker can act
 712          * accordingly.
 713          */
 714 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 715         unsigned long quirks;
 716
 717         unsigned fb_bits; /* framebuffers to flip */
 718         bool update_pipe; /* can a fast modeset be performed? */
 719         bool disable_cxsr;
 720         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 721         bool fb_changed; /* fb on any of the planes is changed */
 722         bool fifo_changed; /* FIFO split is changed */
 723
 724         /* Pipe source size (ie. panel fitter input size)
 725          * All planes will be positioned inside this space,
 726          * and get clipped at the edges. */
 727         int pipe_src_w, pipe_src_h;
 728
 729         /*
 730          * Pipe pixel rate, adjusted for
 731          * panel fitter/pipe scaler downscaling.
 732          */
 733         unsigned int pixel_rate;
 734
 735         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 736          * between pch encoders and cpu encoders. */
 737         bool has_pch_encoder;
 738
 739         /* Are we sending infoframes on the attached port */
 740         bool has_infoframe;
 741
 742         /* CPU Transcoder for the pipe. Currently this can only differ from the
 743          * pipe on Haswell and later (where we have a special eDP transcoder)
 744          * and Broxton (where we have special DSI transcoders). */
 745         enum transcoder cpu_transcoder;
 746
 747         /*
 748          * Use reduced/limited/broadcast rbg range, compressing from the full
 749          * range fed into the crtcs.
 750          */
 751         bool limited_color_range;
 752
 753         /* Bitmask of encoder types (enum intel_output_type)
 754          * driven by the pipe.
 755          */
 756         unsigned int output_types;
 757
 758         /* Whether we should send NULL infoframes. Required for audio. */
 759         bool has_hdmi_sink;
 760
 761         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 762          * has_dp_encoder is set. */
 763         bool has_audio;
 764
 765         /*
 766          * Enable dithering, used when the selected pipe bpp doesn't match the
 767          * plane bpp.
 768          */
 769         bool dither;
 770
 771         /*
 772          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 773          * compliance video pattern tests.
 774          * Disable dither only if it is a compliance test request for
 775          * 18bpp.
 776          */
 777         bool dither_force_disable;
 778
 779         /* Controls for the clock computation, to override various stages. */
 780         bool clock_set;
 781
 782         /* SDVO TV has a bunch of special case. To make multifunction encoders
 783          * work correctly, we need to track this at runtime.*/
 784         bool sdvo_tv_clock;
 785
 786         /*
 787          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 788          * required. This is set in the 2nd loop of calling encoder's
 789          * ->compute_config if the first pick doesn't work out.
 790          */
 791         bool bw_constrained;
 792
 793         /* Settings for the intel dpll used on pretty much everything but
 794          * haswell. */
 795         struct dpll dpll;
 796
 797         /* Selected dpll when shared or NULL. */
 798         struct intel_shared_dpll *shared_dpll;
 799
 800         /* Actual register state of the dpll, for shared dpll cross-checking. */
 801         struct intel_dpll_hw_state dpll_hw_state;
 802
 803         /* DSI PLL registers */
 804         struct {
 805                 u32 ctrl, div;
 806         } dsi_pll;
 807
 808         int pipe_bpp;
 809         struct intel_link_m_n dp_m_n;
 810
 811         /* m2_n2 for eDP downclock */
 812         struct intel_link_m_n dp_m2_n2;
 813         bool has_drrs;
 814
 815         bool has_psr;
 816         bool has_psr2;
 817
 818         /*
 819          * Frequence the dpll for the port should run at. Differs from the
 820          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 821          * already multiplied by pixel_multiplier.
 822          */
 823         int port_clock;
 824
 825         /* Used by SDVO (and if we ever fix it, HDMI). */
 826         unsigned pixel_multiplier;
 827
 828         uint8_t lane_count;
 829
 830         /*
 831          * Used by platforms having DP/HDMI PHY with programmable lane
 832          * latency optimization.
 833          */
 834         uint8_t lane_lat_optim_mask;
 835
 836         /* minimum acceptable voltage level */
 837         u8 min_voltage_level;
 838
 839         /* Panel fitter controls for gen2-gen4 + VLV */
 840         struct {
 841                 u32 control;
 842                 u32 pgm_ratios;
 843                 u32 lvds_border_bits;
 844         } gmch_pfit;
 845
 846         /* Panel fitter placement and size for Ironlake+ */
 847         struct {
 848                 u32 pos;
 849                 u32 size;
 850                 bool enabled;
 851                 bool force_thru;
 852         } pch_pfit;
 853
 854         /* FDI configuration, only valid if has_pch_encoder is set. */
 855         int fdi_lanes;
 856         struct intel_link_m_n fdi_m_n;
 857
 858         bool ips_enabled;
 859         bool ips_force_disable;
 860
 861         bool enable_fbc;
 862
 863         bool double_wide;
 864
 865         int pbn;
 866
 867         struct intel_crtc_scaler_state scaler_state;
 868
 869         /* w/a for waiting 2 vblanks during crtc enable */
 870         enum pipe hsw_workaround_pipe;
 871
 872         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 873         bool disable_lp_wm;
 874
 875         struct intel_crtc_wm_state wm;
 876
 877         /* Gamma mode programmed on the pipe */
 878         uint32_t gamma_mode;
 879
 880         /* bitmask of visible planes (enum plane_id) */
 881         u8 active_planes;
 882
 883         /* HDMI scrambling status */
 884         bool hdmi_scrambling;
 885
 886         /* HDMI High TMDS char rate ratio */
 887         bool hdmi_high_tmds_clock_ratio;
 888
 889         /* output format is YCBCR 4:2:0 */
 890         bool ycbcr420;
 891 };
 892
 893 struct intel_crtc {
 894         struct drm_crtc base;
 895         enum pipe pipe;
 896         /*
 897          * Whether the crtc and the connected output pipeline is active. Implies
 898          * that crtc->enabled is set, i.e. the current mode configuration has
 899          * some outputs connected to this crtc.
 900          */
 901         bool active;
 902         u8 plane_ids_mask;
 903         unsigned long long enabled_power_domains;
 904         struct intel_overlay *overlay;
 905
 906         struct intel_crtc_state *config;
 907
 908         /* global reset count when the last flip was submitted */
 909         unsigned int reset_count;
 910
 911         /* Access to these should be protected by dev_priv->irq_lock. */
 912         bool cpu_fifo_underrun_disabled;
 913         bool pch_fifo_underrun_disabled;
 914
 915         /* per-pipe watermark state */
 916         struct {
 917                 /* watermarks currently being used  */
 918                 union {
 919                         struct intel_pipe_wm ilk;
 920                         struct vlv_wm_state vlv;
 921                         struct g4x_wm_state g4x;
 922                 } active;
 923         } wm;
 924
 925         int scanline_offset;
 926
 927         struct {
 928                 unsigned start_vbl_count;
 929                 ktime_t start_vbl_time;
 930                 int min_vbl, max_vbl;
 931                 int scanline_start;
 932         } debug;
 933
 934         /* scalers available on this crtc */
 935         int num_scalers;
 936 };
 937
 938 struct intel_plane {
 939         struct drm_plane base;
 940         enum i9xx_plane_id i9xx_plane;
 941         enum plane_id id;
 942         enum pipe pipe;
 943         bool can_scale;
 944         bool has_fbc;
 945         int max_downscale;
 946         uint32_t frontbuffer_bit;
 947
 948         struct {
 949                 u32 base, cntl, size;
 950         } cursor;
 951
 952         /*
 953          * NOTE: Do not place new plane state fields here (e.g., when adding
 954          * new plane properties).  New runtime state should now be placed in
 955          * the intel_plane_state structure and accessed via plane_state.
 956          */
 957
 958         void (*update_plane)(struct intel_plane *plane,
 959                              const struct intel_crtc_state *crtc_state,
 960                              const struct intel_plane_state *plane_state);
 961         void (*disable_plane)(struct intel_plane *plane,
 962                               struct intel_crtc *crtc);
 963         bool (*get_hw_state)(struct intel_plane *plane);
 964         int (*check_plane)(struct intel_plane *plane,
 965                            struct intel_crtc_state *crtc_state,
 966                            struct intel_plane_state *state);
 967 };
 968
 969 struct intel_watermark_params {
 970         u16 fifo_size;
 971         u16 max_wm;
 972         u8 default_wm;
 973         u8 guard_size;
 974         u8 cacheline_size;
 975 };
 976
 977 struct cxsr_latency {
 978         bool is_desktop : 1;
 979         bool is_ddr3 : 1;
 980         u16 fsb_freq;
 981         u16 mem_freq;
 982         u16 display_sr;
 983         u16 display_hpll_disable;
 984         u16 cursor_sr;
 985         u16 cursor_hpll_disable;
 986 };
 987
 988 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 989 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 990 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 991 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 992 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 993 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 994 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 995 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 996 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 997
 998 struct intel_hdmi {
 999         i915_reg_t hdmi_reg;
1000         int ddc_bus;
1001         struct {
1002                 enum drm_dp_dual_mode_type type;
1003                 int max_tmds_clock;
1004         } dp_dual_mode;
1005         bool has_hdmi_sink;
1006         bool has_audio;
1007         bool rgb_quant_range_selectable;
1008         struct intel_connector *attached_connector;
1009 };
1010
1011 struct intel_dp_mst_encoder;
1012 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1013
1014 /*
1015  * enum link_m_n_set:
1016  *      When platform provides two set of M_N registers for dp, we can
1017  *      program them and switch between them incase of DRRS.
1018  *      But When only one such register is provided, we have to program the
1019  *      required divider value on that registers itself based on the DRRS state.
1020  *
1021  * M1_N1        : Program dp_m_n on M1_N1 registers
1022  *                        dp_m2_n2 on M2_N2 registers (If supported)
1023  *
1024  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1025  *                        M2_N2 registers are not supported
1026  */
1027
1028 enum link_m_n_set {
1029         /* Sets the m1_n1 and m2_n2 */
1030         M1_N1 = 0,
1031         M2_N2
1032 };
1033
1034 struct intel_dp_compliance_data {
1035         unsigned long edid;
1036         uint8_t video_pattern;
1037         uint16_t hdisplay, vdisplay;
1038         uint8_t bpc;
1039 };
1040
1041 struct intel_dp_compliance {
1042         unsigned long test_type;
1043         struct intel_dp_compliance_data test_data;
1044         bool test_active;
1045         int test_link_rate;
1046         u8 test_lane_count;
1047 };
1048
1049 struct intel_dp {
1050         i915_reg_t output_reg;
1051         uint32_t DP;
1052         int link_rate;
1053         uint8_t lane_count;
1054         uint8_t sink_count;
1055         bool link_mst;
1056         bool link_trained;
1057         bool has_audio;
1058         bool detect_done;
1059         bool reset_link_params;
1060         enum aux_ch aux_ch;
1061         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1062         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1063         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1064         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1065         /* source rates */
1066         int num_source_rates;
1067         const int *source_rates;
1068         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1069         int num_sink_rates;
1070         int sink_rates[DP_MAX_SUPPORTED_RATES];
1071         bool use_rate_select;
1072         /* intersection of source and sink rates */
1073         int num_common_rates;
1074         int common_rates[DP_MAX_SUPPORTED_RATES];
1075         /* Max lane count for the current link */
1076         int max_link_lane_count;
1077         /* Max rate for the current link */
1078         int max_link_rate;
1079         /* sink or branch descriptor */
1080         struct drm_dp_desc desc;
1081         struct drm_dp_aux aux;
1082         enum intel_display_power_domain aux_power_domain;
1083         uint8_t train_set[4];
1084         int panel_power_up_delay;
1085         int panel_power_down_delay;
1086         int panel_power_cycle_delay;
1087         int backlight_on_delay;
1088         int backlight_off_delay;
1089         struct delayed_work panel_vdd_work;
1090         bool want_panel_vdd;
1091         unsigned long last_power_on;
1092         unsigned long last_backlight_off;
1093         ktime_t panel_power_off_time;
1094
1095         struct notifier_block edp_notifier;
1096
1097         /*
1098          * Pipe whose power sequencer is currently locked into
1099          * this port. Only relevant on VLV/CHV.
1100          */
1101         enum pipe pps_pipe;
1102         /*
1103          * Pipe currently driving the port. Used for preventing
1104          * the use of the PPS for any pipe currentrly driving
1105          * external DP as that will mess things up on VLV.
1106          */
1107         enum pipe active_pipe;
1108         /*
1109          * Set if the sequencer may be reset due to a power transition,
1110          * requiring a reinitialization. Only relevant on BXT.
1111          */
1112         bool pps_reset;
1113         struct edp_power_seq pps_delays;
1114
1115         bool can_mst; /* this port supports mst */
1116         bool is_mst;
1117         int active_mst_links;
1118         /* connector directly attached - won't be use for modeset in mst world */
1119         struct intel_connector *attached_connector;
1120
1121         /* mst connector list */
1122         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1123         struct drm_dp_mst_topology_mgr mst_mgr;
1124
1125         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1126         /*
1127          * This function returns the value we have to program the AUX_CTL
1128          * register with to kick off an AUX transaction.
1129          */
1130         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1131                                      bool has_aux_irq,
1132                                      int send_bytes,
1133                                      uint32_t aux_clock_divider);
1134
1135         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1136         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1137
1138         /* This is called before a link training is starterd */
1139         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1140
1141         /* Displayport compliance testing */
1142         struct intel_dp_compliance compliance;
1143 };
1144
1145 struct intel_lspcon {
1146         bool active;
1147         enum drm_lspcon_mode mode;
1148 };
1149
1150 struct intel_digital_port {
1151         struct intel_encoder base;
1152         u32 saved_port_bits;
1153         struct intel_dp dp;
1154         struct intel_hdmi hdmi;
1155         struct intel_lspcon lspcon;
1156         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1157         bool release_cl2_override;
1158         uint8_t max_lanes;
1159         enum intel_display_power_domain ddi_io_power_domain;
1160
1161         void (*write_infoframe)(struct drm_encoder *encoder,
1162                                 const struct intel_crtc_state *crtc_state,
1163                                 unsigned int type,
1164                                 const void *frame, ssize_t len);
1165         void (*set_infoframes)(struct drm_encoder *encoder,
1166                                bool enable,
1167                                const struct intel_crtc_state *crtc_state,
1168                                const struct drm_connector_state *conn_state);
1169         bool (*infoframe_enabled)(struct drm_encoder *encoder,
1170                                   const struct intel_crtc_state *pipe_config);
1171 };
1172
1173 struct intel_dp_mst_encoder {
1174         struct intel_encoder base;
1175         enum pipe pipe;
1176         struct intel_digital_port *primary;
1177         struct intel_connector *connector;
1178 };
1179
1180 static inline enum dpio_channel
1181 vlv_dport_to_channel(struct intel_digital_port *dport)
1182 {
1183         switch (dport->base.port) {
1184         case PORT_B:
1185         case PORT_D:
1186                 return DPIO_CH0;
1187         case PORT_C:
1188                 return DPIO_CH1;
1189         default:
1190                 BUG();
1191         }
1192 }
1193
1194 static inline enum dpio_phy
1195 vlv_dport_to_phy(struct intel_digital_port *dport)
1196 {
1197         switch (dport->base.port) {
1198         case PORT_B:
1199         case PORT_C:
1200                 return DPIO_PHY0;
1201         case PORT_D:
1202                 return DPIO_PHY1;
1203         default:
1204                 BUG();
1205         }
1206 }
1207
1208 static inline enum dpio_channel
1209 vlv_pipe_to_channel(enum pipe pipe)
1210 {
1211         switch (pipe) {
1212         case PIPE_A:
1213         case PIPE_C:
1214                 return DPIO_CH0;
1215         case PIPE_B:
1216                 return DPIO_CH1;
1217         default:
1218                 BUG();
1219         }
1220 }
1221
1222 static inline struct intel_crtc *
1223 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1224 {
1225         return dev_priv->pipe_to_crtc_mapping[pipe];
1226 }
1227
1228 static inline struct intel_crtc *
1229 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1230 {
1231         return dev_priv->plane_to_crtc_mapping[plane];
1232 }
1233
1234 struct intel_load_detect_pipe {
1235         struct drm_atomic_state *restore_state;
1236 };
1237
1238 static inline struct intel_encoder *
1239 intel_attached_encoder(struct drm_connector *connector)
1240 {
1241         return to_intel_connector(connector)->encoder;
1242 }
1243
1244 static inline struct intel_digital_port *
1245 enc_to_dig_port(struct drm_encoder *encoder)
1246 {
1247         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1248
1249         switch (intel_encoder->type) {
1250         case INTEL_OUTPUT_DDI:
1251                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1252         case INTEL_OUTPUT_DP:
1253         case INTEL_OUTPUT_EDP:
1254         case INTEL_OUTPUT_HDMI:
1255                 return container_of(encoder, struct intel_digital_port,
1256                                     base.base);
1257         default:
1258                 return NULL;
1259         }
1260 }
1261
1262 static inline struct intel_dp_mst_encoder *
1263 enc_to_mst(struct drm_encoder *encoder)
1264 {
1265         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1266 }
1267
1268 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1269 {
1270         return &enc_to_dig_port(encoder)->dp;
1271 }
1272
1273 static inline struct intel_digital_port *
1274 dp_to_dig_port(struct intel_dp *intel_dp)
1275 {
1276         return container_of(intel_dp, struct intel_digital_port, dp);
1277 }
1278
1279 static inline struct intel_lspcon *
1280 dp_to_lspcon(struct intel_dp *intel_dp)
1281 {
1282         return &dp_to_dig_port(intel_dp)->lspcon;
1283 }
1284
1285 static inline struct intel_digital_port *
1286 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1287 {
1288         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1289 }
1290
1291 static inline struct intel_plane_state *
1292 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1293                                  struct intel_plane *plane)
1294 {
1295         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1296                                                                    &plane->base));
1297 }
1298
1299 static inline struct intel_crtc_state *
1300 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1301                                 struct intel_crtc *crtc)
1302 {
1303         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1304                                                                  &crtc->base));
1305 }
1306
1307 static inline struct intel_crtc_state *
1308 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1309                                 struct intel_crtc *crtc)
1310 {
1311         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1312                                                                  &crtc->base));
1313 }
1314
1315 /* intel_fifo_underrun.c */
1316 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1317                                            enum pipe pipe, bool enable);
1318 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1319                                            enum pipe pch_transcoder,
1320                                            bool enable);
1321 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1322                                          enum pipe pipe);
1323 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1324                                          enum pipe pch_transcoder);
1325 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1326 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1327
1328 /* i915_irq.c */
1329 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1330 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1331 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1332 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1333 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1334 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1335 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1336 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1337
1338 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1339                                             u32 mask)
1340 {
1341         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1342 }
1343
1344 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1345 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1346 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1347 {
1348         /*
1349          * We only use drm_irq_uninstall() at unload and VT switch, so
1350          * this is the only thing we need to check.
1351          */
1352         return dev_priv->runtime_pm.irqs_enabled;
1353 }
1354
1355 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1356 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1357                                      u8 pipe_mask);
1358 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1359                                      u8 pipe_mask);
1360 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1361 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1362 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1363
1364 /* intel_crt.c */
1365 void intel_crt_init(struct drm_i915_private *dev_priv);
1366 void intel_crt_reset(struct drm_encoder *encoder);
1367
1368 /* intel_ddi.c */
1369 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1370                                 const struct intel_crtc_state *old_crtc_state,
1371                                 const struct drm_connector_state *old_conn_state);
1372 void hsw_fdi_link_train(struct intel_crtc *crtc,
1373                         const struct intel_crtc_state *crtc_state);
1374 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1375 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1376 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1377 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1378                                        enum transcoder cpu_transcoder);
1379 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1380 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1381 struct intel_encoder *
1382 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1383 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1384 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1385 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1386 void intel_ddi_get_config(struct intel_encoder *encoder,
1387                           struct intel_crtc_state *pipe_config);
1388
1389 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1390                                     bool state);
1391 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1392                                          struct intel_crtc_state *crtc_state);
1393 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1394 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1395 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1396 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1397                                      bool enable);
1398
1399 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1400                                    int plane, unsigned int height);
1401
1402 /* intel_audio.c */
1403 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1404 void intel_audio_codec_enable(struct intel_encoder *encoder,
1405                               const struct intel_crtc_state *crtc_state,
1406                               const struct drm_connector_state *conn_state);
1407 void intel_audio_codec_disable(struct intel_encoder *encoder,
1408                                const struct intel_crtc_state *old_crtc_state,
1409                                const struct drm_connector_state *old_conn_state);
1410 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1411 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1412 void intel_audio_init(struct drm_i915_private *dev_priv);
1413 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1414
1415 /* intel_cdclk.c */
1416 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1417 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1418 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1419 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1420 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1421 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1422 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1423 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1424 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1425 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1426 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1427 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1428 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1429 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1430                                const struct intel_cdclk_state *b);
1431 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1432                          const struct intel_cdclk_state *b);
1433 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1434                      const struct intel_cdclk_state *cdclk_state);
1435 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1436                             const char *context);
1437
1438 /* intel_display.c */
1439 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1440 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1441 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1442 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1443 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1444 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1445                       const char *name, u32 reg, int ref_freq);
1446 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1447                            const char *name, u32 reg);
1448 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1449 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1450 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1451 unsigned int intel_fb_xy_to_linear(int x, int y,
1452                                    const struct intel_plane_state *state,
1453                                    int plane);
1454 void intel_add_fb_offsets(int *x, int *y,
1455                           const struct intel_plane_state *state, int plane);
1456 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1457 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1458 void intel_mark_busy(struct drm_i915_private *dev_priv);
1459 void intel_mark_idle(struct drm_i915_private *dev_priv);
1460 int intel_display_suspend(struct drm_device *dev);
1461 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1462 void intel_encoder_destroy(struct drm_encoder *encoder);
1463 int intel_connector_init(struct intel_connector *);
1464 struct intel_connector *intel_connector_alloc(void);
1465 void intel_connector_free(struct intel_connector *connector);
1466 bool intel_connector_get_hw_state(struct intel_connector *connector);
1467 void intel_connector_attach_encoder(struct intel_connector *connector,
1468                                     struct intel_encoder *encoder);
1469 struct drm_display_mode *
1470 intel_encoder_current_mode(struct intel_encoder *encoder);
1471
1472 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1473 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1474                                       struct drm_file *file_priv);
1475 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1476                                              enum pipe pipe);
1477 static inline bool
1478 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1479                     enum intel_output_type type)
1480 {
1481         return crtc_state->output_types & (1 << type);
1482 }
1483 static inline bool
1484 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1485 {
1486         return crtc_state->output_types &
1487                 ((1 << INTEL_OUTPUT_DP) |
1488                  (1 << INTEL_OUTPUT_DP_MST) |
1489                  (1 << INTEL_OUTPUT_EDP));
1490 }
1491 static inline void
1492 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1493 {
1494         drm_wait_one_vblank(&dev_priv->drm, pipe);
1495 }
1496 static inline void
1497 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1498 {
1499         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1500
1501         if (crtc->active)
1502                 intel_wait_for_vblank(dev_priv, pipe);
1503 }
1504
1505 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1506
1507 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1508 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1509                          struct intel_digital_port *dport,
1510                          unsigned int expected_mask);
1511 int intel_get_load_detect_pipe(struct drm_connector *connector,
1512                                const struct drm_display_mode *mode,
1513                                struct intel_load_detect_pipe *old,
1514                                struct drm_modeset_acquire_ctx *ctx);
1515 void intel_release_load_detect_pipe(struct drm_connector *connector,
1516                                     struct intel_load_detect_pipe *old,
1517                                     struct drm_modeset_acquire_ctx *ctx);
1518 struct i915_vma *
1519 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1520                            unsigned int rotation,
1521                            bool uses_fence,
1522                            unsigned long *out_flags);
1523 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1524 struct drm_framebuffer *
1525 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1526                          struct drm_mode_fb_cmd2 *mode_cmd);
1527 int intel_prepare_plane_fb(struct drm_plane *plane,
1528                            struct drm_plane_state *new_state);
1529 void intel_cleanup_plane_fb(struct drm_plane *plane,
1530                             struct drm_plane_state *old_state);
1531 int intel_plane_atomic_get_property(struct drm_plane *plane,
1532                                     const struct drm_plane_state *state,
1533                                     struct drm_property *property,
1534                                     uint64_t *val);
1535 int intel_plane_atomic_set_property(struct drm_plane *plane,
1536                                     struct drm_plane_state *state,
1537                                     struct drm_property *property,
1538                                     uint64_t val);
1539 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1540                                     struct drm_crtc_state *crtc_state,
1541                                     const struct intel_plane_state *old_plane_state,
1542                                     struct drm_plane_state *plane_state);
1543
1544 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1545                                     enum pipe pipe);
1546
1547 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1548                      const struct dpll *dpll);
1549 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1550 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1551
1552 /* modesetting asserts */
1553 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1554                            enum pipe pipe);
1555 void assert_pll(struct drm_i915_private *dev_priv,
1556                 enum pipe pipe, bool state);
1557 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1558 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1559 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1560 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1561 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1562 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1563                        enum pipe pipe, bool state);
1564 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1565 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1566 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1567 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1568 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1569 u32 intel_compute_tile_offset(int *x, int *y,
1570                               const struct intel_plane_state *state, int plane);
1571 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1572 void intel_finish_reset(struct drm_i915_private *dev_priv);
1573 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1574 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1575 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1576 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1577 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1578 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1579 unsigned int skl_cdclk_get_vco(unsigned int freq);
1580 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1581 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1582 void intel_dp_get_m_n(struct intel_crtc *crtc,
1583                       struct intel_crtc_state *pipe_config);
1584 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1585 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1586 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1587                         struct dpll *best_clock);
1588 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1589
1590 bool intel_crtc_active(struct intel_crtc *crtc);
1591 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1592 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1593 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1594 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1595 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1596                                  struct intel_crtc_state *pipe_config);
1597
1598 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1599 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1600
1601 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1602 {
1603         return i915_ggtt_offset(state->vma);
1604 }
1605
1606 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1607                         const struct intel_plane_state *plane_state);
1608 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1609                   const struct intel_plane_state *plane_state);
1610 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1611 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1612                      unsigned int rotation);
1613 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
1614                             struct intel_plane_state *plane_state);
1615 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1616
1617 /* intel_csr.c */
1618 void intel_csr_ucode_init(struct drm_i915_private *);
1619 void intel_csr_load_program(struct drm_i915_private *);
1620 void intel_csr_ucode_fini(struct drm_i915_private *);
1621 void intel_csr_ucode_suspend(struct drm_i915_private *);
1622 void intel_csr_ucode_resume(struct drm_i915_private *);
1623
1624 /* intel_dp.c */
1625 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1626                    enum port port);
1627 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1628                              struct intel_connector *intel_connector);
1629 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1630                               int link_rate, uint8_t lane_count,
1631                               bool link_mst);
1632 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1633                                             int link_rate, uint8_t lane_count);
1634 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1635 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1636 int intel_dp_retrain_link(struct intel_encoder *encoder,
1637                           struct drm_modeset_acquire_ctx *ctx);
1638 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1639 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1640 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1641 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1642 int intel_dp_sink_crc(struct intel_dp *intel_dp,
1643                       struct intel_crtc_state *crtc_state, u8 *crc);
1644 bool intel_dp_compute_config(struct intel_encoder *encoder,
1645                              struct intel_crtc_state *pipe_config,
1646                              struct drm_connector_state *conn_state);
1647 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1648 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1649 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1650                                   bool long_hpd);
1651 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1652                             const struct drm_connector_state *conn_state);
1653 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1654 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1655 void intel_edp_panel_on(struct intel_dp *intel_dp);
1656 void intel_edp_panel_off(struct intel_dp *intel_dp);
1657 void intel_dp_mst_suspend(struct drm_device *dev);
1658 void intel_dp_mst_resume(struct drm_device *dev);
1659 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1660 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1661 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1662 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1663 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1664 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1665 void intel_plane_destroy(struct drm_plane *plane);
1666 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1667                            const struct intel_crtc_state *crtc_state);
1668 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1669                             const struct intel_crtc_state *crtc_state);
1670 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1671                                unsigned int frontbuffer_bits);
1672 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1673                           unsigned int frontbuffer_bits);
1674
1675 void
1676 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1677                                        uint8_t dp_train_pat);
1678 void
1679 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1680 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1681 uint8_t
1682 intel_dp_voltage_max(struct intel_dp *intel_dp);
1683 uint8_t
1684 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1685 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1686                            uint8_t *link_bw, uint8_t *rate_select);
1687 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1688 bool
1689 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1690
1691 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1692 {
1693         return ~((1 << lane_count) - 1) & 0xf;
1694 }
1695
1696 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1697 int intel_dp_link_required(int pixel_clock, int bpp);
1698 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1699 bool intel_digital_port_connected(struct intel_encoder *encoder);
1700
1701 /* intel_dp_aux_backlight.c */
1702 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1703
1704 /* intel_dp_mst.c */
1705 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1706 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1707 /* intel_dsi.c */
1708 void intel_dsi_init(struct drm_i915_private *dev_priv);
1709
1710 /* intel_dsi_dcs_backlight.c */
1711 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1712
1713 /* intel_dvo.c */
1714 void intel_dvo_init(struct drm_i915_private *dev_priv);
1715 /* intel_hotplug.c */
1716 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1717 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1718                            struct intel_connector *connector);
1719
1720 /* legacy fbdev emulation in intel_fbdev.c */
1721 #ifdef CONFIG_DRM_FBDEV_EMULATION
1722 extern int intel_fbdev_init(struct drm_device *dev);
1723 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1724 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1725 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1726 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1727 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1728 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1729 #else
1730 static inline int intel_fbdev_init(struct drm_device *dev)
1731 {
1732         return 0;
1733 }
1734
1735 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1736 {
1737 }
1738
1739 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1740 {
1741 }
1742
1743 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1744 {
1745 }
1746
1747 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1748 {
1749 }
1750
1751 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1752 {
1753 }
1754
1755 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1756 {
1757 }
1758 #endif
1759
1760 /* intel_fbc.c */
1761 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1762                            struct intel_atomic_state *state);
1763 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1764 void intel_fbc_pre_update(struct intel_crtc *crtc,
1765                           struct intel_crtc_state *crtc_state,
1766                           struct intel_plane_state *plane_state);
1767 void intel_fbc_post_update(struct intel_crtc *crtc);
1768 void intel_fbc_init(struct drm_i915_private *dev_priv);
1769 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1770 void intel_fbc_enable(struct intel_crtc *crtc,
1771                       struct intel_crtc_state *crtc_state,
1772                       struct intel_plane_state *plane_state);
1773 void intel_fbc_disable(struct intel_crtc *crtc);
1774 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1775 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1776                           unsigned int frontbuffer_bits,
1777                           enum fb_op_origin origin);
1778 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1779                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1780 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1781 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1782
1783 /* intel_hdmi.c */
1784 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1785                      enum port port);
1786 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1787                                struct intel_connector *intel_connector);
1788 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1789 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1790                                struct intel_crtc_state *pipe_config,
1791                                struct drm_connector_state *conn_state);
1792 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1793                                        struct drm_connector *connector,
1794                                        bool high_tmds_clock_ratio,
1795                                        bool scrambling);
1796 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1797 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1798
1799
1800 /* intel_lvds.c */
1801 void intel_lvds_init(struct drm_i915_private *dev_priv);
1802 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1803 bool intel_is_dual_link_lvds(struct drm_device *dev);
1804
1805
1806 /* intel_modes.c */
1807 int intel_connector_update_modes(struct drm_connector *connector,
1808                                  struct edid *edid);
1809 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1810 void intel_attach_force_audio_property(struct drm_connector *connector);
1811 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1812 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1813
1814
1815 /* intel_overlay.c */
1816 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1817 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1818 int intel_overlay_switch_off(struct intel_overlay *overlay);
1819 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1820                                   struct drm_file *file_priv);
1821 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1822                               struct drm_file *file_priv);
1823 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1824
1825
1826 /* intel_panel.c */
1827 int intel_panel_init(struct intel_panel *panel,
1828                      struct drm_display_mode *fixed_mode,
1829                      struct drm_display_mode *alt_fixed_mode,
1830                      struct drm_display_mode *downclock_mode);
1831 void intel_panel_fini(struct intel_panel *panel);
1832 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1833                             struct drm_display_mode *adjusted_mode);
1834 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1835                              struct intel_crtc_state *pipe_config,
1836                              int fitting_mode);
1837 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1838                               struct intel_crtc_state *pipe_config,
1839                               int fitting_mode);
1840 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1841                                     u32 level, u32 max);
1842 int intel_panel_setup_backlight(struct drm_connector *connector,
1843                                 enum pipe pipe);
1844 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1845                                   const struct drm_connector_state *conn_state);
1846 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1847 void intel_panel_destroy_backlight(struct drm_connector *connector);
1848 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1849 extern struct drm_display_mode *intel_find_panel_downclock(
1850                                 struct drm_i915_private *dev_priv,
1851                                 struct drm_display_mode *fixed_mode,
1852                                 struct drm_connector *connector);
1853
1854 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1855 int intel_backlight_device_register(struct intel_connector *connector);
1856 void intel_backlight_device_unregister(struct intel_connector *connector);
1857 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1858 static inline int intel_backlight_device_register(struct intel_connector *connector)
1859 {
1860         return 0;
1861 }
1862 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1863 {
1864 }
1865 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1866
1867 /* intel_hdcp.c */
1868 void intel_hdcp_atomic_check(struct drm_connector *connector,
1869                              struct drm_connector_state *old_state,
1870                              struct drm_connector_state *new_state);
1871 int intel_hdcp_init(struct intel_connector *connector,
1872                     const struct intel_hdcp_shim *hdcp_shim);
1873 int intel_hdcp_enable(struct intel_connector *connector);
1874 int intel_hdcp_disable(struct intel_connector *connector);
1875 int intel_hdcp_check_link(struct intel_connector *connector);
1876 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
1877
1878 /* intel_psr.c */
1879 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1880 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
1881 void intel_psr_enable(struct intel_dp *intel_dp,
1882                       const struct intel_crtc_state *crtc_state);
1883 void intel_psr_disable(struct intel_dp *intel_dp,
1884                       const struct intel_crtc_state *old_crtc_state);
1885 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1886                           unsigned frontbuffer_bits,
1887                           enum fb_op_origin origin);
1888 void intel_psr_flush(struct drm_i915_private *dev_priv,
1889                      unsigned frontbuffer_bits,
1890                      enum fb_op_origin origin);
1891 void intel_psr_init(struct drm_i915_private *dev_priv);
1892 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1893                                    unsigned frontbuffer_bits);
1894 void intel_psr_compute_config(struct intel_dp *intel_dp,
1895                               struct intel_crtc_state *crtc_state);
1896
1897 /* intel_runtime_pm.c */
1898 int intel_power_domains_init(struct drm_i915_private *);
1899 void intel_power_domains_fini(struct drm_i915_private *);
1900 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1901 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1902 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1903 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1904 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1905 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1906 const char *
1907 intel_display_power_domain_str(enum intel_display_power_domain domain);
1908
1909 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1910                                     enum intel_display_power_domain domain);
1911 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1912                                       enum intel_display_power_domain domain);
1913 void intel_display_power_get(struct drm_i915_private *dev_priv,
1914                              enum intel_display_power_domain domain);
1915 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1916                                         enum intel_display_power_domain domain);
1917 void intel_display_power_put(struct drm_i915_private *dev_priv,
1918                              enum intel_display_power_domain domain);
1919
1920 static inline void
1921 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1922 {
1923         WARN_ONCE(dev_priv->runtime_pm.suspended,
1924                   "Device suspended during HW access\n");
1925 }
1926
1927 static inline void
1928 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1929 {
1930         assert_rpm_device_not_suspended(dev_priv);
1931         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1932                   "RPM wakelock ref not held during HW access");
1933 }
1934
1935 /**
1936  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1937  * @dev_priv: i915 device instance
1938  *
1939  * This function disable asserts that check if we hold an RPM wakelock
1940  * reference, while keeping the device-not-suspended checks still enabled.
1941  * It's meant to be used only in special circumstances where our rule about
1942  * the wakelock refcount wrt. the device power state doesn't hold. According
1943  * to this rule at any point where we access the HW or want to keep the HW in
1944  * an active state we must hold an RPM wakelock reference acquired via one of
1945  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1946  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1947  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1948  * users should avoid using this function.
1949  *
1950  * Any calls to this function must have a symmetric call to
1951  * enable_rpm_wakeref_asserts().
1952  */
1953 static inline void
1954 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1955 {
1956         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
1957 }
1958
1959 /**
1960  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1961  * @dev_priv: i915 device instance
1962  *
1963  * This function re-enables the RPM assert checks after disabling them with
1964  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1965  * circumstances otherwise its use should be avoided.
1966  *
1967  * Any calls to this function must have a symmetric call to
1968  * disable_rpm_wakeref_asserts().
1969  */
1970 static inline void
1971 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1972 {
1973         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
1974 }
1975
1976 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1977 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1978 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1979 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1980
1981 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1982
1983 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1984                              bool override, unsigned int mask);
1985 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1986                           enum dpio_channel ch, bool override);
1987
1988
1989 /* intel_pm.c */
1990 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1991 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1992 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1993 void intel_update_watermarks(struct intel_crtc *crtc);
1994 void intel_init_pm(struct drm_i915_private *dev_priv);
1995 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1996 void intel_pm_setup(struct drm_i915_private *dev_priv);
1997 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1998 void intel_gpu_ips_teardown(void);
1999 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2000 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2001 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2002 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2003 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2004 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2005 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2006 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2007 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2008 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2009 void g4x_wm_get_hw_state(struct drm_device *dev);
2010 void vlv_wm_get_hw_state(struct drm_device *dev);
2011 void ilk_wm_get_hw_state(struct drm_device *dev);
2012 void skl_wm_get_hw_state(struct drm_device *dev);
2013 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2014                           struct skl_ddb_allocation *ddb /* out */);
2015 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2016                               struct skl_pipe_wm *out);
2017 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2018 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2019 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2020 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2021 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2022 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2023                          const struct skl_wm_level *l2);
2024 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2025                                  const struct skl_ddb_entry **entries,
2026                                  const struct skl_ddb_entry *ddb,
2027                                  int ignore);
2028 bool ilk_disable_lp_wm(struct drm_device *dev);
2029 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2030                                   struct intel_crtc_state *cstate);
2031 void intel_init_ipc(struct drm_i915_private *dev_priv);
2032 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2033
2034 /* intel_sdvo.c */
2035 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2036                      i915_reg_t reg, enum port port);
2037
2038
2039 /* intel_sprite.c */
2040 bool intel_format_is_yuv(u32 format);
2041 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2042                              int usecs);
2043 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2044                                               enum pipe pipe, int plane);
2045 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2046                                     struct drm_file *file_priv);
2047 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2048 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2049 void skl_update_plane(struct intel_plane *plane,
2050                       const struct intel_crtc_state *crtc_state,
2051                       const struct intel_plane_state *plane_state);
2052 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
2053 bool skl_plane_get_hw_state(struct intel_plane *plane);
2054 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2055                        enum pipe pipe, enum plane_id plane_id);
2056
2057 /* intel_tv.c */
2058 void intel_tv_init(struct drm_i915_private *dev_priv);
2059
2060 /* intel_atomic.c */
2061 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2062                                                 const struct drm_connector_state *state,
2063                                                 struct drm_property *property,
2064                                                 uint64_t *val);
2065 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2066                                                 struct drm_connector_state *state,
2067                                                 struct drm_property *property,
2068                                                 uint64_t val);
2069 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2070                                          struct drm_connector_state *new_state);
2071 struct drm_connector_state *
2072 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2073
2074 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2075 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2076                                struct drm_crtc_state *state);
2077 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2078 void intel_atomic_state_clear(struct drm_atomic_state *);
2079
2080 static inline struct intel_crtc_state *
2081 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2082                             struct intel_crtc *crtc)
2083 {
2084         struct drm_crtc_state *crtc_state;
2085         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2086         if (IS_ERR(crtc_state))
2087                 return ERR_CAST(crtc_state);
2088
2089         return to_intel_crtc_state(crtc_state);
2090 }
2091
2092 static inline struct intel_crtc_state *
2093 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
2094                                      struct intel_crtc *crtc)
2095 {
2096         struct drm_crtc_state *crtc_state;
2097
2098         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
2099
2100         if (crtc_state)
2101                 return to_intel_crtc_state(crtc_state);
2102         else
2103                 return NULL;
2104 }
2105
2106 static inline struct intel_plane_state *
2107 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
2108                                       struct intel_plane *plane)
2109 {
2110         struct drm_plane_state *plane_state;
2111
2112         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
2113
2114         return to_intel_plane_state(plane_state);
2115 }
2116
2117 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2118                                struct intel_crtc *intel_crtc,
2119                                struct intel_crtc_state *crtc_state);
2120
2121 /* intel_atomic_plane.c */
2122 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2123 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2124 void intel_plane_destroy_state(struct drm_plane *plane,
2125                                struct drm_plane_state *state);
2126 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2127 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2128                                         struct intel_crtc_state *crtc_state,
2129                                         const struct intel_plane_state *old_plane_state,
2130                                         struct intel_plane_state *intel_state);
2131
2132 /* intel_color.c */
2133 void intel_color_init(struct drm_crtc *crtc);
2134 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2135 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2136 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2137
2138 /* intel_lspcon.c */
2139 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2140 void lspcon_resume(struct intel_lspcon *lspcon);
2141 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2142
2143 /* intel_pipe_crc.c */
2144 int intel_pipe_crc_create(struct drm_minor *minor);
2145 #ifdef CONFIG_DEBUG_FS
2146 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2147                               size_t *values_cnt);
2148 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2149 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2150 #else
2151 #define intel_crtc_set_crc_source NULL
2152 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2153 {
2154 }
2155
2156 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2157 {
2158 }
2159 #endif
2160 extern const struct file_operations i915_display_crc_ctl_fops;
2161 #endif /* __INTEL_DRV_H__ */