drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * _wait_for - magic (register) wait macro
  45  *
  46  * Does the right thing for modeset paths when run under kdgb or similar atomic
  47  * contexts. Note that it's important that we check the condition again after
  48  * having timed out, since the timeout could be due to preemption or similar and
  49  * we've never had a chance to check the condition before the timeout.
  50  *
  51  * TODO: When modesetting has fully transitioned to atomic, the below
  52  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  53  * added.
  54  */
  55 #define _wait_for(COND, US, W) ({ \
  56         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  57         int ret__;                                                      \
  58         for (;;) {                                                      \
  59                 bool expired__ = time_after(jiffies, timeout__);        \
  60                 if (COND) {                                             \
  61                         ret__ = 0;                                      \
  62                         break;                                          \
  63                 }                                                       \
  64                 if (expired__) {                                        \
  65                         ret__ = -ETIMEDOUT;                             \
  66                         break;                                          \
  67                 }                                                       \
  68                 if ((W) && drm_can_sleep()) {                           \
  69                         usleep_range((W), (W)*2);                       \
  70                 } else {                                                \
  71                         cpu_relax();                                    \
  72                 }                                                       \
  73         }                                                               \
  74         ret__;                                                          \
  75 })
  76
  77 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  78
  79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  82 #else
  83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  84 #endif
  85
  86 #define _wait_for_atomic(COND, US, ATOMIC) \
  87 ({ \
  88         int cpu, ret, timeout = (US) * 1000; \
  89         u64 base; \
  90         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  91         if (!(ATOMIC)) { \
  92                 preempt_disable(); \
  93                 cpu = smp_processor_id(); \
  94         } \
  95         base = local_clock(); \
  96         for (;;) { \
  97                 u64 now = local_clock(); \
  98                 if (!(ATOMIC)) \
  99                         preempt_enable(); \
 100                 if (COND) { \
 101                         ret = 0; \
 102                         break; \
 103                 } \
 104                 if (now - base >= timeout) { \
 105                         ret = -ETIMEDOUT; \
 106                         break; \
 107                 } \
 108                 cpu_relax(); \
 109                 if (!(ATOMIC)) { \
 110                         preempt_disable(); \
 111                         if (unlikely(cpu != smp_processor_id())) { \
 112                                 timeout -= now - base; \
 113                                 cpu = smp_processor_id(); \
 114                                 base = local_clock(); \
 115                         } \
 116                 } \
 117         } \
 118         ret; \
 119 })
 120
 121 #define wait_for_us(COND, US) \
 122 ({ \
 123         int ret__; \
 124         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 125         if ((US) > 10) \
 126                 ret__ = _wait_for((COND), (US), 10); \
 127         else \
 128                 ret__ = _wait_for_atomic((COND), (US), 0); \
 129         ret__; \
 130 })
 131
 132 #define wait_for_atomic_us(COND, US) \
 133 ({ \
 134         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 135         BUILD_BUG_ON((US) > 50000); \
 136         _wait_for_atomic((COND), (US), 1); \
 137 })
 138
 139 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 140
 141 #define KHz(x) (1000 * (x))
 142 #define MHz(x) KHz(1000 * (x))
 143
 144 /*
 145  * Display related stuff
 146  */
 147
 148 /* store information about an Ixxx DVO */
 149 /* The i830->i865 use multiple DVOs with multiple i2cs */
 150 /* the i915, i945 have a single sDVO i2c bus - which is different */
 151 #define MAX_OUTPUTS 6
 152 /* maximum connectors per crtcs in the mode set */
 153
 154 /* Maximum cursor sizes */
 155 #define GEN2_CURSOR_WIDTH 64
 156 #define GEN2_CURSOR_HEIGHT 64
 157 #define MAX_CURSOR_WIDTH 256
 158 #define MAX_CURSOR_HEIGHT 256
 159
 160 #define INTEL_I2C_BUS_DVO 1
 161 #define INTEL_I2C_BUS_SDVO 2
 162
 163 /* these are outputs from the chip - integrated only
 164    external chips are via DVO or SDVO output */
 165 enum intel_output_type {
 166         INTEL_OUTPUT_UNUSED = 0,
 167         INTEL_OUTPUT_ANALOG = 1,
 168         INTEL_OUTPUT_DVO = 2,
 169         INTEL_OUTPUT_SDVO = 3,
 170         INTEL_OUTPUT_LVDS = 4,
 171         INTEL_OUTPUT_TVOUT = 5,
 172         INTEL_OUTPUT_HDMI = 6,
 173         INTEL_OUTPUT_DP = 7,
 174         INTEL_OUTPUT_EDP = 8,
 175         INTEL_OUTPUT_DSI = 9,
 176         INTEL_OUTPUT_UNKNOWN = 10,
 177         INTEL_OUTPUT_DP_MST = 11,
 178 };
 179
 180 #define INTEL_DVO_CHIP_NONE 0
 181 #define INTEL_DVO_CHIP_LVDS 1
 182 #define INTEL_DVO_CHIP_TMDS 2
 183 #define INTEL_DVO_CHIP_TVOUT 4
 184
 185 #define INTEL_DSI_VIDEO_MODE    0
 186 #define INTEL_DSI_COMMAND_MODE  1
 187
 188 struct intel_framebuffer {
 189         struct drm_framebuffer base;
 190         struct drm_i915_gem_object *obj;
 191         struct intel_rotation_info rot_info;
 192
 193         /* for each plane in the normal GTT view */
 194         struct {
 195                 unsigned int x, y;
 196         } normal[2];
 197         /* for each plane in the rotated GTT view */
 198         struct {
 199                 unsigned int x, y;
 200                 unsigned int pitch; /* pixels */
 201         } rotated[2];
 202 };
 203
 204 struct intel_fbdev {
 205         struct drm_fb_helper helper;
 206         struct intel_framebuffer *fb;
 207         struct i915_vma *vma;
 208         async_cookie_t cookie;
 209         int preferred_bpp;
 210 };
 211
 212 struct intel_encoder {
 213         struct drm_encoder base;
 214
 215         enum intel_output_type type;
 216         enum port port;
 217         unsigned int cloneable;
 218         void (*hot_plug)(struct intel_encoder *);
 219         bool (*compute_config)(struct intel_encoder *,
 220                                struct intel_crtc_state *,
 221                                struct drm_connector_state *);
 222         void (*pre_pll_enable)(struct intel_encoder *,
 223                                struct intel_crtc_state *,
 224                                struct drm_connector_state *);
 225         void (*pre_enable)(struct intel_encoder *,
 226                            struct intel_crtc_state *,
 227                            struct drm_connector_state *);
 228         void (*enable)(struct intel_encoder *,
 229                        struct intel_crtc_state *,
 230                        struct drm_connector_state *);
 231         void (*disable)(struct intel_encoder *,
 232                         struct intel_crtc_state *,
 233                         struct drm_connector_state *);
 234         void (*post_disable)(struct intel_encoder *,
 235                              struct intel_crtc_state *,
 236                              struct drm_connector_state *);
 237         void (*post_pll_disable)(struct intel_encoder *,
 238                                  struct intel_crtc_state *,
 239                                  struct drm_connector_state *);
 240         /* Read out the current hw state of this connector, returning true if
 241          * the encoder is active. If the encoder is enabled it also set the pipe
 242          * it is connected to in the pipe parameter. */
 243         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 244         /* Reconstructs the equivalent mode flags for the current hardware
 245          * state. This must be called _after_ display->get_pipe_config has
 246          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 247          * be set correctly before calling this function. */
 248         void (*get_config)(struct intel_encoder *,
 249                            struct intel_crtc_state *pipe_config);
 250         /* Returns a mask of power domains that need to be referenced as part
 251          * of the hardware state readout code. */
 252         u64 (*get_power_domains)(struct intel_encoder *encoder);
 253         /*
 254          * Called during system suspend after all pending requests for the
 255          * encoder are flushed (for example for DP AUX transactions) and
 256          * device interrupts are disabled.
 257          */
 258         void (*suspend)(struct intel_encoder *);
 259         int crtc_mask;
 260         enum hpd_pin hpd_pin;
 261         enum intel_display_power_domain power_domain;
 262         /* for communication with audio component; protected by av_mutex */
 263         const struct drm_connector *audio_connector;
 264 };
 265
 266 struct intel_panel {
 267         struct drm_display_mode *fixed_mode;
 268         struct drm_display_mode *downclock_mode;
 269
 270         /* backlight */
 271         struct {
 272                 bool present;
 273                 u32 level;
 274                 u32 min;
 275                 u32 max;
 276                 bool enabled;
 277                 bool combination_mode;  /* gen 2/4 only */
 278                 bool active_low_pwm;
 279                 bool alternate_pwm_increment;   /* lpt+ */
 280
 281                 /* PWM chip */
 282                 bool util_pin_active_low;       /* bxt+ */
 283                 u8 controller;          /* bxt+ only */
 284                 struct pwm_device *pwm;
 285
 286                 struct backlight_device *device;
 287
 288                 /* Connector and platform specific backlight functions */
 289                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 290                 uint32_t (*get)(struct intel_connector *connector);
 291                 void (*set)(struct intel_connector *connector, uint32_t level);
 292                 void (*disable)(struct intel_connector *connector);
 293                 void (*enable)(struct intel_connector *connector);
 294                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 295                                       uint32_t hz);
 296                 void (*power)(struct intel_connector *, bool enable);
 297         } backlight;
 298 };
 299
 300 struct intel_connector {
 301         struct drm_connector base;
 302         /*
 303          * The fixed encoder this connector is connected to.
 304          */
 305         struct intel_encoder *encoder;
 306
 307         /* ACPI device id for ACPI and driver cooperation */
 308         u32 acpi_device_id;
 309
 310         /* Reads out the current hw, returning true if the connector is enabled
 311          * and active (i.e. dpms ON state). */
 312         bool (*get_hw_state)(struct intel_connector *);
 313
 314         /* Panel info for eDP and LVDS */
 315         struct intel_panel panel;
 316
 317         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 318         struct edid *edid;
 319         struct edid *detect_edid;
 320
 321         /* since POLL and HPD connectors may use the same HPD line keep the native
 322            state of connector->polled in case hotplug storm detection changes it */
 323         u8 polled;
 324
 325         void *port; /* store this opaque as its illegal to dereference it */
 326
 327         struct intel_dp *mst_port;
 328
 329         /* Work struct to schedule a uevent on link train failure */
 330         struct work_struct modeset_retry_work;
 331 };
 332
 333 struct dpll {
 334         /* given values */
 335         int n;
 336         int m1, m2;
 337         int p1, p2;
 338         /* derived values */
 339         int     dot;
 340         int     vco;
 341         int     m;
 342         int     p;
 343 };
 344
 345 struct intel_atomic_state {
 346         struct drm_atomic_state base;
 347
 348         struct {
 349                 /*
 350                  * Logical state of cdclk (used for all scaling, watermark,
 351                  * etc. calculations and checks). This is computed as if all
 352                  * enabled crtcs were active.
 353                  */
 354                 struct intel_cdclk_state logical;
 355
 356                 /*
 357                  * Actual state of cdclk, can be different from the logical
 358                  * state only when all crtc's are DPMS off.
 359                  */
 360                 struct intel_cdclk_state actual;
 361         } cdclk;
 362
 363         bool dpll_set, modeset;
 364
 365         /*
 366          * Does this transaction change the pipes that are active?  This mask
 367          * tracks which CRTC's have changed their active state at the end of
 368          * the transaction (not counting the temporary disable during modesets).
 369          * This mask should only be non-zero when intel_state->modeset is true,
 370          * but the converse is not necessarily true; simply changing a mode may
 371          * not flip the final active status of any CRTC's
 372          */
 373         unsigned int active_pipe_changes;
 374
 375         unsigned int active_crtcs;
 376         unsigned int min_pixclk[I915_MAX_PIPES];
 377
 378         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 379
 380         /*
 381          * Current watermarks can't be trusted during hardware readout, so
 382          * don't bother calculating intermediate watermarks.
 383          */
 384         bool skip_intermediate_wm;
 385
 386         /* Gen9+ only */
 387         struct skl_wm_values wm_results;
 388
 389         struct i915_sw_fence commit_ready;
 390
 391         struct llist_node freed;
 392 };
 393
 394 struct intel_plane_state {
 395         struct drm_plane_state base;
 396         struct drm_rect clip;
 397         struct i915_vma *vma;
 398
 399         struct {
 400                 u32 offset;
 401                 int x, y;
 402         } main;
 403         struct {
 404                 u32 offset;
 405                 int x, y;
 406         } aux;
 407
 408         /* plane control register */
 409         u32 ctl;
 410
 411         /*
 412          * scaler_id
 413          *    = -1 : not using a scaler
 414          *    >=  0 : using a scalers
 415          *
 416          * plane requiring a scaler:
 417          *   - During check_plane, its bit is set in
 418          *     crtc_state->scaler_state.scaler_users by calling helper function
 419          *     update_scaler_plane.
 420          *   - scaler_id indicates the scaler it got assigned.
 421          *
 422          * plane doesn't require a scaler:
 423          *   - this can happen when scaling is no more required or plane simply
 424          *     got disabled.
 425          *   - During check_plane, corresponding bit is reset in
 426          *     crtc_state->scaler_state.scaler_users by calling helper function
 427          *     update_scaler_plane.
 428          */
 429         int scaler_id;
 430
 431         struct drm_intel_sprite_colorkey ckey;
 432 };
 433
 434 struct intel_initial_plane_config {
 435         struct intel_framebuffer *fb;
 436         unsigned int tiling;
 437         int size;
 438         u32 base;
 439 };
 440
 441 #define SKL_MIN_SRC_W 8
 442 #define SKL_MAX_SRC_W 4096
 443 #define SKL_MIN_SRC_H 8
 444 #define SKL_MAX_SRC_H 4096
 445 #define SKL_MIN_DST_W 8
 446 #define SKL_MAX_DST_W 4096
 447 #define SKL_MIN_DST_H 8
 448 #define SKL_MAX_DST_H 4096
 449
 450 struct intel_scaler {
 451         int in_use;
 452         uint32_t mode;
 453 };
 454
 455 struct intel_crtc_scaler_state {
 456 #define SKL_NUM_SCALERS 2
 457         struct intel_scaler scalers[SKL_NUM_SCALERS];
 458
 459         /*
 460          * scaler_users: keeps track of users requesting scalers on this crtc.
 461          *
 462          *     If a bit is set, a user is using a scaler.
 463          *     Here user can be a plane or crtc as defined below:
 464          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 465          *       bit 31    - crtc
 466          *
 467          * Instead of creating a new index to cover planes and crtc, using
 468          * existing drm_plane_index for planes which is well less than 31
 469          * planes and bit 31 for crtc. This should be fine to cover all
 470          * our platforms.
 471          *
 472          * intel_atomic_setup_scalers will setup available scalers to users
 473          * requesting scalers. It will gracefully fail if request exceeds
 474          * avilability.
 475          */
 476 #define SKL_CRTC_INDEX 31
 477         unsigned scaler_users;
 478
 479         /* scaler used by crtc for panel fitting purpose */
 480         int scaler_id;
 481 };
 482
 483 /* drm_mode->private_flags */
 484 #define I915_MODE_FLAG_INHERITED 1
 485
 486 struct intel_pipe_wm {
 487         struct intel_wm_level wm[5];
 488         struct intel_wm_level raw_wm[5];
 489         uint32_t linetime;
 490         bool fbc_wm_enabled;
 491         bool pipe_enabled;
 492         bool sprites_enabled;
 493         bool sprites_scaled;
 494 };
 495
 496 struct skl_plane_wm {
 497         struct skl_wm_level wm[8];
 498         struct skl_wm_level trans_wm;
 499 };
 500
 501 struct skl_pipe_wm {
 502         struct skl_plane_wm planes[I915_MAX_PLANES];
 503         uint32_t linetime;
 504 };
 505
 506 enum vlv_wm_level {
 507         VLV_WM_LEVEL_PM2,
 508         VLV_WM_LEVEL_PM5,
 509         VLV_WM_LEVEL_DDR_DVFS,
 510         NUM_VLV_WM_LEVELS,
 511 };
 512
 513 struct vlv_wm_state {
 514         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 515         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 516         uint8_t num_levels;
 517         bool cxsr;
 518 };
 519
 520 struct vlv_fifo_state {
 521         u16 plane[I915_MAX_PLANES];
 522 };
 523
 524 enum g4x_wm_level {
 525         G4X_WM_LEVEL_NORMAL,
 526         G4X_WM_LEVEL_SR,
 527         G4X_WM_LEVEL_HPLL,
 528         NUM_G4X_WM_LEVELS,
 529 };
 530
 531 struct g4x_wm_state {
 532         struct g4x_pipe_wm wm;
 533         struct g4x_sr_wm sr;
 534         struct g4x_sr_wm hpll;
 535         bool cxsr;
 536         bool hpll_en;
 537         bool fbc_en;
 538 };
 539
 540 struct intel_crtc_wm_state {
 541         union {
 542                 struct {
 543                         /*
 544                          * Intermediate watermarks; these can be
 545                          * programmed immediately since they satisfy
 546                          * both the current configuration we're
 547                          * switching away from and the new
 548                          * configuration we're switching to.
 549                          */
 550                         struct intel_pipe_wm intermediate;
 551
 552                         /*
 553                          * Optimal watermarks, programmed post-vblank
 554                          * when this state is committed.
 555                          */
 556                         struct intel_pipe_wm optimal;
 557                 } ilk;
 558
 559                 struct {
 560                         /* gen9+ only needs 1-step wm programming */
 561                         struct skl_pipe_wm optimal;
 562                         struct skl_ddb_entry ddb;
 563                 } skl;
 564
 565                 struct {
 566                         /* "raw" watermarks (not inverted) */
 567                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 568                         /* intermediate watermarks (inverted) */
 569                         struct vlv_wm_state intermediate;
 570                         /* optimal watermarks (inverted) */
 571                         struct vlv_wm_state optimal;
 572                         /* display FIFO split */
 573                         struct vlv_fifo_state fifo_state;
 574                 } vlv;
 575
 576                 struct {
 577                         /* "raw" watermarks */
 578                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 579                         /* intermediate watermarks */
 580                         struct g4x_wm_state intermediate;
 581                         /* optimal watermarks */
 582                         struct g4x_wm_state optimal;
 583                 } g4x;
 584         };
 585
 586         /*
 587          * Platforms with two-step watermark programming will need to
 588          * update watermark programming post-vblank to switch from the
 589          * safe intermediate watermarks to the optimal final
 590          * watermarks.
 591          */
 592         bool need_postvbl_update;
 593 };
 594
 595 struct intel_crtc_state {
 596         struct drm_crtc_state base;
 597
 598         /**
 599          * quirks - bitfield with hw state readout quirks
 600          *
 601          * For various reasons the hw state readout code might not be able to
 602          * completely faithfully read out the current state. These cases are
 603          * tracked with quirk flags so that fastboot and state checker can act
 604          * accordingly.
 605          */
 606 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 607         unsigned long quirks;
 608
 609         unsigned fb_bits; /* framebuffers to flip */
 610         bool update_pipe; /* can a fast modeset be performed? */
 611         bool disable_cxsr;
 612         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 613         bool fb_changed; /* fb on any of the planes is changed */
 614         bool fifo_changed; /* FIFO split is changed */
 615
 616         /* Pipe source size (ie. panel fitter input size)
 617          * All planes will be positioned inside this space,
 618          * and get clipped at the edges. */
 619         int pipe_src_w, pipe_src_h;
 620
 621         /*
 622          * Pipe pixel rate, adjusted for
 623          * panel fitter/pipe scaler downscaling.
 624          */
 625         unsigned int pixel_rate;
 626
 627         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 628          * between pch encoders and cpu encoders. */
 629         bool has_pch_encoder;
 630
 631         /* Are we sending infoframes on the attached port */
 632         bool has_infoframe;
 633
 634         /* CPU Transcoder for the pipe. Currently this can only differ from the
 635          * pipe on Haswell and later (where we have a special eDP transcoder)
 636          * and Broxton (where we have special DSI transcoders). */
 637         enum transcoder cpu_transcoder;
 638
 639         /*
 640          * Use reduced/limited/broadcast rbg range, compressing from the full
 641          * range fed into the crtcs.
 642          */
 643         bool limited_color_range;
 644
 645         /* Bitmask of encoder types (enum intel_output_type)
 646          * driven by the pipe.
 647          */
 648         unsigned int output_types;
 649
 650         /* Whether we should send NULL infoframes. Required for audio. */
 651         bool has_hdmi_sink;
 652
 653         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 654          * has_dp_encoder is set. */
 655         bool has_audio;
 656
 657         /*
 658          * Enable dithering, used when the selected pipe bpp doesn't match the
 659          * plane bpp.
 660          */
 661         bool dither;
 662
 663         /*
 664          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 665          * compliance video pattern tests.
 666          * Disable dither only if it is a compliance test request for
 667          * 18bpp.
 668          */
 669         bool dither_force_disable;
 670
 671         /* Controls for the clock computation, to override various stages. */
 672         bool clock_set;
 673
 674         /* SDVO TV has a bunch of special case. To make multifunction encoders
 675          * work correctly, we need to track this at runtime.*/
 676         bool sdvo_tv_clock;
 677
 678         /*
 679          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 680          * required. This is set in the 2nd loop of calling encoder's
 681          * ->compute_config if the first pick doesn't work out.
 682          */
 683         bool bw_constrained;
 684
 685         /* Settings for the intel dpll used on pretty much everything but
 686          * haswell. */
 687         struct dpll dpll;
 688
 689         /* Selected dpll when shared or NULL. */
 690         struct intel_shared_dpll *shared_dpll;
 691
 692         /* Actual register state of the dpll, for shared dpll cross-checking. */
 693         struct intel_dpll_hw_state dpll_hw_state;
 694
 695         /* DSI PLL registers */
 696         struct {
 697                 u32 ctrl, div;
 698         } dsi_pll;
 699
 700         int pipe_bpp;
 701         struct intel_link_m_n dp_m_n;
 702
 703         /* m2_n2 for eDP downclock */
 704         struct intel_link_m_n dp_m2_n2;
 705         bool has_drrs;
 706
 707         /*
 708          * Frequence the dpll for the port should run at. Differs from the
 709          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 710          * already multiplied by pixel_multiplier.
 711          */
 712         int port_clock;
 713
 714         /* Used by SDVO (and if we ever fix it, HDMI). */
 715         unsigned pixel_multiplier;
 716
 717         uint8_t lane_count;
 718
 719         /*
 720          * Used by platforms having DP/HDMI PHY with programmable lane
 721          * latency optimization.
 722          */
 723         uint8_t lane_lat_optim_mask;
 724
 725         /* Panel fitter controls for gen2-gen4 + VLV */
 726         struct {
 727                 u32 control;
 728                 u32 pgm_ratios;
 729                 u32 lvds_border_bits;
 730         } gmch_pfit;
 731
 732         /* Panel fitter placement and size for Ironlake+ */
 733         struct {
 734                 u32 pos;
 735                 u32 size;
 736                 bool enabled;
 737                 bool force_thru;
 738         } pch_pfit;
 739
 740         /* FDI configuration, only valid if has_pch_encoder is set. */
 741         int fdi_lanes;
 742         struct intel_link_m_n fdi_m_n;
 743
 744         bool ips_enabled;
 745
 746         bool enable_fbc;
 747
 748         bool double_wide;
 749
 750         int pbn;
 751
 752         struct intel_crtc_scaler_state scaler_state;
 753
 754         /* w/a for waiting 2 vblanks during crtc enable */
 755         enum pipe hsw_workaround_pipe;
 756
 757         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 758         bool disable_lp_wm;
 759
 760         struct intel_crtc_wm_state wm;
 761
 762         /* Gamma mode programmed on the pipe */
 763         uint32_t gamma_mode;
 764
 765         /* bitmask of visible planes (enum plane_id) */
 766         u8 active_planes;
 767
 768         /* HDMI scrambling status */
 769         bool hdmi_scrambling;
 770
 771         /* HDMI High TMDS char rate ratio */
 772         bool hdmi_high_tmds_clock_ratio;
 773 };
 774
 775 struct intel_crtc {
 776         struct drm_crtc base;
 777         enum pipe pipe;
 778         enum plane plane;
 779         u8 lut_r[256], lut_g[256], lut_b[256];
 780         /*
 781          * Whether the crtc and the connected output pipeline is active. Implies
 782          * that crtc->enabled is set, i.e. the current mode configuration has
 783          * some outputs connected to this crtc.
 784          */
 785         bool active;
 786         bool lowfreq_avail;
 787         u8 plane_ids_mask;
 788         unsigned long long enabled_power_domains;
 789         struct intel_overlay *overlay;
 790         struct intel_flip_work *flip_work;
 791
 792         atomic_t unpin_work_count;
 793
 794         /* Display surface base address adjustement for pageflips. Note that on
 795          * gen4+ this only adjusts up to a tile, offsets within a tile are
 796          * handled in the hw itself (with the TILEOFF register). */
 797         u32 dspaddr_offset;
 798         int adjusted_x;
 799         int adjusted_y;
 800
 801         struct intel_crtc_state *config;
 802
 803         /* global reset count when the last flip was submitted */
 804         unsigned int reset_count;
 805
 806         /* Access to these should be protected by dev_priv->irq_lock. */
 807         bool cpu_fifo_underrun_disabled;
 808         bool pch_fifo_underrun_disabled;
 809
 810         /* per-pipe watermark state */
 811         struct {
 812                 /* watermarks currently being used  */
 813                 union {
 814                         struct intel_pipe_wm ilk;
 815                         struct vlv_wm_state vlv;
 816                         struct g4x_wm_state g4x;
 817                 } active;
 818         } wm;
 819
 820         int scanline_offset;
 821
 822         struct {
 823                 unsigned start_vbl_count;
 824                 ktime_t start_vbl_time;
 825                 int min_vbl, max_vbl;
 826                 int scanline_start;
 827         } debug;
 828
 829         /* scalers available on this crtc */
 830         int num_scalers;
 831 };
 832
 833 struct intel_plane {
 834         struct drm_plane base;
 835         u8 plane;
 836         enum plane_id id;
 837         enum pipe pipe;
 838         bool can_scale;
 839         int max_downscale;
 840         uint32_t frontbuffer_bit;
 841
 842         struct {
 843                 u32 base, cntl, size;
 844         } cursor;
 845
 846         /*
 847          * NOTE: Do not place new plane state fields here (e.g., when adding
 848          * new plane properties).  New runtime state should now be placed in
 849          * the intel_plane_state structure and accessed via plane_state.
 850          */
 851
 852         void (*update_plane)(struct intel_plane *plane,
 853                              const struct intel_crtc_state *crtc_state,
 854                              const struct intel_plane_state *plane_state);
 855         void (*disable_plane)(struct intel_plane *plane,
 856                               struct intel_crtc *crtc);
 857         int (*check_plane)(struct intel_plane *plane,
 858                            struct intel_crtc_state *crtc_state,
 859                            struct intel_plane_state *state);
 860 };
 861
 862 struct intel_watermark_params {
 863         u16 fifo_size;
 864         u16 max_wm;
 865         u8 default_wm;
 866         u8 guard_size;
 867         u8 cacheline_size;
 868 };
 869
 870 struct cxsr_latency {
 871         bool is_desktop : 1;
 872         bool is_ddr3 : 1;
 873         u16 fsb_freq;
 874         u16 mem_freq;
 875         u16 display_sr;
 876         u16 display_hpll_disable;
 877         u16 cursor_sr;
 878         u16 cursor_hpll_disable;
 879 };
 880
 881 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 882 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 883 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 884 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 885 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 886 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 887 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 888 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 889 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 890
 891 struct intel_hdmi {
 892         i915_reg_t hdmi_reg;
 893         int ddc_bus;
 894         struct {
 895                 enum drm_dp_dual_mode_type type;
 896                 int max_tmds_clock;
 897         } dp_dual_mode;
 898         bool limited_color_range;
 899         bool color_range_auto;
 900         bool has_hdmi_sink;
 901         bool has_audio;
 902         enum hdmi_force_audio force_audio;
 903         bool rgb_quant_range_selectable;
 904         struct intel_connector *attached_connector;
 905         void (*write_infoframe)(struct drm_encoder *encoder,
 906                                 const struct intel_crtc_state *crtc_state,
 907                                 enum hdmi_infoframe_type type,
 908                                 const void *frame, ssize_t len);
 909         void (*set_infoframes)(struct drm_encoder *encoder,
 910                                bool enable,
 911                                const struct intel_crtc_state *crtc_state,
 912                                const struct drm_connector_state *conn_state);
 913         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 914                                   const struct intel_crtc_state *pipe_config);
 915 };
 916
 917 struct intel_dp_mst_encoder;
 918 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 919
 920 /*
 921  * enum link_m_n_set:
 922  *      When platform provides two set of M_N registers for dp, we can
 923  *      program them and switch between them incase of DRRS.
 924  *      But When only one such register is provided, we have to program the
 925  *      required divider value on that registers itself based on the DRRS state.
 926  *
 927  * M1_N1        : Program dp_m_n on M1_N1 registers
 928  *                        dp_m2_n2 on M2_N2 registers (If supported)
 929  *
 930  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 931  *                        M2_N2 registers are not supported
 932  */
 933
 934 enum link_m_n_set {
 935         /* Sets the m1_n1 and m2_n2 */
 936         M1_N1 = 0,
 937         M2_N2
 938 };
 939
 940 struct intel_dp_desc {
 941         u8 oui[3];
 942         u8 device_id[6];
 943         u8 hw_rev;
 944         u8 sw_major_rev;
 945         u8 sw_minor_rev;
 946 } __packed;
 947
 948 struct intel_dp_compliance_data {
 949         unsigned long edid;
 950         uint8_t video_pattern;
 951         uint16_t hdisplay, vdisplay;
 952         uint8_t bpc;
 953 };
 954
 955 struct intel_dp_compliance {
 956         unsigned long test_type;
 957         struct intel_dp_compliance_data test_data;
 958         bool test_active;
 959         int test_link_rate;
 960         u8 test_lane_count;
 961 };
 962
 963 struct intel_dp {
 964         i915_reg_t output_reg;
 965         i915_reg_t aux_ch_ctl_reg;
 966         i915_reg_t aux_ch_data_reg[5];
 967         uint32_t DP;
 968         int link_rate;
 969         uint8_t lane_count;
 970         uint8_t sink_count;
 971         bool link_mst;
 972         bool has_audio;
 973         bool detect_done;
 974         bool channel_eq_status;
 975         bool reset_link_params;
 976         enum hdmi_force_audio force_audio;
 977         bool limited_color_range;
 978         bool color_range_auto;
 979         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 980         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 981         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 982         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 983         /* source rates */
 984         int num_source_rates;
 985         const int *source_rates;
 986         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
 987         int num_sink_rates;
 988         int sink_rates[DP_MAX_SUPPORTED_RATES];
 989         bool use_rate_select;
 990         /* intersection of source and sink rates */
 991         int num_common_rates;
 992         int common_rates[DP_MAX_SUPPORTED_RATES];
 993         /* Max lane count for the current link */
 994         int max_link_lane_count;
 995         /* Max rate for the current link */
 996         int max_link_rate;
 997         /* sink or branch descriptor */
 998         struct intel_dp_desc desc;
 999         struct drm_dp_aux aux;
1000         enum intel_display_power_domain aux_power_domain;
1001         uint8_t train_set[4];
1002         int panel_power_up_delay;
1003         int panel_power_down_delay;
1004         int panel_power_cycle_delay;
1005         int backlight_on_delay;
1006         int backlight_off_delay;
1007         struct delayed_work panel_vdd_work;
1008         bool want_panel_vdd;
1009         unsigned long last_power_on;
1010         unsigned long last_backlight_off;
1011         ktime_t panel_power_off_time;
1012
1013         struct notifier_block edp_notifier;
1014
1015         /*
1016          * Pipe whose power sequencer is currently locked into
1017          * this port. Only relevant on VLV/CHV.
1018          */
1019         enum pipe pps_pipe;
1020         /*
1021          * Pipe currently driving the port. Used for preventing
1022          * the use of the PPS for any pipe currentrly driving
1023          * external DP as that will mess things up on VLV.
1024          */
1025         enum pipe active_pipe;
1026         /*
1027          * Set if the sequencer may be reset due to a power transition,
1028          * requiring a reinitialization. Only relevant on BXT.
1029          */
1030         bool pps_reset;
1031         struct edp_power_seq pps_delays;
1032
1033         bool can_mst; /* this port supports mst */
1034         bool is_mst;
1035         int active_mst_links;
1036         /* connector directly attached - won't be use for modeset in mst world */
1037         struct intel_connector *attached_connector;
1038
1039         /* mst connector list */
1040         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1041         struct drm_dp_mst_topology_mgr mst_mgr;
1042
1043         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1044         /*
1045          * This function returns the value we have to program the AUX_CTL
1046          * register with to kick off an AUX transaction.
1047          */
1048         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1049                                      bool has_aux_irq,
1050                                      int send_bytes,
1051                                      uint32_t aux_clock_divider);
1052
1053         /* This is called before a link training is starterd */
1054         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1055
1056         /* Displayport compliance testing */
1057         struct intel_dp_compliance compliance;
1058 };
1059
1060 struct intel_lspcon {
1061         bool active;
1062         enum drm_lspcon_mode mode;
1063 };
1064
1065 struct intel_digital_port {
1066         struct intel_encoder base;
1067         enum port port;
1068         u32 saved_port_bits;
1069         struct intel_dp dp;
1070         struct intel_hdmi hdmi;
1071         struct intel_lspcon lspcon;
1072         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1073         bool release_cl2_override;
1074         uint8_t max_lanes;
1075         enum intel_display_power_domain ddi_io_power_domain;
1076 };
1077
1078 struct intel_dp_mst_encoder {
1079         struct intel_encoder base;
1080         enum pipe pipe;
1081         struct intel_digital_port *primary;
1082         struct intel_connector *connector;
1083 };
1084
1085 static inline enum dpio_channel
1086 vlv_dport_to_channel(struct intel_digital_port *dport)
1087 {
1088         switch (dport->port) {
1089         case PORT_B:
1090         case PORT_D:
1091                 return DPIO_CH0;
1092         case PORT_C:
1093                 return DPIO_CH1;
1094         default:
1095                 BUG();
1096         }
1097 }
1098
1099 static inline enum dpio_phy
1100 vlv_dport_to_phy(struct intel_digital_port *dport)
1101 {
1102         switch (dport->port) {
1103         case PORT_B:
1104         case PORT_C:
1105                 return DPIO_PHY0;
1106         case PORT_D:
1107                 return DPIO_PHY1;
1108         default:
1109                 BUG();
1110         }
1111 }
1112
1113 static inline enum dpio_channel
1114 vlv_pipe_to_channel(enum pipe pipe)
1115 {
1116         switch (pipe) {
1117         case PIPE_A:
1118         case PIPE_C:
1119                 return DPIO_CH0;
1120         case PIPE_B:
1121                 return DPIO_CH1;
1122         default:
1123                 BUG();
1124         }
1125 }
1126
1127 static inline struct intel_crtc *
1128 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1129 {
1130         return dev_priv->pipe_to_crtc_mapping[pipe];
1131 }
1132
1133 static inline struct intel_crtc *
1134 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1135 {
1136         return dev_priv->plane_to_crtc_mapping[plane];
1137 }
1138
1139 struct intel_flip_work {
1140         struct work_struct unpin_work;
1141         struct work_struct mmio_work;
1142
1143         struct drm_crtc *crtc;
1144         struct i915_vma *old_vma;
1145         struct drm_framebuffer *old_fb;
1146         struct drm_i915_gem_object *pending_flip_obj;
1147         struct drm_pending_vblank_event *event;
1148         atomic_t pending;
1149         u32 flip_count;
1150         u32 gtt_offset;
1151         struct drm_i915_gem_request *flip_queued_req;
1152         u32 flip_queued_vblank;
1153         u32 flip_ready_vblank;
1154         unsigned int rotation;
1155 };
1156
1157 struct intel_load_detect_pipe {
1158         struct drm_atomic_state *restore_state;
1159 };
1160
1161 static inline struct intel_encoder *
1162 intel_attached_encoder(struct drm_connector *connector)
1163 {
1164         return to_intel_connector(connector)->encoder;
1165 }
1166
1167 static inline struct intel_digital_port *
1168 enc_to_dig_port(struct drm_encoder *encoder)
1169 {
1170         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1171
1172         switch (intel_encoder->type) {
1173         case INTEL_OUTPUT_UNKNOWN:
1174                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1175         case INTEL_OUTPUT_DP:
1176         case INTEL_OUTPUT_EDP:
1177         case INTEL_OUTPUT_HDMI:
1178                 return container_of(encoder, struct intel_digital_port,
1179                                     base.base);
1180         default:
1181                 return NULL;
1182         }
1183 }
1184
1185 static inline struct intel_dp_mst_encoder *
1186 enc_to_mst(struct drm_encoder *encoder)
1187 {
1188         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1189 }
1190
1191 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1192 {
1193         return &enc_to_dig_port(encoder)->dp;
1194 }
1195
1196 static inline struct intel_digital_port *
1197 dp_to_dig_port(struct intel_dp *intel_dp)
1198 {
1199         return container_of(intel_dp, struct intel_digital_port, dp);
1200 }
1201
1202 static inline struct intel_lspcon *
1203 dp_to_lspcon(struct intel_dp *intel_dp)
1204 {
1205         return &dp_to_dig_port(intel_dp)->lspcon;
1206 }
1207
1208 static inline struct intel_digital_port *
1209 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1210 {
1211         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1212 }
1213
1214 /* intel_fifo_underrun.c */
1215 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1216                                            enum pipe pipe, bool enable);
1217 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1218                                            enum transcoder pch_transcoder,
1219                                            bool enable);
1220 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1221                                          enum pipe pipe);
1222 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1223                                          enum transcoder pch_transcoder);
1224 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1225 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1226
1227 /* i915_irq.c */
1228 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1229 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1230 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1231 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1232 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1233 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1234 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1235 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1236 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1237 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1238
1239 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1240                                             u32 mask)
1241 {
1242         return mask & ~i915->rps.pm_intrmsk_mbz;
1243 }
1244
1245 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1246 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1247 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1248 {
1249         /*
1250          * We only use drm_irq_uninstall() at unload and VT switch, so
1251          * this is the only thing we need to check.
1252          */
1253         return dev_priv->pm.irqs_enabled;
1254 }
1255
1256 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1257 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1258                                      unsigned int pipe_mask);
1259 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1260                                      unsigned int pipe_mask);
1261 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1262 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1263 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1264
1265 /* intel_crt.c */
1266 void intel_crt_init(struct drm_i915_private *dev_priv);
1267 void intel_crt_reset(struct drm_encoder *encoder);
1268
1269 /* intel_ddi.c */
1270 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1271                                 struct intel_crtc_state *old_crtc_state,
1272                                 struct drm_connector_state *old_conn_state);
1273 void hsw_fdi_link_train(struct intel_crtc *crtc,
1274                         const struct intel_crtc_state *crtc_state);
1275 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1276 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1277 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1278 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1279 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1280                                        enum transcoder cpu_transcoder);
1281 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1282 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1283 struct intel_encoder *
1284 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1285 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1286 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1287 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1288 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1289                                  struct intel_crtc *intel_crtc);
1290 void intel_ddi_get_config(struct intel_encoder *encoder,
1291                           struct intel_crtc_state *pipe_config);
1292
1293 void intel_ddi_clock_get(struct intel_encoder *encoder,
1294                          struct intel_crtc_state *pipe_config);
1295 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1296                                     bool state);
1297 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1298 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1299
1300 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1301                                    int plane, unsigned int height);
1302
1303 /* intel_audio.c */
1304 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1305 void intel_audio_codec_enable(struct intel_encoder *encoder,
1306                               const struct intel_crtc_state *crtc_state,
1307                               const struct drm_connector_state *conn_state);
1308 void intel_audio_codec_disable(struct intel_encoder *encoder);
1309 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1310 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1311 void intel_audio_init(struct drm_i915_private *dev_priv);
1312 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1313
1314 /* intel_cdclk.c */
1315 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1316 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1317 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1318 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1319 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1320 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1321 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1322 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1323 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1324                                const struct intel_cdclk_state *b);
1325 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1326                      const struct intel_cdclk_state *cdclk_state);
1327
1328 /* intel_display.c */
1329 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1330 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1331 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1332 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1333                       const char *name, u32 reg, int ref_freq);
1334 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1335                            const char *name, u32 reg);
1336 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1337 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1338 extern const struct drm_plane_funcs intel_plane_funcs;
1339 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1340 unsigned int intel_fb_xy_to_linear(int x, int y,
1341                                    const struct intel_plane_state *state,
1342                                    int plane);
1343 void intel_add_fb_offsets(int *x, int *y,
1344                           const struct intel_plane_state *state, int plane);
1345 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1346 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1347 void intel_mark_busy(struct drm_i915_private *dev_priv);
1348 void intel_mark_idle(struct drm_i915_private *dev_priv);
1349 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1350 int intel_display_suspend(struct drm_device *dev);
1351 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1352 void intel_encoder_destroy(struct drm_encoder *encoder);
1353 int intel_connector_init(struct intel_connector *);
1354 struct intel_connector *intel_connector_alloc(void);
1355 bool intel_connector_get_hw_state(struct intel_connector *connector);
1356 void intel_connector_attach_encoder(struct intel_connector *connector,
1357                                     struct intel_encoder *encoder);
1358 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1359                                              struct drm_crtc *crtc);
1360 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1361 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1362                                 struct drm_file *file_priv);
1363 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1364                                              enum pipe pipe);
1365 static inline bool
1366 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1367                     enum intel_output_type type)
1368 {
1369         return crtc_state->output_types & (1 << type);
1370 }
1371 static inline bool
1372 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1373 {
1374         return crtc_state->output_types &
1375                 ((1 << INTEL_OUTPUT_DP) |
1376                  (1 << INTEL_OUTPUT_DP_MST) |
1377                  (1 << INTEL_OUTPUT_EDP));
1378 }
1379 static inline void
1380 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1381 {
1382         drm_wait_one_vblank(&dev_priv->drm, pipe);
1383 }
1384 static inline void
1385 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1386 {
1387         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1388
1389         if (crtc->active)
1390                 intel_wait_for_vblank(dev_priv, pipe);
1391 }
1392
1393 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1394
1395 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1396 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1397                          struct intel_digital_port *dport,
1398                          unsigned int expected_mask);
1399 int intel_get_load_detect_pipe(struct drm_connector *connector,
1400                                struct drm_display_mode *mode,
1401                                struct intel_load_detect_pipe *old,
1402                                struct drm_modeset_acquire_ctx *ctx);
1403 void intel_release_load_detect_pipe(struct drm_connector *connector,
1404                                     struct intel_load_detect_pipe *old,
1405                                     struct drm_modeset_acquire_ctx *ctx);
1406 struct i915_vma *
1407 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1408 void intel_unpin_fb_vma(struct i915_vma *vma);
1409 struct drm_framebuffer *
1410 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1411                          struct drm_mode_fb_cmd2 *mode_cmd);
1412 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1413 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1414 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1415 int intel_prepare_plane_fb(struct drm_plane *plane,
1416                            struct drm_plane_state *new_state);
1417 void intel_cleanup_plane_fb(struct drm_plane *plane,
1418                             struct drm_plane_state *old_state);
1419 int intel_plane_atomic_get_property(struct drm_plane *plane,
1420                                     const struct drm_plane_state *state,
1421                                     struct drm_property *property,
1422                                     uint64_t *val);
1423 int intel_plane_atomic_set_property(struct drm_plane *plane,
1424                                     struct drm_plane_state *state,
1425                                     struct drm_property *property,
1426                                     uint64_t val);
1427 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1428                                     struct drm_plane_state *plane_state);
1429
1430 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1431                                     enum pipe pipe);
1432
1433 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1434                      const struct dpll *dpll);
1435 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1436 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1437
1438 /* modesetting asserts */
1439 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1440                            enum pipe pipe);
1441 void assert_pll(struct drm_i915_private *dev_priv,
1442                 enum pipe pipe, bool state);
1443 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1444 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1445 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1446 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1447 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1448 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1449                        enum pipe pipe, bool state);
1450 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1451 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1452 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1453 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1454 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1455 u32 intel_compute_tile_offset(int *x, int *y,
1456                               const struct intel_plane_state *state, int plane);
1457 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1458 void intel_finish_reset(struct drm_i915_private *dev_priv);
1459 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1460 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1461 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1462 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1463 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1464 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1465 unsigned int skl_cdclk_get_vco(unsigned int freq);
1466 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1467 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1468 void intel_dp_get_m_n(struct intel_crtc *crtc,
1469                       struct intel_crtc_state *pipe_config);
1470 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1471 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1472 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1473                         struct dpll *best_clock);
1474 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1475
1476 bool intel_crtc_active(struct intel_crtc *crtc);
1477 void hsw_enable_ips(struct intel_crtc *crtc);
1478 void hsw_disable_ips(struct intel_crtc *crtc);
1479 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1480 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1481                                  struct intel_crtc_state *pipe_config);
1482
1483 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1484 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1485
1486 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1487 {
1488         return i915_ggtt_offset(state->vma);
1489 }
1490
1491 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1492                   const struct intel_plane_state *plane_state);
1493 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1494                      unsigned int rotation);
1495 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1496 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1497
1498 /* intel_csr.c */
1499 void intel_csr_ucode_init(struct drm_i915_private *);
1500 void intel_csr_load_program(struct drm_i915_private *);
1501 void intel_csr_ucode_fini(struct drm_i915_private *);
1502 void intel_csr_ucode_suspend(struct drm_i915_private *);
1503 void intel_csr_ucode_resume(struct drm_i915_private *);
1504
1505 /* intel_dp.c */
1506 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1507                    enum port port);
1508 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1509                              struct intel_connector *intel_connector);
1510 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1511                               int link_rate, uint8_t lane_count,
1512                               bool link_mst);
1513 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1514                                             int link_rate, uint8_t lane_count);
1515 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1516 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1517 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1518 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1519 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1520 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1521 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1522 bool intel_dp_compute_config(struct intel_encoder *encoder,
1523                              struct intel_crtc_state *pipe_config,
1524                              struct drm_connector_state *conn_state);
1525 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1526 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1527                                   bool long_hpd);
1528 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1529 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1530 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1531 void intel_edp_panel_on(struct intel_dp *intel_dp);
1532 void intel_edp_panel_off(struct intel_dp *intel_dp);
1533 void intel_dp_mst_suspend(struct drm_device *dev);
1534 void intel_dp_mst_resume(struct drm_device *dev);
1535 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1536 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1537 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1538 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1539 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1540 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1541 void intel_plane_destroy(struct drm_plane *plane);
1542 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1543                            struct intel_crtc_state *crtc_state);
1544 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1545                            struct intel_crtc_state *crtc_state);
1546 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1547                                unsigned int frontbuffer_bits);
1548 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1549                           unsigned int frontbuffer_bits);
1550
1551 void
1552 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1553                                        uint8_t dp_train_pat);
1554 void
1555 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1556 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1557 uint8_t
1558 intel_dp_voltage_max(struct intel_dp *intel_dp);
1559 uint8_t
1560 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1561 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1562                            uint8_t *link_bw, uint8_t *rate_select);
1563 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1564 bool
1565 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1566
1567 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1568 {
1569         return ~((1 << lane_count) - 1) & 0xf;
1570 }
1571
1572 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1573 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1574                           struct intel_dp_desc *desc);
1575 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1576 int intel_dp_link_required(int pixel_clock, int bpp);
1577 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1578 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1579                                   struct intel_digital_port *port);
1580
1581 /* intel_dp_aux_backlight.c */
1582 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1583
1584 /* intel_dp_mst.c */
1585 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1586 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1587 /* intel_dsi.c */
1588 void intel_dsi_init(struct drm_i915_private *dev_priv);
1589
1590 /* intel_dsi_dcs_backlight.c */
1591 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1592
1593 /* intel_dvo.c */
1594 void intel_dvo_init(struct drm_i915_private *dev_priv);
1595 /* intel_hotplug.c */
1596 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1597
1598
1599 /* legacy fbdev emulation in intel_fbdev.c */
1600 #ifdef CONFIG_DRM_FBDEV_EMULATION
1601 extern int intel_fbdev_init(struct drm_device *dev);
1602 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1603 extern void intel_fbdev_fini(struct drm_device *dev);
1604 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1605 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1606 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1607 #else
1608 static inline int intel_fbdev_init(struct drm_device *dev)
1609 {
1610         return 0;
1611 }
1612
1613 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1614 {
1615 }
1616
1617 static inline void intel_fbdev_fini(struct drm_device *dev)
1618 {
1619 }
1620
1621 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1622 {
1623 }
1624
1625 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1626 {
1627 }
1628
1629 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1630 {
1631 }
1632 #endif
1633
1634 /* intel_fbc.c */
1635 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1636                            struct drm_atomic_state *state);
1637 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1638 void intel_fbc_pre_update(struct intel_crtc *crtc,
1639                           struct intel_crtc_state *crtc_state,
1640                           struct intel_plane_state *plane_state);
1641 void intel_fbc_post_update(struct intel_crtc *crtc);
1642 void intel_fbc_init(struct drm_i915_private *dev_priv);
1643 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1644 void intel_fbc_enable(struct intel_crtc *crtc,
1645                       struct intel_crtc_state *crtc_state,
1646                       struct intel_plane_state *plane_state);
1647 void intel_fbc_disable(struct intel_crtc *crtc);
1648 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1649 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1650                           unsigned int frontbuffer_bits,
1651                           enum fb_op_origin origin);
1652 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1653                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1654 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1655 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1656
1657 /* intel_hdmi.c */
1658 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1659                      enum port port);
1660 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1661                                struct intel_connector *intel_connector);
1662 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1663 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1664                                struct intel_crtc_state *pipe_config,
1665                                struct drm_connector_state *conn_state);
1666 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1667                                        struct drm_connector *connector,
1668                                        bool high_tmds_clock_ratio,
1669                                        bool scrambling);
1670 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1671
1672
1673 /* intel_lvds.c */
1674 void intel_lvds_init(struct drm_i915_private *dev_priv);
1675 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1676 bool intel_is_dual_link_lvds(struct drm_device *dev);
1677
1678
1679 /* intel_modes.c */
1680 int intel_connector_update_modes(struct drm_connector *connector,
1681                                  struct edid *edid);
1682 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1683 void intel_attach_force_audio_property(struct drm_connector *connector);
1684 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1685 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1686
1687
1688 /* intel_overlay.c */
1689 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1690 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1691 int intel_overlay_switch_off(struct intel_overlay *overlay);
1692 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1693                                   struct drm_file *file_priv);
1694 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1695                               struct drm_file *file_priv);
1696 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1697
1698
1699 /* intel_panel.c */
1700 int intel_panel_init(struct intel_panel *panel,
1701                      struct drm_display_mode *fixed_mode,
1702                      struct drm_display_mode *downclock_mode);
1703 void intel_panel_fini(struct intel_panel *panel);
1704 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1705                             struct drm_display_mode *adjusted_mode);
1706 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1707                              struct intel_crtc_state *pipe_config,
1708                              int fitting_mode);
1709 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1710                               struct intel_crtc_state *pipe_config,
1711                               int fitting_mode);
1712 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1713                                     u32 level, u32 max);
1714 int intel_panel_setup_backlight(struct drm_connector *connector,
1715                                 enum pipe pipe);
1716 void intel_panel_enable_backlight(struct intel_connector *connector);
1717 void intel_panel_disable_backlight(struct intel_connector *connector);
1718 void intel_panel_destroy_backlight(struct drm_connector *connector);
1719 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1720 extern struct drm_display_mode *intel_find_panel_downclock(
1721                                 struct drm_i915_private *dev_priv,
1722                                 struct drm_display_mode *fixed_mode,
1723                                 struct drm_connector *connector);
1724
1725 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1726 int intel_backlight_device_register(struct intel_connector *connector);
1727 void intel_backlight_device_unregister(struct intel_connector *connector);
1728 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1729 static int intel_backlight_device_register(struct intel_connector *connector)
1730 {
1731         return 0;
1732 }
1733 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1734 {
1735 }
1736 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1737
1738
1739 /* intel_psr.c */
1740 void intel_psr_enable(struct intel_dp *intel_dp);
1741 void intel_psr_disable(struct intel_dp *intel_dp);
1742 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1743                           unsigned frontbuffer_bits);
1744 void intel_psr_flush(struct drm_i915_private *dev_priv,
1745                      unsigned frontbuffer_bits,
1746                      enum fb_op_origin origin);
1747 void intel_psr_init(struct drm_i915_private *dev_priv);
1748 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1749                                    unsigned frontbuffer_bits);
1750
1751 /* intel_runtime_pm.c */
1752 int intel_power_domains_init(struct drm_i915_private *);
1753 void intel_power_domains_fini(struct drm_i915_private *);
1754 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1755 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1756 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1757 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1758 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1759 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1760 const char *
1761 intel_display_power_domain_str(enum intel_display_power_domain domain);
1762
1763 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1764                                     enum intel_display_power_domain domain);
1765 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1766                                       enum intel_display_power_domain domain);
1767 void intel_display_power_get(struct drm_i915_private *dev_priv,
1768                              enum intel_display_power_domain domain);
1769 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1770                                         enum intel_display_power_domain domain);
1771 void intel_display_power_put(struct drm_i915_private *dev_priv,
1772                              enum intel_display_power_domain domain);
1773
1774 static inline void
1775 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1776 {
1777         WARN_ONCE(dev_priv->pm.suspended,
1778                   "Device suspended during HW access\n");
1779 }
1780
1781 static inline void
1782 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1783 {
1784         assert_rpm_device_not_suspended(dev_priv);
1785         WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
1786                   "RPM wakelock ref not held during HW access");
1787 }
1788
1789 /**
1790  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1791  * @dev_priv: i915 device instance
1792  *
1793  * This function disable asserts that check if we hold an RPM wakelock
1794  * reference, while keeping the device-not-suspended checks still enabled.
1795  * It's meant to be used only in special circumstances where our rule about
1796  * the wakelock refcount wrt. the device power state doesn't hold. According
1797  * to this rule at any point where we access the HW or want to keep the HW in
1798  * an active state we must hold an RPM wakelock reference acquired via one of
1799  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1800  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1801  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1802  * users should avoid using this function.
1803  *
1804  * Any calls to this function must have a symmetric call to
1805  * enable_rpm_wakeref_asserts().
1806  */
1807 static inline void
1808 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1809 {
1810         atomic_inc(&dev_priv->pm.wakeref_count);
1811 }
1812
1813 /**
1814  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1815  * @dev_priv: i915 device instance
1816  *
1817  * This function re-enables the RPM assert checks after disabling them with
1818  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1819  * circumstances otherwise its use should be avoided.
1820  *
1821  * Any calls to this function must have a symmetric call to
1822  * disable_rpm_wakeref_asserts().
1823  */
1824 static inline void
1825 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1826 {
1827         atomic_dec(&dev_priv->pm.wakeref_count);
1828 }
1829
1830 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1831 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1832 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1833 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1834
1835 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1836
1837 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1838                              bool override, unsigned int mask);
1839 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1840                           enum dpio_channel ch, bool override);
1841
1842
1843 /* intel_pm.c */
1844 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1845 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1846 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1847 void intel_update_watermarks(struct intel_crtc *crtc);
1848 void intel_init_pm(struct drm_i915_private *dev_priv);
1849 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1850 void intel_pm_setup(struct drm_i915_private *dev_priv);
1851 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1852 void intel_gpu_ips_teardown(void);
1853 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1854 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1855 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1856 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1857 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1858 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1859 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1860 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1861 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1862 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1863 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1864                     struct intel_rps_client *rps,
1865                     unsigned long submitted);
1866 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1867 void g4x_wm_get_hw_state(struct drm_device *dev);
1868 void vlv_wm_get_hw_state(struct drm_device *dev);
1869 void ilk_wm_get_hw_state(struct drm_device *dev);
1870 void skl_wm_get_hw_state(struct drm_device *dev);
1871 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1872                           struct skl_ddb_allocation *ddb /* out */);
1873 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1874                               struct skl_pipe_wm *out);
1875 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1876 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1877 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1878 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1879 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1880 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1881                          const struct skl_wm_level *l2);
1882 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1883                                  const struct skl_ddb_entry *ddb,
1884                                  int ignore);
1885 bool ilk_disable_lp_wm(struct drm_device *dev);
1886 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1887 static inline int intel_enable_rc6(void)
1888 {
1889         return i915.enable_rc6;
1890 }
1891
1892 /* intel_sdvo.c */
1893 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1894                      i915_reg_t reg, enum port port);
1895
1896
1897 /* intel_sprite.c */
1898 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1899                              int usecs);
1900 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1901                                               enum pipe pipe, int plane);
1902 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1903                               struct drm_file *file_priv);
1904 void intel_pipe_update_start(struct intel_crtc *crtc);
1905 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1906
1907 /* intel_tv.c */
1908 void intel_tv_init(struct drm_i915_private *dev_priv);
1909
1910 /* intel_atomic.c */
1911 int intel_connector_atomic_get_property(struct drm_connector *connector,
1912                                         const struct drm_connector_state *state,
1913                                         struct drm_property *property,
1914                                         uint64_t *val);
1915 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1916 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1917                                struct drm_crtc_state *state);
1918 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1919 void intel_atomic_state_clear(struct drm_atomic_state *);
1920
1921 static inline struct intel_crtc_state *
1922 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1923                             struct intel_crtc *crtc)
1924 {
1925         struct drm_crtc_state *crtc_state;
1926         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1927         if (IS_ERR(crtc_state))
1928                 return ERR_CAST(crtc_state);
1929
1930         return to_intel_crtc_state(crtc_state);
1931 }
1932
1933 static inline struct intel_crtc_state *
1934 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1935                                      struct intel_crtc *crtc)
1936 {
1937         struct drm_crtc_state *crtc_state;
1938
1939         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1940
1941         if (crtc_state)
1942                 return to_intel_crtc_state(crtc_state);
1943         else
1944                 return NULL;
1945 }
1946
1947 static inline struct intel_plane_state *
1948 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1949                                       struct intel_plane *plane)
1950 {
1951         struct drm_plane_state *plane_state;
1952
1953         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1954
1955         return to_intel_plane_state(plane_state);
1956 }
1957
1958 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1959                                struct intel_crtc *intel_crtc,
1960                                struct intel_crtc_state *crtc_state);
1961
1962 /* intel_atomic_plane.c */
1963 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1964 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1965 void intel_plane_destroy_state(struct drm_plane *plane,
1966                                struct drm_plane_state *state);
1967 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1968 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1969                                         struct intel_plane_state *intel_state);
1970
1971 /* intel_color.c */
1972 void intel_color_init(struct drm_crtc *crtc);
1973 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1974 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1975 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1976
1977 /* intel_lspcon.c */
1978 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1979 void lspcon_resume(struct intel_lspcon *lspcon);
1980 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
1981
1982 /* intel_pipe_crc.c */
1983 int intel_pipe_crc_create(struct drm_minor *minor);
1984 #ifdef CONFIG_DEBUG_FS
1985 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
1986                               size_t *values_cnt);
1987 #else
1988 #define intel_crtc_set_crc_source NULL
1989 #endif
1990 extern const struct file_operations i915_display_crc_ctl_fops;
1991 #endif /* __INTEL_DRV_H__ */