drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include "intel_drv.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  45 #define DP_DPRX_ESI_LEN 14
  46
  47 /* Compliance test status bits  */
  48 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  49 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  50 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52
  53 struct dp_link_dpll {
  54         int clock;
  55         struct dpll dpll;
  56 };
  57
  58 static const struct dp_link_dpll gen4_dpll[] = {
  59         { 162000,
  60                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  61         { 270000,
  62                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  63 };
  64
  65 static const struct dp_link_dpll pch_dpll[] = {
  66         { 162000,
  67                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  68         { 270000,
  69                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  70 };
  71
  72 static const struct dp_link_dpll vlv_dpll[] = {
  73         { 162000,
  74                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  75         { 270000,
  76                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  77 };
  78
  79 /*
  80  * CHV supports eDP 1.4 that have  more link rates.
  81  * Below only provides the fixed rate but exclude variable rate.
  82  */
  83 static const struct dp_link_dpll chv_dpll[] = {
  84         /*
  85          * CHV requires to program fractional division for m2.
  86          * m2 is stored in fixed point format using formula below
  87          * (m2_int << 22) | m2_fraction
  88          */
  89         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  90                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  91         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  92                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  93         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  94                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  95 };
  96
  97 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  98                                   324000, 432000, 540000 };
  99 static const int skl_rates[] = { 162000, 216000, 270000,
 100                                   324000, 432000, 540000 };
 101 static const int cnl_rates[] = { 162000, 216000, 270000,
 102                                  324000, 432000, 540000,
 103                                  648000, 810000 };
 104 static const int default_rates[] = { 162000, 270000, 540000 };
 105
 106 /**
 107  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 108  * @intel_dp: DP struct
 109  *
 110  * If a CPU or PCH DP output is attached to an eDP panel, this function
 111  * will return true, and false otherwise.
 112  */
 113 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 114 {
 115         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 116
 117         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 118 }
 119
 120 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 121 {
 122         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 123
 124         return intel_dig_port->base.base.dev;
 125 }
 126
 127 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 128 {
 129         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 130 }
 131
 132 static void intel_dp_link_down(struct intel_dp *intel_dp);
 133 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 134 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 135 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 136 static void vlv_steal_power_sequencer(struct drm_device *dev,
 137                                       enum pipe pipe);
 138 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 139
 140 static int intel_dp_num_rates(u8 link_bw_code)
 141 {
 142         switch (link_bw_code) {
 143         default:
 144                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 145                      link_bw_code);
 146         case DP_LINK_BW_1_62:
 147                 return 1;
 148         case DP_LINK_BW_2_7:
 149                 return 2;
 150         case DP_LINK_BW_5_4:
 151                 return 3;
 152         }
 153 }
 154
 155 /* update sink rates from dpcd */
 156 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 157 {
 158         int i, num_rates;
 159
 160         num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 161
 162         for (i = 0; i < num_rates; i++)
 163                 intel_dp->sink_rates[i] = default_rates[i];
 164
 165         intel_dp->num_sink_rates = num_rates;
 166 }
 167
 168 /* Theoretical max between source and sink */
 169 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 170 {
 171         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 172 }
 173
 174 /* Theoretical max between source and sink */
 175 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 176 {
 177         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 178         int source_max = intel_dig_port->max_lanes;
 179         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 180
 181         return min(source_max, sink_max);
 182 }
 183
 184 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 185 {
 186         return intel_dp->max_link_lane_count;
 187 }
 188
 189 int
 190 intel_dp_link_required(int pixel_clock, int bpp)
 191 {
 192         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 193         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 194 }
 195
 196 int
 197 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 198 {
 199         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 200          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 201          * is transmitted every LS_Clk per lane, there is no need to account for
 202          * the channel encoding that is done in the PHY layer here.
 203          */
 204
 205         return max_link_clock * max_lanes;
 206 }
 207
 208 static int
 209 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 210 {
 211         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 212         struct intel_encoder *encoder = &intel_dig_port->base;
 213         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 214         int max_dotclk = dev_priv->max_dotclk_freq;
 215         int ds_max_dotclk;
 216
 217         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 218
 219         if (type != DP_DS_PORT_TYPE_VGA)
 220                 return max_dotclk;
 221
 222         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 223                                                     intel_dp->downstream_ports);
 224
 225         if (ds_max_dotclk != 0)
 226                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 227
 228         return max_dotclk;
 229 }
 230
 231 static void
 232 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 233 {
 234         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 235         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 236         enum port port = dig_port->port;
 237         const int *source_rates;
 238         int size;
 239         u32 voltage;
 240
 241         /* This should only be done once */
 242         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 243
 244         if (IS_GEN9_LP(dev_priv)) {
 245                 source_rates = bxt_rates;
 246                 size = ARRAY_SIZE(bxt_rates);
 247         } else if (IS_CANNONLAKE(dev_priv)) {
 248                 source_rates = cnl_rates;
 249                 size = ARRAY_SIZE(cnl_rates);
 250                 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 251                 if (port == PORT_A || port == PORT_D ||
 252                     voltage == VOLTAGE_INFO_0_85V)
 253                         size -= 2;
 254         } else if (IS_GEN9_BC(dev_priv)) {
 255                 source_rates = skl_rates;
 256                 size = ARRAY_SIZE(skl_rates);
 257         } else {
 258                 source_rates = default_rates;
 259                 size = ARRAY_SIZE(default_rates);
 260         }
 261
 262         /* This depends on the fact that 5.4 is last value in the array */
 263         if (!intel_dp_source_supports_hbr2(intel_dp))
 264                 size--;
 265
 266         intel_dp->source_rates = source_rates;
 267         intel_dp->num_source_rates = size;
 268 }
 269
 270 static int intersect_rates(const int *source_rates, int source_len,
 271                            const int *sink_rates, int sink_len,
 272                            int *common_rates)
 273 {
 274         int i = 0, j = 0, k = 0;
 275
 276         while (i < source_len && j < sink_len) {
 277                 if (source_rates[i] == sink_rates[j]) {
 278                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 279                                 return k;
 280                         common_rates[k] = source_rates[i];
 281                         ++k;
 282                         ++i;
 283                         ++j;
 284                 } else if (source_rates[i] < sink_rates[j]) {
 285                         ++i;
 286                 } else {
 287                         ++j;
 288                 }
 289         }
 290         return k;
 291 }
 292
 293 /* return index of rate in rates array, or -1 if not found */
 294 static int intel_dp_rate_index(const int *rates, int len, int rate)
 295 {
 296         int i;
 297
 298         for (i = 0; i < len; i++)
 299                 if (rate == rates[i])
 300                         return i;
 301
 302         return -1;
 303 }
 304
 305 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 306 {
 307         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 308
 309         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 310                                                      intel_dp->num_source_rates,
 311                                                      intel_dp->sink_rates,
 312                                                      intel_dp->num_sink_rates,
 313                                                      intel_dp->common_rates);
 314
 315         /* Paranoia, there should always be something in common. */
 316         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 317                 intel_dp->common_rates[0] = default_rates[0];
 318                 intel_dp->num_common_rates = 1;
 319         }
 320 }
 321
 322 /* get length of common rates potentially limited by max_rate */
 323 static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
 324                                           int max_rate)
 325 {
 326         const int *common_rates = intel_dp->common_rates;
 327         int i, common_len = intel_dp->num_common_rates;
 328
 329         /* Limit results by potentially reduced max rate */
 330         for (i = 0; i < common_len; i++) {
 331                 if (common_rates[common_len - i - 1] <= max_rate)
 332                         return common_len - i;
 333         }
 334
 335         return 0;
 336 }
 337
 338 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 339                                        uint8_t lane_count)
 340 {
 341         /*
 342          * FIXME: we need to synchronize the current link parameters with
 343          * hardware readout. Currently fast link training doesn't work on
 344          * boot-up.
 345          */
 346         if (link_rate == 0 ||
 347             link_rate > intel_dp->max_link_rate)
 348                 return false;
 349
 350         if (lane_count == 0 ||
 351             lane_count > intel_dp_max_lane_count(intel_dp))
 352                 return false;
 353
 354         return true;
 355 }
 356
 357 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 358                                             int link_rate, uint8_t lane_count)
 359 {
 360         int index;
 361
 362         index = intel_dp_rate_index(intel_dp->common_rates,
 363                                     intel_dp->num_common_rates,
 364                                     link_rate);
 365         if (index > 0) {
 366                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 367                 intel_dp->max_link_lane_count = lane_count;
 368         } else if (lane_count > 1) {
 369                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 370                 intel_dp->max_link_lane_count = lane_count >> 1;
 371         } else {
 372                 DRM_ERROR("Link Training Unsuccessful\n");
 373                 return -1;
 374         }
 375
 376         return 0;
 377 }
 378
 379 static enum drm_mode_status
 380 intel_dp_mode_valid(struct drm_connector *connector,
 381                     struct drm_display_mode *mode)
 382 {
 383         struct intel_dp *intel_dp = intel_attached_dp(connector);
 384         struct intel_connector *intel_connector = to_intel_connector(connector);
 385         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 386         int target_clock = mode->clock;
 387         int max_rate, mode_rate, max_lanes, max_link_clock;
 388         int max_dotclk;
 389
 390         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 391
 392         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 393                 if (mode->hdisplay > fixed_mode->hdisplay)
 394                         return MODE_PANEL;
 395
 396                 if (mode->vdisplay > fixed_mode->vdisplay)
 397                         return MODE_PANEL;
 398
 399                 target_clock = fixed_mode->clock;
 400         }
 401
 402         max_link_clock = intel_dp_max_link_rate(intel_dp);
 403         max_lanes = intel_dp_max_lane_count(intel_dp);
 404
 405         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 406         mode_rate = intel_dp_link_required(target_clock, 18);
 407
 408         if (mode_rate > max_rate || target_clock > max_dotclk)
 409                 return MODE_CLOCK_HIGH;
 410
 411         if (mode->clock < 10000)
 412                 return MODE_CLOCK_LOW;
 413
 414         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 415                 return MODE_H_ILLEGAL;
 416
 417         return MODE_OK;
 418 }
 419
 420 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 421 {
 422         int     i;
 423         uint32_t v = 0;
 424
 425         if (src_bytes > 4)
 426                 src_bytes = 4;
 427         for (i = 0; i < src_bytes; i++)
 428                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 429         return v;
 430 }
 431
 432 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 433 {
 434         int i;
 435         if (dst_bytes > 4)
 436                 dst_bytes = 4;
 437         for (i = 0; i < dst_bytes; i++)
 438                 dst[i] = src >> ((3-i) * 8);
 439 }
 440
 441 static void
 442 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 443                                     struct intel_dp *intel_dp);
 444 static void
 445 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 446                                               struct intel_dp *intel_dp,
 447                                               bool force_disable_vdd);
 448 static void
 449 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
 450
 451 static void pps_lock(struct intel_dp *intel_dp)
 452 {
 453         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 454         struct intel_encoder *encoder = &intel_dig_port->base;
 455         struct drm_device *dev = encoder->base.dev;
 456         struct drm_i915_private *dev_priv = to_i915(dev);
 457
 458         /*
 459          * See vlv_power_sequencer_reset() why we need
 460          * a power domain reference here.
 461          */
 462         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 463
 464         mutex_lock(&dev_priv->pps_mutex);
 465 }
 466
 467 static void pps_unlock(struct intel_dp *intel_dp)
 468 {
 469         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 470         struct intel_encoder *encoder = &intel_dig_port->base;
 471         struct drm_device *dev = encoder->base.dev;
 472         struct drm_i915_private *dev_priv = to_i915(dev);
 473
 474         mutex_unlock(&dev_priv->pps_mutex);
 475
 476         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 477 }
 478
 479 static void
 480 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 481 {
 482         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 483         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 484         enum pipe pipe = intel_dp->pps_pipe;
 485         bool pll_enabled, release_cl_override = false;
 486         enum dpio_phy phy = DPIO_PHY(pipe);
 487         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 488         uint32_t DP;
 489
 490         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 491                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 492                  pipe_name(pipe), port_name(intel_dig_port->port)))
 493                 return;
 494
 495         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 496                       pipe_name(pipe), port_name(intel_dig_port->port));
 497
 498         /* Preserve the BIOS-computed detected bit. This is
 499          * supposed to be read-only.
 500          */
 501         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 502         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 503         DP |= DP_PORT_WIDTH(1);
 504         DP |= DP_LINK_TRAIN_PAT_1;
 505
 506         if (IS_CHERRYVIEW(dev_priv))
 507                 DP |= DP_PIPE_SELECT_CHV(pipe);
 508         else if (pipe == PIPE_B)
 509                 DP |= DP_PIPEB_SELECT;
 510
 511         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 512
 513         /*
 514          * The DPLL for the pipe must be enabled for this to work.
 515          * So enable temporarily it if it's not already enabled.
 516          */
 517         if (!pll_enabled) {
 518                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 519                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 520
 521                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 522                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 523                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 524                                   pipe_name(pipe));
 525                         return;
 526                 }
 527         }
 528
 529         /*
 530          * Similar magic as in intel_dp_enable_port().
 531          * We _must_ do this port enable + disable trick
 532          * to make this power seqeuencer lock onto the port.
 533          * Otherwise even VDD force bit won't work.
 534          */
 535         I915_WRITE(intel_dp->output_reg, DP);
 536         POSTING_READ(intel_dp->output_reg);
 537
 538         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 539         POSTING_READ(intel_dp->output_reg);
 540
 541         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 542         POSTING_READ(intel_dp->output_reg);
 543
 544         if (!pll_enabled) {
 545                 vlv_force_pll_off(dev_priv, pipe);
 546
 547                 if (release_cl_override)
 548                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 549         }
 550 }
 551
 552 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 553 {
 554         struct intel_encoder *encoder;
 555         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 556
 557         /*
 558          * We don't have power sequencer currently.
 559          * Pick one that's not used by other ports.
 560          */
 561         for_each_intel_encoder(&dev_priv->drm, encoder) {
 562                 struct intel_dp *intel_dp;
 563
 564                 if (encoder->type != INTEL_OUTPUT_DP &&
 565                     encoder->type != INTEL_OUTPUT_EDP)
 566                         continue;
 567
 568                 intel_dp = enc_to_intel_dp(&encoder->base);
 569
 570                 if (encoder->type == INTEL_OUTPUT_EDP) {
 571                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 572                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 573
 574                         if (intel_dp->pps_pipe != INVALID_PIPE)
 575                                 pipes &= ~(1 << intel_dp->pps_pipe);
 576                 } else {
 577                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 578
 579                         if (intel_dp->active_pipe != INVALID_PIPE)
 580                                 pipes &= ~(1 << intel_dp->active_pipe);
 581                 }
 582         }
 583
 584         if (pipes == 0)
 585                 return INVALID_PIPE;
 586
 587         return ffs(pipes) - 1;
 588 }
 589
 590 static enum pipe
 591 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 592 {
 593         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 594         struct drm_device *dev = intel_dig_port->base.base.dev;
 595         struct drm_i915_private *dev_priv = to_i915(dev);
 596         enum pipe pipe;
 597
 598         lockdep_assert_held(&dev_priv->pps_mutex);
 599
 600         /* We should never land here with regular DP ports */
 601         WARN_ON(!intel_dp_is_edp(intel_dp));
 602
 603         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 604                 intel_dp->active_pipe != intel_dp->pps_pipe);
 605
 606         if (intel_dp->pps_pipe != INVALID_PIPE)
 607                 return intel_dp->pps_pipe;
 608
 609         pipe = vlv_find_free_pps(dev_priv);
 610
 611         /*
 612          * Didn't find one. This should not happen since there
 613          * are two power sequencers and up to two eDP ports.
 614          */
 615         if (WARN_ON(pipe == INVALID_PIPE))
 616                 pipe = PIPE_A;
 617
 618         vlv_steal_power_sequencer(dev, pipe);
 619         intel_dp->pps_pipe = pipe;
 620
 621         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 622                       pipe_name(intel_dp->pps_pipe),
 623                       port_name(intel_dig_port->port));
 624
 625         /* init power sequencer on this pipe and port */
 626         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 627         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
 628
 629         /*
 630          * Even vdd force doesn't work until we've made
 631          * the power sequencer lock in on the port.
 632          */
 633         vlv_power_sequencer_kick(intel_dp);
 634
 635         return intel_dp->pps_pipe;
 636 }
 637
 638 static int
 639 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 640 {
 641         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 642         struct drm_device *dev = intel_dig_port->base.base.dev;
 643         struct drm_i915_private *dev_priv = to_i915(dev);
 644
 645         lockdep_assert_held(&dev_priv->pps_mutex);
 646
 647         /* We should never land here with regular DP ports */
 648         WARN_ON(!intel_dp_is_edp(intel_dp));
 649
 650         /*
 651          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 652          * mapping needs to be retrieved from VBT, for now just hard-code to
 653          * use instance #0 always.
 654          */
 655         if (!intel_dp->pps_reset)
 656                 return 0;
 657
 658         intel_dp->pps_reset = false;
 659
 660         /*
 661          * Only the HW needs to be reprogrammed, the SW state is fixed and
 662          * has been setup during connector init.
 663          */
 664         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 665
 666         return 0;
 667 }
 668
 669 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 670                                enum pipe pipe);
 671
 672 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 673                                enum pipe pipe)
 674 {
 675         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 676 }
 677
 678 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 679                                 enum pipe pipe)
 680 {
 681         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 682 }
 683
 684 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 685                          enum pipe pipe)
 686 {
 687         return true;
 688 }
 689
 690 static enum pipe
 691 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 692                      enum port port,
 693                      vlv_pipe_check pipe_check)
 694 {
 695         enum pipe pipe;
 696
 697         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 698                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 699                         PANEL_PORT_SELECT_MASK;
 700
 701                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 702                         continue;
 703
 704                 if (!pipe_check(dev_priv, pipe))
 705                         continue;
 706
 707                 return pipe;
 708         }
 709
 710         return INVALID_PIPE;
 711 }
 712
 713 static void
 714 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 715 {
 716         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 717         struct drm_device *dev = intel_dig_port->base.base.dev;
 718         struct drm_i915_private *dev_priv = to_i915(dev);
 719         enum port port = intel_dig_port->port;
 720
 721         lockdep_assert_held(&dev_priv->pps_mutex);
 722
 723         /* try to find a pipe with this port selected */
 724         /* first pick one where the panel is on */
 725         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 726                                                   vlv_pipe_has_pp_on);
 727         /* didn't find one? pick one where vdd is on */
 728         if (intel_dp->pps_pipe == INVALID_PIPE)
 729                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 730                                                           vlv_pipe_has_vdd_on);
 731         /* didn't find one? pick one with just the correct port */
 732         if (intel_dp->pps_pipe == INVALID_PIPE)
 733                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 734                                                           vlv_pipe_any);
 735
 736         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 737         if (intel_dp->pps_pipe == INVALID_PIPE) {
 738                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 739                               port_name(port));
 740                 return;
 741         }
 742
 743         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 744                       port_name(port), pipe_name(intel_dp->pps_pipe));
 745
 746         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 747         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 748 }
 749
 750 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 751 {
 752         struct drm_device *dev = &dev_priv->drm;
 753         struct intel_encoder *encoder;
 754
 755         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 756                     !IS_GEN9_LP(dev_priv)))
 757                 return;
 758
 759         /*
 760          * We can't grab pps_mutex here due to deadlock with power_domain
 761          * mutex when power_domain functions are called while holding pps_mutex.
 762          * That also means that in order to use pps_pipe the code needs to
 763          * hold both a power domain reference and pps_mutex, and the power domain
 764          * reference get/put must be done while _not_ holding pps_mutex.
 765          * pps_{lock,unlock}() do these steps in the correct order, so one
 766          * should use them always.
 767          */
 768
 769         for_each_intel_encoder(dev, encoder) {
 770                 struct intel_dp *intel_dp;
 771
 772                 if (encoder->type != INTEL_OUTPUT_DP &&
 773                     encoder->type != INTEL_OUTPUT_EDP)
 774                         continue;
 775
 776                 intel_dp = enc_to_intel_dp(&encoder->base);
 777
 778                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 779
 780                 if (encoder->type != INTEL_OUTPUT_EDP)
 781                         continue;
 782
 783                 if (IS_GEN9_LP(dev_priv))
 784                         intel_dp->pps_reset = true;
 785                 else
 786                         intel_dp->pps_pipe = INVALID_PIPE;
 787         }
 788 }
 789
 790 struct pps_registers {
 791         i915_reg_t pp_ctrl;
 792         i915_reg_t pp_stat;
 793         i915_reg_t pp_on;
 794         i915_reg_t pp_off;
 795         i915_reg_t pp_div;
 796 };
 797
 798 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 799                                     struct intel_dp *intel_dp,
 800                                     struct pps_registers *regs)
 801 {
 802         int pps_idx = 0;
 803
 804         memset(regs, 0, sizeof(*regs));
 805
 806         if (IS_GEN9_LP(dev_priv))
 807                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 808         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 809                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 810
 811         regs->pp_ctrl = PP_CONTROL(pps_idx);
 812         regs->pp_stat = PP_STATUS(pps_idx);
 813         regs->pp_on = PP_ON_DELAYS(pps_idx);
 814         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 815         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
 816                 regs->pp_div = PP_DIVISOR(pps_idx);
 817 }
 818
 819 static i915_reg_t
 820 _pp_ctrl_reg(struct intel_dp *intel_dp)
 821 {
 822         struct pps_registers regs;
 823
 824         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 825                                 &regs);
 826
 827         return regs.pp_ctrl;
 828 }
 829
 830 static i915_reg_t
 831 _pp_stat_reg(struct intel_dp *intel_dp)
 832 {
 833         struct pps_registers regs;
 834
 835         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 836                                 &regs);
 837
 838         return regs.pp_stat;
 839 }
 840
 841 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 842    This function only applicable when panel PM state is not to be tracked */
 843 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 844                               void *unused)
 845 {
 846         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 847                                                  edp_notifier);
 848         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 849         struct drm_i915_private *dev_priv = to_i915(dev);
 850
 851         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 852                 return 0;
 853
 854         pps_lock(intel_dp);
 855
 856         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 857                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 858                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 859                 u32 pp_div;
 860
 861                 pp_ctrl_reg = PP_CONTROL(pipe);
 862                 pp_div_reg  = PP_DIVISOR(pipe);
 863                 pp_div = I915_READ(pp_div_reg);
 864                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 865
 866                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 867                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 868                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 869                 msleep(intel_dp->panel_power_cycle_delay);
 870         }
 871
 872         pps_unlock(intel_dp);
 873
 874         return 0;
 875 }
 876
 877 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 878 {
 879         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 880         struct drm_i915_private *dev_priv = to_i915(dev);
 881
 882         lockdep_assert_held(&dev_priv->pps_mutex);
 883
 884         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 885             intel_dp->pps_pipe == INVALID_PIPE)
 886                 return false;
 887
 888         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 889 }
 890
 891 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 892 {
 893         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 894         struct drm_i915_private *dev_priv = to_i915(dev);
 895
 896         lockdep_assert_held(&dev_priv->pps_mutex);
 897
 898         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 899             intel_dp->pps_pipe == INVALID_PIPE)
 900                 return false;
 901
 902         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 903 }
 904
 905 static void
 906 intel_dp_check_edp(struct intel_dp *intel_dp)
 907 {
 908         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 909         struct drm_i915_private *dev_priv = to_i915(dev);
 910
 911         if (!intel_dp_is_edp(intel_dp))
 912                 return;
 913
 914         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 915                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 916                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 917                               I915_READ(_pp_stat_reg(intel_dp)),
 918                               I915_READ(_pp_ctrl_reg(intel_dp)));
 919         }
 920 }
 921
 922 static uint32_t
 923 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 924 {
 925         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 926         struct drm_device *dev = intel_dig_port->base.base.dev;
 927         struct drm_i915_private *dev_priv = to_i915(dev);
 928         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 929         uint32_t status;
 930         bool done;
 931
 932 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 933         if (has_aux_irq)
 934                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 935                                           msecs_to_jiffies_timeout(10));
 936         else
 937                 done = wait_for(C, 10) == 0;
 938         if (!done)
 939                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 940                           has_aux_irq);
 941 #undef C
 942
 943         return status;
 944 }
 945
 946 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 947 {
 948         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 949         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 950
 951         if (index)
 952                 return 0;
 953
 954         /*
 955          * The clock divider is based off the hrawclk, and would like to run at
 956          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 957          */
 958         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 959 }
 960
 961 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 962 {
 963         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 964         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 965
 966         if (index)
 967                 return 0;
 968
 969         /*
 970          * The clock divider is based off the cdclk or PCH rawclk, and would
 971          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 972          * divide by 2000 and use that
 973          */
 974         if (intel_dig_port->port == PORT_A)
 975                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 976         else
 977                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 978 }
 979
 980 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 981 {
 982         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 983         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 984
 985         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 986                 /* Workaround for non-ULT HSW */
 987                 switch (index) {
 988                 case 0: return 63;
 989                 case 1: return 72;
 990                 default: return 0;
 991                 }
 992         }
 993
 994         return ilk_get_aux_clock_divider(intel_dp, index);
 995 }
 996
 997 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 998 {
 999         /*
1000          * SKL doesn't need us to program the AUX clock divider (Hardware will
1001          * derive the clock from CDCLK automatically). We still implement the
1002          * get_aux_clock_divider vfunc to plug-in into the existing code.
1003          */
1004         return index ? 0 : 1;
1005 }
1006
1007 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1008                                      bool has_aux_irq,
1009                                      int send_bytes,
1010                                      uint32_t aux_clock_divider)
1011 {
1012         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1013         struct drm_i915_private *dev_priv =
1014                         to_i915(intel_dig_port->base.base.dev);
1015         uint32_t precharge, timeout;
1016
1017         if (IS_GEN6(dev_priv))
1018                 precharge = 3;
1019         else
1020                 precharge = 5;
1021
1022         if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
1023                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1024         else
1025                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1026
1027         return DP_AUX_CH_CTL_SEND_BUSY |
1028                DP_AUX_CH_CTL_DONE |
1029                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1030                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1031                timeout |
1032                DP_AUX_CH_CTL_RECEIVE_ERROR |
1033                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1034                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1035                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1036 }
1037
1038 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1039                                       bool has_aux_irq,
1040                                       int send_bytes,
1041                                       uint32_t unused)
1042 {
1043         return DP_AUX_CH_CTL_SEND_BUSY |
1044                DP_AUX_CH_CTL_DONE |
1045                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1046                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1047                DP_AUX_CH_CTL_TIME_OUT_1600us |
1048                DP_AUX_CH_CTL_RECEIVE_ERROR |
1049                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1050                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1051                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1052 }
1053
1054 static int
1055 intel_dp_aux_ch(struct intel_dp *intel_dp,
1056                 const uint8_t *send, int send_bytes,
1057                 uint8_t *recv, int recv_size)
1058 {
1059         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1060         struct drm_i915_private *dev_priv =
1061                         to_i915(intel_dig_port->base.base.dev);
1062         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1063         uint32_t aux_clock_divider;
1064         int i, ret, recv_bytes;
1065         uint32_t status;
1066         int try, clock = 0;
1067         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1068         bool vdd;
1069
1070         pps_lock(intel_dp);
1071
1072         /*
1073          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1074          * In such cases we want to leave VDD enabled and it's up to upper layers
1075          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1076          * ourselves.
1077          */
1078         vdd = edp_panel_vdd_on(intel_dp);
1079
1080         /* dp aux is extremely sensitive to irq latency, hence request the
1081          * lowest possible wakeup latency and so prevent the cpu from going into
1082          * deep sleep states.
1083          */
1084         pm_qos_update_request(&dev_priv->pm_qos, 0);
1085
1086         intel_dp_check_edp(intel_dp);
1087
1088         /* Try to wait for any previous AUX channel activity */
1089         for (try = 0; try < 3; try++) {
1090                 status = I915_READ_NOTRACE(ch_ctl);
1091                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1092                         break;
1093                 msleep(1);
1094         }
1095
1096         if (try == 3) {
1097                 static u32 last_status = -1;
1098                 const u32 status = I915_READ(ch_ctl);
1099
1100                 if (status != last_status) {
1101                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1102                              status);
1103                         last_status = status;
1104                 }
1105
1106                 ret = -EBUSY;
1107                 goto out;
1108         }
1109
1110         /* Only 5 data registers! */
1111         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1112                 ret = -E2BIG;
1113                 goto out;
1114         }
1115
1116         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1117                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1118                                                           has_aux_irq,
1119                                                           send_bytes,
1120                                                           aux_clock_divider);
1121
1122                 /* Must try at least 3 times according to DP spec */
1123                 for (try = 0; try < 5; try++) {
1124                         /* Load the send data into the aux channel data registers */
1125                         for (i = 0; i < send_bytes; i += 4)
1126                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1127                                            intel_dp_pack_aux(send + i,
1128                                                              send_bytes - i));
1129
1130                         /* Send the command and wait for it to complete */
1131                         I915_WRITE(ch_ctl, send_ctl);
1132
1133                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1134
1135                         /* Clear done status and any errors */
1136                         I915_WRITE(ch_ctl,
1137                                    status |
1138                                    DP_AUX_CH_CTL_DONE |
1139                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1140                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1141
1142                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1143                                 continue;
1144
1145                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1146                          *   400us delay required for errors and timeouts
1147                          *   Timeout errors from the HW already meet this
1148                          *   requirement so skip to next iteration
1149                          */
1150                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1151                                 usleep_range(400, 500);
1152                                 continue;
1153                         }
1154                         if (status & DP_AUX_CH_CTL_DONE)
1155                                 goto done;
1156                 }
1157         }
1158
1159         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1160                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1161                 ret = -EBUSY;
1162                 goto out;
1163         }
1164
1165 done:
1166         /* Check for timeout or receive error.
1167          * Timeouts occur when the sink is not connected
1168          */
1169         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1170                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1171                 ret = -EIO;
1172                 goto out;
1173         }
1174
1175         /* Timeouts occur when the device isn't connected, so they're
1176          * "normal" -- don't fill the kernel log with these */
1177         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1178                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1179                 ret = -ETIMEDOUT;
1180                 goto out;
1181         }
1182
1183         /* Unload any bytes sent back from the other side */
1184         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1185                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1186
1187         /*
1188          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1189          * We have no idea of what happened so we return -EBUSY so
1190          * drm layer takes care for the necessary retries.
1191          */
1192         if (recv_bytes == 0 || recv_bytes > 20) {
1193                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1194                               recv_bytes);
1195                 /*
1196                  * FIXME: This patch was created on top of a series that
1197                  * organize the retries at drm level. There EBUSY should
1198                  * also take care for 1ms wait before retrying.
1199                  * That aux retries re-org is still needed and after that is
1200                  * merged we remove this sleep from here.
1201                  */
1202                 usleep_range(1000, 1500);
1203                 ret = -EBUSY;
1204                 goto out;
1205         }
1206
1207         if (recv_bytes > recv_size)
1208                 recv_bytes = recv_size;
1209
1210         for (i = 0; i < recv_bytes; i += 4)
1211                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1212                                     recv + i, recv_bytes - i);
1213
1214         ret = recv_bytes;
1215 out:
1216         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1217
1218         if (vdd)
1219                 edp_panel_vdd_off(intel_dp, false);
1220
1221         pps_unlock(intel_dp);
1222
1223         return ret;
1224 }
1225
1226 #define BARE_ADDRESS_SIZE       3
1227 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1228 static ssize_t
1229 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1230 {
1231         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1232         uint8_t txbuf[20], rxbuf[20];
1233         size_t txsize, rxsize;
1234         int ret;
1235
1236         txbuf[0] = (msg->request << 4) |
1237                 ((msg->address >> 16) & 0xf);
1238         txbuf[1] = (msg->address >> 8) & 0xff;
1239         txbuf[2] = msg->address & 0xff;
1240         txbuf[3] = msg->size - 1;
1241
1242         switch (msg->request & ~DP_AUX_I2C_MOT) {
1243         case DP_AUX_NATIVE_WRITE:
1244         case DP_AUX_I2C_WRITE:
1245         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1246                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1247                 rxsize = 2; /* 0 or 1 data bytes */
1248
1249                 if (WARN_ON(txsize > 20))
1250                         return -E2BIG;
1251
1252                 WARN_ON(!msg->buffer != !msg->size);
1253
1254                 if (msg->buffer)
1255                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1256
1257                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1258                 if (ret > 0) {
1259                         msg->reply = rxbuf[0] >> 4;
1260
1261                         if (ret > 1) {
1262                                 /* Number of bytes written in a short write. */
1263                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1264                         } else {
1265                                 /* Return payload size. */
1266                                 ret = msg->size;
1267                         }
1268                 }
1269                 break;
1270
1271         case DP_AUX_NATIVE_READ:
1272         case DP_AUX_I2C_READ:
1273                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1274                 rxsize = msg->size + 1;
1275
1276                 if (WARN_ON(rxsize > 20))
1277                         return -E2BIG;
1278
1279                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1280                 if (ret > 0) {
1281                         msg->reply = rxbuf[0] >> 4;
1282                         /*
1283                          * Assume happy day, and copy the data. The caller is
1284                          * expected to check msg->reply before touching it.
1285                          *
1286                          * Return payload size.
1287                          */
1288                         ret--;
1289                         memcpy(msg->buffer, rxbuf + 1, ret);
1290                 }
1291                 break;
1292
1293         default:
1294                 ret = -EINVAL;
1295                 break;
1296         }
1297
1298         return ret;
1299 }
1300
1301 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1302                                 enum port port)
1303 {
1304         const struct ddi_vbt_port_info *info =
1305                 &dev_priv->vbt.ddi_port_info[port];
1306         enum port aux_port;
1307
1308         if (!info->alternate_aux_channel) {
1309                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1310                               port_name(port), port_name(port));
1311                 return port;
1312         }
1313
1314         switch (info->alternate_aux_channel) {
1315         case DP_AUX_A:
1316                 aux_port = PORT_A;
1317                 break;
1318         case DP_AUX_B:
1319                 aux_port = PORT_B;
1320                 break;
1321         case DP_AUX_C:
1322                 aux_port = PORT_C;
1323                 break;
1324         case DP_AUX_D:
1325                 aux_port = PORT_D;
1326                 break;
1327         default:
1328                 MISSING_CASE(info->alternate_aux_channel);
1329                 aux_port = PORT_A;
1330                 break;
1331         }
1332
1333         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1334                       port_name(aux_port), port_name(port));
1335
1336         return aux_port;
1337 }
1338
1339 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1340                                   enum port port)
1341 {
1342         switch (port) {
1343         case PORT_B:
1344         case PORT_C:
1345         case PORT_D:
1346                 return DP_AUX_CH_CTL(port);
1347         default:
1348                 MISSING_CASE(port);
1349                 return DP_AUX_CH_CTL(PORT_B);
1350         }
1351 }
1352
1353 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1354                                    enum port port, int index)
1355 {
1356         switch (port) {
1357         case PORT_B:
1358         case PORT_C:
1359         case PORT_D:
1360                 return DP_AUX_CH_DATA(port, index);
1361         default:
1362                 MISSING_CASE(port);
1363                 return DP_AUX_CH_DATA(PORT_B, index);
1364         }
1365 }
1366
1367 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1368                                   enum port port)
1369 {
1370         switch (port) {
1371         case PORT_A:
1372                 return DP_AUX_CH_CTL(port);
1373         case PORT_B:
1374         case PORT_C:
1375         case PORT_D:
1376                 return PCH_DP_AUX_CH_CTL(port);
1377         default:
1378                 MISSING_CASE(port);
1379                 return DP_AUX_CH_CTL(PORT_A);
1380         }
1381 }
1382
1383 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1384                                    enum port port, int index)
1385 {
1386         switch (port) {
1387         case PORT_A:
1388                 return DP_AUX_CH_DATA(port, index);
1389         case PORT_B:
1390         case PORT_C:
1391         case PORT_D:
1392                 return PCH_DP_AUX_CH_DATA(port, index);
1393         default:
1394                 MISSING_CASE(port);
1395                 return DP_AUX_CH_DATA(PORT_A, index);
1396         }
1397 }
1398
1399 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1400                                   enum port port)
1401 {
1402         switch (port) {
1403         case PORT_A:
1404         case PORT_B:
1405         case PORT_C:
1406         case PORT_D:
1407                 return DP_AUX_CH_CTL(port);
1408         default:
1409                 MISSING_CASE(port);
1410                 return DP_AUX_CH_CTL(PORT_A);
1411         }
1412 }
1413
1414 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1415                                    enum port port, int index)
1416 {
1417         switch (port) {
1418         case PORT_A:
1419         case PORT_B:
1420         case PORT_C:
1421         case PORT_D:
1422                 return DP_AUX_CH_DATA(port, index);
1423         default:
1424                 MISSING_CASE(port);
1425                 return DP_AUX_CH_DATA(PORT_A, index);
1426         }
1427 }
1428
1429 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1430                                     enum port port)
1431 {
1432         if (INTEL_INFO(dev_priv)->gen >= 9)
1433                 return skl_aux_ctl_reg(dev_priv, port);
1434         else if (HAS_PCH_SPLIT(dev_priv))
1435                 return ilk_aux_ctl_reg(dev_priv, port);
1436         else
1437                 return g4x_aux_ctl_reg(dev_priv, port);
1438 }
1439
1440 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1441                                      enum port port, int index)
1442 {
1443         if (INTEL_INFO(dev_priv)->gen >= 9)
1444                 return skl_aux_data_reg(dev_priv, port, index);
1445         else if (HAS_PCH_SPLIT(dev_priv))
1446                 return ilk_aux_data_reg(dev_priv, port, index);
1447         else
1448                 return g4x_aux_data_reg(dev_priv, port, index);
1449 }
1450
1451 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1452 {
1453         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1454         enum port port = intel_aux_port(dev_priv,
1455                                         dp_to_dig_port(intel_dp)->port);
1456         int i;
1457
1458         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1459         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1460                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1461 }
1462
1463 static void
1464 intel_dp_aux_fini(struct intel_dp *intel_dp)
1465 {
1466         kfree(intel_dp->aux.name);
1467 }
1468
1469 static void
1470 intel_dp_aux_init(struct intel_dp *intel_dp)
1471 {
1472         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1473         enum port port = intel_dig_port->port;
1474
1475         intel_aux_reg_init(intel_dp);
1476         drm_dp_aux_init(&intel_dp->aux);
1477
1478         /* Failure to allocate our preferred name is not critical */
1479         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1480         intel_dp->aux.transfer = intel_dp_aux_transfer;
1481 }
1482
1483 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1484 {
1485         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1486         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1487
1488         if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1489             IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1490                 return true;
1491         else
1492                 return false;
1493 }
1494
1495 static void
1496 intel_dp_set_clock(struct intel_encoder *encoder,
1497                    struct intel_crtc_state *pipe_config)
1498 {
1499         struct drm_device *dev = encoder->base.dev;
1500         struct drm_i915_private *dev_priv = to_i915(dev);
1501         const struct dp_link_dpll *divisor = NULL;
1502         int i, count = 0;
1503
1504         if (IS_G4X(dev_priv)) {
1505                 divisor = gen4_dpll;
1506                 count = ARRAY_SIZE(gen4_dpll);
1507         } else if (HAS_PCH_SPLIT(dev_priv)) {
1508                 divisor = pch_dpll;
1509                 count = ARRAY_SIZE(pch_dpll);
1510         } else if (IS_CHERRYVIEW(dev_priv)) {
1511                 divisor = chv_dpll;
1512                 count = ARRAY_SIZE(chv_dpll);
1513         } else if (IS_VALLEYVIEW(dev_priv)) {
1514                 divisor = vlv_dpll;
1515                 count = ARRAY_SIZE(vlv_dpll);
1516         }
1517
1518         if (divisor && count) {
1519                 for (i = 0; i < count; i++) {
1520                         if (pipe_config->port_clock == divisor[i].clock) {
1521                                 pipe_config->dpll = divisor[i].dpll;
1522                                 pipe_config->clock_set = true;
1523                                 break;
1524                         }
1525                 }
1526         }
1527 }
1528
1529 static void snprintf_int_array(char *str, size_t len,
1530                                const int *array, int nelem)
1531 {
1532         int i;
1533
1534         str[0] = '\0';
1535
1536         for (i = 0; i < nelem; i++) {
1537                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1538                 if (r >= len)
1539                         return;
1540                 str += r;
1541                 len -= r;
1542         }
1543 }
1544
1545 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1546 {
1547         char str[128]; /* FIXME: too big for stack? */
1548
1549         if ((drm_debug & DRM_UT_KMS) == 0)
1550                 return;
1551
1552         snprintf_int_array(str, sizeof(str),
1553                            intel_dp->source_rates, intel_dp->num_source_rates);
1554         DRM_DEBUG_KMS("source rates: %s\n", str);
1555
1556         snprintf_int_array(str, sizeof(str),
1557                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1558         DRM_DEBUG_KMS("sink rates: %s\n", str);
1559
1560         snprintf_int_array(str, sizeof(str),
1561                            intel_dp->common_rates, intel_dp->num_common_rates);
1562         DRM_DEBUG_KMS("common rates: %s\n", str);
1563 }
1564
1565 int
1566 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1567 {
1568         int len;
1569
1570         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1571         if (WARN_ON(len <= 0))
1572                 return 162000;
1573
1574         return intel_dp->common_rates[len - 1];
1575 }
1576
1577 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1578 {
1579         int i = intel_dp_rate_index(intel_dp->sink_rates,
1580                                     intel_dp->num_sink_rates, rate);
1581
1582         if (WARN_ON(i < 0))
1583                 i = 0;
1584
1585         return i;
1586 }
1587
1588 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1589                            uint8_t *link_bw, uint8_t *rate_select)
1590 {
1591         /* eDP 1.4 rate select method. */
1592         if (intel_dp->use_rate_select) {
1593                 *link_bw = 0;
1594                 *rate_select =
1595                         intel_dp_rate_select(intel_dp, port_clock);
1596         } else {
1597                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1598                 *rate_select = 0;
1599         }
1600 }
1601
1602 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1603                                 struct intel_crtc_state *pipe_config)
1604 {
1605         int bpp, bpc;
1606
1607         bpp = pipe_config->pipe_bpp;
1608         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1609
1610         if (bpc > 0)
1611                 bpp = min(bpp, 3*bpc);
1612
1613         /* For DP Compliance we override the computed bpp for the pipe */
1614         if (intel_dp->compliance.test_data.bpc != 0) {
1615                 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1616                 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1617                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1618                               pipe_config->pipe_bpp);
1619         }
1620         return bpp;
1621 }
1622
1623 static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
1624                                        struct drm_display_mode *m2)
1625 {
1626         bool bres = false;
1627
1628         if (m1 && m2)
1629                 bres = (m1->hdisplay == m2->hdisplay &&
1630                         m1->hsync_start == m2->hsync_start &&
1631                         m1->hsync_end == m2->hsync_end &&
1632                         m1->htotal == m2->htotal &&
1633                         m1->vdisplay == m2->vdisplay &&
1634                         m1->vsync_start == m2->vsync_start &&
1635                         m1->vsync_end == m2->vsync_end &&
1636                         m1->vtotal == m2->vtotal);
1637         return bres;
1638 }
1639
1640 bool
1641 intel_dp_compute_config(struct intel_encoder *encoder,
1642                         struct intel_crtc_state *pipe_config,
1643                         struct drm_connector_state *conn_state)
1644 {
1645         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1646         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1647         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1648         enum port port = dp_to_dig_port(intel_dp)->port;
1649         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1650         struct intel_connector *intel_connector = intel_dp->attached_connector;
1651         struct intel_digital_connector_state *intel_conn_state =
1652                 to_intel_digital_connector_state(conn_state);
1653         int lane_count, clock;
1654         int min_lane_count = 1;
1655         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1656         /* Conveniently, the link BW constants become indices with a shift...*/
1657         int min_clock = 0;
1658         int max_clock;
1659         int bpp, mode_rate;
1660         int link_avail, link_clock;
1661         int common_len;
1662         uint8_t link_bw, rate_select;
1663         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1664                                            DP_DPCD_QUIRK_LIMITED_M_N);
1665
1666         common_len = intel_dp_common_len_rate_limit(intel_dp,
1667                                                     intel_dp->max_link_rate);
1668
1669         /* No common link rates between source and sink */
1670         WARN_ON(common_len <= 0);
1671
1672         max_clock = common_len - 1;
1673
1674         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1675                 pipe_config->has_pch_encoder = true;
1676
1677         pipe_config->has_drrs = false;
1678         if (port == PORT_A)
1679                 pipe_config->has_audio = false;
1680         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1681                 pipe_config->has_audio = intel_dp->has_audio;
1682         else
1683                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1684
1685         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1686                 struct drm_display_mode *panel_mode =
1687                         intel_connector->panel.alt_fixed_mode;
1688                 struct drm_display_mode *req_mode = &pipe_config->base.mode;
1689
1690                 if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
1691                         panel_mode = intel_connector->panel.fixed_mode;
1692
1693                 drm_mode_debug_printmodeline(panel_mode);
1694
1695                 intel_fixed_panel_mode(panel_mode, adjusted_mode);
1696
1697                 if (INTEL_GEN(dev_priv) >= 9) {
1698                         int ret;
1699                         ret = skl_update_scaler_crtc(pipe_config);
1700                         if (ret)
1701                                 return ret;
1702                 }
1703
1704                 if (HAS_GMCH_DISPLAY(dev_priv))
1705                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1706                                                  conn_state->scaling_mode);
1707                 else
1708                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1709                                                 conn_state->scaling_mode);
1710         }
1711
1712         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1713                 return false;
1714
1715         /* Use values requested by Compliance Test Request */
1716         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1717                 int index;
1718
1719                 /* Validate the compliance test data since max values
1720                  * might have changed due to link train fallback.
1721                  */
1722                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1723                                                intel_dp->compliance.test_lane_count)) {
1724                         index = intel_dp_rate_index(intel_dp->common_rates,
1725                                                     intel_dp->num_common_rates,
1726                                                     intel_dp->compliance.test_link_rate);
1727                         if (index >= 0)
1728                                 min_clock = max_clock = index;
1729                         min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1730                 }
1731         }
1732         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1733                       "max bw %d pixel clock %iKHz\n",
1734                       max_lane_count, intel_dp->common_rates[max_clock],
1735                       adjusted_mode->crtc_clock);
1736
1737         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1738          * bpc in between. */
1739         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1740         if (intel_dp_is_edp(intel_dp)) {
1741
1742                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1743                 if (intel_connector->base.display_info.bpc == 0 &&
1744                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1745                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1746                                       dev_priv->vbt.edp.bpp);
1747                         bpp = dev_priv->vbt.edp.bpp;
1748                 }
1749
1750                 /*
1751                  * Use the maximum clock and number of lanes the eDP panel
1752                  * advertizes being capable of. The panels are generally
1753                  * designed to support only a single clock and lane
1754                  * configuration, and typically these values correspond to the
1755                  * native resolution of the panel.
1756                  */
1757                 min_lane_count = max_lane_count;
1758                 min_clock = max_clock;
1759         }
1760
1761         for (; bpp >= 6*3; bpp -= 2*3) {
1762                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1763                                                    bpp);
1764
1765                 for (clock = min_clock; clock <= max_clock; clock++) {
1766                         for (lane_count = min_lane_count;
1767                                 lane_count <= max_lane_count;
1768                                 lane_count <<= 1) {
1769
1770                                 link_clock = intel_dp->common_rates[clock];
1771                                 link_avail = intel_dp_max_data_rate(link_clock,
1772                                                                     lane_count);
1773
1774                                 if (mode_rate <= link_avail) {
1775                                         goto found;
1776                                 }
1777                         }
1778                 }
1779         }
1780
1781         return false;
1782
1783 found:
1784         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1785                 /*
1786                  * See:
1787                  * CEA-861-E - 5.1 Default Encoding Parameters
1788                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1789                  */
1790                 pipe_config->limited_color_range =
1791                         bpp != 18 &&
1792                         drm_default_rgb_quant_range(adjusted_mode) ==
1793                         HDMI_QUANTIZATION_RANGE_LIMITED;
1794         } else {
1795                 pipe_config->limited_color_range =
1796                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1797         }
1798
1799         pipe_config->lane_count = lane_count;
1800
1801         pipe_config->pipe_bpp = bpp;
1802         pipe_config->port_clock = intel_dp->common_rates[clock];
1803
1804         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1805                               &link_bw, &rate_select);
1806
1807         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1808                       link_bw, rate_select, pipe_config->lane_count,
1809                       pipe_config->port_clock, bpp);
1810         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1811                       mode_rate, link_avail);
1812
1813         intel_link_compute_m_n(bpp, lane_count,
1814                                adjusted_mode->crtc_clock,
1815                                pipe_config->port_clock,
1816                                &pipe_config->dp_m_n,
1817                                reduce_m_n);
1818
1819         if (intel_connector->panel.downclock_mode != NULL &&
1820                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1821                         pipe_config->has_drrs = true;
1822                         intel_link_compute_m_n(bpp, lane_count,
1823                                 intel_connector->panel.downclock_mode->clock,
1824                                 pipe_config->port_clock,
1825                                 &pipe_config->dp_m2_n2,
1826                                 reduce_m_n);
1827         }
1828
1829         /*
1830          * DPLL0 VCO may need to be adjusted to get the correct
1831          * clock for eDP. This will affect cdclk as well.
1832          */
1833         if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1834                 int vco;
1835
1836                 switch (pipe_config->port_clock / 2) {
1837                 case 108000:
1838                 case 216000:
1839                         vco = 8640000;
1840                         break;
1841                 default:
1842                         vco = 8100000;
1843                         break;
1844                 }
1845
1846                 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1847         }
1848
1849         if (!HAS_DDI(dev_priv))
1850                 intel_dp_set_clock(encoder, pipe_config);
1851
1852         return true;
1853 }
1854
1855 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1856                               int link_rate, uint8_t lane_count,
1857                               bool link_mst)
1858 {
1859         intel_dp->link_rate = link_rate;
1860         intel_dp->lane_count = lane_count;
1861         intel_dp->link_mst = link_mst;
1862 }
1863
1864 static void intel_dp_prepare(struct intel_encoder *encoder,
1865                              const struct intel_crtc_state *pipe_config)
1866 {
1867         struct drm_device *dev = encoder->base.dev;
1868         struct drm_i915_private *dev_priv = to_i915(dev);
1869         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1870         enum port port = dp_to_dig_port(intel_dp)->port;
1871         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1872         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1873
1874         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1875                                  pipe_config->lane_count,
1876                                  intel_crtc_has_type(pipe_config,
1877                                                      INTEL_OUTPUT_DP_MST));
1878
1879         /*
1880          * There are four kinds of DP registers:
1881          *
1882          *      IBX PCH
1883          *      SNB CPU
1884          *      IVB CPU
1885          *      CPT PCH
1886          *
1887          * IBX PCH and CPU are the same for almost everything,
1888          * except that the CPU DP PLL is configured in this
1889          * register
1890          *
1891          * CPT PCH is quite different, having many bits moved
1892          * to the TRANS_DP_CTL register instead. That
1893          * configuration happens (oddly) in ironlake_pch_enable
1894          */
1895
1896         /* Preserve the BIOS-computed detected bit. This is
1897          * supposed to be read-only.
1898          */
1899         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1900
1901         /* Handle DP bits in common between all three register formats */
1902         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1903         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1904
1905         /* Split out the IBX/CPU vs CPT settings */
1906
1907         if (IS_GEN7(dev_priv) && port == PORT_A) {
1908                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1909                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1910                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1911                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1912                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1913
1914                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1915                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1916
1917                 intel_dp->DP |= crtc->pipe << 29;
1918         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1919                 u32 trans_dp;
1920
1921                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1922
1923                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1924                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1925                         trans_dp |= TRANS_DP_ENH_FRAMING;
1926                 else
1927                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1928                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1929         } else {
1930                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1931                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1932
1933                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1934                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1935                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1936                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1937                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1938
1939                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1940                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1941
1942                 if (IS_CHERRYVIEW(dev_priv))
1943                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1944                 else if (crtc->pipe == PIPE_B)
1945                         intel_dp->DP |= DP_PIPEB_SELECT;
1946         }
1947 }
1948
1949 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1950 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1951
1952 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1953 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1954
1955 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1956 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1957
1958 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1959                                    struct intel_dp *intel_dp);
1960
1961 static void wait_panel_status(struct intel_dp *intel_dp,
1962                                        u32 mask,
1963                                        u32 value)
1964 {
1965         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1966         struct drm_i915_private *dev_priv = to_i915(dev);
1967         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1968
1969         lockdep_assert_held(&dev_priv->pps_mutex);
1970
1971         intel_pps_verify_state(dev_priv, intel_dp);
1972
1973         pp_stat_reg = _pp_stat_reg(intel_dp);
1974         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1975
1976         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1977                         mask, value,
1978                         I915_READ(pp_stat_reg),
1979                         I915_READ(pp_ctrl_reg));
1980
1981         if (intel_wait_for_register(dev_priv,
1982                                     pp_stat_reg, mask, value,
1983                                     5000))
1984                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1985                                 I915_READ(pp_stat_reg),
1986                                 I915_READ(pp_ctrl_reg));
1987
1988         DRM_DEBUG_KMS("Wait complete\n");
1989 }
1990
1991 static void wait_panel_on(struct intel_dp *intel_dp)
1992 {
1993         DRM_DEBUG_KMS("Wait for panel power on\n");
1994         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1995 }
1996
1997 static void wait_panel_off(struct intel_dp *intel_dp)
1998 {
1999         DRM_DEBUG_KMS("Wait for panel power off time\n");
2000         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2001 }
2002
2003 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2004 {
2005         ktime_t panel_power_on_time;
2006         s64 panel_power_off_duration;
2007
2008         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2009
2010         /* take the difference of currrent time and panel power off time
2011          * and then make panel wait for t11_t12 if needed. */
2012         panel_power_on_time = ktime_get_boottime();
2013         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2014
2015         /* When we disable the VDD override bit last we have to do the manual
2016          * wait. */
2017         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2018                 wait_remaining_ms_from_jiffies(jiffies,
2019                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2020
2021         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2022 }
2023
2024 static void wait_backlight_on(struct intel_dp *intel_dp)
2025 {
2026         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2027                                        intel_dp->backlight_on_delay);
2028 }
2029
2030 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2031 {
2032         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2033                                        intel_dp->backlight_off_delay);
2034 }
2035
2036 /* Read the current pp_control value, unlocking the register if it
2037  * is locked
2038  */
2039
2040 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2041 {
2042         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2043         struct drm_i915_private *dev_priv = to_i915(dev);
2044         u32 control;
2045
2046         lockdep_assert_held(&dev_priv->pps_mutex);
2047
2048         control = I915_READ(_pp_ctrl_reg(intel_dp));
2049         if (WARN_ON(!HAS_DDI(dev_priv) &&
2050                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2051                 control &= ~PANEL_UNLOCK_MASK;
2052                 control |= PANEL_UNLOCK_REGS;
2053         }
2054         return control;
2055 }
2056
2057 /*
2058  * Must be paired with edp_panel_vdd_off().
2059  * Must hold pps_mutex around the whole on/off sequence.
2060  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2061  */
2062 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2063 {
2064         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2065         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2066         struct drm_i915_private *dev_priv = to_i915(dev);
2067         u32 pp;
2068         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2069         bool need_to_disable = !intel_dp->want_panel_vdd;
2070
2071         lockdep_assert_held(&dev_priv->pps_mutex);
2072
2073         if (!intel_dp_is_edp(intel_dp))
2074                 return false;
2075
2076         cancel_delayed_work(&intel_dp->panel_vdd_work);
2077         intel_dp->want_panel_vdd = true;
2078
2079         if (edp_have_panel_vdd(intel_dp))
2080                 return need_to_disable;
2081
2082         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2083
2084         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2085                       port_name(intel_dig_port->port));
2086
2087         if (!edp_have_panel_power(intel_dp))
2088                 wait_panel_power_cycle(intel_dp);
2089
2090         pp = ironlake_get_pp_control(intel_dp);
2091         pp |= EDP_FORCE_VDD;
2092
2093         pp_stat_reg = _pp_stat_reg(intel_dp);
2094         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2095
2096         I915_WRITE(pp_ctrl_reg, pp);
2097         POSTING_READ(pp_ctrl_reg);
2098         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2099                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2100         /*
2101          * If the panel wasn't on, delay before accessing aux channel
2102          */
2103         if (!edp_have_panel_power(intel_dp)) {
2104                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2105                               port_name(intel_dig_port->port));
2106                 msleep(intel_dp->panel_power_up_delay);
2107         }
2108
2109         return need_to_disable;
2110 }
2111
2112 /*
2113  * Must be paired with intel_edp_panel_vdd_off() or
2114  * intel_edp_panel_off().
2115  * Nested calls to these functions are not allowed since
2116  * we drop the lock. Caller must use some higher level
2117  * locking to prevent nested calls from other threads.
2118  */
2119 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2120 {
2121         bool vdd;
2122
2123         if (!intel_dp_is_edp(intel_dp))
2124                 return;
2125
2126         pps_lock(intel_dp);
2127         vdd = edp_panel_vdd_on(intel_dp);
2128         pps_unlock(intel_dp);
2129
2130         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2131              port_name(dp_to_dig_port(intel_dp)->port));
2132 }
2133
2134 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2135 {
2136         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2137         struct drm_i915_private *dev_priv = to_i915(dev);
2138         struct intel_digital_port *intel_dig_port =
2139                 dp_to_dig_port(intel_dp);
2140         u32 pp;
2141         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2142
2143         lockdep_assert_held(&dev_priv->pps_mutex);
2144
2145         WARN_ON(intel_dp->want_panel_vdd);
2146
2147         if (!edp_have_panel_vdd(intel_dp))
2148                 return;
2149
2150         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2151                       port_name(intel_dig_port->port));
2152
2153         pp = ironlake_get_pp_control(intel_dp);
2154         pp &= ~EDP_FORCE_VDD;
2155
2156         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2157         pp_stat_reg = _pp_stat_reg(intel_dp);
2158
2159         I915_WRITE(pp_ctrl_reg, pp);
2160         POSTING_READ(pp_ctrl_reg);
2161
2162         /* Make sure sequencer is idle before allowing subsequent activity */
2163         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2164         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2165
2166         if ((pp & PANEL_POWER_ON) == 0)
2167                 intel_dp->panel_power_off_time = ktime_get_boottime();
2168
2169         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2170 }
2171
2172 static void edp_panel_vdd_work(struct work_struct *__work)
2173 {
2174         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2175                                                  struct intel_dp, panel_vdd_work);
2176
2177         pps_lock(intel_dp);
2178         if (!intel_dp->want_panel_vdd)
2179                 edp_panel_vdd_off_sync(intel_dp);
2180         pps_unlock(intel_dp);
2181 }
2182
2183 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2184 {
2185         unsigned long delay;
2186
2187         /*
2188          * Queue the timer to fire a long time from now (relative to the power
2189          * down delay) to keep the panel power up across a sequence of
2190          * operations.
2191          */
2192         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2193         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2194 }
2195
2196 /*
2197  * Must be paired with edp_panel_vdd_on().
2198  * Must hold pps_mutex around the whole on/off sequence.
2199  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2200  */
2201 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2202 {
2203         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2204
2205         lockdep_assert_held(&dev_priv->pps_mutex);
2206
2207         if (!intel_dp_is_edp(intel_dp))
2208                 return;
2209
2210         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2211              port_name(dp_to_dig_port(intel_dp)->port));
2212
2213         intel_dp->want_panel_vdd = false;
2214
2215         if (sync)
2216                 edp_panel_vdd_off_sync(intel_dp);
2217         else
2218                 edp_panel_vdd_schedule_off(intel_dp);
2219 }
2220
2221 static void edp_panel_on(struct intel_dp *intel_dp)
2222 {
2223         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2224         struct drm_i915_private *dev_priv = to_i915(dev);
2225         u32 pp;
2226         i915_reg_t pp_ctrl_reg;
2227
2228         lockdep_assert_held(&dev_priv->pps_mutex);
2229
2230         if (!intel_dp_is_edp(intel_dp))
2231                 return;
2232
2233         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2234                       port_name(dp_to_dig_port(intel_dp)->port));
2235
2236         if (WARN(edp_have_panel_power(intel_dp),
2237                  "eDP port %c panel power already on\n",
2238                  port_name(dp_to_dig_port(intel_dp)->port)))
2239                 return;
2240
2241         wait_panel_power_cycle(intel_dp);
2242
2243         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2244         pp = ironlake_get_pp_control(intel_dp);
2245         if (IS_GEN5(dev_priv)) {
2246                 /* ILK workaround: disable reset around power sequence */
2247                 pp &= ~PANEL_POWER_RESET;
2248                 I915_WRITE(pp_ctrl_reg, pp);
2249                 POSTING_READ(pp_ctrl_reg);
2250         }
2251
2252         pp |= PANEL_POWER_ON;
2253         if (!IS_GEN5(dev_priv))
2254                 pp |= PANEL_POWER_RESET;
2255
2256         I915_WRITE(pp_ctrl_reg, pp);
2257         POSTING_READ(pp_ctrl_reg);
2258
2259         wait_panel_on(intel_dp);
2260         intel_dp->last_power_on = jiffies;
2261
2262         if (IS_GEN5(dev_priv)) {
2263                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2264                 I915_WRITE(pp_ctrl_reg, pp);
2265                 POSTING_READ(pp_ctrl_reg);
2266         }
2267 }
2268
2269 void intel_edp_panel_on(struct intel_dp *intel_dp)
2270 {
2271         if (!intel_dp_is_edp(intel_dp))
2272                 return;
2273
2274         pps_lock(intel_dp);
2275         edp_panel_on(intel_dp);
2276         pps_unlock(intel_dp);
2277 }
2278
2279
2280 static void edp_panel_off(struct intel_dp *intel_dp)
2281 {
2282         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2283         struct drm_i915_private *dev_priv = to_i915(dev);
2284         u32 pp;
2285         i915_reg_t pp_ctrl_reg;
2286
2287         lockdep_assert_held(&dev_priv->pps_mutex);
2288
2289         if (!intel_dp_is_edp(intel_dp))
2290                 return;
2291
2292         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2293                       port_name(dp_to_dig_port(intel_dp)->port));
2294
2295         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2296              port_name(dp_to_dig_port(intel_dp)->port));
2297
2298         pp = ironlake_get_pp_control(intel_dp);
2299         /* We need to switch off panel power _and_ force vdd, for otherwise some
2300          * panels get very unhappy and cease to work. */
2301         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2302                 EDP_BLC_ENABLE);
2303
2304         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2305
2306         intel_dp->want_panel_vdd = false;
2307
2308         I915_WRITE(pp_ctrl_reg, pp);
2309         POSTING_READ(pp_ctrl_reg);
2310
2311         intel_dp->panel_power_off_time = ktime_get_boottime();
2312         wait_panel_off(intel_dp);
2313
2314         /* We got a reference when we enabled the VDD. */
2315         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2316 }
2317
2318 void intel_edp_panel_off(struct intel_dp *intel_dp)
2319 {
2320         if (!intel_dp_is_edp(intel_dp))
2321                 return;
2322
2323         pps_lock(intel_dp);
2324         edp_panel_off(intel_dp);
2325         pps_unlock(intel_dp);
2326 }
2327
2328 /* Enable backlight in the panel power control. */
2329 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2330 {
2331         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2332         struct drm_device *dev = intel_dig_port->base.base.dev;
2333         struct drm_i915_private *dev_priv = to_i915(dev);
2334         u32 pp;
2335         i915_reg_t pp_ctrl_reg;
2336
2337         /*
2338          * If we enable the backlight right away following a panel power
2339          * on, we may see slight flicker as the panel syncs with the eDP
2340          * link.  So delay a bit to make sure the image is solid before
2341          * allowing it to appear.
2342          */
2343         wait_backlight_on(intel_dp);
2344
2345         pps_lock(intel_dp);
2346
2347         pp = ironlake_get_pp_control(intel_dp);
2348         pp |= EDP_BLC_ENABLE;
2349
2350         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2351
2352         I915_WRITE(pp_ctrl_reg, pp);
2353         POSTING_READ(pp_ctrl_reg);
2354
2355         pps_unlock(intel_dp);
2356 }
2357
2358 /* Enable backlight PWM and backlight PP control. */
2359 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2360                             const struct drm_connector_state *conn_state)
2361 {
2362         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2363
2364         if (!intel_dp_is_edp(intel_dp))
2365                 return;
2366
2367         DRM_DEBUG_KMS("\n");
2368
2369         intel_panel_enable_backlight(crtc_state, conn_state);
2370         _intel_edp_backlight_on(intel_dp);
2371 }
2372
2373 /* Disable backlight in the panel power control. */
2374 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2375 {
2376         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2377         struct drm_i915_private *dev_priv = to_i915(dev);
2378         u32 pp;
2379         i915_reg_t pp_ctrl_reg;
2380
2381         if (!intel_dp_is_edp(intel_dp))
2382                 return;
2383
2384         pps_lock(intel_dp);
2385
2386         pp = ironlake_get_pp_control(intel_dp);
2387         pp &= ~EDP_BLC_ENABLE;
2388
2389         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2390
2391         I915_WRITE(pp_ctrl_reg, pp);
2392         POSTING_READ(pp_ctrl_reg);
2393
2394         pps_unlock(intel_dp);
2395
2396         intel_dp->last_backlight_off = jiffies;
2397         edp_wait_backlight_off(intel_dp);
2398 }
2399
2400 /* Disable backlight PP control and backlight PWM. */
2401 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2402 {
2403         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2404
2405         if (!intel_dp_is_edp(intel_dp))
2406                 return;
2407
2408         DRM_DEBUG_KMS("\n");
2409
2410         _intel_edp_backlight_off(intel_dp);
2411         intel_panel_disable_backlight(old_conn_state);
2412 }
2413
2414 /*
2415  * Hook for controlling the panel power control backlight through the bl_power
2416  * sysfs attribute. Take care to handle multiple calls.
2417  */
2418 static void intel_edp_backlight_power(struct intel_connector *connector,
2419                                       bool enable)
2420 {
2421         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2422         bool is_enabled;
2423
2424         pps_lock(intel_dp);
2425         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2426         pps_unlock(intel_dp);
2427
2428         if (is_enabled == enable)
2429                 return;
2430
2431         DRM_DEBUG_KMS("panel power control backlight %s\n",
2432                       enable ? "enable" : "disable");
2433
2434         if (enable)
2435                 _intel_edp_backlight_on(intel_dp);
2436         else
2437                 _intel_edp_backlight_off(intel_dp);
2438 }
2439
2440 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2441 {
2442         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2443         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2444         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2445
2446         I915_STATE_WARN(cur_state != state,
2447                         "DP port %c state assertion failure (expected %s, current %s)\n",
2448                         port_name(dig_port->port),
2449                         onoff(state), onoff(cur_state));
2450 }
2451 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2452
2453 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2454 {
2455         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2456
2457         I915_STATE_WARN(cur_state != state,
2458                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2459                         onoff(state), onoff(cur_state));
2460 }
2461 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2462 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2463
2464 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2465                                 const struct intel_crtc_state *pipe_config)
2466 {
2467         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2468         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2469
2470         assert_pipe_disabled(dev_priv, crtc->pipe);
2471         assert_dp_port_disabled(intel_dp);
2472         assert_edp_pll_disabled(dev_priv);
2473
2474         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2475                       pipe_config->port_clock);
2476
2477         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2478
2479         if (pipe_config->port_clock == 162000)
2480                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2481         else
2482                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2483
2484         I915_WRITE(DP_A, intel_dp->DP);
2485         POSTING_READ(DP_A);
2486         udelay(500);
2487
2488         /*
2489          * [DevILK] Work around required when enabling DP PLL
2490          * while a pipe is enabled going to FDI:
2491          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2492          * 2. Program DP PLL enable
2493          */
2494         if (IS_GEN5(dev_priv))
2495                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2496
2497         intel_dp->DP |= DP_PLL_ENABLE;
2498
2499         I915_WRITE(DP_A, intel_dp->DP);
2500         POSTING_READ(DP_A);
2501         udelay(200);
2502 }
2503
2504 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2505 {
2506         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2507         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2508         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2509
2510         assert_pipe_disabled(dev_priv, crtc->pipe);
2511         assert_dp_port_disabled(intel_dp);
2512         assert_edp_pll_enabled(dev_priv);
2513
2514         DRM_DEBUG_KMS("disabling eDP PLL\n");
2515
2516         intel_dp->DP &= ~DP_PLL_ENABLE;
2517
2518         I915_WRITE(DP_A, intel_dp->DP);
2519         POSTING_READ(DP_A);
2520         udelay(200);
2521 }
2522
2523 /* If the sink supports it, try to set the power state appropriately */
2524 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2525 {
2526         int ret, i;
2527
2528         /* Should have a valid DPCD by this point */
2529         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2530                 return;
2531
2532         if (mode != DRM_MODE_DPMS_ON) {
2533                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2534                                          DP_SET_POWER_D3);
2535         } else {
2536                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2537
2538                 /*
2539                  * When turning on, we need to retry for 1ms to give the sink
2540                  * time to wake up.
2541                  */
2542                 for (i = 0; i < 3; i++) {
2543                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2544                                                  DP_SET_POWER_D0);
2545                         if (ret == 1)
2546                                 break;
2547                         msleep(1);
2548                 }
2549
2550                 if (ret == 1 && lspcon->active)
2551                         lspcon_wait_pcon_mode(lspcon);
2552         }
2553
2554         if (ret != 1)
2555                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2556                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2557 }
2558
2559 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2560                                   enum pipe *pipe)
2561 {
2562         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2563         enum port port = dp_to_dig_port(intel_dp)->port;
2564         struct drm_device *dev = encoder->base.dev;
2565         struct drm_i915_private *dev_priv = to_i915(dev);
2566         u32 tmp;
2567         bool ret;
2568
2569         if (!intel_display_power_get_if_enabled(dev_priv,
2570                                                 encoder->power_domain))
2571                 return false;
2572
2573         ret = false;
2574
2575         tmp = I915_READ(intel_dp->output_reg);
2576
2577         if (!(tmp & DP_PORT_EN))
2578                 goto out;
2579
2580         if (IS_GEN7(dev_priv) && port == PORT_A) {
2581                 *pipe = PORT_TO_PIPE_CPT(tmp);
2582         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2583                 enum pipe p;
2584
2585                 for_each_pipe(dev_priv, p) {
2586                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2587                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2588                                 *pipe = p;
2589                                 ret = true;
2590
2591                                 goto out;
2592                         }
2593                 }
2594
2595                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2596                               i915_mmio_reg_offset(intel_dp->output_reg));
2597         } else if (IS_CHERRYVIEW(dev_priv)) {
2598                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2599         } else {
2600                 *pipe = PORT_TO_PIPE(tmp);
2601         }
2602
2603         ret = true;
2604
2605 out:
2606         intel_display_power_put(dev_priv, encoder->power_domain);
2607
2608         return ret;
2609 }
2610
2611 static void intel_dp_get_config(struct intel_encoder *encoder,
2612                                 struct intel_crtc_state *pipe_config)
2613 {
2614         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2615         u32 tmp, flags = 0;
2616         struct drm_device *dev = encoder->base.dev;
2617         struct drm_i915_private *dev_priv = to_i915(dev);
2618         enum port port = dp_to_dig_port(intel_dp)->port;
2619         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2620
2621         tmp = I915_READ(intel_dp->output_reg);
2622
2623         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2624
2625         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2626                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2627
2628                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2629                         flags |= DRM_MODE_FLAG_PHSYNC;
2630                 else
2631                         flags |= DRM_MODE_FLAG_NHSYNC;
2632
2633                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2634                         flags |= DRM_MODE_FLAG_PVSYNC;
2635                 else
2636                         flags |= DRM_MODE_FLAG_NVSYNC;
2637         } else {
2638                 if (tmp & DP_SYNC_HS_HIGH)
2639                         flags |= DRM_MODE_FLAG_PHSYNC;
2640                 else
2641                         flags |= DRM_MODE_FLAG_NHSYNC;
2642
2643                 if (tmp & DP_SYNC_VS_HIGH)
2644                         flags |= DRM_MODE_FLAG_PVSYNC;
2645                 else
2646                         flags |= DRM_MODE_FLAG_NVSYNC;
2647         }
2648
2649         pipe_config->base.adjusted_mode.flags |= flags;
2650
2651         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2652                 pipe_config->limited_color_range = true;
2653
2654         pipe_config->lane_count =
2655                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2656
2657         intel_dp_get_m_n(crtc, pipe_config);
2658
2659         if (port == PORT_A) {
2660                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2661                         pipe_config->port_clock = 162000;
2662                 else
2663                         pipe_config->port_clock = 270000;
2664         }
2665
2666         pipe_config->base.adjusted_mode.crtc_clock =
2667                 intel_dotclock_calculate(pipe_config->port_clock,
2668                                          &pipe_config->dp_m_n);
2669
2670         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2671             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2672                 /*
2673                  * This is a big fat ugly hack.
2674                  *
2675                  * Some machines in UEFI boot mode provide us a VBT that has 18
2676                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2677                  * unknown we fail to light up. Yet the same BIOS boots up with
2678                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2679                  * max, not what it tells us to use.
2680                  *
2681                  * Note: This will still be broken if the eDP panel is not lit
2682                  * up by the BIOS, and thus we can't get the mode at module
2683                  * load.
2684                  */
2685                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2686                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2687                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2688         }
2689 }
2690
2691 static void intel_disable_dp(struct intel_encoder *encoder,
2692                              const struct intel_crtc_state *old_crtc_state,
2693                              const struct drm_connector_state *old_conn_state)
2694 {
2695         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2696
2697         if (old_crtc_state->has_audio)
2698                 intel_audio_codec_disable(encoder);
2699
2700         /* Make sure the panel is off before trying to change the mode. But also
2701          * ensure that we have vdd while we switch off the panel. */
2702         intel_edp_panel_vdd_on(intel_dp);
2703         intel_edp_backlight_off(old_conn_state);
2704         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2705         intel_edp_panel_off(intel_dp);
2706 }
2707
2708 static void g4x_disable_dp(struct intel_encoder *encoder,
2709                            const struct intel_crtc_state *old_crtc_state,
2710                            const struct drm_connector_state *old_conn_state)
2711 {
2712         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2713
2714         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2715
2716         /* disable the port before the pipe on g4x */
2717         intel_dp_link_down(intel_dp);
2718 }
2719
2720 static void ilk_disable_dp(struct intel_encoder *encoder,
2721                            const struct intel_crtc_state *old_crtc_state,
2722                            const struct drm_connector_state *old_conn_state)
2723 {
2724         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2725 }
2726
2727 static void vlv_disable_dp(struct intel_encoder *encoder,
2728                            const struct intel_crtc_state *old_crtc_state,
2729                            const struct drm_connector_state *old_conn_state)
2730 {
2731         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2732
2733         intel_psr_disable(intel_dp, old_crtc_state);
2734
2735         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2736 }
2737
2738 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2739                                 const struct intel_crtc_state *old_crtc_state,
2740                                 const struct drm_connector_state *old_conn_state)
2741 {
2742         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2743         enum port port = dp_to_dig_port(intel_dp)->port;
2744
2745         intel_dp_link_down(intel_dp);
2746
2747         /* Only ilk+ has port A */
2748         if (port == PORT_A)
2749                 ironlake_edp_pll_off(intel_dp);
2750 }
2751
2752 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2753                                 const struct intel_crtc_state *old_crtc_state,
2754                                 const struct drm_connector_state *old_conn_state)
2755 {
2756         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2757
2758         intel_dp_link_down(intel_dp);
2759 }
2760
2761 static void chv_post_disable_dp(struct intel_encoder *encoder,
2762                                 const struct intel_crtc_state *old_crtc_state,
2763                                 const struct drm_connector_state *old_conn_state)
2764 {
2765         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2766         struct drm_device *dev = encoder->base.dev;
2767         struct drm_i915_private *dev_priv = to_i915(dev);
2768
2769         intel_dp_link_down(intel_dp);
2770
2771         mutex_lock(&dev_priv->sb_lock);
2772
2773         /* Assert data lane reset */
2774         chv_data_lane_soft_reset(encoder, true);
2775
2776         mutex_unlock(&dev_priv->sb_lock);
2777 }
2778
2779 static void
2780 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2781                          uint32_t *DP,
2782                          uint8_t dp_train_pat)
2783 {
2784         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2785         struct drm_device *dev = intel_dig_port->base.base.dev;
2786         struct drm_i915_private *dev_priv = to_i915(dev);
2787         enum port port = intel_dig_port->port;
2788
2789         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2790                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2791                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2792
2793         if (HAS_DDI(dev_priv)) {
2794                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2795
2796                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2797                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2798                 else
2799                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2800
2801                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2802                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2803                 case DP_TRAINING_PATTERN_DISABLE:
2804                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2805
2806                         break;
2807                 case DP_TRAINING_PATTERN_1:
2808                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2809                         break;
2810                 case DP_TRAINING_PATTERN_2:
2811                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2812                         break;
2813                 case DP_TRAINING_PATTERN_3:
2814                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2815                         break;
2816                 }
2817                 I915_WRITE(DP_TP_CTL(port), temp);
2818
2819         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2820                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2821                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2822
2823                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2824                 case DP_TRAINING_PATTERN_DISABLE:
2825                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2826                         break;
2827                 case DP_TRAINING_PATTERN_1:
2828                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2829                         break;
2830                 case DP_TRAINING_PATTERN_2:
2831                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2832                         break;
2833                 case DP_TRAINING_PATTERN_3:
2834                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2835                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2836                         break;
2837                 }
2838
2839         } else {
2840                 if (IS_CHERRYVIEW(dev_priv))
2841                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2842                 else
2843                         *DP &= ~DP_LINK_TRAIN_MASK;
2844
2845                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2846                 case DP_TRAINING_PATTERN_DISABLE:
2847                         *DP |= DP_LINK_TRAIN_OFF;
2848                         break;
2849                 case DP_TRAINING_PATTERN_1:
2850                         *DP |= DP_LINK_TRAIN_PAT_1;
2851                         break;
2852                 case DP_TRAINING_PATTERN_2:
2853                         *DP |= DP_LINK_TRAIN_PAT_2;
2854                         break;
2855                 case DP_TRAINING_PATTERN_3:
2856                         if (IS_CHERRYVIEW(dev_priv)) {
2857                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2858                         } else {
2859                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2860                                 *DP |= DP_LINK_TRAIN_PAT_2;
2861                         }
2862                         break;
2863                 }
2864         }
2865 }
2866
2867 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2868                                  const struct intel_crtc_state *old_crtc_state)
2869 {
2870         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2871         struct drm_i915_private *dev_priv = to_i915(dev);
2872
2873         /* enable with pattern 1 (as per spec) */
2874
2875         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2876
2877         /*
2878          * Magic for VLV/CHV. We _must_ first set up the register
2879          * without actually enabling the port, and then do another
2880          * write to enable the port. Otherwise link training will
2881          * fail when the power sequencer is freshly used for this port.
2882          */
2883         intel_dp->DP |= DP_PORT_EN;
2884         if (old_crtc_state->has_audio)
2885                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2886
2887         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2888         POSTING_READ(intel_dp->output_reg);
2889 }
2890
2891 static void intel_enable_dp(struct intel_encoder *encoder,
2892                             const struct intel_crtc_state *pipe_config,
2893                             const struct drm_connector_state *conn_state)
2894 {
2895         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2896         struct drm_device *dev = encoder->base.dev;
2897         struct drm_i915_private *dev_priv = to_i915(dev);
2898         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2899         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2900         enum pipe pipe = crtc->pipe;
2901
2902         if (WARN_ON(dp_reg & DP_PORT_EN))
2903                 return;
2904
2905         pps_lock(intel_dp);
2906
2907         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2908                 vlv_init_panel_power_sequencer(intel_dp);
2909
2910         intel_dp_enable_port(intel_dp, pipe_config);
2911
2912         edp_panel_vdd_on(intel_dp);
2913         edp_panel_on(intel_dp);
2914         edp_panel_vdd_off(intel_dp, true);
2915
2916         pps_unlock(intel_dp);
2917
2918         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2919                 unsigned int lane_mask = 0x0;
2920
2921                 if (IS_CHERRYVIEW(dev_priv))
2922                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2923
2924                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2925                                     lane_mask);
2926         }
2927
2928         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2929         intel_dp_start_link_train(intel_dp);
2930         intel_dp_stop_link_train(intel_dp);
2931
2932         if (pipe_config->has_audio) {
2933                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2934                                  pipe_name(pipe));
2935                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2936         }
2937 }
2938
2939 static void g4x_enable_dp(struct intel_encoder *encoder,
2940                           const struct intel_crtc_state *pipe_config,
2941                           const struct drm_connector_state *conn_state)
2942 {
2943         intel_enable_dp(encoder, pipe_config, conn_state);
2944         intel_edp_backlight_on(pipe_config, conn_state);
2945 }
2946
2947 static void vlv_enable_dp(struct intel_encoder *encoder,
2948                           const struct intel_crtc_state *pipe_config,
2949                           const struct drm_connector_state *conn_state)
2950 {
2951         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2952
2953         intel_edp_backlight_on(pipe_config, conn_state);
2954         intel_psr_enable(intel_dp, pipe_config);
2955 }
2956
2957 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2958                               const struct intel_crtc_state *pipe_config,
2959                               const struct drm_connector_state *conn_state)
2960 {
2961         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2962         enum port port = dp_to_dig_port(intel_dp)->port;
2963
2964         intel_dp_prepare(encoder, pipe_config);
2965
2966         /* Only ilk+ has port A */
2967         if (port == PORT_A)
2968                 ironlake_edp_pll_on(intel_dp, pipe_config);
2969 }
2970
2971 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2972 {
2973         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2974         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2975         enum pipe pipe = intel_dp->pps_pipe;
2976         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2977
2978         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2979
2980         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2981                 return;
2982
2983         edp_panel_vdd_off_sync(intel_dp);
2984
2985         /*
2986          * VLV seems to get confused when multiple power seqeuencers
2987          * have the same port selected (even if only one has power/vdd
2988          * enabled). The failure manifests as vlv_wait_port_ready() failing
2989          * CHV on the other hand doesn't seem to mind having the same port
2990          * selected in multiple power seqeuencers, but let's clear the
2991          * port select always when logically disconnecting a power sequencer
2992          * from a port.
2993          */
2994         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2995                       pipe_name(pipe), port_name(intel_dig_port->port));
2996         I915_WRITE(pp_on_reg, 0);
2997         POSTING_READ(pp_on_reg);
2998
2999         intel_dp->pps_pipe = INVALID_PIPE;
3000 }
3001
3002 static void vlv_steal_power_sequencer(struct drm_device *dev,
3003                                       enum pipe pipe)
3004 {
3005         struct drm_i915_private *dev_priv = to_i915(dev);
3006         struct intel_encoder *encoder;
3007
3008         lockdep_assert_held(&dev_priv->pps_mutex);
3009
3010         for_each_intel_encoder(dev, encoder) {
3011                 struct intel_dp *intel_dp;
3012                 enum port port;
3013
3014                 if (encoder->type != INTEL_OUTPUT_DP &&
3015                     encoder->type != INTEL_OUTPUT_EDP)
3016                         continue;
3017
3018                 intel_dp = enc_to_intel_dp(&encoder->base);
3019                 port = dp_to_dig_port(intel_dp)->port;
3020
3021                 WARN(intel_dp->active_pipe == pipe,
3022                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3023                      pipe_name(pipe), port_name(port));
3024
3025                 if (intel_dp->pps_pipe != pipe)
3026                         continue;
3027
3028                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3029                               pipe_name(pipe), port_name(port));
3030
3031                 /* make sure vdd is off before we steal it */
3032                 vlv_detach_power_sequencer(intel_dp);
3033         }
3034 }
3035
3036 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
3037 {
3038         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3039         struct intel_encoder *encoder = &intel_dig_port->base;
3040         struct drm_device *dev = encoder->base.dev;
3041         struct drm_i915_private *dev_priv = to_i915(dev);
3042         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
3043
3044         lockdep_assert_held(&dev_priv->pps_mutex);
3045
3046         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3047
3048         if (intel_dp->pps_pipe != INVALID_PIPE &&
3049             intel_dp->pps_pipe != crtc->pipe) {
3050                 /*
3051                  * If another power sequencer was being used on this
3052                  * port previously make sure to turn off vdd there while
3053                  * we still have control of it.
3054                  */
3055                 vlv_detach_power_sequencer(intel_dp);
3056         }
3057
3058         /*
3059          * We may be stealing the power
3060          * sequencer from another port.
3061          */
3062         vlv_steal_power_sequencer(dev, crtc->pipe);
3063
3064         intel_dp->active_pipe = crtc->pipe;
3065
3066         if (!intel_dp_is_edp(intel_dp))
3067                 return;
3068
3069         /* now it's all ours */
3070         intel_dp->pps_pipe = crtc->pipe;
3071
3072         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3073                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
3074
3075         /* init power sequencer on this pipe and port */
3076         intel_dp_init_panel_power_sequencer(dev, intel_dp);
3077         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
3078 }
3079
3080 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3081                               const struct intel_crtc_state *pipe_config,
3082                               const struct drm_connector_state *conn_state)
3083 {
3084         vlv_phy_pre_encoder_enable(encoder);
3085
3086         intel_enable_dp(encoder, pipe_config, conn_state);
3087 }
3088
3089 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3090                                   const struct intel_crtc_state *pipe_config,
3091                                   const struct drm_connector_state *conn_state)
3092 {
3093         intel_dp_prepare(encoder, pipe_config);
3094
3095         vlv_phy_pre_pll_enable(encoder);
3096 }
3097
3098 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3099                               const struct intel_crtc_state *pipe_config,
3100                               const struct drm_connector_state *conn_state)
3101 {
3102         chv_phy_pre_encoder_enable(encoder);
3103
3104         intel_enable_dp(encoder, pipe_config, conn_state);
3105
3106         /* Second common lane will stay alive on its own now */
3107         chv_phy_release_cl2_override(encoder);
3108 }
3109
3110 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3111                                   const struct intel_crtc_state *pipe_config,
3112                                   const struct drm_connector_state *conn_state)
3113 {
3114         intel_dp_prepare(encoder, pipe_config);
3115
3116         chv_phy_pre_pll_enable(encoder);
3117 }
3118
3119 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3120                                     const struct intel_crtc_state *pipe_config,
3121                                     const struct drm_connector_state *conn_state)
3122 {
3123         chv_phy_post_pll_disable(encoder);
3124 }
3125
3126 /*
3127  * Fetch AUX CH registers 0x202 - 0x207 which contain
3128  * link status information
3129  */
3130 bool
3131 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3132 {
3133         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3134                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3135 }
3136
3137 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3138 {
3139         uint8_t psr_caps = 0;
3140
3141         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
3142                 return false;
3143         return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3144 }
3145
3146 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3147 {
3148         uint8_t dprx = 0;
3149
3150         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3151                               &dprx) != 1)
3152                 return false;
3153         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3154 }
3155
3156 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3157 {
3158         uint8_t alpm_caps = 0;
3159
3160         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
3161                               &alpm_caps) != 1)
3162                 return false;
3163         return alpm_caps & DP_ALPM_CAP;
3164 }
3165
3166 /* These are source-specific values. */
3167 uint8_t
3168 intel_dp_voltage_max(struct intel_dp *intel_dp)
3169 {
3170         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3171         enum port port = dp_to_dig_port(intel_dp)->port;
3172
3173         if (IS_GEN9_LP(dev_priv))
3174                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3175         else if (INTEL_GEN(dev_priv) >= 9) {
3176                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3177                 return intel_ddi_dp_voltage_max(encoder);
3178         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3179                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3180         else if (IS_GEN7(dev_priv) && port == PORT_A)
3181                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3182         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3183                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3184         else
3185                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3186 }
3187
3188 uint8_t
3189 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3190 {
3191         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3192         enum port port = dp_to_dig_port(intel_dp)->port;
3193
3194         if (INTEL_GEN(dev_priv) >= 9) {
3195                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3196                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3197                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3198                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3199                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3200                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3201                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3202                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3203                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3204                 default:
3205                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3206                 }
3207         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3208                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3209                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3210                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3211                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3212                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3213                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3214                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3215                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3216                 default:
3217                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3218                 }
3219         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3220                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3221                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3222                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3223                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3224                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3225                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3226                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3227                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3228                 default:
3229                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3230                 }
3231         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3232                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3233                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3234                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3235                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3236                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3237                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3238                 default:
3239                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3240                 }
3241         } else {
3242                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3243                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3244                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3245                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3246                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3247                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3248                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3249                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3250                 default:
3251                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3252                 }
3253         }
3254 }
3255
3256 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3257 {
3258         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3259         unsigned long demph_reg_value, preemph_reg_value,
3260                 uniqtranscale_reg_value;
3261         uint8_t train_set = intel_dp->train_set[0];
3262
3263         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3264         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3265                 preemph_reg_value = 0x0004000;
3266                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3267                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3268                         demph_reg_value = 0x2B405555;
3269                         uniqtranscale_reg_value = 0x552AB83A;
3270                         break;
3271                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3272                         demph_reg_value = 0x2B404040;
3273                         uniqtranscale_reg_value = 0x5548B83A;
3274                         break;
3275                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3276                         demph_reg_value = 0x2B245555;
3277                         uniqtranscale_reg_value = 0x5560B83A;
3278                         break;
3279                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3280                         demph_reg_value = 0x2B405555;
3281                         uniqtranscale_reg_value = 0x5598DA3A;
3282                         break;
3283                 default:
3284                         return 0;
3285                 }
3286                 break;
3287         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3288                 preemph_reg_value = 0x0002000;
3289                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3290                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3291                         demph_reg_value = 0x2B404040;
3292                         uniqtranscale_reg_value = 0x5552B83A;
3293                         break;
3294                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3295                         demph_reg_value = 0x2B404848;
3296                         uniqtranscale_reg_value = 0x5580B83A;
3297                         break;
3298                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3299                         demph_reg_value = 0x2B404040;
3300                         uniqtranscale_reg_value = 0x55ADDA3A;
3301                         break;
3302                 default:
3303                         return 0;
3304                 }
3305                 break;
3306         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3307                 preemph_reg_value = 0x0000000;
3308                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3309                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3310                         demph_reg_value = 0x2B305555;
3311                         uniqtranscale_reg_value = 0x5570B83A;
3312                         break;
3313                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3314                         demph_reg_value = 0x2B2B4040;
3315                         uniqtranscale_reg_value = 0x55ADDA3A;
3316                         break;
3317                 default:
3318                         return 0;
3319                 }
3320                 break;
3321         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3322                 preemph_reg_value = 0x0006000;
3323                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3324                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3325                         demph_reg_value = 0x1B405555;
3326                         uniqtranscale_reg_value = 0x55ADDA3A;
3327                         break;
3328                 default:
3329                         return 0;
3330                 }
3331                 break;
3332         default:
3333                 return 0;
3334         }
3335
3336         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3337                                  uniqtranscale_reg_value, 0);
3338
3339         return 0;
3340 }
3341
3342 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3343 {
3344         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3345         u32 deemph_reg_value, margin_reg_value;
3346         bool uniq_trans_scale = false;
3347         uint8_t train_set = intel_dp->train_set[0];
3348
3349         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3350         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3351                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3352                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3353                         deemph_reg_value = 128;
3354                         margin_reg_value = 52;
3355                         break;
3356                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3357                         deemph_reg_value = 128;
3358                         margin_reg_value = 77;
3359                         break;
3360                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3361                         deemph_reg_value = 128;
3362                         margin_reg_value = 102;
3363                         break;
3364                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3365                         deemph_reg_value = 128;
3366                         margin_reg_value = 154;
3367                         uniq_trans_scale = true;
3368                         break;
3369                 default:
3370                         return 0;
3371                 }
3372                 break;
3373         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3374                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3375                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3376                         deemph_reg_value = 85;
3377                         margin_reg_value = 78;
3378                         break;
3379                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3380                         deemph_reg_value = 85;
3381                         margin_reg_value = 116;
3382                         break;
3383                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3384                         deemph_reg_value = 85;
3385                         margin_reg_value = 154;
3386                         break;
3387                 default:
3388                         return 0;
3389                 }
3390                 break;
3391         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3392                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3393                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3394                         deemph_reg_value = 64;
3395                         margin_reg_value = 104;
3396                         break;
3397                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3398                         deemph_reg_value = 64;
3399                         margin_reg_value = 154;
3400                         break;
3401                 default:
3402                         return 0;
3403                 }
3404                 break;
3405         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3406                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3407                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3408                         deemph_reg_value = 43;
3409                         margin_reg_value = 154;
3410                         break;
3411                 default:
3412                         return 0;
3413                 }
3414                 break;
3415         default:
3416                 return 0;
3417         }
3418
3419         chv_set_phy_signal_level(encoder, deemph_reg_value,
3420                                  margin_reg_value, uniq_trans_scale);
3421
3422         return 0;
3423 }
3424
3425 static uint32_t
3426 gen4_signal_levels(uint8_t train_set)
3427 {
3428         uint32_t        signal_levels = 0;
3429
3430         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3431         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3432         default:
3433                 signal_levels |= DP_VOLTAGE_0_4;
3434                 break;
3435         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3436                 signal_levels |= DP_VOLTAGE_0_6;
3437                 break;
3438         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3439                 signal_levels |= DP_VOLTAGE_0_8;
3440                 break;
3441         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3442                 signal_levels |= DP_VOLTAGE_1_2;
3443                 break;
3444         }
3445         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3446         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3447         default:
3448                 signal_levels |= DP_PRE_EMPHASIS_0;
3449                 break;
3450         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3451                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3452                 break;
3453         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3454                 signal_levels |= DP_PRE_EMPHASIS_6;
3455                 break;
3456         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3457                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3458                 break;
3459         }
3460         return signal_levels;
3461 }
3462
3463 /* Gen6's DP voltage swing and pre-emphasis control */
3464 static uint32_t
3465 gen6_edp_signal_levels(uint8_t train_set)
3466 {
3467         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3468                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3469         switch (signal_levels) {
3470         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3471         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3472                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3473         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3474                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3475         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3476         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3477                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3478         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3479         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3480                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3481         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3482         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3483                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3484         default:
3485                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3486                               "0x%x\n", signal_levels);
3487                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3488         }
3489 }
3490
3491 /* Gen7's DP voltage swing and pre-emphasis control */
3492 static uint32_t
3493 gen7_edp_signal_levels(uint8_t train_set)
3494 {
3495         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3496                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3497         switch (signal_levels) {
3498         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3499                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3500         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3501                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3502         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3503                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3504
3505         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3506                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3507         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3508                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3509
3510         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3511                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3512         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3513                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3514
3515         default:
3516                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3517                               "0x%x\n", signal_levels);
3518                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3519         }
3520 }
3521
3522 void
3523 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3524 {
3525         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3526         enum port port = intel_dig_port->port;
3527         struct drm_device *dev = intel_dig_port->base.base.dev;
3528         struct drm_i915_private *dev_priv = to_i915(dev);
3529         uint32_t signal_levels, mask = 0;
3530         uint8_t train_set = intel_dp->train_set[0];
3531
3532         if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3533                 signal_levels = bxt_signal_levels(intel_dp);
3534         } else if (HAS_DDI(dev_priv)) {
3535                 signal_levels = ddi_signal_levels(intel_dp);
3536                 mask = DDI_BUF_EMP_MASK;
3537         } else if (IS_CHERRYVIEW(dev_priv)) {
3538                 signal_levels = chv_signal_levels(intel_dp);
3539         } else if (IS_VALLEYVIEW(dev_priv)) {
3540                 signal_levels = vlv_signal_levels(intel_dp);
3541         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3542                 signal_levels = gen7_edp_signal_levels(train_set);
3543                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3544         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3545                 signal_levels = gen6_edp_signal_levels(train_set);
3546                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3547         } else {
3548                 signal_levels = gen4_signal_levels(train_set);
3549                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3550         }
3551
3552         if (mask)
3553                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3554
3555         DRM_DEBUG_KMS("Using vswing level %d\n",
3556                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3557         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3558                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3559                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3560
3561         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3562
3563         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3564         POSTING_READ(intel_dp->output_reg);
3565 }
3566
3567 void
3568 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3569                                        uint8_t dp_train_pat)
3570 {
3571         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3572         struct drm_i915_private *dev_priv =
3573                 to_i915(intel_dig_port->base.base.dev);
3574
3575         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3576
3577         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3578         POSTING_READ(intel_dp->output_reg);
3579 }
3580
3581 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3582 {
3583         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3584         struct drm_device *dev = intel_dig_port->base.base.dev;
3585         struct drm_i915_private *dev_priv = to_i915(dev);
3586         enum port port = intel_dig_port->port;
3587         uint32_t val;
3588
3589         if (!HAS_DDI(dev_priv))
3590                 return;
3591
3592         val = I915_READ(DP_TP_CTL(port));
3593         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3594         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3595         I915_WRITE(DP_TP_CTL(port), val);
3596
3597         /*
3598          * On PORT_A we can have only eDP in SST mode. There the only reason
3599          * we need to set idle transmission mode is to work around a HW issue
3600          * where we enable the pipe while not in idle link-training mode.
3601          * In this case there is requirement to wait for a minimum number of
3602          * idle patterns to be sent.
3603          */
3604         if (port == PORT_A)
3605                 return;
3606
3607         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3608                                     DP_TP_STATUS_IDLE_DONE,
3609                                     DP_TP_STATUS_IDLE_DONE,
3610                                     1))
3611                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3612 }
3613
3614 static void
3615 intel_dp_link_down(struct intel_dp *intel_dp)
3616 {
3617         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3618         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3619         enum port port = intel_dig_port->port;
3620         struct drm_device *dev = intel_dig_port->base.base.dev;
3621         struct drm_i915_private *dev_priv = to_i915(dev);
3622         uint32_t DP = intel_dp->DP;
3623
3624         if (WARN_ON(HAS_DDI(dev_priv)))
3625                 return;
3626
3627         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3628                 return;
3629
3630         DRM_DEBUG_KMS("\n");
3631
3632         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3633             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3634                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3635                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3636         } else {
3637                 if (IS_CHERRYVIEW(dev_priv))
3638                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3639                 else
3640                         DP &= ~DP_LINK_TRAIN_MASK;
3641                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3642         }
3643         I915_WRITE(intel_dp->output_reg, DP);
3644         POSTING_READ(intel_dp->output_reg);
3645
3646         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3647         I915_WRITE(intel_dp->output_reg, DP);
3648         POSTING_READ(intel_dp->output_reg);
3649
3650         /*
3651          * HW workaround for IBX, we need to move the port
3652          * to transcoder A after disabling it to allow the
3653          * matching HDMI port to be enabled on transcoder A.
3654          */
3655         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3656                 /*
3657                  * We get CPU/PCH FIFO underruns on the other pipe when
3658                  * doing the workaround. Sweep them under the rug.
3659                  */
3660                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3661                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3662
3663                 /* always enable with pattern 1 (as per spec) */
3664                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3665                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3666                 I915_WRITE(intel_dp->output_reg, DP);
3667                 POSTING_READ(intel_dp->output_reg);
3668
3669                 DP &= ~DP_PORT_EN;
3670                 I915_WRITE(intel_dp->output_reg, DP);
3671                 POSTING_READ(intel_dp->output_reg);
3672
3673                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3674                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3675                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3676         }
3677
3678         msleep(intel_dp->panel_power_down_delay);
3679
3680         intel_dp->DP = DP;
3681
3682         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3683                 pps_lock(intel_dp);
3684                 intel_dp->active_pipe = INVALID_PIPE;
3685                 pps_unlock(intel_dp);
3686         }
3687 }
3688
3689 bool
3690 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3691 {
3692         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3693                              sizeof(intel_dp->dpcd)) < 0)
3694                 return false; /* aux transfer failed */
3695
3696         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3697
3698         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3699 }
3700
3701 static bool
3702 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3703 {
3704         struct drm_i915_private *dev_priv =
3705                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3706
3707         /* this function is meant to be called only once */
3708         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3709
3710         if (!intel_dp_read_dpcd(intel_dp))
3711                 return false;
3712
3713         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3714                          drm_dp_is_branch(intel_dp->dpcd));
3715
3716         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3717                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3718                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3719
3720         /* Check if the panel supports PSR */
3721         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3722                          intel_dp->psr_dpcd,
3723                          sizeof(intel_dp->psr_dpcd));
3724         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3725                 dev_priv->psr.sink_support = true;
3726                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3727         }
3728
3729         if (INTEL_GEN(dev_priv) >= 9 &&
3730             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3731                 uint8_t frame_sync_cap;
3732
3733                 dev_priv->psr.sink_support = true;
3734                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3735                                       DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3736                                       &frame_sync_cap) != 1)
3737                         frame_sync_cap = 0;
3738                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3739                 /* PSR2 needs frame sync as well */
3740                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3741                 DRM_DEBUG_KMS("PSR2 %s on sink",
3742                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3743
3744                 if (dev_priv->psr.psr2_support) {
3745                         dev_priv->psr.y_cord_support =
3746                                 intel_dp_get_y_cord_status(intel_dp);
3747                         dev_priv->psr.colorimetry_support =
3748                                 intel_dp_get_colorimetry_status(intel_dp);
3749                         dev_priv->psr.alpm =
3750                                 intel_dp_get_alpm_status(intel_dp);
3751                 }
3752
3753         }
3754
3755         /* Read the eDP Display control capabilities registers */
3756         if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3757             drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3758                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3759                              sizeof(intel_dp->edp_dpcd))
3760                 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3761                               intel_dp->edp_dpcd);
3762
3763         /* Intermediate frequency support */
3764         if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3765                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3766                 int i;
3767
3768                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3769                                 sink_rates, sizeof(sink_rates));
3770
3771                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3772                         int val = le16_to_cpu(sink_rates[i]);
3773
3774                         if (val == 0)
3775                                 break;
3776
3777                         /* Value read multiplied by 200kHz gives the per-lane
3778                          * link rate in kHz. The source rates are, however,
3779                          * stored in terms of LS_Clk kHz. The full conversion
3780                          * back to symbols is
3781                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3782                          */
3783                         intel_dp->sink_rates[i] = (val * 200) / 10;
3784                 }
3785                 intel_dp->num_sink_rates = i;
3786         }
3787
3788         if (intel_dp->num_sink_rates)
3789                 intel_dp->use_rate_select = true;
3790         else
3791                 intel_dp_set_sink_rates(intel_dp);
3792
3793         intel_dp_set_common_rates(intel_dp);
3794
3795         return true;
3796 }
3797
3798
3799 static bool
3800 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3801 {
3802         u8 sink_count;
3803
3804         if (!intel_dp_read_dpcd(intel_dp))
3805                 return false;
3806
3807         /* Don't clobber cached eDP rates. */
3808         if (!intel_dp_is_edp(intel_dp)) {
3809                 intel_dp_set_sink_rates(intel_dp);
3810                 intel_dp_set_common_rates(intel_dp);
3811         }
3812
3813         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3814                 return false;
3815
3816         /*
3817          * Sink count can change between short pulse hpd hence
3818          * a member variable in intel_dp will track any changes
3819          * between short pulse interrupts.
3820          */
3821         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3822
3823         /*
3824          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3825          * a dongle is present but no display. Unless we require to know
3826          * if a dongle is present or not, we don't need to update
3827          * downstream port information. So, an early return here saves
3828          * time from performing other operations which are not required.
3829          */
3830         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3831                 return false;
3832
3833         if (!drm_dp_is_branch(intel_dp->dpcd))
3834                 return true; /* native DP sink */
3835
3836         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3837                 return true; /* no per-port downstream info */
3838
3839         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3840                              intel_dp->downstream_ports,
3841                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3842                 return false; /* downstream port status fetch failed */
3843
3844         return true;
3845 }
3846
3847 static bool
3848 intel_dp_can_mst(struct intel_dp *intel_dp)
3849 {
3850         u8 mstm_cap;
3851
3852         if (!i915_modparams.enable_dp_mst)
3853                 return false;
3854
3855         if (!intel_dp->can_mst)
3856                 return false;
3857
3858         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3859                 return false;
3860
3861         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3862                 return false;
3863
3864         return mstm_cap & DP_MST_CAP;
3865 }
3866
3867 static void
3868 intel_dp_configure_mst(struct intel_dp *intel_dp)
3869 {
3870         if (!i915_modparams.enable_dp_mst)
3871                 return;
3872
3873         if (!intel_dp->can_mst)
3874                 return;
3875
3876         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3877
3878         if (intel_dp->is_mst)
3879                 DRM_DEBUG_KMS("Sink is MST capable\n");
3880         else
3881                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3882
3883         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3884                                         intel_dp->is_mst);
3885 }
3886
3887 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3888 {
3889         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3890         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3891         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3892         u8 buf;
3893         int ret = 0;
3894         int count = 0;
3895         int attempts = 10;
3896
3897         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3898                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3899                 ret = -EIO;
3900                 goto out;
3901         }
3902
3903         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3904                                buf & ~DP_TEST_SINK_START) < 0) {
3905                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3906                 ret = -EIO;
3907                 goto out;
3908         }
3909
3910         do {
3911                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3912
3913                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3914                                       DP_TEST_SINK_MISC, &buf) < 0) {
3915                         ret = -EIO;
3916                         goto out;
3917                 }
3918                 count = buf & DP_TEST_COUNT_MASK;
3919         } while (--attempts && count);
3920
3921         if (attempts == 0) {
3922                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3923                 ret = -ETIMEDOUT;
3924         }
3925
3926  out:
3927         hsw_enable_ips(intel_crtc);
3928         return ret;
3929 }
3930
3931 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3932 {
3933         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3934         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3935         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3936         u8 buf;
3937         int ret;
3938
3939         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3940                 return -EIO;
3941
3942         if (!(buf & DP_TEST_CRC_SUPPORTED))
3943                 return -ENOTTY;
3944
3945         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3946                 return -EIO;
3947
3948         if (buf & DP_TEST_SINK_START) {
3949                 ret = intel_dp_sink_crc_stop(intel_dp);
3950                 if (ret)
3951                         return ret;
3952         }
3953
3954         hsw_disable_ips(intel_crtc);
3955
3956         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3957                                buf | DP_TEST_SINK_START) < 0) {
3958                 hsw_enable_ips(intel_crtc);
3959                 return -EIO;
3960         }
3961
3962         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3963         return 0;
3964 }
3965
3966 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3967 {
3968         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3969         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3970         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3971         u8 buf;
3972         int count, ret;
3973         int attempts = 6;
3974
3975         ret = intel_dp_sink_crc_start(intel_dp);
3976         if (ret)
3977                 return ret;
3978
3979         do {
3980                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3981
3982                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3983                                       DP_TEST_SINK_MISC, &buf) < 0) {
3984                         ret = -EIO;
3985                         goto stop;
3986                 }
3987                 count = buf & DP_TEST_COUNT_MASK;
3988
3989         } while (--attempts && count == 0);
3990
3991         if (attempts == 0) {
3992                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3993                 ret = -ETIMEDOUT;
3994                 goto stop;
3995         }
3996
3997         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3998                 ret = -EIO;
3999                 goto stop;
4000         }
4001
4002 stop:
4003         intel_dp_sink_crc_stop(intel_dp);
4004         return ret;
4005 }
4006
4007 static bool
4008 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4009 {
4010         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
4011                                  sink_irq_vector) == 1;
4012 }
4013
4014 static bool
4015 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4016 {
4017         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4018                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4019                 DP_DPRX_ESI_LEN;
4020 }
4021
4022 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4023 {
4024         int status = 0;
4025         int test_link_rate;
4026         uint8_t test_lane_count, test_link_bw;
4027         /* (DP CTS 1.2)
4028          * 4.3.1.11
4029          */
4030         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4031         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4032                                    &test_lane_count);
4033
4034         if (status <= 0) {
4035                 DRM_DEBUG_KMS("Lane count read failed\n");
4036                 return DP_TEST_NAK;
4037         }
4038         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4039
4040         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4041                                    &test_link_bw);
4042         if (status <= 0) {
4043                 DRM_DEBUG_KMS("Link Rate read failed\n");
4044                 return DP_TEST_NAK;
4045         }
4046         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4047
4048         /* Validate the requested link rate and lane count */
4049         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4050                                         test_lane_count))
4051                 return DP_TEST_NAK;
4052
4053         intel_dp->compliance.test_lane_count = test_lane_count;
4054         intel_dp->compliance.test_link_rate = test_link_rate;
4055
4056         return DP_TEST_ACK;
4057 }
4058
4059 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4060 {
4061         uint8_t test_pattern;
4062         uint8_t test_misc;
4063         __be16 h_width, v_height;
4064         int status = 0;
4065
4066         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4067         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4068                                    &test_pattern);
4069         if (status <= 0) {
4070                 DRM_DEBUG_KMS("Test pattern read failed\n");
4071                 return DP_TEST_NAK;
4072         }
4073         if (test_pattern != DP_COLOR_RAMP)
4074                 return DP_TEST_NAK;
4075
4076         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4077                                   &h_width, 2);
4078         if (status <= 0) {
4079                 DRM_DEBUG_KMS("H Width read failed\n");
4080                 return DP_TEST_NAK;
4081         }
4082
4083         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4084                                   &v_height, 2);
4085         if (status <= 0) {
4086                 DRM_DEBUG_KMS("V Height read failed\n");
4087                 return DP_TEST_NAK;
4088         }
4089
4090         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4091                                    &test_misc);
4092         if (status <= 0) {
4093                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4094                 return DP_TEST_NAK;
4095         }
4096         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4097                 return DP_TEST_NAK;
4098         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4099                 return DP_TEST_NAK;
4100         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4101         case DP_TEST_BIT_DEPTH_6:
4102                 intel_dp->compliance.test_data.bpc = 6;
4103                 break;
4104         case DP_TEST_BIT_DEPTH_8:
4105                 intel_dp->compliance.test_data.bpc = 8;
4106                 break;
4107         default:
4108                 return DP_TEST_NAK;
4109         }
4110
4111         intel_dp->compliance.test_data.video_pattern = test_pattern;
4112         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4113         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4114         /* Set test active flag here so userspace doesn't interrupt things */
4115         intel_dp->compliance.test_active = 1;
4116
4117         return DP_TEST_ACK;
4118 }
4119
4120 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4121 {
4122         uint8_t test_result = DP_TEST_ACK;
4123         struct intel_connector *intel_connector = intel_dp->attached_connector;
4124         struct drm_connector *connector = &intel_connector->base;
4125
4126         if (intel_connector->detect_edid == NULL ||
4127             connector->edid_corrupt ||
4128             intel_dp->aux.i2c_defer_count > 6) {
4129                 /* Check EDID read for NACKs, DEFERs and corruption
4130                  * (DP CTS 1.2 Core r1.1)
4131                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4132                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4133                  *    4.2.2.6 : EDID corruption detected
4134                  * Use failsafe mode for all cases
4135                  */
4136                 if (intel_dp->aux.i2c_nack_count > 0 ||
4137                         intel_dp->aux.i2c_defer_count > 0)
4138                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4139                                       intel_dp->aux.i2c_nack_count,
4140                                       intel_dp->aux.i2c_defer_count);
4141                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4142         } else {
4143                 struct edid *block = intel_connector->detect_edid;
4144
4145                 /* We have to write the checksum
4146                  * of the last block read
4147                  */
4148                 block += intel_connector->detect_edid->extensions;
4149
4150                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4151                                        block->checksum) <= 0)
4152                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4153
4154                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4155                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4156         }
4157
4158         /* Set test active flag here so userspace doesn't interrupt things */
4159         intel_dp->compliance.test_active = 1;
4160
4161         return test_result;
4162 }
4163
4164 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4165 {
4166         uint8_t test_result = DP_TEST_NAK;
4167         return test_result;
4168 }
4169
4170 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4171 {
4172         uint8_t response = DP_TEST_NAK;
4173         uint8_t request = 0;
4174         int status;
4175
4176         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4177         if (status <= 0) {
4178                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4179                 goto update_status;
4180         }
4181
4182         switch (request) {
4183         case DP_TEST_LINK_TRAINING:
4184                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4185                 response = intel_dp_autotest_link_training(intel_dp);
4186                 break;
4187         case DP_TEST_LINK_VIDEO_PATTERN:
4188                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4189                 response = intel_dp_autotest_video_pattern(intel_dp);
4190                 break;
4191         case DP_TEST_LINK_EDID_READ:
4192                 DRM_DEBUG_KMS("EDID test requested\n");
4193                 response = intel_dp_autotest_edid(intel_dp);
4194                 break;
4195         case DP_TEST_LINK_PHY_TEST_PATTERN:
4196                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4197                 response = intel_dp_autotest_phy_pattern(intel_dp);
4198                 break;
4199         default:
4200                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4201                 break;
4202         }
4203
4204         if (response & DP_TEST_ACK)
4205                 intel_dp->compliance.test_type = request;
4206
4207 update_status:
4208         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4209         if (status <= 0)
4210                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4211 }
4212
4213 static int
4214 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4215 {
4216         bool bret;
4217
4218         if (intel_dp->is_mst) {
4219                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4220                 int ret = 0;
4221                 int retry;
4222                 bool handled;
4223                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4224 go_again:
4225                 if (bret == true) {
4226
4227                         /* check link status - esi[10] = 0x200c */
4228                         if (intel_dp->active_mst_links &&
4229                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4230                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4231                                 intel_dp_start_link_train(intel_dp);
4232                                 intel_dp_stop_link_train(intel_dp);
4233                         }
4234
4235                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4236                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4237
4238                         if (handled) {
4239                                 for (retry = 0; retry < 3; retry++) {
4240                                         int wret;
4241                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4242                                                                  DP_SINK_COUNT_ESI+1,
4243                                                                  &esi[1], 3);
4244                                         if (wret == 3) {
4245                                                 break;
4246                                         }
4247                                 }
4248
4249                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4250                                 if (bret == true) {
4251                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4252                                         goto go_again;
4253                                 }
4254                         } else
4255                                 ret = 0;
4256
4257                         return ret;
4258                 } else {
4259                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4260                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4261                         intel_dp->is_mst = false;
4262                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4263                         /* send a hotplug event */
4264                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4265                 }
4266         }
4267         return -EINVAL;
4268 }
4269
4270 static void
4271 intel_dp_retrain_link(struct intel_dp *intel_dp)
4272 {
4273         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4274         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4275         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4276
4277         /* Suppress underruns caused by re-training */
4278         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4279         if (crtc->config->has_pch_encoder)
4280                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4281                                                       intel_crtc_pch_transcoder(crtc), false);
4282
4283         intel_dp_start_link_train(intel_dp);
4284         intel_dp_stop_link_train(intel_dp);
4285
4286         /* Keep underrun reporting disabled until things are stable */
4287         intel_wait_for_vblank(dev_priv, crtc->pipe);
4288
4289         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4290         if (crtc->config->has_pch_encoder)
4291                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4292                                                       intel_crtc_pch_transcoder(crtc), true);
4293 }
4294
4295 static void
4296 intel_dp_check_link_status(struct intel_dp *intel_dp)
4297 {
4298         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4299         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4300         u8 link_status[DP_LINK_STATUS_SIZE];
4301
4302         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4303
4304         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4305                 DRM_ERROR("Failed to get link status\n");
4306                 return;
4307         }
4308
4309         if (!intel_encoder->base.crtc)
4310                 return;
4311
4312         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4313                 return;
4314
4315         /*
4316          * Validate the cached values of intel_dp->link_rate and
4317          * intel_dp->lane_count before attempting to retrain.
4318          */
4319         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4320                                         intel_dp->lane_count))
4321                 return;
4322
4323         /* Retrain if Channel EQ or CR not ok */
4324         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4325                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4326                               intel_encoder->base.name);
4327
4328                 intel_dp_retrain_link(intel_dp);
4329         }
4330 }
4331
4332 /*
4333  * According to DP spec
4334  * 5.1.2:
4335  *  1. Read DPCD
4336  *  2. Configure link according to Receiver Capabilities
4337  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4338  *  4. Check link status on receipt of hot-plug interrupt
4339  *
4340  * intel_dp_short_pulse -  handles short pulse interrupts
4341  * when full detection is not required.
4342  * Returns %true if short pulse is handled and full detection
4343  * is NOT required and %false otherwise.
4344  */
4345 static bool
4346 intel_dp_short_pulse(struct intel_dp *intel_dp)
4347 {
4348         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4349         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4350         u8 sink_irq_vector = 0;
4351         u8 old_sink_count = intel_dp->sink_count;
4352         bool ret;
4353
4354         /*
4355          * Clearing compliance test variables to allow capturing
4356          * of values for next automated test request.
4357          */
4358         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4359
4360         /*
4361          * Now read the DPCD to see if it's actually running
4362          * If the current value of sink count doesn't match with
4363          * the value that was stored earlier or dpcd read failed
4364          * we need to do full detection
4365          */
4366         ret = intel_dp_get_dpcd(intel_dp);
4367
4368         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4369                 /* No need to proceed if we are going to do full detect */
4370                 return false;
4371         }
4372
4373         /* Try to read the source of the interrupt */
4374         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4375             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4376             sink_irq_vector != 0) {
4377                 /* Clear interrupt source */
4378                 drm_dp_dpcd_writeb(&intel_dp->aux,
4379                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4380                                    sink_irq_vector);
4381
4382                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4383                         intel_dp_handle_test_request(intel_dp);
4384                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4385                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4386         }
4387
4388         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4389         intel_dp_check_link_status(intel_dp);
4390         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4391         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4392                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4393                 /* Send a Hotplug Uevent to userspace to start modeset */
4394                 drm_kms_helper_hotplug_event(intel_encoder->base.dev);
4395         }
4396
4397         return true;
4398 }
4399
4400 /* XXX this is probably wrong for multiple downstream ports */
4401 static enum drm_connector_status
4402 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4403 {
4404         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4405         uint8_t *dpcd = intel_dp->dpcd;
4406         uint8_t type;
4407
4408         if (lspcon->active)
4409                 lspcon_resume(lspcon);
4410
4411         if (!intel_dp_get_dpcd(intel_dp))
4412                 return connector_status_disconnected;
4413
4414         if (intel_dp_is_edp(intel_dp))
4415                 return connector_status_connected;
4416
4417         /* if there's no downstream port, we're done */
4418         if (!drm_dp_is_branch(dpcd))
4419                 return connector_status_connected;
4420
4421         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4422         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4423             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4424
4425                 return intel_dp->sink_count ?
4426                 connector_status_connected : connector_status_disconnected;
4427         }
4428
4429         if (intel_dp_can_mst(intel_dp))
4430                 return connector_status_connected;
4431
4432         /* If no HPD, poke DDC gently */
4433         if (drm_probe_ddc(&intel_dp->aux.ddc))
4434                 return connector_status_connected;
4435
4436         /* Well we tried, say unknown for unreliable port types */
4437         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4438                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4439                 if (type == DP_DS_PORT_TYPE_VGA ||
4440                     type == DP_DS_PORT_TYPE_NON_EDID)
4441                         return connector_status_unknown;
4442         } else {
4443                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4444                         DP_DWN_STRM_PORT_TYPE_MASK;
4445                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4446                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4447                         return connector_status_unknown;
4448         }
4449
4450         /* Anything else is out of spec, warn and ignore */
4451         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4452         return connector_status_disconnected;
4453 }
4454
4455 static enum drm_connector_status
4456 edp_detect(struct intel_dp *intel_dp)
4457 {
4458         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4459         struct drm_i915_private *dev_priv = to_i915(dev);
4460         enum drm_connector_status status;
4461
4462         status = intel_panel_detect(dev_priv);
4463         if (status == connector_status_unknown)
4464                 status = connector_status_connected;
4465
4466         return status;
4467 }
4468
4469 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4470                                        struct intel_digital_port *port)
4471 {
4472         u32 bit;
4473
4474         switch (port->port) {
4475         case PORT_B:
4476                 bit = SDE_PORTB_HOTPLUG;
4477                 break;
4478         case PORT_C:
4479                 bit = SDE_PORTC_HOTPLUG;
4480                 break;
4481         case PORT_D:
4482                 bit = SDE_PORTD_HOTPLUG;
4483                 break;
4484         default:
4485                 MISSING_CASE(port->port);
4486                 return false;
4487         }
4488
4489         return I915_READ(SDEISR) & bit;
4490 }
4491
4492 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4493                                        struct intel_digital_port *port)
4494 {
4495         u32 bit;
4496
4497         switch (port->port) {
4498         case PORT_B:
4499                 bit = SDE_PORTB_HOTPLUG_CPT;
4500                 break;
4501         case PORT_C:
4502                 bit = SDE_PORTC_HOTPLUG_CPT;
4503                 break;
4504         case PORT_D:
4505                 bit = SDE_PORTD_HOTPLUG_CPT;
4506                 break;
4507         default:
4508                 MISSING_CASE(port->port);
4509                 return false;
4510         }
4511
4512         return I915_READ(SDEISR) & bit;
4513 }
4514
4515 static bool spt_digital_port_connected(struct drm_i915_private *dev_priv,
4516                                        struct intel_digital_port *port)
4517 {
4518         u32 bit;
4519
4520         switch (port->port) {
4521         case PORT_A:
4522                 bit = SDE_PORTA_HOTPLUG_SPT;
4523                 break;
4524         case PORT_E:
4525                 bit = SDE_PORTE_HOTPLUG_SPT;
4526                 break;
4527         default:
4528                 return cpt_digital_port_connected(dev_priv, port);
4529         }
4530
4531         return I915_READ(SDEISR) & bit;
4532 }
4533
4534 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4535                                        struct intel_digital_port *port)
4536 {
4537         u32 bit;
4538
4539         switch (port->port) {
4540         case PORT_B:
4541                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4542                 break;
4543         case PORT_C:
4544                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4545                 break;
4546         case PORT_D:
4547                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4548                 break;
4549         default:
4550                 MISSING_CASE(port->port);
4551                 return false;
4552         }
4553
4554         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4555 }
4556
4557 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4558                                         struct intel_digital_port *port)
4559 {
4560         u32 bit;
4561
4562         switch (port->port) {
4563         case PORT_B:
4564                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4565                 break;
4566         case PORT_C:
4567                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4568                 break;
4569         case PORT_D:
4570                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4571                 break;
4572         default:
4573                 MISSING_CASE(port->port);
4574                 return false;
4575         }
4576
4577         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4578 }
4579
4580 static bool ilk_digital_port_connected(struct drm_i915_private *dev_priv,
4581                                        struct intel_digital_port *port)
4582 {
4583         if (port->port == PORT_A)
4584                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4585         else
4586                 return ibx_digital_port_connected(dev_priv, port);
4587 }
4588
4589 static bool snb_digital_port_connected(struct drm_i915_private *dev_priv,
4590                                        struct intel_digital_port *port)
4591 {
4592         if (port->port == PORT_A)
4593                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4594         else
4595                 return cpt_digital_port_connected(dev_priv, port);
4596 }
4597
4598 static bool ivb_digital_port_connected(struct drm_i915_private *dev_priv,
4599                                        struct intel_digital_port *port)
4600 {
4601         if (port->port == PORT_A)
4602                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4603         else
4604                 return cpt_digital_port_connected(dev_priv, port);
4605 }
4606
4607 static bool bdw_digital_port_connected(struct drm_i915_private *dev_priv,
4608                                        struct intel_digital_port *port)
4609 {
4610         if (port->port == PORT_A)
4611                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4612         else
4613                 return cpt_digital_port_connected(dev_priv, port);
4614 }
4615
4616 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4617                                        struct intel_digital_port *intel_dig_port)
4618 {
4619         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4620         enum port port;
4621         u32 bit;
4622
4623         port = intel_hpd_pin_to_port(intel_encoder->hpd_pin);
4624         switch (port) {
4625         case PORT_A:
4626                 bit = BXT_DE_PORT_HP_DDIA;
4627                 break;
4628         case PORT_B:
4629                 bit = BXT_DE_PORT_HP_DDIB;
4630                 break;
4631         case PORT_C:
4632                 bit = BXT_DE_PORT_HP_DDIC;
4633                 break;
4634         default:
4635                 MISSING_CASE(port);
4636                 return false;
4637         }
4638
4639         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4640 }
4641
4642 /*
4643  * intel_digital_port_connected - is the specified port connected?
4644  * @dev_priv: i915 private structure
4645  * @port: the port to test
4646  *
4647  * Return %true if @port is connected, %false otherwise.
4648  */
4649 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4650                                   struct intel_digital_port *port)
4651 {
4652         if (HAS_GMCH_DISPLAY(dev_priv)) {
4653                 if (IS_GM45(dev_priv))
4654                         return gm45_digital_port_connected(dev_priv, port);
4655                 else
4656                         return g4x_digital_port_connected(dev_priv, port);
4657         }
4658
4659         if (IS_GEN5(dev_priv))
4660                 return ilk_digital_port_connected(dev_priv, port);
4661         else if (IS_GEN6(dev_priv))
4662                 return snb_digital_port_connected(dev_priv, port);
4663         else if (IS_GEN7(dev_priv))
4664                 return ivb_digital_port_connected(dev_priv, port);
4665         else if (IS_GEN8(dev_priv))
4666                 return bdw_digital_port_connected(dev_priv, port);
4667         else if (IS_GEN9_LP(dev_priv))
4668                 return bxt_digital_port_connected(dev_priv, port);
4669         else
4670                 return spt_digital_port_connected(dev_priv, port);
4671 }
4672
4673 static struct edid *
4674 intel_dp_get_edid(struct intel_dp *intel_dp)
4675 {
4676         struct intel_connector *intel_connector = intel_dp->attached_connector;
4677
4678         /* use cached edid if we have one */
4679         if (intel_connector->edid) {
4680                 /* invalid edid */
4681                 if (IS_ERR(intel_connector->edid))
4682                         return NULL;
4683
4684                 return drm_edid_duplicate(intel_connector->edid);
4685         } else
4686                 return drm_get_edid(&intel_connector->base,
4687                                     &intel_dp->aux.ddc);
4688 }
4689
4690 static void
4691 intel_dp_set_edid(struct intel_dp *intel_dp)
4692 {
4693         struct intel_connector *intel_connector = intel_dp->attached_connector;
4694         struct edid *edid;
4695
4696         intel_dp_unset_edid(intel_dp);
4697         edid = intel_dp_get_edid(intel_dp);
4698         intel_connector->detect_edid = edid;
4699
4700         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4701 }
4702
4703 static void
4704 intel_dp_unset_edid(struct intel_dp *intel_dp)
4705 {
4706         struct intel_connector *intel_connector = intel_dp->attached_connector;
4707
4708         kfree(intel_connector->detect_edid);
4709         intel_connector->detect_edid = NULL;
4710
4711         intel_dp->has_audio = false;
4712 }
4713
4714 static int
4715 intel_dp_long_pulse(struct intel_connector *intel_connector)
4716 {
4717         struct drm_connector *connector = &intel_connector->base;
4718         struct intel_dp *intel_dp = intel_attached_dp(connector);
4719         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4720         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4721         struct drm_device *dev = connector->dev;
4722         enum drm_connector_status status;
4723         u8 sink_irq_vector = 0;
4724
4725         WARN_ON(!drm_modeset_is_locked(&connector->dev->mode_config.connection_mutex));
4726
4727         intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
4728
4729         /* Can't disconnect eDP, but you can close the lid... */
4730         if (intel_dp_is_edp(intel_dp))
4731                 status = edp_detect(intel_dp);
4732         else if (intel_digital_port_connected(to_i915(dev),
4733                                               dp_to_dig_port(intel_dp)))
4734                 status = intel_dp_detect_dpcd(intel_dp);
4735         else
4736                 status = connector_status_disconnected;
4737
4738         if (status == connector_status_disconnected) {
4739                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4740
4741                 if (intel_dp->is_mst) {
4742                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4743                                       intel_dp->is_mst,
4744                                       intel_dp->mst_mgr.mst_state);
4745                         intel_dp->is_mst = false;
4746                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4747                                                         intel_dp->is_mst);
4748                 }
4749
4750                 goto out;
4751         }
4752
4753         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4754                 intel_encoder->type = INTEL_OUTPUT_DP;
4755
4756         if (intel_dp->reset_link_params) {
4757                 /* Initial max link lane count */
4758                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4759
4760                 /* Initial max link rate */
4761                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4762
4763                 intel_dp->reset_link_params = false;
4764         }
4765
4766         intel_dp_print_rates(intel_dp);
4767
4768         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4769                          drm_dp_is_branch(intel_dp->dpcd));
4770
4771         intel_dp_configure_mst(intel_dp);
4772
4773         if (intel_dp->is_mst) {
4774                 /*
4775                  * If we are in MST mode then this connector
4776                  * won't appear connected or have anything
4777                  * with EDID on it
4778                  */
4779                 status = connector_status_disconnected;
4780                 goto out;
4781         } else {
4782                 /*
4783                  * If display is now connected check links status,
4784                  * there has been known issues of link loss triggerring
4785                  * long pulse.
4786                  *
4787                  * Some sinks (eg. ASUS PB287Q) seem to perform some
4788                  * weird HPD ping pong during modesets. So we can apparently
4789                  * end up with HPD going low during a modeset, and then
4790                  * going back up soon after. And once that happens we must
4791                  * retrain the link to get a picture. That's in case no
4792                  * userspace component reacted to intermittent HPD dip.
4793                  */
4794                 intel_dp_check_link_status(intel_dp);
4795         }
4796
4797         /*
4798          * Clearing NACK and defer counts to get their exact values
4799          * while reading EDID which are required by Compliance tests
4800          * 4.2.2.4 and 4.2.2.5
4801          */
4802         intel_dp->aux.i2c_nack_count = 0;
4803         intel_dp->aux.i2c_defer_count = 0;
4804
4805         intel_dp_set_edid(intel_dp);
4806         if (intel_dp_is_edp(intel_dp) || intel_connector->detect_edid)
4807                 status = connector_status_connected;
4808         intel_dp->detect_done = true;
4809
4810         /* Try to read the source of the interrupt */
4811         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4812             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4813             sink_irq_vector != 0) {
4814                 /* Clear interrupt source */
4815                 drm_dp_dpcd_writeb(&intel_dp->aux,
4816                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4817                                    sink_irq_vector);
4818
4819                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4820                         intel_dp_handle_test_request(intel_dp);
4821                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4822                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4823         }
4824
4825 out:
4826         if (status != connector_status_connected && !intel_dp->is_mst)
4827                 intel_dp_unset_edid(intel_dp);
4828
4829         intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain);
4830         return status;
4831 }
4832
4833 static int
4834 intel_dp_detect(struct drm_connector *connector,
4835                 struct drm_modeset_acquire_ctx *ctx,
4836                 bool force)
4837 {
4838         struct intel_dp *intel_dp = intel_attached_dp(connector);
4839         int status = connector->status;
4840
4841         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4842                       connector->base.id, connector->name);
4843
4844         /* If full detect is not performed yet, do a full detect */
4845         if (!intel_dp->detect_done)
4846                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4847
4848         intel_dp->detect_done = false;
4849
4850         return status;
4851 }
4852
4853 static void
4854 intel_dp_force(struct drm_connector *connector)
4855 {
4856         struct intel_dp *intel_dp = intel_attached_dp(connector);
4857         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4858         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4859
4860         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4861                       connector->base.id, connector->name);
4862         intel_dp_unset_edid(intel_dp);
4863
4864         if (connector->status != connector_status_connected)
4865                 return;
4866
4867         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4868
4869         intel_dp_set_edid(intel_dp);
4870
4871         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4872
4873         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4874                 intel_encoder->type = INTEL_OUTPUT_DP;
4875 }
4876
4877 static int intel_dp_get_modes(struct drm_connector *connector)
4878 {
4879         struct intel_connector *intel_connector = to_intel_connector(connector);
4880         struct edid *edid;
4881
4882         edid = intel_connector->detect_edid;
4883         if (edid) {
4884                 int ret = intel_connector_update_modes(connector, edid);
4885                 if (ret)
4886                         return ret;
4887         }
4888
4889         /* if eDP has no EDID, fall back to fixed mode */
4890         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4891             intel_connector->panel.fixed_mode) {
4892                 struct drm_display_mode *mode;
4893
4894                 mode = drm_mode_duplicate(connector->dev,
4895                                           intel_connector->panel.fixed_mode);
4896                 if (mode) {
4897                         drm_mode_probed_add(connector, mode);
4898                         return 1;
4899                 }
4900         }
4901
4902         return 0;
4903 }
4904
4905 static int
4906 intel_dp_connector_register(struct drm_connector *connector)
4907 {
4908         struct intel_dp *intel_dp = intel_attached_dp(connector);
4909         int ret;
4910
4911         ret = intel_connector_register(connector);
4912         if (ret)
4913                 return ret;
4914
4915         i915_debugfs_connector_add(connector);
4916
4917         DRM_DEBUG_KMS("registering %s bus for %s\n",
4918                       intel_dp->aux.name, connector->kdev->kobj.name);
4919
4920         intel_dp->aux.dev = connector->kdev;
4921         return drm_dp_aux_register(&intel_dp->aux);
4922 }
4923
4924 static void
4925 intel_dp_connector_unregister(struct drm_connector *connector)
4926 {
4927         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4928         intel_connector_unregister(connector);
4929 }
4930
4931 static void
4932 intel_dp_connector_destroy(struct drm_connector *connector)
4933 {
4934         struct intel_connector *intel_connector = to_intel_connector(connector);
4935
4936         kfree(intel_connector->detect_edid);
4937
4938         if (!IS_ERR_OR_NULL(intel_connector->edid))
4939                 kfree(intel_connector->edid);
4940
4941         /*
4942          * Can't call intel_dp_is_edp() since the encoder may have been
4943          * destroyed already.
4944          */
4945         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4946                 intel_panel_fini(&intel_connector->panel);
4947
4948         drm_connector_cleanup(connector);
4949         kfree(connector);
4950 }
4951
4952 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4953 {
4954         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4955         struct intel_dp *intel_dp = &intel_dig_port->dp;
4956
4957         intel_dp_mst_encoder_cleanup(intel_dig_port);
4958         if (intel_dp_is_edp(intel_dp)) {
4959                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4960                 /*
4961                  * vdd might still be enabled do to the delayed vdd off.
4962                  * Make sure vdd is actually turned off here.
4963                  */
4964                 pps_lock(intel_dp);
4965                 edp_panel_vdd_off_sync(intel_dp);
4966                 pps_unlock(intel_dp);
4967
4968                 if (intel_dp->edp_notifier.notifier_call) {
4969                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4970                         intel_dp->edp_notifier.notifier_call = NULL;
4971                 }
4972         }
4973
4974         intel_dp_aux_fini(intel_dp);
4975
4976         drm_encoder_cleanup(encoder);
4977         kfree(intel_dig_port);
4978 }
4979
4980 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4981 {
4982         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4983
4984         if (!intel_dp_is_edp(intel_dp))
4985                 return;
4986
4987         /*
4988          * vdd might still be enabled do to the delayed vdd off.
4989          * Make sure vdd is actually turned off here.
4990          */
4991         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4992         pps_lock(intel_dp);
4993         edp_panel_vdd_off_sync(intel_dp);
4994         pps_unlock(intel_dp);
4995 }
4996
4997 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4998 {
4999         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5000         struct drm_device *dev = intel_dig_port->base.base.dev;
5001         struct drm_i915_private *dev_priv = to_i915(dev);
5002
5003         lockdep_assert_held(&dev_priv->pps_mutex);
5004
5005         if (!edp_have_panel_vdd(intel_dp))
5006                 return;
5007
5008         /*
5009          * The VDD bit needs a power domain reference, so if the bit is
5010          * already enabled when we boot or resume, grab this reference and
5011          * schedule a vdd off, so we don't hold on to the reference
5012          * indefinitely.
5013          */
5014         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5015         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5016
5017         edp_panel_vdd_schedule_off(intel_dp);
5018 }
5019
5020 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5021 {
5022         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5023
5024         if ((intel_dp->DP & DP_PORT_EN) == 0)
5025                 return INVALID_PIPE;
5026
5027         if (IS_CHERRYVIEW(dev_priv))
5028                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5029         else
5030                 return PORT_TO_PIPE(intel_dp->DP);
5031 }
5032
5033 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5034 {
5035         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5036         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5037         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5038
5039         if (!HAS_DDI(dev_priv))
5040                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5041
5042         if (lspcon->active)
5043                 lspcon_resume(lspcon);
5044
5045         intel_dp->reset_link_params = true;
5046
5047         pps_lock(intel_dp);
5048
5049         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5050                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5051
5052         if (intel_dp_is_edp(intel_dp)) {
5053                 /* Reinit the power sequencer, in case BIOS did something with it. */
5054                 intel_dp_pps_init(encoder->dev, intel_dp);
5055                 intel_edp_panel_vdd_sanitize(intel_dp);
5056         }
5057
5058         pps_unlock(intel_dp);
5059 }
5060
5061 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5062         .force = intel_dp_force,
5063         .fill_modes = drm_helper_probe_single_connector_modes,
5064         .atomic_get_property = intel_digital_connector_atomic_get_property,
5065         .atomic_set_property = intel_digital_connector_atomic_set_property,
5066         .late_register = intel_dp_connector_register,
5067         .early_unregister = intel_dp_connector_unregister,
5068         .destroy = intel_dp_connector_destroy,
5069         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5070         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5071 };
5072
5073 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5074         .detect_ctx = intel_dp_detect,
5075         .get_modes = intel_dp_get_modes,
5076         .mode_valid = intel_dp_mode_valid,
5077         .atomic_check = intel_digital_connector_atomic_check,
5078 };
5079
5080 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5081         .reset = intel_dp_encoder_reset,
5082         .destroy = intel_dp_encoder_destroy,
5083 };
5084
5085 enum irqreturn
5086 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5087 {
5088         struct intel_dp *intel_dp = &intel_dig_port->dp;
5089         struct drm_device *dev = intel_dig_port->base.base.dev;
5090         struct drm_i915_private *dev_priv = to_i915(dev);
5091         enum irqreturn ret = IRQ_NONE;
5092
5093         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
5094             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
5095                 intel_dig_port->base.type = INTEL_OUTPUT_DP;
5096
5097         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5098                 /*
5099                  * vdd off can generate a long pulse on eDP which
5100                  * would require vdd on to handle it, and thus we
5101                  * would end up in an endless cycle of
5102                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5103                  */
5104                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5105                               port_name(intel_dig_port->port));
5106                 return IRQ_HANDLED;
5107         }
5108
5109         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5110                       port_name(intel_dig_port->port),
5111                       long_hpd ? "long" : "short");
5112
5113         if (long_hpd) {
5114                 intel_dp->reset_link_params = true;
5115                 intel_dp->detect_done = false;
5116                 return IRQ_NONE;
5117         }
5118
5119         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5120
5121         if (intel_dp->is_mst) {
5122                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5123                         /*
5124                          * If we were in MST mode, and device is not
5125                          * there, get out of MST mode
5126                          */
5127                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5128                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5129                         intel_dp->is_mst = false;
5130                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5131                                                         intel_dp->is_mst);
5132                         intel_dp->detect_done = false;
5133                         goto put_power;
5134                 }
5135         }
5136
5137         if (!intel_dp->is_mst) {
5138                 if (!intel_dp_short_pulse(intel_dp)) {
5139                         intel_dp->detect_done = false;
5140                         goto put_power;
5141                 }
5142         }
5143
5144         ret = IRQ_HANDLED;
5145
5146 put_power:
5147         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5148
5149         return ret;
5150 }
5151
5152 /* check the VBT to see whether the eDP is on another port */
5153 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5154 {
5155         /*
5156          * eDP not supported on g4x. so bail out early just
5157          * for a bit extra safety in case the VBT is bonkers.
5158          */
5159         if (INTEL_GEN(dev_priv) < 5)
5160                 return false;
5161
5162         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5163                 return true;
5164
5165         return intel_bios_is_port_edp(dev_priv, port);
5166 }
5167
5168 static void
5169 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5170 {
5171         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5172
5173         intel_attach_force_audio_property(connector);
5174         intel_attach_broadcast_rgb_property(connector);
5175
5176         if (intel_dp_is_edp(intel_dp)) {
5177                 u32 allowed_scalers;
5178
5179                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5180                 if (!HAS_GMCH_DISPLAY(dev_priv))
5181                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5182
5183                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5184
5185                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5186
5187         }
5188 }
5189
5190 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5191 {
5192         intel_dp->panel_power_off_time = ktime_get_boottime();
5193         intel_dp->last_power_on = jiffies;
5194         intel_dp->last_backlight_off = jiffies;
5195 }
5196
5197 static void
5198 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
5199                            struct intel_dp *intel_dp, struct edp_power_seq *seq)
5200 {
5201         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5202         struct pps_registers regs;
5203
5204         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5205
5206         /* Workaround: Need to write PP_CONTROL with the unlock key as
5207          * the very first thing. */
5208         pp_ctl = ironlake_get_pp_control(intel_dp);
5209
5210         pp_on = I915_READ(regs.pp_on);
5211         pp_off = I915_READ(regs.pp_off);
5212         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
5213                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5214                 pp_div = I915_READ(regs.pp_div);
5215         }
5216
5217         /* Pull timing values out of registers */
5218         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5219                      PANEL_POWER_UP_DELAY_SHIFT;
5220
5221         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5222                   PANEL_LIGHT_ON_DELAY_SHIFT;
5223
5224         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5225                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5226
5227         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5228                    PANEL_POWER_DOWN_DELAY_SHIFT;
5229
5230         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5231                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5232                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5233         } else {
5234                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5235                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5236         }
5237 }
5238
5239 static void
5240 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5241 {
5242         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5243                       state_name,
5244                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5245 }
5246
5247 static void
5248 intel_pps_verify_state(struct drm_i915_private *dev_priv,
5249                        struct intel_dp *intel_dp)
5250 {
5251         struct edp_power_seq hw;
5252         struct edp_power_seq *sw = &intel_dp->pps_delays;
5253
5254         intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
5255
5256         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5257             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5258                 DRM_ERROR("PPS state mismatch\n");
5259                 intel_pps_dump_state("sw", sw);
5260                 intel_pps_dump_state("hw", &hw);
5261         }
5262 }
5263
5264 static void
5265 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5266                                     struct intel_dp *intel_dp)
5267 {
5268         struct drm_i915_private *dev_priv = to_i915(dev);
5269         struct edp_power_seq cur, vbt, spec,
5270                 *final = &intel_dp->pps_delays;
5271
5272         lockdep_assert_held(&dev_priv->pps_mutex);
5273
5274         /* already initialized? */
5275         if (final->t11_t12 != 0)
5276                 return;
5277
5278         intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5279
5280         intel_pps_dump_state("cur", &cur);
5281
5282         vbt = dev_priv->vbt.edp.pps;
5283         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5284          * of 500ms appears to be too short. Ocassionally the panel
5285          * just fails to power back on. Increasing the delay to 800ms
5286          * seems sufficient to avoid this problem.
5287          */
5288         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5289                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 900 * 10);
5290                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5291                               vbt.t11_t12);
5292         }
5293         /* T11_T12 delay is special and actually in units of 100ms, but zero
5294          * based in the hw (so we need to add 100 ms). But the sw vbt
5295          * table multiplies it with 1000 to make it in units of 100usec,
5296          * too. */
5297         vbt.t11_t12 += 100 * 10;
5298
5299         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5300          * our hw here, which are all in 100usec. */
5301         spec.t1_t3 = 210 * 10;
5302         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5303         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5304         spec.t10 = 500 * 10;
5305         /* This one is special and actually in units of 100ms, but zero
5306          * based in the hw (so we need to add 100 ms). But the sw vbt
5307          * table multiplies it with 1000 to make it in units of 100usec,
5308          * too. */
5309         spec.t11_t12 = (510 + 100) * 10;
5310
5311         intel_pps_dump_state("vbt", &vbt);
5312
5313         /* Use the max of the register settings and vbt. If both are
5314          * unset, fall back to the spec limits. */
5315 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5316                                        spec.field : \
5317                                        max(cur.field, vbt.field))
5318         assign_final(t1_t3);
5319         assign_final(t8);
5320         assign_final(t9);
5321         assign_final(t10);
5322         assign_final(t11_t12);
5323 #undef assign_final
5324
5325 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5326         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5327         intel_dp->backlight_on_delay = get_delay(t8);
5328         intel_dp->backlight_off_delay = get_delay(t9);
5329         intel_dp->panel_power_down_delay = get_delay(t10);
5330         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5331 #undef get_delay
5332
5333         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5334                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5335                       intel_dp->panel_power_cycle_delay);
5336
5337         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5338                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5339
5340         /*
5341          * We override the HW backlight delays to 1 because we do manual waits
5342          * on them. For T8, even BSpec recommends doing it. For T9, if we
5343          * don't do this, we'll end up waiting for the backlight off delay
5344          * twice: once when we do the manual sleep, and once when we disable
5345          * the panel and wait for the PP_STATUS bit to become zero.
5346          */
5347         final->t8 = 1;
5348         final->t9 = 1;
5349 }
5350
5351 static void
5352 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5353                                               struct intel_dp *intel_dp,
5354                                               bool force_disable_vdd)
5355 {
5356         struct drm_i915_private *dev_priv = to_i915(dev);
5357         u32 pp_on, pp_off, pp_div, port_sel = 0;
5358         int div = dev_priv->rawclk_freq / 1000;
5359         struct pps_registers regs;
5360         enum port port = dp_to_dig_port(intel_dp)->port;
5361         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5362
5363         lockdep_assert_held(&dev_priv->pps_mutex);
5364
5365         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5366
5367         /*
5368          * On some VLV machines the BIOS can leave the VDD
5369          * enabled even on power seqeuencers which aren't
5370          * hooked up to any port. This would mess up the
5371          * power domain tracking the first time we pick
5372          * one of these power sequencers for use since
5373          * edp_panel_vdd_on() would notice that the VDD was
5374          * already on and therefore wouldn't grab the power
5375          * domain reference. Disable VDD first to avoid this.
5376          * This also avoids spuriously turning the VDD on as
5377          * soon as the new power seqeuencer gets initialized.
5378          */
5379         if (force_disable_vdd) {
5380                 u32 pp = ironlake_get_pp_control(intel_dp);
5381
5382                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5383
5384                 if (pp & EDP_FORCE_VDD)
5385                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5386
5387                 pp &= ~EDP_FORCE_VDD;
5388
5389                 I915_WRITE(regs.pp_ctrl, pp);
5390         }
5391
5392         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5393                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5394         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5395                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5396         /* Compute the divisor for the pp clock, simply match the Bspec
5397          * formula. */
5398         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5399                 pp_div = I915_READ(regs.pp_ctrl);
5400                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5401                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5402                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5403         } else {
5404                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5405                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5406                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5407         }
5408
5409         /* Haswell doesn't have any port selection bits for the panel
5410          * power sequencer any more. */
5411         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5412                 port_sel = PANEL_PORT_SELECT_VLV(port);
5413         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5414                 if (port == PORT_A)
5415                         port_sel = PANEL_PORT_SELECT_DPA;
5416                 else
5417                         port_sel = PANEL_PORT_SELECT_DPD;
5418         }
5419
5420         pp_on |= port_sel;
5421
5422         I915_WRITE(regs.pp_on, pp_on);
5423         I915_WRITE(regs.pp_off, pp_off);
5424         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
5425                 I915_WRITE(regs.pp_ctrl, pp_div);
5426         else
5427                 I915_WRITE(regs.pp_div, pp_div);
5428
5429         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5430                       I915_READ(regs.pp_on),
5431                       I915_READ(regs.pp_off),
5432                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
5433                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5434                       I915_READ(regs.pp_div));
5435 }
5436
5437 static void intel_dp_pps_init(struct drm_device *dev,
5438                               struct intel_dp *intel_dp)
5439 {
5440         struct drm_i915_private *dev_priv = to_i915(dev);
5441
5442         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5443                 vlv_initial_power_sequencer_setup(intel_dp);
5444         } else {
5445                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5446                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5447         }
5448 }
5449
5450 /**
5451  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5452  * @dev_priv: i915 device
5453  * @crtc_state: a pointer to the active intel_crtc_state
5454  * @refresh_rate: RR to be programmed
5455  *
5456  * This function gets called when refresh rate (RR) has to be changed from
5457  * one frequency to another. Switches can be between high and low RR
5458  * supported by the panel or to any other RR based on media playback (in
5459  * this case, RR value needs to be passed from user space).
5460  *
5461  * The caller of this function needs to take a lock on dev_priv->drrs.
5462  */
5463 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5464                                     const struct intel_crtc_state *crtc_state,
5465                                     int refresh_rate)
5466 {
5467         struct intel_encoder *encoder;
5468         struct intel_digital_port *dig_port = NULL;
5469         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5470         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5471         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5472
5473         if (refresh_rate <= 0) {
5474                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5475                 return;
5476         }
5477
5478         if (intel_dp == NULL) {
5479                 DRM_DEBUG_KMS("DRRS not supported.\n");
5480                 return;
5481         }
5482
5483         dig_port = dp_to_dig_port(intel_dp);
5484         encoder = &dig_port->base;
5485         intel_crtc = to_intel_crtc(encoder->base.crtc);
5486
5487         if (!intel_crtc) {
5488                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5489                 return;
5490         }
5491
5492         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5493                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5494                 return;
5495         }
5496
5497         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5498                         refresh_rate)
5499                 index = DRRS_LOW_RR;
5500
5501         if (index == dev_priv->drrs.refresh_rate_type) {
5502                 DRM_DEBUG_KMS(
5503                         "DRRS requested for previously set RR...ignoring\n");
5504                 return;
5505         }
5506
5507         if (!crtc_state->base.active) {
5508                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5509                 return;
5510         }
5511
5512         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5513                 switch (index) {
5514                 case DRRS_HIGH_RR:
5515                         intel_dp_set_m_n(intel_crtc, M1_N1);
5516                         break;
5517                 case DRRS_LOW_RR:
5518                         intel_dp_set_m_n(intel_crtc, M2_N2);
5519                         break;
5520                 case DRRS_MAX_RR:
5521                 default:
5522                         DRM_ERROR("Unsupported refreshrate type\n");
5523                 }
5524         } else if (INTEL_GEN(dev_priv) > 6) {
5525                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5526                 u32 val;
5527
5528                 val = I915_READ(reg);
5529                 if (index > DRRS_HIGH_RR) {
5530                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5531                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5532                         else
5533                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5534                 } else {
5535                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5536                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5537                         else
5538                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5539                 }
5540                 I915_WRITE(reg, val);
5541         }
5542
5543         dev_priv->drrs.refresh_rate_type = index;
5544
5545         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5546 }
5547
5548 /**
5549  * intel_edp_drrs_enable - init drrs struct if supported
5550  * @intel_dp: DP struct
5551  * @crtc_state: A pointer to the active crtc state.
5552  *
5553  * Initializes frontbuffer_bits and drrs.dp
5554  */
5555 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5556                            const struct intel_crtc_state *crtc_state)
5557 {
5558         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5559         struct drm_i915_private *dev_priv = to_i915(dev);
5560
5561         if (!crtc_state->has_drrs) {
5562                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5563                 return;
5564         }
5565
5566         if (dev_priv->psr.enabled) {
5567                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5568                 return;
5569         }
5570
5571         mutex_lock(&dev_priv->drrs.mutex);
5572         if (WARN_ON(dev_priv->drrs.dp)) {
5573                 DRM_ERROR("DRRS already enabled\n");
5574                 goto unlock;
5575         }
5576
5577         dev_priv->drrs.busy_frontbuffer_bits = 0;
5578
5579         dev_priv->drrs.dp = intel_dp;
5580
5581 unlock:
5582         mutex_unlock(&dev_priv->drrs.mutex);
5583 }
5584
5585 /**
5586  * intel_edp_drrs_disable - Disable DRRS
5587  * @intel_dp: DP struct
5588  * @old_crtc_state: Pointer to old crtc_state.
5589  *
5590  */
5591 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5592                             const struct intel_crtc_state *old_crtc_state)
5593 {
5594         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5595         struct drm_i915_private *dev_priv = to_i915(dev);
5596
5597         if (!old_crtc_state->has_drrs)
5598                 return;
5599
5600         mutex_lock(&dev_priv->drrs.mutex);
5601         if (!dev_priv->drrs.dp) {
5602                 mutex_unlock(&dev_priv->drrs.mutex);
5603                 return;
5604         }
5605
5606         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5607                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5608                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5609
5610         dev_priv->drrs.dp = NULL;
5611         mutex_unlock(&dev_priv->drrs.mutex);
5612
5613         cancel_delayed_work_sync(&dev_priv->drrs.work);
5614 }
5615
5616 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5617 {
5618         struct drm_i915_private *dev_priv =
5619                 container_of(work, typeof(*dev_priv), drrs.work.work);
5620         struct intel_dp *intel_dp;
5621
5622         mutex_lock(&dev_priv->drrs.mutex);
5623
5624         intel_dp = dev_priv->drrs.dp;
5625
5626         if (!intel_dp)
5627                 goto unlock;
5628
5629         /*
5630          * The delayed work can race with an invalidate hence we need to
5631          * recheck.
5632          */
5633
5634         if (dev_priv->drrs.busy_frontbuffer_bits)
5635                 goto unlock;
5636
5637         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5638                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5639
5640                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5641                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5642         }
5643
5644 unlock:
5645         mutex_unlock(&dev_priv->drrs.mutex);
5646 }
5647
5648 /**
5649  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5650  * @dev_priv: i915 device
5651  * @frontbuffer_bits: frontbuffer plane tracking bits
5652  *
5653  * This function gets called everytime rendering on the given planes start.
5654  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5655  *
5656  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5657  */
5658 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5659                                unsigned int frontbuffer_bits)
5660 {
5661         struct drm_crtc *crtc;
5662         enum pipe pipe;
5663
5664         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5665                 return;
5666
5667         cancel_delayed_work(&dev_priv->drrs.work);
5668
5669         mutex_lock(&dev_priv->drrs.mutex);
5670         if (!dev_priv->drrs.dp) {
5671                 mutex_unlock(&dev_priv->drrs.mutex);
5672                 return;
5673         }
5674
5675         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5676         pipe = to_intel_crtc(crtc)->pipe;
5677
5678         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5679         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5680
5681         /* invalidate means busy screen hence upclock */
5682         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5683                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5684                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5685
5686         mutex_unlock(&dev_priv->drrs.mutex);
5687 }
5688
5689 /**
5690  * intel_edp_drrs_flush - Restart Idleness DRRS
5691  * @dev_priv: i915 device
5692  * @frontbuffer_bits: frontbuffer plane tracking bits
5693  *
5694  * This function gets called every time rendering on the given planes has
5695  * completed or flip on a crtc is completed. So DRRS should be upclocked
5696  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5697  * if no other planes are dirty.
5698  *
5699  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5700  */
5701 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5702                           unsigned int frontbuffer_bits)
5703 {
5704         struct drm_crtc *crtc;
5705         enum pipe pipe;
5706
5707         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5708                 return;
5709
5710         cancel_delayed_work(&dev_priv->drrs.work);
5711
5712         mutex_lock(&dev_priv->drrs.mutex);
5713         if (!dev_priv->drrs.dp) {
5714                 mutex_unlock(&dev_priv->drrs.mutex);
5715                 return;
5716         }
5717
5718         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5719         pipe = to_intel_crtc(crtc)->pipe;
5720
5721         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5722         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5723
5724         /* flush means busy screen hence upclock */
5725         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5726                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5727                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5728
5729         /*
5730          * flush also means no more activity hence schedule downclock, if all
5731          * other fbs are quiescent too
5732          */
5733         if (!dev_priv->drrs.busy_frontbuffer_bits)
5734                 schedule_delayed_work(&dev_priv->drrs.work,
5735                                 msecs_to_jiffies(1000));
5736         mutex_unlock(&dev_priv->drrs.mutex);
5737 }
5738
5739 /**
5740  * DOC: Display Refresh Rate Switching (DRRS)
5741  *
5742  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5743  * which enables swtching between low and high refresh rates,
5744  * dynamically, based on the usage scenario. This feature is applicable
5745  * for internal panels.
5746  *
5747  * Indication that the panel supports DRRS is given by the panel EDID, which
5748  * would list multiple refresh rates for one resolution.
5749  *
5750  * DRRS is of 2 types - static and seamless.
5751  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5752  * (may appear as a blink on screen) and is used in dock-undock scenario.
5753  * Seamless DRRS involves changing RR without any visual effect to the user
5754  * and can be used during normal system usage. This is done by programming
5755  * certain registers.
5756  *
5757  * Support for static/seamless DRRS may be indicated in the VBT based on
5758  * inputs from the panel spec.
5759  *
5760  * DRRS saves power by switching to low RR based on usage scenarios.
5761  *
5762  * The implementation is based on frontbuffer tracking implementation.  When
5763  * there is a disturbance on the screen triggered by user activity or a periodic
5764  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5765  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5766  * made.
5767  *
5768  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5769  * and intel_edp_drrs_flush() are called.
5770  *
5771  * DRRS can be further extended to support other internal panels and also
5772  * the scenario of video playback wherein RR is set based on the rate
5773  * requested by userspace.
5774  */
5775
5776 /**
5777  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5778  * @intel_connector: eDP connector
5779  * @fixed_mode: preferred mode of panel
5780  *
5781  * This function is  called only once at driver load to initialize basic
5782  * DRRS stuff.
5783  *
5784  * Returns:
5785  * Downclock mode if panel supports it, else return NULL.
5786  * DRRS support is determined by the presence of downclock mode (apart
5787  * from VBT setting).
5788  */
5789 static struct drm_display_mode *
5790 intel_dp_drrs_init(struct intel_connector *intel_connector,
5791                 struct drm_display_mode *fixed_mode)
5792 {
5793         struct drm_connector *connector = &intel_connector->base;
5794         struct drm_device *dev = connector->dev;
5795         struct drm_i915_private *dev_priv = to_i915(dev);
5796         struct drm_display_mode *downclock_mode = NULL;
5797
5798         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5799         mutex_init(&dev_priv->drrs.mutex);
5800
5801         if (INTEL_GEN(dev_priv) <= 6) {
5802                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5803                 return NULL;
5804         }
5805
5806         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5807                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5808                 return NULL;
5809         }
5810
5811         downclock_mode = intel_find_panel_downclock
5812                                         (dev_priv, fixed_mode, connector);
5813
5814         if (!downclock_mode) {
5815                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5816                 return NULL;
5817         }
5818
5819         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5820
5821         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5822         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5823         return downclock_mode;
5824 }
5825
5826 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5827                                      struct intel_connector *intel_connector)
5828 {
5829         struct drm_connector *connector = &intel_connector->base;
5830         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5831         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5832         struct drm_device *dev = intel_encoder->base.dev;
5833         struct drm_i915_private *dev_priv = to_i915(dev);
5834         struct drm_display_mode *fixed_mode = NULL;
5835         struct drm_display_mode *alt_fixed_mode = NULL;
5836         struct drm_display_mode *downclock_mode = NULL;
5837         bool has_dpcd;
5838         struct drm_display_mode *scan;
5839         struct edid *edid;
5840         enum pipe pipe = INVALID_PIPE;
5841
5842         if (!intel_dp_is_edp(intel_dp))
5843                 return true;
5844
5845         /*
5846          * On IBX/CPT we may get here with LVDS already registered. Since the
5847          * driver uses the only internal power sequencer available for both
5848          * eDP and LVDS bail out early in this case to prevent interfering
5849          * with an already powered-on LVDS power sequencer.
5850          */
5851         if (intel_get_lvds_encoder(dev)) {
5852                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5853                 DRM_INFO("LVDS was detected, not registering eDP\n");
5854
5855                 return false;
5856         }
5857
5858         pps_lock(intel_dp);
5859
5860         intel_dp_init_panel_power_timestamps(intel_dp);
5861         intel_dp_pps_init(dev, intel_dp);
5862         intel_edp_panel_vdd_sanitize(intel_dp);
5863
5864         pps_unlock(intel_dp);
5865
5866         /* Cache DPCD and EDID for edp. */
5867         has_dpcd = intel_edp_init_dpcd(intel_dp);
5868
5869         if (!has_dpcd) {
5870                 /* if this fails, presume the device is a ghost */
5871                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5872                 goto out_vdd_off;
5873         }
5874
5875         mutex_lock(&dev->mode_config.mutex);
5876         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5877         if (edid) {
5878                 if (drm_add_edid_modes(connector, edid)) {
5879                         drm_mode_connector_update_edid_property(connector,
5880                                                                 edid);
5881                         drm_edid_to_eld(connector, edid);
5882                 } else {
5883                         kfree(edid);
5884                         edid = ERR_PTR(-EINVAL);
5885                 }
5886         } else {
5887                 edid = ERR_PTR(-ENOENT);
5888         }
5889         intel_connector->edid = edid;
5890
5891         /* prefer fixed mode from EDID if available, save an alt mode also */
5892         list_for_each_entry(scan, &connector->probed_modes, head) {
5893                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5894                         fixed_mode = drm_mode_duplicate(dev, scan);
5895                         downclock_mode = intel_dp_drrs_init(
5896                                                 intel_connector, fixed_mode);
5897                 } else if (!alt_fixed_mode) {
5898                         alt_fixed_mode = drm_mode_duplicate(dev, scan);
5899                 }
5900         }
5901
5902         /* fallback to VBT if available for eDP */
5903         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5904                 fixed_mode = drm_mode_duplicate(dev,
5905                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5906                 if (fixed_mode) {
5907                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5908                         connector->display_info.width_mm = fixed_mode->width_mm;
5909                         connector->display_info.height_mm = fixed_mode->height_mm;
5910                 }
5911         }
5912         mutex_unlock(&dev->mode_config.mutex);
5913
5914         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5915                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5916                 register_reboot_notifier(&intel_dp->edp_notifier);
5917
5918                 /*
5919                  * Figure out the current pipe for the initial backlight setup.
5920                  * If the current pipe isn't valid, try the PPS pipe, and if that
5921                  * fails just assume pipe A.
5922                  */
5923                 pipe = vlv_active_pipe(intel_dp);
5924
5925                 if (pipe != PIPE_A && pipe != PIPE_B)
5926                         pipe = intel_dp->pps_pipe;
5927
5928                 if (pipe != PIPE_A && pipe != PIPE_B)
5929                         pipe = PIPE_A;
5930
5931                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5932                               pipe_name(pipe));
5933         }
5934
5935         intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode,
5936                          downclock_mode);
5937         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5938         intel_panel_setup_backlight(connector, pipe);
5939
5940         return true;
5941
5942 out_vdd_off:
5943         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5944         /*
5945          * vdd might still be enabled do to the delayed vdd off.
5946          * Make sure vdd is actually turned off here.
5947          */
5948         pps_lock(intel_dp);
5949         edp_panel_vdd_off_sync(intel_dp);
5950         pps_unlock(intel_dp);
5951
5952         return false;
5953 }
5954
5955 /* Set up the hotplug pin and aux power domain. */
5956 static void
5957 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5958 {
5959         struct intel_encoder *encoder = &intel_dig_port->base;
5960         struct intel_dp *intel_dp = &intel_dig_port->dp;
5961
5962         encoder->hpd_pin = intel_hpd_pin(intel_dig_port->port);
5963
5964         switch (intel_dig_port->port) {
5965         case PORT_A:
5966                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
5967                 break;
5968         case PORT_B:
5969                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
5970                 break;
5971         case PORT_C:
5972                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
5973                 break;
5974         case PORT_D:
5975                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5976                 break;
5977         case PORT_E:
5978                 /* FIXME: Check VBT for actual wiring of PORT E */
5979                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5980                 break;
5981         default:
5982                 MISSING_CASE(intel_dig_port->port);
5983         }
5984 }
5985
5986 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5987 {
5988         struct intel_connector *intel_connector;
5989         struct drm_connector *connector;
5990
5991         intel_connector = container_of(work, typeof(*intel_connector),
5992                                        modeset_retry_work);
5993         connector = &intel_connector->base;
5994         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5995                       connector->name);
5996
5997         /* Grab the locks before changing connector property*/
5998         mutex_lock(&connector->dev->mode_config.mutex);
5999         /* Set connector link status to BAD and send a Uevent to notify
6000          * userspace to do a modeset.
6001          */
6002         drm_mode_connector_set_link_status_property(connector,
6003                                                     DRM_MODE_LINK_STATUS_BAD);
6004         mutex_unlock(&connector->dev->mode_config.mutex);
6005         /* Send Hotplug uevent so userspace can reprobe */
6006         drm_kms_helper_hotplug_event(connector->dev);
6007 }
6008
6009 bool
6010 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6011                         struct intel_connector *intel_connector)
6012 {
6013         struct drm_connector *connector = &intel_connector->base;
6014         struct intel_dp *intel_dp = &intel_dig_port->dp;
6015         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6016         struct drm_device *dev = intel_encoder->base.dev;
6017         struct drm_i915_private *dev_priv = to_i915(dev);
6018         enum port port = intel_dig_port->port;
6019         int type;
6020
6021         /* Initialize the work for modeset in case of link train failure */
6022         INIT_WORK(&intel_connector->modeset_retry_work,
6023                   intel_dp_modeset_retry_work_fn);
6024
6025         if (WARN(intel_dig_port->max_lanes < 1,
6026                  "Not enough lanes (%d) for DP on port %c\n",
6027                  intel_dig_port->max_lanes, port_name(port)))
6028                 return false;
6029
6030         intel_dp_set_source_rates(intel_dp);
6031
6032         intel_dp->reset_link_params = true;
6033         intel_dp->pps_pipe = INVALID_PIPE;
6034         intel_dp->active_pipe = INVALID_PIPE;
6035
6036         /* intel_dp vfuncs */
6037         if (INTEL_GEN(dev_priv) >= 9)
6038                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
6039         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6040                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
6041         else if (HAS_PCH_SPLIT(dev_priv))
6042                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
6043         else
6044                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
6045
6046         if (INTEL_GEN(dev_priv) >= 9)
6047                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
6048         else
6049                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
6050
6051         if (HAS_DDI(dev_priv))
6052                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6053
6054         /* Preserve the current hw state. */
6055         intel_dp->DP = I915_READ(intel_dp->output_reg);
6056         intel_dp->attached_connector = intel_connector;
6057
6058         if (intel_dp_is_port_edp(dev_priv, port))
6059                 type = DRM_MODE_CONNECTOR_eDP;
6060         else
6061                 type = DRM_MODE_CONNECTOR_DisplayPort;
6062
6063         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6064                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6065
6066         /*
6067          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6068          * for DP the encoder type can be set by the caller to
6069          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6070          */
6071         if (type == DRM_MODE_CONNECTOR_eDP)
6072                 intel_encoder->type = INTEL_OUTPUT_EDP;
6073
6074         /* eDP only on port B and/or C on vlv/chv */
6075         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6076                     intel_dp_is_edp(intel_dp) &&
6077                     port != PORT_B && port != PORT_C))
6078                 return false;
6079
6080         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6081                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6082                         port_name(port));
6083
6084         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6085         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6086
6087         connector->interlace_allowed = true;
6088         connector->doublescan_allowed = 0;
6089
6090         intel_dp_init_connector_port_info(intel_dig_port);
6091
6092         intel_dp_aux_init(intel_dp);
6093
6094         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6095                           edp_panel_vdd_work);
6096
6097         intel_connector_attach_encoder(intel_connector, intel_encoder);
6098
6099         if (HAS_DDI(dev_priv))
6100                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6101         else
6102                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6103
6104         /* init MST on ports that can support it */
6105         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6106             (port == PORT_B || port == PORT_C || port == PORT_D))
6107                 intel_dp_mst_encoder_init(intel_dig_port,
6108                                           intel_connector->base.base.id);
6109
6110         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6111                 intel_dp_aux_fini(intel_dp);
6112                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6113                 goto fail;
6114         }
6115
6116         intel_dp_add_properties(intel_dp, connector);
6117
6118         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6119          * 0xd.  Failure to do so will result in spurious interrupts being
6120          * generated on the port when a cable is not attached.
6121          */
6122         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6123                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6124                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6125         }
6126
6127         return true;
6128
6129 fail:
6130         drm_connector_cleanup(connector);
6131
6132         return false;
6133 }
6134
6135 bool intel_dp_init(struct drm_i915_private *dev_priv,
6136                    i915_reg_t output_reg,
6137                    enum port port)
6138 {
6139         struct intel_digital_port *intel_dig_port;
6140         struct intel_encoder *intel_encoder;
6141         struct drm_encoder *encoder;
6142         struct intel_connector *intel_connector;
6143
6144         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6145         if (!intel_dig_port)
6146                 return false;
6147
6148         intel_connector = intel_connector_alloc();
6149         if (!intel_connector)
6150                 goto err_connector_alloc;
6151
6152         intel_encoder = &intel_dig_port->base;
6153         encoder = &intel_encoder->base;
6154
6155         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6156                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6157                              "DP %c", port_name(port)))
6158                 goto err_encoder_init;
6159
6160         intel_encoder->compute_config = intel_dp_compute_config;
6161         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6162         intel_encoder->get_config = intel_dp_get_config;
6163         intel_encoder->suspend = intel_dp_encoder_suspend;
6164         if (IS_CHERRYVIEW(dev_priv)) {
6165                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6166                 intel_encoder->pre_enable = chv_pre_enable_dp;
6167                 intel_encoder->enable = vlv_enable_dp;
6168                 intel_encoder->disable = vlv_disable_dp;
6169                 intel_encoder->post_disable = chv_post_disable_dp;
6170                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6171         } else if (IS_VALLEYVIEW(dev_priv)) {
6172                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6173                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6174                 intel_encoder->enable = vlv_enable_dp;
6175                 intel_encoder->disable = vlv_disable_dp;
6176                 intel_encoder->post_disable = vlv_post_disable_dp;
6177         } else if (INTEL_GEN(dev_priv) >= 5) {
6178                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6179                 intel_encoder->enable = g4x_enable_dp;
6180                 intel_encoder->disable = ilk_disable_dp;
6181                 intel_encoder->post_disable = ilk_post_disable_dp;
6182         } else {
6183                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6184                 intel_encoder->enable = g4x_enable_dp;
6185                 intel_encoder->disable = g4x_disable_dp;
6186         }
6187
6188         intel_dig_port->port = port;
6189         intel_dig_port->dp.output_reg = output_reg;
6190         intel_dig_port->max_lanes = 4;
6191
6192         intel_encoder->type = INTEL_OUTPUT_DP;
6193         intel_encoder->power_domain = intel_port_to_power_domain(port);
6194         if (IS_CHERRYVIEW(dev_priv)) {
6195                 if (port == PORT_D)
6196                         intel_encoder->crtc_mask = 1 << 2;
6197                 else
6198                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6199         } else {
6200                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6201         }
6202         intel_encoder->cloneable = 0;
6203         intel_encoder->port = port;
6204
6205         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6206         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6207
6208         if (port != PORT_A)
6209                 intel_infoframe_init(intel_dig_port);
6210
6211         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6212                 goto err_init_connector;
6213
6214         return true;
6215
6216 err_init_connector:
6217         drm_encoder_cleanup(encoder);
6218 err_encoder_init:
6219         kfree(intel_connector);
6220 err_connector_alloc:
6221         kfree(intel_dig_port);
6222         return false;
6223 }
6224
6225 void intel_dp_mst_suspend(struct drm_device *dev)
6226 {
6227         struct drm_i915_private *dev_priv = to_i915(dev);
6228         int i;
6229
6230         /* disable MST */
6231         for (i = 0; i < I915_MAX_PORTS; i++) {
6232                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6233
6234                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6235                         continue;
6236
6237                 if (intel_dig_port->dp.is_mst)
6238                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6239         }
6240 }
6241
6242 void intel_dp_mst_resume(struct drm_device *dev)
6243 {
6244         struct drm_i915_private *dev_priv = to_i915(dev);
6245         int i;
6246
6247         for (i = 0; i < I915_MAX_PORTS; i++) {
6248                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6249                 int ret;
6250
6251                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6252                         continue;
6253
6254                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6255                 if (ret)
6256                         intel_dp_check_mst_status(&intel_dig_port->dp);
6257         }
6258 }