drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include "intel_drv.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  45
  46 /* Compliance test status bits  */
  47 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  48 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  50 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51
  52 struct dp_link_dpll {
  53         int clock;
  54         struct dpll dpll;
  55 };
  56
  57 static const struct dp_link_dpll gen4_dpll[] = {
  58         { 162000,
  59                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  60         { 270000,
  61                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  62 };
  63
  64 static const struct dp_link_dpll pch_dpll[] = {
  65         { 162000,
  66                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  67         { 270000,
  68                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  69 };
  70
  71 static const struct dp_link_dpll vlv_dpll[] = {
  72         { 162000,
  73                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  74         { 270000,
  75                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  76 };
  77
  78 /*
  79  * CHV supports eDP 1.4 that have  more link rates.
  80  * Below only provides the fixed rate but exclude variable rate.
  81  */
  82 static const struct dp_link_dpll chv_dpll[] = {
  83         /*
  84          * CHV requires to program fractional division for m2.
  85          * m2 is stored in fixed point format using formula below
  86          * (m2_int << 22) | m2_fraction
  87          */
  88         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  89                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  90         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  92         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  93                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  94 };
  95
  96 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int skl_rates[] = { 162000, 216000, 270000,
  99                                   324000, 432000, 540000 };
 100 static const int default_rates[] = { 162000, 270000, 540000 };
 101
 102 /**
 103  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 104  * @intel_dp: DP struct
 105  *
 106  * If a CPU or PCH DP output is attached to an eDP panel, this function
 107  * will return true, and false otherwise.
 108  */
 109 static bool is_edp(struct intel_dp *intel_dp)
 110 {
 111         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 112
 113         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 114 }
 115
 116 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 117 {
 118         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 119
 120         return intel_dig_port->base.base.dev;
 121 }
 122
 123 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 124 {
 125         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 126 }
 127
 128 static void intel_dp_link_down(struct intel_dp *intel_dp);
 129 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 130 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 131 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 132 static void vlv_steal_power_sequencer(struct drm_device *dev,
 133                                       enum pipe pipe);
 134 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 135
 136 static int intel_dp_num_rates(u8 link_bw_code)
 137 {
 138         switch (link_bw_code) {
 139         default:
 140                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 141                      link_bw_code);
 142         case DP_LINK_BW_1_62:
 143                 return 1;
 144         case DP_LINK_BW_2_7:
 145                 return 2;
 146         case DP_LINK_BW_5_4:
 147                 return 3;
 148         }
 149 }
 150
 151 /* update sink rates from dpcd */
 152 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 153 {
 154         int i, num_rates;
 155
 156         num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 157
 158         for (i = 0; i < num_rates; i++)
 159                 intel_dp->sink_rates[i] = default_rates[i];
 160
 161         intel_dp->num_sink_rates = num_rates;
 162 }
 163
 164 /* Theoretical max between source and sink */
 165 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 166 {
 167         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 168 }
 169
 170 /* Theoretical max between source and sink */
 171 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 172 {
 173         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 174         int source_max = intel_dig_port->max_lanes;
 175         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 176
 177         return min(source_max, sink_max);
 178 }
 179
 180 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 181 {
 182         return intel_dp->max_link_lane_count;
 183 }
 184
 185 int
 186 intel_dp_link_required(int pixel_clock, int bpp)
 187 {
 188         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 189         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 190 }
 191
 192 int
 193 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 194 {
 195         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 196          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 197          * is transmitted every LS_Clk per lane, there is no need to account for
 198          * the channel encoding that is done in the PHY layer here.
 199          */
 200
 201         return max_link_clock * max_lanes;
 202 }
 203
 204 static int
 205 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 206 {
 207         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 208         struct intel_encoder *encoder = &intel_dig_port->base;
 209         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 210         int max_dotclk = dev_priv->max_dotclk_freq;
 211         int ds_max_dotclk;
 212
 213         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 214
 215         if (type != DP_DS_PORT_TYPE_VGA)
 216                 return max_dotclk;
 217
 218         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 219                                                     intel_dp->downstream_ports);
 220
 221         if (ds_max_dotclk != 0)
 222                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 223
 224         return max_dotclk;
 225 }
 226
 227 static void
 228 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 229 {
 230         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 231         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 232         const int *source_rates;
 233         int size;
 234
 235         /* This should only be done once */
 236         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 237
 238         if (IS_GEN9_LP(dev_priv)) {
 239                 source_rates = bxt_rates;
 240                 size = ARRAY_SIZE(bxt_rates);
 241         } else if (IS_GEN9_BC(dev_priv)) {
 242                 source_rates = skl_rates;
 243                 size = ARRAY_SIZE(skl_rates);
 244         } else {
 245                 source_rates = default_rates;
 246                 size = ARRAY_SIZE(default_rates);
 247         }
 248
 249         /* This depends on the fact that 5.4 is last value in the array */
 250         if (!intel_dp_source_supports_hbr2(intel_dp))
 251                 size--;
 252
 253         intel_dp->source_rates = source_rates;
 254         intel_dp->num_source_rates = size;
 255 }
 256
 257 static int intersect_rates(const int *source_rates, int source_len,
 258                            const int *sink_rates, int sink_len,
 259                            int *common_rates)
 260 {
 261         int i = 0, j = 0, k = 0;
 262
 263         while (i < source_len && j < sink_len) {
 264                 if (source_rates[i] == sink_rates[j]) {
 265                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 266                                 return k;
 267                         common_rates[k] = source_rates[i];
 268                         ++k;
 269                         ++i;
 270                         ++j;
 271                 } else if (source_rates[i] < sink_rates[j]) {
 272                         ++i;
 273                 } else {
 274                         ++j;
 275                 }
 276         }
 277         return k;
 278 }
 279
 280 /* return index of rate in rates array, or -1 if not found */
 281 static int intel_dp_rate_index(const int *rates, int len, int rate)
 282 {
 283         int i;
 284
 285         for (i = 0; i < len; i++)
 286                 if (rate == rates[i])
 287                         return i;
 288
 289         return -1;
 290 }
 291
 292 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 293 {
 294         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 295
 296         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 297                                                      intel_dp->num_source_rates,
 298                                                      intel_dp->sink_rates,
 299                                                      intel_dp->num_sink_rates,
 300                                                      intel_dp->common_rates);
 301
 302         /* Paranoia, there should always be something in common. */
 303         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 304                 intel_dp->common_rates[0] = default_rates[0];
 305                 intel_dp->num_common_rates = 1;
 306         }
 307 }
 308
 309 /* get length of common rates potentially limited by max_rate */
 310 static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
 311                                           int max_rate)
 312 {
 313         const int *common_rates = intel_dp->common_rates;
 314         int i, common_len = intel_dp->num_common_rates;
 315
 316         /* Limit results by potentially reduced max rate */
 317         for (i = 0; i < common_len; i++) {
 318                 if (common_rates[common_len - i - 1] <= max_rate)
 319                         return common_len - i;
 320         }
 321
 322         return 0;
 323 }
 324
 325 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp)
 326 {
 327         /*
 328          * FIXME: we need to synchronize the current link parameters with
 329          * hardware readout. Currently fast link training doesn't work on
 330          * boot-up.
 331          */
 332         if (intel_dp->link_rate == 0 ||
 333             intel_dp->link_rate > intel_dp->max_link_rate)
 334                 return false;
 335
 336         if (intel_dp->lane_count == 0 ||
 337             intel_dp->lane_count > intel_dp_max_lane_count(intel_dp))
 338                 return false;
 339
 340         return true;
 341 }
 342
 343 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 344                                             int link_rate, uint8_t lane_count)
 345 {
 346         int index;
 347
 348         index = intel_dp_rate_index(intel_dp->common_rates,
 349                                     intel_dp->num_common_rates,
 350                                     link_rate);
 351         if (index > 0) {
 352                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 353                 intel_dp->max_link_lane_count = lane_count;
 354         } else if (lane_count > 1) {
 355                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 356                 intel_dp->max_link_lane_count = lane_count >> 1;
 357         } else {
 358                 DRM_ERROR("Link Training Unsuccessful\n");
 359                 return -1;
 360         }
 361
 362         return 0;
 363 }
 364
 365 static enum drm_mode_status
 366 intel_dp_mode_valid(struct drm_connector *connector,
 367                     struct drm_display_mode *mode)
 368 {
 369         struct intel_dp *intel_dp = intel_attached_dp(connector);
 370         struct intel_connector *intel_connector = to_intel_connector(connector);
 371         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 372         int target_clock = mode->clock;
 373         int max_rate, mode_rate, max_lanes, max_link_clock;
 374         int max_dotclk;
 375
 376         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 377
 378         if (is_edp(intel_dp) && fixed_mode) {
 379                 if (mode->hdisplay > fixed_mode->hdisplay)
 380                         return MODE_PANEL;
 381
 382                 if (mode->vdisplay > fixed_mode->vdisplay)
 383                         return MODE_PANEL;
 384
 385                 target_clock = fixed_mode->clock;
 386         }
 387
 388         max_link_clock = intel_dp_max_link_rate(intel_dp);
 389         max_lanes = intel_dp_max_lane_count(intel_dp);
 390
 391         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 392         mode_rate = intel_dp_link_required(target_clock, 18);
 393
 394         if (mode_rate > max_rate || target_clock > max_dotclk)
 395                 return MODE_CLOCK_HIGH;
 396
 397         if (mode->clock < 10000)
 398                 return MODE_CLOCK_LOW;
 399
 400         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 401                 return MODE_H_ILLEGAL;
 402
 403         return MODE_OK;
 404 }
 405
 406 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 407 {
 408         int     i;
 409         uint32_t v = 0;
 410
 411         if (src_bytes > 4)
 412                 src_bytes = 4;
 413         for (i = 0; i < src_bytes; i++)
 414                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 415         return v;
 416 }
 417
 418 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 419 {
 420         int i;
 421         if (dst_bytes > 4)
 422                 dst_bytes = 4;
 423         for (i = 0; i < dst_bytes; i++)
 424                 dst[i] = src >> ((3-i) * 8);
 425 }
 426
 427 static void
 428 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 429                                     struct intel_dp *intel_dp);
 430 static void
 431 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 432                                               struct intel_dp *intel_dp,
 433                                               bool force_disable_vdd);
 434 static void
 435 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
 436
 437 static void pps_lock(struct intel_dp *intel_dp)
 438 {
 439         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 440         struct intel_encoder *encoder = &intel_dig_port->base;
 441         struct drm_device *dev = encoder->base.dev;
 442         struct drm_i915_private *dev_priv = to_i915(dev);
 443
 444         /*
 445          * See vlv_power_sequencer_reset() why we need
 446          * a power domain reference here.
 447          */
 448         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 449
 450         mutex_lock(&dev_priv->pps_mutex);
 451 }
 452
 453 static void pps_unlock(struct intel_dp *intel_dp)
 454 {
 455         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 456         struct intel_encoder *encoder = &intel_dig_port->base;
 457         struct drm_device *dev = encoder->base.dev;
 458         struct drm_i915_private *dev_priv = to_i915(dev);
 459
 460         mutex_unlock(&dev_priv->pps_mutex);
 461
 462         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 463 }
 464
 465 static void
 466 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 467 {
 468         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 469         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 470         enum pipe pipe = intel_dp->pps_pipe;
 471         bool pll_enabled, release_cl_override = false;
 472         enum dpio_phy phy = DPIO_PHY(pipe);
 473         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 474         uint32_t DP;
 475
 476         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 477                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 478                  pipe_name(pipe), port_name(intel_dig_port->port)))
 479                 return;
 480
 481         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 482                       pipe_name(pipe), port_name(intel_dig_port->port));
 483
 484         /* Preserve the BIOS-computed detected bit. This is
 485          * supposed to be read-only.
 486          */
 487         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 488         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 489         DP |= DP_PORT_WIDTH(1);
 490         DP |= DP_LINK_TRAIN_PAT_1;
 491
 492         if (IS_CHERRYVIEW(dev_priv))
 493                 DP |= DP_PIPE_SELECT_CHV(pipe);
 494         else if (pipe == PIPE_B)
 495                 DP |= DP_PIPEB_SELECT;
 496
 497         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 498
 499         /*
 500          * The DPLL for the pipe must be enabled for this to work.
 501          * So enable temporarily it if it's not already enabled.
 502          */
 503         if (!pll_enabled) {
 504                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 505                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 506
 507                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 508                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 509                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 510                                   pipe_name(pipe));
 511                         return;
 512                 }
 513         }
 514
 515         /*
 516          * Similar magic as in intel_dp_enable_port().
 517          * We _must_ do this port enable + disable trick
 518          * to make this power seqeuencer lock onto the port.
 519          * Otherwise even VDD force bit won't work.
 520          */
 521         I915_WRITE(intel_dp->output_reg, DP);
 522         POSTING_READ(intel_dp->output_reg);
 523
 524         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 525         POSTING_READ(intel_dp->output_reg);
 526
 527         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 528         POSTING_READ(intel_dp->output_reg);
 529
 530         if (!pll_enabled) {
 531                 vlv_force_pll_off(dev_priv, pipe);
 532
 533                 if (release_cl_override)
 534                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 535         }
 536 }
 537
 538 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 539 {
 540         struct intel_encoder *encoder;
 541         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 542
 543         /*
 544          * We don't have power sequencer currently.
 545          * Pick one that's not used by other ports.
 546          */
 547         for_each_intel_encoder(&dev_priv->drm, encoder) {
 548                 struct intel_dp *intel_dp;
 549
 550                 if (encoder->type != INTEL_OUTPUT_DP &&
 551                     encoder->type != INTEL_OUTPUT_EDP)
 552                         continue;
 553
 554                 intel_dp = enc_to_intel_dp(&encoder->base);
 555
 556                 if (encoder->type == INTEL_OUTPUT_EDP) {
 557                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 558                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 559
 560                         if (intel_dp->pps_pipe != INVALID_PIPE)
 561                                 pipes &= ~(1 << intel_dp->pps_pipe);
 562                 } else {
 563                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 564
 565                         if (intel_dp->active_pipe != INVALID_PIPE)
 566                                 pipes &= ~(1 << intel_dp->active_pipe);
 567                 }
 568         }
 569
 570         if (pipes == 0)
 571                 return INVALID_PIPE;
 572
 573         return ffs(pipes) - 1;
 574 }
 575
 576 static enum pipe
 577 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 578 {
 579         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 580         struct drm_device *dev = intel_dig_port->base.base.dev;
 581         struct drm_i915_private *dev_priv = to_i915(dev);
 582         enum pipe pipe;
 583
 584         lockdep_assert_held(&dev_priv->pps_mutex);
 585
 586         /* We should never land here with regular DP ports */
 587         WARN_ON(!is_edp(intel_dp));
 588
 589         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 590                 intel_dp->active_pipe != intel_dp->pps_pipe);
 591
 592         if (intel_dp->pps_pipe != INVALID_PIPE)
 593                 return intel_dp->pps_pipe;
 594
 595         pipe = vlv_find_free_pps(dev_priv);
 596
 597         /*
 598          * Didn't find one. This should not happen since there
 599          * are two power sequencers and up to two eDP ports.
 600          */
 601         if (WARN_ON(pipe == INVALID_PIPE))
 602                 pipe = PIPE_A;
 603
 604         vlv_steal_power_sequencer(dev, pipe);
 605         intel_dp->pps_pipe = pipe;
 606
 607         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 608                       pipe_name(intel_dp->pps_pipe),
 609                       port_name(intel_dig_port->port));
 610
 611         /* init power sequencer on this pipe and port */
 612         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 613         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
 614
 615         /*
 616          * Even vdd force doesn't work until we've made
 617          * the power sequencer lock in on the port.
 618          */
 619         vlv_power_sequencer_kick(intel_dp);
 620
 621         return intel_dp->pps_pipe;
 622 }
 623
 624 static int
 625 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 626 {
 627         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 628         struct drm_device *dev = intel_dig_port->base.base.dev;
 629         struct drm_i915_private *dev_priv = to_i915(dev);
 630
 631         lockdep_assert_held(&dev_priv->pps_mutex);
 632
 633         /* We should never land here with regular DP ports */
 634         WARN_ON(!is_edp(intel_dp));
 635
 636         /*
 637          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 638          * mapping needs to be retrieved from VBT, for now just hard-code to
 639          * use instance #0 always.
 640          */
 641         if (!intel_dp->pps_reset)
 642                 return 0;
 643
 644         intel_dp->pps_reset = false;
 645
 646         /*
 647          * Only the HW needs to be reprogrammed, the SW state is fixed and
 648          * has been setup during connector init.
 649          */
 650         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 651
 652         return 0;
 653 }
 654
 655 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 656                                enum pipe pipe);
 657
 658 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 659                                enum pipe pipe)
 660 {
 661         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 662 }
 663
 664 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 665                                 enum pipe pipe)
 666 {
 667         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 668 }
 669
 670 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 671                          enum pipe pipe)
 672 {
 673         return true;
 674 }
 675
 676 static enum pipe
 677 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 678                      enum port port,
 679                      vlv_pipe_check pipe_check)
 680 {
 681         enum pipe pipe;
 682
 683         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 684                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 685                         PANEL_PORT_SELECT_MASK;
 686
 687                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 688                         continue;
 689
 690                 if (!pipe_check(dev_priv, pipe))
 691                         continue;
 692
 693                 return pipe;
 694         }
 695
 696         return INVALID_PIPE;
 697 }
 698
 699 static void
 700 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 701 {
 702         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 703         struct drm_device *dev = intel_dig_port->base.base.dev;
 704         struct drm_i915_private *dev_priv = to_i915(dev);
 705         enum port port = intel_dig_port->port;
 706
 707         lockdep_assert_held(&dev_priv->pps_mutex);
 708
 709         /* try to find a pipe with this port selected */
 710         /* first pick one where the panel is on */
 711         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 712                                                   vlv_pipe_has_pp_on);
 713         /* didn't find one? pick one where vdd is on */
 714         if (intel_dp->pps_pipe == INVALID_PIPE)
 715                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 716                                                           vlv_pipe_has_vdd_on);
 717         /* didn't find one? pick one with just the correct port */
 718         if (intel_dp->pps_pipe == INVALID_PIPE)
 719                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 720                                                           vlv_pipe_any);
 721
 722         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 723         if (intel_dp->pps_pipe == INVALID_PIPE) {
 724                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 725                               port_name(port));
 726                 return;
 727         }
 728
 729         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 730                       port_name(port), pipe_name(intel_dp->pps_pipe));
 731
 732         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 733         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 734 }
 735
 736 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 737 {
 738         struct drm_device *dev = &dev_priv->drm;
 739         struct intel_encoder *encoder;
 740
 741         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 742                     !IS_GEN9_LP(dev_priv)))
 743                 return;
 744
 745         /*
 746          * We can't grab pps_mutex here due to deadlock with power_domain
 747          * mutex when power_domain functions are called while holding pps_mutex.
 748          * That also means that in order to use pps_pipe the code needs to
 749          * hold both a power domain reference and pps_mutex, and the power domain
 750          * reference get/put must be done while _not_ holding pps_mutex.
 751          * pps_{lock,unlock}() do these steps in the correct order, so one
 752          * should use them always.
 753          */
 754
 755         for_each_intel_encoder(dev, encoder) {
 756                 struct intel_dp *intel_dp;
 757
 758                 if (encoder->type != INTEL_OUTPUT_DP &&
 759                     encoder->type != INTEL_OUTPUT_EDP)
 760                         continue;
 761
 762                 intel_dp = enc_to_intel_dp(&encoder->base);
 763
 764                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 765
 766                 if (encoder->type != INTEL_OUTPUT_EDP)
 767                         continue;
 768
 769                 if (IS_GEN9_LP(dev_priv))
 770                         intel_dp->pps_reset = true;
 771                 else
 772                         intel_dp->pps_pipe = INVALID_PIPE;
 773         }
 774 }
 775
 776 struct pps_registers {
 777         i915_reg_t pp_ctrl;
 778         i915_reg_t pp_stat;
 779         i915_reg_t pp_on;
 780         i915_reg_t pp_off;
 781         i915_reg_t pp_div;
 782 };
 783
 784 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 785                                     struct intel_dp *intel_dp,
 786                                     struct pps_registers *regs)
 787 {
 788         int pps_idx = 0;
 789
 790         memset(regs, 0, sizeof(*regs));
 791
 792         if (IS_GEN9_LP(dev_priv))
 793                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 794         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 795                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 796
 797         regs->pp_ctrl = PP_CONTROL(pps_idx);
 798         regs->pp_stat = PP_STATUS(pps_idx);
 799         regs->pp_on = PP_ON_DELAYS(pps_idx);
 800         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 801         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
 802                 regs->pp_div = PP_DIVISOR(pps_idx);
 803 }
 804
 805 static i915_reg_t
 806 _pp_ctrl_reg(struct intel_dp *intel_dp)
 807 {
 808         struct pps_registers regs;
 809
 810         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 811                                 &regs);
 812
 813         return regs.pp_ctrl;
 814 }
 815
 816 static i915_reg_t
 817 _pp_stat_reg(struct intel_dp *intel_dp)
 818 {
 819         struct pps_registers regs;
 820
 821         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 822                                 &regs);
 823
 824         return regs.pp_stat;
 825 }
 826
 827 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 828    This function only applicable when panel PM state is not to be tracked */
 829 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 830                               void *unused)
 831 {
 832         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 833                                                  edp_notifier);
 834         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 835         struct drm_i915_private *dev_priv = to_i915(dev);
 836
 837         if (!is_edp(intel_dp) || code != SYS_RESTART)
 838                 return 0;
 839
 840         pps_lock(intel_dp);
 841
 842         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 843                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 844                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 845                 u32 pp_div;
 846
 847                 pp_ctrl_reg = PP_CONTROL(pipe);
 848                 pp_div_reg  = PP_DIVISOR(pipe);
 849                 pp_div = I915_READ(pp_div_reg);
 850                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 851
 852                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 853                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 854                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 855                 msleep(intel_dp->panel_power_cycle_delay);
 856         }
 857
 858         pps_unlock(intel_dp);
 859
 860         return 0;
 861 }
 862
 863 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 864 {
 865         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 866         struct drm_i915_private *dev_priv = to_i915(dev);
 867
 868         lockdep_assert_held(&dev_priv->pps_mutex);
 869
 870         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 871             intel_dp->pps_pipe == INVALID_PIPE)
 872                 return false;
 873
 874         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 875 }
 876
 877 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 878 {
 879         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 880         struct drm_i915_private *dev_priv = to_i915(dev);
 881
 882         lockdep_assert_held(&dev_priv->pps_mutex);
 883
 884         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 885             intel_dp->pps_pipe == INVALID_PIPE)
 886                 return false;
 887
 888         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 889 }
 890
 891 static void
 892 intel_dp_check_edp(struct intel_dp *intel_dp)
 893 {
 894         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 895         struct drm_i915_private *dev_priv = to_i915(dev);
 896
 897         if (!is_edp(intel_dp))
 898                 return;
 899
 900         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 901                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 902                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 903                               I915_READ(_pp_stat_reg(intel_dp)),
 904                               I915_READ(_pp_ctrl_reg(intel_dp)));
 905         }
 906 }
 907
 908 static uint32_t
 909 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 910 {
 911         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 912         struct drm_device *dev = intel_dig_port->base.base.dev;
 913         struct drm_i915_private *dev_priv = to_i915(dev);
 914         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 915         uint32_t status;
 916         bool done;
 917
 918 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 919         if (has_aux_irq)
 920                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 921                                           msecs_to_jiffies_timeout(10));
 922         else
 923                 done = wait_for(C, 10) == 0;
 924         if (!done)
 925                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 926                           has_aux_irq);
 927 #undef C
 928
 929         return status;
 930 }
 931
 932 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 933 {
 934         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 935         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 936
 937         if (index)
 938                 return 0;
 939
 940         /*
 941          * The clock divider is based off the hrawclk, and would like to run at
 942          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 943          */
 944         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 945 }
 946
 947 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 948 {
 949         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 950         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 951
 952         if (index)
 953                 return 0;
 954
 955         /*
 956          * The clock divider is based off the cdclk or PCH rawclk, and would
 957          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 958          * divide by 2000 and use that
 959          */
 960         if (intel_dig_port->port == PORT_A)
 961                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 962         else
 963                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 964 }
 965
 966 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 967 {
 968         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 969         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 970
 971         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 972                 /* Workaround for non-ULT HSW */
 973                 switch (index) {
 974                 case 0: return 63;
 975                 case 1: return 72;
 976                 default: return 0;
 977                 }
 978         }
 979
 980         return ilk_get_aux_clock_divider(intel_dp, index);
 981 }
 982
 983 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 984 {
 985         /*
 986          * SKL doesn't need us to program the AUX clock divider (Hardware will
 987          * derive the clock from CDCLK automatically). We still implement the
 988          * get_aux_clock_divider vfunc to plug-in into the existing code.
 989          */
 990         return index ? 0 : 1;
 991 }
 992
 993 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 994                                      bool has_aux_irq,
 995                                      int send_bytes,
 996                                      uint32_t aux_clock_divider)
 997 {
 998         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 999         struct drm_i915_private *dev_priv =
1000                         to_i915(intel_dig_port->base.base.dev);
1001         uint32_t precharge, timeout;
1002
1003         if (IS_GEN6(dev_priv))
1004                 precharge = 3;
1005         else
1006                 precharge = 5;
1007
1008         if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
1009                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1010         else
1011                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1012
1013         return DP_AUX_CH_CTL_SEND_BUSY |
1014                DP_AUX_CH_CTL_DONE |
1015                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1016                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1017                timeout |
1018                DP_AUX_CH_CTL_RECEIVE_ERROR |
1019                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1020                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1021                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1022 }
1023
1024 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1025                                       bool has_aux_irq,
1026                                       int send_bytes,
1027                                       uint32_t unused)
1028 {
1029         return DP_AUX_CH_CTL_SEND_BUSY |
1030                DP_AUX_CH_CTL_DONE |
1031                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1032                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1033                DP_AUX_CH_CTL_TIME_OUT_1600us |
1034                DP_AUX_CH_CTL_RECEIVE_ERROR |
1035                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1036                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1037                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1038 }
1039
1040 static int
1041 intel_dp_aux_ch(struct intel_dp *intel_dp,
1042                 const uint8_t *send, int send_bytes,
1043                 uint8_t *recv, int recv_size)
1044 {
1045         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1046         struct drm_i915_private *dev_priv =
1047                         to_i915(intel_dig_port->base.base.dev);
1048         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1049         uint32_t aux_clock_divider;
1050         int i, ret, recv_bytes;
1051         uint32_t status;
1052         int try, clock = 0;
1053         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1054         bool vdd;
1055
1056         pps_lock(intel_dp);
1057
1058         /*
1059          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1060          * In such cases we want to leave VDD enabled and it's up to upper layers
1061          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1062          * ourselves.
1063          */
1064         vdd = edp_panel_vdd_on(intel_dp);
1065
1066         /* dp aux is extremely sensitive to irq latency, hence request the
1067          * lowest possible wakeup latency and so prevent the cpu from going into
1068          * deep sleep states.
1069          */
1070         pm_qos_update_request(&dev_priv->pm_qos, 0);
1071
1072         intel_dp_check_edp(intel_dp);
1073
1074         /* Try to wait for any previous AUX channel activity */
1075         for (try = 0; try < 3; try++) {
1076                 status = I915_READ_NOTRACE(ch_ctl);
1077                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1078                         break;
1079                 msleep(1);
1080         }
1081
1082         if (try == 3) {
1083                 static u32 last_status = -1;
1084                 const u32 status = I915_READ(ch_ctl);
1085
1086                 if (status != last_status) {
1087                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1088                              status);
1089                         last_status = status;
1090                 }
1091
1092                 ret = -EBUSY;
1093                 goto out;
1094         }
1095
1096         /* Only 5 data registers! */
1097         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1098                 ret = -E2BIG;
1099                 goto out;
1100         }
1101
1102         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1103                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1104                                                           has_aux_irq,
1105                                                           send_bytes,
1106                                                           aux_clock_divider);
1107
1108                 /* Must try at least 3 times according to DP spec */
1109                 for (try = 0; try < 5; try++) {
1110                         /* Load the send data into the aux channel data registers */
1111                         for (i = 0; i < send_bytes; i += 4)
1112                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1113                                            intel_dp_pack_aux(send + i,
1114                                                              send_bytes - i));
1115
1116                         /* Send the command and wait for it to complete */
1117                         I915_WRITE(ch_ctl, send_ctl);
1118
1119                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1120
1121                         /* Clear done status and any errors */
1122                         I915_WRITE(ch_ctl,
1123                                    status |
1124                                    DP_AUX_CH_CTL_DONE |
1125                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1126                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1127
1128                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1129                                 continue;
1130
1131                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1132                          *   400us delay required for errors and timeouts
1133                          *   Timeout errors from the HW already meet this
1134                          *   requirement so skip to next iteration
1135                          */
1136                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1137                                 usleep_range(400, 500);
1138                                 continue;
1139                         }
1140                         if (status & DP_AUX_CH_CTL_DONE)
1141                                 goto done;
1142                 }
1143         }
1144
1145         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1146                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1147                 ret = -EBUSY;
1148                 goto out;
1149         }
1150
1151 done:
1152         /* Check for timeout or receive error.
1153          * Timeouts occur when the sink is not connected
1154          */
1155         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1156                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1157                 ret = -EIO;
1158                 goto out;
1159         }
1160
1161         /* Timeouts occur when the device isn't connected, so they're
1162          * "normal" -- don't fill the kernel log with these */
1163         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1164                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1165                 ret = -ETIMEDOUT;
1166                 goto out;
1167         }
1168
1169         /* Unload any bytes sent back from the other side */
1170         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1171                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1172
1173         /*
1174          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1175          * We have no idea of what happened so we return -EBUSY so
1176          * drm layer takes care for the necessary retries.
1177          */
1178         if (recv_bytes == 0 || recv_bytes > 20) {
1179                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1180                               recv_bytes);
1181                 /*
1182                  * FIXME: This patch was created on top of a series that
1183                  * organize the retries at drm level. There EBUSY should
1184                  * also take care for 1ms wait before retrying.
1185                  * That aux retries re-org is still needed and after that is
1186                  * merged we remove this sleep from here.
1187                  */
1188                 usleep_range(1000, 1500);
1189                 ret = -EBUSY;
1190                 goto out;
1191         }
1192
1193         if (recv_bytes > recv_size)
1194                 recv_bytes = recv_size;
1195
1196         for (i = 0; i < recv_bytes; i += 4)
1197                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1198                                     recv + i, recv_bytes - i);
1199
1200         ret = recv_bytes;
1201 out:
1202         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1203
1204         if (vdd)
1205                 edp_panel_vdd_off(intel_dp, false);
1206
1207         pps_unlock(intel_dp);
1208
1209         return ret;
1210 }
1211
1212 #define BARE_ADDRESS_SIZE       3
1213 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1214 static ssize_t
1215 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1216 {
1217         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1218         uint8_t txbuf[20], rxbuf[20];
1219         size_t txsize, rxsize;
1220         int ret;
1221
1222         txbuf[0] = (msg->request << 4) |
1223                 ((msg->address >> 16) & 0xf);
1224         txbuf[1] = (msg->address >> 8) & 0xff;
1225         txbuf[2] = msg->address & 0xff;
1226         txbuf[3] = msg->size - 1;
1227
1228         switch (msg->request & ~DP_AUX_I2C_MOT) {
1229         case DP_AUX_NATIVE_WRITE:
1230         case DP_AUX_I2C_WRITE:
1231         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1232                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1233                 rxsize = 2; /* 0 or 1 data bytes */
1234
1235                 if (WARN_ON(txsize > 20))
1236                         return -E2BIG;
1237
1238                 WARN_ON(!msg->buffer != !msg->size);
1239
1240                 if (msg->buffer)
1241                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1242
1243                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1244                 if (ret > 0) {
1245                         msg->reply = rxbuf[0] >> 4;
1246
1247                         if (ret > 1) {
1248                                 /* Number of bytes written in a short write. */
1249                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1250                         } else {
1251                                 /* Return payload size. */
1252                                 ret = msg->size;
1253                         }
1254                 }
1255                 break;
1256
1257         case DP_AUX_NATIVE_READ:
1258         case DP_AUX_I2C_READ:
1259                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1260                 rxsize = msg->size + 1;
1261
1262                 if (WARN_ON(rxsize > 20))
1263                         return -E2BIG;
1264
1265                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1266                 if (ret > 0) {
1267                         msg->reply = rxbuf[0] >> 4;
1268                         /*
1269                          * Assume happy day, and copy the data. The caller is
1270                          * expected to check msg->reply before touching it.
1271                          *
1272                          * Return payload size.
1273                          */
1274                         ret--;
1275                         memcpy(msg->buffer, rxbuf + 1, ret);
1276                 }
1277                 break;
1278
1279         default:
1280                 ret = -EINVAL;
1281                 break;
1282         }
1283
1284         return ret;
1285 }
1286
1287 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1288                                 enum port port)
1289 {
1290         const struct ddi_vbt_port_info *info =
1291                 &dev_priv->vbt.ddi_port_info[port];
1292         enum port aux_port;
1293
1294         if (!info->alternate_aux_channel) {
1295                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1296                               port_name(port), port_name(port));
1297                 return port;
1298         }
1299
1300         switch (info->alternate_aux_channel) {
1301         case DP_AUX_A:
1302                 aux_port = PORT_A;
1303                 break;
1304         case DP_AUX_B:
1305                 aux_port = PORT_B;
1306                 break;
1307         case DP_AUX_C:
1308                 aux_port = PORT_C;
1309                 break;
1310         case DP_AUX_D:
1311                 aux_port = PORT_D;
1312                 break;
1313         default:
1314                 MISSING_CASE(info->alternate_aux_channel);
1315                 aux_port = PORT_A;
1316                 break;
1317         }
1318
1319         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1320                       port_name(aux_port), port_name(port));
1321
1322         return aux_port;
1323 }
1324
1325 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1326                                   enum port port)
1327 {
1328         switch (port) {
1329         case PORT_B:
1330         case PORT_C:
1331         case PORT_D:
1332                 return DP_AUX_CH_CTL(port);
1333         default:
1334                 MISSING_CASE(port);
1335                 return DP_AUX_CH_CTL(PORT_B);
1336         }
1337 }
1338
1339 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1340                                    enum port port, int index)
1341 {
1342         switch (port) {
1343         case PORT_B:
1344         case PORT_C:
1345         case PORT_D:
1346                 return DP_AUX_CH_DATA(port, index);
1347         default:
1348                 MISSING_CASE(port);
1349                 return DP_AUX_CH_DATA(PORT_B, index);
1350         }
1351 }
1352
1353 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1354                                   enum port port)
1355 {
1356         switch (port) {
1357         case PORT_A:
1358                 return DP_AUX_CH_CTL(port);
1359         case PORT_B:
1360         case PORT_C:
1361         case PORT_D:
1362                 return PCH_DP_AUX_CH_CTL(port);
1363         default:
1364                 MISSING_CASE(port);
1365                 return DP_AUX_CH_CTL(PORT_A);
1366         }
1367 }
1368
1369 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1370                                    enum port port, int index)
1371 {
1372         switch (port) {
1373         case PORT_A:
1374                 return DP_AUX_CH_DATA(port, index);
1375         case PORT_B:
1376         case PORT_C:
1377         case PORT_D:
1378                 return PCH_DP_AUX_CH_DATA(port, index);
1379         default:
1380                 MISSING_CASE(port);
1381                 return DP_AUX_CH_DATA(PORT_A, index);
1382         }
1383 }
1384
1385 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1386                                   enum port port)
1387 {
1388         switch (port) {
1389         case PORT_A:
1390         case PORT_B:
1391         case PORT_C:
1392         case PORT_D:
1393                 return DP_AUX_CH_CTL(port);
1394         default:
1395                 MISSING_CASE(port);
1396                 return DP_AUX_CH_CTL(PORT_A);
1397         }
1398 }
1399
1400 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1401                                    enum port port, int index)
1402 {
1403         switch (port) {
1404         case PORT_A:
1405         case PORT_B:
1406         case PORT_C:
1407         case PORT_D:
1408                 return DP_AUX_CH_DATA(port, index);
1409         default:
1410                 MISSING_CASE(port);
1411                 return DP_AUX_CH_DATA(PORT_A, index);
1412         }
1413 }
1414
1415 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1416                                     enum port port)
1417 {
1418         if (INTEL_INFO(dev_priv)->gen >= 9)
1419                 return skl_aux_ctl_reg(dev_priv, port);
1420         else if (HAS_PCH_SPLIT(dev_priv))
1421                 return ilk_aux_ctl_reg(dev_priv, port);
1422         else
1423                 return g4x_aux_ctl_reg(dev_priv, port);
1424 }
1425
1426 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1427                                      enum port port, int index)
1428 {
1429         if (INTEL_INFO(dev_priv)->gen >= 9)
1430                 return skl_aux_data_reg(dev_priv, port, index);
1431         else if (HAS_PCH_SPLIT(dev_priv))
1432                 return ilk_aux_data_reg(dev_priv, port, index);
1433         else
1434                 return g4x_aux_data_reg(dev_priv, port, index);
1435 }
1436
1437 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1438 {
1439         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1440         enum port port = intel_aux_port(dev_priv,
1441                                         dp_to_dig_port(intel_dp)->port);
1442         int i;
1443
1444         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1445         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1446                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1447 }
1448
1449 static void
1450 intel_dp_aux_fini(struct intel_dp *intel_dp)
1451 {
1452         kfree(intel_dp->aux.name);
1453 }
1454
1455 static void
1456 intel_dp_aux_init(struct intel_dp *intel_dp)
1457 {
1458         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1459         enum port port = intel_dig_port->port;
1460
1461         intel_aux_reg_init(intel_dp);
1462         drm_dp_aux_init(&intel_dp->aux);
1463
1464         /* Failure to allocate our preferred name is not critical */
1465         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1466         intel_dp->aux.transfer = intel_dp_aux_transfer;
1467 }
1468
1469 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1470 {
1471         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1472         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1473
1474         if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1475             IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1476                 return true;
1477         else
1478                 return false;
1479 }
1480
1481 static void
1482 intel_dp_set_clock(struct intel_encoder *encoder,
1483                    struct intel_crtc_state *pipe_config)
1484 {
1485         struct drm_device *dev = encoder->base.dev;
1486         struct drm_i915_private *dev_priv = to_i915(dev);
1487         const struct dp_link_dpll *divisor = NULL;
1488         int i, count = 0;
1489
1490         if (IS_G4X(dev_priv)) {
1491                 divisor = gen4_dpll;
1492                 count = ARRAY_SIZE(gen4_dpll);
1493         } else if (HAS_PCH_SPLIT(dev_priv)) {
1494                 divisor = pch_dpll;
1495                 count = ARRAY_SIZE(pch_dpll);
1496         } else if (IS_CHERRYVIEW(dev_priv)) {
1497                 divisor = chv_dpll;
1498                 count = ARRAY_SIZE(chv_dpll);
1499         } else if (IS_VALLEYVIEW(dev_priv)) {
1500                 divisor = vlv_dpll;
1501                 count = ARRAY_SIZE(vlv_dpll);
1502         }
1503
1504         if (divisor && count) {
1505                 for (i = 0; i < count; i++) {
1506                         if (pipe_config->port_clock == divisor[i].clock) {
1507                                 pipe_config->dpll = divisor[i].dpll;
1508                                 pipe_config->clock_set = true;
1509                                 break;
1510                         }
1511                 }
1512         }
1513 }
1514
1515 static void snprintf_int_array(char *str, size_t len,
1516                                const int *array, int nelem)
1517 {
1518         int i;
1519
1520         str[0] = '\0';
1521
1522         for (i = 0; i < nelem; i++) {
1523                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1524                 if (r >= len)
1525                         return;
1526                 str += r;
1527                 len -= r;
1528         }
1529 }
1530
1531 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1532 {
1533         char str[128]; /* FIXME: too big for stack? */
1534
1535         if ((drm_debug & DRM_UT_KMS) == 0)
1536                 return;
1537
1538         snprintf_int_array(str, sizeof(str),
1539                            intel_dp->source_rates, intel_dp->num_source_rates);
1540         DRM_DEBUG_KMS("source rates: %s\n", str);
1541
1542         snprintf_int_array(str, sizeof(str),
1543                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1544         DRM_DEBUG_KMS("sink rates: %s\n", str);
1545
1546         snprintf_int_array(str, sizeof(str),
1547                            intel_dp->common_rates, intel_dp->num_common_rates);
1548         DRM_DEBUG_KMS("common rates: %s\n", str);
1549 }
1550
1551 int
1552 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1553 {
1554         int len;
1555
1556         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1557         if (WARN_ON(len <= 0))
1558                 return 162000;
1559
1560         return intel_dp->common_rates[len - 1];
1561 }
1562
1563 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1564 {
1565         int i = intel_dp_rate_index(intel_dp->sink_rates,
1566                                     intel_dp->num_sink_rates, rate);
1567
1568         if (WARN_ON(i < 0))
1569                 i = 0;
1570
1571         return i;
1572 }
1573
1574 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1575                            uint8_t *link_bw, uint8_t *rate_select)
1576 {
1577         /* eDP 1.4 rate select method. */
1578         if (intel_dp->use_rate_select) {
1579                 *link_bw = 0;
1580                 *rate_select =
1581                         intel_dp_rate_select(intel_dp, port_clock);
1582         } else {
1583                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1584                 *rate_select = 0;
1585         }
1586 }
1587
1588 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1589                                 struct intel_crtc_state *pipe_config)
1590 {
1591         int bpp, bpc;
1592
1593         bpp = pipe_config->pipe_bpp;
1594         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1595
1596         if (bpc > 0)
1597                 bpp = min(bpp, 3*bpc);
1598
1599         /* For DP Compliance we override the computed bpp for the pipe */
1600         if (intel_dp->compliance.test_data.bpc != 0) {
1601                 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1602                 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1603                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1604                               pipe_config->pipe_bpp);
1605         }
1606         return bpp;
1607 }
1608
1609 bool
1610 intel_dp_compute_config(struct intel_encoder *encoder,
1611                         struct intel_crtc_state *pipe_config,
1612                         struct drm_connector_state *conn_state)
1613 {
1614         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1615         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1616         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1617         enum port port = dp_to_dig_port(intel_dp)->port;
1618         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1619         struct intel_connector *intel_connector = intel_dp->attached_connector;
1620         struct intel_digital_connector_state *intel_conn_state =
1621                 to_intel_digital_connector_state(conn_state);
1622         int lane_count, clock;
1623         int min_lane_count = 1;
1624         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1625         /* Conveniently, the link BW constants become indices with a shift...*/
1626         int min_clock = 0;
1627         int max_clock;
1628         int bpp, mode_rate;
1629         int link_avail, link_clock;
1630         int common_len;
1631         uint8_t link_bw, rate_select;
1632         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1633                                            DP_DPCD_QUIRK_LIMITED_M_N);
1634
1635         common_len = intel_dp_common_len_rate_limit(intel_dp,
1636                                                     intel_dp->max_link_rate);
1637
1638         /* No common link rates between source and sink */
1639         WARN_ON(common_len <= 0);
1640
1641         max_clock = common_len - 1;
1642
1643         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1644                 pipe_config->has_pch_encoder = true;
1645
1646         pipe_config->has_drrs = false;
1647         if (port == PORT_A)
1648                 pipe_config->has_audio = false;
1649         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1650                 pipe_config->has_audio = intel_dp->has_audio;
1651         else
1652                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1653
1654         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1655                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1656                                        adjusted_mode);
1657
1658                 if (INTEL_GEN(dev_priv) >= 9) {
1659                         int ret;
1660                         ret = skl_update_scaler_crtc(pipe_config);
1661                         if (ret)
1662                                 return ret;
1663                 }
1664
1665                 if (HAS_GMCH_DISPLAY(dev_priv))
1666                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1667                                                  conn_state->scaling_mode);
1668                 else
1669                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1670                                                 conn_state->scaling_mode);
1671         }
1672
1673         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1674                 return false;
1675
1676         /* Use values requested by Compliance Test Request */
1677         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1678                 int index;
1679
1680                 index = intel_dp_rate_index(intel_dp->common_rates,
1681                                             intel_dp->num_common_rates,
1682                                             intel_dp->compliance.test_link_rate);
1683                 if (index >= 0)
1684                         min_clock = max_clock = index;
1685                 min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1686         }
1687         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1688                       "max bw %d pixel clock %iKHz\n",
1689                       max_lane_count, intel_dp->common_rates[max_clock],
1690                       adjusted_mode->crtc_clock);
1691
1692         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1693          * bpc in between. */
1694         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1695         if (is_edp(intel_dp)) {
1696
1697                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1698                 if (intel_connector->base.display_info.bpc == 0 &&
1699                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1700                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1701                                       dev_priv->vbt.edp.bpp);
1702                         bpp = dev_priv->vbt.edp.bpp;
1703                 }
1704
1705                 /*
1706                  * Use the maximum clock and number of lanes the eDP panel
1707                  * advertizes being capable of. The panels are generally
1708                  * designed to support only a single clock and lane
1709                  * configuration, and typically these values correspond to the
1710                  * native resolution of the panel.
1711                  */
1712                 min_lane_count = max_lane_count;
1713                 min_clock = max_clock;
1714         }
1715
1716         for (; bpp >= 6*3; bpp -= 2*3) {
1717                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1718                                                    bpp);
1719
1720                 for (clock = min_clock; clock <= max_clock; clock++) {
1721                         for (lane_count = min_lane_count;
1722                                 lane_count <= max_lane_count;
1723                                 lane_count <<= 1) {
1724
1725                                 link_clock = intel_dp->common_rates[clock];
1726                                 link_avail = intel_dp_max_data_rate(link_clock,
1727                                                                     lane_count);
1728
1729                                 if (mode_rate <= link_avail) {
1730                                         goto found;
1731                                 }
1732                         }
1733                 }
1734         }
1735
1736         return false;
1737
1738 found:
1739         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1740                 /*
1741                  * See:
1742                  * CEA-861-E - 5.1 Default Encoding Parameters
1743                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1744                  */
1745                 pipe_config->limited_color_range =
1746                         bpp != 18 &&
1747                         drm_default_rgb_quant_range(adjusted_mode) ==
1748                         HDMI_QUANTIZATION_RANGE_LIMITED;
1749         } else {
1750                 pipe_config->limited_color_range =
1751                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1752         }
1753
1754         pipe_config->lane_count = lane_count;
1755
1756         pipe_config->pipe_bpp = bpp;
1757         pipe_config->port_clock = intel_dp->common_rates[clock];
1758
1759         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1760                               &link_bw, &rate_select);
1761
1762         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1763                       link_bw, rate_select, pipe_config->lane_count,
1764                       pipe_config->port_clock, bpp);
1765         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1766                       mode_rate, link_avail);
1767
1768         intel_link_compute_m_n(bpp, lane_count,
1769                                adjusted_mode->crtc_clock,
1770                                pipe_config->port_clock,
1771                                &pipe_config->dp_m_n,
1772                                reduce_m_n);
1773
1774         if (intel_connector->panel.downclock_mode != NULL &&
1775                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1776                         pipe_config->has_drrs = true;
1777                         intel_link_compute_m_n(bpp, lane_count,
1778                                 intel_connector->panel.downclock_mode->clock,
1779                                 pipe_config->port_clock,
1780                                 &pipe_config->dp_m2_n2,
1781                                 reduce_m_n);
1782         }
1783
1784         /*
1785          * DPLL0 VCO may need to be adjusted to get the correct
1786          * clock for eDP. This will affect cdclk as well.
1787          */
1788         if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1789                 int vco;
1790
1791                 switch (pipe_config->port_clock / 2) {
1792                 case 108000:
1793                 case 216000:
1794                         vco = 8640000;
1795                         break;
1796                 default:
1797                         vco = 8100000;
1798                         break;
1799                 }
1800
1801                 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1802         }
1803
1804         if (!HAS_DDI(dev_priv))
1805                 intel_dp_set_clock(encoder, pipe_config);
1806
1807         return true;
1808 }
1809
1810 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1811                               int link_rate, uint8_t lane_count,
1812                               bool link_mst)
1813 {
1814         intel_dp->link_rate = link_rate;
1815         intel_dp->lane_count = lane_count;
1816         intel_dp->link_mst = link_mst;
1817 }
1818
1819 static void intel_dp_prepare(struct intel_encoder *encoder,
1820                              struct intel_crtc_state *pipe_config)
1821 {
1822         struct drm_device *dev = encoder->base.dev;
1823         struct drm_i915_private *dev_priv = to_i915(dev);
1824         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1825         enum port port = dp_to_dig_port(intel_dp)->port;
1826         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1827         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1828
1829         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1830                                  pipe_config->lane_count,
1831                                  intel_crtc_has_type(pipe_config,
1832                                                      INTEL_OUTPUT_DP_MST));
1833
1834         /*
1835          * There are four kinds of DP registers:
1836          *
1837          *      IBX PCH
1838          *      SNB CPU
1839          *      IVB CPU
1840          *      CPT PCH
1841          *
1842          * IBX PCH and CPU are the same for almost everything,
1843          * except that the CPU DP PLL is configured in this
1844          * register
1845          *
1846          * CPT PCH is quite different, having many bits moved
1847          * to the TRANS_DP_CTL register instead. That
1848          * configuration happens (oddly) in ironlake_pch_enable
1849          */
1850
1851         /* Preserve the BIOS-computed detected bit. This is
1852          * supposed to be read-only.
1853          */
1854         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1855
1856         /* Handle DP bits in common between all three register formats */
1857         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1858         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1859
1860         /* Split out the IBX/CPU vs CPT settings */
1861
1862         if (IS_GEN7(dev_priv) && port == PORT_A) {
1863                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1864                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1865                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1866                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1867                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1868
1869                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1870                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1871
1872                 intel_dp->DP |= crtc->pipe << 29;
1873         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1874                 u32 trans_dp;
1875
1876                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1877
1878                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1879                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1880                         trans_dp |= TRANS_DP_ENH_FRAMING;
1881                 else
1882                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1883                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1884         } else {
1885                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1886                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1887
1888                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1889                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1890                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1891                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1892                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1893
1894                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1895                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1896
1897                 if (IS_CHERRYVIEW(dev_priv))
1898                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1899                 else if (crtc->pipe == PIPE_B)
1900                         intel_dp->DP |= DP_PIPEB_SELECT;
1901         }
1902 }
1903
1904 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1905 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1906
1907 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1908 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1909
1910 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1911 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1912
1913 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1914                                    struct intel_dp *intel_dp);
1915
1916 static void wait_panel_status(struct intel_dp *intel_dp,
1917                                        u32 mask,
1918                                        u32 value)
1919 {
1920         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1921         struct drm_i915_private *dev_priv = to_i915(dev);
1922         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1923
1924         lockdep_assert_held(&dev_priv->pps_mutex);
1925
1926         intel_pps_verify_state(dev_priv, intel_dp);
1927
1928         pp_stat_reg = _pp_stat_reg(intel_dp);
1929         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1930
1931         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1932                         mask, value,
1933                         I915_READ(pp_stat_reg),
1934                         I915_READ(pp_ctrl_reg));
1935
1936         if (intel_wait_for_register(dev_priv,
1937                                     pp_stat_reg, mask, value,
1938                                     5000))
1939                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1940                                 I915_READ(pp_stat_reg),
1941                                 I915_READ(pp_ctrl_reg));
1942
1943         DRM_DEBUG_KMS("Wait complete\n");
1944 }
1945
1946 static void wait_panel_on(struct intel_dp *intel_dp)
1947 {
1948         DRM_DEBUG_KMS("Wait for panel power on\n");
1949         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1950 }
1951
1952 static void wait_panel_off(struct intel_dp *intel_dp)
1953 {
1954         DRM_DEBUG_KMS("Wait for panel power off time\n");
1955         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1956 }
1957
1958 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1959 {
1960         ktime_t panel_power_on_time;
1961         s64 panel_power_off_duration;
1962
1963         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1964
1965         /* take the difference of currrent time and panel power off time
1966          * and then make panel wait for t11_t12 if needed. */
1967         panel_power_on_time = ktime_get_boottime();
1968         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1969
1970         /* When we disable the VDD override bit last we have to do the manual
1971          * wait. */
1972         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1973                 wait_remaining_ms_from_jiffies(jiffies,
1974                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1975
1976         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1977 }
1978
1979 static void wait_backlight_on(struct intel_dp *intel_dp)
1980 {
1981         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1982                                        intel_dp->backlight_on_delay);
1983 }
1984
1985 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1986 {
1987         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1988                                        intel_dp->backlight_off_delay);
1989 }
1990
1991 /* Read the current pp_control value, unlocking the register if it
1992  * is locked
1993  */
1994
1995 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1996 {
1997         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1998         struct drm_i915_private *dev_priv = to_i915(dev);
1999         u32 control;
2000
2001         lockdep_assert_held(&dev_priv->pps_mutex);
2002
2003         control = I915_READ(_pp_ctrl_reg(intel_dp));
2004         if (WARN_ON(!HAS_DDI(dev_priv) &&
2005                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2006                 control &= ~PANEL_UNLOCK_MASK;
2007                 control |= PANEL_UNLOCK_REGS;
2008         }
2009         return control;
2010 }
2011
2012 /*
2013  * Must be paired with edp_panel_vdd_off().
2014  * Must hold pps_mutex around the whole on/off sequence.
2015  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2016  */
2017 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2018 {
2019         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2020         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2021         struct drm_i915_private *dev_priv = to_i915(dev);
2022         u32 pp;
2023         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2024         bool need_to_disable = !intel_dp->want_panel_vdd;
2025
2026         lockdep_assert_held(&dev_priv->pps_mutex);
2027
2028         if (!is_edp(intel_dp))
2029                 return false;
2030
2031         cancel_delayed_work(&intel_dp->panel_vdd_work);
2032         intel_dp->want_panel_vdd = true;
2033
2034         if (edp_have_panel_vdd(intel_dp))
2035                 return need_to_disable;
2036
2037         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2038
2039         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2040                       port_name(intel_dig_port->port));
2041
2042         if (!edp_have_panel_power(intel_dp))
2043                 wait_panel_power_cycle(intel_dp);
2044
2045         pp = ironlake_get_pp_control(intel_dp);
2046         pp |= EDP_FORCE_VDD;
2047
2048         pp_stat_reg = _pp_stat_reg(intel_dp);
2049         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2050
2051         I915_WRITE(pp_ctrl_reg, pp);
2052         POSTING_READ(pp_ctrl_reg);
2053         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2054                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2055         /*
2056          * If the panel wasn't on, delay before accessing aux channel
2057          */
2058         if (!edp_have_panel_power(intel_dp)) {
2059                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2060                               port_name(intel_dig_port->port));
2061                 msleep(intel_dp->panel_power_up_delay);
2062         }
2063
2064         return need_to_disable;
2065 }
2066
2067 /*
2068  * Must be paired with intel_edp_panel_vdd_off() or
2069  * intel_edp_panel_off().
2070  * Nested calls to these functions are not allowed since
2071  * we drop the lock. Caller must use some higher level
2072  * locking to prevent nested calls from other threads.
2073  */
2074 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2075 {
2076         bool vdd;
2077
2078         if (!is_edp(intel_dp))
2079                 return;
2080
2081         pps_lock(intel_dp);
2082         vdd = edp_panel_vdd_on(intel_dp);
2083         pps_unlock(intel_dp);
2084
2085         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2086              port_name(dp_to_dig_port(intel_dp)->port));
2087 }
2088
2089 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2090 {
2091         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2092         struct drm_i915_private *dev_priv = to_i915(dev);
2093         struct intel_digital_port *intel_dig_port =
2094                 dp_to_dig_port(intel_dp);
2095         u32 pp;
2096         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2097
2098         lockdep_assert_held(&dev_priv->pps_mutex);
2099
2100         WARN_ON(intel_dp->want_panel_vdd);
2101
2102         if (!edp_have_panel_vdd(intel_dp))
2103                 return;
2104
2105         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2106                       port_name(intel_dig_port->port));
2107
2108         pp = ironlake_get_pp_control(intel_dp);
2109         pp &= ~EDP_FORCE_VDD;
2110
2111         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2112         pp_stat_reg = _pp_stat_reg(intel_dp);
2113
2114         I915_WRITE(pp_ctrl_reg, pp);
2115         POSTING_READ(pp_ctrl_reg);
2116
2117         /* Make sure sequencer is idle before allowing subsequent activity */
2118         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2119         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2120
2121         if ((pp & PANEL_POWER_ON) == 0)
2122                 intel_dp->panel_power_off_time = ktime_get_boottime();
2123
2124         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2125 }
2126
2127 static void edp_panel_vdd_work(struct work_struct *__work)
2128 {
2129         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2130                                                  struct intel_dp, panel_vdd_work);
2131
2132         pps_lock(intel_dp);
2133         if (!intel_dp->want_panel_vdd)
2134                 edp_panel_vdd_off_sync(intel_dp);
2135         pps_unlock(intel_dp);
2136 }
2137
2138 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2139 {
2140         unsigned long delay;
2141
2142         /*
2143          * Queue the timer to fire a long time from now (relative to the power
2144          * down delay) to keep the panel power up across a sequence of
2145          * operations.
2146          */
2147         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2148         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2149 }
2150
2151 /*
2152  * Must be paired with edp_panel_vdd_on().
2153  * Must hold pps_mutex around the whole on/off sequence.
2154  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2155  */
2156 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2157 {
2158         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2159
2160         lockdep_assert_held(&dev_priv->pps_mutex);
2161
2162         if (!is_edp(intel_dp))
2163                 return;
2164
2165         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2166              port_name(dp_to_dig_port(intel_dp)->port));
2167
2168         intel_dp->want_panel_vdd = false;
2169
2170         if (sync)
2171                 edp_panel_vdd_off_sync(intel_dp);
2172         else
2173                 edp_panel_vdd_schedule_off(intel_dp);
2174 }
2175
2176 static void edp_panel_on(struct intel_dp *intel_dp)
2177 {
2178         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2179         struct drm_i915_private *dev_priv = to_i915(dev);
2180         u32 pp;
2181         i915_reg_t pp_ctrl_reg;
2182
2183         lockdep_assert_held(&dev_priv->pps_mutex);
2184
2185         if (!is_edp(intel_dp))
2186                 return;
2187
2188         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2189                       port_name(dp_to_dig_port(intel_dp)->port));
2190
2191         if (WARN(edp_have_panel_power(intel_dp),
2192                  "eDP port %c panel power already on\n",
2193                  port_name(dp_to_dig_port(intel_dp)->port)))
2194                 return;
2195
2196         wait_panel_power_cycle(intel_dp);
2197
2198         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2199         pp = ironlake_get_pp_control(intel_dp);
2200         if (IS_GEN5(dev_priv)) {
2201                 /* ILK workaround: disable reset around power sequence */
2202                 pp &= ~PANEL_POWER_RESET;
2203                 I915_WRITE(pp_ctrl_reg, pp);
2204                 POSTING_READ(pp_ctrl_reg);
2205         }
2206
2207         pp |= PANEL_POWER_ON;
2208         if (!IS_GEN5(dev_priv))
2209                 pp |= PANEL_POWER_RESET;
2210
2211         I915_WRITE(pp_ctrl_reg, pp);
2212         POSTING_READ(pp_ctrl_reg);
2213
2214         wait_panel_on(intel_dp);
2215         intel_dp->last_power_on = jiffies;
2216
2217         if (IS_GEN5(dev_priv)) {
2218                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2219                 I915_WRITE(pp_ctrl_reg, pp);
2220                 POSTING_READ(pp_ctrl_reg);
2221         }
2222 }
2223
2224 void intel_edp_panel_on(struct intel_dp *intel_dp)
2225 {
2226         if (!is_edp(intel_dp))
2227                 return;
2228
2229         pps_lock(intel_dp);
2230         edp_panel_on(intel_dp);
2231         pps_unlock(intel_dp);
2232 }
2233
2234
2235 static void edp_panel_off(struct intel_dp *intel_dp)
2236 {
2237         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2238         struct drm_i915_private *dev_priv = to_i915(dev);
2239         u32 pp;
2240         i915_reg_t pp_ctrl_reg;
2241
2242         lockdep_assert_held(&dev_priv->pps_mutex);
2243
2244         if (!is_edp(intel_dp))
2245                 return;
2246
2247         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2248                       port_name(dp_to_dig_port(intel_dp)->port));
2249
2250         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2251              port_name(dp_to_dig_port(intel_dp)->port));
2252
2253         pp = ironlake_get_pp_control(intel_dp);
2254         /* We need to switch off panel power _and_ force vdd, for otherwise some
2255          * panels get very unhappy and cease to work. */
2256         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2257                 EDP_BLC_ENABLE);
2258
2259         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2260
2261         intel_dp->want_panel_vdd = false;
2262
2263         I915_WRITE(pp_ctrl_reg, pp);
2264         POSTING_READ(pp_ctrl_reg);
2265
2266         intel_dp->panel_power_off_time = ktime_get_boottime();
2267         wait_panel_off(intel_dp);
2268
2269         /* We got a reference when we enabled the VDD. */
2270         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2271 }
2272
2273 void intel_edp_panel_off(struct intel_dp *intel_dp)
2274 {
2275         if (!is_edp(intel_dp))
2276                 return;
2277
2278         pps_lock(intel_dp);
2279         edp_panel_off(intel_dp);
2280         pps_unlock(intel_dp);
2281 }
2282
2283 /* Enable backlight in the panel power control. */
2284 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2285 {
2286         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2287         struct drm_device *dev = intel_dig_port->base.base.dev;
2288         struct drm_i915_private *dev_priv = to_i915(dev);
2289         u32 pp;
2290         i915_reg_t pp_ctrl_reg;
2291
2292         /*
2293          * If we enable the backlight right away following a panel power
2294          * on, we may see slight flicker as the panel syncs with the eDP
2295          * link.  So delay a bit to make sure the image is solid before
2296          * allowing it to appear.
2297          */
2298         wait_backlight_on(intel_dp);
2299
2300         pps_lock(intel_dp);
2301
2302         pp = ironlake_get_pp_control(intel_dp);
2303         pp |= EDP_BLC_ENABLE;
2304
2305         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2306
2307         I915_WRITE(pp_ctrl_reg, pp);
2308         POSTING_READ(pp_ctrl_reg);
2309
2310         pps_unlock(intel_dp);
2311 }
2312
2313 /* Enable backlight PWM and backlight PP control. */
2314 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2315                             const struct drm_connector_state *conn_state)
2316 {
2317         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2318
2319         if (!is_edp(intel_dp))
2320                 return;
2321
2322         DRM_DEBUG_KMS("\n");
2323
2324         intel_panel_enable_backlight(crtc_state, conn_state);
2325         _intel_edp_backlight_on(intel_dp);
2326 }
2327
2328 /* Disable backlight in the panel power control. */
2329 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2330 {
2331         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2332         struct drm_i915_private *dev_priv = to_i915(dev);
2333         u32 pp;
2334         i915_reg_t pp_ctrl_reg;
2335
2336         if (!is_edp(intel_dp))
2337                 return;
2338
2339         pps_lock(intel_dp);
2340
2341         pp = ironlake_get_pp_control(intel_dp);
2342         pp &= ~EDP_BLC_ENABLE;
2343
2344         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2345
2346         I915_WRITE(pp_ctrl_reg, pp);
2347         POSTING_READ(pp_ctrl_reg);
2348
2349         pps_unlock(intel_dp);
2350
2351         intel_dp->last_backlight_off = jiffies;
2352         edp_wait_backlight_off(intel_dp);
2353 }
2354
2355 /* Disable backlight PP control and backlight PWM. */
2356 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2357 {
2358         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2359
2360         if (!is_edp(intel_dp))
2361                 return;
2362
2363         DRM_DEBUG_KMS("\n");
2364
2365         _intel_edp_backlight_off(intel_dp);
2366         intel_panel_disable_backlight(old_conn_state);
2367 }
2368
2369 /*
2370  * Hook for controlling the panel power control backlight through the bl_power
2371  * sysfs attribute. Take care to handle multiple calls.
2372  */
2373 static void intel_edp_backlight_power(struct intel_connector *connector,
2374                                       bool enable)
2375 {
2376         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2377         bool is_enabled;
2378
2379         pps_lock(intel_dp);
2380         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2381         pps_unlock(intel_dp);
2382
2383         if (is_enabled == enable)
2384                 return;
2385
2386         DRM_DEBUG_KMS("panel power control backlight %s\n",
2387                       enable ? "enable" : "disable");
2388
2389         if (enable)
2390                 _intel_edp_backlight_on(intel_dp);
2391         else
2392                 _intel_edp_backlight_off(intel_dp);
2393 }
2394
2395 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2396 {
2397         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2398         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2399         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2400
2401         I915_STATE_WARN(cur_state != state,
2402                         "DP port %c state assertion failure (expected %s, current %s)\n",
2403                         port_name(dig_port->port),
2404                         onoff(state), onoff(cur_state));
2405 }
2406 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2407
2408 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2409 {
2410         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2411
2412         I915_STATE_WARN(cur_state != state,
2413                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2414                         onoff(state), onoff(cur_state));
2415 }
2416 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2417 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2418
2419 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2420                                 struct intel_crtc_state *pipe_config)
2421 {
2422         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2423         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2424
2425         assert_pipe_disabled(dev_priv, crtc->pipe);
2426         assert_dp_port_disabled(intel_dp);
2427         assert_edp_pll_disabled(dev_priv);
2428
2429         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2430                       pipe_config->port_clock);
2431
2432         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2433
2434         if (pipe_config->port_clock == 162000)
2435                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2436         else
2437                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2438
2439         I915_WRITE(DP_A, intel_dp->DP);
2440         POSTING_READ(DP_A);
2441         udelay(500);
2442
2443         /*
2444          * [DevILK] Work around required when enabling DP PLL
2445          * while a pipe is enabled going to FDI:
2446          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2447          * 2. Program DP PLL enable
2448          */
2449         if (IS_GEN5(dev_priv))
2450                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2451
2452         intel_dp->DP |= DP_PLL_ENABLE;
2453
2454         I915_WRITE(DP_A, intel_dp->DP);
2455         POSTING_READ(DP_A);
2456         udelay(200);
2457 }
2458
2459 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2460 {
2461         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2462         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2463         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2464
2465         assert_pipe_disabled(dev_priv, crtc->pipe);
2466         assert_dp_port_disabled(intel_dp);
2467         assert_edp_pll_enabled(dev_priv);
2468
2469         DRM_DEBUG_KMS("disabling eDP PLL\n");
2470
2471         intel_dp->DP &= ~DP_PLL_ENABLE;
2472
2473         I915_WRITE(DP_A, intel_dp->DP);
2474         POSTING_READ(DP_A);
2475         udelay(200);
2476 }
2477
2478 /* If the sink supports it, try to set the power state appropriately */
2479 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2480 {
2481         int ret, i;
2482
2483         /* Should have a valid DPCD by this point */
2484         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2485                 return;
2486
2487         if (mode != DRM_MODE_DPMS_ON) {
2488                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2489                                          DP_SET_POWER_D3);
2490         } else {
2491                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2492
2493                 /*
2494                  * When turning on, we need to retry for 1ms to give the sink
2495                  * time to wake up.
2496                  */
2497                 for (i = 0; i < 3; i++) {
2498                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2499                                                  DP_SET_POWER_D0);
2500                         if (ret == 1)
2501                                 break;
2502                         msleep(1);
2503                 }
2504
2505                 if (ret == 1 && lspcon->active)
2506                         lspcon_wait_pcon_mode(lspcon);
2507         }
2508
2509         if (ret != 1)
2510                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2511                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2512 }
2513
2514 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2515                                   enum pipe *pipe)
2516 {
2517         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2518         enum port port = dp_to_dig_port(intel_dp)->port;
2519         struct drm_device *dev = encoder->base.dev;
2520         struct drm_i915_private *dev_priv = to_i915(dev);
2521         u32 tmp;
2522         bool ret;
2523
2524         if (!intel_display_power_get_if_enabled(dev_priv,
2525                                                 encoder->power_domain))
2526                 return false;
2527
2528         ret = false;
2529
2530         tmp = I915_READ(intel_dp->output_reg);
2531
2532         if (!(tmp & DP_PORT_EN))
2533                 goto out;
2534
2535         if (IS_GEN7(dev_priv) && port == PORT_A) {
2536                 *pipe = PORT_TO_PIPE_CPT(tmp);
2537         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2538                 enum pipe p;
2539
2540                 for_each_pipe(dev_priv, p) {
2541                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2542                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2543                                 *pipe = p;
2544                                 ret = true;
2545
2546                                 goto out;
2547                         }
2548                 }
2549
2550                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2551                               i915_mmio_reg_offset(intel_dp->output_reg));
2552         } else if (IS_CHERRYVIEW(dev_priv)) {
2553                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2554         } else {
2555                 *pipe = PORT_TO_PIPE(tmp);
2556         }
2557
2558         ret = true;
2559
2560 out:
2561         intel_display_power_put(dev_priv, encoder->power_domain);
2562
2563         return ret;
2564 }
2565
2566 static void intel_dp_get_config(struct intel_encoder *encoder,
2567                                 struct intel_crtc_state *pipe_config)
2568 {
2569         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2570         u32 tmp, flags = 0;
2571         struct drm_device *dev = encoder->base.dev;
2572         struct drm_i915_private *dev_priv = to_i915(dev);
2573         enum port port = dp_to_dig_port(intel_dp)->port;
2574         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2575
2576         tmp = I915_READ(intel_dp->output_reg);
2577
2578         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2579
2580         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2581                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2582
2583                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2584                         flags |= DRM_MODE_FLAG_PHSYNC;
2585                 else
2586                         flags |= DRM_MODE_FLAG_NHSYNC;
2587
2588                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2589                         flags |= DRM_MODE_FLAG_PVSYNC;
2590                 else
2591                         flags |= DRM_MODE_FLAG_NVSYNC;
2592         } else {
2593                 if (tmp & DP_SYNC_HS_HIGH)
2594                         flags |= DRM_MODE_FLAG_PHSYNC;
2595                 else
2596                         flags |= DRM_MODE_FLAG_NHSYNC;
2597
2598                 if (tmp & DP_SYNC_VS_HIGH)
2599                         flags |= DRM_MODE_FLAG_PVSYNC;
2600                 else
2601                         flags |= DRM_MODE_FLAG_NVSYNC;
2602         }
2603
2604         pipe_config->base.adjusted_mode.flags |= flags;
2605
2606         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2607                 pipe_config->limited_color_range = true;
2608
2609         pipe_config->lane_count =
2610                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2611
2612         intel_dp_get_m_n(crtc, pipe_config);
2613
2614         if (port == PORT_A) {
2615                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2616                         pipe_config->port_clock = 162000;
2617                 else
2618                         pipe_config->port_clock = 270000;
2619         }
2620
2621         pipe_config->base.adjusted_mode.crtc_clock =
2622                 intel_dotclock_calculate(pipe_config->port_clock,
2623                                          &pipe_config->dp_m_n);
2624
2625         if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2626             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2627                 /*
2628                  * This is a big fat ugly hack.
2629                  *
2630                  * Some machines in UEFI boot mode provide us a VBT that has 18
2631                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2632                  * unknown we fail to light up. Yet the same BIOS boots up with
2633                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2634                  * max, not what it tells us to use.
2635                  *
2636                  * Note: This will still be broken if the eDP panel is not lit
2637                  * up by the BIOS, and thus we can't get the mode at module
2638                  * load.
2639                  */
2640                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2641                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2642                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2643         }
2644 }
2645
2646 static void intel_disable_dp(struct intel_encoder *encoder,
2647                              struct intel_crtc_state *old_crtc_state,
2648                              struct drm_connector_state *old_conn_state)
2649 {
2650         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2651         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2652
2653         if (old_crtc_state->has_audio)
2654                 intel_audio_codec_disable(encoder);
2655
2656         if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2657                 intel_psr_disable(intel_dp);
2658
2659         /* Make sure the panel is off before trying to change the mode. But also
2660          * ensure that we have vdd while we switch off the panel. */
2661         intel_edp_panel_vdd_on(intel_dp);
2662         intel_edp_backlight_off(old_conn_state);
2663         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2664         intel_edp_panel_off(intel_dp);
2665
2666         /* disable the port before the pipe on g4x */
2667         if (INTEL_GEN(dev_priv) < 5)
2668                 intel_dp_link_down(intel_dp);
2669 }
2670
2671 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2672                                 struct intel_crtc_state *old_crtc_state,
2673                                 struct drm_connector_state *old_conn_state)
2674 {
2675         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2676         enum port port = dp_to_dig_port(intel_dp)->port;
2677
2678         intel_dp_link_down(intel_dp);
2679
2680         /* Only ilk+ has port A */
2681         if (port == PORT_A)
2682                 ironlake_edp_pll_off(intel_dp);
2683 }
2684
2685 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2686                                 struct intel_crtc_state *old_crtc_state,
2687                                 struct drm_connector_state *old_conn_state)
2688 {
2689         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2690
2691         intel_dp_link_down(intel_dp);
2692 }
2693
2694 static void chv_post_disable_dp(struct intel_encoder *encoder,
2695                                 struct intel_crtc_state *old_crtc_state,
2696                                 struct drm_connector_state *old_conn_state)
2697 {
2698         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2699         struct drm_device *dev = encoder->base.dev;
2700         struct drm_i915_private *dev_priv = to_i915(dev);
2701
2702         intel_dp_link_down(intel_dp);
2703
2704         mutex_lock(&dev_priv->sb_lock);
2705
2706         /* Assert data lane reset */
2707         chv_data_lane_soft_reset(encoder, true);
2708
2709         mutex_unlock(&dev_priv->sb_lock);
2710 }
2711
2712 static void
2713 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2714                          uint32_t *DP,
2715                          uint8_t dp_train_pat)
2716 {
2717         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2718         struct drm_device *dev = intel_dig_port->base.base.dev;
2719         struct drm_i915_private *dev_priv = to_i915(dev);
2720         enum port port = intel_dig_port->port;
2721
2722         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2723                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2724                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2725
2726         if (HAS_DDI(dev_priv)) {
2727                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2728
2729                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2730                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2731                 else
2732                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2733
2734                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2735                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2736                 case DP_TRAINING_PATTERN_DISABLE:
2737                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2738
2739                         break;
2740                 case DP_TRAINING_PATTERN_1:
2741                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2742                         break;
2743                 case DP_TRAINING_PATTERN_2:
2744                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2745                         break;
2746                 case DP_TRAINING_PATTERN_3:
2747                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2748                         break;
2749                 }
2750                 I915_WRITE(DP_TP_CTL(port), temp);
2751
2752         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2753                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2754                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2755
2756                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2757                 case DP_TRAINING_PATTERN_DISABLE:
2758                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2759                         break;
2760                 case DP_TRAINING_PATTERN_1:
2761                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2762                         break;
2763                 case DP_TRAINING_PATTERN_2:
2764                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2765                         break;
2766                 case DP_TRAINING_PATTERN_3:
2767                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2768                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2769                         break;
2770                 }
2771
2772         } else {
2773                 if (IS_CHERRYVIEW(dev_priv))
2774                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2775                 else
2776                         *DP &= ~DP_LINK_TRAIN_MASK;
2777
2778                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2779                 case DP_TRAINING_PATTERN_DISABLE:
2780                         *DP |= DP_LINK_TRAIN_OFF;
2781                         break;
2782                 case DP_TRAINING_PATTERN_1:
2783                         *DP |= DP_LINK_TRAIN_PAT_1;
2784                         break;
2785                 case DP_TRAINING_PATTERN_2:
2786                         *DP |= DP_LINK_TRAIN_PAT_2;
2787                         break;
2788                 case DP_TRAINING_PATTERN_3:
2789                         if (IS_CHERRYVIEW(dev_priv)) {
2790                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2791                         } else {
2792                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2793                                 *DP |= DP_LINK_TRAIN_PAT_2;
2794                         }
2795                         break;
2796                 }
2797         }
2798 }
2799
2800 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2801                                  struct intel_crtc_state *old_crtc_state)
2802 {
2803         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2804         struct drm_i915_private *dev_priv = to_i915(dev);
2805
2806         /* enable with pattern 1 (as per spec) */
2807
2808         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2809
2810         /*
2811          * Magic for VLV/CHV. We _must_ first set up the register
2812          * without actually enabling the port, and then do another
2813          * write to enable the port. Otherwise link training will
2814          * fail when the power sequencer is freshly used for this port.
2815          */
2816         intel_dp->DP |= DP_PORT_EN;
2817         if (old_crtc_state->has_audio)
2818                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2819
2820         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2821         POSTING_READ(intel_dp->output_reg);
2822 }
2823
2824 static void intel_enable_dp(struct intel_encoder *encoder,
2825                             struct intel_crtc_state *pipe_config,
2826                             struct drm_connector_state *conn_state)
2827 {
2828         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2829         struct drm_device *dev = encoder->base.dev;
2830         struct drm_i915_private *dev_priv = to_i915(dev);
2831         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2832         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2833         enum pipe pipe = crtc->pipe;
2834
2835         if (WARN_ON(dp_reg & DP_PORT_EN))
2836                 return;
2837
2838         pps_lock(intel_dp);
2839
2840         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2841                 vlv_init_panel_power_sequencer(intel_dp);
2842
2843         intel_dp_enable_port(intel_dp, pipe_config);
2844
2845         edp_panel_vdd_on(intel_dp);
2846         edp_panel_on(intel_dp);
2847         edp_panel_vdd_off(intel_dp, true);
2848
2849         pps_unlock(intel_dp);
2850
2851         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2852                 unsigned int lane_mask = 0x0;
2853
2854                 if (IS_CHERRYVIEW(dev_priv))
2855                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2856
2857                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2858                                     lane_mask);
2859         }
2860
2861         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2862         intel_dp_start_link_train(intel_dp);
2863         intel_dp_stop_link_train(intel_dp);
2864
2865         if (pipe_config->has_audio) {
2866                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2867                                  pipe_name(pipe));
2868                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2869         }
2870 }
2871
2872 static void g4x_enable_dp(struct intel_encoder *encoder,
2873                           struct intel_crtc_state *pipe_config,
2874                           struct drm_connector_state *conn_state)
2875 {
2876         intel_enable_dp(encoder, pipe_config, conn_state);
2877         intel_edp_backlight_on(pipe_config, conn_state);
2878 }
2879
2880 static void vlv_enable_dp(struct intel_encoder *encoder,
2881                           struct intel_crtc_state *pipe_config,
2882                           struct drm_connector_state *conn_state)
2883 {
2884         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2885
2886         intel_edp_backlight_on(pipe_config, conn_state);
2887         intel_psr_enable(intel_dp);
2888 }
2889
2890 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2891                               struct intel_crtc_state *pipe_config,
2892                               struct drm_connector_state *conn_state)
2893 {
2894         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2895         enum port port = dp_to_dig_port(intel_dp)->port;
2896
2897         intel_dp_prepare(encoder, pipe_config);
2898
2899         /* Only ilk+ has port A */
2900         if (port == PORT_A)
2901                 ironlake_edp_pll_on(intel_dp, pipe_config);
2902 }
2903
2904 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2905 {
2906         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2907         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2908         enum pipe pipe = intel_dp->pps_pipe;
2909         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2910
2911         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2912
2913         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2914                 return;
2915
2916         edp_panel_vdd_off_sync(intel_dp);
2917
2918         /*
2919          * VLV seems to get confused when multiple power seqeuencers
2920          * have the same port selected (even if only one has power/vdd
2921          * enabled). The failure manifests as vlv_wait_port_ready() failing
2922          * CHV on the other hand doesn't seem to mind having the same port
2923          * selected in multiple power seqeuencers, but let's clear the
2924          * port select always when logically disconnecting a power sequencer
2925          * from a port.
2926          */
2927         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2928                       pipe_name(pipe), port_name(intel_dig_port->port));
2929         I915_WRITE(pp_on_reg, 0);
2930         POSTING_READ(pp_on_reg);
2931
2932         intel_dp->pps_pipe = INVALID_PIPE;
2933 }
2934
2935 static void vlv_steal_power_sequencer(struct drm_device *dev,
2936                                       enum pipe pipe)
2937 {
2938         struct drm_i915_private *dev_priv = to_i915(dev);
2939         struct intel_encoder *encoder;
2940
2941         lockdep_assert_held(&dev_priv->pps_mutex);
2942
2943         for_each_intel_encoder(dev, encoder) {
2944                 struct intel_dp *intel_dp;
2945                 enum port port;
2946
2947                 if (encoder->type != INTEL_OUTPUT_DP &&
2948                     encoder->type != INTEL_OUTPUT_EDP)
2949                         continue;
2950
2951                 intel_dp = enc_to_intel_dp(&encoder->base);
2952                 port = dp_to_dig_port(intel_dp)->port;
2953
2954                 WARN(intel_dp->active_pipe == pipe,
2955                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
2956                      pipe_name(pipe), port_name(port));
2957
2958                 if (intel_dp->pps_pipe != pipe)
2959                         continue;
2960
2961                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2962                               pipe_name(pipe), port_name(port));
2963
2964                 /* make sure vdd is off before we steal it */
2965                 vlv_detach_power_sequencer(intel_dp);
2966         }
2967 }
2968
2969 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2970 {
2971         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2972         struct intel_encoder *encoder = &intel_dig_port->base;
2973         struct drm_device *dev = encoder->base.dev;
2974         struct drm_i915_private *dev_priv = to_i915(dev);
2975         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2976
2977         lockdep_assert_held(&dev_priv->pps_mutex);
2978
2979         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2980
2981         if (intel_dp->pps_pipe != INVALID_PIPE &&
2982             intel_dp->pps_pipe != crtc->pipe) {
2983                 /*
2984                  * If another power sequencer was being used on this
2985                  * port previously make sure to turn off vdd there while
2986                  * we still have control of it.
2987                  */
2988                 vlv_detach_power_sequencer(intel_dp);
2989         }
2990
2991         /*
2992          * We may be stealing the power
2993          * sequencer from another port.
2994          */
2995         vlv_steal_power_sequencer(dev, crtc->pipe);
2996
2997         intel_dp->active_pipe = crtc->pipe;
2998
2999         if (!is_edp(intel_dp))
3000                 return;
3001
3002         /* now it's all ours */
3003         intel_dp->pps_pipe = crtc->pipe;
3004
3005         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3006                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
3007
3008         /* init power sequencer on this pipe and port */
3009         intel_dp_init_panel_power_sequencer(dev, intel_dp);
3010         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
3011 }
3012
3013 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3014                               struct intel_crtc_state *pipe_config,
3015                               struct drm_connector_state *conn_state)
3016 {
3017         vlv_phy_pre_encoder_enable(encoder);
3018
3019         intel_enable_dp(encoder, pipe_config, conn_state);
3020 }
3021
3022 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3023                                   struct intel_crtc_state *pipe_config,
3024                                   struct drm_connector_state *conn_state)
3025 {
3026         intel_dp_prepare(encoder, pipe_config);
3027
3028         vlv_phy_pre_pll_enable(encoder);
3029 }
3030
3031 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3032                               struct intel_crtc_state *pipe_config,
3033                               struct drm_connector_state *conn_state)
3034 {
3035         chv_phy_pre_encoder_enable(encoder);
3036
3037         intel_enable_dp(encoder, pipe_config, conn_state);
3038
3039         /* Second common lane will stay alive on its own now */
3040         chv_phy_release_cl2_override(encoder);
3041 }
3042
3043 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3044                                   struct intel_crtc_state *pipe_config,
3045                                   struct drm_connector_state *conn_state)
3046 {
3047         intel_dp_prepare(encoder, pipe_config);
3048
3049         chv_phy_pre_pll_enable(encoder);
3050 }
3051
3052 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3053                                     struct intel_crtc_state *pipe_config,
3054                                     struct drm_connector_state *conn_state)
3055 {
3056         chv_phy_post_pll_disable(encoder);
3057 }
3058
3059 /*
3060  * Fetch AUX CH registers 0x202 - 0x207 which contain
3061  * link status information
3062  */
3063 bool
3064 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3065 {
3066         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3067                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3068 }
3069
3070 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3071 {
3072         uint8_t psr_caps = 0;
3073
3074         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
3075                 return false;
3076         return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3077 }
3078
3079 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3080 {
3081         uint8_t dprx = 0;
3082
3083         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3084                               &dprx) != 1)
3085                 return false;
3086         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3087 }
3088
3089 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3090 {
3091         uint8_t alpm_caps = 0;
3092
3093         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
3094                               &alpm_caps) != 1)
3095                 return false;
3096         return alpm_caps & DP_ALPM_CAP;
3097 }
3098
3099 /* These are source-specific values. */
3100 uint8_t
3101 intel_dp_voltage_max(struct intel_dp *intel_dp)
3102 {
3103         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3104         enum port port = dp_to_dig_port(intel_dp)->port;
3105
3106         if (IS_GEN9_LP(dev_priv))
3107                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3108         else if (INTEL_GEN(dev_priv) >= 9) {
3109                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3110                 return intel_ddi_dp_voltage_max(encoder);
3111         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3112                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3113         else if (IS_GEN7(dev_priv) && port == PORT_A)
3114                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3115         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3116                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3117         else
3118                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3119 }
3120
3121 uint8_t
3122 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3123 {
3124         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3125         enum port port = dp_to_dig_port(intel_dp)->port;
3126
3127         if (INTEL_GEN(dev_priv) >= 9) {
3128                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3129                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3130                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3131                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3132                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3133                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3134                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3135                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3136                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3137                 default:
3138                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3139                 }
3140         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3141                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3142                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3143                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3144                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3145                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3146                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3147                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3148                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3149                 default:
3150                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3151                 }
3152         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3153                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3154                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3155                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3156                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3157                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3158                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3159                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3160                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3161                 default:
3162                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3163                 }
3164         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3165                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3166                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3167                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3168                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3169                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3170                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3171                 default:
3172                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3173                 }
3174         } else {
3175                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3176                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3177                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3178                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3179                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3180                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3181                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3182                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3183                 default:
3184                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3185                 }
3186         }
3187 }
3188
3189 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3190 {
3191         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3192         unsigned long demph_reg_value, preemph_reg_value,
3193                 uniqtranscale_reg_value;
3194         uint8_t train_set = intel_dp->train_set[0];
3195
3196         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3197         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3198                 preemph_reg_value = 0x0004000;
3199                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3200                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3201                         demph_reg_value = 0x2B405555;
3202                         uniqtranscale_reg_value = 0x552AB83A;
3203                         break;
3204                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3205                         demph_reg_value = 0x2B404040;
3206                         uniqtranscale_reg_value = 0x5548B83A;
3207                         break;
3208                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3209                         demph_reg_value = 0x2B245555;
3210                         uniqtranscale_reg_value = 0x5560B83A;
3211                         break;
3212                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3213                         demph_reg_value = 0x2B405555;
3214                         uniqtranscale_reg_value = 0x5598DA3A;
3215                         break;
3216                 default:
3217                         return 0;
3218                 }
3219                 break;
3220         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3221                 preemph_reg_value = 0x0002000;
3222                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3223                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3224                         demph_reg_value = 0x2B404040;
3225                         uniqtranscale_reg_value = 0x5552B83A;
3226                         break;
3227                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3228                         demph_reg_value = 0x2B404848;
3229                         uniqtranscale_reg_value = 0x5580B83A;
3230                         break;
3231                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3232                         demph_reg_value = 0x2B404040;
3233                         uniqtranscale_reg_value = 0x55ADDA3A;
3234                         break;
3235                 default:
3236                         return 0;
3237                 }
3238                 break;
3239         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3240                 preemph_reg_value = 0x0000000;
3241                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3242                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3243                         demph_reg_value = 0x2B305555;
3244                         uniqtranscale_reg_value = 0x5570B83A;
3245                         break;
3246                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3247                         demph_reg_value = 0x2B2B4040;
3248                         uniqtranscale_reg_value = 0x55ADDA3A;
3249                         break;
3250                 default:
3251                         return 0;
3252                 }
3253                 break;
3254         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3255                 preemph_reg_value = 0x0006000;
3256                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3257                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3258                         demph_reg_value = 0x1B405555;
3259                         uniqtranscale_reg_value = 0x55ADDA3A;
3260                         break;
3261                 default:
3262                         return 0;
3263                 }
3264                 break;
3265         default:
3266                 return 0;
3267         }
3268
3269         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3270                                  uniqtranscale_reg_value, 0);
3271
3272         return 0;
3273 }
3274
3275 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3276 {
3277         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3278         u32 deemph_reg_value, margin_reg_value;
3279         bool uniq_trans_scale = false;
3280         uint8_t train_set = intel_dp->train_set[0];
3281
3282         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3283         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3284                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3285                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3286                         deemph_reg_value = 128;
3287                         margin_reg_value = 52;
3288                         break;
3289                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3290                         deemph_reg_value = 128;
3291                         margin_reg_value = 77;
3292                         break;
3293                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3294                         deemph_reg_value = 128;
3295                         margin_reg_value = 102;
3296                         break;
3297                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3298                         deemph_reg_value = 128;
3299                         margin_reg_value = 154;
3300                         uniq_trans_scale = true;
3301                         break;
3302                 default:
3303                         return 0;
3304                 }
3305                 break;
3306         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3307                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3308                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3309                         deemph_reg_value = 85;
3310                         margin_reg_value = 78;
3311                         break;
3312                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3313                         deemph_reg_value = 85;
3314                         margin_reg_value = 116;
3315                         break;
3316                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3317                         deemph_reg_value = 85;
3318                         margin_reg_value = 154;
3319                         break;
3320                 default:
3321                         return 0;
3322                 }
3323                 break;
3324         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3325                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3326                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3327                         deemph_reg_value = 64;
3328                         margin_reg_value = 104;
3329                         break;
3330                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3331                         deemph_reg_value = 64;
3332                         margin_reg_value = 154;
3333                         break;
3334                 default:
3335                         return 0;
3336                 }
3337                 break;
3338         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3339                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3340                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3341                         deemph_reg_value = 43;
3342                         margin_reg_value = 154;
3343                         break;
3344                 default:
3345                         return 0;
3346                 }
3347                 break;
3348         default:
3349                 return 0;
3350         }
3351
3352         chv_set_phy_signal_level(encoder, deemph_reg_value,
3353                                  margin_reg_value, uniq_trans_scale);
3354
3355         return 0;
3356 }
3357
3358 static uint32_t
3359 gen4_signal_levels(uint8_t train_set)
3360 {
3361         uint32_t        signal_levels = 0;
3362
3363         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3364         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3365         default:
3366                 signal_levels |= DP_VOLTAGE_0_4;
3367                 break;
3368         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3369                 signal_levels |= DP_VOLTAGE_0_6;
3370                 break;
3371         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3372                 signal_levels |= DP_VOLTAGE_0_8;
3373                 break;
3374         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3375                 signal_levels |= DP_VOLTAGE_1_2;
3376                 break;
3377         }
3378         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3379         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3380         default:
3381                 signal_levels |= DP_PRE_EMPHASIS_0;
3382                 break;
3383         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3384                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3385                 break;
3386         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3387                 signal_levels |= DP_PRE_EMPHASIS_6;
3388                 break;
3389         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3390                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3391                 break;
3392         }
3393         return signal_levels;
3394 }
3395
3396 /* Gen6's DP voltage swing and pre-emphasis control */
3397 static uint32_t
3398 gen6_edp_signal_levels(uint8_t train_set)
3399 {
3400         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3401                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3402         switch (signal_levels) {
3403         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3404         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3405                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3406         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3407                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3408         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3409         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3410                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3411         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3412         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3413                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3414         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3415         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3416                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3417         default:
3418                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3419                               "0x%x\n", signal_levels);
3420                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3421         }
3422 }
3423
3424 /* Gen7's DP voltage swing and pre-emphasis control */
3425 static uint32_t
3426 gen7_edp_signal_levels(uint8_t train_set)
3427 {
3428         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3429                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3430         switch (signal_levels) {
3431         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3432                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3433         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3434                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3435         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3436                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3437
3438         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3439                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3440         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3441                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3442
3443         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3444                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3445         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3446                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3447
3448         default:
3449                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3450                               "0x%x\n", signal_levels);
3451                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3452         }
3453 }
3454
3455 void
3456 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3457 {
3458         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3459         enum port port = intel_dig_port->port;
3460         struct drm_device *dev = intel_dig_port->base.base.dev;
3461         struct drm_i915_private *dev_priv = to_i915(dev);
3462         uint32_t signal_levels, mask = 0;
3463         uint8_t train_set = intel_dp->train_set[0];
3464
3465         if (HAS_DDI(dev_priv)) {
3466                 signal_levels = ddi_signal_levels(intel_dp);
3467
3468                 if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
3469                         signal_levels = 0;
3470                 else
3471                         mask = DDI_BUF_EMP_MASK;
3472         } else if (IS_CHERRYVIEW(dev_priv)) {
3473                 signal_levels = chv_signal_levels(intel_dp);
3474         } else if (IS_VALLEYVIEW(dev_priv)) {
3475                 signal_levels = vlv_signal_levels(intel_dp);
3476         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3477                 signal_levels = gen7_edp_signal_levels(train_set);
3478                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3479         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3480                 signal_levels = gen6_edp_signal_levels(train_set);
3481                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3482         } else {
3483                 signal_levels = gen4_signal_levels(train_set);
3484                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3485         }
3486
3487         if (mask)
3488                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3489
3490         DRM_DEBUG_KMS("Using vswing level %d\n",
3491                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3492         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3493                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3494                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3495
3496         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3497
3498         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3499         POSTING_READ(intel_dp->output_reg);
3500 }
3501
3502 void
3503 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3504                                        uint8_t dp_train_pat)
3505 {
3506         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3507         struct drm_i915_private *dev_priv =
3508                 to_i915(intel_dig_port->base.base.dev);
3509
3510         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3511
3512         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3513         POSTING_READ(intel_dp->output_reg);
3514 }
3515
3516 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3517 {
3518         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3519         struct drm_device *dev = intel_dig_port->base.base.dev;
3520         struct drm_i915_private *dev_priv = to_i915(dev);
3521         enum port port = intel_dig_port->port;
3522         uint32_t val;
3523
3524         if (!HAS_DDI(dev_priv))
3525                 return;
3526
3527         val = I915_READ(DP_TP_CTL(port));
3528         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3529         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3530         I915_WRITE(DP_TP_CTL(port), val);
3531
3532         /*
3533          * On PORT_A we can have only eDP in SST mode. There the only reason
3534          * we need to set idle transmission mode is to work around a HW issue
3535          * where we enable the pipe while not in idle link-training mode.
3536          * In this case there is requirement to wait for a minimum number of
3537          * idle patterns to be sent.
3538          */
3539         if (port == PORT_A)
3540                 return;
3541
3542         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3543                                     DP_TP_STATUS_IDLE_DONE,
3544                                     DP_TP_STATUS_IDLE_DONE,
3545                                     1))
3546                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3547 }
3548
3549 static void
3550 intel_dp_link_down(struct intel_dp *intel_dp)
3551 {
3552         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3553         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3554         enum port port = intel_dig_port->port;
3555         struct drm_device *dev = intel_dig_port->base.base.dev;
3556         struct drm_i915_private *dev_priv = to_i915(dev);
3557         uint32_t DP = intel_dp->DP;
3558
3559         if (WARN_ON(HAS_DDI(dev_priv)))
3560                 return;
3561
3562         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3563                 return;
3564
3565         DRM_DEBUG_KMS("\n");
3566
3567         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3568             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3569                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3570                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3571         } else {
3572                 if (IS_CHERRYVIEW(dev_priv))
3573                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3574                 else
3575                         DP &= ~DP_LINK_TRAIN_MASK;
3576                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3577         }
3578         I915_WRITE(intel_dp->output_reg, DP);
3579         POSTING_READ(intel_dp->output_reg);
3580
3581         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3582         I915_WRITE(intel_dp->output_reg, DP);
3583         POSTING_READ(intel_dp->output_reg);
3584
3585         /*
3586          * HW workaround for IBX, we need to move the port
3587          * to transcoder A after disabling it to allow the
3588          * matching HDMI port to be enabled on transcoder A.
3589          */
3590         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3591                 /*
3592                  * We get CPU/PCH FIFO underruns on the other pipe when
3593                  * doing the workaround. Sweep them under the rug.
3594                  */
3595                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3596                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3597
3598                 /* always enable with pattern 1 (as per spec) */
3599                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3600                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3601                 I915_WRITE(intel_dp->output_reg, DP);
3602                 POSTING_READ(intel_dp->output_reg);
3603
3604                 DP &= ~DP_PORT_EN;
3605                 I915_WRITE(intel_dp->output_reg, DP);
3606                 POSTING_READ(intel_dp->output_reg);
3607
3608                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3609                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3610                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3611         }
3612
3613         msleep(intel_dp->panel_power_down_delay);
3614
3615         intel_dp->DP = DP;
3616
3617         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3618                 pps_lock(intel_dp);
3619                 intel_dp->active_pipe = INVALID_PIPE;
3620                 pps_unlock(intel_dp);
3621         }
3622 }
3623
3624 bool
3625 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3626 {
3627         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3628                              sizeof(intel_dp->dpcd)) < 0)
3629                 return false; /* aux transfer failed */
3630
3631         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3632
3633         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3634 }
3635
3636 static bool
3637 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3638 {
3639         struct drm_i915_private *dev_priv =
3640                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3641
3642         /* this function is meant to be called only once */
3643         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3644
3645         if (!intel_dp_read_dpcd(intel_dp))
3646                 return false;
3647
3648         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3649                          drm_dp_is_branch(intel_dp->dpcd));
3650
3651         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3652                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3653                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3654
3655         /* Check if the panel supports PSR */
3656         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3657                          intel_dp->psr_dpcd,
3658                          sizeof(intel_dp->psr_dpcd));
3659         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3660                 dev_priv->psr.sink_support = true;
3661                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3662         }
3663
3664         if (INTEL_GEN(dev_priv) >= 9 &&
3665             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3666                 uint8_t frame_sync_cap;
3667
3668                 dev_priv->psr.sink_support = true;
3669                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3670                                       DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3671                                       &frame_sync_cap) != 1)
3672                         frame_sync_cap = 0;
3673                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3674                 /* PSR2 needs frame sync as well */
3675                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3676                 DRM_DEBUG_KMS("PSR2 %s on sink",
3677                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3678
3679                 if (dev_priv->psr.psr2_support) {
3680                         dev_priv->psr.y_cord_support =
3681                                 intel_dp_get_y_cord_status(intel_dp);
3682                         dev_priv->psr.colorimetry_support =
3683                                 intel_dp_get_colorimetry_status(intel_dp);
3684                         dev_priv->psr.alpm =
3685                                 intel_dp_get_alpm_status(intel_dp);
3686                 }
3687
3688         }
3689
3690         /* Read the eDP Display control capabilities registers */
3691         if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3692             drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3693                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3694                              sizeof(intel_dp->edp_dpcd))
3695                 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3696                               intel_dp->edp_dpcd);
3697
3698         /* Intermediate frequency support */
3699         if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3700                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3701                 int i;
3702
3703                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3704                                 sink_rates, sizeof(sink_rates));
3705
3706                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3707                         int val = le16_to_cpu(sink_rates[i]);
3708
3709                         if (val == 0)
3710                                 break;
3711
3712                         /* Value read multiplied by 200kHz gives the per-lane
3713                          * link rate in kHz. The source rates are, however,
3714                          * stored in terms of LS_Clk kHz. The full conversion
3715                          * back to symbols is
3716                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3717                          */
3718                         intel_dp->sink_rates[i] = (val * 200) / 10;
3719                 }
3720                 intel_dp->num_sink_rates = i;
3721         }
3722
3723         if (intel_dp->num_sink_rates)
3724                 intel_dp->use_rate_select = true;
3725         else
3726                 intel_dp_set_sink_rates(intel_dp);
3727
3728         intel_dp_set_common_rates(intel_dp);
3729
3730         return true;
3731 }
3732
3733
3734 static bool
3735 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3736 {
3737         u8 sink_count;
3738
3739         if (!intel_dp_read_dpcd(intel_dp))
3740                 return false;
3741
3742         /* Don't clobber cached eDP rates. */
3743         if (!is_edp(intel_dp)) {
3744                 intel_dp_set_sink_rates(intel_dp);
3745                 intel_dp_set_common_rates(intel_dp);
3746         }
3747
3748         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3749                 return false;
3750
3751         /*
3752          * Sink count can change between short pulse hpd hence
3753          * a member variable in intel_dp will track any changes
3754          * between short pulse interrupts.
3755          */
3756         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3757
3758         /*
3759          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3760          * a dongle is present but no display. Unless we require to know
3761          * if a dongle is present or not, we don't need to update
3762          * downstream port information. So, an early return here saves
3763          * time from performing other operations which are not required.
3764          */
3765         if (!is_edp(intel_dp) && !intel_dp->sink_count)
3766                 return false;
3767
3768         if (!drm_dp_is_branch(intel_dp->dpcd))
3769                 return true; /* native DP sink */
3770
3771         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3772                 return true; /* no per-port downstream info */
3773
3774         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3775                              intel_dp->downstream_ports,
3776                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3777                 return false; /* downstream port status fetch failed */
3778
3779         return true;
3780 }
3781
3782 static bool
3783 intel_dp_can_mst(struct intel_dp *intel_dp)
3784 {
3785         u8 mstm_cap;
3786
3787         if (!i915.enable_dp_mst)
3788                 return false;
3789
3790         if (!intel_dp->can_mst)
3791                 return false;
3792
3793         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3794                 return false;
3795
3796         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3797                 return false;
3798
3799         return mstm_cap & DP_MST_CAP;
3800 }
3801
3802 static void
3803 intel_dp_configure_mst(struct intel_dp *intel_dp)
3804 {
3805         if (!i915.enable_dp_mst)
3806                 return;
3807
3808         if (!intel_dp->can_mst)
3809                 return;
3810
3811         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3812
3813         if (intel_dp->is_mst)
3814                 DRM_DEBUG_KMS("Sink is MST capable\n");
3815         else
3816                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3817
3818         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3819                                         intel_dp->is_mst);
3820 }
3821
3822 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3823 {
3824         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3825         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3826         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3827         u8 buf;
3828         int ret = 0;
3829         int count = 0;
3830         int attempts = 10;
3831
3832         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3833                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3834                 ret = -EIO;
3835                 goto out;
3836         }
3837
3838         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3839                                buf & ~DP_TEST_SINK_START) < 0) {
3840                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3841                 ret = -EIO;
3842                 goto out;
3843         }
3844
3845         do {
3846                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3847
3848                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3849                                       DP_TEST_SINK_MISC, &buf) < 0) {
3850                         ret = -EIO;
3851                         goto out;
3852                 }
3853                 count = buf & DP_TEST_COUNT_MASK;
3854         } while (--attempts && count);
3855
3856         if (attempts == 0) {
3857                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3858                 ret = -ETIMEDOUT;
3859         }
3860
3861  out:
3862         hsw_enable_ips(intel_crtc);
3863         return ret;
3864 }
3865
3866 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3867 {
3868         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3869         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3870         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3871         u8 buf;
3872         int ret;
3873
3874         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3875                 return -EIO;
3876
3877         if (!(buf & DP_TEST_CRC_SUPPORTED))
3878                 return -ENOTTY;
3879
3880         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3881                 return -EIO;
3882
3883         if (buf & DP_TEST_SINK_START) {
3884                 ret = intel_dp_sink_crc_stop(intel_dp);
3885                 if (ret)
3886                         return ret;
3887         }
3888
3889         hsw_disable_ips(intel_crtc);
3890
3891         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3892                                buf | DP_TEST_SINK_START) < 0) {
3893                 hsw_enable_ips(intel_crtc);
3894                 return -EIO;
3895         }
3896
3897         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3898         return 0;
3899 }
3900
3901 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3902 {
3903         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3904         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3905         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3906         u8 buf;
3907         int count, ret;
3908         int attempts = 6;
3909
3910         ret = intel_dp_sink_crc_start(intel_dp);
3911         if (ret)
3912                 return ret;
3913
3914         do {
3915                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3916
3917                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3918                                       DP_TEST_SINK_MISC, &buf) < 0) {
3919                         ret = -EIO;
3920                         goto stop;
3921                 }
3922                 count = buf & DP_TEST_COUNT_MASK;
3923
3924         } while (--attempts && count == 0);
3925
3926         if (attempts == 0) {
3927                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3928                 ret = -ETIMEDOUT;
3929                 goto stop;
3930         }
3931
3932         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3933                 ret = -EIO;
3934                 goto stop;
3935         }
3936
3937 stop:
3938         intel_dp_sink_crc_stop(intel_dp);
3939         return ret;
3940 }
3941
3942 static bool
3943 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3944 {
3945         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
3946                                  sink_irq_vector) == 1;
3947 }
3948
3949 static bool
3950 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3951 {
3952         int ret;
3953
3954         ret = drm_dp_dpcd_read(&intel_dp->aux,
3955                                              DP_SINK_COUNT_ESI,
3956                                              sink_irq_vector, 14);
3957         if (ret != 14)
3958                 return false;
3959
3960         return true;
3961 }
3962
3963 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3964 {
3965         int status = 0;
3966         int min_lane_count = 1;
3967         int link_rate_index, test_link_rate;
3968         uint8_t test_lane_count, test_link_bw;
3969         /* (DP CTS 1.2)
3970          * 4.3.1.11
3971          */
3972         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3973         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3974                                    &test_lane_count);
3975
3976         if (status <= 0) {
3977                 DRM_DEBUG_KMS("Lane count read failed\n");
3978                 return DP_TEST_NAK;
3979         }
3980         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3981         /* Validate the requested lane count */
3982         if (test_lane_count < min_lane_count ||
3983             test_lane_count > intel_dp->max_link_lane_count)
3984                 return DP_TEST_NAK;
3985
3986         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3987                                    &test_link_bw);
3988         if (status <= 0) {
3989                 DRM_DEBUG_KMS("Link Rate read failed\n");
3990                 return DP_TEST_NAK;
3991         }
3992         /* Validate the requested link rate */
3993         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3994         link_rate_index = intel_dp_rate_index(intel_dp->common_rates,
3995                                               intel_dp->num_common_rates,
3996                                               test_link_rate);
3997         if (link_rate_index < 0)
3998                 return DP_TEST_NAK;
3999
4000         intel_dp->compliance.test_lane_count = test_lane_count;
4001         intel_dp->compliance.test_link_rate = test_link_rate;
4002
4003         return DP_TEST_ACK;
4004 }
4005
4006 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4007 {
4008         uint8_t test_pattern;
4009         uint8_t test_misc;
4010         __be16 h_width, v_height;
4011         int status = 0;
4012
4013         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4014         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4015                                    &test_pattern);
4016         if (status <= 0) {
4017                 DRM_DEBUG_KMS("Test pattern read failed\n");
4018                 return DP_TEST_NAK;
4019         }
4020         if (test_pattern != DP_COLOR_RAMP)
4021                 return DP_TEST_NAK;
4022
4023         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4024                                   &h_width, 2);
4025         if (status <= 0) {
4026                 DRM_DEBUG_KMS("H Width read failed\n");
4027                 return DP_TEST_NAK;
4028         }
4029
4030         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4031                                   &v_height, 2);
4032         if (status <= 0) {
4033                 DRM_DEBUG_KMS("V Height read failed\n");
4034                 return DP_TEST_NAK;
4035         }
4036
4037         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4038                                    &test_misc);
4039         if (status <= 0) {
4040                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4041                 return DP_TEST_NAK;
4042         }
4043         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4044                 return DP_TEST_NAK;
4045         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4046                 return DP_TEST_NAK;
4047         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4048         case DP_TEST_BIT_DEPTH_6:
4049                 intel_dp->compliance.test_data.bpc = 6;
4050                 break;
4051         case DP_TEST_BIT_DEPTH_8:
4052                 intel_dp->compliance.test_data.bpc = 8;
4053                 break;
4054         default:
4055                 return DP_TEST_NAK;
4056         }
4057
4058         intel_dp->compliance.test_data.video_pattern = test_pattern;
4059         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4060         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4061         /* Set test active flag here so userspace doesn't interrupt things */
4062         intel_dp->compliance.test_active = 1;
4063
4064         return DP_TEST_ACK;
4065 }
4066
4067 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4068 {
4069         uint8_t test_result = DP_TEST_ACK;
4070         struct intel_connector *intel_connector = intel_dp->attached_connector;
4071         struct drm_connector *connector = &intel_connector->base;
4072
4073         if (intel_connector->detect_edid == NULL ||
4074             connector->edid_corrupt ||
4075             intel_dp->aux.i2c_defer_count > 6) {
4076                 /* Check EDID read for NACKs, DEFERs and corruption
4077                  * (DP CTS 1.2 Core r1.1)
4078                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4079                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4080                  *    4.2.2.6 : EDID corruption detected
4081                  * Use failsafe mode for all cases
4082                  */
4083                 if (intel_dp->aux.i2c_nack_count > 0 ||
4084                         intel_dp->aux.i2c_defer_count > 0)
4085                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4086                                       intel_dp->aux.i2c_nack_count,
4087                                       intel_dp->aux.i2c_defer_count);
4088                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4089         } else {
4090                 struct edid *block = intel_connector->detect_edid;
4091
4092                 /* We have to write the checksum
4093                  * of the last block read
4094                  */
4095                 block += intel_connector->detect_edid->extensions;
4096
4097                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4098                                        block->checksum) <= 0)
4099                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4100
4101                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4102                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4103         }
4104
4105         /* Set test active flag here so userspace doesn't interrupt things */
4106         intel_dp->compliance.test_active = 1;
4107
4108         return test_result;
4109 }
4110
4111 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4112 {
4113         uint8_t test_result = DP_TEST_NAK;
4114         return test_result;
4115 }
4116
4117 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4118 {
4119         uint8_t response = DP_TEST_NAK;
4120         uint8_t request = 0;
4121         int status;
4122
4123         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4124         if (status <= 0) {
4125                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4126                 goto update_status;
4127         }
4128
4129         switch (request) {
4130         case DP_TEST_LINK_TRAINING:
4131                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4132                 response = intel_dp_autotest_link_training(intel_dp);
4133                 break;
4134         case DP_TEST_LINK_VIDEO_PATTERN:
4135                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4136                 response = intel_dp_autotest_video_pattern(intel_dp);
4137                 break;
4138         case DP_TEST_LINK_EDID_READ:
4139                 DRM_DEBUG_KMS("EDID test requested\n");
4140                 response = intel_dp_autotest_edid(intel_dp);
4141                 break;
4142         case DP_TEST_LINK_PHY_TEST_PATTERN:
4143                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4144                 response = intel_dp_autotest_phy_pattern(intel_dp);
4145                 break;
4146         default:
4147                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4148                 break;
4149         }
4150
4151         if (response & DP_TEST_ACK)
4152                 intel_dp->compliance.test_type = request;
4153
4154 update_status:
4155         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4156         if (status <= 0)
4157                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4158 }
4159
4160 static int
4161 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4162 {
4163         bool bret;
4164
4165         if (intel_dp->is_mst) {
4166                 u8 esi[16] = { 0 };
4167                 int ret = 0;
4168                 int retry;
4169                 bool handled;
4170                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4171 go_again:
4172                 if (bret == true) {
4173
4174                         /* check link status - esi[10] = 0x200c */
4175                         if (intel_dp->active_mst_links &&
4176                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4177                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4178                                 intel_dp_start_link_train(intel_dp);
4179                                 intel_dp_stop_link_train(intel_dp);
4180                         }
4181
4182                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4183                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4184
4185                         if (handled) {
4186                                 for (retry = 0; retry < 3; retry++) {
4187                                         int wret;
4188                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4189                                                                  DP_SINK_COUNT_ESI+1,
4190                                                                  &esi[1], 3);
4191                                         if (wret == 3) {
4192                                                 break;
4193                                         }
4194                                 }
4195
4196                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4197                                 if (bret == true) {
4198                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4199                                         goto go_again;
4200                                 }
4201                         } else
4202                                 ret = 0;
4203
4204                         return ret;
4205                 } else {
4206                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4207                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4208                         intel_dp->is_mst = false;
4209                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4210                         /* send a hotplug event */
4211                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4212                 }
4213         }
4214         return -EINVAL;
4215 }
4216
4217 static void
4218 intel_dp_retrain_link(struct intel_dp *intel_dp)
4219 {
4220         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4221         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4222         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4223
4224         /* Suppress underruns caused by re-training */
4225         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4226         if (crtc->config->has_pch_encoder)
4227                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4228                                                       intel_crtc_pch_transcoder(crtc), false);
4229
4230         intel_dp_start_link_train(intel_dp);
4231         intel_dp_stop_link_train(intel_dp);
4232
4233         /* Keep underrun reporting disabled until things are stable */
4234         intel_wait_for_vblank(dev_priv, crtc->pipe);
4235
4236         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4237         if (crtc->config->has_pch_encoder)
4238                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4239                                                       intel_crtc_pch_transcoder(crtc), true);
4240 }
4241
4242 static void
4243 intel_dp_check_link_status(struct intel_dp *intel_dp)
4244 {
4245         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4246         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4247         u8 link_status[DP_LINK_STATUS_SIZE];
4248
4249         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4250
4251         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4252                 DRM_ERROR("Failed to get link status\n");
4253                 return;
4254         }
4255
4256         if (!intel_encoder->base.crtc)
4257                 return;
4258
4259         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4260                 return;
4261
4262         /*
4263          * Validate the cached values of intel_dp->link_rate and
4264          * intel_dp->lane_count before attempting to retrain.
4265          */
4266         if (!intel_dp_link_params_valid(intel_dp))
4267                 return;
4268
4269         /* Retrain if Channel EQ or CR not ok */
4270         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4271                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4272                               intel_encoder->base.name);
4273
4274                 intel_dp_retrain_link(intel_dp);
4275         }
4276 }
4277
4278 /*
4279  * According to DP spec
4280  * 5.1.2:
4281  *  1. Read DPCD
4282  *  2. Configure link according to Receiver Capabilities
4283  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4284  *  4. Check link status on receipt of hot-plug interrupt
4285  *
4286  * intel_dp_short_pulse -  handles short pulse interrupts
4287  * when full detection is not required.
4288  * Returns %true if short pulse is handled and full detection
4289  * is NOT required and %false otherwise.
4290  */
4291 static bool
4292 intel_dp_short_pulse(struct intel_dp *intel_dp)
4293 {
4294         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4295         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4296         u8 sink_irq_vector = 0;
4297         u8 old_sink_count = intel_dp->sink_count;
4298         bool ret;
4299
4300         /*
4301          * Clearing compliance test variables to allow capturing
4302          * of values for next automated test request.
4303          */
4304         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4305
4306         /*
4307          * Now read the DPCD to see if it's actually running
4308          * If the current value of sink count doesn't match with
4309          * the value that was stored earlier or dpcd read failed
4310          * we need to do full detection
4311          */
4312         ret = intel_dp_get_dpcd(intel_dp);
4313
4314         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4315                 /* No need to proceed if we are going to do full detect */
4316                 return false;
4317         }
4318
4319         /* Try to read the source of the interrupt */
4320         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4321             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4322             sink_irq_vector != 0) {
4323                 /* Clear interrupt source */
4324                 drm_dp_dpcd_writeb(&intel_dp->aux,
4325                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4326                                    sink_irq_vector);
4327
4328                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4329                         intel_dp_handle_test_request(intel_dp);
4330                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4331                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4332         }
4333
4334         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4335         intel_dp_check_link_status(intel_dp);
4336         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4337         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4338                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4339                 /* Send a Hotplug Uevent to userspace to start modeset */
4340                 drm_kms_helper_hotplug_event(intel_encoder->base.dev);
4341         }
4342
4343         return true;
4344 }
4345
4346 /* XXX this is probably wrong for multiple downstream ports */
4347 static enum drm_connector_status
4348 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4349 {
4350         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4351         uint8_t *dpcd = intel_dp->dpcd;
4352         uint8_t type;
4353
4354         if (lspcon->active)
4355                 lspcon_resume(lspcon);
4356
4357         if (!intel_dp_get_dpcd(intel_dp))
4358                 return connector_status_disconnected;
4359
4360         if (is_edp(intel_dp))
4361                 return connector_status_connected;
4362
4363         /* if there's no downstream port, we're done */
4364         if (!drm_dp_is_branch(dpcd))
4365                 return connector_status_connected;
4366
4367         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4368         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4369             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4370
4371                 return intel_dp->sink_count ?
4372                 connector_status_connected : connector_status_disconnected;
4373         }
4374
4375         if (intel_dp_can_mst(intel_dp))
4376                 return connector_status_connected;
4377
4378         /* If no HPD, poke DDC gently */
4379         if (drm_probe_ddc(&intel_dp->aux.ddc))
4380                 return connector_status_connected;
4381
4382         /* Well we tried, say unknown for unreliable port types */
4383         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4384                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4385                 if (type == DP_DS_PORT_TYPE_VGA ||
4386                     type == DP_DS_PORT_TYPE_NON_EDID)
4387                         return connector_status_unknown;
4388         } else {
4389                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4390                         DP_DWN_STRM_PORT_TYPE_MASK;
4391                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4392                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4393                         return connector_status_unknown;
4394         }
4395
4396         /* Anything else is out of spec, warn and ignore */
4397         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4398         return connector_status_disconnected;
4399 }
4400
4401 static enum drm_connector_status
4402 edp_detect(struct intel_dp *intel_dp)
4403 {
4404         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4405         struct drm_i915_private *dev_priv = to_i915(dev);
4406         enum drm_connector_status status;
4407
4408         status = intel_panel_detect(dev_priv);
4409         if (status == connector_status_unknown)
4410                 status = connector_status_connected;
4411
4412         return status;
4413 }
4414
4415 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4416                                        struct intel_digital_port *port)
4417 {
4418         u32 bit;
4419
4420         switch (port->port) {
4421         case PORT_A:
4422                 return true;
4423         case PORT_B:
4424                 bit = SDE_PORTB_HOTPLUG;
4425                 break;
4426         case PORT_C:
4427                 bit = SDE_PORTC_HOTPLUG;
4428                 break;
4429         case PORT_D:
4430                 bit = SDE_PORTD_HOTPLUG;
4431                 break;
4432         default:
4433                 MISSING_CASE(port->port);
4434                 return false;
4435         }
4436
4437         return I915_READ(SDEISR) & bit;
4438 }
4439
4440 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4441                                        struct intel_digital_port *port)
4442 {
4443         u32 bit;
4444
4445         switch (port->port) {
4446         case PORT_A:
4447                 return true;
4448         case PORT_B:
4449                 bit = SDE_PORTB_HOTPLUG_CPT;
4450                 break;
4451         case PORT_C:
4452                 bit = SDE_PORTC_HOTPLUG_CPT;
4453                 break;
4454         case PORT_D:
4455                 bit = SDE_PORTD_HOTPLUG_CPT;
4456                 break;
4457         case PORT_E:
4458                 bit = SDE_PORTE_HOTPLUG_SPT;
4459                 break;
4460         default:
4461                 MISSING_CASE(port->port);
4462                 return false;
4463         }
4464
4465         return I915_READ(SDEISR) & bit;
4466 }
4467
4468 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4469                                        struct intel_digital_port *port)
4470 {
4471         u32 bit;
4472
4473         switch (port->port) {
4474         case PORT_B:
4475                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4476                 break;
4477         case PORT_C:
4478                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4479                 break;
4480         case PORT_D:
4481                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4482                 break;
4483         default:
4484                 MISSING_CASE(port->port);
4485                 return false;
4486         }
4487
4488         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4489 }
4490
4491 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4492                                         struct intel_digital_port *port)
4493 {
4494         u32 bit;
4495
4496         switch (port->port) {
4497         case PORT_B:
4498                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4499                 break;
4500         case PORT_C:
4501                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4502                 break;
4503         case PORT_D:
4504                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4505                 break;
4506         default:
4507                 MISSING_CASE(port->port);
4508                 return false;
4509         }
4510
4511         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4512 }
4513
4514 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4515                                        struct intel_digital_port *intel_dig_port)
4516 {
4517         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4518         enum port port;
4519         u32 bit;
4520
4521         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4522         switch (port) {
4523         case PORT_A:
4524                 bit = BXT_DE_PORT_HP_DDIA;
4525                 break;
4526         case PORT_B:
4527                 bit = BXT_DE_PORT_HP_DDIB;
4528                 break;
4529         case PORT_C:
4530                 bit = BXT_DE_PORT_HP_DDIC;
4531                 break;
4532         default:
4533                 MISSING_CASE(port);
4534                 return false;
4535         }
4536
4537         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4538 }
4539
4540 /*
4541  * intel_digital_port_connected - is the specified port connected?
4542  * @dev_priv: i915 private structure
4543  * @port: the port to test
4544  *
4545  * Return %true if @port is connected, %false otherwise.
4546  */
4547 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4548                                   struct intel_digital_port *port)
4549 {
4550         if (HAS_PCH_IBX(dev_priv))
4551                 return ibx_digital_port_connected(dev_priv, port);
4552         else if (HAS_PCH_SPLIT(dev_priv))
4553                 return cpt_digital_port_connected(dev_priv, port);
4554         else if (IS_GEN9_LP(dev_priv))
4555                 return bxt_digital_port_connected(dev_priv, port);
4556         else if (IS_GM45(dev_priv))
4557                 return gm45_digital_port_connected(dev_priv, port);
4558         else
4559                 return g4x_digital_port_connected(dev_priv, port);
4560 }
4561
4562 static struct edid *
4563 intel_dp_get_edid(struct intel_dp *intel_dp)
4564 {
4565         struct intel_connector *intel_connector = intel_dp->attached_connector;
4566
4567         /* use cached edid if we have one */
4568         if (intel_connector->edid) {
4569                 /* invalid edid */
4570                 if (IS_ERR(intel_connector->edid))
4571                         return NULL;
4572
4573                 return drm_edid_duplicate(intel_connector->edid);
4574         } else
4575                 return drm_get_edid(&intel_connector->base,
4576                                     &intel_dp->aux.ddc);
4577 }
4578
4579 static void
4580 intel_dp_set_edid(struct intel_dp *intel_dp)
4581 {
4582         struct intel_connector *intel_connector = intel_dp->attached_connector;
4583         struct edid *edid;
4584
4585         intel_dp_unset_edid(intel_dp);
4586         edid = intel_dp_get_edid(intel_dp);
4587         intel_connector->detect_edid = edid;
4588
4589         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4590 }
4591
4592 static void
4593 intel_dp_unset_edid(struct intel_dp *intel_dp)
4594 {
4595         struct intel_connector *intel_connector = intel_dp->attached_connector;
4596
4597         kfree(intel_connector->detect_edid);
4598         intel_connector->detect_edid = NULL;
4599
4600         intel_dp->has_audio = false;
4601 }
4602
4603 static int
4604 intel_dp_long_pulse(struct intel_connector *intel_connector)
4605 {
4606         struct drm_connector *connector = &intel_connector->base;
4607         struct intel_dp *intel_dp = intel_attached_dp(connector);
4608         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4609         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4610         struct drm_device *dev = connector->dev;
4611         enum drm_connector_status status;
4612         u8 sink_irq_vector = 0;
4613
4614         WARN_ON(!drm_modeset_is_locked(&connector->dev->mode_config.connection_mutex));
4615
4616         intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
4617
4618         /* Can't disconnect eDP, but you can close the lid... */
4619         if (is_edp(intel_dp))
4620                 status = edp_detect(intel_dp);
4621         else if (intel_digital_port_connected(to_i915(dev),
4622                                               dp_to_dig_port(intel_dp)))
4623                 status = intel_dp_detect_dpcd(intel_dp);
4624         else
4625                 status = connector_status_disconnected;
4626
4627         if (status == connector_status_disconnected) {
4628                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4629
4630                 if (intel_dp->is_mst) {
4631                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4632                                       intel_dp->is_mst,
4633                                       intel_dp->mst_mgr.mst_state);
4634                         intel_dp->is_mst = false;
4635                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4636                                                         intel_dp->is_mst);
4637                 }
4638
4639                 goto out;
4640         }
4641
4642         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4643                 intel_encoder->type = INTEL_OUTPUT_DP;
4644
4645         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4646                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
4647                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4648
4649         if (intel_dp->reset_link_params) {
4650                 /* Initial max link lane count */
4651                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4652
4653                 /* Initial max link rate */
4654                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4655
4656                 intel_dp->reset_link_params = false;
4657         }
4658
4659         intel_dp_print_rates(intel_dp);
4660
4661         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4662                          drm_dp_is_branch(intel_dp->dpcd));
4663
4664         intel_dp_configure_mst(intel_dp);
4665
4666         if (intel_dp->is_mst) {
4667                 /*
4668                  * If we are in MST mode then this connector
4669                  * won't appear connected or have anything
4670                  * with EDID on it
4671                  */
4672                 status = connector_status_disconnected;
4673                 goto out;
4674         } else {
4675                 /*
4676                  * If display is now connected check links status,
4677                  * there has been known issues of link loss triggerring
4678                  * long pulse.
4679                  *
4680                  * Some sinks (eg. ASUS PB287Q) seem to perform some
4681                  * weird HPD ping pong during modesets. So we can apparently
4682                  * end up with HPD going low during a modeset, and then
4683                  * going back up soon after. And once that happens we must
4684                  * retrain the link to get a picture. That's in case no
4685                  * userspace component reacted to intermittent HPD dip.
4686                  */
4687                 intel_dp_check_link_status(intel_dp);
4688         }
4689
4690         /*
4691          * Clearing NACK and defer counts to get their exact values
4692          * while reading EDID which are required by Compliance tests
4693          * 4.2.2.4 and 4.2.2.5
4694          */
4695         intel_dp->aux.i2c_nack_count = 0;
4696         intel_dp->aux.i2c_defer_count = 0;
4697
4698         intel_dp_set_edid(intel_dp);
4699         if (is_edp(intel_dp) || intel_connector->detect_edid)
4700                 status = connector_status_connected;
4701         intel_dp->detect_done = true;
4702
4703         /* Try to read the source of the interrupt */
4704         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4705             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4706             sink_irq_vector != 0) {
4707                 /* Clear interrupt source */
4708                 drm_dp_dpcd_writeb(&intel_dp->aux,
4709                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4710                                    sink_irq_vector);
4711
4712                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4713                         intel_dp_handle_test_request(intel_dp);
4714                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4715                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4716         }
4717
4718 out:
4719         if (status != connector_status_connected && !intel_dp->is_mst)
4720                 intel_dp_unset_edid(intel_dp);
4721
4722         intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain);
4723         return status;
4724 }
4725
4726 static int
4727 intel_dp_detect(struct drm_connector *connector,
4728                 struct drm_modeset_acquire_ctx *ctx,
4729                 bool force)
4730 {
4731         struct intel_dp *intel_dp = intel_attached_dp(connector);
4732         int status = connector->status;
4733
4734         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4735                       connector->base.id, connector->name);
4736
4737         /* If full detect is not performed yet, do a full detect */
4738         if (!intel_dp->detect_done)
4739                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4740
4741         intel_dp->detect_done = false;
4742
4743         return status;
4744 }
4745
4746 static void
4747 intel_dp_force(struct drm_connector *connector)
4748 {
4749         struct intel_dp *intel_dp = intel_attached_dp(connector);
4750         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4751         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4752
4753         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4754                       connector->base.id, connector->name);
4755         intel_dp_unset_edid(intel_dp);
4756
4757         if (connector->status != connector_status_connected)
4758                 return;
4759
4760         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4761
4762         intel_dp_set_edid(intel_dp);
4763
4764         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4765
4766         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4767                 intel_encoder->type = INTEL_OUTPUT_DP;
4768 }
4769
4770 static int intel_dp_get_modes(struct drm_connector *connector)
4771 {
4772         struct intel_connector *intel_connector = to_intel_connector(connector);
4773         struct edid *edid;
4774
4775         edid = intel_connector->detect_edid;
4776         if (edid) {
4777                 int ret = intel_connector_update_modes(connector, edid);
4778                 if (ret)
4779                         return ret;
4780         }
4781
4782         /* if eDP has no EDID, fall back to fixed mode */
4783         if (is_edp(intel_attached_dp(connector)) &&
4784             intel_connector->panel.fixed_mode) {
4785                 struct drm_display_mode *mode;
4786
4787                 mode = drm_mode_duplicate(connector->dev,
4788                                           intel_connector->panel.fixed_mode);
4789                 if (mode) {
4790                         drm_mode_probed_add(connector, mode);
4791                         return 1;
4792                 }
4793         }
4794
4795         return 0;
4796 }
4797
4798 static int
4799 intel_dp_connector_register(struct drm_connector *connector)
4800 {
4801         struct intel_dp *intel_dp = intel_attached_dp(connector);
4802         int ret;
4803
4804         ret = intel_connector_register(connector);
4805         if (ret)
4806                 return ret;
4807
4808         i915_debugfs_connector_add(connector);
4809
4810         DRM_DEBUG_KMS("registering %s bus for %s\n",
4811                       intel_dp->aux.name, connector->kdev->kobj.name);
4812
4813         intel_dp->aux.dev = connector->kdev;
4814         return drm_dp_aux_register(&intel_dp->aux);
4815 }
4816
4817 static void
4818 intel_dp_connector_unregister(struct drm_connector *connector)
4819 {
4820         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4821         intel_connector_unregister(connector);
4822 }
4823
4824 static void
4825 intel_dp_connector_destroy(struct drm_connector *connector)
4826 {
4827         struct intel_connector *intel_connector = to_intel_connector(connector);
4828
4829         kfree(intel_connector->detect_edid);
4830
4831         if (!IS_ERR_OR_NULL(intel_connector->edid))
4832                 kfree(intel_connector->edid);
4833
4834         /* Can't call is_edp() since the encoder may have been destroyed
4835          * already. */
4836         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4837                 intel_panel_fini(&intel_connector->panel);
4838
4839         drm_connector_cleanup(connector);
4840         kfree(connector);
4841 }
4842
4843 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4844 {
4845         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4846         struct intel_dp *intel_dp = &intel_dig_port->dp;
4847
4848         intel_dp_mst_encoder_cleanup(intel_dig_port);
4849         if (is_edp(intel_dp)) {
4850                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4851                 /*
4852                  * vdd might still be enabled do to the delayed vdd off.
4853                  * Make sure vdd is actually turned off here.
4854                  */
4855                 pps_lock(intel_dp);
4856                 edp_panel_vdd_off_sync(intel_dp);
4857                 pps_unlock(intel_dp);
4858
4859                 if (intel_dp->edp_notifier.notifier_call) {
4860                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4861                         intel_dp->edp_notifier.notifier_call = NULL;
4862                 }
4863         }
4864
4865         intel_dp_aux_fini(intel_dp);
4866
4867         drm_encoder_cleanup(encoder);
4868         kfree(intel_dig_port);
4869 }
4870
4871 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4872 {
4873         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4874
4875         if (!is_edp(intel_dp))
4876                 return;
4877
4878         /*
4879          * vdd might still be enabled do to the delayed vdd off.
4880          * Make sure vdd is actually turned off here.
4881          */
4882         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4883         pps_lock(intel_dp);
4884         edp_panel_vdd_off_sync(intel_dp);
4885         pps_unlock(intel_dp);
4886 }
4887
4888 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4889 {
4890         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4891         struct drm_device *dev = intel_dig_port->base.base.dev;
4892         struct drm_i915_private *dev_priv = to_i915(dev);
4893
4894         lockdep_assert_held(&dev_priv->pps_mutex);
4895
4896         if (!edp_have_panel_vdd(intel_dp))
4897                 return;
4898
4899         /*
4900          * The VDD bit needs a power domain reference, so if the bit is
4901          * already enabled when we boot or resume, grab this reference and
4902          * schedule a vdd off, so we don't hold on to the reference
4903          * indefinitely.
4904          */
4905         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4906         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4907
4908         edp_panel_vdd_schedule_off(intel_dp);
4909 }
4910
4911 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
4912 {
4913         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4914
4915         if ((intel_dp->DP & DP_PORT_EN) == 0)
4916                 return INVALID_PIPE;
4917
4918         if (IS_CHERRYVIEW(dev_priv))
4919                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
4920         else
4921                 return PORT_TO_PIPE(intel_dp->DP);
4922 }
4923
4924 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4925 {
4926         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4927         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4928         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4929
4930         if (!HAS_DDI(dev_priv))
4931                 intel_dp->DP = I915_READ(intel_dp->output_reg);
4932
4933         if (lspcon->active)
4934                 lspcon_resume(lspcon);
4935
4936         intel_dp->reset_link_params = true;
4937
4938         pps_lock(intel_dp);
4939
4940         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4941                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
4942
4943         if (is_edp(intel_dp)) {
4944                 /* Reinit the power sequencer, in case BIOS did something with it. */
4945                 intel_dp_pps_init(encoder->dev, intel_dp);
4946                 intel_edp_panel_vdd_sanitize(intel_dp);
4947         }
4948
4949         pps_unlock(intel_dp);
4950 }
4951
4952 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4953         .dpms = drm_atomic_helper_connector_dpms,
4954         .force = intel_dp_force,
4955         .fill_modes = drm_helper_probe_single_connector_modes,
4956         .set_property = drm_atomic_helper_connector_set_property,
4957         .atomic_get_property = intel_digital_connector_atomic_get_property,
4958         .atomic_set_property = intel_digital_connector_atomic_set_property,
4959         .late_register = intel_dp_connector_register,
4960         .early_unregister = intel_dp_connector_unregister,
4961         .destroy = intel_dp_connector_destroy,
4962         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4963         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
4964 };
4965
4966 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4967         .detect_ctx = intel_dp_detect,
4968         .get_modes = intel_dp_get_modes,
4969         .mode_valid = intel_dp_mode_valid,
4970         .atomic_check = intel_digital_connector_atomic_check,
4971 };
4972
4973 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4974         .reset = intel_dp_encoder_reset,
4975         .destroy = intel_dp_encoder_destroy,
4976 };
4977
4978 enum irqreturn
4979 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4980 {
4981         struct intel_dp *intel_dp = &intel_dig_port->dp;
4982         struct drm_device *dev = intel_dig_port->base.base.dev;
4983         struct drm_i915_private *dev_priv = to_i915(dev);
4984         enum irqreturn ret = IRQ_NONE;
4985
4986         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4987             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4988                 intel_dig_port->base.type = INTEL_OUTPUT_DP;
4989
4990         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4991                 /*
4992                  * vdd off can generate a long pulse on eDP which
4993                  * would require vdd on to handle it, and thus we
4994                  * would end up in an endless cycle of
4995                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4996                  */
4997                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4998                               port_name(intel_dig_port->port));
4999                 return IRQ_HANDLED;
5000         }
5001
5002         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5003                       port_name(intel_dig_port->port),
5004                       long_hpd ? "long" : "short");
5005
5006         if (long_hpd) {
5007                 intel_dp->reset_link_params = true;
5008                 intel_dp->detect_done = false;
5009                 return IRQ_NONE;
5010         }
5011
5012         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5013
5014         if (intel_dp->is_mst) {
5015                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5016                         /*
5017                          * If we were in MST mode, and device is not
5018                          * there, get out of MST mode
5019                          */
5020                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5021                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5022                         intel_dp->is_mst = false;
5023                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5024                                                         intel_dp->is_mst);
5025                         intel_dp->detect_done = false;
5026                         goto put_power;
5027                 }
5028         }
5029
5030         if (!intel_dp->is_mst) {
5031                 if (!intel_dp_short_pulse(intel_dp)) {
5032                         intel_dp->detect_done = false;
5033                         goto put_power;
5034                 }
5035         }
5036
5037         ret = IRQ_HANDLED;
5038
5039 put_power:
5040         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5041
5042         return ret;
5043 }
5044
5045 /* check the VBT to see whether the eDP is on another port */
5046 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
5047 {
5048         /*
5049          * eDP not supported on g4x. so bail out early just
5050          * for a bit extra safety in case the VBT is bonkers.
5051          */
5052         if (INTEL_GEN(dev_priv) < 5)
5053                 return false;
5054
5055         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5056                 return true;
5057
5058         return intel_bios_is_port_edp(dev_priv, port);
5059 }
5060
5061 static void
5062 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5063 {
5064         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5065
5066         intel_attach_force_audio_property(connector);
5067         intel_attach_broadcast_rgb_property(connector);
5068
5069         if (is_edp(intel_dp)) {
5070                 u32 allowed_scalers;
5071
5072                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5073                 if (!HAS_GMCH_DISPLAY(dev_priv))
5074                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5075
5076                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5077
5078                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5079
5080         }
5081 }
5082
5083 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5084 {
5085         intel_dp->panel_power_off_time = ktime_get_boottime();
5086         intel_dp->last_power_on = jiffies;
5087         intel_dp->last_backlight_off = jiffies;
5088 }
5089
5090 static void
5091 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
5092                            struct intel_dp *intel_dp, struct edp_power_seq *seq)
5093 {
5094         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5095         struct pps_registers regs;
5096
5097         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5098
5099         /* Workaround: Need to write PP_CONTROL with the unlock key as
5100          * the very first thing. */
5101         pp_ctl = ironlake_get_pp_control(intel_dp);
5102
5103         pp_on = I915_READ(regs.pp_on);
5104         pp_off = I915_READ(regs.pp_off);
5105         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
5106                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5107                 pp_div = I915_READ(regs.pp_div);
5108         }
5109
5110         /* Pull timing values out of registers */
5111         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5112                      PANEL_POWER_UP_DELAY_SHIFT;
5113
5114         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5115                   PANEL_LIGHT_ON_DELAY_SHIFT;
5116
5117         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5118                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5119
5120         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5121                    PANEL_POWER_DOWN_DELAY_SHIFT;
5122
5123         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5124                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5125                         BXT_POWER_CYCLE_DELAY_SHIFT;
5126                 if (tmp > 0)
5127                         seq->t11_t12 = (tmp - 1) * 1000;
5128                 else
5129                         seq->t11_t12 = 0;
5130         } else {
5131                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5132                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5133         }
5134 }
5135
5136 static void
5137 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5138 {
5139         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5140                       state_name,
5141                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5142 }
5143
5144 static void
5145 intel_pps_verify_state(struct drm_i915_private *dev_priv,
5146                        struct intel_dp *intel_dp)
5147 {
5148         struct edp_power_seq hw;
5149         struct edp_power_seq *sw = &intel_dp->pps_delays;
5150
5151         intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
5152
5153         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5154             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5155                 DRM_ERROR("PPS state mismatch\n");
5156                 intel_pps_dump_state("sw", sw);
5157                 intel_pps_dump_state("hw", &hw);
5158         }
5159 }
5160
5161 static void
5162 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5163                                     struct intel_dp *intel_dp)
5164 {
5165         struct drm_i915_private *dev_priv = to_i915(dev);
5166         struct edp_power_seq cur, vbt, spec,
5167                 *final = &intel_dp->pps_delays;
5168
5169         lockdep_assert_held(&dev_priv->pps_mutex);
5170
5171         /* already initialized? */
5172         if (final->t11_t12 != 0)
5173                 return;
5174
5175         intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5176
5177         intel_pps_dump_state("cur", &cur);
5178
5179         vbt = dev_priv->vbt.edp.pps;
5180
5181         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5182          * our hw here, which are all in 100usec. */
5183         spec.t1_t3 = 210 * 10;
5184         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5185         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5186         spec.t10 = 500 * 10;
5187         /* This one is special and actually in units of 100ms, but zero
5188          * based in the hw (so we need to add 100 ms). But the sw vbt
5189          * table multiplies it with 1000 to make it in units of 100usec,
5190          * too. */
5191         spec.t11_t12 = (510 + 100) * 10;
5192
5193         intel_pps_dump_state("vbt", &vbt);
5194
5195         /* Use the max of the register settings and vbt. If both are
5196          * unset, fall back to the spec limits. */
5197 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5198                                        spec.field : \
5199                                        max(cur.field, vbt.field))
5200         assign_final(t1_t3);
5201         assign_final(t8);
5202         assign_final(t9);
5203         assign_final(t10);
5204         assign_final(t11_t12);
5205 #undef assign_final
5206
5207 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5208         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5209         intel_dp->backlight_on_delay = get_delay(t8);
5210         intel_dp->backlight_off_delay = get_delay(t9);
5211         intel_dp->panel_power_down_delay = get_delay(t10);
5212         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5213 #undef get_delay
5214
5215         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5216                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5217                       intel_dp->panel_power_cycle_delay);
5218
5219         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5220                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5221
5222         /*
5223          * We override the HW backlight delays to 1 because we do manual waits
5224          * on them. For T8, even BSpec recommends doing it. For T9, if we
5225          * don't do this, we'll end up waiting for the backlight off delay
5226          * twice: once when we do the manual sleep, and once when we disable
5227          * the panel and wait for the PP_STATUS bit to become zero.
5228          */
5229         final->t8 = 1;
5230         final->t9 = 1;
5231 }
5232
5233 static void
5234 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5235                                               struct intel_dp *intel_dp,
5236                                               bool force_disable_vdd)
5237 {
5238         struct drm_i915_private *dev_priv = to_i915(dev);
5239         u32 pp_on, pp_off, pp_div, port_sel = 0;
5240         int div = dev_priv->rawclk_freq / 1000;
5241         struct pps_registers regs;
5242         enum port port = dp_to_dig_port(intel_dp)->port;
5243         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5244
5245         lockdep_assert_held(&dev_priv->pps_mutex);
5246
5247         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5248
5249         /*
5250          * On some VLV machines the BIOS can leave the VDD
5251          * enabled even on power seqeuencers which aren't
5252          * hooked up to any port. This would mess up the
5253          * power domain tracking the first time we pick
5254          * one of these power sequencers for use since
5255          * edp_panel_vdd_on() would notice that the VDD was
5256          * already on and therefore wouldn't grab the power
5257          * domain reference. Disable VDD first to avoid this.
5258          * This also avoids spuriously turning the VDD on as
5259          * soon as the new power seqeuencer gets initialized.
5260          */
5261         if (force_disable_vdd) {
5262                 u32 pp = ironlake_get_pp_control(intel_dp);
5263
5264                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5265
5266                 if (pp & EDP_FORCE_VDD)
5267                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5268
5269                 pp &= ~EDP_FORCE_VDD;
5270
5271                 I915_WRITE(regs.pp_ctrl, pp);
5272         }
5273
5274         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5275                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5276         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5277                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5278         /* Compute the divisor for the pp clock, simply match the Bspec
5279          * formula. */
5280         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5281                 pp_div = I915_READ(regs.pp_ctrl);
5282                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5283                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5284                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5285         } else {
5286                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5287                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5288                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5289         }
5290
5291         /* Haswell doesn't have any port selection bits for the panel
5292          * power sequencer any more. */
5293         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5294                 port_sel = PANEL_PORT_SELECT_VLV(port);
5295         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5296                 if (port == PORT_A)
5297                         port_sel = PANEL_PORT_SELECT_DPA;
5298                 else
5299                         port_sel = PANEL_PORT_SELECT_DPD;
5300         }
5301
5302         pp_on |= port_sel;
5303
5304         I915_WRITE(regs.pp_on, pp_on);
5305         I915_WRITE(regs.pp_off, pp_off);
5306         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
5307                 I915_WRITE(regs.pp_ctrl, pp_div);
5308         else
5309                 I915_WRITE(regs.pp_div, pp_div);
5310
5311         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5312                       I915_READ(regs.pp_on),
5313                       I915_READ(regs.pp_off),
5314                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
5315                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5316                       I915_READ(regs.pp_div));
5317 }
5318
5319 static void intel_dp_pps_init(struct drm_device *dev,
5320                               struct intel_dp *intel_dp)
5321 {
5322         struct drm_i915_private *dev_priv = to_i915(dev);
5323
5324         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5325                 vlv_initial_power_sequencer_setup(intel_dp);
5326         } else {
5327                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5328                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5329         }
5330 }
5331
5332 /**
5333  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5334  * @dev_priv: i915 device
5335  * @crtc_state: a pointer to the active intel_crtc_state
5336  * @refresh_rate: RR to be programmed
5337  *
5338  * This function gets called when refresh rate (RR) has to be changed from
5339  * one frequency to another. Switches can be between high and low RR
5340  * supported by the panel or to any other RR based on media playback (in
5341  * this case, RR value needs to be passed from user space).
5342  *
5343  * The caller of this function needs to take a lock on dev_priv->drrs.
5344  */
5345 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5346                                     struct intel_crtc_state *crtc_state,
5347                                     int refresh_rate)
5348 {
5349         struct intel_encoder *encoder;
5350         struct intel_digital_port *dig_port = NULL;
5351         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5353         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5354
5355         if (refresh_rate <= 0) {
5356                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5357                 return;
5358         }
5359
5360         if (intel_dp == NULL) {
5361                 DRM_DEBUG_KMS("DRRS not supported.\n");
5362                 return;
5363         }
5364
5365         /*
5366          * FIXME: This needs proper synchronization with psr state for some
5367          * platforms that cannot have PSR and DRRS enabled at the same time.
5368          */
5369
5370         dig_port = dp_to_dig_port(intel_dp);
5371         encoder = &dig_port->base;
5372         intel_crtc = to_intel_crtc(encoder->base.crtc);
5373
5374         if (!intel_crtc) {
5375                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5376                 return;
5377         }
5378
5379         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5380                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5381                 return;
5382         }
5383
5384         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5385                         refresh_rate)
5386                 index = DRRS_LOW_RR;
5387
5388         if (index == dev_priv->drrs.refresh_rate_type) {
5389                 DRM_DEBUG_KMS(
5390                         "DRRS requested for previously set RR...ignoring\n");
5391                 return;
5392         }
5393
5394         if (!crtc_state->base.active) {
5395                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5396                 return;
5397         }
5398
5399         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5400                 switch (index) {
5401                 case DRRS_HIGH_RR:
5402                         intel_dp_set_m_n(intel_crtc, M1_N1);
5403                         break;
5404                 case DRRS_LOW_RR:
5405                         intel_dp_set_m_n(intel_crtc, M2_N2);
5406                         break;
5407                 case DRRS_MAX_RR:
5408                 default:
5409                         DRM_ERROR("Unsupported refreshrate type\n");
5410                 }
5411         } else if (INTEL_GEN(dev_priv) > 6) {
5412                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5413                 u32 val;
5414
5415                 val = I915_READ(reg);
5416                 if (index > DRRS_HIGH_RR) {
5417                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5418                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5419                         else
5420                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5421                 } else {
5422                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5423                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5424                         else
5425                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5426                 }
5427                 I915_WRITE(reg, val);
5428         }
5429
5430         dev_priv->drrs.refresh_rate_type = index;
5431
5432         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5433 }
5434
5435 /**
5436  * intel_edp_drrs_enable - init drrs struct if supported
5437  * @intel_dp: DP struct
5438  * @crtc_state: A pointer to the active crtc state.
5439  *
5440  * Initializes frontbuffer_bits and drrs.dp
5441  */
5442 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5443                            struct intel_crtc_state *crtc_state)
5444 {
5445         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5446         struct drm_i915_private *dev_priv = to_i915(dev);
5447
5448         if (!crtc_state->has_drrs) {
5449                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5450                 return;
5451         }
5452
5453         mutex_lock(&dev_priv->drrs.mutex);
5454         if (WARN_ON(dev_priv->drrs.dp)) {
5455                 DRM_ERROR("DRRS already enabled\n");
5456                 goto unlock;
5457         }
5458
5459         dev_priv->drrs.busy_frontbuffer_bits = 0;
5460
5461         dev_priv->drrs.dp = intel_dp;
5462
5463 unlock:
5464         mutex_unlock(&dev_priv->drrs.mutex);
5465 }
5466
5467 /**
5468  * intel_edp_drrs_disable - Disable DRRS
5469  * @intel_dp: DP struct
5470  * @old_crtc_state: Pointer to old crtc_state.
5471  *
5472  */
5473 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5474                             struct intel_crtc_state *old_crtc_state)
5475 {
5476         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5477         struct drm_i915_private *dev_priv = to_i915(dev);
5478
5479         if (!old_crtc_state->has_drrs)
5480                 return;
5481
5482         mutex_lock(&dev_priv->drrs.mutex);
5483         if (!dev_priv->drrs.dp) {
5484                 mutex_unlock(&dev_priv->drrs.mutex);
5485                 return;
5486         }
5487
5488         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5489                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5490                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5491
5492         dev_priv->drrs.dp = NULL;
5493         mutex_unlock(&dev_priv->drrs.mutex);
5494
5495         cancel_delayed_work_sync(&dev_priv->drrs.work);
5496 }
5497
5498 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5499 {
5500         struct drm_i915_private *dev_priv =
5501                 container_of(work, typeof(*dev_priv), drrs.work.work);
5502         struct intel_dp *intel_dp;
5503
5504         mutex_lock(&dev_priv->drrs.mutex);
5505
5506         intel_dp = dev_priv->drrs.dp;
5507
5508         if (!intel_dp)
5509                 goto unlock;
5510
5511         /*
5512          * The delayed work can race with an invalidate hence we need to
5513          * recheck.
5514          */
5515
5516         if (dev_priv->drrs.busy_frontbuffer_bits)
5517                 goto unlock;
5518
5519         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5520                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5521
5522                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5523                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5524         }
5525
5526 unlock:
5527         mutex_unlock(&dev_priv->drrs.mutex);
5528 }
5529
5530 /**
5531  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5532  * @dev_priv: i915 device
5533  * @frontbuffer_bits: frontbuffer plane tracking bits
5534  *
5535  * This function gets called everytime rendering on the given planes start.
5536  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5537  *
5538  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5539  */
5540 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5541                                unsigned int frontbuffer_bits)
5542 {
5543         struct drm_crtc *crtc;
5544         enum pipe pipe;
5545
5546         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5547                 return;
5548
5549         cancel_delayed_work(&dev_priv->drrs.work);
5550
5551         mutex_lock(&dev_priv->drrs.mutex);
5552         if (!dev_priv->drrs.dp) {
5553                 mutex_unlock(&dev_priv->drrs.mutex);
5554                 return;
5555         }
5556
5557         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5558         pipe = to_intel_crtc(crtc)->pipe;
5559
5560         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5561         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5562
5563         /* invalidate means busy screen hence upclock */
5564         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5565                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5566                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5567
5568         mutex_unlock(&dev_priv->drrs.mutex);
5569 }
5570
5571 /**
5572  * intel_edp_drrs_flush - Restart Idleness DRRS
5573  * @dev_priv: i915 device
5574  * @frontbuffer_bits: frontbuffer plane tracking bits
5575  *
5576  * This function gets called every time rendering on the given planes has
5577  * completed or flip on a crtc is completed. So DRRS should be upclocked
5578  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5579  * if no other planes are dirty.
5580  *
5581  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5582  */
5583 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5584                           unsigned int frontbuffer_bits)
5585 {
5586         struct drm_crtc *crtc;
5587         enum pipe pipe;
5588
5589         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5590                 return;
5591
5592         cancel_delayed_work(&dev_priv->drrs.work);
5593
5594         mutex_lock(&dev_priv->drrs.mutex);
5595         if (!dev_priv->drrs.dp) {
5596                 mutex_unlock(&dev_priv->drrs.mutex);
5597                 return;
5598         }
5599
5600         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5601         pipe = to_intel_crtc(crtc)->pipe;
5602
5603         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5604         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5605
5606         /* flush means busy screen hence upclock */
5607         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5608                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5609                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5610
5611         /*
5612          * flush also means no more activity hence schedule downclock, if all
5613          * other fbs are quiescent too
5614          */
5615         if (!dev_priv->drrs.busy_frontbuffer_bits)
5616                 schedule_delayed_work(&dev_priv->drrs.work,
5617                                 msecs_to_jiffies(1000));
5618         mutex_unlock(&dev_priv->drrs.mutex);
5619 }
5620
5621 /**
5622  * DOC: Display Refresh Rate Switching (DRRS)
5623  *
5624  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5625  * which enables swtching between low and high refresh rates,
5626  * dynamically, based on the usage scenario. This feature is applicable
5627  * for internal panels.
5628  *
5629  * Indication that the panel supports DRRS is given by the panel EDID, which
5630  * would list multiple refresh rates for one resolution.
5631  *
5632  * DRRS is of 2 types - static and seamless.
5633  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5634  * (may appear as a blink on screen) and is used in dock-undock scenario.
5635  * Seamless DRRS involves changing RR without any visual effect to the user
5636  * and can be used during normal system usage. This is done by programming
5637  * certain registers.
5638  *
5639  * Support for static/seamless DRRS may be indicated in the VBT based on
5640  * inputs from the panel spec.
5641  *
5642  * DRRS saves power by switching to low RR based on usage scenarios.
5643  *
5644  * The implementation is based on frontbuffer tracking implementation.  When
5645  * there is a disturbance on the screen triggered by user activity or a periodic
5646  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5647  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5648  * made.
5649  *
5650  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5651  * and intel_edp_drrs_flush() are called.
5652  *
5653  * DRRS can be further extended to support other internal panels and also
5654  * the scenario of video playback wherein RR is set based on the rate
5655  * requested by userspace.
5656  */
5657
5658 /**
5659  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5660  * @intel_connector: eDP connector
5661  * @fixed_mode: preferred mode of panel
5662  *
5663  * This function is  called only once at driver load to initialize basic
5664  * DRRS stuff.
5665  *
5666  * Returns:
5667  * Downclock mode if panel supports it, else return NULL.
5668  * DRRS support is determined by the presence of downclock mode (apart
5669  * from VBT setting).
5670  */
5671 static struct drm_display_mode *
5672 intel_dp_drrs_init(struct intel_connector *intel_connector,
5673                 struct drm_display_mode *fixed_mode)
5674 {
5675         struct drm_connector *connector = &intel_connector->base;
5676         struct drm_device *dev = connector->dev;
5677         struct drm_i915_private *dev_priv = to_i915(dev);
5678         struct drm_display_mode *downclock_mode = NULL;
5679
5680         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5681         mutex_init(&dev_priv->drrs.mutex);
5682
5683         if (INTEL_GEN(dev_priv) <= 6) {
5684                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5685                 return NULL;
5686         }
5687
5688         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5689                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5690                 return NULL;
5691         }
5692
5693         downclock_mode = intel_find_panel_downclock
5694                                         (dev_priv, fixed_mode, connector);
5695
5696         if (!downclock_mode) {
5697                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5698                 return NULL;
5699         }
5700
5701         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5702
5703         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5704         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5705         return downclock_mode;
5706 }
5707
5708 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5709                                      struct intel_connector *intel_connector)
5710 {
5711         struct drm_connector *connector = &intel_connector->base;
5712         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5713         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5714         struct drm_device *dev = intel_encoder->base.dev;
5715         struct drm_i915_private *dev_priv = to_i915(dev);
5716         struct drm_display_mode *fixed_mode = NULL;
5717         struct drm_display_mode *downclock_mode = NULL;
5718         bool has_dpcd;
5719         struct drm_display_mode *scan;
5720         struct edid *edid;
5721         enum pipe pipe = INVALID_PIPE;
5722
5723         if (!is_edp(intel_dp))
5724                 return true;
5725
5726         /*
5727          * On IBX/CPT we may get here with LVDS already registered. Since the
5728          * driver uses the only internal power sequencer available for both
5729          * eDP and LVDS bail out early in this case to prevent interfering
5730          * with an already powered-on LVDS power sequencer.
5731          */
5732         if (intel_get_lvds_encoder(dev)) {
5733                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5734                 DRM_INFO("LVDS was detected, not registering eDP\n");
5735
5736                 return false;
5737         }
5738
5739         pps_lock(intel_dp);
5740
5741         intel_dp_init_panel_power_timestamps(intel_dp);
5742         intel_dp_pps_init(dev, intel_dp);
5743         intel_edp_panel_vdd_sanitize(intel_dp);
5744
5745         pps_unlock(intel_dp);
5746
5747         /* Cache DPCD and EDID for edp. */
5748         has_dpcd = intel_edp_init_dpcd(intel_dp);
5749
5750         if (!has_dpcd) {
5751                 /* if this fails, presume the device is a ghost */
5752                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5753                 goto out_vdd_off;
5754         }
5755
5756         mutex_lock(&dev->mode_config.mutex);
5757         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5758         if (edid) {
5759                 if (drm_add_edid_modes(connector, edid)) {
5760                         drm_mode_connector_update_edid_property(connector,
5761                                                                 edid);
5762                         drm_edid_to_eld(connector, edid);
5763                 } else {
5764                         kfree(edid);
5765                         edid = ERR_PTR(-EINVAL);
5766                 }
5767         } else {
5768                 edid = ERR_PTR(-ENOENT);
5769         }
5770         intel_connector->edid = edid;
5771
5772         /* prefer fixed mode from EDID if available */
5773         list_for_each_entry(scan, &connector->probed_modes, head) {
5774                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5775                         fixed_mode = drm_mode_duplicate(dev, scan);
5776                         downclock_mode = intel_dp_drrs_init(
5777                                                 intel_connector, fixed_mode);
5778                         break;
5779                 }
5780         }
5781
5782         /* fallback to VBT if available for eDP */
5783         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5784                 fixed_mode = drm_mode_duplicate(dev,
5785                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5786                 if (fixed_mode) {
5787                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5788                         connector->display_info.width_mm = fixed_mode->width_mm;
5789                         connector->display_info.height_mm = fixed_mode->height_mm;
5790                 }
5791         }
5792         mutex_unlock(&dev->mode_config.mutex);
5793
5794         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5795                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5796                 register_reboot_notifier(&intel_dp->edp_notifier);
5797
5798                 /*
5799                  * Figure out the current pipe for the initial backlight setup.
5800                  * If the current pipe isn't valid, try the PPS pipe, and if that
5801                  * fails just assume pipe A.
5802                  */
5803                 pipe = vlv_active_pipe(intel_dp);
5804
5805                 if (pipe != PIPE_A && pipe != PIPE_B)
5806                         pipe = intel_dp->pps_pipe;
5807
5808                 if (pipe != PIPE_A && pipe != PIPE_B)
5809                         pipe = PIPE_A;
5810
5811                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5812                               pipe_name(pipe));
5813         }
5814
5815         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5816         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5817         intel_panel_setup_backlight(connector, pipe);
5818
5819         return true;
5820
5821 out_vdd_off:
5822         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5823         /*
5824          * vdd might still be enabled do to the delayed vdd off.
5825          * Make sure vdd is actually turned off here.
5826          */
5827         pps_lock(intel_dp);
5828         edp_panel_vdd_off_sync(intel_dp);
5829         pps_unlock(intel_dp);
5830
5831         return false;
5832 }
5833
5834 /* Set up the hotplug pin and aux power domain. */
5835 static void
5836 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5837 {
5838         struct intel_encoder *encoder = &intel_dig_port->base;
5839         struct intel_dp *intel_dp = &intel_dig_port->dp;
5840
5841         switch (intel_dig_port->port) {
5842         case PORT_A:
5843                 encoder->hpd_pin = HPD_PORT_A;
5844                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
5845                 break;
5846         case PORT_B:
5847                 encoder->hpd_pin = HPD_PORT_B;
5848                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
5849                 break;
5850         case PORT_C:
5851                 encoder->hpd_pin = HPD_PORT_C;
5852                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
5853                 break;
5854         case PORT_D:
5855                 encoder->hpd_pin = HPD_PORT_D;
5856                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5857                 break;
5858         case PORT_E:
5859                 encoder->hpd_pin = HPD_PORT_E;
5860
5861                 /* FIXME: Check VBT for actual wiring of PORT E */
5862                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5863                 break;
5864         default:
5865                 MISSING_CASE(intel_dig_port->port);
5866         }
5867 }
5868
5869 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5870 {
5871         struct intel_connector *intel_connector;
5872         struct drm_connector *connector;
5873
5874         intel_connector = container_of(work, typeof(*intel_connector),
5875                                        modeset_retry_work);
5876         connector = &intel_connector->base;
5877         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5878                       connector->name);
5879
5880         /* Grab the locks before changing connector property*/
5881         mutex_lock(&connector->dev->mode_config.mutex);
5882         /* Set connector link status to BAD and send a Uevent to notify
5883          * userspace to do a modeset.
5884          */
5885         drm_mode_connector_set_link_status_property(connector,
5886                                                     DRM_MODE_LINK_STATUS_BAD);
5887         mutex_unlock(&connector->dev->mode_config.mutex);
5888         /* Send Hotplug uevent so userspace can reprobe */
5889         drm_kms_helper_hotplug_event(connector->dev);
5890 }
5891
5892 bool
5893 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5894                         struct intel_connector *intel_connector)
5895 {
5896         struct drm_connector *connector = &intel_connector->base;
5897         struct intel_dp *intel_dp = &intel_dig_port->dp;
5898         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5899         struct drm_device *dev = intel_encoder->base.dev;
5900         struct drm_i915_private *dev_priv = to_i915(dev);
5901         enum port port = intel_dig_port->port;
5902         int type;
5903
5904         /* Initialize the work for modeset in case of link train failure */
5905         INIT_WORK(&intel_connector->modeset_retry_work,
5906                   intel_dp_modeset_retry_work_fn);
5907
5908         if (WARN(intel_dig_port->max_lanes < 1,
5909                  "Not enough lanes (%d) for DP on port %c\n",
5910                  intel_dig_port->max_lanes, port_name(port)))
5911                 return false;
5912
5913         intel_dp_set_source_rates(intel_dp);
5914
5915         intel_dp->reset_link_params = true;
5916         intel_dp->pps_pipe = INVALID_PIPE;
5917         intel_dp->active_pipe = INVALID_PIPE;
5918
5919         /* intel_dp vfuncs */
5920         if (INTEL_GEN(dev_priv) >= 9)
5921                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5922         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5923                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5924         else if (HAS_PCH_SPLIT(dev_priv))
5925                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5926         else
5927                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5928
5929         if (INTEL_GEN(dev_priv) >= 9)
5930                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5931         else
5932                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5933
5934         if (HAS_DDI(dev_priv))
5935                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5936
5937         /* Preserve the current hw state. */
5938         intel_dp->DP = I915_READ(intel_dp->output_reg);
5939         intel_dp->attached_connector = intel_connector;
5940
5941         if (intel_dp_is_edp(dev_priv, port))
5942                 type = DRM_MODE_CONNECTOR_eDP;
5943         else
5944                 type = DRM_MODE_CONNECTOR_DisplayPort;
5945
5946         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5947                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5948
5949         /*
5950          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5951          * for DP the encoder type can be set by the caller to
5952          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5953          */
5954         if (type == DRM_MODE_CONNECTOR_eDP)
5955                 intel_encoder->type = INTEL_OUTPUT_EDP;
5956
5957         /* eDP only on port B and/or C on vlv/chv */
5958         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5959                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5960                 return false;
5961
5962         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5963                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5964                         port_name(port));
5965
5966         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5967         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5968
5969         connector->interlace_allowed = true;
5970         connector->doublescan_allowed = 0;
5971
5972         intel_dp_init_connector_port_info(intel_dig_port);
5973
5974         intel_dp_aux_init(intel_dp);
5975
5976         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5977                           edp_panel_vdd_work);
5978
5979         intel_connector_attach_encoder(intel_connector, intel_encoder);
5980
5981         if (HAS_DDI(dev_priv))
5982                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5983         else
5984                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5985
5986         /* init MST on ports that can support it */
5987         if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
5988             (port == PORT_B || port == PORT_C || port == PORT_D))
5989                 intel_dp_mst_encoder_init(intel_dig_port,
5990                                           intel_connector->base.base.id);
5991
5992         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5993                 intel_dp_aux_fini(intel_dp);
5994                 intel_dp_mst_encoder_cleanup(intel_dig_port);
5995                 goto fail;
5996         }
5997
5998         intel_dp_add_properties(intel_dp, connector);
5999
6000         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6001          * 0xd.  Failure to do so will result in spurious interrupts being
6002          * generated on the port when a cable is not attached.
6003          */
6004         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6005                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6006                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6007         }
6008
6009         return true;
6010
6011 fail:
6012         drm_connector_cleanup(connector);
6013
6014         return false;
6015 }
6016
6017 bool intel_dp_init(struct drm_i915_private *dev_priv,
6018                    i915_reg_t output_reg,
6019                    enum port port)
6020 {
6021         struct intel_digital_port *intel_dig_port;
6022         struct intel_encoder *intel_encoder;
6023         struct drm_encoder *encoder;
6024         struct intel_connector *intel_connector;
6025
6026         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6027         if (!intel_dig_port)
6028                 return false;
6029
6030         intel_connector = intel_connector_alloc();
6031         if (!intel_connector)
6032                 goto err_connector_alloc;
6033
6034         intel_encoder = &intel_dig_port->base;
6035         encoder = &intel_encoder->base;
6036
6037         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6038                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6039                              "DP %c", port_name(port)))
6040                 goto err_encoder_init;
6041
6042         intel_encoder->compute_config = intel_dp_compute_config;
6043         intel_encoder->disable = intel_disable_dp;
6044         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6045         intel_encoder->get_config = intel_dp_get_config;
6046         intel_encoder->suspend = intel_dp_encoder_suspend;
6047         if (IS_CHERRYVIEW(dev_priv)) {
6048                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6049                 intel_encoder->pre_enable = chv_pre_enable_dp;
6050                 intel_encoder->enable = vlv_enable_dp;
6051                 intel_encoder->post_disable = chv_post_disable_dp;
6052                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6053         } else if (IS_VALLEYVIEW(dev_priv)) {
6054                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6055                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6056                 intel_encoder->enable = vlv_enable_dp;
6057                 intel_encoder->post_disable = vlv_post_disable_dp;
6058         } else {
6059                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6060                 intel_encoder->enable = g4x_enable_dp;
6061                 if (INTEL_GEN(dev_priv) >= 5)
6062                         intel_encoder->post_disable = ilk_post_disable_dp;
6063         }
6064
6065         intel_dig_port->port = port;
6066         intel_dig_port->dp.output_reg = output_reg;
6067         intel_dig_port->max_lanes = 4;
6068
6069         intel_encoder->type = INTEL_OUTPUT_DP;
6070         intel_encoder->power_domain = intel_port_to_power_domain(port);
6071         if (IS_CHERRYVIEW(dev_priv)) {
6072                 if (port == PORT_D)
6073                         intel_encoder->crtc_mask = 1 << 2;
6074                 else
6075                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6076         } else {
6077                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6078         }
6079         intel_encoder->cloneable = 0;
6080         intel_encoder->port = port;
6081
6082         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6083         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6084
6085         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6086                 goto err_init_connector;
6087
6088         return true;
6089
6090 err_init_connector:
6091         drm_encoder_cleanup(encoder);
6092 err_encoder_init:
6093         kfree(intel_connector);
6094 err_connector_alloc:
6095         kfree(intel_dig_port);
6096         return false;
6097 }
6098
6099 void intel_dp_mst_suspend(struct drm_device *dev)
6100 {
6101         struct drm_i915_private *dev_priv = to_i915(dev);
6102         int i;
6103
6104         /* disable MST */
6105         for (i = 0; i < I915_MAX_PORTS; i++) {
6106                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6107
6108                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6109                         continue;
6110
6111                 if (intel_dig_port->dp.is_mst)
6112                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6113         }
6114 }
6115
6116 void intel_dp_mst_resume(struct drm_device *dev)
6117 {
6118         struct drm_i915_private *dev_priv = to_i915(dev);
6119         int i;
6120
6121         for (i = 0; i < I915_MAX_PORTS; i++) {
6122                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6123                 int ret;
6124
6125                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6126                         continue;
6127
6128                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6129                 if (ret)
6130                         intel_dp_check_mst_status(&intel_dig_port->dp);
6131         }
6132 }