drivers/gpu/drm/i915/intel_display.h

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DISPLAY_H_
  26 #define _INTEL_DISPLAY_H_
  27
  28 #include <drm/drm_util.h>
  29
  30 enum i915_gpio {
  31         GPIOA,
  32         GPIOB,
  33         GPIOC,
  34         GPIOD,
  35         GPIOE,
  36         GPIOF,
  37         GPIOG,
  38         GPIOH,
  39         __GPIOI_UNUSED,
  40         GPIOJ,
  41         GPIOK,
  42         GPIOL,
  43         GPIOM,
  44 };
  45
  46 /*
  47  * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
  48  * rest have consecutive values and match the enum values of transcoders
  49  * with a 1:1 transcoder -> pipe mapping.
  50  */
  51 enum pipe {
  52         INVALID_PIPE = -1,
  53
  54         PIPE_A = 0,
  55         PIPE_B,
  56         PIPE_C,
  57         _PIPE_EDP,
  58
  59         I915_MAX_PIPES = _PIPE_EDP
  60 };
  61
  62 #define pipe_name(p) ((p) + 'A')
  63
  64 enum transcoder {
  65         /*
  66          * The following transcoders have a 1:1 transcoder -> pipe mapping,
  67          * keep their values fixed: the code assumes that TRANSCODER_A=0, the
  68          * rest have consecutive values and match the enum values of the pipes
  69          * they map to.
  70          */
  71         TRANSCODER_A = PIPE_A,
  72         TRANSCODER_B = PIPE_B,
  73         TRANSCODER_C = PIPE_C,
  74
  75         /*
  76          * The following transcoders can map to any pipe, their enum value
  77          * doesn't need to stay fixed.
  78          */
  79         TRANSCODER_EDP,
  80         TRANSCODER_DSI_0,
  81         TRANSCODER_DSI_1,
  82         TRANSCODER_DSI_A = TRANSCODER_DSI_0,    /* legacy DSI */
  83         TRANSCODER_DSI_C = TRANSCODER_DSI_1,    /* legacy DSI */
  84
  85         I915_MAX_TRANSCODERS
  86 };
  87
  88 static inline const char *transcoder_name(enum transcoder transcoder)
  89 {
  90         switch (transcoder) {
  91         case TRANSCODER_A:
  92                 return "A";
  93         case TRANSCODER_B:
  94                 return "B";
  95         case TRANSCODER_C:
  96                 return "C";
  97         case TRANSCODER_EDP:
  98                 return "EDP";
  99         case TRANSCODER_DSI_A:
 100                 return "DSI A";
 101         case TRANSCODER_DSI_C:
 102                 return "DSI C";
 103         default:
 104                 return "<invalid>";
 105         }
 106 }
 107
 108 static inline bool transcoder_is_dsi(enum transcoder transcoder)
 109 {
 110         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
 111 }
 112
 113 /*
 114  * Global legacy plane identifier. Valid only for primary/sprite
 115  * planes on pre-g4x, and only for primary planes on g4x-bdw.
 116  */
 117 enum i9xx_plane_id {
 118         PLANE_A,
 119         PLANE_B,
 120         PLANE_C,
 121 };
 122
 123 #define plane_name(p) ((p) + 'A')
 124 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 125
 126 /*
 127  * Per-pipe plane identifier.
 128  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 129  * number of planes per CRTC.  Not all platforms really have this many planes,
 130  * which means some arrays of size I915_MAX_PLANES may have unused entries
 131  * between the topmost sprite plane and the cursor plane.
 132  *
 133  * This is expected to be passed to various register macros
 134  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 135  */
 136 enum plane_id {
 137         PLANE_PRIMARY,
 138         PLANE_SPRITE0,
 139         PLANE_SPRITE1,
 140         PLANE_SPRITE2,
 141         PLANE_SPRITE3,
 142         PLANE_SPRITE4,
 143         PLANE_SPRITE5,
 144         PLANE_CURSOR,
 145
 146         I915_MAX_PLANES,
 147 };
 148
 149 #define for_each_plane_id_on_crtc(__crtc, __p) \
 150         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 151                 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
 152
 153 enum port {
 154         PORT_NONE = -1,
 155
 156         PORT_A = 0,
 157         PORT_B,
 158         PORT_C,
 159         PORT_D,
 160         PORT_E,
 161         PORT_F,
 162
 163         I915_MAX_PORTS
 164 };
 165
 166 #define port_name(p) ((p) + 'A')
 167
 168 /*
 169  * Ports identifier referenced from other drivers.
 170  * Expected to remain stable over time
 171  */
 172 static inline const char *port_identifier(enum port port)
 173 {
 174         switch (port) {
 175         case PORT_A:
 176                 return "Port A";
 177         case PORT_B:
 178                 return "Port B";
 179         case PORT_C:
 180                 return "Port C";
 181         case PORT_D:
 182                 return "Port D";
 183         case PORT_E:
 184                 return "Port E";
 185         case PORT_F:
 186                 return "Port F";
 187         default:
 188                 return "<invalid>";
 189         }
 190 }
 191
 192 enum tc_port {
 193         PORT_TC_NONE = -1,
 194
 195         PORT_TC1 = 0,
 196         PORT_TC2,
 197         PORT_TC3,
 198         PORT_TC4,
 199
 200         I915_MAX_TC_PORTS
 201 };
 202
 203 enum tc_port_type {
 204         TC_PORT_UNKNOWN = 0,
 205         TC_PORT_TYPEC,
 206         TC_PORT_TBT,
 207         TC_PORT_LEGACY,
 208 };
 209
 210 enum dpio_channel {
 211         DPIO_CH0,
 212         DPIO_CH1
 213 };
 214
 215 enum dpio_phy {
 216         DPIO_PHY0,
 217         DPIO_PHY1,
 218         DPIO_PHY2,
 219 };
 220
 221 #define I915_NUM_PHYS_VLV 2
 222
 223 enum aux_ch {
 224         AUX_CH_A,
 225         AUX_CH_B,
 226         AUX_CH_C,
 227         AUX_CH_D,
 228         AUX_CH_E, /* ICL+ */
 229         AUX_CH_F,
 230 };
 231
 232 #define aux_ch_name(a) ((a) + 'A')
 233
 234 enum intel_display_power_domain {
 235         POWER_DOMAIN_PIPE_A,
 236         POWER_DOMAIN_PIPE_B,
 237         POWER_DOMAIN_PIPE_C,
 238         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 239         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 240         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 241         POWER_DOMAIN_TRANSCODER_A,
 242         POWER_DOMAIN_TRANSCODER_B,
 243         POWER_DOMAIN_TRANSCODER_C,
 244         POWER_DOMAIN_TRANSCODER_EDP,
 245         POWER_DOMAIN_TRANSCODER_EDP_VDSC,
 246         POWER_DOMAIN_TRANSCODER_DSI_A,
 247         POWER_DOMAIN_TRANSCODER_DSI_C,
 248         POWER_DOMAIN_PORT_DDI_A_LANES,
 249         POWER_DOMAIN_PORT_DDI_B_LANES,
 250         POWER_DOMAIN_PORT_DDI_C_LANES,
 251         POWER_DOMAIN_PORT_DDI_D_LANES,
 252         POWER_DOMAIN_PORT_DDI_E_LANES,
 253         POWER_DOMAIN_PORT_DDI_F_LANES,
 254         POWER_DOMAIN_PORT_DDI_A_IO,
 255         POWER_DOMAIN_PORT_DDI_B_IO,
 256         POWER_DOMAIN_PORT_DDI_C_IO,
 257         POWER_DOMAIN_PORT_DDI_D_IO,
 258         POWER_DOMAIN_PORT_DDI_E_IO,
 259         POWER_DOMAIN_PORT_DDI_F_IO,
 260         POWER_DOMAIN_PORT_DSI,
 261         POWER_DOMAIN_PORT_CRT,
 262         POWER_DOMAIN_PORT_OTHER,
 263         POWER_DOMAIN_VGA,
 264         POWER_DOMAIN_AUDIO,
 265         POWER_DOMAIN_PLLS,
 266         POWER_DOMAIN_AUX_A,
 267         POWER_DOMAIN_AUX_B,
 268         POWER_DOMAIN_AUX_C,
 269         POWER_DOMAIN_AUX_D,
 270         POWER_DOMAIN_AUX_E,
 271         POWER_DOMAIN_AUX_F,
 272         POWER_DOMAIN_AUX_IO_A,
 273         POWER_DOMAIN_AUX_TBT1,
 274         POWER_DOMAIN_AUX_TBT2,
 275         POWER_DOMAIN_AUX_TBT3,
 276         POWER_DOMAIN_AUX_TBT4,
 277         POWER_DOMAIN_GMBUS,
 278         POWER_DOMAIN_MODESET,
 279         POWER_DOMAIN_GT_IRQ,
 280         POWER_DOMAIN_INIT,
 281
 282         POWER_DOMAIN_NUM,
 283 };
 284
 285 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 286 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 287                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 288 #define POWER_DOMAIN_TRANSCODER(tran) \
 289         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 290          (tran) + POWER_DOMAIN_TRANSCODER_A)
 291
 292 /* Used by dp and fdi links */
 293 struct intel_link_m_n {
 294         u32 tu;
 295         u32 gmch_m;
 296         u32 gmch_n;
 297         u32 link_m;
 298         u32 link_n;
 299 };
 300
 301 #define for_each_pipe(__dev_priv, __p) \
 302         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 303
 304 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 305         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
 306                 for_each_if((__mask) & BIT(__p))
 307
 308 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
 309         for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
 310                 for_each_if ((__mask) & (1 << (__t)))
 311
 312 #define for_each_universal_plane(__dev_priv, __pipe, __p)               \
 313         for ((__p) = 0;                                                 \
 314              (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
 315              (__p)++)
 316
 317 #define for_each_sprite(__dev_priv, __p, __s)                           \
 318         for ((__s) = 0;                                                 \
 319              (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];        \
 320              (__s)++)
 321
 322 #define for_each_port_masked(__port, __ports_mask) \
 323         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)  \
 324                 for_each_if((__ports_mask) & BIT(__port))
 325
 326 #define for_each_crtc(dev, crtc) \
 327         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 328
 329 #define for_each_intel_plane(dev, intel_plane) \
 330         list_for_each_entry(intel_plane,                        \
 331                             &(dev)->mode_config.plane_list,     \
 332                             base.head)
 333
 334 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 335         list_for_each_entry(intel_plane,                                \
 336                             &(dev)->mode_config.plane_list,             \
 337                             base.head)                                  \
 338                 for_each_if((plane_mask) &                              \
 339                             drm_plane_mask(&intel_plane->base)))
 340
 341 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 342         list_for_each_entry(intel_plane,                                \
 343                             &(dev)->mode_config.plane_list,             \
 344                             base.head)                                  \
 345                 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
 346
 347 #define for_each_intel_crtc(dev, intel_crtc)                            \
 348         list_for_each_entry(intel_crtc,                                 \
 349                             &(dev)->mode_config.crtc_list,              \
 350                             base.head)
 351
 352 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
 353         list_for_each_entry(intel_crtc,                                 \
 354                             &(dev)->mode_config.crtc_list,              \
 355                             base.head)                                  \
 356                 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
 357
 358 #define for_each_intel_encoder(dev, intel_encoder)              \
 359         list_for_each_entry(intel_encoder,                      \
 360                             &(dev)->mode_config.encoder_list,   \
 361                             base.head)
 362
 363 #define for_each_intel_dp(dev, intel_encoder)                   \
 364         for_each_intel_encoder(dev, intel_encoder)              \
 365                 for_each_if(intel_encoder_is_dp(intel_encoder))
 366
 367 #define for_each_intel_connector_iter(intel_connector, iter) \
 368         while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
 369
 370 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 371         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 372                 for_each_if((intel_encoder)->base.crtc == (__crtc))
 373
 374 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 375         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 376                 for_each_if((intel_connector)->base.encoder == (__encoder))
 377
 378 #define for_each_power_domain(domain, mask)                             \
 379         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
 380                 for_each_if(BIT_ULL(domain) & (mask))
 381
 382 #define for_each_power_well(__dev_priv, __power_well)                           \
 383         for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
 384              (__power_well) - (__dev_priv)->power_domains.power_wells < \
 385                 (__dev_priv)->power_domains.power_well_count;           \
 386              (__power_well)++)
 387
 388 #define for_each_power_well_reverse(__dev_priv, __power_well)                   \
 389         for ((__power_well) = (__dev_priv)->power_domains.power_wells +         \
 390                               (__dev_priv)->power_domains.power_well_count - 1; \
 391              (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;     \
 392              (__power_well)--)
 393
 394 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)     \
 395         for_each_power_well(__dev_priv, __power_well)                           \
 396                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 397
 398 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
 399         for_each_power_well_reverse(__dev_priv, __power_well)                   \
 400                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 401
 402 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
 403         for ((__i) = 0; \
 404              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 405                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 406                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
 407              (__i)++) \
 408                 for_each_if(plane)
 409
 410 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
 411         for ((__i) = 0; \
 412              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 413                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 414                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 415              (__i)++) \
 416                 for_each_if(plane)
 417
 418 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
 419         for ((__i) = 0; \
 420              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 421                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 422                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 423              (__i)++) \
 424                 for_each_if(crtc)
 425
 426 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
 427         for ((__i) = 0; \
 428              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 429                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 430                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
 431                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 432              (__i)++) \
 433                 for_each_if(plane)
 434
 435 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 436         for ((__i) = 0; \
 437              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 438                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 439                       (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 440                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 441              (__i)++) \
 442                 for_each_if(crtc)
 443
 444 void intel_link_compute_m_n(u16 bpp, int nlanes,
 445                             int pixel_clock, int link_clock,
 446                             struct intel_link_m_n *m_n,
 447                             bool constant_n);
 448 bool is_ccs_modifier(u64 modifier);
 449 #endif