drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include "drmP.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "drm_dp_helper.h"
  38
  39 #include "drm_crtc_helper.h"
  40
  41 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  42
  43 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  44 static void intel_update_watermarks(struct drm_device *dev);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  46
  47 typedef struct {
  48     /* given values */
  49     int n;
  50     int m1, m2;
  51     int p1, p2;
  52     /* derived values */
  53     int dot;
  54     int vco;
  55     int m;
  56     int p;
  57 } intel_clock_t;
  58
  59 typedef struct {
  60     int min, max;
  61 } intel_range_t;
  62
  63 typedef struct {
  64     int dot_limit;
  65     int p2_slow, p2_fast;
  66 } intel_p2_t;
  67
  68 #define INTEL_P2_NUM                  2
  69 typedef struct intel_limit intel_limit_t;
  70 struct intel_limit {
  71     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  72     intel_p2_t      p2;
  73     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  74                       int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define PINEVIEW_VCO_MIN                1700000
 106 #define PINEVIEW_VCO_MAX                3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* Pineview's Ncounter is a ring counter */
 110 #define PINEVIEW_N_MIN                3
 111 #define PINEVIEW_N_MAX                6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define PINEVIEW_M_MIN                2
 115 #define PINEVIEW_M_MAX              256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* Pineview M1 is reserved, and must be 0 */
 121 #define PINEVIEW_M1_MIN               0
 122 #define PINEVIEW_M1_MAX               0
 123 #define PINEVIEW_M2_MIN               0
 124 #define PINEVIEW_M2_MAX               254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define PINEVIEW_P_LVDS_MIN                   7
 130 #define PINEVIEW_P_LVDS_MAX                  112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* Ironlake / Sandybridge */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IRONLAKE_DOT_MIN         25000
 242 #define IRONLAKE_DOT_MAX         350000
 243 #define IRONLAKE_VCO_MIN         1760000
 244 #define IRONLAKE_VCO_MAX         3510000
 245 #define IRONLAKE_M1_MIN          12
 246 #define IRONLAKE_M1_MAX          22
 247 #define IRONLAKE_M2_MIN          5
 248 #define IRONLAKE_M2_MAX          9
 249 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 250
 251 /* We have parameter ranges for different type of outputs. */
 252
 253 /* DAC & HDMI Refclk 120Mhz */
 254 #define IRONLAKE_DAC_N_MIN      1
 255 #define IRONLAKE_DAC_N_MAX      5
 256 #define IRONLAKE_DAC_M_MIN      79
 257 #define IRONLAKE_DAC_M_MAX      127
 258 #define IRONLAKE_DAC_P_MIN      5
 259 #define IRONLAKE_DAC_P_MAX      80
 260 #define IRONLAKE_DAC_P1_MIN     1
 261 #define IRONLAKE_DAC_P1_MAX     8
 262 #define IRONLAKE_DAC_P2_SLOW    10
 263 #define IRONLAKE_DAC_P2_FAST    5
 264
 265 /* LVDS single-channel 120Mhz refclk */
 266 #define IRONLAKE_LVDS_S_N_MIN   1
 267 #define IRONLAKE_LVDS_S_N_MAX   3
 268 #define IRONLAKE_LVDS_S_M_MIN   79
 269 #define IRONLAKE_LVDS_S_M_MAX   118
 270 #define IRONLAKE_LVDS_S_P_MIN   28
 271 #define IRONLAKE_LVDS_S_P_MAX   112
 272 #define IRONLAKE_LVDS_S_P1_MIN  2
 273 #define IRONLAKE_LVDS_S_P1_MAX  8
 274 #define IRONLAKE_LVDS_S_P2_SLOW 14
 275 #define IRONLAKE_LVDS_S_P2_FAST 14
 276
 277 /* LVDS dual-channel 120Mhz refclk */
 278 #define IRONLAKE_LVDS_D_N_MIN   1
 279 #define IRONLAKE_LVDS_D_N_MAX   3
 280 #define IRONLAKE_LVDS_D_M_MIN   79
 281 #define IRONLAKE_LVDS_D_M_MAX   127
 282 #define IRONLAKE_LVDS_D_P_MIN   14
 283 #define IRONLAKE_LVDS_D_P_MAX   56
 284 #define IRONLAKE_LVDS_D_P1_MIN  2
 285 #define IRONLAKE_LVDS_D_P1_MAX  8
 286 #define IRONLAKE_LVDS_D_P2_SLOW 7
 287 #define IRONLAKE_LVDS_D_P2_FAST 7
 288
 289 /* LVDS single-channel 100Mhz refclk */
 290 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 291 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 292 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 293 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 294 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 295 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 296 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 297 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 298 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 299 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 300
 301 /* LVDS dual-channel 100Mhz refclk */
 302 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 303 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 304 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 305 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 306 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 307 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 308 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 309 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 310 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 311 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 312
 313 /* DisplayPort */
 314 #define IRONLAKE_DP_N_MIN               1
 315 #define IRONLAKE_DP_N_MAX               2
 316 #define IRONLAKE_DP_M_MIN               81
 317 #define IRONLAKE_DP_M_MAX               90
 318 #define IRONLAKE_DP_P_MIN               10
 319 #define IRONLAKE_DP_P_MAX               20
 320 #define IRONLAKE_DP_P2_FAST             10
 321 #define IRONLAKE_DP_P2_SLOW             10
 322 #define IRONLAKE_DP_P2_LIMIT            0
 323 #define IRONLAKE_DP_P1_MIN              1
 324 #define IRONLAKE_DP_P1_MAX              2
 325
 326 /* FDI */
 327 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 328
 329 static bool
 330 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 331                     int target, int refclk, intel_clock_t *best_clock);
 332 static bool
 333 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 334                         int target, int refclk, intel_clock_t *best_clock);
 335
 336 static bool
 337 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 338                       int target, int refclk, intel_clock_t *best_clock);
 339 static bool
 340 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 341                            int target, int refclk, intel_clock_t *best_clock);
 342
 343 static const intel_limit_t intel_limits_i8xx_dvo = {
 344         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 345         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 346         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 347         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 348         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 349         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 350         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 351         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 352         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 353                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 354         .find_pll = intel_find_best_PLL,
 355 };
 356
 357 static const intel_limit_t intel_limits_i8xx_lvds = {
 358         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 359         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 360         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 361         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 362         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 363         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 364         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 365         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 366         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 367                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 368         .find_pll = intel_find_best_PLL,
 369 };
 370
 371 static const intel_limit_t intel_limits_i9xx_sdvo = {
 372         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 373         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 374         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 375         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 376         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 377         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 378         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 379         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 380         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 381                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 382         .find_pll = intel_find_best_PLL,
 383 };
 384
 385 static const intel_limit_t intel_limits_i9xx_lvds = {
 386         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 387         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 388         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 389         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 390         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 391         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 392         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 393         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 394         /* The single-channel range is 25-112Mhz, and dual-channel
 395          * is 80-224Mhz.  Prefer single channel as much as possible.
 396          */
 397         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 398                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 399         .find_pll = intel_find_best_PLL,
 400 };
 401
 402     /* below parameter and function is for G4X Chipset Family*/
 403 static const intel_limit_t intel_limits_g4x_sdvo = {
 404         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 405         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 406         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 407         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 408         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 409         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 410         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 411         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 412         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 413                  .p2_slow = G4X_P2_SDVO_SLOW,
 414                  .p2_fast = G4X_P2_SDVO_FAST
 415         },
 416         .find_pll = intel_g4x_find_best_PLL,
 417 };
 418
 419 static const intel_limit_t intel_limits_g4x_hdmi = {
 420         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 421         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 422         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 423         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 424         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 425         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 426         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 427         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 428         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 429                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 430                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 431         },
 432         .find_pll = intel_g4x_find_best_PLL,
 433 };
 434
 435 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 436         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 437                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 438         .vco = { .min = G4X_VCO_MIN,
 439                  .max = G4X_VCO_MAX },
 440         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 441                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 442         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 443                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 444         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 445                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 446         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 447                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 448         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 450         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 451                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 452         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 453                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 454                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 455         },
 456         .find_pll = intel_g4x_find_best_PLL,
 457 };
 458
 459 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 460         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 461                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 462         .vco = { .min = G4X_VCO_MIN,
 463                  .max = G4X_VCO_MAX },
 464         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 465                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 466         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 467                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 468         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 469                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 470         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 471                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 472         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 474         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 475                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 476         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 477                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 478                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 479         },
 480         .find_pll = intel_g4x_find_best_PLL,
 481 };
 482
 483 static const intel_limit_t intel_limits_g4x_display_port = {
 484         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 485                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 486         .vco = { .min = G4X_VCO_MIN,
 487                  .max = G4X_VCO_MAX},
 488         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 489                  .max = G4X_N_DISPLAY_PORT_MAX },
 490         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 491                  .max = G4X_M_DISPLAY_PORT_MAX },
 492         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 493                  .max = G4X_M1_DISPLAY_PORT_MAX },
 494         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 495                  .max = G4X_M2_DISPLAY_PORT_MAX },
 496         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 497                  .max = G4X_P_DISPLAY_PORT_MAX },
 498         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 499                  .max = G4X_P1_DISPLAY_PORT_MAX},
 500         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 501                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 502                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 503         .find_pll = intel_find_pll_g4x_dp,
 504 };
 505
 506 static const intel_limit_t intel_limits_pineview_sdvo = {
 507         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 508         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 509         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 510         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 511         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 512         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 513         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 514         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 515         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 516                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 517         .find_pll = intel_find_best_PLL,
 518 };
 519
 520 static const intel_limit_t intel_limits_pineview_lvds = {
 521         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 522         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 523         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 524         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 525         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 526         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 527         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 528         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 529         /* Pineview only supports single-channel mode. */
 530         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 531                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 532         .find_pll = intel_find_best_PLL,
 533 };
 534
 535 static const intel_limit_t intel_limits_ironlake_dac = {
 536         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 537         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 538         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 539         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 540         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 541         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 542         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 543         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 544         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 545                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 546                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 547         .find_pll = intel_g4x_find_best_PLL,
 548 };
 549
 550 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 551         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 552         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 553         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 554         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 555         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 556         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 557         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 558         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 559         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 560                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 561                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 562         .find_pll = intel_g4x_find_best_PLL,
 563 };
 564
 565 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 566         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 567         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 568         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 569         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 570         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 571         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 572         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 573         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 574         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 575                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 576                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 577         .find_pll = intel_g4x_find_best_PLL,
 578 };
 579
 580 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 581         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 582         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 583         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 584         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 585         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 586         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 587         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 588         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 589         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 590                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 591                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 592         .find_pll = intel_g4x_find_best_PLL,
 593 };
 594
 595 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 596         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 597         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 598         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 599         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 600         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 601         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 602         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 603         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 604         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 605                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 606                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 607         .find_pll = intel_g4x_find_best_PLL,
 608 };
 609
 610 static const intel_limit_t intel_limits_ironlake_display_port = {
 611         .dot = { .min = IRONLAKE_DOT_MIN,
 612                  .max = IRONLAKE_DOT_MAX },
 613         .vco = { .min = IRONLAKE_VCO_MIN,
 614                  .max = IRONLAKE_VCO_MAX},
 615         .n   = { .min = IRONLAKE_DP_N_MIN,
 616                  .max = IRONLAKE_DP_N_MAX },
 617         .m   = { .min = IRONLAKE_DP_M_MIN,
 618                  .max = IRONLAKE_DP_M_MAX },
 619         .m1  = { .min = IRONLAKE_M1_MIN,
 620                  .max = IRONLAKE_M1_MAX },
 621         .m2  = { .min = IRONLAKE_M2_MIN,
 622                  .max = IRONLAKE_M2_MAX },
 623         .p   = { .min = IRONLAKE_DP_P_MIN,
 624                  .max = IRONLAKE_DP_P_MAX },
 625         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 626                  .max = IRONLAKE_DP_P1_MAX},
 627         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 628                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 629                  .p2_fast = IRONLAKE_DP_P2_FAST },
 630         .find_pll = intel_find_pll_ironlake_dp,
 631 };
 632
 633 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 634 {
 635         struct drm_device *dev = crtc->dev;
 636         struct drm_i915_private *dev_priv = dev->dev_private;
 637         const intel_limit_t *limit;
 638         int refclk = 120;
 639
 640         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 641                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 642                         refclk = 100;
 643
 644                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 645                     LVDS_CLKB_POWER_UP) {
 646                         /* LVDS dual channel */
 647                         if (refclk == 100)
 648                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 649                         else
 650                                 limit = &intel_limits_ironlake_dual_lvds;
 651                 } else {
 652                         if (refclk == 100)
 653                                 limit = &intel_limits_ironlake_single_lvds_100m;
 654                         else
 655                                 limit = &intel_limits_ironlake_single_lvds;
 656                 }
 657         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 658                         HAS_eDP)
 659                 limit = &intel_limits_ironlake_display_port;
 660         else
 661                 limit = &intel_limits_ironlake_dac;
 662
 663         return limit;
 664 }
 665
 666 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 667 {
 668         struct drm_device *dev = crtc->dev;
 669         struct drm_i915_private *dev_priv = dev->dev_private;
 670         const intel_limit_t *limit;
 671
 672         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 673                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 674                     LVDS_CLKB_POWER_UP)
 675                         /* LVDS with dual channel */
 676                         limit = &intel_limits_g4x_dual_channel_lvds;
 677                 else
 678                         /* LVDS with dual channel */
 679                         limit = &intel_limits_g4x_single_channel_lvds;
 680         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 681                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 682                 limit = &intel_limits_g4x_hdmi;
 683         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 684                 limit = &intel_limits_g4x_sdvo;
 685         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 686                 limit = &intel_limits_g4x_display_port;
 687         } else /* The option is for other outputs */
 688                 limit = &intel_limits_i9xx_sdvo;
 689
 690         return limit;
 691 }
 692
 693 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 694 {
 695         struct drm_device *dev = crtc->dev;
 696         const intel_limit_t *limit;
 697
 698         if (HAS_PCH_SPLIT(dev))
 699                 limit = intel_ironlake_limit(crtc);
 700         else if (IS_G4X(dev)) {
 701                 limit = intel_g4x_limit(crtc);
 702         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 703                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 704                         limit = &intel_limits_i9xx_lvds;
 705                 else
 706                         limit = &intel_limits_i9xx_sdvo;
 707         } else if (IS_PINEVIEW(dev)) {
 708                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 709                         limit = &intel_limits_pineview_lvds;
 710                 else
 711                         limit = &intel_limits_pineview_sdvo;
 712         } else {
 713                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 714                         limit = &intel_limits_i8xx_lvds;
 715                 else
 716                         limit = &intel_limits_i8xx_dvo;
 717         }
 718         return limit;
 719 }
 720
 721 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 722 static void pineview_clock(int refclk, intel_clock_t *clock)
 723 {
 724         clock->m = clock->m2 + 2;
 725         clock->p = clock->p1 * clock->p2;
 726         clock->vco = refclk * clock->m / clock->n;
 727         clock->dot = clock->vco / clock->p;
 728 }
 729
 730 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 731 {
 732         if (IS_PINEVIEW(dev)) {
 733                 pineview_clock(refclk, clock);
 734                 return;
 735         }
 736         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 737         clock->p = clock->p1 * clock->p2;
 738         clock->vco = refclk * clock->m / (clock->n + 2);
 739         clock->dot = clock->vco / clock->p;
 740 }
 741
 742 /**
 743  * Returns whether any output on the specified pipe is of the specified type
 744  */
 745 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 746 {
 747     struct drm_device *dev = crtc->dev;
 748     struct drm_mode_config *mode_config = &dev->mode_config;
 749     struct drm_encoder *l_entry;
 750
 751     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 752             if (l_entry && l_entry->crtc == crtc) {
 753                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 754                     if (intel_encoder->type == type)
 755                             return true;
 756             }
 757     }
 758     return false;
 759 }
 760
 761 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 762 /**
 763  * Returns whether the given set of divisors are valid for a given refclk with
 764  * the given connectors.
 765  */
 766
 767 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 768 {
 769         const intel_limit_t *limit = intel_limit (crtc);
 770         struct drm_device *dev = crtc->dev;
 771
 772         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 773                 INTELPllInvalid ("p1 out of range\n");
 774         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 775                 INTELPllInvalid ("p out of range\n");
 776         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 777                 INTELPllInvalid ("m2 out of range\n");
 778         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 779                 INTELPllInvalid ("m1 out of range\n");
 780         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 781                 INTELPllInvalid ("m1 <= m2\n");
 782         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 783                 INTELPllInvalid ("m out of range\n");
 784         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 785                 INTELPllInvalid ("n out of range\n");
 786         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 787                 INTELPllInvalid ("vco out of range\n");
 788         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 789          * connector, etc., rather than just a single range.
 790          */
 791         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 792                 INTELPllInvalid ("dot out of range\n");
 793
 794         return true;
 795 }
 796
 797 static bool
 798 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 799                     int target, int refclk, intel_clock_t *best_clock)
 800
 801 {
 802         struct drm_device *dev = crtc->dev;
 803         struct drm_i915_private *dev_priv = dev->dev_private;
 804         intel_clock_t clock;
 805         int err = target;
 806
 807         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 808             (I915_READ(LVDS)) != 0) {
 809                 /*
 810                  * For LVDS, if the panel is on, just rely on its current
 811                  * settings for dual-channel.  We haven't figured out how to
 812                  * reliably set up different single/dual channel state, if we
 813                  * even can.
 814                  */
 815                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 816                     LVDS_CLKB_POWER_UP)
 817                         clock.p2 = limit->p2.p2_fast;
 818                 else
 819                         clock.p2 = limit->p2.p2_slow;
 820         } else {
 821                 if (target < limit->p2.dot_limit)
 822                         clock.p2 = limit->p2.p2_slow;
 823                 else
 824                         clock.p2 = limit->p2.p2_fast;
 825         }
 826
 827         memset (best_clock, 0, sizeof (*best_clock));
 828
 829         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 830              clock.m1++) {
 831                 for (clock.m2 = limit->m2.min;
 832                      clock.m2 <= limit->m2.max; clock.m2++) {
 833                         /* m1 is always 0 in Pineview */
 834                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 835                                 break;
 836                         for (clock.n = limit->n.min;
 837                              clock.n <= limit->n.max; clock.n++) {
 838                                 for (clock.p1 = limit->p1.min;
 839                                         clock.p1 <= limit->p1.max; clock.p1++) {
 840                                         int this_err;
 841
 842                                         intel_clock(dev, refclk, &clock);
 843
 844                                         if (!intel_PLL_is_valid(crtc, &clock))
 845                                                 continue;
 846
 847                                         this_err = abs(clock.dot - target);
 848                                         if (this_err < err) {
 849                                                 *best_clock = clock;
 850                                                 err = this_err;
 851                                         }
 852                                 }
 853                         }
 854                 }
 855         }
 856
 857         return (err != target);
 858 }
 859
 860 static bool
 861 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 862                         int target, int refclk, intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc->dev;
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         intel_clock_t clock;
 867         int max_n;
 868         bool found;
 869         /* approximately equals target * 0.00488 */
 870         int err_most = (target >> 8) + (target >> 10);
 871         found = false;
 872
 873         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 874                 int lvds_reg;
 875
 876                 if (HAS_PCH_SPLIT(dev))
 877                         lvds_reg = PCH_LVDS;
 878                 else
 879                         lvds_reg = LVDS;
 880                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 881                     LVDS_CLKB_POWER_UP)
 882                         clock.p2 = limit->p2.p2_fast;
 883                 else
 884                         clock.p2 = limit->p2.p2_slow;
 885         } else {
 886                 if (target < limit->p2.dot_limit)
 887                         clock.p2 = limit->p2.p2_slow;
 888                 else
 889                         clock.p2 = limit->p2.p2_fast;
 890         }
 891
 892         memset(best_clock, 0, sizeof(*best_clock));
 893         max_n = limit->n.max;
 894         /* based on hardware requirement, prefer smaller n to precision */
 895         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 896                 /* based on hardware requirement, prefere larger m1,m2 */
 897                 for (clock.m1 = limit->m1.max;
 898                      clock.m1 >= limit->m1.min; clock.m1--) {
 899                         for (clock.m2 = limit->m2.max;
 900                              clock.m2 >= limit->m2.min; clock.m2--) {
 901                                 for (clock.p1 = limit->p1.max;
 902                                      clock.p1 >= limit->p1.min; clock.p1--) {
 903                                         int this_err;
 904
 905                                         intel_clock(dev, refclk, &clock);
 906                                         if (!intel_PLL_is_valid(crtc, &clock))
 907                                                 continue;
 908                                         this_err = abs(clock.dot - target) ;
 909                                         if (this_err < err_most) {
 910                                                 *best_clock = clock;
 911                                                 err_most = this_err;
 912                                                 max_n = clock.n;
 913                                                 found = true;
 914                                         }
 915                                 }
 916                         }
 917                 }
 918         }
 919         return found;
 920 }
 921
 922 static bool
 923 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 924                            int target, int refclk, intel_clock_t *best_clock)
 925 {
 926         struct drm_device *dev = crtc->dev;
 927         intel_clock_t clock;
 928
 929         /* return directly when it is eDP */
 930         if (HAS_eDP)
 931                 return true;
 932
 933         if (target < 200000) {
 934                 clock.n = 1;
 935                 clock.p1 = 2;
 936                 clock.p2 = 10;
 937                 clock.m1 = 12;
 938                 clock.m2 = 9;
 939         } else {
 940                 clock.n = 2;
 941                 clock.p1 = 1;
 942                 clock.p2 = 10;
 943                 clock.m1 = 14;
 944                 clock.m2 = 8;
 945         }
 946         intel_clock(dev, refclk, &clock);
 947         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 948         return true;
 949 }
 950
 951 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 952 static bool
 953 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 954                       int target, int refclk, intel_clock_t *best_clock)
 955 {
 956     intel_clock_t clock;
 957     if (target < 200000) {
 958         clock.p1 = 2;
 959         clock.p2 = 10;
 960         clock.n = 2;
 961         clock.m1 = 23;
 962         clock.m2 = 8;
 963     } else {
 964         clock.p1 = 1;
 965         clock.p2 = 10;
 966         clock.n = 1;
 967         clock.m1 = 14;
 968         clock.m2 = 2;
 969     }
 970     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 971     clock.p = (clock.p1 * clock.p2);
 972     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 973     clock.vco = 0;
 974     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 975     return true;
 976 }
 977
 978 void
 979 intel_wait_for_vblank(struct drm_device *dev)
 980 {
 981         /* Wait for 20ms, i.e. one cycle at 50hz. */
 982         msleep(20);
 983 }
 984
 985 /* Parameters have changed, update FBC info */
 986 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 987 {
 988         struct drm_device *dev = crtc->dev;
 989         struct drm_i915_private *dev_priv = dev->dev_private;
 990         struct drm_framebuffer *fb = crtc->fb;
 991         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 992         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
 993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 994         int plane, i;
 995         u32 fbc_ctl, fbc_ctl2;
 996
 997         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 998
 999         if (fb->pitch < dev_priv->cfb_pitch)
1000                 dev_priv->cfb_pitch = fb->pitch;
1001
1002         /* FBC_CTL wants 64B units */
1003         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1004         dev_priv->cfb_fence = obj_priv->fence_reg;
1005         dev_priv->cfb_plane = intel_crtc->plane;
1006         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1007
1008         /* Clear old tags */
1009         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1010                 I915_WRITE(FBC_TAG + (i * 4), 0);
1011
1012         /* Set it up... */
1013         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1014         if (obj_priv->tiling_mode != I915_TILING_NONE)
1015                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1016         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1017         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1018
1019         /* enable it... */
1020         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1021         if (IS_I945GM(dev))
1022                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1023         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1024         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1025         if (obj_priv->tiling_mode != I915_TILING_NONE)
1026                 fbc_ctl |= dev_priv->cfb_fence;
1027         I915_WRITE(FBC_CONTROL, fbc_ctl);
1028
1029         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1030                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1031 }
1032
1033 void i8xx_disable_fbc(struct drm_device *dev)
1034 {
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036         unsigned long timeout = jiffies + msecs_to_jiffies(1);
1037         u32 fbc_ctl;
1038
1039         if (!I915_HAS_FBC(dev))
1040                 return;
1041
1042         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1043                 return; /* Already off, just return */
1044
1045         /* Disable compression */
1046         fbc_ctl = I915_READ(FBC_CONTROL);
1047         fbc_ctl &= ~FBC_CTL_EN;
1048         I915_WRITE(FBC_CONTROL, fbc_ctl);
1049
1050         /* Wait for compressing bit to clear */
1051         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1052                 if (time_after(jiffies, timeout)) {
1053                         DRM_DEBUG_DRIVER("FBC idle timed out\n");
1054                         break;
1055                 }
1056                 ; /* do nothing */
1057         }
1058
1059         intel_wait_for_vblank(dev);
1060
1061         DRM_DEBUG_KMS("disabled FBC\n");
1062 }
1063
1064 static bool i8xx_fbc_enabled(struct drm_device *dev)
1065 {
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067
1068         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1069 }
1070
1071 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1072 {
1073         struct drm_device *dev = crtc->dev;
1074         struct drm_i915_private *dev_priv = dev->dev_private;
1075         struct drm_framebuffer *fb = crtc->fb;
1076         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1077         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1079         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1080                      DPFC_CTL_PLANEB);
1081         unsigned long stall_watermark = 200;
1082         u32 dpfc_ctl;
1083
1084         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1085         dev_priv->cfb_fence = obj_priv->fence_reg;
1086         dev_priv->cfb_plane = intel_crtc->plane;
1087
1088         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1089         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1090                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1091                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1092         } else {
1093                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1094         }
1095
1096         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1097         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1098                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1099                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1100         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1101
1102         /* enable it... */
1103         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1104
1105         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1106 }
1107
1108 void g4x_disable_fbc(struct drm_device *dev)
1109 {
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111         u32 dpfc_ctl;
1112
1113         /* Disable compression */
1114         dpfc_ctl = I915_READ(DPFC_CONTROL);
1115         dpfc_ctl &= ~DPFC_CTL_EN;
1116         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1117         intel_wait_for_vblank(dev);
1118
1119         DRM_DEBUG_KMS("disabled FBC\n");
1120 }
1121
1122 static bool g4x_fbc_enabled(struct drm_device *dev)
1123 {
1124         struct drm_i915_private *dev_priv = dev->dev_private;
1125
1126         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1127 }
1128
1129 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1130 {
1131         struct drm_device *dev = crtc->dev;
1132         struct drm_i915_private *dev_priv = dev->dev_private;
1133         struct drm_framebuffer *fb = crtc->fb;
1134         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1135         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1137         int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1138                                                DPFC_CTL_PLANEB;
1139         unsigned long stall_watermark = 200;
1140         u32 dpfc_ctl;
1141
1142         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1143         dev_priv->cfb_fence = obj_priv->fence_reg;
1144         dev_priv->cfb_plane = intel_crtc->plane;
1145
1146         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1147         dpfc_ctl &= DPFC_RESERVED;
1148         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1149         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1150                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1151                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1152         } else {
1153                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1154         }
1155
1156         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1157         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1158                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1159                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1160         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1161         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1162         /* enable it... */
1163         I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1164                    DPFC_CTL_EN);
1165
1166         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1167 }
1168
1169 void ironlake_disable_fbc(struct drm_device *dev)
1170 {
1171         struct drm_i915_private *dev_priv = dev->dev_private;
1172         u32 dpfc_ctl;
1173
1174         /* Disable compression */
1175         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1176         dpfc_ctl &= ~DPFC_CTL_EN;
1177         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1178         intel_wait_for_vblank(dev);
1179
1180         DRM_DEBUG_KMS("disabled FBC\n");
1181 }
1182
1183 static bool ironlake_fbc_enabled(struct drm_device *dev)
1184 {
1185         struct drm_i915_private *dev_priv = dev->dev_private;
1186
1187         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1188 }
1189
1190 bool intel_fbc_enabled(struct drm_device *dev)
1191 {
1192         struct drm_i915_private *dev_priv = dev->dev_private;
1193
1194         if (!dev_priv->display.fbc_enabled)
1195                 return false;
1196
1197         return dev_priv->display.fbc_enabled(dev);
1198 }
1199
1200 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1201 {
1202         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1203
1204         if (!dev_priv->display.enable_fbc)
1205                 return;
1206
1207         dev_priv->display.enable_fbc(crtc, interval);
1208 }
1209
1210 void intel_disable_fbc(struct drm_device *dev)
1211 {
1212         struct drm_i915_private *dev_priv = dev->dev_private;
1213
1214         if (!dev_priv->display.disable_fbc)
1215                 return;
1216
1217         dev_priv->display.disable_fbc(dev);
1218 }
1219
1220 /**
1221  * intel_update_fbc - enable/disable FBC as needed
1222  * @crtc: CRTC to point the compressor at
1223  * @mode: mode in use
1224  *
1225  * Set up the framebuffer compression hardware at mode set time.  We
1226  * enable it if possible:
1227  *   - plane A only (on pre-965)
1228  *   - no pixel mulitply/line duplication
1229  *   - no alpha buffer discard
1230  *   - no dual wide
1231  *   - framebuffer <= 2048 in width, 1536 in height
1232  *
1233  * We can't assume that any compression will take place (worst case),
1234  * so the compressed buffer has to be the same size as the uncompressed
1235  * one.  It also must reside (along with the line length buffer) in
1236  * stolen memory.
1237  *
1238  * We need to enable/disable FBC on a global basis.
1239  */
1240 static void intel_update_fbc(struct drm_crtc *crtc,
1241                              struct drm_display_mode *mode)
1242 {
1243         struct drm_device *dev = crtc->dev;
1244         struct drm_i915_private *dev_priv = dev->dev_private;
1245         struct drm_framebuffer *fb = crtc->fb;
1246         struct intel_framebuffer *intel_fb;
1247         struct drm_i915_gem_object *obj_priv;
1248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1249         int plane = intel_crtc->plane;
1250
1251         if (!i915_powersave)
1252                 return;
1253
1254         if (!I915_HAS_FBC(dev))
1255                 return;
1256
1257         if (!crtc->fb)
1258                 return;
1259
1260         intel_fb = to_intel_framebuffer(fb);
1261         obj_priv = to_intel_bo(intel_fb->obj);
1262
1263         /*
1264          * If FBC is already on, we just have to verify that we can
1265          * keep it that way...
1266          * Need to disable if:
1267          *   - changing FBC params (stride, fence, mode)
1268          *   - new fb is too large to fit in compressed buffer
1269          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1270          */
1271         if (intel_fb->obj->size > dev_priv->cfb_size) {
1272                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1273                                 "compression\n");
1274                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1275                 goto out_disable;
1276         }
1277         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1278             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1279                 DRM_DEBUG_KMS("mode incompatible with compression, "
1280                                 "disabling\n");
1281                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1282                 goto out_disable;
1283         }
1284         if ((mode->hdisplay > 2048) ||
1285             (mode->vdisplay > 1536)) {
1286                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1287                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1288                 goto out_disable;
1289         }
1290         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1291                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1292                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1293                 goto out_disable;
1294         }
1295         if (obj_priv->tiling_mode != I915_TILING_X) {
1296                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1297                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1298                 goto out_disable;
1299         }
1300
1301         if (intel_fbc_enabled(dev)) {
1302                 /* We can re-enable it in this case, but need to update pitch */
1303                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1304                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1305                     (plane != dev_priv->cfb_plane))
1306                         intel_disable_fbc(dev);
1307         }
1308
1309         /* Now try to turn it back on if possible */
1310         if (!intel_fbc_enabled(dev))
1311                 intel_enable_fbc(crtc, 500);
1312
1313         return;
1314
1315 out_disable:
1316         /* Multiple disables should be harmless */
1317         if (intel_fbc_enabled(dev)) {
1318                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1319                 intel_disable_fbc(dev);
1320         }
1321 }
1322
1323 static int
1324 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1325 {
1326         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1327         u32 alignment;
1328         int ret;
1329
1330         switch (obj_priv->tiling_mode) {
1331         case I915_TILING_NONE:
1332                 alignment = 64 * 1024;
1333                 break;
1334         case I915_TILING_X:
1335                 /* pin() will align the object as required by fence */
1336                 alignment = 0;
1337                 break;
1338         case I915_TILING_Y:
1339                 /* FIXME: Is this true? */
1340                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1341                 return -EINVAL;
1342         default:
1343                 BUG();
1344         }
1345
1346         ret = i915_gem_object_pin(obj, alignment);
1347         if (ret != 0)
1348                 return ret;
1349
1350         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1351          * fence, whereas 965+ only requires a fence if using
1352          * framebuffer compression.  For simplicity, we always install
1353          * a fence as the cost is not that onerous.
1354          */
1355         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1356             obj_priv->tiling_mode != I915_TILING_NONE) {
1357                 ret = i915_gem_object_get_fence_reg(obj);
1358                 if (ret != 0) {
1359                         i915_gem_object_unpin(obj);
1360                         return ret;
1361                 }
1362         }
1363
1364         return 0;
1365 }
1366
1367 static int
1368 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1369                     struct drm_framebuffer *old_fb)
1370 {
1371         struct drm_device *dev = crtc->dev;
1372         struct drm_i915_private *dev_priv = dev->dev_private;
1373         struct drm_i915_master_private *master_priv;
1374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1375         struct intel_framebuffer *intel_fb;
1376         struct drm_i915_gem_object *obj_priv;
1377         struct drm_gem_object *obj;
1378         int pipe = intel_crtc->pipe;
1379         int plane = intel_crtc->plane;
1380         unsigned long Start, Offset;
1381         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1382         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1383         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1384         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1385         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1386         u32 dspcntr;
1387         int ret;
1388
1389         /* no fb bound */
1390         if (!crtc->fb) {
1391                 DRM_DEBUG_KMS("No FB bound\n");
1392                 return 0;
1393         }
1394
1395         switch (plane) {
1396         case 0:
1397         case 1:
1398                 break;
1399         default:
1400                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1401                 return -EINVAL;
1402         }
1403
1404         intel_fb = to_intel_framebuffer(crtc->fb);
1405         obj = intel_fb->obj;
1406         obj_priv = to_intel_bo(obj);
1407
1408         mutex_lock(&dev->struct_mutex);
1409         ret = intel_pin_and_fence_fb_obj(dev, obj);
1410         if (ret != 0) {
1411                 mutex_unlock(&dev->struct_mutex);
1412                 return ret;
1413         }
1414
1415         ret = i915_gem_object_set_to_display_plane(obj);
1416         if (ret != 0) {
1417                 i915_gem_object_unpin(obj);
1418                 mutex_unlock(&dev->struct_mutex);
1419                 return ret;
1420         }
1421
1422         dspcntr = I915_READ(dspcntr_reg);
1423         /* Mask out pixel format bits in case we change it */
1424         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1425         switch (crtc->fb->bits_per_pixel) {
1426         case 8:
1427                 dspcntr |= DISPPLANE_8BPP;
1428                 break;
1429         case 16:
1430                 if (crtc->fb->depth == 15)
1431                         dspcntr |= DISPPLANE_15_16BPP;
1432                 else
1433                         dspcntr |= DISPPLANE_16BPP;
1434                 break;
1435         case 24:
1436         case 32:
1437                 if (crtc->fb->depth == 30)
1438                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1439                 else
1440                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1441                 break;
1442         default:
1443                 DRM_ERROR("Unknown color depth\n");
1444                 i915_gem_object_unpin(obj);
1445                 mutex_unlock(&dev->struct_mutex);
1446                 return -EINVAL;
1447         }
1448         if (IS_I965G(dev)) {
1449                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1450                         dspcntr |= DISPPLANE_TILED;
1451                 else
1452                         dspcntr &= ~DISPPLANE_TILED;
1453         }
1454
1455         if (HAS_PCH_SPLIT(dev))
1456                 /* must disable */
1457                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1458
1459         I915_WRITE(dspcntr_reg, dspcntr);
1460
1461         Start = obj_priv->gtt_offset;
1462         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1463
1464         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1465                       Start, Offset, x, y, crtc->fb->pitch);
1466         I915_WRITE(dspstride, crtc->fb->pitch);
1467         if (IS_I965G(dev)) {
1468                 I915_WRITE(dspbase, Offset);
1469                 I915_READ(dspbase);
1470                 I915_WRITE(dspsurf, Start);
1471                 I915_READ(dspsurf);
1472                 I915_WRITE(dsptileoff, (y << 16) | x);
1473         } else {
1474                 I915_WRITE(dspbase, Start + Offset);
1475                 I915_READ(dspbase);
1476         }
1477
1478         if ((IS_I965G(dev) || plane == 0))
1479                 intel_update_fbc(crtc, &crtc->mode);
1480
1481         intel_wait_for_vblank(dev);
1482
1483         if (old_fb) {
1484                 intel_fb = to_intel_framebuffer(old_fb);
1485                 obj_priv = to_intel_bo(intel_fb->obj);
1486                 i915_gem_object_unpin(intel_fb->obj);
1487         }
1488         intel_increase_pllclock(crtc, true);
1489
1490         mutex_unlock(&dev->struct_mutex);
1491
1492         if (!dev->primary->master)
1493                 return 0;
1494
1495         master_priv = dev->primary->master->driver_priv;
1496         if (!master_priv->sarea_priv)
1497                 return 0;
1498
1499         if (pipe) {
1500                 master_priv->sarea_priv->pipeB_x = x;
1501                 master_priv->sarea_priv->pipeB_y = y;
1502         } else {
1503                 master_priv->sarea_priv->pipeA_x = x;
1504                 master_priv->sarea_priv->pipeA_y = y;
1505         }
1506
1507         return 0;
1508 }
1509
1510 /* Disable the VGA plane that we never use */
1511 static void i915_disable_vga (struct drm_device *dev)
1512 {
1513         struct drm_i915_private *dev_priv = dev->dev_private;
1514         u8 sr1;
1515         u32 vga_reg;
1516
1517         if (HAS_PCH_SPLIT(dev))
1518                 vga_reg = CPU_VGACNTRL;
1519         else
1520                 vga_reg = VGACNTRL;
1521
1522         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1523                 return;
1524
1525         I915_WRITE8(VGA_SR_INDEX, 1);
1526         sr1 = I915_READ8(VGA_SR_DATA);
1527         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1528         udelay(100);
1529
1530         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1531 }
1532
1533 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1534 {
1535         struct drm_device *dev = crtc->dev;
1536         struct drm_i915_private *dev_priv = dev->dev_private;
1537         u32 dpa_ctl;
1538
1539         DRM_DEBUG_KMS("\n");
1540         dpa_ctl = I915_READ(DP_A);
1541         dpa_ctl &= ~DP_PLL_ENABLE;
1542         I915_WRITE(DP_A, dpa_ctl);
1543 }
1544
1545 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1546 {
1547         struct drm_device *dev = crtc->dev;
1548         struct drm_i915_private *dev_priv = dev->dev_private;
1549         u32 dpa_ctl;
1550
1551         dpa_ctl = I915_READ(DP_A);
1552         dpa_ctl |= DP_PLL_ENABLE;
1553         I915_WRITE(DP_A, dpa_ctl);
1554         udelay(200);
1555 }
1556
1557
1558 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1559 {
1560         struct drm_device *dev = crtc->dev;
1561         struct drm_i915_private *dev_priv = dev->dev_private;
1562         u32 dpa_ctl;
1563
1564         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1565         dpa_ctl = I915_READ(DP_A);
1566         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1567
1568         if (clock < 200000) {
1569                 u32 temp;
1570                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1571                 /* workaround for 160Mhz:
1572                    1) program 0x4600c bits 15:0 = 0x8124
1573                    2) program 0x46010 bit 0 = 1
1574                    3) program 0x46034 bit 24 = 1
1575                    4) program 0x64000 bit 14 = 1
1576                    */
1577                 temp = I915_READ(0x4600c);
1578                 temp &= 0xffff0000;
1579                 I915_WRITE(0x4600c, temp | 0x8124);
1580
1581                 temp = I915_READ(0x46010);
1582                 I915_WRITE(0x46010, temp | 1);
1583
1584                 temp = I915_READ(0x46034);
1585                 I915_WRITE(0x46034, temp | (1 << 24));
1586         } else {
1587                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1588         }
1589         I915_WRITE(DP_A, dpa_ctl);
1590
1591         udelay(500);
1592 }
1593
1594 /* The FDI link training functions for ILK/Ibexpeak. */
1595 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1596 {
1597         struct drm_device *dev = crtc->dev;
1598         struct drm_i915_private *dev_priv = dev->dev_private;
1599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1600         int pipe = intel_crtc->pipe;
1601         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1602         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1603         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1604         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1605         u32 temp, tries = 0;
1606
1607         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1608            for train result */
1609         temp = I915_READ(fdi_rx_imr_reg);
1610         temp &= ~FDI_RX_SYMBOL_LOCK;
1611         temp &= ~FDI_RX_BIT_LOCK;
1612         I915_WRITE(fdi_rx_imr_reg, temp);
1613         I915_READ(fdi_rx_imr_reg);
1614         udelay(150);
1615
1616         /* enable CPU FDI TX and PCH FDI RX */
1617         temp = I915_READ(fdi_tx_reg);
1618         temp |= FDI_TX_ENABLE;
1619         temp &= ~(7 << 19);
1620         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1621         temp &= ~FDI_LINK_TRAIN_NONE;
1622         temp |= FDI_LINK_TRAIN_PATTERN_1;
1623         I915_WRITE(fdi_tx_reg, temp);
1624         I915_READ(fdi_tx_reg);
1625
1626         temp = I915_READ(fdi_rx_reg);
1627         temp &= ~FDI_LINK_TRAIN_NONE;
1628         temp |= FDI_LINK_TRAIN_PATTERN_1;
1629         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1630         I915_READ(fdi_rx_reg);
1631         udelay(150);
1632
1633         for (tries = 0; tries < 5; tries++) {
1634                 temp = I915_READ(fdi_rx_iir_reg);
1635                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1636
1637                 if ((temp & FDI_RX_BIT_LOCK)) {
1638                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1639                         I915_WRITE(fdi_rx_iir_reg,
1640                                    temp | FDI_RX_BIT_LOCK);
1641                         break;
1642                 }
1643         }
1644         if (tries == 5)
1645                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1646
1647         /* Train 2 */
1648         temp = I915_READ(fdi_tx_reg);
1649         temp &= ~FDI_LINK_TRAIN_NONE;
1650         temp |= FDI_LINK_TRAIN_PATTERN_2;
1651         I915_WRITE(fdi_tx_reg, temp);
1652
1653         temp = I915_READ(fdi_rx_reg);
1654         temp &= ~FDI_LINK_TRAIN_NONE;
1655         temp |= FDI_LINK_TRAIN_PATTERN_2;
1656         I915_WRITE(fdi_rx_reg, temp);
1657         udelay(150);
1658
1659         tries = 0;
1660
1661         for (tries = 0; tries < 5; tries++) {
1662                 temp = I915_READ(fdi_rx_iir_reg);
1663                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1664
1665                 if (temp & FDI_RX_SYMBOL_LOCK) {
1666                         I915_WRITE(fdi_rx_iir_reg,
1667                                    temp | FDI_RX_SYMBOL_LOCK);
1668                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1669                         break;
1670                 }
1671         }
1672         if (tries == 5)
1673                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1674
1675         DRM_DEBUG_KMS("FDI train done\n");
1676 }
1677
1678 static int snb_b_fdi_train_param [] = {
1679         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1680         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1681         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1682         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1683 };
1684
1685 /* The FDI link training functions for SNB/Cougarpoint. */
1686 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1687 {
1688         struct drm_device *dev = crtc->dev;
1689         struct drm_i915_private *dev_priv = dev->dev_private;
1690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1691         int pipe = intel_crtc->pipe;
1692         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1693         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1694         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1695         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1696         u32 temp, i;
1697
1698         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1699            for train result */
1700         temp = I915_READ(fdi_rx_imr_reg);
1701         temp &= ~FDI_RX_SYMBOL_LOCK;
1702         temp &= ~FDI_RX_BIT_LOCK;
1703         I915_WRITE(fdi_rx_imr_reg, temp);
1704         I915_READ(fdi_rx_imr_reg);
1705         udelay(150);
1706
1707         /* enable CPU FDI TX and PCH FDI RX */
1708         temp = I915_READ(fdi_tx_reg);
1709         temp |= FDI_TX_ENABLE;
1710         temp &= ~(7 << 19);
1711         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1712         temp &= ~FDI_LINK_TRAIN_NONE;
1713         temp |= FDI_LINK_TRAIN_PATTERN_1;
1714         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1715         /* SNB-B */
1716         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1717         I915_WRITE(fdi_tx_reg, temp);
1718         I915_READ(fdi_tx_reg);
1719
1720         temp = I915_READ(fdi_rx_reg);
1721         if (HAS_PCH_CPT(dev)) {
1722                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1723                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1724         } else {
1725                 temp &= ~FDI_LINK_TRAIN_NONE;
1726                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1727         }
1728         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1729         I915_READ(fdi_rx_reg);
1730         udelay(150);
1731
1732         for (i = 0; i < 4; i++ ) {
1733                 temp = I915_READ(fdi_tx_reg);
1734                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1735                 temp |= snb_b_fdi_train_param[i];
1736                 I915_WRITE(fdi_tx_reg, temp);
1737                 udelay(500);
1738
1739                 temp = I915_READ(fdi_rx_iir_reg);
1740                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1741
1742                 if (temp & FDI_RX_BIT_LOCK) {
1743                         I915_WRITE(fdi_rx_iir_reg,
1744                                    temp | FDI_RX_BIT_LOCK);
1745                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1746                         break;
1747                 }
1748         }
1749         if (i == 4)
1750                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1751
1752         /* Train 2 */
1753         temp = I915_READ(fdi_tx_reg);
1754         temp &= ~FDI_LINK_TRAIN_NONE;
1755         temp |= FDI_LINK_TRAIN_PATTERN_2;
1756         if (IS_GEN6(dev)) {
1757                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1758                 /* SNB-B */
1759                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1760         }
1761         I915_WRITE(fdi_tx_reg, temp);
1762
1763         temp = I915_READ(fdi_rx_reg);
1764         if (HAS_PCH_CPT(dev)) {
1765                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1766                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1767         } else {
1768                 temp &= ~FDI_LINK_TRAIN_NONE;
1769                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1770         }
1771         I915_WRITE(fdi_rx_reg, temp);
1772         udelay(150);
1773
1774         for (i = 0; i < 4; i++ ) {
1775                 temp = I915_READ(fdi_tx_reg);
1776                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1777                 temp |= snb_b_fdi_train_param[i];
1778                 I915_WRITE(fdi_tx_reg, temp);
1779                 udelay(500);
1780
1781                 temp = I915_READ(fdi_rx_iir_reg);
1782                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1783
1784                 if (temp & FDI_RX_SYMBOL_LOCK) {
1785                         I915_WRITE(fdi_rx_iir_reg,
1786                                    temp | FDI_RX_SYMBOL_LOCK);
1787                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1788                         break;
1789                 }
1790         }
1791         if (i == 4)
1792                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1793
1794         DRM_DEBUG_KMS("FDI train done.\n");
1795 }
1796
1797 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1798 {
1799         struct drm_device *dev = crtc->dev;
1800         struct drm_i915_private *dev_priv = dev->dev_private;
1801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1802         int pipe = intel_crtc->pipe;
1803         int plane = intel_crtc->plane;
1804         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1805         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1806         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1807         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1808         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1809         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1810         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1811         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1812         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1813         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1814         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1815         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1816         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1817         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1818         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1819         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1820         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1821         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1822         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1823         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1824         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1825         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1826         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1827         u32 temp;
1828         int n;
1829         u32 pipe_bpc;
1830
1831         temp = I915_READ(pipeconf_reg);
1832         pipe_bpc = temp & PIPE_BPC_MASK;
1833
1834         /* XXX: When our outputs are all unaware of DPMS modes other than off
1835          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1836          */
1837         switch (mode) {
1838         case DRM_MODE_DPMS_ON:
1839         case DRM_MODE_DPMS_STANDBY:
1840         case DRM_MODE_DPMS_SUSPEND:
1841                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1842
1843                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1844                         temp = I915_READ(PCH_LVDS);
1845                         if ((temp & LVDS_PORT_EN) == 0) {
1846                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1847                                 POSTING_READ(PCH_LVDS);
1848                         }
1849                 }
1850
1851                 if (HAS_eDP) {
1852                         /* enable eDP PLL */
1853                         ironlake_enable_pll_edp(crtc);
1854                 } else {
1855
1856                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1857                         temp = I915_READ(fdi_rx_reg);
1858                         /*
1859                          * make the BPC in FDI Rx be consistent with that in
1860                          * pipeconf reg.
1861                          */
1862                         temp &= ~(0x7 << 16);
1863                         temp |= (pipe_bpc << 11);
1864                         temp &= ~(7 << 19);
1865                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1866                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1867                         I915_READ(fdi_rx_reg);
1868                         udelay(200);
1869
1870                         /* Switch from Rawclk to PCDclk */
1871                         temp = I915_READ(fdi_rx_reg);
1872                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1873                         I915_READ(fdi_rx_reg);
1874                         udelay(200);
1875
1876                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1877                         temp = I915_READ(fdi_tx_reg);
1878                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1879                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1880                                 I915_READ(fdi_tx_reg);
1881                                 udelay(100);
1882                         }
1883                 }
1884
1885                 /* Enable panel fitting for LVDS */
1886                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1887                         temp = I915_READ(pf_ctl_reg);
1888                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1889
1890                         /* currently full aspect */
1891                         I915_WRITE(pf_win_pos, 0);
1892
1893                         I915_WRITE(pf_win_size,
1894                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1895                                    (dev_priv->panel_fixed_mode->vdisplay));
1896                 }
1897
1898                 /* Enable CPU pipe */
1899                 temp = I915_READ(pipeconf_reg);
1900                 if ((temp & PIPEACONF_ENABLE) == 0) {
1901                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1902                         I915_READ(pipeconf_reg);
1903                         udelay(100);
1904                 }
1905
1906                 /* configure and enable CPU plane */
1907                 temp = I915_READ(dspcntr_reg);
1908                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1909                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1910                         /* Flush the plane changes */
1911                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1912                 }
1913
1914                 if (!HAS_eDP) {
1915                         /* For PCH output, training FDI link */
1916                         if (IS_GEN6(dev))
1917                                 gen6_fdi_link_train(crtc);
1918                         else
1919                                 ironlake_fdi_link_train(crtc);
1920
1921                         /* enable PCH DPLL */
1922                         temp = I915_READ(pch_dpll_reg);
1923                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1924                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1925                                 I915_READ(pch_dpll_reg);
1926                         }
1927                         udelay(200);
1928
1929                         if (HAS_PCH_CPT(dev)) {
1930                                 /* Be sure PCH DPLL SEL is set */
1931                                 temp = I915_READ(PCH_DPLL_SEL);
1932                                 if (trans_dpll_sel == 0 &&
1933                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1934                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1935                                 else if (trans_dpll_sel == 1 &&
1936                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1937                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1938                                 I915_WRITE(PCH_DPLL_SEL, temp);
1939                                 I915_READ(PCH_DPLL_SEL);
1940                         }
1941
1942                         /* set transcoder timing */
1943                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1944                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1945                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1946
1947                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1948                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1949                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1950
1951                         /* enable normal train */
1952                         temp = I915_READ(fdi_tx_reg);
1953                         temp &= ~FDI_LINK_TRAIN_NONE;
1954                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1955                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1956                         I915_READ(fdi_tx_reg);
1957
1958                         temp = I915_READ(fdi_rx_reg);
1959                         if (HAS_PCH_CPT(dev)) {
1960                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1961                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1962                         } else {
1963                                 temp &= ~FDI_LINK_TRAIN_NONE;
1964                                 temp |= FDI_LINK_TRAIN_NONE;
1965                         }
1966                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1967                         I915_READ(fdi_rx_reg);
1968
1969                         /* wait one idle pattern time */
1970                         udelay(100);
1971
1972                         /* For PCH DP, enable TRANS_DP_CTL */
1973                         if (HAS_PCH_CPT(dev) &&
1974                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1975                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1976                                 int reg;
1977
1978                                 reg = I915_READ(trans_dp_ctl);
1979                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
1980                                 reg = TRANS_DP_OUTPUT_ENABLE |
1981                                       TRANS_DP_ENH_FRAMING |
1982                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
1983                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
1984
1985                                 switch (intel_trans_dp_port_sel(crtc)) {
1986                                 case PCH_DP_B:
1987                                         reg |= TRANS_DP_PORT_SEL_B;
1988                                         break;
1989                                 case PCH_DP_C:
1990                                         reg |= TRANS_DP_PORT_SEL_C;
1991                                         break;
1992                                 case PCH_DP_D:
1993                                         reg |= TRANS_DP_PORT_SEL_D;
1994                                         break;
1995                                 default:
1996                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1997                                         reg |= TRANS_DP_PORT_SEL_B;
1998                                         break;
1999                                 }
2000
2001                                 I915_WRITE(trans_dp_ctl, reg);
2002                                 POSTING_READ(trans_dp_ctl);
2003                         }
2004
2005                         /* enable PCH transcoder */
2006                         temp = I915_READ(transconf_reg);
2007                         /*
2008                          * make the BPC in transcoder be consistent with
2009                          * that in pipeconf reg.
2010                          */
2011                         temp &= ~PIPE_BPC_MASK;
2012                         temp |= pipe_bpc;
2013                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2014                         I915_READ(transconf_reg);
2015
2016                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
2017                                 ;
2018
2019                 }
2020
2021                 intel_crtc_load_lut(crtc);
2022
2023                 intel_update_fbc(crtc, &crtc->mode);
2024
2025         break;
2026         case DRM_MODE_DPMS_OFF:
2027                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
2028
2029                 drm_vblank_off(dev, pipe);
2030                 /* Disable display plane */
2031                 temp = I915_READ(dspcntr_reg);
2032                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2033                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2034                         /* Flush the plane changes */
2035                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2036                         I915_READ(dspbase_reg);
2037                 }
2038
2039                 if (dev_priv->cfb_plane == plane &&
2040                     dev_priv->display.disable_fbc)
2041                         dev_priv->display.disable_fbc(dev);
2042
2043                 i915_disable_vga(dev);
2044
2045                 /* disable cpu pipe, disable after all planes disabled */
2046                 temp = I915_READ(pipeconf_reg);
2047                 if ((temp & PIPEACONF_ENABLE) != 0) {
2048                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2049                         I915_READ(pipeconf_reg);
2050                         n = 0;
2051                         /* wait for cpu pipe off, pipe state */
2052                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2053                                 n++;
2054                                 if (n < 60) {
2055                                         udelay(500);
2056                                         continue;
2057                                 } else {
2058                                         DRM_DEBUG_KMS("pipe %d off delay\n",
2059                                                                 pipe);
2060                                         break;
2061                                 }
2062                         }
2063                 } else
2064                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2065
2066                 udelay(100);
2067
2068                 /* Disable PF */
2069                 temp = I915_READ(pf_ctl_reg);
2070                 if ((temp & PF_ENABLE) != 0) {
2071                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2072                         I915_READ(pf_ctl_reg);
2073                 }
2074                 I915_WRITE(pf_win_size, 0);
2075                 POSTING_READ(pf_win_size);
2076
2077
2078                 /* disable CPU FDI tx and PCH FDI rx */
2079                 temp = I915_READ(fdi_tx_reg);
2080                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2081                 I915_READ(fdi_tx_reg);
2082
2083                 temp = I915_READ(fdi_rx_reg);
2084                 /* BPC in FDI rx is consistent with that in pipeconf */
2085                 temp &= ~(0x07 << 16);
2086                 temp |= (pipe_bpc << 11);
2087                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2088                 I915_READ(fdi_rx_reg);
2089
2090                 udelay(100);
2091
2092                 /* still set train pattern 1 */
2093                 temp = I915_READ(fdi_tx_reg);
2094                 temp &= ~FDI_LINK_TRAIN_NONE;
2095                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2096                 I915_WRITE(fdi_tx_reg, temp);
2097                 POSTING_READ(fdi_tx_reg);
2098
2099                 temp = I915_READ(fdi_rx_reg);
2100                 if (HAS_PCH_CPT(dev)) {
2101                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2102                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2103                 } else {
2104                         temp &= ~FDI_LINK_TRAIN_NONE;
2105                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2106                 }
2107                 I915_WRITE(fdi_rx_reg, temp);
2108                 POSTING_READ(fdi_rx_reg);
2109
2110                 udelay(100);
2111
2112                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2113                         temp = I915_READ(PCH_LVDS);
2114                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2115                         I915_READ(PCH_LVDS);
2116                         udelay(100);
2117                 }
2118
2119                 /* disable PCH transcoder */
2120                 temp = I915_READ(transconf_reg);
2121                 if ((temp & TRANS_ENABLE) != 0) {
2122                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2123                         I915_READ(transconf_reg);
2124                         n = 0;
2125                         /* wait for PCH transcoder off, transcoder state */
2126                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2127                                 n++;
2128                                 if (n < 60) {
2129                                         udelay(500);
2130                                         continue;
2131                                 } else {
2132                                         DRM_DEBUG_KMS("transcoder %d off "
2133                                                         "delay\n", pipe);
2134                                         break;
2135                                 }
2136                         }
2137                 }
2138
2139                 temp = I915_READ(transconf_reg);
2140                 /* BPC in transcoder is consistent with that in pipeconf */
2141                 temp &= ~PIPE_BPC_MASK;
2142                 temp |= pipe_bpc;
2143                 I915_WRITE(transconf_reg, temp);
2144                 I915_READ(transconf_reg);
2145                 udelay(100);
2146
2147                 if (HAS_PCH_CPT(dev)) {
2148                         /* disable TRANS_DP_CTL */
2149                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2150                         int reg;
2151
2152                         reg = I915_READ(trans_dp_ctl);
2153                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2154                         I915_WRITE(trans_dp_ctl, reg);
2155                         POSTING_READ(trans_dp_ctl);
2156
2157                         /* disable DPLL_SEL */
2158                         temp = I915_READ(PCH_DPLL_SEL);
2159                         if (trans_dpll_sel == 0)
2160                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2161                         else
2162                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2163                         I915_WRITE(PCH_DPLL_SEL, temp);
2164                         I915_READ(PCH_DPLL_SEL);
2165
2166                 }
2167
2168                 /* disable PCH DPLL */
2169                 temp = I915_READ(pch_dpll_reg);
2170                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2171                 I915_READ(pch_dpll_reg);
2172
2173                 if (HAS_eDP) {
2174                         ironlake_disable_pll_edp(crtc);
2175                 }
2176
2177                 /* Switch from PCDclk to Rawclk */
2178                 temp = I915_READ(fdi_rx_reg);
2179                 temp &= ~FDI_SEL_PCDCLK;
2180                 I915_WRITE(fdi_rx_reg, temp);
2181                 I915_READ(fdi_rx_reg);
2182
2183                 /* Disable CPU FDI TX PLL */
2184                 temp = I915_READ(fdi_tx_reg);
2185                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2186                 I915_READ(fdi_tx_reg);
2187                 udelay(100);
2188
2189                 temp = I915_READ(fdi_rx_reg);
2190                 temp &= ~FDI_RX_PLL_ENABLE;
2191                 I915_WRITE(fdi_rx_reg, temp);
2192                 I915_READ(fdi_rx_reg);
2193
2194                 /* Wait for the clocks to turn off. */
2195                 udelay(100);
2196                 break;
2197         }
2198 }
2199
2200 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2201 {
2202         struct intel_overlay *overlay;
2203         int ret;
2204
2205         if (!enable && intel_crtc->overlay) {
2206                 overlay = intel_crtc->overlay;
2207                 mutex_lock(&overlay->dev->struct_mutex);
2208                 for (;;) {
2209                         ret = intel_overlay_switch_off(overlay);
2210                         if (ret == 0)
2211                                 break;
2212
2213                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2214                         if (ret != 0) {
2215                                 /* overlay doesn't react anymore. Usually
2216                                  * results in a black screen and an unkillable
2217                                  * X server. */
2218                                 BUG();
2219                                 overlay->hw_wedged = HW_WEDGED;
2220                                 break;
2221                         }
2222                 }
2223                 mutex_unlock(&overlay->dev->struct_mutex);
2224         }
2225         /* Let userspace switch the overlay on again. In most cases userspace
2226          * has to recompute where to put it anyway. */
2227
2228         return;
2229 }
2230
2231 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2232 {
2233         struct drm_device *dev = crtc->dev;
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236         int pipe = intel_crtc->pipe;
2237         int plane = intel_crtc->plane;
2238         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2239         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2240         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2241         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2242         u32 temp;
2243
2244         /* XXX: When our outputs are all unaware of DPMS modes other than off
2245          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2246          */
2247         switch (mode) {
2248         case DRM_MODE_DPMS_ON:
2249         case DRM_MODE_DPMS_STANDBY:
2250         case DRM_MODE_DPMS_SUSPEND:
2251                 intel_update_watermarks(dev);
2252
2253                 /* Enable the DPLL */
2254                 temp = I915_READ(dpll_reg);
2255                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2256                         I915_WRITE(dpll_reg, temp);
2257                         I915_READ(dpll_reg);
2258                         /* Wait for the clocks to stabilize. */
2259                         udelay(150);
2260                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2261                         I915_READ(dpll_reg);
2262                         /* Wait for the clocks to stabilize. */
2263                         udelay(150);
2264                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2265                         I915_READ(dpll_reg);
2266                         /* Wait for the clocks to stabilize. */
2267                         udelay(150);
2268                 }
2269
2270                 /* Enable the pipe */
2271                 temp = I915_READ(pipeconf_reg);
2272                 if ((temp & PIPEACONF_ENABLE) == 0)
2273                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2274
2275                 /* Enable the plane */
2276                 temp = I915_READ(dspcntr_reg);
2277                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2278                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2279                         /* Flush the plane changes */
2280                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2281                 }
2282
2283                 intel_crtc_load_lut(crtc);
2284
2285                 if ((IS_I965G(dev) || plane == 0))
2286                         intel_update_fbc(crtc, &crtc->mode);
2287
2288                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2289                 intel_crtc_dpms_overlay(intel_crtc, true);
2290         break;
2291         case DRM_MODE_DPMS_OFF:
2292                 intel_update_watermarks(dev);
2293
2294                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2295                 intel_crtc_dpms_overlay(intel_crtc, false);
2296                 drm_vblank_off(dev, pipe);
2297
2298                 if (dev_priv->cfb_plane == plane &&
2299                     dev_priv->display.disable_fbc)
2300                         dev_priv->display.disable_fbc(dev);
2301
2302                 /* Disable the VGA plane that we never use */
2303                 i915_disable_vga(dev);
2304
2305                 /* Disable display plane */
2306                 temp = I915_READ(dspcntr_reg);
2307                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2308                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2309                         /* Flush the plane changes */
2310                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2311                         I915_READ(dspbase_reg);
2312                 }
2313
2314                 if (!IS_I9XX(dev)) {
2315                         /* Wait for vblank for the disable to take effect */
2316                         intel_wait_for_vblank(dev);
2317                 }
2318
2319                 /* Next, disable display pipes */
2320                 temp = I915_READ(pipeconf_reg);
2321                 if ((temp & PIPEACONF_ENABLE) != 0) {
2322                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2323                         I915_READ(pipeconf_reg);
2324                 }
2325
2326                 /* Wait for vblank for the disable to take effect. */
2327                 intel_wait_for_vblank(dev);
2328
2329                 temp = I915_READ(dpll_reg);
2330                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2331                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2332                         I915_READ(dpll_reg);
2333                 }
2334
2335                 /* Wait for the clocks to turn off. */
2336                 udelay(150);
2337                 break;
2338         }
2339 }
2340
2341 /**
2342  * Sets the power management mode of the pipe and plane.
2343  *
2344  * This code should probably grow support for turning the cursor off and back
2345  * on appropriately at the same time as we're turning the pipe off/on.
2346  */
2347 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2348 {
2349         struct drm_device *dev = crtc->dev;
2350         struct drm_i915_private *dev_priv = dev->dev_private;
2351         struct drm_i915_master_private *master_priv;
2352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2353         int pipe = intel_crtc->pipe;
2354         bool enabled;
2355
2356         dev_priv->display.dpms(crtc, mode);
2357
2358         intel_crtc->dpms_mode = mode;
2359
2360         if (!dev->primary->master)
2361                 return;
2362
2363         master_priv = dev->primary->master->driver_priv;
2364         if (!master_priv->sarea_priv)
2365                 return;
2366
2367         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2368
2369         switch (pipe) {
2370         case 0:
2371                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2372                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2373                 break;
2374         case 1:
2375                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2376                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2377                 break;
2378         default:
2379                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2380                 break;
2381         }
2382 }
2383
2384 static void intel_crtc_prepare (struct drm_crtc *crtc)
2385 {
2386         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2387         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2388 }
2389
2390 static void intel_crtc_commit (struct drm_crtc *crtc)
2391 {
2392         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2393         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2394 }
2395
2396 void intel_encoder_prepare (struct drm_encoder *encoder)
2397 {
2398         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2399         /* lvds has its own version of prepare see intel_lvds_prepare */
2400         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2401 }
2402
2403 void intel_encoder_commit (struct drm_encoder *encoder)
2404 {
2405         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2406         /* lvds has its own version of commit see intel_lvds_commit */
2407         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2408 }
2409
2410 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2411                                   struct drm_display_mode *mode,
2412                                   struct drm_display_mode *adjusted_mode)
2413 {
2414         struct drm_device *dev = crtc->dev;
2415         if (HAS_PCH_SPLIT(dev)) {
2416                 /* FDI link clock is fixed at 2.7G */
2417                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2418                         return false;
2419         }
2420
2421         drm_mode_set_crtcinfo(adjusted_mode, 0);
2422         return true;
2423 }
2424
2425 static int i945_get_display_clock_speed(struct drm_device *dev)
2426 {
2427         return 400000;
2428 }
2429
2430 static int i915_get_display_clock_speed(struct drm_device *dev)
2431 {
2432         return 333000;
2433 }
2434
2435 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2436 {
2437         return 200000;
2438 }
2439
2440 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2441 {
2442         u16 gcfgc = 0;
2443
2444         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2445
2446         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2447                 return 133000;
2448         else {
2449                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2450                 case GC_DISPLAY_CLOCK_333_MHZ:
2451                         return 333000;
2452                 default:
2453                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2454                         return 190000;
2455                 }
2456         }
2457 }
2458
2459 static int i865_get_display_clock_speed(struct drm_device *dev)
2460 {
2461         return 266000;
2462 }
2463
2464 static int i855_get_display_clock_speed(struct drm_device *dev)
2465 {
2466         u16 hpllcc = 0;
2467         /* Assume that the hardware is in the high speed state.  This
2468          * should be the default.
2469          */
2470         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2471         case GC_CLOCK_133_200:
2472         case GC_CLOCK_100_200:
2473                 return 200000;
2474         case GC_CLOCK_166_250:
2475                 return 250000;
2476         case GC_CLOCK_100_133:
2477                 return 133000;
2478         }
2479
2480         /* Shouldn't happen */
2481         return 0;
2482 }
2483
2484 static int i830_get_display_clock_speed(struct drm_device *dev)
2485 {
2486         return 133000;
2487 }
2488
2489 /**
2490  * Return the pipe currently connected to the panel fitter,
2491  * or -1 if the panel fitter is not present or not in use
2492  */
2493 int intel_panel_fitter_pipe (struct drm_device *dev)
2494 {
2495         struct drm_i915_private *dev_priv = dev->dev_private;
2496         u32  pfit_control;
2497
2498         /* i830 doesn't have a panel fitter */
2499         if (IS_I830(dev))
2500                 return -1;
2501
2502         pfit_control = I915_READ(PFIT_CONTROL);
2503
2504         /* See if the panel fitter is in use */
2505         if ((pfit_control & PFIT_ENABLE) == 0)
2506                 return -1;
2507
2508         /* 965 can place panel fitter on either pipe */
2509         if (IS_I965G(dev))
2510                 return (pfit_control >> 29) & 0x3;
2511
2512         /* older chips can only use pipe 1 */
2513         return 1;
2514 }
2515
2516 struct fdi_m_n {
2517         u32        tu;
2518         u32        gmch_m;
2519         u32        gmch_n;
2520         u32        link_m;
2521         u32        link_n;
2522 };
2523
2524 static void
2525 fdi_reduce_ratio(u32 *num, u32 *den)
2526 {
2527         while (*num > 0xffffff || *den > 0xffffff) {
2528                 *num >>= 1;
2529                 *den >>= 1;
2530         }
2531 }
2532
2533 #define DATA_N 0x800000
2534 #define LINK_N 0x80000
2535
2536 static void
2537 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2538                      int link_clock, struct fdi_m_n *m_n)
2539 {
2540         u64 temp;
2541
2542         m_n->tu = 64; /* default size */
2543
2544         temp = (u64) DATA_N * pixel_clock;
2545         temp = div_u64(temp, link_clock);
2546         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2547         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2548         m_n->gmch_n = DATA_N;
2549         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2550
2551         temp = (u64) LINK_N * pixel_clock;
2552         m_n->link_m = div_u64(temp, link_clock);
2553         m_n->link_n = LINK_N;
2554         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2555 }
2556
2557
2558 struct intel_watermark_params {
2559         unsigned long fifo_size;
2560         unsigned long max_wm;
2561         unsigned long default_wm;
2562         unsigned long guard_size;
2563         unsigned long cacheline_size;
2564 };
2565
2566 /* Pineview has different values for various configs */
2567 static struct intel_watermark_params pineview_display_wm = {
2568         PINEVIEW_DISPLAY_FIFO,
2569         PINEVIEW_MAX_WM,
2570         PINEVIEW_DFT_WM,
2571         PINEVIEW_GUARD_WM,
2572         PINEVIEW_FIFO_LINE_SIZE
2573 };
2574 static struct intel_watermark_params pineview_display_hplloff_wm = {
2575         PINEVIEW_DISPLAY_FIFO,
2576         PINEVIEW_MAX_WM,
2577         PINEVIEW_DFT_HPLLOFF_WM,
2578         PINEVIEW_GUARD_WM,
2579         PINEVIEW_FIFO_LINE_SIZE
2580 };
2581 static struct intel_watermark_params pineview_cursor_wm = {
2582         PINEVIEW_CURSOR_FIFO,
2583         PINEVIEW_CURSOR_MAX_WM,
2584         PINEVIEW_CURSOR_DFT_WM,
2585         PINEVIEW_CURSOR_GUARD_WM,
2586         PINEVIEW_FIFO_LINE_SIZE,
2587 };
2588 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2589         PINEVIEW_CURSOR_FIFO,
2590         PINEVIEW_CURSOR_MAX_WM,
2591         PINEVIEW_CURSOR_DFT_WM,
2592         PINEVIEW_CURSOR_GUARD_WM,
2593         PINEVIEW_FIFO_LINE_SIZE
2594 };
2595 static struct intel_watermark_params g4x_wm_info = {
2596         G4X_FIFO_SIZE,
2597         G4X_MAX_WM,
2598         G4X_MAX_WM,
2599         2,
2600         G4X_FIFO_LINE_SIZE,
2601 };
2602 static struct intel_watermark_params g4x_cursor_wm_info = {
2603         I965_CURSOR_FIFO,
2604         I965_CURSOR_MAX_WM,
2605         I965_CURSOR_DFT_WM,
2606         2,
2607         G4X_FIFO_LINE_SIZE,
2608 };
2609 static struct intel_watermark_params i965_cursor_wm_info = {
2610         I965_CURSOR_FIFO,
2611         I965_CURSOR_MAX_WM,
2612         I965_CURSOR_DFT_WM,
2613         2,
2614         I915_FIFO_LINE_SIZE,
2615 };
2616 static struct intel_watermark_params i945_wm_info = {
2617         I945_FIFO_SIZE,
2618         I915_MAX_WM,
2619         1,
2620         2,
2621         I915_FIFO_LINE_SIZE
2622 };
2623 static struct intel_watermark_params i915_wm_info = {
2624         I915_FIFO_SIZE,
2625         I915_MAX_WM,
2626         1,
2627         2,
2628         I915_FIFO_LINE_SIZE
2629 };
2630 static struct intel_watermark_params i855_wm_info = {
2631         I855GM_FIFO_SIZE,
2632         I915_MAX_WM,
2633         1,
2634         2,
2635         I830_FIFO_LINE_SIZE
2636 };
2637 static struct intel_watermark_params i830_wm_info = {
2638         I830_FIFO_SIZE,
2639         I915_MAX_WM,
2640         1,
2641         2,
2642         I830_FIFO_LINE_SIZE
2643 };
2644
2645 static struct intel_watermark_params ironlake_display_wm_info = {
2646         ILK_DISPLAY_FIFO,
2647         ILK_DISPLAY_MAXWM,
2648         ILK_DISPLAY_DFTWM,
2649         2,
2650         ILK_FIFO_LINE_SIZE
2651 };
2652
2653 static struct intel_watermark_params ironlake_cursor_wm_info = {
2654         ILK_CURSOR_FIFO,
2655         ILK_CURSOR_MAXWM,
2656         ILK_CURSOR_DFTWM,
2657         2,
2658         ILK_FIFO_LINE_SIZE
2659 };
2660
2661 static struct intel_watermark_params ironlake_display_srwm_info = {
2662         ILK_DISPLAY_SR_FIFO,
2663         ILK_DISPLAY_MAX_SRWM,
2664         ILK_DISPLAY_DFT_SRWM,
2665         2,
2666         ILK_FIFO_LINE_SIZE
2667 };
2668
2669 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2670         ILK_CURSOR_SR_FIFO,
2671         ILK_CURSOR_MAX_SRWM,
2672         ILK_CURSOR_DFT_SRWM,
2673         2,
2674         ILK_FIFO_LINE_SIZE
2675 };
2676
2677 /**
2678  * intel_calculate_wm - calculate watermark level
2679  * @clock_in_khz: pixel clock
2680  * @wm: chip FIFO params
2681  * @pixel_size: display pixel size
2682  * @latency_ns: memory latency for the platform
2683  *
2684  * Calculate the watermark level (the level at which the display plane will
2685  * start fetching from memory again).  Each chip has a different display
2686  * FIFO size and allocation, so the caller needs to figure that out and pass
2687  * in the correct intel_watermark_params structure.
2688  *
2689  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2690  * on the pixel size.  When it reaches the watermark level, it'll start
2691  * fetching FIFO line sized based chunks from memory until the FIFO fills
2692  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2693  * will occur, and a display engine hang could result.
2694  */
2695 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2696                                         struct intel_watermark_params *wm,
2697                                         int pixel_size,
2698                                         unsigned long latency_ns)
2699 {
2700         long entries_required, wm_size;
2701
2702         /*
2703          * Note: we need to make sure we don't overflow for various clock &
2704          * latency values.
2705          * clocks go from a few thousand to several hundred thousand.
2706          * latency is usually a few thousand
2707          */
2708         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2709                 1000;
2710         entries_required /= wm->cacheline_size;
2711
2712         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2713
2714         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2715
2716         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2717
2718         /* Don't promote wm_size to unsigned... */
2719         if (wm_size > (long)wm->max_wm)
2720                 wm_size = wm->max_wm;
2721         if (wm_size <= 0)
2722                 wm_size = wm->default_wm;
2723         return wm_size;
2724 }
2725
2726 struct cxsr_latency {
2727         int is_desktop;
2728         int is_ddr3;
2729         unsigned long fsb_freq;
2730         unsigned long mem_freq;
2731         unsigned long display_sr;
2732         unsigned long display_hpll_disable;
2733         unsigned long cursor_sr;
2734         unsigned long cursor_hpll_disable;
2735 };
2736
2737 static struct cxsr_latency cxsr_latency_table[] = {
2738         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2739         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2740         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2741         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2742         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2743
2744         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2745         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2746         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2747         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2748         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2749
2750         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2751         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2752         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2753         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2754         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2755
2756         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2757         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2758         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2759         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2760         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2761
2762         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2763         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2764         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2765         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2766         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2767
2768         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2769         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2770         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2771         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2772         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2773 };
2774
2775 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2776                                                    int fsb, int mem)
2777 {
2778         int i;
2779         struct cxsr_latency *latency;
2780
2781         if (fsb == 0 || mem == 0)
2782                 return NULL;
2783
2784         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2785                 latency = &cxsr_latency_table[i];
2786                 if (is_desktop == latency->is_desktop &&
2787                     is_ddr3 == latency->is_ddr3 &&
2788                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2789                         return latency;
2790         }
2791
2792         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2793
2794         return NULL;
2795 }
2796
2797 static void pineview_disable_cxsr(struct drm_device *dev)
2798 {
2799         struct drm_i915_private *dev_priv = dev->dev_private;
2800         u32 reg;
2801
2802         /* deactivate cxsr */
2803         reg = I915_READ(DSPFW3);
2804         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2805         I915_WRITE(DSPFW3, reg);
2806         DRM_INFO("Big FIFO is disabled\n");
2807 }
2808
2809 /*
2810  * Latency for FIFO fetches is dependent on several factors:
2811  *   - memory configuration (speed, channels)
2812  *   - chipset
2813  *   - current MCH state
2814  * It can be fairly high in some situations, so here we assume a fairly
2815  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2816  * set this value too high, the FIFO will fetch frequently to stay full)
2817  * and power consumption (set it too low to save power and we might see
2818  * FIFO underruns and display "flicker").
2819  *
2820  * A value of 5us seems to be a good balance; safe for very low end
2821  * platforms but not overly aggressive on lower latency configs.
2822  */
2823 static const int latency_ns = 5000;
2824
2825 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2826 {
2827         struct drm_i915_private *dev_priv = dev->dev_private;
2828         uint32_t dsparb = I915_READ(DSPARB);
2829         int size;
2830
2831         if (plane == 0)
2832                 size = dsparb & 0x7f;
2833         else
2834                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2835                         (dsparb & 0x7f);
2836
2837         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2838                         plane ? "B" : "A", size);
2839
2840         return size;
2841 }
2842
2843 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2844 {
2845         struct drm_i915_private *dev_priv = dev->dev_private;
2846         uint32_t dsparb = I915_READ(DSPARB);
2847         int size;
2848
2849         if (plane == 0)
2850                 size = dsparb & 0x1ff;
2851         else
2852                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2853                         (dsparb & 0x1ff);
2854         size >>= 1; /* Convert to cachelines */
2855
2856         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2857                         plane ? "B" : "A", size);
2858
2859         return size;
2860 }
2861
2862 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2863 {
2864         struct drm_i915_private *dev_priv = dev->dev_private;
2865         uint32_t dsparb = I915_READ(DSPARB);
2866         int size;
2867
2868         size = dsparb & 0x7f;
2869         size >>= 2; /* Convert to cachelines */
2870
2871         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2872                         plane ? "B" : "A",
2873                   size);
2874
2875         return size;
2876 }
2877
2878 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2879 {
2880         struct drm_i915_private *dev_priv = dev->dev_private;
2881         uint32_t dsparb = I915_READ(DSPARB);
2882         int size;
2883
2884         size = dsparb & 0x7f;
2885         size >>= 1; /* Convert to cachelines */
2886
2887         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2888                         plane ? "B" : "A", size);
2889
2890         return size;
2891 }
2892
2893 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2894                           int planeb_clock, int sr_hdisplay, int unused,
2895                           int pixel_size)
2896 {
2897         struct drm_i915_private *dev_priv = dev->dev_private;
2898         u32 reg;
2899         unsigned long wm;
2900         struct cxsr_latency *latency;
2901         int sr_clock;
2902
2903         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2904                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2905         if (!latency) {
2906                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2907                 pineview_disable_cxsr(dev);
2908                 return;
2909         }
2910
2911         if (!planea_clock || !planeb_clock) {
2912                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2913
2914                 /* Display SR */
2915                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2916                                         pixel_size, latency->display_sr);
2917                 reg = I915_READ(DSPFW1);
2918                 reg &= ~DSPFW_SR_MASK;
2919                 reg |= wm << DSPFW_SR_SHIFT;
2920                 I915_WRITE(DSPFW1, reg);
2921                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2922
2923                 /* cursor SR */
2924                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2925                                         pixel_size, latency->cursor_sr);
2926                 reg = I915_READ(DSPFW3);
2927                 reg &= ~DSPFW_CURSOR_SR_MASK;
2928                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2929                 I915_WRITE(DSPFW3, reg);
2930
2931                 /* Display HPLL off SR */
2932                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2933                                         pixel_size, latency->display_hpll_disable);
2934                 reg = I915_READ(DSPFW3);
2935                 reg &= ~DSPFW_HPLL_SR_MASK;
2936                 reg |= wm & DSPFW_HPLL_SR_MASK;
2937                 I915_WRITE(DSPFW3, reg);
2938
2939                 /* cursor HPLL off SR */
2940                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2941                                         pixel_size, latency->cursor_hpll_disable);
2942                 reg = I915_READ(DSPFW3);
2943                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2944                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2945                 I915_WRITE(DSPFW3, reg);
2946                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2947
2948                 /* activate cxsr */
2949                 reg = I915_READ(DSPFW3);
2950                 reg |= PINEVIEW_SELF_REFRESH_EN;
2951                 I915_WRITE(DSPFW3, reg);
2952                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2953         } else {
2954                 pineview_disable_cxsr(dev);
2955                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2956         }
2957 }
2958
2959 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2960                           int planeb_clock, int sr_hdisplay, int sr_htotal,
2961                           int pixel_size)
2962 {
2963         struct drm_i915_private *dev_priv = dev->dev_private;
2964         int total_size, cacheline_size;
2965         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2966         struct intel_watermark_params planea_params, planeb_params;
2967         unsigned long line_time_us;
2968         int sr_clock, sr_entries = 0, entries_required;
2969
2970         /* Create copies of the base settings for each pipe */
2971         planea_params = planeb_params = g4x_wm_info;
2972
2973         /* Grab a couple of global values before we overwrite them */
2974         total_size = planea_params.fifo_size;
2975         cacheline_size = planea_params.cacheline_size;
2976
2977         /*
2978          * Note: we need to make sure we don't overflow for various clock &
2979          * latency values.
2980          * clocks go from a few thousand to several hundred thousand.
2981          * latency is usually a few thousand
2982          */
2983         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2984                 1000;
2985         entries_required /= G4X_FIFO_LINE_SIZE;
2986         planea_wm = entries_required + planea_params.guard_size;
2987
2988         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2989                 1000;
2990         entries_required /= G4X_FIFO_LINE_SIZE;
2991         planeb_wm = entries_required + planeb_params.guard_size;
2992
2993         cursora_wm = cursorb_wm = 16;
2994         cursor_sr = 32;
2995
2996         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2997
2998         /* Calc sr entries for one plane configs */
2999         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3000                 /* self-refresh has much higher latency */
3001                 static const int sr_latency_ns = 12000;
3002
3003                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3004                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3005
3006                 /* Use ns/us then divide to preserve precision */
3007                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3008                               pixel_size * sr_hdisplay;
3009                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3010
3011                 entries_required = (((sr_latency_ns / line_time_us) +
3012                                      1000) / 1000) * pixel_size * 64;
3013                 entries_required = roundup(entries_required /
3014                                            g4x_cursor_wm_info.cacheline_size, 1);
3015                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3016
3017                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3018                         cursor_sr = g4x_cursor_wm_info.max_wm;
3019                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3020                               "cursor %d\n", sr_entries, cursor_sr);
3021
3022                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3023         } else {
3024                 /* Turn off self refresh if both pipes are enabled */
3025                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3026                                         & ~FW_BLC_SELF_EN);
3027         }
3028
3029         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3030                   planea_wm, planeb_wm, sr_entries);
3031
3032         planea_wm &= 0x3f;
3033         planeb_wm &= 0x3f;
3034
3035         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3036                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3037                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3038         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3039                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3040         /* HPLL off in SR has some issues on G4x... disable it */
3041         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3042                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3043 }
3044
3045 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3046                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3047                            int pixel_size)
3048 {
3049         struct drm_i915_private *dev_priv = dev->dev_private;
3050         unsigned long line_time_us;
3051         int sr_clock, sr_entries, srwm = 1;
3052         int cursor_sr = 16;
3053
3054         /* Calc sr entries for one plane configs */
3055         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3056                 /* self-refresh has much higher latency */
3057                 static const int sr_latency_ns = 12000;
3058
3059                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3060                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3061
3062                 /* Use ns/us then divide to preserve precision */
3063                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3064                               pixel_size * sr_hdisplay;
3065                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
3066                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3067                 srwm = I965_FIFO_SIZE - sr_entries;
3068                 if (srwm < 0)
3069                         srwm = 1;
3070                 srwm &= 0x1ff;
3071
3072                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3073                              pixel_size * 64;
3074                 sr_entries = roundup(sr_entries /
3075                                      i965_cursor_wm_info.cacheline_size, 1);
3076                 cursor_sr = i965_cursor_wm_info.fifo_size -
3077                             (sr_entries + i965_cursor_wm_info.guard_size);
3078
3079                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3080                         cursor_sr = i965_cursor_wm_info.max_wm;
3081
3082                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3083                               "cursor %d\n", srwm, cursor_sr);
3084
3085                 if (IS_I965GM(dev))
3086                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3087         } else {
3088                 /* Turn off self refresh if both pipes are enabled */
3089                 if (IS_I965GM(dev))
3090                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3091                                    & ~FW_BLC_SELF_EN);
3092         }
3093
3094         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3095                       srwm);
3096
3097         /* 965 has limitations... */
3098         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3099                    (8 << 0));
3100         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3101         /* update cursor SR watermark */
3102         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3103 }
3104
3105 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3106                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3107                            int pixel_size)
3108 {
3109         struct drm_i915_private *dev_priv = dev->dev_private;
3110         uint32_t fwater_lo;
3111         uint32_t fwater_hi;
3112         int total_size, cacheline_size, cwm, srwm = 1;
3113         int planea_wm, planeb_wm;
3114         struct intel_watermark_params planea_params, planeb_params;
3115         unsigned long line_time_us;
3116         int sr_clock, sr_entries = 0;
3117
3118         /* Create copies of the base settings for each pipe */
3119         if (IS_I965GM(dev) || IS_I945GM(dev))
3120                 planea_params = planeb_params = i945_wm_info;
3121         else if (IS_I9XX(dev))
3122                 planea_params = planeb_params = i915_wm_info;
3123         else
3124                 planea_params = planeb_params = i855_wm_info;
3125
3126         /* Grab a couple of global values before we overwrite them */
3127         total_size = planea_params.fifo_size;
3128         cacheline_size = planea_params.cacheline_size;
3129
3130         /* Update per-plane FIFO sizes */
3131         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3132         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3133
3134         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3135                                        pixel_size, latency_ns);
3136         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3137                                        pixel_size, latency_ns);
3138         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3139
3140         /*
3141          * Overlay gets an aggressive default since video jitter is bad.
3142          */
3143         cwm = 2;
3144
3145         /* Calc sr entries for one plane configs */
3146         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3147             (!planea_clock || !planeb_clock)) {
3148                 /* self-refresh has much higher latency */
3149                 static const int sr_latency_ns = 6000;
3150
3151                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3152                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3153
3154                 /* Use ns/us then divide to preserve precision */
3155                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3156                               pixel_size * sr_hdisplay;
3157                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3158                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3159                 srwm = total_size - sr_entries;
3160                 if (srwm < 0)
3161                         srwm = 1;
3162
3163                 if (IS_I945G(dev) || IS_I945GM(dev))
3164                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3165                 else if (IS_I915GM(dev)) {
3166                         /* 915M has a smaller SRWM field */
3167                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3168                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3169                 }
3170         } else {
3171                 /* Turn off self refresh if both pipes are enabled */
3172                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3173                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3174                                    & ~FW_BLC_SELF_EN);
3175                 } else if (IS_I915GM(dev)) {
3176                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3177                 }
3178         }
3179
3180         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3181                   planea_wm, planeb_wm, cwm, srwm);
3182
3183         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3184         fwater_hi = (cwm & 0x1f);
3185
3186         /* Set request length to 8 cachelines per fetch */
3187         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3188         fwater_hi = fwater_hi | (1 << 8);
3189
3190         I915_WRITE(FW_BLC, fwater_lo);
3191         I915_WRITE(FW_BLC2, fwater_hi);
3192 }
3193
3194 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3195                            int unused2, int unused3, int pixel_size)
3196 {
3197         struct drm_i915_private *dev_priv = dev->dev_private;
3198         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3199         int planea_wm;
3200
3201         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3202
3203         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3204                                        pixel_size, latency_ns);
3205         fwater_lo |= (3<<8) | planea_wm;
3206
3207         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3208
3209         I915_WRITE(FW_BLC, fwater_lo);
3210 }
3211
3212 #define ILK_LP0_PLANE_LATENCY           700
3213 #define ILK_LP0_CURSOR_LATENCY          1300
3214
3215 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3216                        int planeb_clock, int sr_hdisplay, int sr_htotal,
3217                        int pixel_size)
3218 {
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3221         int sr_wm, cursor_wm;
3222         unsigned long line_time_us;
3223         int sr_clock, entries_required;
3224         u32 reg_value;
3225         int line_count;
3226         int planea_htotal = 0, planeb_htotal = 0;
3227         struct drm_crtc *crtc;
3228         struct intel_crtc *intel_crtc;
3229
3230         /* Need htotal for all active display plane */
3231         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3232                 intel_crtc = to_intel_crtc(crtc);
3233                 if (crtc->enabled) {
3234                         if (intel_crtc->plane == 0)
3235                                 planea_htotal = crtc->mode.htotal;
3236                         else
3237                                 planeb_htotal = crtc->mode.htotal;
3238                 }
3239         }
3240
3241         /* Calculate and update the watermark for plane A */
3242         if (planea_clock) {
3243                 entries_required = ((planea_clock / 1000) * pixel_size *
3244                                      ILK_LP0_PLANE_LATENCY) / 1000;
3245                 entries_required = DIV_ROUND_UP(entries_required,
3246                                    ironlake_display_wm_info.cacheline_size);
3247                 planea_wm = entries_required +
3248                             ironlake_display_wm_info.guard_size;
3249
3250                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3251                         planea_wm = ironlake_display_wm_info.max_wm;
3252
3253                 /* Use the large buffer method to calculate cursor watermark */
3254                 line_time_us = (planea_htotal * 1000) / planea_clock;
3255
3256                 /* Use ns/us then divide to preserve precision */
3257                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3258
3259                 /* calculate the cursor watermark for cursor A */
3260                 entries_required = line_count * 64 * pixel_size;
3261                 entries_required = DIV_ROUND_UP(entries_required,
3262                                                 ironlake_cursor_wm_info.cacheline_size);
3263                 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3264                 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3265                         cursora_wm = ironlake_cursor_wm_info.max_wm;
3266
3267                 reg_value = I915_READ(WM0_PIPEA_ILK);
3268                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3269                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3270                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3271                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3272                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3273                                 "cursor: %d\n", planea_wm, cursora_wm);
3274         }
3275         /* Calculate and update the watermark for plane B */
3276         if (planeb_clock) {
3277                 entries_required = ((planeb_clock / 1000) * pixel_size *
3278                                      ILK_LP0_PLANE_LATENCY) / 1000;
3279                 entries_required = DIV_ROUND_UP(entries_required,
3280                                    ironlake_display_wm_info.cacheline_size);
3281                 planeb_wm = entries_required +
3282                             ironlake_display_wm_info.guard_size;
3283
3284                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3285                         planeb_wm = ironlake_display_wm_info.max_wm;
3286
3287                 /* Use the large buffer method to calculate cursor watermark */
3288                 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3289
3290                 /* Use ns/us then divide to preserve precision */
3291                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3292
3293                 /* calculate the cursor watermark for cursor B */
3294                 entries_required = line_count * 64 * pixel_size;
3295                 entries_required = DIV_ROUND_UP(entries_required,
3296                                                 ironlake_cursor_wm_info.cacheline_size);
3297                 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3298                 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3299                         cursorb_wm = ironlake_cursor_wm_info.max_wm;
3300
3301                 reg_value = I915_READ(WM0_PIPEB_ILK);
3302                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3303                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3304                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3305                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3306                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3307                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3308         }
3309
3310         /*
3311          * Calculate and update the self-refresh watermark only when one
3312          * display plane is used.
3313          */
3314         if (!planea_clock || !planeb_clock) {
3315
3316                 /* Read the self-refresh latency. The unit is 0.5us */
3317                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3318
3319                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3320                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3321
3322                 /* Use ns/us then divide to preserve precision */
3323                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3324                                / 1000;
3325
3326                 /* calculate the self-refresh watermark for display plane */
3327                 entries_required = line_count * sr_hdisplay * pixel_size;
3328                 entries_required = DIV_ROUND_UP(entries_required,
3329                                    ironlake_display_srwm_info.cacheline_size);
3330                 sr_wm = entries_required +
3331                         ironlake_display_srwm_info.guard_size;
3332
3333                 /* calculate the self-refresh watermark for display cursor */
3334                 entries_required = line_count * pixel_size * 64;
3335                 entries_required = DIV_ROUND_UP(entries_required,
3336                                    ironlake_cursor_srwm_info.cacheline_size);
3337                 cursor_wm = entries_required +
3338                             ironlake_cursor_srwm_info.guard_size;
3339
3340                 /* configure watermark and enable self-refresh */
3341                 reg_value = I915_READ(WM1_LP_ILK);
3342                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3343                                WM1_LP_CURSOR_MASK);
3344                 reg_value |= WM1_LP_SR_EN |
3345                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3346                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3347
3348                 I915_WRITE(WM1_LP_ILK, reg_value);
3349                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3350                                 "cursor %d\n", sr_wm, cursor_wm);
3351
3352         } else {
3353                 /* Turn off self refresh if both pipes are enabled */
3354                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3355         }
3356 }
3357 /**
3358  * intel_update_watermarks - update FIFO watermark values based on current modes
3359  *
3360  * Calculate watermark values for the various WM regs based on current mode
3361  * and plane configuration.
3362  *
3363  * There are several cases to deal with here:
3364  *   - normal (i.e. non-self-refresh)
3365  *   - self-refresh (SR) mode
3366  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3367  *   - lines are small relative to FIFO size (buffer can hold more than 2
3368  *     lines), so need to account for TLB latency
3369  *
3370  *   The normal calculation is:
3371  *     watermark = dotclock * bytes per pixel * latency
3372  *   where latency is platform & configuration dependent (we assume pessimal
3373  *   values here).
3374  *
3375  *   The SR calculation is:
3376  *     watermark = (trunc(latency/line time)+1) * surface width *
3377  *       bytes per pixel
3378  *   where
3379  *     line time = htotal / dotclock
3380  *     surface width = hdisplay for normal plane and 64 for cursor
3381  *   and latency is assumed to be high, as above.
3382  *
3383  * The final value programmed to the register should always be rounded up,
3384  * and include an extra 2 entries to account for clock crossings.
3385  *
3386  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3387  * to set the non-SR watermarks to 8.
3388   */
3389 static void intel_update_watermarks(struct drm_device *dev)
3390 {
3391         struct drm_i915_private *dev_priv = dev->dev_private;
3392         struct drm_crtc *crtc;
3393         struct intel_crtc *intel_crtc;
3394         int sr_hdisplay = 0;
3395         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3396         int enabled = 0, pixel_size = 0;
3397         int sr_htotal = 0;
3398
3399         if (!dev_priv->display.update_wm)
3400                 return;
3401
3402         /* Get the clock config from both planes */
3403         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3404                 intel_crtc = to_intel_crtc(crtc);
3405                 if (crtc->enabled) {
3406                         enabled++;
3407                         if (intel_crtc->plane == 0) {
3408                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3409                                           intel_crtc->pipe, crtc->mode.clock);
3410                                 planea_clock = crtc->mode.clock;
3411                         } else {
3412                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3413                                           intel_crtc->pipe, crtc->mode.clock);
3414                                 planeb_clock = crtc->mode.clock;
3415                         }
3416                         sr_hdisplay = crtc->mode.hdisplay;
3417                         sr_clock = crtc->mode.clock;
3418                         sr_htotal = crtc->mode.htotal;
3419                         if (crtc->fb)
3420                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3421                         else
3422                                 pixel_size = 4; /* by default */
3423                 }
3424         }
3425
3426         if (enabled <= 0)
3427                 return;
3428
3429         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3430                                     sr_hdisplay, sr_htotal, pixel_size);
3431 }
3432
3433 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3434                                struct drm_display_mode *mode,
3435                                struct drm_display_mode *adjusted_mode,
3436                                int x, int y,
3437                                struct drm_framebuffer *old_fb)
3438 {
3439         struct drm_device *dev = crtc->dev;
3440         struct drm_i915_private *dev_priv = dev->dev_private;
3441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3442         int pipe = intel_crtc->pipe;
3443         int plane = intel_crtc->plane;
3444         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3445         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3446         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3447         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3448         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3449         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3450         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3451         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3452         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3453         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3454         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3455         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3456         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3457         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3458         int refclk, num_connectors = 0;
3459         intel_clock_t clock, reduced_clock;
3460         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3461         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3462         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3463         bool is_edp = false;
3464         struct drm_mode_config *mode_config = &dev->mode_config;
3465         struct drm_encoder *encoder;
3466         struct intel_encoder *intel_encoder = NULL;
3467         const intel_limit_t *limit;
3468         int ret;
3469         struct fdi_m_n m_n = {0};
3470         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3471         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3472         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3473         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3474         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3475         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3476         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3477         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3478         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3479         int lvds_reg = LVDS;
3480         u32 temp;
3481         int sdvo_pixel_multiply;
3482         int target_clock;
3483
3484         drm_vblank_pre_modeset(dev, pipe);
3485
3486         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3487
3488                 if (!encoder || encoder->crtc != crtc)
3489                         continue;
3490
3491                 intel_encoder = enc_to_intel_encoder(encoder);
3492
3493                 switch (intel_encoder->type) {
3494                 case INTEL_OUTPUT_LVDS:
3495                         is_lvds = true;
3496                         break;
3497                 case INTEL_OUTPUT_SDVO:
3498                 case INTEL_OUTPUT_HDMI:
3499                         is_sdvo = true;
3500                         if (intel_encoder->needs_tv_clock)
3501                                 is_tv = true;
3502                         break;
3503                 case INTEL_OUTPUT_DVO:
3504                         is_dvo = true;
3505                         break;
3506                 case INTEL_OUTPUT_TVOUT:
3507                         is_tv = true;
3508                         break;
3509                 case INTEL_OUTPUT_ANALOG:
3510                         is_crt = true;
3511                         break;
3512                 case INTEL_OUTPUT_DISPLAYPORT:
3513                         is_dp = true;
3514                         break;
3515                 case INTEL_OUTPUT_EDP:
3516                         is_edp = true;
3517                         break;
3518                 }
3519
3520                 num_connectors++;
3521         }
3522
3523         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3524                 refclk = dev_priv->lvds_ssc_freq * 1000;
3525                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3526                                         refclk / 1000);
3527         } else if (IS_I9XX(dev)) {
3528                 refclk = 96000;
3529                 if (HAS_PCH_SPLIT(dev))
3530                         refclk = 120000; /* 120Mhz refclk */
3531         } else {
3532                 refclk = 48000;
3533         }
3534
3535
3536         /*
3537          * Returns a set of divisors for the desired target clock with the given
3538          * refclk, or FALSE.  The returned values represent the clock equation:
3539          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3540          */
3541         limit = intel_limit(crtc);
3542         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3543         if (!ok) {
3544                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3545                 drm_vblank_post_modeset(dev, pipe);
3546                 return -EINVAL;
3547         }
3548
3549         if (is_lvds && dev_priv->lvds_downclock_avail) {
3550                 has_reduced_clock = limit->find_pll(limit, crtc,
3551                                                             dev_priv->lvds_downclock,
3552                                                             refclk,
3553                                                             &reduced_clock);
3554                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3555                         /*
3556                          * If the different P is found, it means that we can't
3557                          * switch the display clock by using the FP0/FP1.
3558                          * In such case we will disable the LVDS downclock
3559                          * feature.
3560                          */
3561                         DRM_DEBUG_KMS("Different P is found for "
3562                                                 "LVDS clock/downclock\n");
3563                         has_reduced_clock = 0;
3564                 }
3565         }
3566         /* SDVO TV has fixed PLL values depend on its clock range,
3567            this mirrors vbios setting. */
3568         if (is_sdvo && is_tv) {
3569                 if (adjusted_mode->clock >= 100000
3570                                 && adjusted_mode->clock < 140500) {
3571                         clock.p1 = 2;
3572                         clock.p2 = 10;
3573                         clock.n = 3;
3574                         clock.m1 = 16;
3575                         clock.m2 = 8;
3576                 } else if (adjusted_mode->clock >= 140500
3577                                 && adjusted_mode->clock <= 200000) {
3578                         clock.p1 = 1;
3579                         clock.p2 = 10;
3580                         clock.n = 6;
3581                         clock.m1 = 12;
3582                         clock.m2 = 8;
3583                 }
3584         }
3585
3586         /* FDI link */
3587         if (HAS_PCH_SPLIT(dev)) {
3588                 int lane = 0, link_bw, bpp;
3589                 /* eDP doesn't require FDI link, so just set DP M/N
3590                    according to current link config */
3591                 if (is_edp) {
3592                         target_clock = mode->clock;
3593                         intel_edp_link_config(intel_encoder,
3594                                         &lane, &link_bw);
3595                 } else {
3596                         /* DP over FDI requires target mode clock
3597                            instead of link clock */
3598                         if (is_dp)
3599                                 target_clock = mode->clock;
3600                         else
3601                                 target_clock = adjusted_mode->clock;
3602                         link_bw = 270000;
3603                 }
3604
3605                 /* determine panel color depth */
3606                 temp = I915_READ(pipeconf_reg);
3607                 temp &= ~PIPE_BPC_MASK;
3608                 if (is_lvds) {
3609                         int lvds_reg = I915_READ(PCH_LVDS);
3610                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3611                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3612                                 temp |= PIPE_8BPC;
3613                         else
3614                                 temp |= PIPE_6BPC;
3615                 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3616                         switch (dev_priv->edp_bpp/3) {
3617                         case 8:
3618                                 temp |= PIPE_8BPC;
3619                                 break;
3620                         case 10:
3621                                 temp |= PIPE_10BPC;
3622                                 break;
3623                         case 6:
3624                                 temp |= PIPE_6BPC;
3625                                 break;
3626                         case 12:
3627                                 temp |= PIPE_12BPC;
3628                                 break;
3629                         }
3630                 } else
3631                         temp |= PIPE_8BPC;
3632                 I915_WRITE(pipeconf_reg, temp);
3633                 I915_READ(pipeconf_reg);
3634
3635                 switch (temp & PIPE_BPC_MASK) {
3636                 case PIPE_8BPC:
3637                         bpp = 24;
3638                         break;
3639                 case PIPE_10BPC:
3640                         bpp = 30;
3641                         break;
3642                 case PIPE_6BPC:
3643                         bpp = 18;
3644                         break;
3645                 case PIPE_12BPC:
3646                         bpp = 36;
3647                         break;
3648                 default:
3649                         DRM_ERROR("unknown pipe bpc value\n");
3650                         bpp = 24;
3651                 }
3652
3653                 if (!lane) {
3654                         /*
3655                          * Account for spread spectrum to avoid
3656                          * oversubscribing the link. Max center spread
3657                          * is 2.5%; use 5% for safety's sake.
3658                          */
3659                         u32 bps = target_clock * bpp * 21 / 20;
3660                         lane = bps / (link_bw * 8) + 1;
3661                 }
3662
3663                 intel_crtc->fdi_lanes = lane;
3664
3665                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3666         }
3667
3668         /* Ironlake: try to setup display ref clock before DPLL
3669          * enabling. This is only under driver's control after
3670          * PCH B stepping, previous chipset stepping should be
3671          * ignoring this setting.
3672          */
3673         if (HAS_PCH_SPLIT(dev)) {
3674                 temp = I915_READ(PCH_DREF_CONTROL);
3675                 /* Always enable nonspread source */
3676                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3677                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3678                 I915_WRITE(PCH_DREF_CONTROL, temp);
3679                 POSTING_READ(PCH_DREF_CONTROL);
3680
3681                 temp &= ~DREF_SSC_SOURCE_MASK;
3682                 temp |= DREF_SSC_SOURCE_ENABLE;
3683                 I915_WRITE(PCH_DREF_CONTROL, temp);
3684                 POSTING_READ(PCH_DREF_CONTROL);
3685
3686                 udelay(200);
3687
3688                 if (is_edp) {
3689                         if (dev_priv->lvds_use_ssc) {
3690                                 temp |= DREF_SSC1_ENABLE;
3691                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3692                                 POSTING_READ(PCH_DREF_CONTROL);
3693
3694                                 udelay(200);
3695
3696                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3697                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3698                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3699                                 POSTING_READ(PCH_DREF_CONTROL);
3700                         } else {
3701                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3702                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3703                                 POSTING_READ(PCH_DREF_CONTROL);
3704                         }
3705                 }
3706         }
3707
3708         if (IS_PINEVIEW(dev)) {
3709                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3710                 if (has_reduced_clock)
3711                         fp2 = (1 << reduced_clock.n) << 16 |
3712                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3713         } else {
3714                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3715                 if (has_reduced_clock)
3716                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3717                                 reduced_clock.m2;
3718         }
3719
3720         if (!HAS_PCH_SPLIT(dev))
3721                 dpll = DPLL_VGA_MODE_DIS;
3722
3723         if (IS_I9XX(dev)) {
3724                 if (is_lvds)
3725                         dpll |= DPLLB_MODE_LVDS;
3726                 else
3727                         dpll |= DPLLB_MODE_DAC_SERIAL;
3728                 if (is_sdvo) {
3729                         dpll |= DPLL_DVO_HIGH_SPEED;
3730                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3731                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3732                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3733                         else if (HAS_PCH_SPLIT(dev))
3734                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3735                 }
3736                 if (is_dp)
3737                         dpll |= DPLL_DVO_HIGH_SPEED;
3738
3739                 /* compute bitmask from p1 value */
3740                 if (IS_PINEVIEW(dev))
3741                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3742                 else {
3743                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3744                         /* also FPA1 */
3745                         if (HAS_PCH_SPLIT(dev))
3746                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3747                         if (IS_G4X(dev) && has_reduced_clock)
3748                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3749                 }
3750                 switch (clock.p2) {
3751                 case 5:
3752                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3753                         break;
3754                 case 7:
3755                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3756                         break;
3757                 case 10:
3758                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3759                         break;
3760                 case 14:
3761                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3762                         break;
3763                 }
3764                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3765                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3766         } else {
3767                 if (is_lvds) {
3768                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3769                 } else {
3770                         if (clock.p1 == 2)
3771                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3772                         else
3773                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3774                         if (clock.p2 == 4)
3775                                 dpll |= PLL_P2_DIVIDE_BY_4;
3776                 }
3777         }
3778
3779         if (is_sdvo && is_tv)
3780                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3781         else if (is_tv)
3782                 /* XXX: just matching BIOS for now */
3783                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3784                 dpll |= 3;
3785         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3786                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3787         else
3788                 dpll |= PLL_REF_INPUT_DREFCLK;
3789
3790         /* setup pipeconf */
3791         pipeconf = I915_READ(pipeconf_reg);
3792
3793         /* Set up the display plane register */
3794         dspcntr = DISPPLANE_GAMMA_ENABLE;
3795
3796         /* Ironlake's plane is forced to pipe, bit 24 is to
3797            enable color space conversion */
3798         if (!HAS_PCH_SPLIT(dev)) {
3799                 if (pipe == 0)
3800                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3801                 else
3802                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3803         }
3804
3805         if (pipe == 0 && !IS_I965G(dev)) {
3806                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3807                  * core speed.
3808                  *
3809                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3810                  * pipe == 0 check?
3811                  */
3812                 if (mode->clock >
3813                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3814                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3815                 else
3816                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3817         }
3818
3819         dspcntr |= DISPLAY_PLANE_ENABLE;
3820         pipeconf |= PIPEACONF_ENABLE;
3821         dpll |= DPLL_VCO_ENABLE;
3822
3823
3824         /* Disable the panel fitter if it was on our pipe */
3825         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3826                 I915_WRITE(PFIT_CONTROL, 0);
3827
3828         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3829         drm_mode_debug_printmodeline(mode);
3830
3831         /* assign to Ironlake registers */
3832         if (HAS_PCH_SPLIT(dev)) {
3833                 fp_reg = pch_fp_reg;
3834                 dpll_reg = pch_dpll_reg;
3835         }
3836
3837         if (is_edp) {
3838                 ironlake_disable_pll_edp(crtc);
3839         } else if ((dpll & DPLL_VCO_ENABLE)) {
3840                 I915_WRITE(fp_reg, fp);
3841                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3842                 I915_READ(dpll_reg);
3843                 udelay(150);
3844         }
3845
3846         /* enable transcoder DPLL */
3847         if (HAS_PCH_CPT(dev)) {
3848                 temp = I915_READ(PCH_DPLL_SEL);
3849                 if (trans_dpll_sel == 0)
3850                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3851                 else
3852                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3853                 I915_WRITE(PCH_DPLL_SEL, temp);
3854                 I915_READ(PCH_DPLL_SEL);
3855                 udelay(150);
3856         }
3857
3858         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3859          * This is an exception to the general rule that mode_set doesn't turn
3860          * things on.
3861          */
3862         if (is_lvds) {
3863                 u32 lvds;
3864
3865                 if (HAS_PCH_SPLIT(dev))
3866                         lvds_reg = PCH_LVDS;
3867
3868                 lvds = I915_READ(lvds_reg);
3869                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3870                 if (pipe == 1) {
3871                         if (HAS_PCH_CPT(dev))
3872                                 lvds |= PORT_TRANS_B_SEL_CPT;
3873                         else
3874                                 lvds |= LVDS_PIPEB_SELECT;
3875                 } else {
3876                         if (HAS_PCH_CPT(dev))
3877                                 lvds &= ~PORT_TRANS_SEL_MASK;
3878                         else
3879                                 lvds &= ~LVDS_PIPEB_SELECT;
3880                 }
3881                 /* set the corresponsding LVDS_BORDER bit */
3882                 lvds |= dev_priv->lvds_border_bits;
3883                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3884                  * set the DPLLs for dual-channel mode or not.
3885                  */
3886                 if (clock.p2 == 7)
3887                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3888                 else
3889                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3890
3891                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3892                  * appropriately here, but we need to look more thoroughly into how
3893                  * panels behave in the two modes.
3894                  */
3895                 /* set the dithering flag */
3896                 if (IS_I965G(dev)) {
3897                         if (dev_priv->lvds_dither) {
3898                                 if (HAS_PCH_SPLIT(dev)) {
3899                                         pipeconf |= PIPE_ENABLE_DITHER;
3900                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
3901                                 } else
3902                                         lvds |= LVDS_ENABLE_DITHER;
3903                         } else {
3904                                 if (HAS_PCH_SPLIT(dev)) {
3905                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3906                                         pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3907                                 } else
3908                                         lvds &= ~LVDS_ENABLE_DITHER;
3909                         }
3910                 }
3911                 I915_WRITE(lvds_reg, lvds);
3912                 I915_READ(lvds_reg);
3913         }
3914         if (is_dp)
3915                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3916         else if (HAS_PCH_SPLIT(dev)) {
3917                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3918                 if (pipe == 0) {
3919                         I915_WRITE(TRANSA_DATA_M1, 0);
3920                         I915_WRITE(TRANSA_DATA_N1, 0);
3921                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3922                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3923                 } else {
3924                         I915_WRITE(TRANSB_DATA_M1, 0);
3925                         I915_WRITE(TRANSB_DATA_N1, 0);
3926                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3927                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3928                 }
3929         }
3930
3931         if (!is_edp) {
3932                 I915_WRITE(fp_reg, fp);
3933                 I915_WRITE(dpll_reg, dpll);
3934                 I915_READ(dpll_reg);
3935                 /* Wait for the clocks to stabilize. */
3936                 udelay(150);
3937
3938                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3939                         if (is_sdvo) {
3940                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3941                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3942                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3943                         } else
3944                                 I915_WRITE(dpll_md_reg, 0);
3945                 } else {
3946                         /* write it again -- the BIOS does, after all */
3947                         I915_WRITE(dpll_reg, dpll);
3948                 }
3949                 I915_READ(dpll_reg);
3950                 /* Wait for the clocks to stabilize. */
3951                 udelay(150);
3952         }
3953
3954         if (is_lvds && has_reduced_clock && i915_powersave) {
3955                 I915_WRITE(fp_reg + 4, fp2);
3956                 intel_crtc->lowfreq_avail = true;
3957                 if (HAS_PIPE_CXSR(dev)) {
3958                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3959                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3960                 }
3961         } else {
3962                 I915_WRITE(fp_reg + 4, fp);
3963                 intel_crtc->lowfreq_avail = false;
3964                 if (HAS_PIPE_CXSR(dev)) {
3965                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3966                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3967                 }
3968         }
3969
3970         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3971                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3972                 /* the chip adds 2 halflines automatically */
3973                 adjusted_mode->crtc_vdisplay -= 1;
3974                 adjusted_mode->crtc_vtotal -= 1;
3975                 adjusted_mode->crtc_vblank_start -= 1;
3976                 adjusted_mode->crtc_vblank_end -= 1;
3977                 adjusted_mode->crtc_vsync_end -= 1;
3978                 adjusted_mode->crtc_vsync_start -= 1;
3979         } else
3980                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
3981
3982         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3983                    ((adjusted_mode->crtc_htotal - 1) << 16));
3984         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3985                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3986         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3987                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3988         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3989                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3990         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3991                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3992         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3993                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3994         /* pipesrc and dspsize control the size that is scaled from, which should
3995          * always be the user's requested size.
3996          */
3997         if (!HAS_PCH_SPLIT(dev)) {
3998                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3999                                 (mode->hdisplay - 1));
4000                 I915_WRITE(dsppos_reg, 0);
4001         }
4002         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4003
4004         if (HAS_PCH_SPLIT(dev)) {
4005                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4006                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4007                 I915_WRITE(link_m1_reg, m_n.link_m);
4008                 I915_WRITE(link_n1_reg, m_n.link_n);
4009
4010                 if (is_edp) {
4011                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4012                 } else {
4013                         /* enable FDI RX PLL too */
4014                         temp = I915_READ(fdi_rx_reg);
4015                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4016                         I915_READ(fdi_rx_reg);
4017                         udelay(200);
4018
4019                         /* enable FDI TX PLL too */
4020                         temp = I915_READ(fdi_tx_reg);
4021                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4022                         I915_READ(fdi_tx_reg);
4023
4024                         /* enable FDI RX PCDCLK */
4025                         temp = I915_READ(fdi_rx_reg);
4026                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4027                         I915_READ(fdi_rx_reg);
4028                         udelay(200);
4029                 }
4030         }
4031
4032         I915_WRITE(pipeconf_reg, pipeconf);
4033         I915_READ(pipeconf_reg);
4034
4035         intel_wait_for_vblank(dev);
4036
4037         if (IS_IRONLAKE(dev)) {
4038                 /* enable address swizzle for tiling buffer */
4039                 temp = I915_READ(DISP_ARB_CTL);
4040                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4041         }
4042
4043         I915_WRITE(dspcntr_reg, dspcntr);
4044
4045         /* Flush the plane changes */
4046         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4047
4048         if ((IS_I965G(dev) || plane == 0))
4049                 intel_update_fbc(crtc, &crtc->mode);
4050
4051         intel_update_watermarks(dev);
4052
4053         drm_vblank_post_modeset(dev, pipe);
4054
4055         return ret;
4056 }
4057
4058 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4059 void intel_crtc_load_lut(struct drm_crtc *crtc)
4060 {
4061         struct drm_device *dev = crtc->dev;
4062         struct drm_i915_private *dev_priv = dev->dev_private;
4063         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4064         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4065         int i;
4066
4067         /* The clocks have to be on to load the palette. */
4068         if (!crtc->enabled)
4069                 return;
4070
4071         /* use legacy palette for Ironlake */
4072         if (HAS_PCH_SPLIT(dev))
4073                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4074                                                    LGC_PALETTE_B;
4075
4076         for (i = 0; i < 256; i++) {
4077                 I915_WRITE(palreg + 4 * i,
4078                            (intel_crtc->lut_r[i] << 16) |
4079                            (intel_crtc->lut_g[i] << 8) |
4080                            intel_crtc->lut_b[i]);
4081         }
4082 }
4083
4084 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4085                                  struct drm_file *file_priv,
4086                                  uint32_t handle,
4087                                  uint32_t width, uint32_t height)
4088 {
4089         struct drm_device *dev = crtc->dev;
4090         struct drm_i915_private *dev_priv = dev->dev_private;
4091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4092         struct drm_gem_object *bo;
4093         struct drm_i915_gem_object *obj_priv;
4094         int pipe = intel_crtc->pipe;
4095         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
4096         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
4097         uint32_t temp = I915_READ(control);
4098         size_t addr;
4099         int ret;
4100
4101         DRM_DEBUG_KMS("\n");
4102
4103         /* if we want to turn off the cursor ignore width and height */
4104         if (!handle) {
4105                 DRM_DEBUG_KMS("cursor off\n");
4106                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4107                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4108                         temp |= CURSOR_MODE_DISABLE;
4109                 } else {
4110                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4111                 }
4112                 addr = 0;
4113                 bo = NULL;
4114                 mutex_lock(&dev->struct_mutex);
4115                 goto finish;
4116         }
4117
4118         /* Currently we only support 64x64 cursors */
4119         if (width != 64 || height != 64) {
4120                 DRM_ERROR("we currently only support 64x64 cursors\n");
4121                 return -EINVAL;
4122         }
4123
4124         bo = drm_gem_object_lookup(dev, file_priv, handle);
4125         if (!bo)
4126                 return -ENOENT;
4127
4128         obj_priv = to_intel_bo(bo);
4129
4130         if (bo->size < width * height * 4) {
4131                 DRM_ERROR("buffer is to small\n");
4132                 ret = -ENOMEM;
4133                 goto fail;
4134         }
4135
4136         /* we only need to pin inside GTT if cursor is non-phy */
4137         mutex_lock(&dev->struct_mutex);
4138         if (!dev_priv->info->cursor_needs_physical) {
4139                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4140                 if (ret) {
4141                         DRM_ERROR("failed to pin cursor bo\n");
4142                         goto fail_locked;
4143                 }
4144
4145                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4146                 if (ret) {
4147                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4148                         goto fail_unpin;
4149                 }
4150
4151                 addr = obj_priv->gtt_offset;
4152         } else {
4153                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
4154                 if (ret) {
4155                         DRM_ERROR("failed to attach phys object\n");
4156                         goto fail_locked;
4157                 }
4158                 addr = obj_priv->phys_obj->handle->busaddr;
4159         }
4160
4161         if (!IS_I9XX(dev))
4162                 I915_WRITE(CURSIZE, (height << 12) | width);
4163
4164         /* Hooray for CUR*CNTR differences */
4165         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4166                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4167                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4168                 temp |= (pipe << 28); /* Connect to correct pipe */
4169         } else {
4170                 temp &= ~(CURSOR_FORMAT_MASK);
4171                 temp |= CURSOR_ENABLE;
4172                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4173         }
4174
4175  finish:
4176         I915_WRITE(control, temp);
4177         I915_WRITE(base, addr);
4178
4179         if (intel_crtc->cursor_bo) {
4180                 if (dev_priv->info->cursor_needs_physical) {
4181                         if (intel_crtc->cursor_bo != bo)
4182                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4183                 } else
4184                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4185                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4186         }
4187
4188         mutex_unlock(&dev->struct_mutex);
4189
4190         intel_crtc->cursor_addr = addr;
4191         intel_crtc->cursor_bo = bo;
4192
4193         return 0;
4194 fail_unpin:
4195         i915_gem_object_unpin(bo);
4196 fail_locked:
4197         mutex_unlock(&dev->struct_mutex);
4198 fail:
4199         drm_gem_object_unreference_unlocked(bo);
4200         return ret;
4201 }
4202
4203 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4204 {
4205         struct drm_device *dev = crtc->dev;
4206         struct drm_i915_private *dev_priv = dev->dev_private;
4207         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4208         struct intel_framebuffer *intel_fb;
4209         int pipe = intel_crtc->pipe;
4210         uint32_t temp = 0;
4211         uint32_t adder;
4212
4213         if (crtc->fb) {
4214                 intel_fb = to_intel_framebuffer(crtc->fb);
4215                 intel_mark_busy(dev, intel_fb->obj);
4216         }
4217
4218         if (x < 0) {
4219                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4220                 x = -x;
4221         }
4222         if (y < 0) {
4223                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4224                 y = -y;
4225         }
4226
4227         temp |= x << CURSOR_X_SHIFT;
4228         temp |= y << CURSOR_Y_SHIFT;
4229
4230         adder = intel_crtc->cursor_addr;
4231         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
4232         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
4233
4234         return 0;
4235 }
4236
4237 /** Sets the color ramps on behalf of RandR */
4238 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4239                                  u16 blue, int regno)
4240 {
4241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4242
4243         intel_crtc->lut_r[regno] = red >> 8;
4244         intel_crtc->lut_g[regno] = green >> 8;
4245         intel_crtc->lut_b[regno] = blue >> 8;
4246 }
4247
4248 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4249                              u16 *blue, int regno)
4250 {
4251         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4252
4253         *red = intel_crtc->lut_r[regno] << 8;
4254         *green = intel_crtc->lut_g[regno] << 8;
4255         *blue = intel_crtc->lut_b[regno] << 8;
4256 }
4257
4258 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4259                                  u16 *blue, uint32_t size)
4260 {
4261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4262         int i;
4263
4264         if (size != 256)
4265                 return;
4266
4267         for (i = 0; i < 256; i++) {
4268                 intel_crtc->lut_r[i] = red[i] >> 8;
4269                 intel_crtc->lut_g[i] = green[i] >> 8;
4270                 intel_crtc->lut_b[i] = blue[i] >> 8;
4271         }
4272
4273         intel_crtc_load_lut(crtc);
4274 }
4275
4276 /**
4277  * Get a pipe with a simple mode set on it for doing load-based monitor
4278  * detection.
4279  *
4280  * It will be up to the load-detect code to adjust the pipe as appropriate for
4281  * its requirements.  The pipe will be connected to no other encoders.
4282  *
4283  * Currently this code will only succeed if there is a pipe with no encoders
4284  * configured for it.  In the future, it could choose to temporarily disable
4285  * some outputs to free up a pipe for its use.
4286  *
4287  * \return crtc, or NULL if no pipes are available.
4288  */
4289
4290 /* VESA 640x480x72Hz mode to set on the pipe */
4291 static struct drm_display_mode load_detect_mode = {
4292         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4293                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4294 };
4295
4296 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4297                                             struct drm_connector *connector,
4298                                             struct drm_display_mode *mode,
4299                                             int *dpms_mode)
4300 {
4301         struct intel_crtc *intel_crtc;
4302         struct drm_crtc *possible_crtc;
4303         struct drm_crtc *supported_crtc =NULL;
4304         struct drm_encoder *encoder = &intel_encoder->enc;
4305         struct drm_crtc *crtc = NULL;
4306         struct drm_device *dev = encoder->dev;
4307         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4308         struct drm_crtc_helper_funcs *crtc_funcs;
4309         int i = -1;
4310
4311         /*
4312          * Algorithm gets a little messy:
4313          *   - if the connector already has an assigned crtc, use it (but make
4314          *     sure it's on first)
4315          *   - try to find the first unused crtc that can drive this connector,
4316          *     and use that if we find one
4317          *   - if there are no unused crtcs available, try to use the first
4318          *     one we found that supports the connector
4319          */
4320
4321         /* See if we already have a CRTC for this connector */
4322         if (encoder->crtc) {
4323                 crtc = encoder->crtc;
4324                 /* Make sure the crtc and connector are running */
4325                 intel_crtc = to_intel_crtc(crtc);
4326                 *dpms_mode = intel_crtc->dpms_mode;
4327                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4328                         crtc_funcs = crtc->helper_private;
4329                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4330                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4331                 }
4332                 return crtc;
4333         }
4334
4335         /* Find an unused one (if possible) */
4336         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4337                 i++;
4338                 if (!(encoder->possible_crtcs & (1 << i)))
4339                         continue;
4340                 if (!possible_crtc->enabled) {
4341                         crtc = possible_crtc;
4342                         break;
4343                 }
4344                 if (!supported_crtc)
4345                         supported_crtc = possible_crtc;
4346         }
4347
4348         /*
4349          * If we didn't find an unused CRTC, don't use any.
4350          */
4351         if (!crtc) {
4352                 return NULL;
4353         }
4354
4355         encoder->crtc = crtc;
4356         connector->encoder = encoder;
4357         intel_encoder->load_detect_temp = true;
4358
4359         intel_crtc = to_intel_crtc(crtc);
4360         *dpms_mode = intel_crtc->dpms_mode;
4361
4362         if (!crtc->enabled) {
4363                 if (!mode)
4364                         mode = &load_detect_mode;
4365                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4366         } else {
4367                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4368                         crtc_funcs = crtc->helper_private;
4369                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4370                 }
4371
4372                 /* Add this connector to the crtc */
4373                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4374                 encoder_funcs->commit(encoder);
4375         }
4376         /* let the connector get through one full cycle before testing */
4377         intel_wait_for_vblank(dev);
4378
4379         return crtc;
4380 }
4381
4382 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4383                                     struct drm_connector *connector, int dpms_mode)
4384 {
4385         struct drm_encoder *encoder = &intel_encoder->enc;
4386         struct drm_device *dev = encoder->dev;
4387         struct drm_crtc *crtc = encoder->crtc;
4388         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4389         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4390
4391         if (intel_encoder->load_detect_temp) {
4392                 encoder->crtc = NULL;
4393                 connector->encoder = NULL;
4394                 intel_encoder->load_detect_temp = false;
4395                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4396                 drm_helper_disable_unused_functions(dev);
4397         }
4398
4399         /* Switch crtc and encoder back off if necessary */
4400         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4401                 if (encoder->crtc == crtc)
4402                         encoder_funcs->dpms(encoder, dpms_mode);
4403                 crtc_funcs->dpms(crtc, dpms_mode);
4404         }
4405 }
4406
4407 /* Returns the clock of the currently programmed mode of the given pipe. */
4408 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4409 {
4410         struct drm_i915_private *dev_priv = dev->dev_private;
4411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4412         int pipe = intel_crtc->pipe;
4413         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4414         u32 fp;
4415         intel_clock_t clock;
4416
4417         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4418                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4419         else
4420                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4421
4422         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4423         if (IS_PINEVIEW(dev)) {
4424                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4425                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4426         } else {
4427                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4428                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4429         }
4430
4431         if (IS_I9XX(dev)) {
4432                 if (IS_PINEVIEW(dev))
4433                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4434                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4435                 else
4436                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4437                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4438
4439                 switch (dpll & DPLL_MODE_MASK) {
4440                 case DPLLB_MODE_DAC_SERIAL:
4441                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4442                                 5 : 10;
4443                         break;
4444                 case DPLLB_MODE_LVDS:
4445                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4446                                 7 : 14;
4447                         break;
4448                 default:
4449                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4450                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4451                         return 0;
4452                 }
4453
4454                 /* XXX: Handle the 100Mhz refclk */
4455                 intel_clock(dev, 96000, &clock);
4456         } else {
4457                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4458
4459                 if (is_lvds) {
4460                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4461                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4462                         clock.p2 = 14;
4463
4464                         if ((dpll & PLL_REF_INPUT_MASK) ==
4465                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4466                                 /* XXX: might not be 66MHz */
4467                                 intel_clock(dev, 66000, &clock);
4468                         } else
4469                                 intel_clock(dev, 48000, &clock);
4470                 } else {
4471                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4472                                 clock.p1 = 2;
4473                         else {
4474                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4475                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4476                         }
4477                         if (dpll & PLL_P2_DIVIDE_BY_4)
4478                                 clock.p2 = 4;
4479                         else
4480                                 clock.p2 = 2;
4481
4482                         intel_clock(dev, 48000, &clock);
4483                 }
4484         }
4485
4486         /* XXX: It would be nice to validate the clocks, but we can't reuse
4487          * i830PllIsValid() because it relies on the xf86_config connector
4488          * configuration being accurate, which it isn't necessarily.
4489          */
4490
4491         return clock.dot;
4492 }
4493
4494 /** Returns the currently programmed mode of the given pipe. */
4495 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4496                                              struct drm_crtc *crtc)
4497 {
4498         struct drm_i915_private *dev_priv = dev->dev_private;
4499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4500         int pipe = intel_crtc->pipe;
4501         struct drm_display_mode *mode;
4502         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4503         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4504         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4505         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4506
4507         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4508         if (!mode)
4509                 return NULL;
4510
4511         mode->clock = intel_crtc_clock_get(dev, crtc);
4512         mode->hdisplay = (htot & 0xffff) + 1;
4513         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4514         mode->hsync_start = (hsync & 0xffff) + 1;
4515         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4516         mode->vdisplay = (vtot & 0xffff) + 1;
4517         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4518         mode->vsync_start = (vsync & 0xffff) + 1;
4519         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4520
4521         drm_mode_set_name(mode);
4522         drm_mode_set_crtcinfo(mode, 0);
4523
4524         return mode;
4525 }
4526
4527 #define GPU_IDLE_TIMEOUT 500 /* ms */
4528
4529 /* When this timer fires, we've been idle for awhile */
4530 static void intel_gpu_idle_timer(unsigned long arg)
4531 {
4532         struct drm_device *dev = (struct drm_device *)arg;
4533         drm_i915_private_t *dev_priv = dev->dev_private;
4534
4535         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4536
4537         dev_priv->busy = false;
4538
4539         queue_work(dev_priv->wq, &dev_priv->idle_work);
4540 }
4541
4542 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4543
4544 static void intel_crtc_idle_timer(unsigned long arg)
4545 {
4546         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4547         struct drm_crtc *crtc = &intel_crtc->base;
4548         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4549
4550         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4551
4552         intel_crtc->busy = false;
4553
4554         queue_work(dev_priv->wq, &dev_priv->idle_work);
4555 }
4556
4557 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4558 {
4559         struct drm_device *dev = crtc->dev;
4560         drm_i915_private_t *dev_priv = dev->dev_private;
4561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4562         int pipe = intel_crtc->pipe;
4563         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4564         int dpll = I915_READ(dpll_reg);
4565
4566         if (HAS_PCH_SPLIT(dev))
4567                 return;
4568
4569         if (!dev_priv->lvds_downclock_avail)
4570                 return;
4571
4572         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4573                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4574
4575                 /* Unlock panel regs */
4576                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4577
4578                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4579                 I915_WRITE(dpll_reg, dpll);
4580                 dpll = I915_READ(dpll_reg);
4581                 intel_wait_for_vblank(dev);
4582                 dpll = I915_READ(dpll_reg);
4583                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4584                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4585
4586                 /* ...and lock them again */
4587                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4588         }
4589
4590         /* Schedule downclock */
4591         if (schedule)
4592                 mod_timer(&intel_crtc->idle_timer, jiffies +
4593                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4594 }
4595
4596 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4597 {
4598         struct drm_device *dev = crtc->dev;
4599         drm_i915_private_t *dev_priv = dev->dev_private;
4600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4601         int pipe = intel_crtc->pipe;
4602         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4603         int dpll = I915_READ(dpll_reg);
4604
4605         if (HAS_PCH_SPLIT(dev))
4606                 return;
4607
4608         if (!dev_priv->lvds_downclock_avail)
4609                 return;
4610
4611         /*
4612          * Since this is called by a timer, we should never get here in
4613          * the manual case.
4614          */
4615         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4616                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4617
4618                 /* Unlock panel regs */
4619                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4620
4621                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4622                 I915_WRITE(dpll_reg, dpll);
4623                 dpll = I915_READ(dpll_reg);
4624                 intel_wait_for_vblank(dev);
4625                 dpll = I915_READ(dpll_reg);
4626                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4627                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4628
4629                 /* ...and lock them again */
4630                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4631         }
4632
4633 }
4634
4635 /**
4636  * intel_idle_update - adjust clocks for idleness
4637  * @work: work struct
4638  *
4639  * Either the GPU or display (or both) went idle.  Check the busy status
4640  * here and adjust the CRTC and GPU clocks as necessary.
4641  */
4642 static void intel_idle_update(struct work_struct *work)
4643 {
4644         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4645                                                     idle_work);
4646         struct drm_device *dev = dev_priv->dev;
4647         struct drm_crtc *crtc;
4648         struct intel_crtc *intel_crtc;
4649         int enabled = 0;
4650
4651         if (!i915_powersave)
4652                 return;
4653
4654         mutex_lock(&dev->struct_mutex);
4655
4656         i915_update_gfx_val(dev_priv);
4657
4658         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4659                 /* Skip inactive CRTCs */
4660                 if (!crtc->fb)
4661                         continue;
4662
4663                 enabled++;
4664                 intel_crtc = to_intel_crtc(crtc);
4665                 if (!intel_crtc->busy)
4666                         intel_decrease_pllclock(crtc);
4667         }
4668
4669         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4670                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4671                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4672         }
4673
4674         mutex_unlock(&dev->struct_mutex);
4675 }
4676
4677 /**
4678  * intel_mark_busy - mark the GPU and possibly the display busy
4679  * @dev: drm device
4680  * @obj: object we're operating on
4681  *
4682  * Callers can use this function to indicate that the GPU is busy processing
4683  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4684  * buffer), we'll also mark the display as busy, so we know to increase its
4685  * clock frequency.
4686  */
4687 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4688 {
4689         drm_i915_private_t *dev_priv = dev->dev_private;
4690         struct drm_crtc *crtc = NULL;
4691         struct intel_framebuffer *intel_fb;
4692         struct intel_crtc *intel_crtc;
4693
4694         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4695                 return;
4696
4697         if (!dev_priv->busy) {
4698                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4699                         u32 fw_blc_self;
4700
4701                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4702                         fw_blc_self = I915_READ(FW_BLC_SELF);
4703                         fw_blc_self &= ~FW_BLC_SELF_EN;
4704                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4705                 }
4706                 dev_priv->busy = true;
4707         } else
4708                 mod_timer(&dev_priv->idle_timer, jiffies +
4709                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4710
4711         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4712                 if (!crtc->fb)
4713                         continue;
4714
4715                 intel_crtc = to_intel_crtc(crtc);
4716                 intel_fb = to_intel_framebuffer(crtc->fb);
4717                 if (intel_fb->obj == obj) {
4718                         if (!intel_crtc->busy) {
4719                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4720                                         u32 fw_blc_self;
4721
4722                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4723                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4724                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4725                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4726                                 }
4727                                 /* Non-busy -> busy, upclock */
4728                                 intel_increase_pllclock(crtc, true);
4729                                 intel_crtc->busy = true;
4730                         } else {
4731                                 /* Busy -> busy, put off timer */
4732                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4733                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4734                         }
4735                 }
4736         }
4737 }
4738
4739 static void intel_crtc_destroy(struct drm_crtc *crtc)
4740 {
4741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4742
4743         drm_crtc_cleanup(crtc);
4744         kfree(intel_crtc);
4745 }
4746
4747 struct intel_unpin_work {
4748         struct work_struct work;
4749         struct drm_device *dev;
4750         struct drm_gem_object *old_fb_obj;
4751         struct drm_gem_object *pending_flip_obj;
4752         struct drm_pending_vblank_event *event;
4753         int pending;
4754 };
4755
4756 static void intel_unpin_work_fn(struct work_struct *__work)
4757 {
4758         struct intel_unpin_work *work =
4759                 container_of(__work, struct intel_unpin_work, work);
4760
4761         mutex_lock(&work->dev->struct_mutex);
4762         i915_gem_object_unpin(work->old_fb_obj);
4763         drm_gem_object_unreference(work->pending_flip_obj);
4764         drm_gem_object_unreference(work->old_fb_obj);
4765         mutex_unlock(&work->dev->struct_mutex);
4766         kfree(work);
4767 }
4768
4769 static void do_intel_finish_page_flip(struct drm_device *dev,
4770                                       struct drm_crtc *crtc)
4771 {
4772         drm_i915_private_t *dev_priv = dev->dev_private;
4773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4774         struct intel_unpin_work *work;
4775         struct drm_i915_gem_object *obj_priv;
4776         struct drm_pending_vblank_event *e;
4777         struct timeval now;
4778         unsigned long flags;
4779
4780         /* Ignore early vblank irqs */
4781         if (intel_crtc == NULL)
4782                 return;
4783
4784         spin_lock_irqsave(&dev->event_lock, flags);
4785         work = intel_crtc->unpin_work;
4786         if (work == NULL || !work->pending) {
4787                 spin_unlock_irqrestore(&dev->event_lock, flags);
4788                 return;
4789         }
4790
4791         intel_crtc->unpin_work = NULL;
4792         drm_vblank_put(dev, intel_crtc->pipe);
4793
4794         if (work->event) {
4795                 e = work->event;
4796                 do_gettimeofday(&now);
4797                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4798                 e->event.tv_sec = now.tv_sec;
4799                 e->event.tv_usec = now.tv_usec;
4800                 list_add_tail(&e->base.link,
4801                               &e->base.file_priv->event_list);
4802                 wake_up_interruptible(&e->base.file_priv->event_wait);
4803         }
4804
4805         spin_unlock_irqrestore(&dev->event_lock, flags);
4806
4807         obj_priv = to_intel_bo(work->pending_flip_obj);
4808
4809         /* Initial scanout buffer will have a 0 pending flip count */
4810         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4811             atomic_dec_and_test(&obj_priv->pending_flip))
4812                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4813         schedule_work(&work->work);
4814
4815         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4816 }
4817
4818 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4819 {
4820         drm_i915_private_t *dev_priv = dev->dev_private;
4821         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4822
4823         do_intel_finish_page_flip(dev, crtc);
4824 }
4825
4826 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4827 {
4828         drm_i915_private_t *dev_priv = dev->dev_private;
4829         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4830
4831         do_intel_finish_page_flip(dev, crtc);
4832 }
4833
4834 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4835 {
4836         drm_i915_private_t *dev_priv = dev->dev_private;
4837         struct intel_crtc *intel_crtc =
4838                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4839         unsigned long flags;
4840
4841         spin_lock_irqsave(&dev->event_lock, flags);
4842         if (intel_crtc->unpin_work) {
4843                 intel_crtc->unpin_work->pending = 1;
4844         } else {
4845                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4846         }
4847         spin_unlock_irqrestore(&dev->event_lock, flags);
4848 }
4849
4850 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4851                                 struct drm_framebuffer *fb,
4852                                 struct drm_pending_vblank_event *event)
4853 {
4854         struct drm_device *dev = crtc->dev;
4855         struct drm_i915_private *dev_priv = dev->dev_private;
4856         struct intel_framebuffer *intel_fb;
4857         struct drm_i915_gem_object *obj_priv;
4858         struct drm_gem_object *obj;
4859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4860         struct intel_unpin_work *work;
4861         unsigned long flags;
4862         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4863         int ret, pipesrc;
4864         u32 flip_mask;
4865
4866         work = kzalloc(sizeof *work, GFP_KERNEL);
4867         if (work == NULL)
4868                 return -ENOMEM;
4869
4870         work->event = event;
4871         work->dev = crtc->dev;
4872         intel_fb = to_intel_framebuffer(crtc->fb);
4873         work->old_fb_obj = intel_fb->obj;
4874         INIT_WORK(&work->work, intel_unpin_work_fn);
4875
4876         /* We borrow the event spin lock for protecting unpin_work */
4877         spin_lock_irqsave(&dev->event_lock, flags);
4878         if (intel_crtc->unpin_work) {
4879                 spin_unlock_irqrestore(&dev->event_lock, flags);
4880                 kfree(work);
4881
4882                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4883                 return -EBUSY;
4884         }
4885         intel_crtc->unpin_work = work;
4886         spin_unlock_irqrestore(&dev->event_lock, flags);
4887
4888         intel_fb = to_intel_framebuffer(fb);
4889         obj = intel_fb->obj;
4890
4891         mutex_lock(&dev->struct_mutex);
4892         ret = intel_pin_and_fence_fb_obj(dev, obj);
4893         if (ret)
4894                 goto cleanup_work;
4895
4896         /* Reference the objects for the scheduled work. */
4897         drm_gem_object_reference(work->old_fb_obj);
4898         drm_gem_object_reference(obj);
4899
4900         crtc->fb = fb;
4901         ret = i915_gem_object_flush_write_domain(obj);
4902         if (ret)
4903                 goto cleanup_objs;
4904
4905         ret = drm_vblank_get(dev, intel_crtc->pipe);
4906         if (ret)
4907                 goto cleanup_objs;
4908
4909         obj_priv = to_intel_bo(obj);
4910         atomic_inc(&obj_priv->pending_flip);
4911         work->pending_flip_obj = obj;
4912
4913         if (intel_crtc->plane)
4914                 flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4915         else
4916                 flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
4917
4918         /* Wait for any previous flip to finish */
4919         if (IS_GEN3(dev))
4920                 while (I915_READ(ISR) & flip_mask)
4921                         ;
4922
4923         BEGIN_LP_RING(4);
4924         if (IS_I965G(dev)) {
4925                 OUT_RING(MI_DISPLAY_FLIP |
4926                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4927                 OUT_RING(fb->pitch);
4928                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4929                 pipesrc = I915_READ(pipesrc_reg);
4930                 OUT_RING(pipesrc & 0x0fff0fff);
4931         } else {
4932                 OUT_RING(MI_DISPLAY_FLIP_I915 |
4933                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4934                 OUT_RING(fb->pitch);
4935                 OUT_RING(obj_priv->gtt_offset);
4936                 OUT_RING(MI_NOOP);
4937         }
4938         ADVANCE_LP_RING();
4939
4940         mutex_unlock(&dev->struct_mutex);
4941
4942         trace_i915_flip_request(intel_crtc->plane, obj);
4943
4944         return 0;
4945
4946 cleanup_objs:
4947         drm_gem_object_unreference(work->old_fb_obj);
4948         drm_gem_object_unreference(obj);
4949 cleanup_work:
4950         mutex_unlock(&dev->struct_mutex);
4951
4952         spin_lock_irqsave(&dev->event_lock, flags);
4953         intel_crtc->unpin_work = NULL;
4954         spin_unlock_irqrestore(&dev->event_lock, flags);
4955
4956         kfree(work);
4957
4958         return ret;
4959 }
4960
4961 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4962         .dpms = intel_crtc_dpms,
4963         .mode_fixup = intel_crtc_mode_fixup,
4964         .mode_set = intel_crtc_mode_set,
4965         .mode_set_base = intel_pipe_set_base,
4966         .prepare = intel_crtc_prepare,
4967         .commit = intel_crtc_commit,
4968         .load_lut = intel_crtc_load_lut,
4969 };
4970
4971 static const struct drm_crtc_funcs intel_crtc_funcs = {
4972         .cursor_set = intel_crtc_cursor_set,
4973         .cursor_move = intel_crtc_cursor_move,
4974         .gamma_set = intel_crtc_gamma_set,
4975         .set_config = drm_crtc_helper_set_config,
4976         .destroy = intel_crtc_destroy,
4977         .page_flip = intel_crtc_page_flip,
4978 };
4979
4980
4981 static void intel_crtc_init(struct drm_device *dev, int pipe)
4982 {
4983         drm_i915_private_t *dev_priv = dev->dev_private;
4984         struct intel_crtc *intel_crtc;
4985         int i;
4986
4987         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4988         if (intel_crtc == NULL)
4989                 return;
4990
4991         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4992
4993         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4994         intel_crtc->pipe = pipe;
4995         intel_crtc->plane = pipe;
4996         for (i = 0; i < 256; i++) {
4997                 intel_crtc->lut_r[i] = i;
4998                 intel_crtc->lut_g[i] = i;
4999                 intel_crtc->lut_b[i] = i;
5000         }
5001
5002         /* Swap pipes & planes for FBC on pre-965 */
5003         intel_crtc->pipe = pipe;
5004         intel_crtc->plane = pipe;
5005         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5006                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5007                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5008         }
5009
5010         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5011                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5012         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5013         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5014
5015         intel_crtc->cursor_addr = 0;
5016         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5017         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5018
5019         intel_crtc->busy = false;
5020
5021         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5022                     (unsigned long)intel_crtc);
5023 }
5024
5025 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5026                                 struct drm_file *file_priv)
5027 {
5028         drm_i915_private_t *dev_priv = dev->dev_private;
5029         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5030         struct drm_mode_object *drmmode_obj;
5031         struct intel_crtc *crtc;
5032
5033         if (!dev_priv) {
5034                 DRM_ERROR("called with no initialization\n");
5035                 return -EINVAL;
5036         }
5037
5038         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5039                         DRM_MODE_OBJECT_CRTC);
5040
5041         if (!drmmode_obj) {
5042                 DRM_ERROR("no such CRTC id\n");
5043                 return -EINVAL;
5044         }
5045
5046         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5047         pipe_from_crtc_id->pipe = crtc->pipe;
5048
5049         return 0;
5050 }
5051
5052 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5053 {
5054         struct drm_crtc *crtc = NULL;
5055
5056         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5057                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5058                 if (intel_crtc->pipe == pipe)
5059                         break;
5060         }
5061         return crtc;
5062 }
5063
5064 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5065 {
5066         int index_mask = 0;
5067         struct drm_encoder *encoder;
5068         int entry = 0;
5069
5070         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5071                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5072                 if (type_mask & intel_encoder->clone_mask)
5073                         index_mask |= (1 << entry);
5074                 entry++;
5075         }
5076         return index_mask;
5077 }
5078
5079
5080 static void intel_setup_outputs(struct drm_device *dev)
5081 {
5082         struct drm_i915_private *dev_priv = dev->dev_private;
5083         struct drm_encoder *encoder;
5084
5085         intel_crt_init(dev);
5086
5087         /* Set up integrated LVDS */
5088         if (IS_MOBILE(dev) && !IS_I830(dev))
5089                 intel_lvds_init(dev);
5090
5091         if (HAS_PCH_SPLIT(dev)) {
5092                 int found;
5093
5094                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5095                         intel_dp_init(dev, DP_A);
5096
5097                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5098                         /* PCH SDVOB multiplex with HDMIB */
5099                         found = intel_sdvo_init(dev, PCH_SDVOB);
5100                         if (!found)
5101                                 intel_hdmi_init(dev, HDMIB);
5102                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5103                                 intel_dp_init(dev, PCH_DP_B);
5104                 }
5105
5106                 if (I915_READ(HDMIC) & PORT_DETECTED)
5107                         intel_hdmi_init(dev, HDMIC);
5108
5109                 if (I915_READ(HDMID) & PORT_DETECTED)
5110                         intel_hdmi_init(dev, HDMID);
5111
5112                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5113                         intel_dp_init(dev, PCH_DP_C);
5114
5115                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
5116                         intel_dp_init(dev, PCH_DP_D);
5117
5118         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5119                 bool found = false;
5120
5121                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5122                         DRM_DEBUG_KMS("probing SDVOB\n");
5123                         found = intel_sdvo_init(dev, SDVOB);
5124                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5125                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5126                                 intel_hdmi_init(dev, SDVOB);
5127                         }
5128
5129                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5130                                 DRM_DEBUG_KMS("probing DP_B\n");
5131                                 intel_dp_init(dev, DP_B);
5132                         }
5133                 }
5134
5135                 /* Before G4X SDVOC doesn't have its own detect register */
5136
5137                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5138                         DRM_DEBUG_KMS("probing SDVOC\n");
5139                         found = intel_sdvo_init(dev, SDVOC);
5140                 }
5141
5142                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5143
5144                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5145                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5146                                 intel_hdmi_init(dev, SDVOC);
5147                         }
5148                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5149                                 DRM_DEBUG_KMS("probing DP_C\n");
5150                                 intel_dp_init(dev, DP_C);
5151                         }
5152                 }
5153
5154                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5155                     (I915_READ(DP_D) & DP_DETECTED)) {
5156                         DRM_DEBUG_KMS("probing DP_D\n");
5157                         intel_dp_init(dev, DP_D);
5158                 }
5159         } else if (IS_GEN2(dev))
5160                 intel_dvo_init(dev);
5161
5162         if (SUPPORTS_TV(dev))
5163                 intel_tv_init(dev);
5164
5165         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5166                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5167
5168                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5169                 encoder->possible_clones = intel_encoder_clones(dev,
5170                                                 intel_encoder->clone_mask);
5171         }
5172 }
5173
5174 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5175 {
5176         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5177
5178         drm_framebuffer_cleanup(fb);
5179         drm_gem_object_unreference_unlocked(intel_fb->obj);
5180
5181         kfree(intel_fb);
5182 }
5183
5184 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5185                                                 struct drm_file *file_priv,
5186                                                 unsigned int *handle)
5187 {
5188         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5189         struct drm_gem_object *object = intel_fb->obj;
5190
5191         return drm_gem_handle_create(file_priv, object, handle);
5192 }
5193
5194 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5195         .destroy = intel_user_framebuffer_destroy,
5196         .create_handle = intel_user_framebuffer_create_handle,
5197 };
5198
5199 int intel_framebuffer_init(struct drm_device *dev,
5200                            struct intel_framebuffer *intel_fb,
5201                            struct drm_mode_fb_cmd *mode_cmd,
5202                            struct drm_gem_object *obj)
5203 {
5204         int ret;
5205
5206         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5207         if (ret) {
5208                 DRM_ERROR("framebuffer init failed %d\n", ret);
5209                 return ret;
5210         }
5211
5212         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5213         intel_fb->obj = obj;
5214         return 0;
5215 }
5216
5217 static struct drm_framebuffer *
5218 intel_user_framebuffer_create(struct drm_device *dev,
5219                               struct drm_file *filp,
5220                               struct drm_mode_fb_cmd *mode_cmd)
5221 {
5222         struct drm_gem_object *obj;
5223         struct intel_framebuffer *intel_fb;
5224         int ret;
5225
5226         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5227         if (!obj)
5228                 return NULL;
5229
5230         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5231         if (!intel_fb)
5232                 return NULL;
5233
5234         ret = intel_framebuffer_init(dev, intel_fb,
5235                                      mode_cmd, obj);
5236         if (ret) {
5237                 drm_gem_object_unreference_unlocked(obj);
5238                 kfree(intel_fb);
5239                 return NULL;
5240         }
5241
5242         return &intel_fb->base;
5243 }
5244
5245 static const struct drm_mode_config_funcs intel_mode_funcs = {
5246         .fb_create = intel_user_framebuffer_create,
5247         .output_poll_changed = intel_fb_output_poll_changed,
5248 };
5249
5250 static struct drm_gem_object *
5251 intel_alloc_power_context(struct drm_device *dev)
5252 {
5253         struct drm_gem_object *pwrctx;
5254         int ret;
5255
5256         pwrctx = i915_gem_alloc_object(dev, 4096);
5257         if (!pwrctx) {
5258                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5259                 return NULL;
5260         }
5261
5262         mutex_lock(&dev->struct_mutex);
5263         ret = i915_gem_object_pin(pwrctx, 4096);
5264         if (ret) {
5265                 DRM_ERROR("failed to pin power context: %d\n", ret);
5266                 goto err_unref;
5267         }
5268
5269         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5270         if (ret) {
5271                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5272                 goto err_unpin;
5273         }
5274         mutex_unlock(&dev->struct_mutex);
5275
5276         return pwrctx;
5277
5278 err_unpin:
5279         i915_gem_object_unpin(pwrctx);
5280 err_unref:
5281         drm_gem_object_unreference(pwrctx);
5282         mutex_unlock(&dev->struct_mutex);
5283         return NULL;
5284 }
5285
5286 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5287 {
5288         struct drm_i915_private *dev_priv = dev->dev_private;
5289         u16 rgvswctl;
5290
5291         rgvswctl = I915_READ16(MEMSWCTL);
5292         if (rgvswctl & MEMCTL_CMD_STS) {
5293                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5294                 return false; /* still busy with another command */
5295         }
5296
5297         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5298                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5299         I915_WRITE16(MEMSWCTL, rgvswctl);
5300         POSTING_READ16(MEMSWCTL);
5301
5302         rgvswctl |= MEMCTL_CMD_STS;
5303         I915_WRITE16(MEMSWCTL, rgvswctl);
5304
5305         return true;
5306 }
5307
5308 void ironlake_enable_drps(struct drm_device *dev)
5309 {
5310         struct drm_i915_private *dev_priv = dev->dev_private;
5311         u32 rgvmodectl = I915_READ(MEMMODECTL);
5312         u8 fmax, fmin, fstart, vstart;
5313         int i = 0;
5314
5315         /* 100ms RC evaluation intervals */
5316         I915_WRITE(RCUPEI, 100000);
5317         I915_WRITE(RCDNEI, 100000);
5318
5319         /* Set max/min thresholds to 90ms and 80ms respectively */
5320         I915_WRITE(RCBMAXAVG, 90000);
5321         I915_WRITE(RCBMINAVG, 80000);
5322
5323         I915_WRITE(MEMIHYST, 1);
5324
5325         /* Set up min, max, and cur for interrupt handling */
5326         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5327         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5328         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5329                 MEMMODE_FSTART_SHIFT;
5330         fstart = fmax;
5331
5332         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5333                 PXVFREQ_PX_SHIFT;
5334
5335         dev_priv->fmax = fstart; /* IPS callback will increase this */
5336         dev_priv->fstart = fstart;
5337
5338         dev_priv->max_delay = fmax;
5339         dev_priv->min_delay = fmin;
5340         dev_priv->cur_delay = fstart;
5341
5342         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5343                          fstart);
5344
5345         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5346
5347         /*
5348          * Interrupts will be enabled in ironlake_irq_postinstall
5349          */
5350
5351         I915_WRITE(VIDSTART, vstart);
5352         POSTING_READ(VIDSTART);
5353
5354         rgvmodectl |= MEMMODE_SWMODE_EN;
5355         I915_WRITE(MEMMODECTL, rgvmodectl);
5356
5357         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5358                 if (i++ > 100) {
5359                         DRM_ERROR("stuck trying to change perf mode\n");
5360                         break;
5361                 }
5362                 msleep(1);
5363         }
5364         msleep(1);
5365
5366         ironlake_set_drps(dev, fstart);
5367
5368         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5369                 I915_READ(0x112e0);
5370         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5371         dev_priv->last_count2 = I915_READ(0x112f4);
5372         getrawmonotonic(&dev_priv->last_time2);
5373 }
5374
5375 void ironlake_disable_drps(struct drm_device *dev)
5376 {
5377         struct drm_i915_private *dev_priv = dev->dev_private;
5378         u16 rgvswctl = I915_READ16(MEMSWCTL);
5379
5380         /* Ack interrupts, disable EFC interrupt */
5381         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5382         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5383         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5384         I915_WRITE(DEIIR, DE_PCU_EVENT);
5385         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5386
5387         /* Go back to the starting frequency */
5388         ironlake_set_drps(dev, dev_priv->fstart);
5389         msleep(1);
5390         rgvswctl |= MEMCTL_CMD_STS;
5391         I915_WRITE(MEMSWCTL, rgvswctl);
5392         msleep(1);
5393
5394 }
5395
5396 static unsigned long intel_pxfreq(u32 vidfreq)
5397 {
5398         unsigned long freq;
5399         int div = (vidfreq & 0x3f0000) >> 16;
5400         int post = (vidfreq & 0x3000) >> 12;
5401         int pre = (vidfreq & 0x7);
5402
5403         if (!pre)
5404                 return 0;
5405
5406         freq = ((div * 133333) / ((1<<post) * pre));
5407
5408         return freq;
5409 }
5410
5411 void intel_init_emon(struct drm_device *dev)
5412 {
5413         struct drm_i915_private *dev_priv = dev->dev_private;
5414         u32 lcfuse;
5415         u8 pxw[16];
5416         int i;
5417
5418         /* Disable to program */
5419         I915_WRITE(ECR, 0);
5420         POSTING_READ(ECR);
5421
5422         /* Program energy weights for various events */
5423         I915_WRITE(SDEW, 0x15040d00);
5424         I915_WRITE(CSIEW0, 0x007f0000);
5425         I915_WRITE(CSIEW1, 0x1e220004);
5426         I915_WRITE(CSIEW2, 0x04000004);
5427
5428         for (i = 0; i < 5; i++)
5429                 I915_WRITE(PEW + (i * 4), 0);
5430         for (i = 0; i < 3; i++)
5431                 I915_WRITE(DEW + (i * 4), 0);
5432
5433         /* Program P-state weights to account for frequency power adjustment */
5434         for (i = 0; i < 16; i++) {
5435                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5436                 unsigned long freq = intel_pxfreq(pxvidfreq);
5437                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5438                         PXVFREQ_PX_SHIFT;
5439                 unsigned long val;
5440
5441                 val = vid * vid;
5442                 val *= (freq / 1000);
5443                 val *= 255;
5444                 val /= (127*127*900);
5445                 if (val > 0xff)
5446                         DRM_ERROR("bad pxval: %ld\n", val);
5447                 pxw[i] = val;
5448         }
5449         /* Render standby states get 0 weight */
5450         pxw[14] = 0;
5451         pxw[15] = 0;
5452
5453         for (i = 0; i < 4; i++) {
5454                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5455                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5456                 I915_WRITE(PXW + (i * 4), val);
5457         }
5458
5459         /* Adjust magic regs to magic values (more experimental results) */
5460         I915_WRITE(OGW0, 0);
5461         I915_WRITE(OGW1, 0);
5462         I915_WRITE(EG0, 0x00007f00);
5463         I915_WRITE(EG1, 0x0000000e);
5464         I915_WRITE(EG2, 0x000e0000);
5465         I915_WRITE(EG3, 0x68000300);
5466         I915_WRITE(EG4, 0x42000000);
5467         I915_WRITE(EG5, 0x00140031);
5468         I915_WRITE(EG6, 0);
5469         I915_WRITE(EG7, 0);
5470
5471         for (i = 0; i < 8; i++)
5472                 I915_WRITE(PXWL + (i * 4), 0);
5473
5474         /* Enable PMON + select events */
5475         I915_WRITE(ECR, 0x80000019);
5476
5477         lcfuse = I915_READ(LCFUSE02);
5478
5479         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5480 }
5481
5482 void intel_init_clock_gating(struct drm_device *dev)
5483 {
5484         struct drm_i915_private *dev_priv = dev->dev_private;
5485
5486         /*
5487          * Disable clock gating reported to work incorrectly according to the
5488          * specs, but enable as much else as we can.
5489          */
5490         if (HAS_PCH_SPLIT(dev)) {
5491                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5492
5493                 if (IS_IRONLAKE(dev)) {
5494                         /* Required for FBC */
5495                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5496                         /* Required for CxSR */
5497                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5498
5499                         I915_WRITE(PCH_3DCGDIS0,
5500                                    MARIUNIT_CLOCK_GATE_DISABLE |
5501                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5502                 }
5503
5504                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5505
5506                 /*
5507                  * According to the spec the following bits should be set in
5508                  * order to enable memory self-refresh
5509                  * The bit 22/21 of 0x42004
5510                  * The bit 5 of 0x42020
5511                  * The bit 15 of 0x45000
5512                  */
5513                 if (IS_IRONLAKE(dev)) {
5514                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5515                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5516                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5517                         I915_WRITE(ILK_DSPCLK_GATE,
5518                                         (I915_READ(ILK_DSPCLK_GATE) |
5519                                                 ILK_DPARB_CLK_GATE));
5520                         I915_WRITE(DISP_ARB_CTL,
5521                                         (I915_READ(DISP_ARB_CTL) |
5522                                                 DISP_FBC_WM_DIS));
5523                 }
5524                 /*
5525                  * Based on the document from hardware guys the following bits
5526                  * should be set unconditionally in order to enable FBC.
5527                  * The bit 22 of 0x42000
5528                  * The bit 22 of 0x42004
5529                  * The bit 7,8,9 of 0x42020.
5530                  */
5531                 if (IS_IRONLAKE_M(dev)) {
5532                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5533                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5534                                    ILK_FBCQ_DIS);
5535                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5536                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5537                                    ILK_DPARB_GATE);
5538                         I915_WRITE(ILK_DSPCLK_GATE,
5539                                    I915_READ(ILK_DSPCLK_GATE) |
5540                                    ILK_DPFC_DIS1 |
5541                                    ILK_DPFC_DIS2 |
5542                                    ILK_CLK_FBC);
5543                 }
5544                 return;
5545         } else if (IS_G4X(dev)) {
5546                 uint32_t dspclk_gate;
5547                 I915_WRITE(RENCLK_GATE_D1, 0);
5548                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5549                        GS_UNIT_CLOCK_GATE_DISABLE |
5550                        CL_UNIT_CLOCK_GATE_DISABLE);
5551                 I915_WRITE(RAMCLK_GATE_D, 0);
5552                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5553                         OVRUNIT_CLOCK_GATE_DISABLE |
5554                         OVCUNIT_CLOCK_GATE_DISABLE;
5555                 if (IS_GM45(dev))
5556                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5557                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5558         } else if (IS_I965GM(dev)) {
5559                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5560                 I915_WRITE(RENCLK_GATE_D2, 0);
5561                 I915_WRITE(DSPCLK_GATE_D, 0);
5562                 I915_WRITE(RAMCLK_GATE_D, 0);
5563                 I915_WRITE16(DEUC, 0);
5564         } else if (IS_I965G(dev)) {
5565                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5566                        I965_RCC_CLOCK_GATE_DISABLE |
5567                        I965_RCPB_CLOCK_GATE_DISABLE |
5568                        I965_ISC_CLOCK_GATE_DISABLE |
5569                        I965_FBC_CLOCK_GATE_DISABLE);
5570                 I915_WRITE(RENCLK_GATE_D2, 0);
5571         } else if (IS_I9XX(dev)) {
5572                 u32 dstate = I915_READ(D_STATE);
5573
5574                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5575                         DSTATE_DOT_CLOCK_GATING;
5576                 I915_WRITE(D_STATE, dstate);
5577         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5578                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5579         } else if (IS_I830(dev)) {
5580                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5581         }
5582
5583         /*
5584          * GPU can automatically power down the render unit if given a page
5585          * to save state.
5586          */
5587         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5588                 struct drm_i915_gem_object *obj_priv = NULL;
5589
5590                 if (dev_priv->pwrctx) {
5591                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5592                 } else {
5593                         struct drm_gem_object *pwrctx;
5594
5595                         pwrctx = intel_alloc_power_context(dev);
5596                         if (pwrctx) {
5597                                 dev_priv->pwrctx = pwrctx;
5598                                 obj_priv = to_intel_bo(pwrctx);
5599                         }
5600                 }
5601
5602                 if (obj_priv) {
5603                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5604                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5605                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5606                 }
5607         }
5608 }
5609
5610 /* Set up chip specific display functions */
5611 static void intel_init_display(struct drm_device *dev)
5612 {
5613         struct drm_i915_private *dev_priv = dev->dev_private;
5614
5615         /* We always want a DPMS function */
5616         if (HAS_PCH_SPLIT(dev))
5617                 dev_priv->display.dpms = ironlake_crtc_dpms;
5618         else
5619                 dev_priv->display.dpms = i9xx_crtc_dpms;
5620
5621         if (I915_HAS_FBC(dev)) {
5622                 if (IS_IRONLAKE_M(dev)) {
5623                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5624                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5625                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5626                 } else if (IS_GM45(dev)) {
5627                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5628                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5629                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5630                 } else if (IS_I965GM(dev)) {
5631                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5632                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5633                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5634                 }
5635                 /* 855GM needs testing */
5636         }
5637
5638         /* Returns the core display clock speed */
5639         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5640                 dev_priv->display.get_display_clock_speed =
5641                         i945_get_display_clock_speed;
5642         else if (IS_I915G(dev))
5643                 dev_priv->display.get_display_clock_speed =
5644                         i915_get_display_clock_speed;
5645         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5646                 dev_priv->display.get_display_clock_speed =
5647                         i9xx_misc_get_display_clock_speed;
5648         else if (IS_I915GM(dev))
5649                 dev_priv->display.get_display_clock_speed =
5650                         i915gm_get_display_clock_speed;
5651         else if (IS_I865G(dev))
5652                 dev_priv->display.get_display_clock_speed =
5653                         i865_get_display_clock_speed;
5654         else if (IS_I85X(dev))
5655                 dev_priv->display.get_display_clock_speed =
5656                         i855_get_display_clock_speed;
5657         else /* 852, 830 */
5658                 dev_priv->display.get_display_clock_speed =
5659                         i830_get_display_clock_speed;
5660
5661         /* For FIFO watermark updates */
5662         if (HAS_PCH_SPLIT(dev)) {
5663                 if (IS_IRONLAKE(dev)) {
5664                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5665                                 dev_priv->display.update_wm = ironlake_update_wm;
5666                         else {
5667                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5668                                               "Disable CxSR\n");
5669                                 dev_priv->display.update_wm = NULL;
5670                         }
5671                 } else
5672                         dev_priv->display.update_wm = NULL;
5673         } else if (IS_PINEVIEW(dev)) {
5674                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5675                                             dev_priv->is_ddr3,
5676                                             dev_priv->fsb_freq,
5677                                             dev_priv->mem_freq)) {
5678                         DRM_INFO("failed to find known CxSR latency "
5679                                  "(found ddr%s fsb freq %d, mem freq %d), "
5680                                  "disabling CxSR\n",
5681                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5682                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5683                         /* Disable CxSR and never update its watermark again */
5684                         pineview_disable_cxsr(dev);
5685                         dev_priv->display.update_wm = NULL;
5686                 } else
5687                         dev_priv->display.update_wm = pineview_update_wm;
5688         } else if (IS_G4X(dev))
5689                 dev_priv->display.update_wm = g4x_update_wm;
5690         else if (IS_I965G(dev))
5691                 dev_priv->display.update_wm = i965_update_wm;
5692         else if (IS_I9XX(dev)) {
5693                 dev_priv->display.update_wm = i9xx_update_wm;
5694                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5695         } else if (IS_I85X(dev)) {
5696                 dev_priv->display.update_wm = i9xx_update_wm;
5697                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5698         } else {
5699                 dev_priv->display.update_wm = i830_update_wm;
5700                 if (IS_845G(dev))
5701                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5702                 else
5703                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5704         }
5705 }
5706
5707 void intel_modeset_init(struct drm_device *dev)
5708 {
5709         struct drm_i915_private *dev_priv = dev->dev_private;
5710         int i;
5711
5712         drm_mode_config_init(dev);
5713
5714         dev->mode_config.min_width = 0;
5715         dev->mode_config.min_height = 0;
5716
5717         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5718
5719         intel_init_display(dev);
5720
5721         if (IS_I965G(dev)) {
5722                 dev->mode_config.max_width = 8192;
5723                 dev->mode_config.max_height = 8192;
5724         } else if (IS_I9XX(dev)) {
5725                 dev->mode_config.max_width = 4096;
5726                 dev->mode_config.max_height = 4096;
5727         } else {
5728                 dev->mode_config.max_width = 2048;
5729                 dev->mode_config.max_height = 2048;
5730         }
5731
5732         /* set memory base */
5733         if (IS_I9XX(dev))
5734                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5735         else
5736                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5737
5738         if (IS_MOBILE(dev) || IS_I9XX(dev))
5739                 dev_priv->num_pipe = 2;
5740         else
5741                 dev_priv->num_pipe = 1;
5742         DRM_DEBUG_KMS("%d display pipe%s available.\n",
5743                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
5744
5745         for (i = 0; i < dev_priv->num_pipe; i++) {
5746                 intel_crtc_init(dev, i);
5747         }
5748
5749         intel_setup_outputs(dev);
5750
5751         intel_init_clock_gating(dev);
5752
5753         if (IS_IRONLAKE_M(dev)) {
5754                 ironlake_enable_drps(dev);
5755                 intel_init_emon(dev);
5756         }
5757
5758         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5759         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5760                     (unsigned long)dev);
5761
5762         intel_setup_overlay(dev);
5763 }
5764
5765 void intel_modeset_cleanup(struct drm_device *dev)
5766 {
5767         struct drm_i915_private *dev_priv = dev->dev_private;
5768         struct drm_crtc *crtc;
5769         struct intel_crtc *intel_crtc;
5770
5771         mutex_lock(&dev->struct_mutex);
5772
5773         drm_kms_helper_poll_fini(dev);
5774         intel_fbdev_fini(dev);
5775
5776         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5777                 /* Skip inactive CRTCs */
5778                 if (!crtc->fb)
5779                         continue;
5780
5781                 intel_crtc = to_intel_crtc(crtc);
5782                 intel_increase_pllclock(crtc, false);
5783                 del_timer_sync(&intel_crtc->idle_timer);
5784         }
5785
5786         del_timer_sync(&dev_priv->idle_timer);
5787
5788         if (dev_priv->display.disable_fbc)
5789                 dev_priv->display.disable_fbc(dev);
5790
5791         if (dev_priv->pwrctx) {
5792                 struct drm_i915_gem_object *obj_priv;
5793
5794                 obj_priv = to_intel_bo(dev_priv->pwrctx);
5795                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5796                 I915_READ(PWRCTXA);
5797                 i915_gem_object_unpin(dev_priv->pwrctx);
5798                 drm_gem_object_unreference(dev_priv->pwrctx);
5799         }
5800
5801         if (IS_IRONLAKE_M(dev))
5802                 ironlake_disable_drps(dev);
5803
5804         mutex_unlock(&dev->struct_mutex);
5805
5806         drm_mode_config_cleanup(dev);
5807 }
5808
5809
5810 /*
5811  * Return which encoder is currently attached for connector.
5812  */
5813 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5814 {
5815         struct drm_mode_object *obj;
5816         struct drm_encoder *encoder;
5817         int i;
5818
5819         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5820                 if (connector->encoder_ids[i] == 0)
5821                         break;
5822
5823                 obj = drm_mode_object_find(connector->dev,
5824                                            connector->encoder_ids[i],
5825                                            DRM_MODE_OBJECT_ENCODER);
5826                 if (!obj)
5827                         continue;
5828
5829                 encoder = obj_to_encoder(obj);
5830                 return encoder;
5831         }
5832         return NULL;
5833 }
5834
5835 /*
5836  * set vga decode state - true == enable VGA decode
5837  */
5838 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5839 {
5840         struct drm_i915_private *dev_priv = dev->dev_private;
5841         u16 gmch_ctrl;
5842
5843         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5844         if (state)
5845                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5846         else
5847                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5848         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5849         return 0;
5850 }