drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "intel_dsi.h"
  41 #include "i915_trace.h"
  42 #include <drm/drm_atomic.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_dp_helper.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_plane_helper.h>
  47 #include <drm/drm_rect.h>
  48 #include <linux/dma_remapping.h>
  49 #include <linux/reservation.h>
  50
  51 static bool is_mmio_work(struct intel_flip_work *work)
  52 {
  53         return work->mmio_work.func;
  54 }
  55
  56 /* Primary plane formats for gen <= 3 */
  57 static const uint32_t i8xx_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB1555,
  61         DRM_FORMAT_XRGB8888,
  62 };
  63
  64 /* Primary plane formats for gen >= 4 */
  65 static const uint32_t i965_primary_formats[] = {
  66         DRM_FORMAT_C8,
  67         DRM_FORMAT_RGB565,
  68         DRM_FORMAT_XRGB8888,
  69         DRM_FORMAT_XBGR8888,
  70         DRM_FORMAT_XRGB2101010,
  71         DRM_FORMAT_XBGR2101010,
  72 };
  73
  74 static const uint32_t skl_primary_formats[] = {
  75         DRM_FORMAT_C8,
  76         DRM_FORMAT_RGB565,
  77         DRM_FORMAT_XRGB8888,
  78         DRM_FORMAT_XBGR8888,
  79         DRM_FORMAT_ARGB8888,
  80         DRM_FORMAT_ABGR8888,
  81         DRM_FORMAT_XRGB2101010,
  82         DRM_FORMAT_XBGR2101010,
  83         DRM_FORMAT_YUYV,
  84         DRM_FORMAT_YVYU,
  85         DRM_FORMAT_UYVY,
  86         DRM_FORMAT_VYUY,
  87 };
  88
  89 /* Cursor formats */
  90 static const uint32_t intel_cursor_formats[] = {
  91         DRM_FORMAT_ARGB8888,
  92 };
  93
  94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  95                                 struct intel_crtc_state *pipe_config);
  96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  97                                    struct intel_crtc_state *pipe_config);
  98
  99 static int intel_framebuffer_init(struct drm_device *dev,
 100                                   struct intel_framebuffer *ifb,
 101                                   struct drm_mode_fb_cmd2 *mode_cmd,
 102                                   struct drm_i915_gem_object *obj);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void skl_init_scalers(struct drm_i915_private *dev_priv,
 119                              struct intel_crtc *crtc,
 120                              struct intel_crtc_state *crtc_state);
 121 static void skylake_pfit_enable(struct intel_crtc *crtc);
 122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 127 static int bxt_calc_cdclk(int max_pixclk);
 128
 129 struct intel_limit {
 130         struct {
 131                 int min, max;
 132         } dot, vco, n, m, m1, m2, p, p1;
 133
 134         struct {
 135                 int dot_limit;
 136                 int p2_slow, p2_fast;
 137         } p2;
 138 };
 139
 140 /* returns HPLL frequency in kHz */
 141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 142 {
 143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 144
 145         /* Obtain SKU information */
 146         mutex_lock(&dev_priv->sb_lock);
 147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 148                 CCK_FUSE_HPLL_FREQ_MASK;
 149         mutex_unlock(&dev_priv->sb_lock);
 150
 151         return vco_freq[hpll_freq] * 1000;
 152 }
 153
 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 155                       const char *name, u32 reg, int ref_freq)
 156 {
 157         u32 val;
 158         int divider;
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 171 }
 172
 173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 174                                   const char *name, u32 reg)
 175 {
 176         if (dev_priv->hpll_freq == 0)
 177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 178
 179         return vlv_get_cck_clock(dev_priv, name, reg,
 180                                  dev_priv->hpll_freq);
 181 }
 182
 183 static int
 184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 185 {
 186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 187 }
 188
 189 static int
 190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 191 {
 192         /* RAWCLK_FREQ_VLV register updated from power well code */
 193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 195 }
 196
 197 static int
 198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 199 {
 200         uint32_t clkcfg;
 201
 202         /* hrawclock is 1/4 the FSB frequency */
 203         clkcfg = I915_READ(CLKCFG);
 204         switch (clkcfg & CLKCFG_FSB_MASK) {
 205         case CLKCFG_FSB_400:
 206                 return 100000;
 207         case CLKCFG_FSB_533:
 208                 return 133333;
 209         case CLKCFG_FSB_667:
 210                 return 166667;
 211         case CLKCFG_FSB_800:
 212                 return 200000;
 213         case CLKCFG_FSB_1067:
 214                 return 266667;
 215         case CLKCFG_FSB_1333:
 216                 return 333333;
 217         /* these two are just a guess; one of them might be right */
 218         case CLKCFG_FSB_1600:
 219         case CLKCFG_FSB_1600_ALT:
 220                 return 400000;
 221         default:
 222                 return 133333;
 223         }
 224 }
 225
 226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 227 {
 228         if (HAS_PCH_SPLIT(dev_priv))
 229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 234         else
 235                 return; /* no rawclk on other platforms, or no need to know it */
 236
 237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 238 }
 239
 240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 241 {
 242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 243                 return;
 244
 245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 246                                                       CCK_CZ_CLOCK_CONTROL);
 247
 248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 249 }
 250
 251 static inline u32 /* units of 100MHz */
 252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 253                     const struct intel_crtc_state *pipe_config)
 254 {
 255         if (HAS_DDI(dev_priv))
 256                 return pipe_config->port_clock; /* SPLL */
 257         else if (IS_GEN5(dev_priv))
 258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 259         else
 260                 return 270000;
 261 }
 262
 263 static const struct intel_limit intel_limits_i8xx_dac = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 2, .max = 33 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 4, .p2_fast = 2 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i8xx_dvo = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 908000, .max = 1512000 },
 279         .n = { .min = 2, .max = 16 },
 280         .m = { .min = 96, .max = 140 },
 281         .m1 = { .min = 18, .max = 26 },
 282         .m2 = { .min = 6, .max = 16 },
 283         .p = { .min = 4, .max = 128 },
 284         .p1 = { .min = 2, .max = 33 },
 285         .p2 = { .dot_limit = 165000,
 286                 .p2_slow = 4, .p2_fast = 4 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i8xx_lvds = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 908000, .max = 1512000 },
 292         .n = { .min = 2, .max = 16 },
 293         .m = { .min = 96, .max = 140 },
 294         .m1 = { .min = 18, .max = 26 },
 295         .m2 = { .min = 6, .max = 16 },
 296         .p = { .min = 4, .max = 128 },
 297         .p1 = { .min = 1, .max = 6 },
 298         .p2 = { .dot_limit = 165000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302 static const struct intel_limit intel_limits_i9xx_sdvo = {
 303         .dot = { .min = 20000, .max = 400000 },
 304         .vco = { .min = 1400000, .max = 2800000 },
 305         .n = { .min = 1, .max = 6 },
 306         .m = { .min = 70, .max = 120 },
 307         .m1 = { .min = 8, .max = 18 },
 308         .m2 = { .min = 3, .max = 7 },
 309         .p = { .min = 5, .max = 80 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 200000,
 312                 .p2_slow = 10, .p2_fast = 5 },
 313 };
 314
 315 static const struct intel_limit intel_limits_i9xx_lvds = {
 316         .dot = { .min = 20000, .max = 400000 },
 317         .vco = { .min = 1400000, .max = 2800000 },
 318         .n = { .min = 1, .max = 6 },
 319         .m = { .min = 70, .max = 120 },
 320         .m1 = { .min = 8, .max = 18 },
 321         .m2 = { .min = 3, .max = 7 },
 322         .p = { .min = 7, .max = 98 },
 323         .p1 = { .min = 1, .max = 8 },
 324         .p2 = { .dot_limit = 112000,
 325                 .p2_slow = 14, .p2_fast = 7 },
 326 };
 327
 328
 329 static const struct intel_limit intel_limits_g4x_sdvo = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 1750000, .max = 3500000},
 332         .n = { .min = 1, .max = 4 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 1, .max = 3},
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 10,
 340                 .p2_fast = 10
 341         },
 342 };
 343
 344 static const struct intel_limit intel_limits_g4x_hdmi = {
 345         .dot = { .min = 22000, .max = 400000 },
 346         .vco = { .min = 1750000, .max = 3500000},
 347         .n = { .min = 1, .max = 4 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 16, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 5, .max = 80 },
 352         .p1 = { .min = 1, .max = 8},
 353         .p2 = { .dot_limit = 165000,
 354                 .p2_slow = 10, .p2_fast = 5 },
 355 };
 356
 357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 358         .dot = { .min = 20000, .max = 115000 },
 359         .vco = { .min = 1750000, .max = 3500000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 104, .max = 138 },
 362         .m1 = { .min = 17, .max = 23 },
 363         .m2 = { .min = 5, .max = 11 },
 364         .p = { .min = 28, .max = 112 },
 365         .p1 = { .min = 2, .max = 8 },
 366         .p2 = { .dot_limit = 0,
 367                 .p2_slow = 14, .p2_fast = 14
 368         },
 369 };
 370
 371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 372         .dot = { .min = 80000, .max = 224000 },
 373         .vco = { .min = 1750000, .max = 3500000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 104, .max = 138 },
 376         .m1 = { .min = 17, .max = 23 },
 377         .m2 = { .min = 5, .max = 11 },
 378         .p = { .min = 14, .max = 42 },
 379         .p1 = { .min = 2, .max = 6 },
 380         .p2 = { .dot_limit = 0,
 381                 .p2_slow = 7, .p2_fast = 7
 382         },
 383 };
 384
 385 static const struct intel_limit intel_limits_pineview_sdvo = {
 386         .dot = { .min = 20000, .max = 400000},
 387         .vco = { .min = 1700000, .max = 3500000 },
 388         /* Pineview's Ncounter is a ring counter */
 389         .n = { .min = 3, .max = 6 },
 390         .m = { .min = 2, .max = 256 },
 391         /* Pineview only has one combined m divider, which we treat as m2. */
 392         .m1 = { .min = 0, .max = 0 },
 393         .m2 = { .min = 0, .max = 254 },
 394         .p = { .min = 5, .max = 80 },
 395         .p1 = { .min = 1, .max = 8 },
 396         .p2 = { .dot_limit = 200000,
 397                 .p2_slow = 10, .p2_fast = 5 },
 398 };
 399
 400 static const struct intel_limit intel_limits_pineview_lvds = {
 401         .dot = { .min = 20000, .max = 400000 },
 402         .vco = { .min = 1700000, .max = 3500000 },
 403         .n = { .min = 3, .max = 6 },
 404         .m = { .min = 2, .max = 256 },
 405         .m1 = { .min = 0, .max = 0 },
 406         .m2 = { .min = 0, .max = 254 },
 407         .p = { .min = 7, .max = 112 },
 408         .p1 = { .min = 1, .max = 8 },
 409         .p2 = { .dot_limit = 112000,
 410                 .p2_slow = 14, .p2_fast = 14 },
 411 };
 412
 413 /* Ironlake / Sandybridge
 414  *
 415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 416  * the range value for them is (actual_value - 2).
 417  */
 418 static const struct intel_limit intel_limits_ironlake_dac = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 5 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 5, .max = 80 },
 426         .p1 = { .min = 1, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 10, .p2_fast = 5 },
 429 };
 430
 431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 3 },
 435         .m = { .min = 79, .max = 118 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 127 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 56 },
 452         .p1 = { .min = 2, .max = 8 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 /* LVDS 100mhz refclk limits. */
 458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 459         .dot = { .min = 25000, .max = 350000 },
 460         .vco = { .min = 1760000, .max = 3510000 },
 461         .n = { .min = 1, .max = 2 },
 462         .m = { .min = 79, .max = 126 },
 463         .m1 = { .min = 12, .max = 22 },
 464         .m2 = { .min = 5, .max = 9 },
 465         .p = { .min = 28, .max = 112 },
 466         .p1 = { .min = 2, .max = 8 },
 467         .p2 = { .dot_limit = 225000,
 468                 .p2_slow = 14, .p2_fast = 14 },
 469 };
 470
 471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 472         .dot = { .min = 25000, .max = 350000 },
 473         .vco = { .min = 1760000, .max = 3510000 },
 474         .n = { .min = 1, .max = 3 },
 475         .m = { .min = 79, .max = 126 },
 476         .m1 = { .min = 12, .max = 22 },
 477         .m2 = { .min = 5, .max = 9 },
 478         .p = { .min = 14, .max = 42 },
 479         .p1 = { .min = 2, .max = 6 },
 480         .p2 = { .dot_limit = 225000,
 481                 .p2_slow = 7, .p2_fast = 7 },
 482 };
 483
 484 static const struct intel_limit intel_limits_vlv = {
 485          /*
 486           * These are the data rate limits (measured in fast clocks)
 487           * since those are the strictest limits we have. The fast
 488           * clock and actual rate limits are more relaxed, so checking
 489           * them would make no difference.
 490           */
 491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 492         .vco = { .min = 4000000, .max = 6000000 },
 493         .n = { .min = 1, .max = 7 },
 494         .m1 = { .min = 2, .max = 3 },
 495         .m2 = { .min = 11, .max = 156 },
 496         .p1 = { .min = 2, .max = 3 },
 497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 498 };
 499
 500 static const struct intel_limit intel_limits_chv = {
 501         /*
 502          * These are the data rate limits (measured in fast clocks)
 503          * since those are the strictest limits we have.  The fast
 504          * clock and actual rate limits are more relaxed, so checking
 505          * them would make no difference.
 506          */
 507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 508         .vco = { .min = 4800000, .max = 6480000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 514 };
 515
 516 static const struct intel_limit intel_limits_bxt = {
 517         /* FIXME: find real dot limits */
 518         .dot = { .min = 0, .max = INT_MAX },
 519         .vco = { .min = 4800000, .max = 6700000 },
 520         .n = { .min = 1, .max = 1 },
 521         .m1 = { .min = 2, .max = 2 },
 522         /* FIXME: find real m2 limits */
 523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 524         .p1 = { .min = 2, .max = 4 },
 525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 526 };
 527
 528 static bool
 529 needs_modeset(struct drm_crtc_state *state)
 530 {
 531         return drm_atomic_crtc_needs_modeset(state);
 532 }
 533
 534 /*
 535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 538  * The helpers' return value is the rate of the clock that is fed to the
 539  * display engine's pipe which can be the above fast dot clock rate or a
 540  * divided-down version of it.
 541  */
 542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 544 {
 545         clock->m = clock->m2 + 2;
 546         clock->p = clock->p1 * clock->p2;
 547         if (WARN_ON(clock->n == 0 || clock->p == 0))
 548                 return 0;
 549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 551
 552         return clock->dot;
 553 }
 554
 555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 556 {
 557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 558 }
 559
 560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 561 {
 562         clock->m = i9xx_dpll_compute_m(clock);
 563         clock->p = clock->p1 * clock->p2;
 564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 565                 return 0;
 566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 568
 569         return clock->dot;
 570 }
 571
 572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 573 {
 574         clock->m = clock->m1 * clock->m2;
 575         clock->p = clock->p1 * clock->p2;
 576         if (WARN_ON(clock->n == 0 || clock->p == 0))
 577                 return 0;
 578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 580
 581         return clock->dot / 5;
 582 }
 583
 584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 585 {
 586         clock->m = clock->m1 * clock->m2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 591                         clock->n << 22);
 592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 593
 594         return clock->dot / 5;
 595 }
 596
 597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 598 /**
 599  * Returns whether the given set of divisors are valid for a given refclk with
 600  * the given connectors.
 601  */
 602
 603 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 604                                const struct intel_limit *limit,
 605                                const struct dpll *clock)
 606 {
 607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 608                 INTELPllInvalid("n out of range\n");
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 612                 INTELPllInvalid("m2 out of range\n");
 613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 614                 INTELPllInvalid("m1 out of range\n");
 615
 616         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 617             !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
 618                 if (clock->m1 <= clock->m2)
 619                         INTELPllInvalid("m1 <= m2\n");
 620
 621         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 622             !IS_BROXTON(dev_priv)) {
 623                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 624                         INTELPllInvalid("p out of range\n");
 625                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 626                         INTELPllInvalid("m out of range\n");
 627         }
 628
 629         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 630                 INTELPllInvalid("vco out of range\n");
 631         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 632          * connector, etc., rather than just a single range.
 633          */
 634         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 635                 INTELPllInvalid("dot out of range\n");
 636
 637         return true;
 638 }
 639
 640 static int
 641 i9xx_select_p2_div(const struct intel_limit *limit,
 642                    const struct intel_crtc_state *crtc_state,
 643                    int target)
 644 {
 645         struct drm_device *dev = crtc_state->base.crtc->dev;
 646
 647         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 648                 /*
 649                  * For LVDS just rely on its current settings for dual-channel.
 650                  * We haven't figured out how to reliably set up different
 651                  * single/dual channel state, if we even can.
 652                  */
 653                 if (intel_is_dual_link_lvds(dev))
 654                         return limit->p2.p2_fast;
 655                 else
 656                         return limit->p2.p2_slow;
 657         } else {
 658                 if (target < limit->p2.dot_limit)
 659                         return limit->p2.p2_slow;
 660                 else
 661                         return limit->p2.p2_fast;
 662         }
 663 }
 664
 665 /*
 666  * Returns a set of divisors for the desired target clock with the given
 667  * refclk, or FALSE.  The returned values represent the clock equation:
 668  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 669  *
 670  * Target and reference clocks are specified in kHz.
 671  *
 672  * If match_clock is provided, then best_clock P divider must match the P
 673  * divider from @match_clock used for LVDS downclocking.
 674  */
 675 static bool
 676 i9xx_find_best_dpll(const struct intel_limit *limit,
 677                     struct intel_crtc_state *crtc_state,
 678                     int target, int refclk, struct dpll *match_clock,
 679                     struct dpll *best_clock)
 680 {
 681         struct drm_device *dev = crtc_state->base.crtc->dev;
 682         struct dpll clock;
 683         int err = target;
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 688
 689         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 690              clock.m1++) {
 691                 for (clock.m2 = limit->m2.min;
 692                      clock.m2 <= limit->m2.max; clock.m2++) {
 693                         if (clock.m2 >= clock.m1)
 694                                 break;
 695                         for (clock.n = limit->n.min;
 696                              clock.n <= limit->n.max; clock.n++) {
 697                                 for (clock.p1 = limit->p1.min;
 698                                         clock.p1 <= limit->p1.max; clock.p1++) {
 699                                         int this_err;
 700
 701                                         i9xx_calc_dpll_params(refclk, &clock);
 702                                         if (!intel_PLL_is_valid(to_i915(dev),
 703                                                                 limit,
 704                                                                 &clock))
 705                                                 continue;
 706                                         if (match_clock &&
 707                                             clock.p != match_clock->p)
 708                                                 continue;
 709
 710                                         this_err = abs(clock.dot - target);
 711                                         if (this_err < err) {
 712                                                 *best_clock = clock;
 713                                                 err = this_err;
 714                                         }
 715                                 }
 716                         }
 717                 }
 718         }
 719
 720         return (err != target);
 721 }
 722
 723 /*
 724  * Returns a set of divisors for the desired target clock with the given
 725  * refclk, or FALSE.  The returned values represent the clock equation:
 726  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 727  *
 728  * Target and reference clocks are specified in kHz.
 729  *
 730  * If match_clock is provided, then best_clock P divider must match the P
 731  * divider from @match_clock used for LVDS downclocking.
 732  */
 733 static bool
 734 pnv_find_best_dpll(const struct intel_limit *limit,
 735                    struct intel_crtc_state *crtc_state,
 736                    int target, int refclk, struct dpll *match_clock,
 737                    struct dpll *best_clock)
 738 {
 739         struct drm_device *dev = crtc_state->base.crtc->dev;
 740         struct dpll clock;
 741         int err = target;
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744
 745         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 746
 747         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 748              clock.m1++) {
 749                 for (clock.m2 = limit->m2.min;
 750                      clock.m2 <= limit->m2.max; clock.m2++) {
 751                         for (clock.n = limit->n.min;
 752                              clock.n <= limit->n.max; clock.n++) {
 753                                 for (clock.p1 = limit->p1.min;
 754                                         clock.p1 <= limit->p1.max; clock.p1++) {
 755                                         int this_err;
 756
 757                                         pnv_calc_dpll_params(refclk, &clock);
 758                                         if (!intel_PLL_is_valid(to_i915(dev),
 759                                                                 limit,
 760                                                                 &clock))
 761                                                 continue;
 762                                         if (match_clock &&
 763                                             clock.p != match_clock->p)
 764                                                 continue;
 765
 766                                         this_err = abs(clock.dot - target);
 767                                         if (this_err < err) {
 768                                                 *best_clock = clock;
 769                                                 err = this_err;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return (err != target);
 777 }
 778
 779 /*
 780  * Returns a set of divisors for the desired target clock with the given
 781  * refclk, or FALSE.  The returned values represent the clock equation:
 782  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 783  *
 784  * Target and reference clocks are specified in kHz.
 785  *
 786  * If match_clock is provided, then best_clock P divider must match the P
 787  * divider from @match_clock used for LVDS downclocking.
 788  */
 789 static bool
 790 g4x_find_best_dpll(const struct intel_limit *limit,
 791                    struct intel_crtc_state *crtc_state,
 792                    int target, int refclk, struct dpll *match_clock,
 793                    struct dpll *best_clock)
 794 {
 795         struct drm_device *dev = crtc_state->base.crtc->dev;
 796         struct dpll clock;
 797         int max_n;
 798         bool found = false;
 799         /* approximately equals target * 0.00585 */
 800         int err_most = (target >> 8) + (target >> 9);
 801
 802         memset(best_clock, 0, sizeof(*best_clock));
 803
 804         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 805
 806         max_n = limit->n.max;
 807         /* based on hardware requirement, prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirement, prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         i9xx_calc_dpll_params(refclk, &clock);
 819                                         if (!intel_PLL_is_valid(to_i915(dev),
 820                                                                 limit,
 821                                                                 &clock))
 822                                                 continue;
 823
 824                                         this_err = abs(clock.dot - target);
 825                                         if (this_err < err_most) {
 826                                                 *best_clock = clock;
 827                                                 err_most = this_err;
 828                                                 max_n = clock.n;
 829                                                 found = true;
 830                                         }
 831                                 }
 832                         }
 833                 }
 834         }
 835         return found;
 836 }
 837
 838 /*
 839  * Check if the calculated PLL configuration is more optimal compared to the
 840  * best configuration and error found so far. Return the calculated error.
 841  */
 842 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 843                                const struct dpll *calculated_clock,
 844                                const struct dpll *best_clock,
 845                                unsigned int best_error_ppm,
 846                                unsigned int *error_ppm)
 847 {
 848         /*
 849          * For CHV ignore the error and consider only the P value.
 850          * Prefer a bigger P value based on HW requirements.
 851          */
 852         if (IS_CHERRYVIEW(to_i915(dev))) {
 853                 *error_ppm = 0;
 854
 855                 return calculated_clock->p > best_clock->p;
 856         }
 857
 858         if (WARN_ON_ONCE(!target_freq))
 859                 return false;
 860
 861         *error_ppm = div_u64(1000000ULL *
 862                                 abs(target_freq - calculated_clock->dot),
 863                              target_freq);
 864         /*
 865          * Prefer a better P value over a better (smaller) error if the error
 866          * is small. Ensure this preference for future configurations too by
 867          * setting the error to 0.
 868          */
 869         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 870                 *error_ppm = 0;
 871
 872                 return true;
 873         }
 874
 875         return *error_ppm + 10 < best_error_ppm;
 876 }
 877
 878 /*
 879  * Returns a set of divisors for the desired target clock with the given
 880  * refclk, or FALSE.  The returned values represent the clock equation:
 881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 882  */
 883 static bool
 884 vlv_find_best_dpll(const struct intel_limit *limit,
 885                    struct intel_crtc_state *crtc_state,
 886                    int target, int refclk, struct dpll *match_clock,
 887                    struct dpll *best_clock)
 888 {
 889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 890         struct drm_device *dev = crtc->base.dev;
 891         struct dpll clock;
 892         unsigned int bestppm = 1000000;
 893         /* min update 19.2 MHz */
 894         int max_n = min(limit->n.max, refclk / 19200);
 895         bool found = false;
 896
 897         target *= 5; /* fast clock */
 898
 899         memset(best_clock, 0, sizeof(*best_clock));
 900
 901         /* based on hardware requirement, prefer smaller n to precision */
 902         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 903                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 904                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 905                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 906                                 clock.p = clock.p1 * clock.p2;
 907                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 908                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 909                                         unsigned int ppm;
 910
 911                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 912                                                                      refclk * clock.m1);
 913
 914                                         vlv_calc_dpll_params(refclk, &clock);
 915
 916                                         if (!intel_PLL_is_valid(to_i915(dev),
 917                                                                 limit,
 918                                                                 &clock))
 919                                                 continue;
 920
 921                                         if (!vlv_PLL_is_optimal(dev, target,
 922                                                                 &clock,
 923                                                                 best_clock,
 924                                                                 bestppm, &ppm))
 925                                                 continue;
 926
 927                                         *best_clock = clock;
 928                                         bestppm = ppm;
 929                                         found = true;
 930                                 }
 931                         }
 932                 }
 933         }
 934
 935         return found;
 936 }
 937
 938 /*
 939  * Returns a set of divisors for the desired target clock with the given
 940  * refclk, or FALSE.  The returned values represent the clock equation:
 941  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 942  */
 943 static bool
 944 chv_find_best_dpll(const struct intel_limit *limit,
 945                    struct intel_crtc_state *crtc_state,
 946                    int target, int refclk, struct dpll *match_clock,
 947                    struct dpll *best_clock)
 948 {
 949         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 950         struct drm_device *dev = crtc->base.dev;
 951         unsigned int best_error_ppm;
 952         struct dpll clock;
 953         uint64_t m2;
 954         int found = false;
 955
 956         memset(best_clock, 0, sizeof(*best_clock));
 957         best_error_ppm = 1000000;
 958
 959         /*
 960          * Based on hardware doc, the n always set to 1, and m1 always
 961          * set to 2.  If requires to support 200Mhz refclk, we need to
 962          * revisit this because n may not 1 anymore.
 963          */
 964         clock.n = 1, clock.m1 = 2;
 965         target *= 5;    /* fast clock */
 966
 967         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 968                 for (clock.p2 = limit->p2.p2_fast;
 969                                 clock.p2 >= limit->p2.p2_slow;
 970                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 971                         unsigned int error_ppm;
 972
 973                         clock.p = clock.p1 * clock.p2;
 974
 975                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 976                                         clock.n) << 22, refclk * clock.m1);
 977
 978                         if (m2 > INT_MAX/clock.m1)
 979                                 continue;
 980
 981                         clock.m2 = m2;
 982
 983                         chv_calc_dpll_params(refclk, &clock);
 984
 985                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 986                                 continue;
 987
 988                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 989                                                 best_error_ppm, &error_ppm))
 990                                 continue;
 991
 992                         *best_clock = clock;
 993                         best_error_ppm = error_ppm;
 994                         found = true;
 995                 }
 996         }
 997
 998         return found;
 999 }
1000
1001 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1002                         struct dpll *best_clock)
1003 {
1004         int refclk = 100000;
1005         const struct intel_limit *limit = &intel_limits_bxt;
1006
1007         return chv_find_best_dpll(limit, crtc_state,
1008                                   target_clock, refclk, NULL, best_clock);
1009 }
1010
1011 bool intel_crtc_active(struct intel_crtc *crtc)
1012 {
1013         /* Be paranoid as we can arrive here with only partial
1014          * state retrieved from the hardware during setup.
1015          *
1016          * We can ditch the adjusted_mode.crtc_clock check as soon
1017          * as Haswell has gained clock readout/fastboot support.
1018          *
1019          * We can ditch the crtc->primary->fb check as soon as we can
1020          * properly reconstruct framebuffers.
1021          *
1022          * FIXME: The intel_crtc->active here should be switched to
1023          * crtc->state->active once we have proper CRTC states wired up
1024          * for atomic.
1025          */
1026         return crtc->active && crtc->base.primary->state->fb &&
1027                 crtc->config->base.adjusted_mode.crtc_clock;
1028 }
1029
1030 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1031                                              enum pipe pipe)
1032 {
1033         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1034
1035         return crtc->config->cpu_transcoder;
1036 }
1037
1038 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1039 {
1040         i915_reg_t reg = PIPEDSL(pipe);
1041         u32 line1, line2;
1042         u32 line_mask;
1043
1044         if (IS_GEN2(dev_priv))
1045                 line_mask = DSL_LINEMASK_GEN2;
1046         else
1047                 line_mask = DSL_LINEMASK_GEN3;
1048
1049         line1 = I915_READ(reg) & line_mask;
1050         msleep(5);
1051         line2 = I915_READ(reg) & line_mask;
1052
1053         return line1 == line2;
1054 }
1055
1056 /*
1057  * intel_wait_for_pipe_off - wait for pipe to turn off
1058  * @crtc: crtc whose pipe to wait for
1059  *
1060  * After disabling a pipe, we can't wait for vblank in the usual way,
1061  * spinning on the vblank interrupt status bit, since we won't actually
1062  * see an interrupt when the pipe is disabled.
1063  *
1064  * On Gen4 and above:
1065  *   wait for the pipe register state bit to turn off
1066  *
1067  * Otherwise:
1068  *   wait for the display line value to settle (it usually
1069  *   ends up stopping at the start of the next frame).
1070  *
1071  */
1072 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1073 {
1074         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076         enum pipe pipe = crtc->pipe;
1077
1078         if (INTEL_GEN(dev_priv) >= 4) {
1079                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081                 /* Wait for the Pipe State to go off */
1082                 if (intel_wait_for_register(dev_priv,
1083                                             reg, I965_PIPECONF_ACTIVE, 0,
1084                                             100))
1085                         WARN(1, "pipe_off wait timed out\n");
1086         } else {
1087                 /* Wait for the display line to settle */
1088                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1089                         WARN(1, "pipe_off wait timed out\n");
1090         }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state)
1096 {
1097         u32 val;
1098         bool cur_state;
1099
1100         val = I915_READ(DPLL(pipe));
1101         cur_state = !!(val & DPLL_VCO_ENABLE);
1102         I915_STATE_WARN(cur_state != state,
1103              "PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112
1113         mutex_lock(&dev_priv->sb_lock);
1114         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115         mutex_unlock(&dev_priv->sb_lock);
1116
1117         cur_state = val & DSI_PLL_VCO_EN;
1118         I915_STATE_WARN(cur_state != state,
1119              "DSI PLL state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124                           enum pipe pipe, bool state)
1125 {
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (HAS_DDI(dev_priv)) {
1131                 /* DDI does not have a specific FDI_TX register */
1132                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134         } else {
1135                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         I915_STATE_WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150
1151         val = I915_READ(FDI_RX_CTL(pipe));
1152         cur_state = !!(val & FDI_RX_ENABLE);
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI RX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161                                       enum pipe pipe)
1162 {
1163         u32 val;
1164
1165         /* ILK FDI PLL is always enabled */
1166         if (IS_GEN5(dev_priv))
1167                 return;
1168
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv))
1171                 return;
1172
1173         val = I915_READ(FDI_TX_CTL(pipe));
1174         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         u32 val;
1181         bool cur_state;
1182
1183         val = I915_READ(FDI_RX_CTL(pipe));
1184         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185         I915_STATE_WARN(cur_state != state,
1186              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187                         onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1191 {
1192         i915_reg_t pp_reg;
1193         u32 val;
1194         enum pipe panel_pipe = PIPE_A;
1195         bool locked = true;
1196
1197         if (WARN_ON(HAS_DDI(dev_priv)))
1198                 return;
1199
1200         if (HAS_PCH_SPLIT(dev_priv)) {
1201                 u32 port_sel;
1202
1203                 pp_reg = PP_CONTROL(0);
1204                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1205
1206                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1207                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1208                         panel_pipe = PIPE_B;
1209                 /* XXX: else fix for eDP */
1210         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1211                 /* presumably write lock depends on pipe, not port select */
1212                 pp_reg = PP_CONTROL(pipe);
1213                 panel_pipe = pipe;
1214         } else {
1215                 pp_reg = PP_CONTROL(0);
1216                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1217                         panel_pipe = PIPE_B;
1218         }
1219
1220         val = I915_READ(pp_reg);
1221         if (!(val & PANEL_POWER_ON) ||
1222             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1223                 locked = false;
1224
1225         I915_STATE_WARN(panel_pipe == pipe && locked,
1226              "panel assertion failure, pipe %c regs locked\n",
1227              pipe_name(pipe));
1228 }
1229
1230 static void assert_cursor(struct drm_i915_private *dev_priv,
1231                           enum pipe pipe, bool state)
1232 {
1233         bool cur_state;
1234
1235         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
1236                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1237         else
1238                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1239
1240         I915_STATE_WARN(cur_state != state,
1241              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1242                         pipe_name(pipe), onoff(state), onoff(cur_state));
1243 }
1244 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1245 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1246
1247 void assert_pipe(struct drm_i915_private *dev_priv,
1248                  enum pipe pipe, bool state)
1249 {
1250         bool cur_state;
1251         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1252                                                                       pipe);
1253         enum intel_display_power_domain power_domain;
1254
1255         /* if we need the pipe quirk it must be always on */
1256         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1257             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1258                 state = true;
1259
1260         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1261         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1262                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1263                 cur_state = !!(val & PIPECONF_ENABLE);
1264
1265                 intel_display_power_put(dev_priv, power_domain);
1266         } else {
1267                 cur_state = false;
1268         }
1269
1270         I915_STATE_WARN(cur_state != state,
1271              "pipe %c assertion failure (expected %s, current %s)\n",
1272                         pipe_name(pipe), onoff(state), onoff(cur_state));
1273 }
1274
1275 static void assert_plane(struct drm_i915_private *dev_priv,
1276                          enum plane plane, bool state)
1277 {
1278         u32 val;
1279         bool cur_state;
1280
1281         val = I915_READ(DSPCNTR(plane));
1282         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1283         I915_STATE_WARN(cur_state != state,
1284              "plane %c assertion failure (expected %s, current %s)\n",
1285                         plane_name(plane), onoff(state), onoff(cur_state));
1286 }
1287
1288 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1289 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1290
1291 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1292                                    enum pipe pipe)
1293 {
1294         int i;
1295
1296         /* Primary planes are fixed to pipes on gen4+ */
1297         if (INTEL_GEN(dev_priv) >= 4) {
1298                 u32 val = I915_READ(DSPCNTR(pipe));
1299                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1300                      "plane %c assertion failure, should be disabled but not\n",
1301                      plane_name(pipe));
1302                 return;
1303         }
1304
1305         /* Need to check both planes against the pipe */
1306         for_each_pipe(dev_priv, i) {
1307                 u32 val = I915_READ(DSPCNTR(i));
1308                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1309                         DISPPLANE_SEL_PIPE_SHIFT;
1310                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1311                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1312                      plane_name(i), pipe_name(pipe));
1313         }
1314 }
1315
1316 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1317                                     enum pipe pipe)
1318 {
1319         int sprite;
1320
1321         if (INTEL_GEN(dev_priv) >= 9) {
1322                 for_each_sprite(dev_priv, pipe, sprite) {
1323                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1324                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1325                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1326                              sprite, pipe_name(pipe));
1327                 }
1328         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1329                 for_each_sprite(dev_priv, pipe, sprite) {
1330                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1331                         I915_STATE_WARN(val & SP_ENABLE,
1332                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1333                              sprite_name(pipe, sprite), pipe_name(pipe));
1334                 }
1335         } else if (INTEL_GEN(dev_priv) >= 7) {
1336                 u32 val = I915_READ(SPRCTL(pipe));
1337                 I915_STATE_WARN(val & SPRITE_ENABLE,
1338                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1339                      plane_name(pipe), pipe_name(pipe));
1340         } else if (INTEL_GEN(dev_priv) >= 5) {
1341                 u32 val = I915_READ(DVSCNTR(pipe));
1342                 I915_STATE_WARN(val & DVS_ENABLE,
1343                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                      plane_name(pipe), pipe_name(pipe));
1345         }
1346 }
1347
1348 static void assert_vblank_disabled(struct drm_crtc *crtc)
1349 {
1350         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1351                 drm_crtc_vblank_put(crtc);
1352 }
1353
1354 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355                                     enum pipe pipe)
1356 {
1357         u32 val;
1358         bool enabled;
1359
1360         val = I915_READ(PCH_TRANSCONF(pipe));
1361         enabled = !!(val & TRANS_ENABLE);
1362         I915_STATE_WARN(enabled,
1363              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1364              pipe_name(pipe));
1365 }
1366
1367 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1368                             enum pipe pipe, u32 port_sel, u32 val)
1369 {
1370         if ((val & DP_PORT_EN) == 0)
1371                 return false;
1372
1373         if (HAS_PCH_CPT(dev_priv)) {
1374                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1375                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376                         return false;
1377         } else if (IS_CHERRYVIEW(dev_priv)) {
1378                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379                         return false;
1380         } else {
1381                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382                         return false;
1383         }
1384         return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388                               enum pipe pipe, u32 val)
1389 {
1390         if ((val & SDVO_ENABLE) == 0)
1391                 return false;
1392
1393         if (HAS_PCH_CPT(dev_priv)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395                         return false;
1396         } else if (IS_CHERRYVIEW(dev_priv)) {
1397                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398                         return false;
1399         } else {
1400                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401                         return false;
1402         }
1403         return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407                               enum pipe pipe, u32 val)
1408 {
1409         if ((val & LVDS_PORT_EN) == 0)
1410                 return false;
1411
1412         if (HAS_PCH_CPT(dev_priv)) {
1413                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414                         return false;
1415         } else {
1416                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417                         return false;
1418         }
1419         return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423                               enum pipe pipe, u32 val)
1424 {
1425         if ((val & ADPA_DAC_ENABLE) == 0)
1426                 return false;
1427         if (HAS_PCH_CPT(dev_priv)) {
1428                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429                         return false;
1430         } else {
1431                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432                         return false;
1433         }
1434         return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438                                    enum pipe pipe, i915_reg_t reg,
1439                                    u32 port_sel)
1440 {
1441         u32 val = I915_READ(reg);
1442         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1443              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1444              i915_mmio_reg_offset(reg), pipe_name(pipe));
1445
1446         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1447              && (val & DP_PIPEB_SELECT),
1448              "IBX PCH dp port still using transcoder B\n");
1449 }
1450
1451 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1452                                      enum pipe pipe, i915_reg_t reg)
1453 {
1454         u32 val = I915_READ(reg);
1455         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1456              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1457              i915_mmio_reg_offset(reg), pipe_name(pipe));
1458
1459         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1460              && (val & SDVO_PIPE_B_SELECT),
1461              "IBX PCH hdmi port still using transcoder B\n");
1462 }
1463
1464 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1465                                       enum pipe pipe)
1466 {
1467         u32 val;
1468
1469         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473         val = I915_READ(PCH_ADPA);
1474         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1475              "PCH VGA enabled on transcoder %c, should be disabled\n",
1476              pipe_name(pipe));
1477
1478         val = I915_READ(PCH_LVDS);
1479         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1480              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1485         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1486 }
1487
1488 static void _vlv_enable_pll(struct intel_crtc *crtc,
1489                             const struct intel_crtc_state *pipe_config)
1490 {
1491         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1492         enum pipe pipe = crtc->pipe;
1493
1494         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1495         POSTING_READ(DPLL(pipe));
1496         udelay(150);
1497
1498         if (intel_wait_for_register(dev_priv,
1499                                     DPLL(pipe),
1500                                     DPLL_LOCK_VLV,
1501                                     DPLL_LOCK_VLV,
1502                                     1))
1503                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1504 }
1505
1506 static void vlv_enable_pll(struct intel_crtc *crtc,
1507                            const struct intel_crtc_state *pipe_config)
1508 {
1509         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1510         enum pipe pipe = crtc->pipe;
1511
1512         assert_pipe_disabled(dev_priv, pipe);
1513
1514         /* PLL is protected by panel, make sure we can write it */
1515         assert_panel_unlocked(dev_priv, pipe);
1516
1517         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1518                 _vlv_enable_pll(crtc, pipe_config);
1519
1520         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1521         POSTING_READ(DPLL_MD(pipe));
1522 }
1523
1524
1525 static void _chv_enable_pll(struct intel_crtc *crtc,
1526                             const struct intel_crtc_state *pipe_config)
1527 {
1528         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1529         enum pipe pipe = crtc->pipe;
1530         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1531         u32 tmp;
1532
1533         mutex_lock(&dev_priv->sb_lock);
1534
1535         /* Enable back the 10bit clock to display controller */
1536         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1537         tmp |= DPIO_DCLKP_EN;
1538         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1539
1540         mutex_unlock(&dev_priv->sb_lock);
1541
1542         /*
1543          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1544          */
1545         udelay(1);
1546
1547         /* Enable PLL */
1548         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1549
1550         /* Check PLL is locked */
1551         if (intel_wait_for_register(dev_priv,
1552                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1553                                     1))
1554                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1555 }
1556
1557 static void chv_enable_pll(struct intel_crtc *crtc,
1558                            const struct intel_crtc_state *pipe_config)
1559 {
1560         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561         enum pipe pipe = crtc->pipe;
1562
1563         assert_pipe_disabled(dev_priv, pipe);
1564
1565         /* PLL is protected by panel, make sure we can write it */
1566         assert_panel_unlocked(dev_priv, pipe);
1567
1568         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1569                 _chv_enable_pll(crtc, pipe_config);
1570
1571         if (pipe != PIPE_A) {
1572                 /*
1573                  * WaPixelRepeatModeFixForC0:chv
1574                  *
1575                  * DPLLCMD is AWOL. Use chicken bits to propagate
1576                  * the value from DPLLBMD to either pipe B or C.
1577                  */
1578                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1579                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1580                 I915_WRITE(CBR4_VLV, 0);
1581                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1582
1583                 /*
1584                  * DPLLB VGA mode also seems to cause problems.
1585                  * We should always have it disabled.
1586                  */
1587                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1588         } else {
1589                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1590                 POSTING_READ(DPLL_MD(pipe));
1591         }
1592 }
1593
1594 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1595 {
1596         struct intel_crtc *crtc;
1597         int count = 0;
1598
1599         for_each_intel_crtc(&dev_priv->drm, crtc) {
1600                 count += crtc->base.state->active &&
1601                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1602         }
1603
1604         return count;
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1610         i915_reg_t reg = DPLL(crtc->pipe);
1611         u32 dpll = crtc->config->dpll_hw_state.dpll;
1612
1613         assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615         /* PLL is protected by panel, make sure we can write it */
1616         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1617                 assert_panel_unlocked(dev_priv, crtc->pipe);
1618
1619         /* Enable DVO 2x clock on both PLLs if necessary */
1620         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1621                 /*
1622                  * It appears to be important that we don't enable this
1623                  * for the current pipe before otherwise configuring the
1624                  * PLL. No idea how this should be handled if multiple
1625                  * DVO outputs are enabled simultaneosly.
1626                  */
1627                 dpll |= DPLL_DVO_2X_MODE;
1628                 I915_WRITE(DPLL(!crtc->pipe),
1629                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1630         }
1631
1632         /*
1633          * Apparently we need to have VGA mode enabled prior to changing
1634          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1635          * dividers, even though the register value does change.
1636          */
1637         I915_WRITE(reg, 0);
1638
1639         I915_WRITE(reg, dpll);
1640
1641         /* Wait for the clocks to stabilize. */
1642         POSTING_READ(reg);
1643         udelay(150);
1644
1645         if (INTEL_GEN(dev_priv) >= 4) {
1646                 I915_WRITE(DPLL_MD(crtc->pipe),
1647                            crtc->config->dpll_hw_state.dpll_md);
1648         } else {
1649                 /* The pixel multiplier can only be updated once the
1650                  * DPLL is enabled and the clocks are stable.
1651                  *
1652                  * So write it again.
1653                  */
1654                 I915_WRITE(reg, dpll);
1655         }
1656
1657         /* We do this three times for luck */
1658         I915_WRITE(reg, dpll);
1659         POSTING_READ(reg);
1660         udelay(150); /* wait for warmup */
1661         I915_WRITE(reg, dpll);
1662         POSTING_READ(reg);
1663         udelay(150); /* wait for warmup */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667 }
1668
1669 /**
1670  * i9xx_disable_pll - disable a PLL
1671  * @dev_priv: i915 private structure
1672  * @pipe: pipe PLL to disable
1673  *
1674  * Disable the PLL for @pipe, making sure the pipe is off first.
1675  *
1676  * Note!  This is for pre-ILK only.
1677  */
1678 static void i9xx_disable_pll(struct intel_crtc *crtc)
1679 {
1680         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1681         enum pipe pipe = crtc->pipe;
1682
1683         /* Disable DVO 2x clock on both PLLs if necessary */
1684         if (IS_I830(dev_priv) &&
1685             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1686             !intel_num_dvo_pipes(dev_priv)) {
1687                 I915_WRITE(DPLL(PIPE_B),
1688                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1689                 I915_WRITE(DPLL(PIPE_A),
1690                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1691         }
1692
1693         /* Don't disable pipe or pipe PLLs if needed */
1694         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1695             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1696                 return;
1697
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700
1701         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1702         POSTING_READ(DPLL(pipe));
1703 }
1704
1705 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1706 {
1707         u32 val;
1708
1709         /* Make sure the pipe isn't still relying on us */
1710         assert_pipe_disabled(dev_priv, pipe);
1711
1712         val = DPLL_INTEGRATED_REF_CLK_VLV |
1713                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1714         if (pipe != PIPE_A)
1715                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1716
1717         I915_WRITE(DPLL(pipe), val);
1718         POSTING_READ(DPLL(pipe));
1719 }
1720
1721 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1722 {
1723         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1724         u32 val;
1725
1726         /* Make sure the pipe isn't still relying on us */
1727         assert_pipe_disabled(dev_priv, pipe);
1728
1729         val = DPLL_SSC_REF_CLK_CHV |
1730                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1731         if (pipe != PIPE_A)
1732                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1733
1734         I915_WRITE(DPLL(pipe), val);
1735         POSTING_READ(DPLL(pipe));
1736
1737         mutex_lock(&dev_priv->sb_lock);
1738
1739         /* Disable 10bit clock to display controller */
1740         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1741         val &= ~DPIO_DCLKP_EN;
1742         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1743
1744         mutex_unlock(&dev_priv->sb_lock);
1745 }
1746
1747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1748                          struct intel_digital_port *dport,
1749                          unsigned int expected_mask)
1750 {
1751         u32 port_mask;
1752         i915_reg_t dpll_reg;
1753
1754         switch (dport->port) {
1755         case PORT_B:
1756                 port_mask = DPLL_PORTB_READY_MASK;
1757                 dpll_reg = DPLL(0);
1758                 break;
1759         case PORT_C:
1760                 port_mask = DPLL_PORTC_READY_MASK;
1761                 dpll_reg = DPLL(0);
1762                 expected_mask <<= 4;
1763                 break;
1764         case PORT_D:
1765                 port_mask = DPLL_PORTD_READY_MASK;
1766                 dpll_reg = DPIO_PHY_STATUS;
1767                 break;
1768         default:
1769                 BUG();
1770         }
1771
1772         if (intel_wait_for_register(dev_priv,
1773                                     dpll_reg, port_mask, expected_mask,
1774                                     1000))
1775                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1776                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1777 }
1778
1779 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1780                                            enum pipe pipe)
1781 {
1782         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1783                                                                 pipe);
1784         i915_reg_t reg;
1785         uint32_t val, pipeconf_val;
1786
1787         /* Make sure PCH DPLL is enabled */
1788         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1789
1790         /* FDI must be feeding us bits for PCH ports */
1791         assert_fdi_tx_enabled(dev_priv, pipe);
1792         assert_fdi_rx_enabled(dev_priv, pipe);
1793
1794         if (HAS_PCH_CPT(dev_priv)) {
1795                 /* Workaround: Set the timing override bit before enabling the
1796                  * pch transcoder. */
1797                 reg = TRANS_CHICKEN2(pipe);
1798                 val = I915_READ(reg);
1799                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1800                 I915_WRITE(reg, val);
1801         }
1802
1803         reg = PCH_TRANSCONF(pipe);
1804         val = I915_READ(reg);
1805         pipeconf_val = I915_READ(PIPECONF(pipe));
1806
1807         if (HAS_PCH_IBX(dev_priv)) {
1808                 /*
1809                  * Make the BPC in transcoder be consistent with
1810                  * that in pipeconf reg. For HDMI we must use 8bpc
1811                  * here for both 8bpc and 12bpc.
1812                  */
1813                 val &= ~PIPECONF_BPC_MASK;
1814                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1815                         val |= PIPECONF_8BPC;
1816                 else
1817                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1818         }
1819
1820         val &= ~TRANS_INTERLACE_MASK;
1821         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1822                 if (HAS_PCH_IBX(dev_priv) &&
1823                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1824                         val |= TRANS_LEGACY_INTERLACED_ILK;
1825                 else
1826                         val |= TRANS_INTERLACED;
1827         else
1828                 val |= TRANS_PROGRESSIVE;
1829
1830         I915_WRITE(reg, val | TRANS_ENABLE);
1831         if (intel_wait_for_register(dev_priv,
1832                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1833                                     100))
1834                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1835 }
1836
1837 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1838                                       enum transcoder cpu_transcoder)
1839 {
1840         u32 val, pipeconf_val;
1841
1842         /* FDI must be feeding us bits for PCH ports */
1843         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1844         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1845
1846         /* Workaround: set timing override bit. */
1847         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1848         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1849         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1850
1851         val = TRANS_ENABLE;
1852         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1853
1854         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1855             PIPECONF_INTERLACED_ILK)
1856                 val |= TRANS_INTERLACED;
1857         else
1858                 val |= TRANS_PROGRESSIVE;
1859
1860         I915_WRITE(LPT_TRANSCONF, val);
1861         if (intel_wait_for_register(dev_priv,
1862                                     LPT_TRANSCONF,
1863                                     TRANS_STATE_ENABLE,
1864                                     TRANS_STATE_ENABLE,
1865                                     100))
1866                 DRM_ERROR("Failed to enable PCH transcoder\n");
1867 }
1868
1869 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1870                                             enum pipe pipe)
1871 {
1872         i915_reg_t reg;
1873         uint32_t val;
1874
1875         /* FDI relies on the transcoder */
1876         assert_fdi_tx_disabled(dev_priv, pipe);
1877         assert_fdi_rx_disabled(dev_priv, pipe);
1878
1879         /* Ports must be off as well */
1880         assert_pch_ports_disabled(dev_priv, pipe);
1881
1882         reg = PCH_TRANSCONF(pipe);
1883         val = I915_READ(reg);
1884         val &= ~TRANS_ENABLE;
1885         I915_WRITE(reg, val);
1886         /* wait for PCH transcoder off, transcoder state */
1887         if (intel_wait_for_register(dev_priv,
1888                                     reg, TRANS_STATE_ENABLE, 0,
1889                                     50))
1890                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1891
1892         if (HAS_PCH_CPT(dev_priv)) {
1893                 /* Workaround: Clear the timing override chicken bit again. */
1894                 reg = TRANS_CHICKEN2(pipe);
1895                 val = I915_READ(reg);
1896                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1897                 I915_WRITE(reg, val);
1898         }
1899 }
1900
1901 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1902 {
1903         u32 val;
1904
1905         val = I915_READ(LPT_TRANSCONF);
1906         val &= ~TRANS_ENABLE;
1907         I915_WRITE(LPT_TRANSCONF, val);
1908         /* wait for PCH transcoder off, transcoder state */
1909         if (intel_wait_for_register(dev_priv,
1910                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1911                                     50))
1912                 DRM_ERROR("Failed to disable PCH transcoder\n");
1913
1914         /* Workaround: clear timing override bit. */
1915         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1916         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1918 }
1919
1920 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1921 {
1922         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1923
1924         WARN_ON(!crtc->config->has_pch_encoder);
1925
1926         if (HAS_PCH_LPT(dev_priv))
1927                 return TRANSCODER_A;
1928         else
1929                 return (enum transcoder) crtc->pipe;
1930 }
1931
1932 /**
1933  * intel_enable_pipe - enable a pipe, asserting requirements
1934  * @crtc: crtc responsible for the pipe
1935  *
1936  * Enable @crtc's pipe, making sure that various hardware specific requirements
1937  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1938  */
1939 static void intel_enable_pipe(struct intel_crtc *crtc)
1940 {
1941         struct drm_device *dev = crtc->base.dev;
1942         struct drm_i915_private *dev_priv = to_i915(dev);
1943         enum pipe pipe = crtc->pipe;
1944         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1945         i915_reg_t reg;
1946         u32 val;
1947
1948         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1949
1950         assert_planes_disabled(dev_priv, pipe);
1951         assert_cursor_disabled(dev_priv, pipe);
1952         assert_sprites_disabled(dev_priv, pipe);
1953
1954         /*
1955          * A pipe without a PLL won't actually be able to drive bits from
1956          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1957          * need the check.
1958          */
1959         if (HAS_GMCH_DISPLAY(dev_priv)) {
1960                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1961                         assert_dsi_pll_enabled(dev_priv);
1962                 else
1963                         assert_pll_enabled(dev_priv, pipe);
1964         } else {
1965                 if (crtc->config->has_pch_encoder) {
1966                         /* if driving the PCH, we need FDI enabled */
1967                         assert_fdi_rx_pll_enabled(dev_priv,
1968                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1969                         assert_fdi_tx_pll_enabled(dev_priv,
1970                                                   (enum pipe) cpu_transcoder);
1971                 }
1972                 /* FIXME: assert CPU port conditions for SNB+ */
1973         }
1974
1975         reg = PIPECONF(cpu_transcoder);
1976         val = I915_READ(reg);
1977         if (val & PIPECONF_ENABLE) {
1978                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1979                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1980                 return;
1981         }
1982
1983         I915_WRITE(reg, val | PIPECONF_ENABLE);
1984         POSTING_READ(reg);
1985
1986         /*
1987          * Until the pipe starts DSL will read as 0, which would cause
1988          * an apparent vblank timestamp jump, which messes up also the
1989          * frame count when it's derived from the timestamps. So let's
1990          * wait for the pipe to start properly before we call
1991          * drm_crtc_vblank_on()
1992          */
1993         if (dev->max_vblank_count == 0 &&
1994             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1995                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1996 }
1997
1998 /**
1999  * intel_disable_pipe - disable a pipe, asserting requirements
2000  * @crtc: crtc whose pipes is to be disabled
2001  *
2002  * Disable the pipe of @crtc, making sure that various hardware
2003  * specific requirements are met, if applicable, e.g. plane
2004  * disabled, panel fitter off, etc.
2005  *
2006  * Will wait until the pipe has shut down before returning.
2007  */
2008 static void intel_disable_pipe(struct intel_crtc *crtc)
2009 {
2010         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2011         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2012         enum pipe pipe = crtc->pipe;
2013         i915_reg_t reg;
2014         u32 val;
2015
2016         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2017
2018         /*
2019          * Make sure planes won't keep trying to pump pixels to us,
2020          * or we might hang the display.
2021          */
2022         assert_planes_disabled(dev_priv, pipe);
2023         assert_cursor_disabled(dev_priv, pipe);
2024         assert_sprites_disabled(dev_priv, pipe);
2025
2026         reg = PIPECONF(cpu_transcoder);
2027         val = I915_READ(reg);
2028         if ((val & PIPECONF_ENABLE) == 0)
2029                 return;
2030
2031         /*
2032          * Double wide has implications for planes
2033          * so best keep it disabled when not needed.
2034          */
2035         if (crtc->config->double_wide)
2036                 val &= ~PIPECONF_DOUBLE_WIDE;
2037
2038         /* Don't disable pipe or pipe PLLs if needed */
2039         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2040             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2041                 val &= ~PIPECONF_ENABLE;
2042
2043         I915_WRITE(reg, val);
2044         if ((val & PIPECONF_ENABLE) == 0)
2045                 intel_wait_for_pipe_off(crtc);
2046 }
2047
2048 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2049 {
2050         return IS_GEN2(dev_priv) ? 2048 : 4096;
2051 }
2052
2053 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2054                                            uint64_t fb_modifier, unsigned int cpp)
2055 {
2056         switch (fb_modifier) {
2057         case DRM_FORMAT_MOD_NONE:
2058                 return cpp;
2059         case I915_FORMAT_MOD_X_TILED:
2060                 if (IS_GEN2(dev_priv))
2061                         return 128;
2062                 else
2063                         return 512;
2064         case I915_FORMAT_MOD_Y_TILED:
2065                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2066                         return 128;
2067                 else
2068                         return 512;
2069         case I915_FORMAT_MOD_Yf_TILED:
2070                 switch (cpp) {
2071                 case 1:
2072                         return 64;
2073                 case 2:
2074                 case 4:
2075                         return 128;
2076                 case 8:
2077                 case 16:
2078                         return 256;
2079                 default:
2080                         MISSING_CASE(cpp);
2081                         return cpp;
2082                 }
2083                 break;
2084         default:
2085                 MISSING_CASE(fb_modifier);
2086                 return cpp;
2087         }
2088 }
2089
2090 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2091                                uint64_t fb_modifier, unsigned int cpp)
2092 {
2093         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2094                 return 1;
2095         else
2096                 return intel_tile_size(dev_priv) /
2097                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2098 }
2099
2100 /* Return the tile dimensions in pixel units */
2101 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2102                             unsigned int *tile_width,
2103                             unsigned int *tile_height,
2104                             uint64_t fb_modifier,
2105                             unsigned int cpp)
2106 {
2107         unsigned int tile_width_bytes =
2108                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2109
2110         *tile_width = tile_width_bytes / cpp;
2111         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2112 }
2113
2114 unsigned int
2115 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2116                       uint32_t pixel_format, uint64_t fb_modifier)
2117 {
2118         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2119         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2120
2121         return ALIGN(height, tile_height);
2122 }
2123
2124 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2125 {
2126         unsigned int size = 0;
2127         int i;
2128
2129         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2130                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2131
2132         return size;
2133 }
2134
2135 static void
2136 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2137                         const struct drm_framebuffer *fb,
2138                         unsigned int rotation)
2139 {
2140         if (drm_rotation_90_or_270(rotation)) {
2141                 *view = i915_ggtt_view_rotated;
2142                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2143         } else {
2144                 *view = i915_ggtt_view_normal;
2145         }
2146 }
2147
2148 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2149 {
2150         if (INTEL_INFO(dev_priv)->gen >= 9)
2151                 return 256 * 1024;
2152         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2153                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2154                 return 128 * 1024;
2155         else if (INTEL_INFO(dev_priv)->gen >= 4)
2156                 return 4 * 1024;
2157         else
2158                 return 0;
2159 }
2160
2161 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2162                                          uint64_t fb_modifier)
2163 {
2164         switch (fb_modifier) {
2165         case DRM_FORMAT_MOD_NONE:
2166                 return intel_linear_alignment(dev_priv);
2167         case I915_FORMAT_MOD_X_TILED:
2168                 if (INTEL_INFO(dev_priv)->gen >= 9)
2169                         return 256 * 1024;
2170                 return 0;
2171         case I915_FORMAT_MOD_Y_TILED:
2172         case I915_FORMAT_MOD_Yf_TILED:
2173                 return 1 * 1024 * 1024;
2174         default:
2175                 MISSING_CASE(fb_modifier);
2176                 return 0;
2177         }
2178 }
2179
2180 struct i915_vma *
2181 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2182 {
2183         struct drm_device *dev = fb->dev;
2184         struct drm_i915_private *dev_priv = to_i915(dev);
2185         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2186         struct i915_ggtt_view view;
2187         struct i915_vma *vma;
2188         u32 alignment;
2189
2190         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2191
2192         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2193
2194         intel_fill_fb_ggtt_view(&view, fb, rotation);
2195
2196         /* Note that the w/a also requires 64 PTE of padding following the
2197          * bo. We currently fill all unused PTE with the shadow page and so
2198          * we should always have valid PTE following the scanout preventing
2199          * the VT-d warning.
2200          */
2201         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2202                 alignment = 256 * 1024;
2203
2204         /*
2205          * Global gtt pte registers are special registers which actually forward
2206          * writes to a chunk of system memory. Which means that there is no risk
2207          * that the register values disappear as soon as we call
2208          * intel_runtime_pm_put(), so it is correct to wrap only the
2209          * pin/unpin/fence and not more.
2210          */
2211         intel_runtime_pm_get(dev_priv);
2212
2213         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2214         if (IS_ERR(vma))
2215                 goto err;
2216
2217         if (i915_vma_is_map_and_fenceable(vma)) {
2218                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2219                  * fence, whereas 965+ only requires a fence if using
2220                  * framebuffer compression.  For simplicity, we always, when
2221                  * possible, install a fence as the cost is not that onerous.
2222                  *
2223                  * If we fail to fence the tiled scanout, then either the
2224                  * modeset will reject the change (which is highly unlikely as
2225                  * the affected systems, all but one, do not have unmappable
2226                  * space) or we will not be able to enable full powersaving
2227                  * techniques (also likely not to apply due to various limits
2228                  * FBC and the like impose on the size of the buffer, which
2229                  * presumably we violated anyway with this unmappable buffer).
2230                  * Anyway, it is presumably better to stumble onwards with
2231                  * something and try to run the system in a "less than optimal"
2232                  * mode that matches the user configuration.
2233                  */
2234                 if (i915_vma_get_fence(vma) == 0)
2235                         i915_vma_pin_fence(vma);
2236         }
2237
2238 err:
2239         intel_runtime_pm_put(dev_priv);
2240         return vma;
2241 }
2242
2243 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2244 {
2245         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2246         struct i915_ggtt_view view;
2247         struct i915_vma *vma;
2248
2249         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2250
2251         intel_fill_fb_ggtt_view(&view, fb, rotation);
2252         vma = i915_gem_object_to_ggtt(obj, &view);
2253
2254         i915_vma_unpin_fence(vma);
2255         i915_gem_object_unpin_from_display_plane(vma);
2256 }
2257
2258 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2259                           unsigned int rotation)
2260 {
2261         if (drm_rotation_90_or_270(rotation))
2262                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2263         else
2264                 return fb->pitches[plane];
2265 }
2266
2267 /*
2268  * Convert the x/y offsets into a linear offset.
2269  * Only valid with 0/180 degree rotation, which is fine since linear
2270  * offset is only used with linear buffers on pre-hsw and tiled buffers
2271  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2272  */
2273 u32 intel_fb_xy_to_linear(int x, int y,
2274                           const struct intel_plane_state *state,
2275                           int plane)
2276 {
2277         const struct drm_framebuffer *fb = state->base.fb;
2278         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2279         unsigned int pitch = fb->pitches[plane];
2280
2281         return y * pitch + x * cpp;
2282 }
2283
2284 /*
2285  * Add the x/y offsets derived from fb->offsets[] to the user
2286  * specified plane src x/y offsets. The resulting x/y offsets
2287  * specify the start of scanout from the beginning of the gtt mapping.
2288  */
2289 void intel_add_fb_offsets(int *x, int *y,
2290                           const struct intel_plane_state *state,
2291                           int plane)
2292
2293 {
2294         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2295         unsigned int rotation = state->base.rotation;
2296
2297         if (drm_rotation_90_or_270(rotation)) {
2298                 *x += intel_fb->rotated[plane].x;
2299                 *y += intel_fb->rotated[plane].y;
2300         } else {
2301                 *x += intel_fb->normal[plane].x;
2302                 *y += intel_fb->normal[plane].y;
2303         }
2304 }
2305
2306 /*
2307  * Input tile dimensions and pitch must already be
2308  * rotated to match x and y, and in pixel units.
2309  */
2310 static u32 _intel_adjust_tile_offset(int *x, int *y,
2311                                      unsigned int tile_width,
2312                                      unsigned int tile_height,
2313                                      unsigned int tile_size,
2314                                      unsigned int pitch_tiles,
2315                                      u32 old_offset,
2316                                      u32 new_offset)
2317 {
2318         unsigned int pitch_pixels = pitch_tiles * tile_width;
2319         unsigned int tiles;
2320
2321         WARN_ON(old_offset & (tile_size - 1));
2322         WARN_ON(new_offset & (tile_size - 1));
2323         WARN_ON(new_offset > old_offset);
2324
2325         tiles = (old_offset - new_offset) / tile_size;
2326
2327         *y += tiles / pitch_tiles * tile_height;
2328         *x += tiles % pitch_tiles * tile_width;
2329
2330         /* minimize x in case it got needlessly big */
2331         *y += *x / pitch_pixels * tile_height;
2332         *x %= pitch_pixels;
2333
2334         return new_offset;
2335 }
2336
2337 /*
2338  * Adjust the tile offset by moving the difference into
2339  * the x/y offsets.
2340  */
2341 static u32 intel_adjust_tile_offset(int *x, int *y,
2342                                     const struct intel_plane_state *state, int plane,
2343                                     u32 old_offset, u32 new_offset)
2344 {
2345         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2346         const struct drm_framebuffer *fb = state->base.fb;
2347         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2348         unsigned int rotation = state->base.rotation;
2349         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2350
2351         WARN_ON(new_offset > old_offset);
2352
2353         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2354                 unsigned int tile_size, tile_width, tile_height;
2355                 unsigned int pitch_tiles;
2356
2357                 tile_size = intel_tile_size(dev_priv);
2358                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2359                                 fb->modifier, cpp);
2360
2361                 if (drm_rotation_90_or_270(rotation)) {
2362                         pitch_tiles = pitch / tile_height;
2363                         swap(tile_width, tile_height);
2364                 } else {
2365                         pitch_tiles = pitch / (tile_width * cpp);
2366                 }
2367
2368                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2369                                           tile_size, pitch_tiles,
2370                                           old_offset, new_offset);
2371         } else {
2372                 old_offset += *y * pitch + *x * cpp;
2373
2374                 *y = (old_offset - new_offset) / pitch;
2375                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2376         }
2377
2378         return new_offset;
2379 }
2380
2381 /*
2382  * Computes the linear offset to the base tile and adjusts
2383  * x, y. bytes per pixel is assumed to be a power-of-two.
2384  *
2385  * In the 90/270 rotated case, x and y are assumed
2386  * to be already rotated to match the rotated GTT view, and
2387  * pitch is the tile_height aligned framebuffer height.
2388  *
2389  * This function is used when computing the derived information
2390  * under intel_framebuffer, so using any of that information
2391  * here is not allowed. Anything under drm_framebuffer can be
2392  * used. This is why the user has to pass in the pitch since it
2393  * is specified in the rotated orientation.
2394  */
2395 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2396                                       int *x, int *y,
2397                                       const struct drm_framebuffer *fb, int plane,
2398                                       unsigned int pitch,
2399                                       unsigned int rotation,
2400                                       u32 alignment)
2401 {
2402         uint64_t fb_modifier = fb->modifier;
2403         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2404         u32 offset, offset_aligned;
2405
2406         if (alignment)
2407                 alignment--;
2408
2409         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2410                 unsigned int tile_size, tile_width, tile_height;
2411                 unsigned int tile_rows, tiles, pitch_tiles;
2412
2413                 tile_size = intel_tile_size(dev_priv);
2414                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2415                                 fb_modifier, cpp);
2416
2417                 if (drm_rotation_90_or_270(rotation)) {
2418                         pitch_tiles = pitch / tile_height;
2419                         swap(tile_width, tile_height);
2420                 } else {
2421                         pitch_tiles = pitch / (tile_width * cpp);
2422                 }
2423
2424                 tile_rows = *y / tile_height;
2425                 *y %= tile_height;
2426
2427                 tiles = *x / tile_width;
2428                 *x %= tile_width;
2429
2430                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2431                 offset_aligned = offset & ~alignment;
2432
2433                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2434                                           tile_size, pitch_tiles,
2435                                           offset, offset_aligned);
2436         } else {
2437                 offset = *y * pitch + *x * cpp;
2438                 offset_aligned = offset & ~alignment;
2439
2440                 *y = (offset & alignment) / pitch;
2441                 *x = ((offset & alignment) - *y * pitch) / cpp;
2442         }
2443
2444         return offset_aligned;
2445 }
2446
2447 u32 intel_compute_tile_offset(int *x, int *y,
2448                               const struct intel_plane_state *state,
2449                               int plane)
2450 {
2451         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2452         const struct drm_framebuffer *fb = state->base.fb;
2453         unsigned int rotation = state->base.rotation;
2454         int pitch = intel_fb_pitch(fb, plane, rotation);
2455         u32 alignment;
2456
2457         /* AUX_DIST needs only 4K alignment */
2458         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2459                 alignment = 4096;
2460         else
2461                 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2462
2463         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2464                                           rotation, alignment);
2465 }
2466
2467 /* Convert the fb->offset[] linear offset into x/y offsets */
2468 static void intel_fb_offset_to_xy(int *x, int *y,
2469                                   const struct drm_framebuffer *fb, int plane)
2470 {
2471         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2472         unsigned int pitch = fb->pitches[plane];
2473         u32 linear_offset = fb->offsets[plane];
2474
2475         *y = linear_offset / pitch;
2476         *x = linear_offset % pitch / cpp;
2477 }
2478
2479 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2480 {
2481         switch (fb_modifier) {
2482         case I915_FORMAT_MOD_X_TILED:
2483                 return I915_TILING_X;
2484         case I915_FORMAT_MOD_Y_TILED:
2485                 return I915_TILING_Y;
2486         default:
2487                 return I915_TILING_NONE;
2488         }
2489 }
2490
2491 static int
2492 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2493                    struct drm_framebuffer *fb)
2494 {
2495         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2496         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2497         u32 gtt_offset_rotated = 0;
2498         unsigned int max_size = 0;
2499         uint32_t format = fb->pixel_format;
2500         int i, num_planes = drm_format_num_planes(format);
2501         unsigned int tile_size = intel_tile_size(dev_priv);
2502
2503         for (i = 0; i < num_planes; i++) {
2504                 unsigned int width, height;
2505                 unsigned int cpp, size;
2506                 u32 offset;
2507                 int x, y;
2508
2509                 cpp = drm_format_plane_cpp(format, i);
2510                 width = drm_format_plane_width(fb->width, format, i);
2511                 height = drm_format_plane_height(fb->height, format, i);
2512
2513                 intel_fb_offset_to_xy(&x, &y, fb, i);
2514
2515                 /*
2516                  * The fence (if used) is aligned to the start of the object
2517                  * so having the framebuffer wrap around across the edge of the
2518                  * fenced region doesn't really work. We have no API to configure
2519                  * the fence start offset within the object (nor could we probably
2520                  * on gen2/3). So it's just easier if we just require that the
2521                  * fb layout agrees with the fence layout. We already check that the
2522                  * fb stride matches the fence stride elsewhere.
2523                  */
2524                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2525                     (x + width) * cpp > fb->pitches[i]) {
2526                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2527                                   i, fb->offsets[i]);
2528                         return -EINVAL;
2529                 }
2530
2531                 /*
2532                  * First pixel of the framebuffer from
2533                  * the start of the normal gtt mapping.
2534                  */
2535                 intel_fb->normal[i].x = x;
2536                 intel_fb->normal[i].y = y;
2537
2538                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2539                                                     fb, 0, fb->pitches[i],
2540                                                     DRM_ROTATE_0, tile_size);
2541                 offset /= tile_size;
2542
2543                 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2544                         unsigned int tile_width, tile_height;
2545                         unsigned int pitch_tiles;
2546                         struct drm_rect r;
2547
2548                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2549                                         fb->modifier, cpp);
2550
2551                         rot_info->plane[i].offset = offset;
2552                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2553                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2554                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2555
2556                         intel_fb->rotated[i].pitch =
2557                                 rot_info->plane[i].height * tile_height;
2558
2559                         /* how many tiles does this plane need */
2560                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2561                         /*
2562                          * If the plane isn't horizontally tile aligned,
2563                          * we need one more tile.
2564                          */
2565                         if (x != 0)
2566                                 size++;
2567
2568                         /* rotate the x/y offsets to match the GTT view */
2569                         r.x1 = x;
2570                         r.y1 = y;
2571                         r.x2 = x + width;
2572                         r.y2 = y + height;
2573                         drm_rect_rotate(&r,
2574                                         rot_info->plane[i].width * tile_width,
2575                                         rot_info->plane[i].height * tile_height,
2576                                         DRM_ROTATE_270);
2577                         x = r.x1;
2578                         y = r.y1;
2579
2580                         /* rotate the tile dimensions to match the GTT view */
2581                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2582                         swap(tile_width, tile_height);
2583
2584                         /*
2585                          * We only keep the x/y offsets, so push all of the
2586                          * gtt offset into the x/y offsets.
2587                          */
2588                         _intel_adjust_tile_offset(&x, &y, tile_size,
2589                                                   tile_width, tile_height, pitch_tiles,
2590                                                   gtt_offset_rotated * tile_size, 0);
2591
2592                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2593
2594                         /*
2595                          * First pixel of the framebuffer from
2596                          * the start of the rotated gtt mapping.
2597                          */
2598                         intel_fb->rotated[i].x = x;
2599                         intel_fb->rotated[i].y = y;
2600                 } else {
2601                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2602                                             x * cpp, tile_size);
2603                 }
2604
2605                 /* how many tiles in total needed in the bo */
2606                 max_size = max(max_size, offset + size);
2607         }
2608
2609         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2610                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2611                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2612                 return -EINVAL;
2613         }
2614
2615         return 0;
2616 }
2617
2618 static int i9xx_format_to_fourcc(int format)
2619 {
2620         switch (format) {
2621         case DISPPLANE_8BPP:
2622                 return DRM_FORMAT_C8;
2623         case DISPPLANE_BGRX555:
2624                 return DRM_FORMAT_XRGB1555;
2625         case DISPPLANE_BGRX565:
2626                 return DRM_FORMAT_RGB565;
2627         default:
2628         case DISPPLANE_BGRX888:
2629                 return DRM_FORMAT_XRGB8888;
2630         case DISPPLANE_RGBX888:
2631                 return DRM_FORMAT_XBGR8888;
2632         case DISPPLANE_BGRX101010:
2633                 return DRM_FORMAT_XRGB2101010;
2634         case DISPPLANE_RGBX101010:
2635                 return DRM_FORMAT_XBGR2101010;
2636         }
2637 }
2638
2639 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2640 {
2641         switch (format) {
2642         case PLANE_CTL_FORMAT_RGB_565:
2643                 return DRM_FORMAT_RGB565;
2644         default:
2645         case PLANE_CTL_FORMAT_XRGB_8888:
2646                 if (rgb_order) {
2647                         if (alpha)
2648                                 return DRM_FORMAT_ABGR8888;
2649                         else
2650                                 return DRM_FORMAT_XBGR8888;
2651                 } else {
2652                         if (alpha)
2653                                 return DRM_FORMAT_ARGB8888;
2654                         else
2655                                 return DRM_FORMAT_XRGB8888;
2656                 }
2657         case PLANE_CTL_FORMAT_XRGB_2101010:
2658                 if (rgb_order)
2659                         return DRM_FORMAT_XBGR2101010;
2660                 else
2661                         return DRM_FORMAT_XRGB2101010;
2662         }
2663 }
2664
2665 static bool
2666 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2667                               struct intel_initial_plane_config *plane_config)
2668 {
2669         struct drm_device *dev = crtc->base.dev;
2670         struct drm_i915_private *dev_priv = to_i915(dev);
2671         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2672         struct drm_i915_gem_object *obj = NULL;
2673         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2674         struct drm_framebuffer *fb = &plane_config->fb->base;
2675         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2676         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2677                                     PAGE_SIZE);
2678
2679         size_aligned -= base_aligned;
2680
2681         if (plane_config->size == 0)
2682                 return false;
2683
2684         /* If the FB is too big, just don't use it since fbdev is not very
2685          * important and we should probably use that space with FBC or other
2686          * features. */
2687         if (size_aligned * 2 > ggtt->stolen_usable_size)
2688                 return false;
2689
2690         mutex_lock(&dev->struct_mutex);
2691
2692         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2693                                                              base_aligned,
2694                                                              base_aligned,
2695                                                              size_aligned);
2696         if (!obj) {
2697                 mutex_unlock(&dev->struct_mutex);
2698                 return false;
2699         }
2700
2701         if (plane_config->tiling == I915_TILING_X)
2702                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2703
2704         mode_cmd.pixel_format = fb->pixel_format;
2705         mode_cmd.width = fb->width;
2706         mode_cmd.height = fb->height;
2707         mode_cmd.pitches[0] = fb->pitches[0];
2708         mode_cmd.modifier[0] = fb->modifier;
2709         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2710
2711         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2712                                    &mode_cmd, obj)) {
2713                 DRM_DEBUG_KMS("intel fb init failed\n");
2714                 goto out_unref_obj;
2715         }
2716
2717         mutex_unlock(&dev->struct_mutex);
2718
2719         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2720         return true;
2721
2722 out_unref_obj:
2723         i915_gem_object_put(obj);
2724         mutex_unlock(&dev->struct_mutex);
2725         return false;
2726 }
2727
2728 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2729 static void
2730 update_state_fb(struct drm_plane *plane)
2731 {
2732         if (plane->fb == plane->state->fb)
2733                 return;
2734
2735         if (plane->state->fb)
2736                 drm_framebuffer_unreference(plane->state->fb);
2737         plane->state->fb = plane->fb;
2738         if (plane->state->fb)
2739                 drm_framebuffer_reference(plane->state->fb);
2740 }
2741
2742 static void
2743 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2744                              struct intel_initial_plane_config *plane_config)
2745 {
2746         struct drm_device *dev = intel_crtc->base.dev;
2747         struct drm_i915_private *dev_priv = to_i915(dev);
2748         struct drm_crtc *c;
2749         struct intel_crtc *i;
2750         struct drm_i915_gem_object *obj;
2751         struct drm_plane *primary = intel_crtc->base.primary;
2752         struct drm_plane_state *plane_state = primary->state;
2753         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2754         struct intel_plane *intel_plane = to_intel_plane(primary);
2755         struct intel_plane_state *intel_state =
2756                 to_intel_plane_state(plane_state);
2757         struct drm_framebuffer *fb;
2758
2759         if (!plane_config->fb)
2760                 return;
2761
2762         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2763                 fb = &plane_config->fb->base;
2764                 goto valid_fb;
2765         }
2766
2767         kfree(plane_config->fb);
2768
2769         /*
2770          * Failed to alloc the obj, check to see if we should share
2771          * an fb with another CRTC instead
2772          */
2773         for_each_crtc(dev, c) {
2774                 i = to_intel_crtc(c);
2775
2776                 if (c == &intel_crtc->base)
2777                         continue;
2778
2779                 if (!i->active)
2780                         continue;
2781
2782                 fb = c->primary->fb;
2783                 if (!fb)
2784                         continue;
2785
2786                 obj = intel_fb_obj(fb);
2787                 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2788                         drm_framebuffer_reference(fb);
2789                         goto valid_fb;
2790                 }
2791         }
2792
2793         /*
2794          * We've failed to reconstruct the BIOS FB.  Current display state
2795          * indicates that the primary plane is visible, but has a NULL FB,
2796          * which will lead to problems later if we don't fix it up.  The
2797          * simplest solution is to just disable the primary plane now and
2798          * pretend the BIOS never had it enabled.
2799          */
2800         to_intel_plane_state(plane_state)->base.visible = false;
2801         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2802         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2803         intel_plane->disable_plane(primary, &intel_crtc->base);
2804
2805         return;
2806
2807 valid_fb:
2808         plane_state->src_x = 0;
2809         plane_state->src_y = 0;
2810         plane_state->src_w = fb->width << 16;
2811         plane_state->src_h = fb->height << 16;
2812
2813         plane_state->crtc_x = 0;
2814         plane_state->crtc_y = 0;
2815         plane_state->crtc_w = fb->width;
2816         plane_state->crtc_h = fb->height;
2817
2818         intel_state->base.src = drm_plane_state_src(plane_state);
2819         intel_state->base.dst = drm_plane_state_dest(plane_state);
2820
2821         obj = intel_fb_obj(fb);
2822         if (i915_gem_object_is_tiled(obj))
2823                 dev_priv->preserve_bios_swizzle = true;
2824
2825         drm_framebuffer_reference(fb);
2826         primary->fb = primary->state->fb = fb;
2827         primary->crtc = primary->state->crtc = &intel_crtc->base;
2828         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2829         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2830                   &obj->frontbuffer_bits);
2831 }
2832
2833 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2834                                unsigned int rotation)
2835 {
2836         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2837
2838         switch (fb->modifier) {
2839         case DRM_FORMAT_MOD_NONE:
2840         case I915_FORMAT_MOD_X_TILED:
2841                 switch (cpp) {
2842                 case 8:
2843                         return 4096;
2844                 case 4:
2845                 case 2:
2846                 case 1:
2847                         return 8192;
2848                 default:
2849                         MISSING_CASE(cpp);
2850                         break;
2851                 }
2852                 break;
2853         case I915_FORMAT_MOD_Y_TILED:
2854         case I915_FORMAT_MOD_Yf_TILED:
2855                 switch (cpp) {
2856                 case 8:
2857                         return 2048;
2858                 case 4:
2859                         return 4096;
2860                 case 2:
2861                 case 1:
2862                         return 8192;
2863                 default:
2864                         MISSING_CASE(cpp);
2865                         break;
2866                 }
2867                 break;
2868         default:
2869                 MISSING_CASE(fb->modifier);
2870         }
2871
2872         return 2048;
2873 }
2874
2875 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2876 {
2877         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2878         const struct drm_framebuffer *fb = plane_state->base.fb;
2879         unsigned int rotation = plane_state->base.rotation;
2880         int x = plane_state->base.src.x1 >> 16;
2881         int y = plane_state->base.src.y1 >> 16;
2882         int w = drm_rect_width(&plane_state->base.src) >> 16;
2883         int h = drm_rect_height(&plane_state->base.src) >> 16;
2884         int max_width = skl_max_plane_width(fb, 0, rotation);
2885         int max_height = 4096;
2886         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2887
2888         if (w > max_width || h > max_height) {
2889                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2890                               w, h, max_width, max_height);
2891                 return -EINVAL;
2892         }
2893
2894         intel_add_fb_offsets(&x, &y, plane_state, 0);
2895         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2896
2897         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2898
2899         /*
2900          * AUX surface offset is specified as the distance from the
2901          * main surface offset, and it must be non-negative. Make
2902          * sure that is what we will get.
2903          */
2904         if (offset > aux_offset)
2905                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2906                                                   offset, aux_offset & ~(alignment - 1));
2907
2908         /*
2909          * When using an X-tiled surface, the plane blows up
2910          * if the x offset + width exceed the stride.
2911          *
2912          * TODO: linear and Y-tiled seem fine, Yf untested,
2913          */
2914         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2915                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2916
2917                 while ((x + w) * cpp > fb->pitches[0]) {
2918                         if (offset == 0) {
2919                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2920                                 return -EINVAL;
2921                         }
2922
2923                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2924                                                           offset, offset - alignment);
2925                 }
2926         }
2927
2928         plane_state->main.offset = offset;
2929         plane_state->main.x = x;
2930         plane_state->main.y = y;
2931
2932         return 0;
2933 }
2934
2935 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2936 {
2937         const struct drm_framebuffer *fb = plane_state->base.fb;
2938         unsigned int rotation = plane_state->base.rotation;
2939         int max_width = skl_max_plane_width(fb, 1, rotation);
2940         int max_height = 4096;
2941         int x = plane_state->base.src.x1 >> 17;
2942         int y = plane_state->base.src.y1 >> 17;
2943         int w = drm_rect_width(&plane_state->base.src) >> 17;
2944         int h = drm_rect_height(&plane_state->base.src) >> 17;
2945         u32 offset;
2946
2947         intel_add_fb_offsets(&x, &y, plane_state, 1);
2948         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2949
2950         /* FIXME not quite sure how/if these apply to the chroma plane */
2951         if (w > max_width || h > max_height) {
2952                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2953                               w, h, max_width, max_height);
2954                 return -EINVAL;
2955         }
2956
2957         plane_state->aux.offset = offset;
2958         plane_state->aux.x = x;
2959         plane_state->aux.y = y;
2960
2961         return 0;
2962 }
2963
2964 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2965 {
2966         const struct drm_framebuffer *fb = plane_state->base.fb;
2967         unsigned int rotation = plane_state->base.rotation;
2968         int ret;
2969
2970         /* Rotate src coordinates to match rotated GTT view */
2971         if (drm_rotation_90_or_270(rotation))
2972                 drm_rect_rotate(&plane_state->base.src,
2973                                 fb->width << 16, fb->height << 16,
2974                                 DRM_ROTATE_270);
2975
2976         /*
2977          * Handle the AUX surface first since
2978          * the main surface setup depends on it.
2979          */
2980         if (fb->pixel_format == DRM_FORMAT_NV12) {
2981                 ret = skl_check_nv12_aux_surface(plane_state);
2982                 if (ret)
2983                         return ret;
2984         } else {
2985                 plane_state->aux.offset = ~0xfff;
2986                 plane_state->aux.x = 0;
2987                 plane_state->aux.y = 0;
2988         }
2989
2990         ret = skl_check_main_surface(plane_state);
2991         if (ret)
2992                 return ret;
2993
2994         return 0;
2995 }
2996
2997 static void i9xx_update_primary_plane(struct drm_plane *primary,
2998                                       const struct intel_crtc_state *crtc_state,
2999                                       const struct intel_plane_state *plane_state)
3000 {
3001         struct drm_i915_private *dev_priv = to_i915(primary->dev);
3002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3003         struct drm_framebuffer *fb = plane_state->base.fb;
3004         int plane = intel_crtc->plane;
3005         u32 linear_offset;
3006         u32 dspcntr;
3007         i915_reg_t reg = DSPCNTR(plane);
3008         unsigned int rotation = plane_state->base.rotation;
3009         int x = plane_state->base.src.x1 >> 16;
3010         int y = plane_state->base.src.y1 >> 16;
3011
3012         dspcntr = DISPPLANE_GAMMA_ENABLE;
3013
3014         dspcntr |= DISPLAY_PLANE_ENABLE;
3015
3016         if (INTEL_GEN(dev_priv) < 4) {
3017                 if (intel_crtc->pipe == PIPE_B)
3018                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3019
3020                 /* pipesrc and dspsize control the size that is scaled from,
3021                  * which should always be the user's requested size.
3022                  */
3023                 I915_WRITE(DSPSIZE(plane),
3024                            ((crtc_state->pipe_src_h - 1) << 16) |
3025                            (crtc_state->pipe_src_w - 1));
3026                 I915_WRITE(DSPPOS(plane), 0);
3027         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3028                 I915_WRITE(PRIMSIZE(plane),
3029                            ((crtc_state->pipe_src_h - 1) << 16) |
3030                            (crtc_state->pipe_src_w - 1));
3031                 I915_WRITE(PRIMPOS(plane), 0);
3032                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3033         }
3034
3035         switch (fb->pixel_format) {
3036         case DRM_FORMAT_C8:
3037                 dspcntr |= DISPPLANE_8BPP;
3038                 break;
3039         case DRM_FORMAT_XRGB1555:
3040                 dspcntr |= DISPPLANE_BGRX555;
3041                 break;
3042         case DRM_FORMAT_RGB565:
3043                 dspcntr |= DISPPLANE_BGRX565;
3044                 break;
3045         case DRM_FORMAT_XRGB8888:
3046                 dspcntr |= DISPPLANE_BGRX888;
3047                 break;
3048         case DRM_FORMAT_XBGR8888:
3049                 dspcntr |= DISPPLANE_RGBX888;
3050                 break;
3051         case DRM_FORMAT_XRGB2101010:
3052                 dspcntr |= DISPPLANE_BGRX101010;
3053                 break;
3054         case DRM_FORMAT_XBGR2101010:
3055                 dspcntr |= DISPPLANE_RGBX101010;
3056                 break;
3057         default:
3058                 BUG();
3059         }
3060
3061         if (INTEL_GEN(dev_priv) >= 4 &&
3062             fb->modifier == I915_FORMAT_MOD_X_TILED)
3063                 dspcntr |= DISPPLANE_TILED;
3064
3065         if (rotation & DRM_ROTATE_180)
3066                 dspcntr |= DISPPLANE_ROTATE_180;
3067
3068         if (rotation & DRM_REFLECT_X)
3069                 dspcntr |= DISPPLANE_MIRROR;
3070
3071         if (IS_G4X(dev_priv))
3072                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3073
3074         intel_add_fb_offsets(&x, &y, plane_state, 0);
3075
3076         if (INTEL_GEN(dev_priv) >= 4)
3077                 intel_crtc->dspaddr_offset =
3078                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3079
3080         if (rotation & DRM_ROTATE_180) {
3081                 x += crtc_state->pipe_src_w - 1;
3082                 y += crtc_state->pipe_src_h - 1;
3083         } else if (rotation & DRM_REFLECT_X) {
3084                 x += crtc_state->pipe_src_w - 1;
3085         }
3086
3087         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3088
3089         if (INTEL_GEN(dev_priv) < 4)
3090                 intel_crtc->dspaddr_offset = linear_offset;
3091
3092         intel_crtc->adjusted_x = x;
3093         intel_crtc->adjusted_y = y;
3094
3095         I915_WRITE(reg, dspcntr);
3096
3097         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3098         if (INTEL_GEN(dev_priv) >= 4) {
3099                 I915_WRITE(DSPSURF(plane),
3100                            intel_fb_gtt_offset(fb, rotation) +
3101                            intel_crtc->dspaddr_offset);
3102                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3103                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3104         } else {
3105                 I915_WRITE(DSPADDR(plane),
3106                            intel_fb_gtt_offset(fb, rotation) +
3107                            intel_crtc->dspaddr_offset);
3108         }
3109         POSTING_READ(reg);
3110 }
3111
3112 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3113                                        struct drm_crtc *crtc)
3114 {
3115         struct drm_device *dev = crtc->dev;
3116         struct drm_i915_private *dev_priv = to_i915(dev);
3117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3118         int plane = intel_crtc->plane;
3119
3120         I915_WRITE(DSPCNTR(plane), 0);
3121         if (INTEL_INFO(dev_priv)->gen >= 4)
3122                 I915_WRITE(DSPSURF(plane), 0);
3123         else
3124                 I915_WRITE(DSPADDR(plane), 0);
3125         POSTING_READ(DSPCNTR(plane));
3126 }
3127
3128 static void ironlake_update_primary_plane(struct drm_plane *primary,
3129                                           const struct intel_crtc_state *crtc_state,
3130                                           const struct intel_plane_state *plane_state)
3131 {
3132         struct drm_device *dev = primary->dev;
3133         struct drm_i915_private *dev_priv = to_i915(dev);
3134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3135         struct drm_framebuffer *fb = plane_state->base.fb;
3136         int plane = intel_crtc->plane;
3137         u32 linear_offset;
3138         u32 dspcntr;
3139         i915_reg_t reg = DSPCNTR(plane);
3140         unsigned int rotation = plane_state->base.rotation;
3141         int x = plane_state->base.src.x1 >> 16;
3142         int y = plane_state->base.src.y1 >> 16;
3143
3144         dspcntr = DISPPLANE_GAMMA_ENABLE;
3145         dspcntr |= DISPLAY_PLANE_ENABLE;
3146
3147         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3148                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3149
3150         switch (fb->pixel_format) {
3151         case DRM_FORMAT_C8:
3152                 dspcntr |= DISPPLANE_8BPP;
3153                 break;
3154         case DRM_FORMAT_RGB565:
3155                 dspcntr |= DISPPLANE_BGRX565;
3156                 break;
3157         case DRM_FORMAT_XRGB8888:
3158                 dspcntr |= DISPPLANE_BGRX888;
3159                 break;
3160         case DRM_FORMAT_XBGR8888:
3161                 dspcntr |= DISPPLANE_RGBX888;
3162                 break;
3163         case DRM_FORMAT_XRGB2101010:
3164                 dspcntr |= DISPPLANE_BGRX101010;
3165                 break;
3166         case DRM_FORMAT_XBGR2101010:
3167                 dspcntr |= DISPPLANE_RGBX101010;
3168                 break;
3169         default:
3170                 BUG();
3171         }
3172
3173         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3174                 dspcntr |= DISPPLANE_TILED;
3175
3176         if (rotation & DRM_ROTATE_180)
3177                 dspcntr |= DISPPLANE_ROTATE_180;
3178
3179         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3180                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3181
3182         intel_add_fb_offsets(&x, &y, plane_state, 0);
3183
3184         intel_crtc->dspaddr_offset =
3185                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3186
3187         /* HSW+ does this automagically in hardware */
3188         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3189             rotation & DRM_ROTATE_180) {
3190                 x += crtc_state->pipe_src_w - 1;
3191                 y += crtc_state->pipe_src_h - 1;
3192         }
3193
3194         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3195
3196         intel_crtc->adjusted_x = x;
3197         intel_crtc->adjusted_y = y;
3198
3199         I915_WRITE(reg, dspcntr);
3200
3201         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3202         I915_WRITE(DSPSURF(plane),
3203                    intel_fb_gtt_offset(fb, rotation) +
3204                    intel_crtc->dspaddr_offset);
3205         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3206                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3207         } else {
3208                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3209                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3210         }
3211         POSTING_READ(reg);
3212 }
3213
3214 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3215                               uint64_t fb_modifier, uint32_t pixel_format)
3216 {
3217         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3218                 return 64;
3219         } else {
3220                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3221
3222                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3223         }
3224 }
3225
3226 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3227                         unsigned int rotation)
3228 {
3229         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3230         struct i915_ggtt_view view;
3231         struct i915_vma *vma;
3232
3233         intel_fill_fb_ggtt_view(&view, fb, rotation);
3234
3235         vma = i915_gem_object_to_ggtt(obj, &view);
3236         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3237                  view.type))
3238                 return -1;
3239
3240         return i915_ggtt_offset(vma);
3241 }
3242
3243 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3244 {
3245         struct drm_device *dev = intel_crtc->base.dev;
3246         struct drm_i915_private *dev_priv = to_i915(dev);
3247
3248         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3249         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3250         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3251 }
3252
3253 /*
3254  * This function detaches (aka. unbinds) unused scalers in hardware
3255  */
3256 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3257 {
3258         struct intel_crtc_scaler_state *scaler_state;
3259         int i;
3260
3261         scaler_state = &intel_crtc->config->scaler_state;
3262
3263         /* loop through and disable scalers that aren't in use */
3264         for (i = 0; i < intel_crtc->num_scalers; i++) {
3265                 if (!scaler_state->scalers[i].in_use)
3266                         skl_detach_scaler(intel_crtc, i);
3267         }
3268 }
3269
3270 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3271                      unsigned int rotation)
3272 {
3273         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3274         u32 stride = intel_fb_pitch(fb, plane, rotation);
3275
3276         /*
3277          * The stride is either expressed as a multiple of 64 bytes chunks for
3278          * linear buffers or in number of tiles for tiled buffers.
3279          */
3280         if (drm_rotation_90_or_270(rotation)) {
3281                 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3282
3283                 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
3284         } else {
3285                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
3286                                                     fb->pixel_format);
3287         }
3288
3289         return stride;
3290 }
3291
3292 u32 skl_plane_ctl_format(uint32_t pixel_format)
3293 {
3294         switch (pixel_format) {
3295         case DRM_FORMAT_C8:
3296                 return PLANE_CTL_FORMAT_INDEXED;
3297         case DRM_FORMAT_RGB565:
3298                 return PLANE_CTL_FORMAT_RGB_565;
3299         case DRM_FORMAT_XBGR8888:
3300                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3301         case DRM_FORMAT_XRGB8888:
3302                 return PLANE_CTL_FORMAT_XRGB_8888;
3303         /*
3304          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3305          * to be already pre-multiplied. We need to add a knob (or a different
3306          * DRM_FORMAT) for user-space to configure that.
3307          */
3308         case DRM_FORMAT_ABGR8888:
3309                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3310                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3311         case DRM_FORMAT_ARGB8888:
3312                 return PLANE_CTL_FORMAT_XRGB_8888 |
3313                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3314         case DRM_FORMAT_XRGB2101010:
3315                 return PLANE_CTL_FORMAT_XRGB_2101010;
3316         case DRM_FORMAT_XBGR2101010:
3317                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3318         case DRM_FORMAT_YUYV:
3319                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3320         case DRM_FORMAT_YVYU:
3321                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3322         case DRM_FORMAT_UYVY:
3323                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3324         case DRM_FORMAT_VYUY:
3325                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3326         default:
3327                 MISSING_CASE(pixel_format);
3328         }
3329
3330         return 0;
3331 }
3332
3333 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3334 {
3335         switch (fb_modifier) {
3336         case DRM_FORMAT_MOD_NONE:
3337                 break;
3338         case I915_FORMAT_MOD_X_TILED:
3339                 return PLANE_CTL_TILED_X;
3340         case I915_FORMAT_MOD_Y_TILED:
3341                 return PLANE_CTL_TILED_Y;
3342         case I915_FORMAT_MOD_Yf_TILED:
3343                 return PLANE_CTL_TILED_YF;
3344         default:
3345                 MISSING_CASE(fb_modifier);
3346         }
3347
3348         return 0;
3349 }
3350
3351 u32 skl_plane_ctl_rotation(unsigned int rotation)
3352 {
3353         switch (rotation) {
3354         case DRM_ROTATE_0:
3355                 break;
3356         /*
3357          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3358          * while i915 HW rotation is clockwise, thats why this swapping.
3359          */
3360         case DRM_ROTATE_90:
3361                 return PLANE_CTL_ROTATE_270;
3362         case DRM_ROTATE_180:
3363                 return PLANE_CTL_ROTATE_180;
3364         case DRM_ROTATE_270:
3365                 return PLANE_CTL_ROTATE_90;
3366         default:
3367                 MISSING_CASE(rotation);
3368         }
3369
3370         return 0;
3371 }
3372
3373 static void skylake_update_primary_plane(struct drm_plane *plane,
3374                                          const struct intel_crtc_state *crtc_state,
3375                                          const struct intel_plane_state *plane_state)
3376 {
3377         struct drm_device *dev = plane->dev;
3378         struct drm_i915_private *dev_priv = to_i915(dev);
3379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3380         struct drm_framebuffer *fb = plane_state->base.fb;
3381         int pipe = intel_crtc->pipe;
3382         u32 plane_ctl;
3383         unsigned int rotation = plane_state->base.rotation;
3384         u32 stride = skl_plane_stride(fb, 0, rotation);
3385         u32 surf_addr = plane_state->main.offset;
3386         int scaler_id = plane_state->scaler_id;
3387         int src_x = plane_state->main.x;
3388         int src_y = plane_state->main.y;
3389         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3390         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3391         int dst_x = plane_state->base.dst.x1;
3392         int dst_y = plane_state->base.dst.y1;
3393         int dst_w = drm_rect_width(&plane_state->base.dst);
3394         int dst_h = drm_rect_height(&plane_state->base.dst);
3395
3396         plane_ctl = PLANE_CTL_ENABLE |
3397                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3398                     PLANE_CTL_PIPE_CSC_ENABLE;
3399
3400         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3401         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3402         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3403         plane_ctl |= skl_plane_ctl_rotation(rotation);
3404
3405         /* Sizes are 0 based */
3406         src_w--;
3407         src_h--;
3408         dst_w--;
3409         dst_h--;
3410
3411         intel_crtc->dspaddr_offset = surf_addr;
3412
3413         intel_crtc->adjusted_x = src_x;
3414         intel_crtc->adjusted_y = src_y;
3415
3416         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3417         I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3418         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3419         I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3420
3421         if (scaler_id >= 0) {
3422                 uint32_t ps_ctrl = 0;
3423
3424                 WARN_ON(!dst_w || !dst_h);
3425                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3426                         crtc_state->scaler_state.scalers[scaler_id].mode;
3427                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3428                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3429                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3430                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3431                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3432         } else {
3433                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3434         }
3435
3436         I915_WRITE(PLANE_SURF(pipe, 0),
3437                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
3438
3439         POSTING_READ(PLANE_SURF(pipe, 0));
3440 }
3441
3442 static void skylake_disable_primary_plane(struct drm_plane *primary,
3443                                           struct drm_crtc *crtc)
3444 {
3445         struct drm_device *dev = crtc->dev;
3446         struct drm_i915_private *dev_priv = to_i915(dev);
3447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3448         int pipe = intel_crtc->pipe;
3449
3450         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3451         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3452         POSTING_READ(PLANE_SURF(pipe, 0));
3453 }
3454
3455 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3456 static int
3457 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3458                            int x, int y, enum mode_set_atomic state)
3459 {
3460         /* Support for kgdboc is disabled, this needs a major rework. */
3461         DRM_ERROR("legacy panic handler not supported any more.\n");
3462
3463         return -ENODEV;
3464 }
3465
3466 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3467 {
3468         struct intel_crtc *crtc;
3469
3470         for_each_intel_crtc(&dev_priv->drm, crtc)
3471                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3472 }
3473
3474 static void intel_update_primary_planes(struct drm_device *dev)
3475 {
3476         struct drm_crtc *crtc;
3477
3478         for_each_crtc(dev, crtc) {
3479                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3480                 struct intel_plane_state *plane_state =
3481                         to_intel_plane_state(plane->base.state);
3482
3483                 if (plane_state->base.visible)
3484                         plane->update_plane(&plane->base,
3485                                             to_intel_crtc_state(crtc->state),
3486                                             plane_state);
3487         }
3488 }
3489
3490 static int
3491 __intel_display_resume(struct drm_device *dev,
3492                        struct drm_atomic_state *state)
3493 {
3494         struct drm_crtc_state *crtc_state;
3495         struct drm_crtc *crtc;
3496         int i, ret;
3497
3498         intel_modeset_setup_hw_state(dev);
3499         i915_redisable_vga(to_i915(dev));
3500
3501         if (!state)
3502                 return 0;
3503
3504         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3505                 /*
3506                  * Force recalculation even if we restore
3507                  * current state. With fast modeset this may not result
3508                  * in a modeset when the state is compatible.
3509                  */
3510                 crtc_state->mode_changed = true;
3511         }
3512
3513         /* ignore any reset values/BIOS leftovers in the WM registers */
3514         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3515
3516         ret = drm_atomic_commit(state);
3517
3518         WARN_ON(ret == -EDEADLK);
3519         return ret;
3520 }
3521
3522 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3523 {
3524         return intel_has_gpu_reset(dev_priv) &&
3525                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3526 }
3527
3528 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3529 {
3530         struct drm_device *dev = &dev_priv->drm;
3531         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3532         struct drm_atomic_state *state;
3533         int ret;
3534
3535         /*
3536          * Need mode_config.mutex so that we don't
3537          * trample ongoing ->detect() and whatnot.
3538          */
3539         mutex_lock(&dev->mode_config.mutex);
3540         drm_modeset_acquire_init(ctx, 0);
3541         while (1) {
3542                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3543                 if (ret != -EDEADLK)
3544                         break;
3545
3546                 drm_modeset_backoff(ctx);
3547         }
3548
3549         /* reset doesn't touch the display, but flips might get nuked anyway, */
3550         if (!i915.force_reset_modeset_test &&
3551             !gpu_reset_clobbers_display(dev_priv))
3552                 return;
3553
3554         /*
3555          * Disabling the crtcs gracefully seems nicer. Also the
3556          * g33 docs say we should at least disable all the planes.
3557          */
3558         state = drm_atomic_helper_duplicate_state(dev, ctx);
3559         if (IS_ERR(state)) {
3560                 ret = PTR_ERR(state);
3561                 state = NULL;
3562                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3563                 goto err;
3564         }
3565
3566         ret = drm_atomic_helper_disable_all(dev, ctx);
3567         if (ret) {
3568                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3569                 goto err;
3570         }
3571
3572         dev_priv->modeset_restore_state = state;
3573         state->acquire_ctx = ctx;
3574         return;
3575
3576 err:
3577         drm_atomic_state_put(state);
3578 }
3579
3580 void intel_finish_reset(struct drm_i915_private *dev_priv)
3581 {
3582         struct drm_device *dev = &dev_priv->drm;
3583         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3584         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3585         int ret;
3586
3587         /*
3588          * Flips in the rings will be nuked by the reset,
3589          * so complete all pending flips so that user space
3590          * will get its events and not get stuck.
3591          */
3592         intel_complete_page_flips(dev_priv);
3593
3594         dev_priv->modeset_restore_state = NULL;
3595
3596         /* reset doesn't touch the display */
3597         if (!gpu_reset_clobbers_display(dev_priv)) {
3598                 if (!state) {
3599                         /*
3600                          * Flips in the rings have been nuked by the reset,
3601                          * so update the base address of all primary
3602                          * planes to the the last fb to make sure we're
3603                          * showing the correct fb after a reset.
3604                          *
3605                          * FIXME: Atomic will make this obsolete since we won't schedule
3606                          * CS-based flips (which might get lost in gpu resets) any more.
3607                          */
3608                         intel_update_primary_planes(dev);
3609                 } else {
3610                         ret = __intel_display_resume(dev, state);
3611                         if (ret)
3612                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3613                 }
3614         } else {
3615                 /*
3616                  * The display has been reset as well,
3617                  * so need a full re-initialization.
3618                  */
3619                 intel_runtime_pm_disable_interrupts(dev_priv);
3620                 intel_runtime_pm_enable_interrupts(dev_priv);
3621
3622                 intel_pps_unlock_regs_wa(dev_priv);
3623                 intel_modeset_init_hw(dev);
3624
3625                 spin_lock_irq(&dev_priv->irq_lock);
3626                 if (dev_priv->display.hpd_irq_setup)
3627                         dev_priv->display.hpd_irq_setup(dev_priv);
3628                 spin_unlock_irq(&dev_priv->irq_lock);
3629
3630                 ret = __intel_display_resume(dev, state);
3631                 if (ret)
3632                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3633
3634                 intel_hpd_init(dev_priv);
3635         }
3636
3637         if (state)
3638                 drm_atomic_state_put(state);
3639         drm_modeset_drop_locks(ctx);
3640         drm_modeset_acquire_fini(ctx);
3641         mutex_unlock(&dev->mode_config.mutex);
3642 }
3643
3644 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3645 {
3646         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3647
3648         if (i915_reset_in_progress(error))
3649                 return true;
3650
3651         if (crtc->reset_count != i915_reset_count(error))
3652                 return true;
3653
3654         return false;
3655 }
3656
3657 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3658 {
3659         struct drm_device *dev = crtc->dev;
3660         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3661         bool pending;
3662
3663         if (abort_flip_on_reset(intel_crtc))
3664                 return false;
3665
3666         spin_lock_irq(&dev->event_lock);
3667         pending = to_intel_crtc(crtc)->flip_work != NULL;
3668         spin_unlock_irq(&dev->event_lock);
3669
3670         return pending;
3671 }
3672
3673 static void intel_update_pipe_config(struct intel_crtc *crtc,
3674                                      struct intel_crtc_state *old_crtc_state)
3675 {
3676         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3677         struct intel_crtc_state *pipe_config =
3678                 to_intel_crtc_state(crtc->base.state);
3679
3680         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3681         crtc->base.mode = crtc->base.state->mode;
3682
3683         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3684                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3685                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3686
3687         /*
3688          * Update pipe size and adjust fitter if needed: the reason for this is
3689          * that in compute_mode_changes we check the native mode (not the pfit
3690          * mode) to see if we can flip rather than do a full mode set. In the
3691          * fastboot case, we'll flip, but if we don't update the pipesrc and
3692          * pfit state, we'll end up with a big fb scanned out into the wrong
3693          * sized surface.
3694          */
3695
3696         I915_WRITE(PIPESRC(crtc->pipe),
3697                    ((pipe_config->pipe_src_w - 1) << 16) |
3698                    (pipe_config->pipe_src_h - 1));
3699
3700         /* on skylake this is done by detaching scalers */
3701         if (INTEL_GEN(dev_priv) >= 9) {
3702                 skl_detach_scalers(crtc);
3703
3704                 if (pipe_config->pch_pfit.enabled)
3705                         skylake_pfit_enable(crtc);
3706         } else if (HAS_PCH_SPLIT(dev_priv)) {
3707                 if (pipe_config->pch_pfit.enabled)
3708                         ironlake_pfit_enable(crtc);
3709                 else if (old_crtc_state->pch_pfit.enabled)
3710                         ironlake_pfit_disable(crtc, true);
3711         }
3712 }
3713
3714 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3715 {
3716         struct drm_device *dev = crtc->dev;
3717         struct drm_i915_private *dev_priv = to_i915(dev);
3718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3719         int pipe = intel_crtc->pipe;
3720         i915_reg_t reg;
3721         u32 temp;
3722
3723         /* enable normal train */
3724         reg = FDI_TX_CTL(pipe);
3725         temp = I915_READ(reg);
3726         if (IS_IVYBRIDGE(dev_priv)) {
3727                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3728                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3729         } else {
3730                 temp &= ~FDI_LINK_TRAIN_NONE;
3731                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3732         }
3733         I915_WRITE(reg, temp);
3734
3735         reg = FDI_RX_CTL(pipe);
3736         temp = I915_READ(reg);
3737         if (HAS_PCH_CPT(dev_priv)) {
3738                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3739                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3740         } else {
3741                 temp &= ~FDI_LINK_TRAIN_NONE;
3742                 temp |= FDI_LINK_TRAIN_NONE;
3743         }
3744         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3745
3746         /* wait one idle pattern time */
3747         POSTING_READ(reg);
3748         udelay(1000);
3749
3750         /* IVB wants error correction enabled */
3751         if (IS_IVYBRIDGE(dev_priv))
3752                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3753                            FDI_FE_ERRC_ENABLE);
3754 }
3755
3756 /* The FDI link training functions for ILK/Ibexpeak. */
3757 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3758 {
3759         struct drm_device *dev = crtc->dev;
3760         struct drm_i915_private *dev_priv = to_i915(dev);
3761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3762         int pipe = intel_crtc->pipe;
3763         i915_reg_t reg;
3764         u32 temp, tries;
3765
3766         /* FDI needs bits from pipe first */
3767         assert_pipe_enabled(dev_priv, pipe);
3768
3769         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3770            for train result */
3771         reg = FDI_RX_IMR(pipe);
3772         temp = I915_READ(reg);
3773         temp &= ~FDI_RX_SYMBOL_LOCK;
3774         temp &= ~FDI_RX_BIT_LOCK;
3775         I915_WRITE(reg, temp);
3776         I915_READ(reg);
3777         udelay(150);
3778
3779         /* enable CPU FDI TX and PCH FDI RX */
3780         reg = FDI_TX_CTL(pipe);
3781         temp = I915_READ(reg);
3782         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3783         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3784         temp &= ~FDI_LINK_TRAIN_NONE;
3785         temp |= FDI_LINK_TRAIN_PATTERN_1;
3786         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3787
3788         reg = FDI_RX_CTL(pipe);
3789         temp = I915_READ(reg);
3790         temp &= ~FDI_LINK_TRAIN_NONE;
3791         temp |= FDI_LINK_TRAIN_PATTERN_1;
3792         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3793
3794         POSTING_READ(reg);
3795         udelay(150);
3796
3797         /* Ironlake workaround, enable clock pointer after FDI enable*/
3798         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3799         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3800                    FDI_RX_PHASE_SYNC_POINTER_EN);
3801
3802         reg = FDI_RX_IIR(pipe);
3803         for (tries = 0; tries < 5; tries++) {
3804                 temp = I915_READ(reg);
3805                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3806
3807                 if ((temp & FDI_RX_BIT_LOCK)) {
3808                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3809                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3810                         break;
3811                 }
3812         }
3813         if (tries == 5)
3814                 DRM_ERROR("FDI train 1 fail!\n");
3815
3816         /* Train 2 */
3817         reg = FDI_TX_CTL(pipe);
3818         temp = I915_READ(reg);
3819         temp &= ~FDI_LINK_TRAIN_NONE;
3820         temp |= FDI_LINK_TRAIN_PATTERN_2;
3821         I915_WRITE(reg, temp);
3822
3823         reg = FDI_RX_CTL(pipe);
3824         temp = I915_READ(reg);
3825         temp &= ~FDI_LINK_TRAIN_NONE;
3826         temp |= FDI_LINK_TRAIN_PATTERN_2;
3827         I915_WRITE(reg, temp);
3828
3829         POSTING_READ(reg);
3830         udelay(150);
3831
3832         reg = FDI_RX_IIR(pipe);
3833         for (tries = 0; tries < 5; tries++) {
3834                 temp = I915_READ(reg);
3835                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3836
3837                 if (temp & FDI_RX_SYMBOL_LOCK) {
3838                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3839                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3840                         break;
3841                 }
3842         }
3843         if (tries == 5)
3844                 DRM_ERROR("FDI train 2 fail!\n");
3845
3846         DRM_DEBUG_KMS("FDI train done\n");
3847
3848 }
3849
3850 static const int snb_b_fdi_train_param[] = {
3851         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3852         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3853         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3854         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3855 };
3856
3857 /* The FDI link training functions for SNB/Cougarpoint. */
3858 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3859 {
3860         struct drm_device *dev = crtc->dev;
3861         struct drm_i915_private *dev_priv = to_i915(dev);
3862         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3863         int pipe = intel_crtc->pipe;
3864         i915_reg_t reg;
3865         u32 temp, i, retry;
3866
3867         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3868            for train result */
3869         reg = FDI_RX_IMR(pipe);
3870         temp = I915_READ(reg);
3871         temp &= ~FDI_RX_SYMBOL_LOCK;
3872         temp &= ~FDI_RX_BIT_LOCK;
3873         I915_WRITE(reg, temp);
3874
3875         POSTING_READ(reg);
3876         udelay(150);
3877
3878         /* enable CPU FDI TX and PCH FDI RX */
3879         reg = FDI_TX_CTL(pipe);
3880         temp = I915_READ(reg);
3881         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3882         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3883         temp &= ~FDI_LINK_TRAIN_NONE;
3884         temp |= FDI_LINK_TRAIN_PATTERN_1;
3885         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3886         /* SNB-B */
3887         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3888         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3889
3890         I915_WRITE(FDI_RX_MISC(pipe),
3891                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3892
3893         reg = FDI_RX_CTL(pipe);
3894         temp = I915_READ(reg);
3895         if (HAS_PCH_CPT(dev_priv)) {
3896                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3897                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3898         } else {
3899                 temp &= ~FDI_LINK_TRAIN_NONE;
3900                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3901         }
3902         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3903
3904         POSTING_READ(reg);
3905         udelay(150);
3906
3907         for (i = 0; i < 4; i++) {
3908                 reg = FDI_TX_CTL(pipe);
3909                 temp = I915_READ(reg);
3910                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3911                 temp |= snb_b_fdi_train_param[i];
3912                 I915_WRITE(reg, temp);
3913
3914                 POSTING_READ(reg);
3915                 udelay(500);
3916
3917                 for (retry = 0; retry < 5; retry++) {
3918                         reg = FDI_RX_IIR(pipe);
3919                         temp = I915_READ(reg);
3920                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3921                         if (temp & FDI_RX_BIT_LOCK) {
3922                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3923                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3924                                 break;
3925                         }
3926                         udelay(50);
3927                 }
3928                 if (retry < 5)
3929                         break;
3930         }
3931         if (i == 4)
3932                 DRM_ERROR("FDI train 1 fail!\n");
3933
3934         /* Train 2 */
3935         reg = FDI_TX_CTL(pipe);
3936         temp = I915_READ(reg);
3937         temp &= ~FDI_LINK_TRAIN_NONE;
3938         temp |= FDI_LINK_TRAIN_PATTERN_2;
3939         if (IS_GEN6(dev_priv)) {
3940                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3941                 /* SNB-B */
3942                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3943         }
3944         I915_WRITE(reg, temp);
3945
3946         reg = FDI_RX_CTL(pipe);
3947         temp = I915_READ(reg);
3948         if (HAS_PCH_CPT(dev_priv)) {
3949                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3950                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3951         } else {
3952                 temp &= ~FDI_LINK_TRAIN_NONE;
3953                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3954         }
3955         I915_WRITE(reg, temp);
3956
3957         POSTING_READ(reg);
3958         udelay(150);
3959
3960         for (i = 0; i < 4; i++) {
3961                 reg = FDI_TX_CTL(pipe);
3962                 temp = I915_READ(reg);
3963                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3964                 temp |= snb_b_fdi_train_param[i];
3965                 I915_WRITE(reg, temp);
3966
3967                 POSTING_READ(reg);
3968                 udelay(500);
3969
3970                 for (retry = 0; retry < 5; retry++) {
3971                         reg = FDI_RX_IIR(pipe);
3972                         temp = I915_READ(reg);
3973                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3974                         if (temp & FDI_RX_SYMBOL_LOCK) {
3975                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3976                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3977                                 break;
3978                         }
3979                         udelay(50);
3980                 }
3981                 if (retry < 5)
3982                         break;
3983         }
3984         if (i == 4)
3985                 DRM_ERROR("FDI train 2 fail!\n");
3986
3987         DRM_DEBUG_KMS("FDI train done.\n");
3988 }
3989
3990 /* Manual link training for Ivy Bridge A0 parts */
3991 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3992 {
3993         struct drm_device *dev = crtc->dev;
3994         struct drm_i915_private *dev_priv = to_i915(dev);
3995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3996         int pipe = intel_crtc->pipe;
3997         i915_reg_t reg;
3998         u32 temp, i, j;
3999
4000         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4001            for train result */
4002         reg = FDI_RX_IMR(pipe);
4003         temp = I915_READ(reg);
4004         temp &= ~FDI_RX_SYMBOL_LOCK;
4005         temp &= ~FDI_RX_BIT_LOCK;
4006         I915_WRITE(reg, temp);
4007
4008         POSTING_READ(reg);
4009         udelay(150);
4010
4011         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4012                       I915_READ(FDI_RX_IIR(pipe)));
4013
4014         /* Try each vswing and preemphasis setting twice before moving on */
4015         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4016                 /* disable first in case we need to retry */
4017                 reg = FDI_TX_CTL(pipe);
4018                 temp = I915_READ(reg);
4019                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4020                 temp &= ~FDI_TX_ENABLE;
4021                 I915_WRITE(reg, temp);
4022
4023                 reg = FDI_RX_CTL(pipe);
4024                 temp = I915_READ(reg);
4025                 temp &= ~FDI_LINK_TRAIN_AUTO;
4026                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4027                 temp &= ~FDI_RX_ENABLE;
4028                 I915_WRITE(reg, temp);
4029
4030                 /* enable CPU FDI TX and PCH FDI RX */
4031                 reg = FDI_TX_CTL(pipe);
4032                 temp = I915_READ(reg);
4033                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4034                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4035                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4036                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4037                 temp |= snb_b_fdi_train_param[j/2];
4038                 temp |= FDI_COMPOSITE_SYNC;
4039                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4040
4041                 I915_WRITE(FDI_RX_MISC(pipe),
4042                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4043
4044                 reg = FDI_RX_CTL(pipe);
4045                 temp = I915_READ(reg);
4046                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4047                 temp |= FDI_COMPOSITE_SYNC;
4048                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4049
4050                 POSTING_READ(reg);
4051                 udelay(1); /* should be 0.5us */
4052
4053                 for (i = 0; i < 4; i++) {
4054                         reg = FDI_RX_IIR(pipe);
4055                         temp = I915_READ(reg);
4056                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4057
4058                         if (temp & FDI_RX_BIT_LOCK ||
4059                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4060                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4061                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4062                                               i);
4063                                 break;
4064                         }
4065                         udelay(1); /* should be 0.5us */
4066                 }
4067                 if (i == 4) {
4068                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4069                         continue;
4070                 }
4071
4072                 /* Train 2 */
4073                 reg = FDI_TX_CTL(pipe);
4074                 temp = I915_READ(reg);
4075                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4076                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4077                 I915_WRITE(reg, temp);
4078
4079                 reg = FDI_RX_CTL(pipe);
4080                 temp = I915_READ(reg);
4081                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4082                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4083                 I915_WRITE(reg, temp);
4084
4085                 POSTING_READ(reg);
4086                 udelay(2); /* should be 1.5us */
4087
4088                 for (i = 0; i < 4; i++) {
4089                         reg = FDI_RX_IIR(pipe);
4090                         temp = I915_READ(reg);
4091                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4092
4093                         if (temp & FDI_RX_SYMBOL_LOCK ||
4094                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4095                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4096                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4097                                               i);
4098                                 goto train_done;
4099                         }
4100                         udelay(2); /* should be 1.5us */
4101                 }
4102                 if (i == 4)
4103                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4104         }
4105
4106 train_done:
4107         DRM_DEBUG_KMS("FDI train done.\n");
4108 }
4109
4110 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4111 {
4112         struct drm_device *dev = intel_crtc->base.dev;
4113         struct drm_i915_private *dev_priv = to_i915(dev);
4114         int pipe = intel_crtc->pipe;
4115         i915_reg_t reg;
4116         u32 temp;
4117
4118         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4119         reg = FDI_RX_CTL(pipe);
4120         temp = I915_READ(reg);
4121         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4122         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4123         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4124         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4125
4126         POSTING_READ(reg);
4127         udelay(200);
4128
4129         /* Switch from Rawclk to PCDclk */
4130         temp = I915_READ(reg);
4131         I915_WRITE(reg, temp | FDI_PCDCLK);
4132
4133         POSTING_READ(reg);
4134         udelay(200);
4135
4136         /* Enable CPU FDI TX PLL, always on for Ironlake */
4137         reg = FDI_TX_CTL(pipe);
4138         temp = I915_READ(reg);
4139         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4140                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4141
4142                 POSTING_READ(reg);
4143                 udelay(100);
4144         }
4145 }
4146
4147 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4148 {
4149         struct drm_device *dev = intel_crtc->base.dev;
4150         struct drm_i915_private *dev_priv = to_i915(dev);
4151         int pipe = intel_crtc->pipe;
4152         i915_reg_t reg;
4153         u32 temp;
4154
4155         /* Switch from PCDclk to Rawclk */
4156         reg = FDI_RX_CTL(pipe);
4157         temp = I915_READ(reg);
4158         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4159
4160         /* Disable CPU FDI TX PLL */
4161         reg = FDI_TX_CTL(pipe);
4162         temp = I915_READ(reg);
4163         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4164
4165         POSTING_READ(reg);
4166         udelay(100);
4167
4168         reg = FDI_RX_CTL(pipe);
4169         temp = I915_READ(reg);
4170         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4171
4172         /* Wait for the clocks to turn off. */
4173         POSTING_READ(reg);
4174         udelay(100);
4175 }
4176
4177 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4178 {
4179         struct drm_device *dev = crtc->dev;
4180         struct drm_i915_private *dev_priv = to_i915(dev);
4181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4182         int pipe = intel_crtc->pipe;
4183         i915_reg_t reg;
4184         u32 temp;
4185
4186         /* disable CPU FDI tx and PCH FDI rx */
4187         reg = FDI_TX_CTL(pipe);
4188         temp = I915_READ(reg);
4189         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4190         POSTING_READ(reg);
4191
4192         reg = FDI_RX_CTL(pipe);
4193         temp = I915_READ(reg);
4194         temp &= ~(0x7 << 16);
4195         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4196         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4197
4198         POSTING_READ(reg);
4199         udelay(100);
4200
4201         /* Ironlake workaround, disable clock pointer after downing FDI */
4202         if (HAS_PCH_IBX(dev_priv))
4203                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4204
4205         /* still set train pattern 1 */
4206         reg = FDI_TX_CTL(pipe);
4207         temp = I915_READ(reg);
4208         temp &= ~FDI_LINK_TRAIN_NONE;
4209         temp |= FDI_LINK_TRAIN_PATTERN_1;
4210         I915_WRITE(reg, temp);
4211
4212         reg = FDI_RX_CTL(pipe);
4213         temp = I915_READ(reg);
4214         if (HAS_PCH_CPT(dev_priv)) {
4215                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4216                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4217         } else {
4218                 temp &= ~FDI_LINK_TRAIN_NONE;
4219                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4220         }
4221         /* BPC in FDI rx is consistent with that in PIPECONF */
4222         temp &= ~(0x07 << 16);
4223         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4224         I915_WRITE(reg, temp);
4225
4226         POSTING_READ(reg);
4227         udelay(100);
4228 }
4229
4230 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4231 {
4232         struct drm_i915_private *dev_priv = to_i915(dev);
4233         struct intel_crtc *crtc;
4234
4235         /* Note that we don't need to be called with mode_config.lock here
4236          * as our list of CRTC objects is static for the lifetime of the
4237          * device and so cannot disappear as we iterate. Similarly, we can
4238          * happily treat the predicates as racy, atomic checks as userspace
4239          * cannot claim and pin a new fb without at least acquring the
4240          * struct_mutex and so serialising with us.
4241          */
4242         for_each_intel_crtc(dev, crtc) {
4243                 if (atomic_read(&crtc->unpin_work_count) == 0)
4244                         continue;
4245
4246                 if (crtc->flip_work)
4247                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4248
4249                 return true;
4250         }
4251
4252         return false;
4253 }
4254
4255 static void page_flip_completed(struct intel_crtc *intel_crtc)
4256 {
4257         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4258         struct intel_flip_work *work = intel_crtc->flip_work;
4259
4260         intel_crtc->flip_work = NULL;
4261
4262         if (work->event)
4263                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4264
4265         drm_crtc_vblank_put(&intel_crtc->base);
4266
4267         wake_up_all(&dev_priv->pending_flip_queue);
4268         queue_work(dev_priv->wq, &work->unpin_work);
4269
4270         trace_i915_flip_complete(intel_crtc->plane,
4271                                  work->pending_flip_obj);
4272 }
4273
4274 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4275 {
4276         struct drm_device *dev = crtc->dev;
4277         struct drm_i915_private *dev_priv = to_i915(dev);
4278         long ret;
4279
4280         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4281
4282         ret = wait_event_interruptible_timeout(
4283                                         dev_priv->pending_flip_queue,
4284                                         !intel_crtc_has_pending_flip(crtc),
4285                                         60*HZ);
4286
4287         if (ret < 0)
4288                 return ret;
4289
4290         if (ret == 0) {
4291                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4292                 struct intel_flip_work *work;
4293
4294                 spin_lock_irq(&dev->event_lock);
4295                 work = intel_crtc->flip_work;
4296                 if (work && !is_mmio_work(work)) {
4297                         WARN_ONCE(1, "Removing stuck page flip\n");
4298                         page_flip_completed(intel_crtc);
4299                 }
4300                 spin_unlock_irq(&dev->event_lock);
4301         }
4302
4303         return 0;
4304 }
4305
4306 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4307 {
4308         u32 temp;
4309
4310         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4311
4312         mutex_lock(&dev_priv->sb_lock);
4313
4314         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4315         temp |= SBI_SSCCTL_DISABLE;
4316         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4317
4318         mutex_unlock(&dev_priv->sb_lock);
4319 }
4320
4321 /* Program iCLKIP clock to the desired frequency */
4322 static void lpt_program_iclkip(struct drm_crtc *crtc)
4323 {
4324         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4325         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4326         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4327         u32 temp;
4328
4329         lpt_disable_iclkip(dev_priv);
4330
4331         /* The iCLK virtual clock root frequency is in MHz,
4332          * but the adjusted_mode->crtc_clock in in KHz. To get the
4333          * divisors, it is necessary to divide one by another, so we
4334          * convert the virtual clock precision to KHz here for higher
4335          * precision.
4336          */
4337         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4338                 u32 iclk_virtual_root_freq = 172800 * 1000;
4339                 u32 iclk_pi_range = 64;
4340                 u32 desired_divisor;
4341
4342                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4343                                                     clock << auxdiv);
4344                 divsel = (desired_divisor / iclk_pi_range) - 2;
4345                 phaseinc = desired_divisor % iclk_pi_range;
4346
4347                 /*
4348                  * Near 20MHz is a corner case which is
4349                  * out of range for the 7-bit divisor
4350                  */
4351                 if (divsel <= 0x7f)
4352                         break;
4353         }
4354
4355         /* This should not happen with any sane values */
4356         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4357                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4358         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4359                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4360
4361         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4362                         clock,
4363                         auxdiv,
4364                         divsel,
4365                         phasedir,
4366                         phaseinc);
4367
4368         mutex_lock(&dev_priv->sb_lock);
4369
4370         /* Program SSCDIVINTPHASE6 */
4371         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4372         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4373         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4374         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4375         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4376         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4377         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4378         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4379
4380         /* Program SSCAUXDIV */
4381         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4382         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4383         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4384         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4385
4386         /* Enable modulator and associated divider */
4387         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4388         temp &= ~SBI_SSCCTL_DISABLE;
4389         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4390
4391         mutex_unlock(&dev_priv->sb_lock);
4392
4393         /* Wait for initialization time */
4394         udelay(24);
4395
4396         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4397 }
4398
4399 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4400 {
4401         u32 divsel, phaseinc, auxdiv;
4402         u32 iclk_virtual_root_freq = 172800 * 1000;
4403         u32 iclk_pi_range = 64;
4404         u32 desired_divisor;
4405         u32 temp;
4406
4407         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4408                 return 0;
4409
4410         mutex_lock(&dev_priv->sb_lock);
4411
4412         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4413         if (temp & SBI_SSCCTL_DISABLE) {
4414                 mutex_unlock(&dev_priv->sb_lock);
4415                 return 0;
4416         }
4417
4418         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4419         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4420                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4421         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4422                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4423
4424         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4425         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4426                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4427
4428         mutex_unlock(&dev_priv->sb_lock);
4429
4430         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4431
4432         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4433                                  desired_divisor << auxdiv);
4434 }
4435
4436 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4437                                                 enum pipe pch_transcoder)
4438 {
4439         struct drm_device *dev = crtc->base.dev;
4440         struct drm_i915_private *dev_priv = to_i915(dev);
4441         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4442
4443         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4444                    I915_READ(HTOTAL(cpu_transcoder)));
4445         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4446                    I915_READ(HBLANK(cpu_transcoder)));
4447         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4448                    I915_READ(HSYNC(cpu_transcoder)));
4449
4450         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4451                    I915_READ(VTOTAL(cpu_transcoder)));
4452         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4453                    I915_READ(VBLANK(cpu_transcoder)));
4454         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4455                    I915_READ(VSYNC(cpu_transcoder)));
4456         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4457                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4458 }
4459
4460 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4461 {
4462         struct drm_i915_private *dev_priv = to_i915(dev);
4463         uint32_t temp;
4464
4465         temp = I915_READ(SOUTH_CHICKEN1);
4466         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4467                 return;
4468
4469         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4470         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4471
4472         temp &= ~FDI_BC_BIFURCATION_SELECT;
4473         if (enable)
4474                 temp |= FDI_BC_BIFURCATION_SELECT;
4475
4476         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4477         I915_WRITE(SOUTH_CHICKEN1, temp);
4478         POSTING_READ(SOUTH_CHICKEN1);
4479 }
4480
4481 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4482 {
4483         struct drm_device *dev = intel_crtc->base.dev;
4484
4485         switch (intel_crtc->pipe) {
4486         case PIPE_A:
4487                 break;
4488         case PIPE_B:
4489                 if (intel_crtc->config->fdi_lanes > 2)
4490                         cpt_set_fdi_bc_bifurcation(dev, false);
4491                 else
4492                         cpt_set_fdi_bc_bifurcation(dev, true);
4493
4494                 break;
4495         case PIPE_C:
4496                 cpt_set_fdi_bc_bifurcation(dev, true);
4497
4498                 break;
4499         default:
4500                 BUG();
4501         }
4502 }
4503
4504 /* Return which DP Port should be selected for Transcoder DP control */
4505 static enum port
4506 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4507 {
4508         struct drm_device *dev = crtc->dev;
4509         struct intel_encoder *encoder;
4510
4511         for_each_encoder_on_crtc(dev, crtc, encoder) {
4512                 if (encoder->type == INTEL_OUTPUT_DP ||
4513                     encoder->type == INTEL_OUTPUT_EDP)
4514                         return enc_to_dig_port(&encoder->base)->port;
4515         }
4516
4517         return -1;
4518 }
4519
4520 /*
4521  * Enable PCH resources required for PCH ports:
4522  *   - PCH PLLs
4523  *   - FDI training & RX/TX
4524  *   - update transcoder timings
4525  *   - DP transcoding bits
4526  *   - transcoder
4527  */
4528 static void ironlake_pch_enable(struct drm_crtc *crtc)
4529 {
4530         struct drm_device *dev = crtc->dev;
4531         struct drm_i915_private *dev_priv = to_i915(dev);
4532         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4533         int pipe = intel_crtc->pipe;
4534         u32 temp;
4535
4536         assert_pch_transcoder_disabled(dev_priv, pipe);
4537
4538         if (IS_IVYBRIDGE(dev_priv))
4539                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4540
4541         /* Write the TU size bits before fdi link training, so that error
4542          * detection works. */
4543         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4544                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4545
4546         /* For PCH output, training FDI link */
4547         dev_priv->display.fdi_link_train(crtc);
4548
4549         /* We need to program the right clock selection before writing the pixel
4550          * mutliplier into the DPLL. */
4551         if (HAS_PCH_CPT(dev_priv)) {
4552                 u32 sel;
4553
4554                 temp = I915_READ(PCH_DPLL_SEL);
4555                 temp |= TRANS_DPLL_ENABLE(pipe);
4556                 sel = TRANS_DPLLB_SEL(pipe);
4557                 if (intel_crtc->config->shared_dpll ==
4558                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4559                         temp |= sel;
4560                 else
4561                         temp &= ~sel;
4562                 I915_WRITE(PCH_DPLL_SEL, temp);
4563         }
4564
4565         /* XXX: pch pll's can be enabled any time before we enable the PCH
4566          * transcoder, and we actually should do this to not upset any PCH
4567          * transcoder that already use the clock when we share it.
4568          *
4569          * Note that enable_shared_dpll tries to do the right thing, but
4570          * get_shared_dpll unconditionally resets the pll - we need that to have
4571          * the right LVDS enable sequence. */
4572         intel_enable_shared_dpll(intel_crtc);
4573
4574         /* set transcoder timing, panel must allow it */
4575         assert_panel_unlocked(dev_priv, pipe);
4576         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4577
4578         intel_fdi_normal_train(crtc);
4579
4580         /* For PCH DP, enable TRANS_DP_CTL */
4581         if (HAS_PCH_CPT(dev_priv) &&
4582             intel_crtc_has_dp_encoder(intel_crtc->config)) {
4583                 const struct drm_display_mode *adjusted_mode =
4584                         &intel_crtc->config->base.adjusted_mode;
4585                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4586                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4587                 temp = I915_READ(reg);
4588                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4589                           TRANS_DP_SYNC_MASK |
4590                           TRANS_DP_BPC_MASK);
4591                 temp |= TRANS_DP_OUTPUT_ENABLE;
4592                 temp |= bpc << 9; /* same format but at 11:9 */
4593
4594                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4595                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4596                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4597                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4598
4599                 switch (intel_trans_dp_port_sel(crtc)) {
4600                 case PORT_B:
4601                         temp |= TRANS_DP_PORT_SEL_B;
4602                         break;
4603                 case PORT_C:
4604                         temp |= TRANS_DP_PORT_SEL_C;
4605                         break;
4606                 case PORT_D:
4607                         temp |= TRANS_DP_PORT_SEL_D;
4608                         break;
4609                 default:
4610                         BUG();
4611                 }
4612
4613                 I915_WRITE(reg, temp);
4614         }
4615
4616         ironlake_enable_pch_transcoder(dev_priv, pipe);
4617 }
4618
4619 static void lpt_pch_enable(struct drm_crtc *crtc)
4620 {
4621         struct drm_device *dev = crtc->dev;
4622         struct drm_i915_private *dev_priv = to_i915(dev);
4623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4624         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4625
4626         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4627
4628         lpt_program_iclkip(crtc);
4629
4630         /* Set transcoder timing. */
4631         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4632
4633         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4634 }
4635
4636 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4637 {
4638         struct drm_i915_private *dev_priv = to_i915(dev);
4639         i915_reg_t dslreg = PIPEDSL(pipe);
4640         u32 temp;
4641
4642         temp = I915_READ(dslreg);
4643         udelay(500);
4644         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4645                 if (wait_for(I915_READ(dslreg) != temp, 5))
4646                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4647         }
4648 }
4649
4650 static int
4651 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4652                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4653                   int src_w, int src_h, int dst_w, int dst_h)
4654 {
4655         struct intel_crtc_scaler_state *scaler_state =
4656                 &crtc_state->scaler_state;
4657         struct intel_crtc *intel_crtc =
4658                 to_intel_crtc(crtc_state->base.crtc);
4659         int need_scaling;
4660
4661         need_scaling = drm_rotation_90_or_270(rotation) ?
4662                 (src_h != dst_w || src_w != dst_h):
4663                 (src_w != dst_w || src_h != dst_h);
4664
4665         /*
4666          * if plane is being disabled or scaler is no more required or force detach
4667          *  - free scaler binded to this plane/crtc
4668          *  - in order to do this, update crtc->scaler_usage
4669          *
4670          * Here scaler state in crtc_state is set free so that
4671          * scaler can be assigned to other user. Actual register
4672          * update to free the scaler is done in plane/panel-fit programming.
4673          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4674          */
4675         if (force_detach || !need_scaling) {
4676                 if (*scaler_id >= 0) {
4677                         scaler_state->scaler_users &= ~(1 << scaler_user);
4678                         scaler_state->scalers[*scaler_id].in_use = 0;
4679
4680                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4681                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4682                                 intel_crtc->pipe, scaler_user, *scaler_id,
4683                                 scaler_state->scaler_users);
4684                         *scaler_id = -1;
4685                 }
4686                 return 0;
4687         }
4688
4689         /* range checks */
4690         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4691                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4692
4693                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4694                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4695                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4696                         "size is out of scaler range\n",
4697                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4698                 return -EINVAL;
4699         }
4700
4701         /* mark this plane as a scaler user in crtc_state */
4702         scaler_state->scaler_users |= (1 << scaler_user);
4703         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4704                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4705                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4706                 scaler_state->scaler_users);
4707
4708         return 0;
4709 }
4710
4711 /**
4712  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4713  *
4714  * @state: crtc's scaler state
4715  *
4716  * Return
4717  *     0 - scaler_usage updated successfully
4718  *    error - requested scaling cannot be supported or other error condition
4719  */
4720 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4721 {
4722         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4723
4724         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4725                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4726                 state->pipe_src_w, state->pipe_src_h,
4727                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4728 }
4729
4730 /**
4731  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4732  *
4733  * @state: crtc's scaler state
4734  * @plane_state: atomic plane state to update
4735  *
4736  * Return
4737  *     0 - scaler_usage updated successfully
4738  *    error - requested scaling cannot be supported or other error condition
4739  */
4740 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4741                                    struct intel_plane_state *plane_state)
4742 {
4743
4744         struct intel_plane *intel_plane =
4745                 to_intel_plane(plane_state->base.plane);
4746         struct drm_framebuffer *fb = plane_state->base.fb;
4747         int ret;
4748
4749         bool force_detach = !fb || !plane_state->base.visible;
4750
4751         ret = skl_update_scaler(crtc_state, force_detach,
4752                                 drm_plane_index(&intel_plane->base),
4753                                 &plane_state->scaler_id,
4754                                 plane_state->base.rotation,
4755                                 drm_rect_width(&plane_state->base.src) >> 16,
4756                                 drm_rect_height(&plane_state->base.src) >> 16,
4757                                 drm_rect_width(&plane_state->base.dst),
4758                                 drm_rect_height(&plane_state->base.dst));
4759
4760         if (ret || plane_state->scaler_id < 0)
4761                 return ret;
4762
4763         /* check colorkey */
4764         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4765                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4766                               intel_plane->base.base.id,
4767                               intel_plane->base.name);
4768                 return -EINVAL;
4769         }
4770
4771         /* Check src format */
4772         switch (fb->pixel_format) {
4773         case DRM_FORMAT_RGB565:
4774         case DRM_FORMAT_XBGR8888:
4775         case DRM_FORMAT_XRGB8888:
4776         case DRM_FORMAT_ABGR8888:
4777         case DRM_FORMAT_ARGB8888:
4778         case DRM_FORMAT_XRGB2101010:
4779         case DRM_FORMAT_XBGR2101010:
4780         case DRM_FORMAT_YUYV:
4781         case DRM_FORMAT_YVYU:
4782         case DRM_FORMAT_UYVY:
4783         case DRM_FORMAT_VYUY:
4784                 break;
4785         default:
4786                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4787                               intel_plane->base.base.id, intel_plane->base.name,
4788                               fb->base.id, fb->pixel_format);
4789                 return -EINVAL;
4790         }
4791
4792         return 0;
4793 }
4794
4795 static void skylake_scaler_disable(struct intel_crtc *crtc)
4796 {
4797         int i;
4798
4799         for (i = 0; i < crtc->num_scalers; i++)
4800                 skl_detach_scaler(crtc, i);
4801 }
4802
4803 static void skylake_pfit_enable(struct intel_crtc *crtc)
4804 {
4805         struct drm_device *dev = crtc->base.dev;
4806         struct drm_i915_private *dev_priv = to_i915(dev);
4807         int pipe = crtc->pipe;
4808         struct intel_crtc_scaler_state *scaler_state =
4809                 &crtc->config->scaler_state;
4810
4811         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4812
4813         if (crtc->config->pch_pfit.enabled) {
4814                 int id;
4815
4816                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4817                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4818                         return;
4819                 }
4820
4821                 id = scaler_state->scaler_id;
4822                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4823                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4824                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4825                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4826
4827                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4828         }
4829 }
4830
4831 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4832 {
4833         struct drm_device *dev = crtc->base.dev;
4834         struct drm_i915_private *dev_priv = to_i915(dev);
4835         int pipe = crtc->pipe;
4836
4837         if (crtc->config->pch_pfit.enabled) {
4838                 /* Force use of hard-coded filter coefficients
4839                  * as some pre-programmed values are broken,
4840                  * e.g. x201.
4841                  */
4842                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4843                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4844                                                  PF_PIPE_SEL_IVB(pipe));
4845                 else
4846                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4847                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4848                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4849         }
4850 }
4851
4852 void hsw_enable_ips(struct intel_crtc *crtc)
4853 {
4854         struct drm_device *dev = crtc->base.dev;
4855         struct drm_i915_private *dev_priv = to_i915(dev);
4856
4857         if (!crtc->config->ips_enabled)
4858                 return;
4859
4860         /*
4861          * We can only enable IPS after we enable a plane and wait for a vblank
4862          * This function is called from post_plane_update, which is run after
4863          * a vblank wait.
4864          */
4865
4866         assert_plane_enabled(dev_priv, crtc->plane);
4867         if (IS_BROADWELL(dev_priv)) {
4868                 mutex_lock(&dev_priv->rps.hw_lock);
4869                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4870                 mutex_unlock(&dev_priv->rps.hw_lock);
4871                 /* Quoting Art Runyan: "its not safe to expect any particular
4872                  * value in IPS_CTL bit 31 after enabling IPS through the
4873                  * mailbox." Moreover, the mailbox may return a bogus state,
4874                  * so we need to just enable it and continue on.
4875                  */
4876         } else {
4877                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4878                 /* The bit only becomes 1 in the next vblank, so this wait here
4879                  * is essentially intel_wait_for_vblank. If we don't have this
4880                  * and don't wait for vblanks until the end of crtc_enable, then
4881                  * the HW state readout code will complain that the expected
4882                  * IPS_CTL value is not the one we read. */
4883                 if (intel_wait_for_register(dev_priv,
4884                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4885                                             50))
4886                         DRM_ERROR("Timed out waiting for IPS enable\n");
4887         }
4888 }
4889
4890 void hsw_disable_ips(struct intel_crtc *crtc)
4891 {
4892         struct drm_device *dev = crtc->base.dev;
4893         struct drm_i915_private *dev_priv = to_i915(dev);
4894
4895         if (!crtc->config->ips_enabled)
4896                 return;
4897
4898         assert_plane_enabled(dev_priv, crtc->plane);
4899         if (IS_BROADWELL(dev_priv)) {
4900                 mutex_lock(&dev_priv->rps.hw_lock);
4901                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4902                 mutex_unlock(&dev_priv->rps.hw_lock);
4903                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4904                 if (intel_wait_for_register(dev_priv,
4905                                             IPS_CTL, IPS_ENABLE, 0,
4906                                             42))
4907                         DRM_ERROR("Timed out waiting for IPS disable\n");
4908         } else {
4909                 I915_WRITE(IPS_CTL, 0);
4910                 POSTING_READ(IPS_CTL);
4911         }
4912
4913         /* We need to wait for a vblank before we can disable the plane. */
4914         intel_wait_for_vblank(dev_priv, crtc->pipe);
4915 }
4916
4917 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4918 {
4919         if (intel_crtc->overlay) {
4920                 struct drm_device *dev = intel_crtc->base.dev;
4921                 struct drm_i915_private *dev_priv = to_i915(dev);
4922
4923                 mutex_lock(&dev->struct_mutex);
4924                 dev_priv->mm.interruptible = false;
4925                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4926                 dev_priv->mm.interruptible = true;
4927                 mutex_unlock(&dev->struct_mutex);
4928         }
4929
4930         /* Let userspace switch the overlay on again. In most cases userspace
4931          * has to recompute where to put it anyway.
4932          */
4933 }
4934
4935 /**
4936  * intel_post_enable_primary - Perform operations after enabling primary plane
4937  * @crtc: the CRTC whose primary plane was just enabled
4938  *
4939  * Performs potentially sleeping operations that must be done after the primary
4940  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4941  * called due to an explicit primary plane update, or due to an implicit
4942  * re-enable that is caused when a sprite plane is updated to no longer
4943  * completely hide the primary plane.
4944  */
4945 static void
4946 intel_post_enable_primary(struct drm_crtc *crtc)
4947 {
4948         struct drm_device *dev = crtc->dev;
4949         struct drm_i915_private *dev_priv = to_i915(dev);
4950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4951         int pipe = intel_crtc->pipe;
4952
4953         /*
4954          * FIXME IPS should be fine as long as one plane is
4955          * enabled, but in practice it seems to have problems
4956          * when going from primary only to sprite only and vice
4957          * versa.
4958          */
4959         hsw_enable_ips(intel_crtc);
4960
4961         /*
4962          * Gen2 reports pipe underruns whenever all planes are disabled.
4963          * So don't enable underrun reporting before at least some planes
4964          * are enabled.
4965          * FIXME: Need to fix the logic to work when we turn off all planes
4966          * but leave the pipe running.
4967          */
4968         if (IS_GEN2(dev_priv))
4969                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4970
4971         /* Underruns don't always raise interrupts, so check manually. */
4972         intel_check_cpu_fifo_underruns(dev_priv);
4973         intel_check_pch_fifo_underruns(dev_priv);
4974 }
4975
4976 /* FIXME move all this to pre_plane_update() with proper state tracking */
4977 static void
4978 intel_pre_disable_primary(struct drm_crtc *crtc)
4979 {
4980         struct drm_device *dev = crtc->dev;
4981         struct drm_i915_private *dev_priv = to_i915(dev);
4982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4983         int pipe = intel_crtc->pipe;
4984
4985         /*
4986          * Gen2 reports pipe underruns whenever all planes are disabled.
4987          * So diasble underrun reporting before all the planes get disabled.
4988          * FIXME: Need to fix the logic to work when we turn off all planes
4989          * but leave the pipe running.
4990          */
4991         if (IS_GEN2(dev_priv))
4992                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4993
4994         /*
4995          * FIXME IPS should be fine as long as one plane is
4996          * enabled, but in practice it seems to have problems
4997          * when going from primary only to sprite only and vice
4998          * versa.
4999          */
5000         hsw_disable_ips(intel_crtc);
5001 }
5002
5003 /* FIXME get rid of this and use pre_plane_update */
5004 static void
5005 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5006 {
5007         struct drm_device *dev = crtc->dev;
5008         struct drm_i915_private *dev_priv = to_i915(dev);
5009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5010         int pipe = intel_crtc->pipe;
5011
5012         intel_pre_disable_primary(crtc);
5013
5014         /*
5015          * Vblank time updates from the shadow to live plane control register
5016          * are blocked if the memory self-refresh mode is active at that
5017          * moment. So to make sure the plane gets truly disabled, disable
5018          * first the self-refresh mode. The self-refresh enable bit in turn
5019          * will be checked/applied by the HW only at the next frame start
5020          * event which is after the vblank start event, so we need to have a
5021          * wait-for-vblank between disabling the plane and the pipe.
5022          */
5023         if (HAS_GMCH_DISPLAY(dev_priv)) {
5024                 intel_set_memory_cxsr(dev_priv, false);
5025                 dev_priv->wm.vlv.cxsr = false;
5026                 intel_wait_for_vblank(dev_priv, pipe);
5027         }
5028 }
5029
5030 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5031 {
5032         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5033         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5034         struct intel_crtc_state *pipe_config =
5035                 to_intel_crtc_state(crtc->base.state);
5036         struct drm_plane *primary = crtc->base.primary;
5037         struct drm_plane_state *old_pri_state =
5038                 drm_atomic_get_existing_plane_state(old_state, primary);
5039
5040         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5041
5042         crtc->wm.cxsr_allowed = true;
5043
5044         if (pipe_config->update_wm_post && pipe_config->base.active)
5045                 intel_update_watermarks(crtc);
5046
5047         if (old_pri_state) {
5048                 struct intel_plane_state *primary_state =
5049                         to_intel_plane_state(primary->state);
5050                 struct intel_plane_state *old_primary_state =
5051                         to_intel_plane_state(old_pri_state);
5052
5053                 intel_fbc_post_update(crtc);
5054
5055                 if (primary_state->base.visible &&
5056                     (needs_modeset(&pipe_config->base) ||
5057                      !old_primary_state->base.visible))
5058                         intel_post_enable_primary(&crtc->base);
5059         }
5060 }
5061
5062 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5063 {
5064         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5065         struct drm_device *dev = crtc->base.dev;
5066         struct drm_i915_private *dev_priv = to_i915(dev);
5067         struct intel_crtc_state *pipe_config =
5068                 to_intel_crtc_state(crtc->base.state);
5069         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5070         struct drm_plane *primary = crtc->base.primary;
5071         struct drm_plane_state *old_pri_state =
5072                 drm_atomic_get_existing_plane_state(old_state, primary);
5073         bool modeset = needs_modeset(&pipe_config->base);
5074         struct intel_atomic_state *old_intel_state =
5075                 to_intel_atomic_state(old_state);
5076
5077         if (old_pri_state) {
5078                 struct intel_plane_state *primary_state =
5079                         to_intel_plane_state(primary->state);
5080                 struct intel_plane_state *old_primary_state =
5081                         to_intel_plane_state(old_pri_state);
5082
5083                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5084
5085                 if (old_primary_state->base.visible &&
5086                     (modeset || !primary_state->base.visible))
5087                         intel_pre_disable_primary(&crtc->base);
5088         }
5089
5090         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5091                 crtc->wm.cxsr_allowed = false;
5092
5093                 /*
5094                  * Vblank time updates from the shadow to live plane control register
5095                  * are blocked if the memory self-refresh mode is active at that
5096                  * moment. So to make sure the plane gets truly disabled, disable
5097                  * first the self-refresh mode. The self-refresh enable bit in turn
5098                  * will be checked/applied by the HW only at the next frame start
5099                  * event which is after the vblank start event, so we need to have a
5100                  * wait-for-vblank between disabling the plane and the pipe.
5101                  */
5102                 if (old_crtc_state->base.active) {
5103                         intel_set_memory_cxsr(dev_priv, false);
5104                         dev_priv->wm.vlv.cxsr = false;
5105                         intel_wait_for_vblank(dev_priv, crtc->pipe);
5106                 }
5107         }
5108
5109         /*
5110          * IVB workaround: must disable low power watermarks for at least
5111          * one frame before enabling scaling.  LP watermarks can be re-enabled
5112          * when scaling is disabled.
5113          *
5114          * WaCxSRDisabledForSpriteScaling:ivb
5115          */
5116         if (pipe_config->disable_lp_wm) {
5117                 ilk_disable_lp_wm(dev);
5118                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5119         }
5120
5121         /*
5122          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5123          * watermark programming here.
5124          */
5125         if (needs_modeset(&pipe_config->base))
5126                 return;
5127
5128         /*
5129          * For platforms that support atomic watermarks, program the
5130          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5131          * will be the intermediate values that are safe for both pre- and
5132          * post- vblank; when vblank happens, the 'active' values will be set
5133          * to the final 'target' values and we'll do this again to get the
5134          * optimal watermarks.  For gen9+ platforms, the values we program here
5135          * will be the final target values which will get automatically latched
5136          * at vblank time; no further programming will be necessary.
5137          *
5138          * If a platform hasn't been transitioned to atomic watermarks yet,
5139          * we'll continue to update watermarks the old way, if flags tell
5140          * us to.
5141          */
5142         if (dev_priv->display.initial_watermarks != NULL)
5143                 dev_priv->display.initial_watermarks(old_intel_state,
5144                                                      pipe_config);
5145         else if (pipe_config->update_wm_pre)
5146                 intel_update_watermarks(crtc);
5147 }
5148
5149 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5150 {
5151         struct drm_device *dev = crtc->dev;
5152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5153         struct drm_plane *p;
5154         int pipe = intel_crtc->pipe;
5155
5156         intel_crtc_dpms_overlay_disable(intel_crtc);
5157
5158         drm_for_each_plane_mask(p, dev, plane_mask)
5159                 to_intel_plane(p)->disable_plane(p, crtc);
5160
5161         /*
5162          * FIXME: Once we grow proper nuclear flip support out of this we need
5163          * to compute the mask of flip planes precisely. For the time being
5164          * consider this a flip to a NULL plane.
5165          */
5166         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5167 }
5168
5169 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5170                                           struct intel_crtc_state *crtc_state,
5171                                           struct drm_atomic_state *old_state)
5172 {
5173         struct drm_connector_state *old_conn_state;
5174         struct drm_connector *conn;
5175         int i;
5176
5177         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5178                 struct drm_connector_state *conn_state = conn->state;
5179                 struct intel_encoder *encoder =
5180                         to_intel_encoder(conn_state->best_encoder);
5181
5182                 if (conn_state->crtc != crtc)
5183                         continue;
5184
5185                 if (encoder->pre_pll_enable)
5186                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5187         }
5188 }
5189
5190 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5191                                       struct intel_crtc_state *crtc_state,
5192                                       struct drm_atomic_state *old_state)
5193 {
5194         struct drm_connector_state *old_conn_state;
5195         struct drm_connector *conn;
5196         int i;
5197
5198         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5199                 struct drm_connector_state *conn_state = conn->state;
5200                 struct intel_encoder *encoder =
5201                         to_intel_encoder(conn_state->best_encoder);
5202
5203                 if (conn_state->crtc != crtc)
5204                         continue;
5205
5206                 if (encoder->pre_enable)
5207                         encoder->pre_enable(encoder, crtc_state, conn_state);
5208         }
5209 }
5210
5211 static void intel_encoders_enable(struct drm_crtc *crtc,
5212                                   struct intel_crtc_state *crtc_state,
5213                                   struct drm_atomic_state *old_state)
5214 {
5215         struct drm_connector_state *old_conn_state;
5216         struct drm_connector *conn;
5217         int i;
5218
5219         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5220                 struct drm_connector_state *conn_state = conn->state;
5221                 struct intel_encoder *encoder =
5222                         to_intel_encoder(conn_state->best_encoder);
5223
5224                 if (conn_state->crtc != crtc)
5225                         continue;
5226
5227                 encoder->enable(encoder, crtc_state, conn_state);
5228                 intel_opregion_notify_encoder(encoder, true);
5229         }
5230 }
5231
5232 static void intel_encoders_disable(struct drm_crtc *crtc,
5233                                    struct intel_crtc_state *old_crtc_state,
5234                                    struct drm_atomic_state *old_state)
5235 {
5236         struct drm_connector_state *old_conn_state;
5237         struct drm_connector *conn;
5238         int i;
5239
5240         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5241                 struct intel_encoder *encoder =
5242                         to_intel_encoder(old_conn_state->best_encoder);
5243
5244                 if (old_conn_state->crtc != crtc)
5245                         continue;
5246
5247                 intel_opregion_notify_encoder(encoder, false);
5248                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5249         }
5250 }
5251
5252 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5253                                         struct intel_crtc_state *old_crtc_state,
5254                                         struct drm_atomic_state *old_state)
5255 {
5256         struct drm_connector_state *old_conn_state;
5257         struct drm_connector *conn;
5258         int i;
5259
5260         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5261                 struct intel_encoder *encoder =
5262                         to_intel_encoder(old_conn_state->best_encoder);
5263
5264                 if (old_conn_state->crtc != crtc)
5265                         continue;
5266
5267                 if (encoder->post_disable)
5268                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5269         }
5270 }
5271
5272 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5273                                             struct intel_crtc_state *old_crtc_state,
5274                                             struct drm_atomic_state *old_state)
5275 {
5276         struct drm_connector_state *old_conn_state;
5277         struct drm_connector *conn;
5278         int i;
5279
5280         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5281                 struct intel_encoder *encoder =
5282                         to_intel_encoder(old_conn_state->best_encoder);
5283
5284                 if (old_conn_state->crtc != crtc)
5285                         continue;
5286
5287                 if (encoder->post_pll_disable)
5288                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5289         }
5290 }
5291
5292 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5293                                  struct drm_atomic_state *old_state)
5294 {
5295         struct drm_crtc *crtc = pipe_config->base.crtc;
5296         struct drm_device *dev = crtc->dev;
5297         struct drm_i915_private *dev_priv = to_i915(dev);
5298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5299         int pipe = intel_crtc->pipe;
5300         struct intel_atomic_state *old_intel_state =
5301                 to_intel_atomic_state(old_state);
5302
5303         if (WARN_ON(intel_crtc->active))
5304                 return;
5305
5306         /*
5307          * Sometimes spurious CPU pipe underruns happen during FDI
5308          * training, at least with VGA+HDMI cloning. Suppress them.
5309          *
5310          * On ILK we get an occasional spurious CPU pipe underruns
5311          * between eDP port A enable and vdd enable. Also PCH port
5312          * enable seems to result in the occasional CPU pipe underrun.
5313          *
5314          * Spurious PCH underruns also occur during PCH enabling.
5315          */
5316         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5317                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5318         if (intel_crtc->config->has_pch_encoder)
5319                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5320
5321         if (intel_crtc->config->has_pch_encoder)
5322                 intel_prepare_shared_dpll(intel_crtc);
5323
5324         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5325                 intel_dp_set_m_n(intel_crtc, M1_N1);
5326
5327         intel_set_pipe_timings(intel_crtc);
5328         intel_set_pipe_src_size(intel_crtc);
5329
5330         if (intel_crtc->config->has_pch_encoder) {
5331                 intel_cpu_transcoder_set_m_n(intel_crtc,
5332                                      &intel_crtc->config->fdi_m_n, NULL);
5333         }
5334
5335         ironlake_set_pipeconf(crtc);
5336
5337         intel_crtc->active = true;
5338
5339         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5340
5341         if (intel_crtc->config->has_pch_encoder) {
5342                 /* Note: FDI PLL enabling _must_ be done before we enable the
5343                  * cpu pipes, hence this is separate from all the other fdi/pch
5344                  * enabling. */
5345                 ironlake_fdi_pll_enable(intel_crtc);
5346         } else {
5347                 assert_fdi_tx_disabled(dev_priv, pipe);
5348                 assert_fdi_rx_disabled(dev_priv, pipe);
5349         }
5350
5351         ironlake_pfit_enable(intel_crtc);
5352
5353         /*
5354          * On ILK+ LUT must be loaded before the pipe is running but with
5355          * clocks enabled
5356          */
5357         intel_color_load_luts(&pipe_config->base);
5358
5359         if (dev_priv->display.initial_watermarks != NULL)
5360                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5361         intel_enable_pipe(intel_crtc);
5362
5363         if (intel_crtc->config->has_pch_encoder)
5364                 ironlake_pch_enable(crtc);
5365
5366         assert_vblank_disabled(crtc);
5367         drm_crtc_vblank_on(crtc);
5368
5369         intel_encoders_enable(crtc, pipe_config, old_state);
5370
5371         if (HAS_PCH_CPT(dev_priv))
5372                 cpt_verify_modeset(dev, intel_crtc->pipe);
5373
5374         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5375         if (intel_crtc->config->has_pch_encoder)
5376                 intel_wait_for_vblank(dev_priv, pipe);
5377         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5378         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5379 }
5380
5381 /* IPS only exists on ULT machines and is tied to pipe A. */
5382 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5383 {
5384         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5385 }
5386
5387 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5388                                 struct drm_atomic_state *old_state)
5389 {
5390         struct drm_crtc *crtc = pipe_config->base.crtc;
5391         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5393         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5394         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5395         struct intel_atomic_state *old_intel_state =
5396                 to_intel_atomic_state(old_state);
5397
5398         if (WARN_ON(intel_crtc->active))
5399                 return;
5400
5401         if (intel_crtc->config->has_pch_encoder)
5402                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5403                                                       false);
5404
5405         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5406
5407         if (intel_crtc->config->shared_dpll)
5408                 intel_enable_shared_dpll(intel_crtc);
5409
5410         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5411                 intel_dp_set_m_n(intel_crtc, M1_N1);
5412
5413         if (!transcoder_is_dsi(cpu_transcoder))
5414                 intel_set_pipe_timings(intel_crtc);
5415
5416         intel_set_pipe_src_size(intel_crtc);
5417
5418         if (cpu_transcoder != TRANSCODER_EDP &&
5419             !transcoder_is_dsi(cpu_transcoder)) {
5420                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5421                            intel_crtc->config->pixel_multiplier - 1);
5422         }
5423
5424         if (intel_crtc->config->has_pch_encoder) {
5425                 intel_cpu_transcoder_set_m_n(intel_crtc,
5426                                      &intel_crtc->config->fdi_m_n, NULL);
5427         }
5428
5429         if (!transcoder_is_dsi(cpu_transcoder))
5430                 haswell_set_pipeconf(crtc);
5431
5432         haswell_set_pipemisc(crtc);
5433
5434         intel_color_set_csc(&pipe_config->base);
5435
5436         intel_crtc->active = true;
5437
5438         if (intel_crtc->config->has_pch_encoder)
5439                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5440         else
5441                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5442
5443         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5444
5445         if (intel_crtc->config->has_pch_encoder)
5446                 dev_priv->display.fdi_link_train(crtc);
5447
5448         if (!transcoder_is_dsi(cpu_transcoder))
5449                 intel_ddi_enable_pipe_clock(intel_crtc);
5450
5451         if (INTEL_GEN(dev_priv) >= 9)
5452                 skylake_pfit_enable(intel_crtc);
5453         else
5454                 ironlake_pfit_enable(intel_crtc);
5455
5456         /*
5457          * On ILK+ LUT must be loaded before the pipe is running but with
5458          * clocks enabled
5459          */
5460         intel_color_load_luts(&pipe_config->base);
5461
5462         intel_ddi_set_pipe_settings(crtc);
5463         if (!transcoder_is_dsi(cpu_transcoder))
5464                 intel_ddi_enable_transcoder_func(crtc);
5465
5466         if (dev_priv->display.initial_watermarks != NULL)
5467                 dev_priv->display.initial_watermarks(old_intel_state,
5468                                                      pipe_config);
5469         else
5470                 intel_update_watermarks(intel_crtc);
5471
5472         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5473         if (!transcoder_is_dsi(cpu_transcoder))
5474                 intel_enable_pipe(intel_crtc);
5475
5476         if (intel_crtc->config->has_pch_encoder)
5477                 lpt_pch_enable(crtc);
5478
5479         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5480                 intel_ddi_set_vc_payload_alloc(crtc, true);
5481
5482         assert_vblank_disabled(crtc);
5483         drm_crtc_vblank_on(crtc);
5484
5485         intel_encoders_enable(crtc, pipe_config, old_state);
5486
5487         if (intel_crtc->config->has_pch_encoder) {
5488                 intel_wait_for_vblank(dev_priv, pipe);
5489                 intel_wait_for_vblank(dev_priv, pipe);
5490                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5491                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5492                                                       true);
5493         }
5494
5495         /* If we change the relative order between pipe/planes enabling, we need
5496          * to change the workaround. */
5497         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5498         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5499                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5500                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5501         }
5502 }
5503
5504 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5505 {
5506         struct drm_device *dev = crtc->base.dev;
5507         struct drm_i915_private *dev_priv = to_i915(dev);
5508         int pipe = crtc->pipe;
5509
5510         /* To avoid upsetting the power well on haswell only disable the pfit if
5511          * it's in use. The hw state code will make sure we get this right. */
5512         if (force || crtc->config->pch_pfit.enabled) {
5513                 I915_WRITE(PF_CTL(pipe), 0);
5514                 I915_WRITE(PF_WIN_POS(pipe), 0);
5515                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5516         }
5517 }
5518
5519 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5520                                   struct drm_atomic_state *old_state)
5521 {
5522         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5523         struct drm_device *dev = crtc->dev;
5524         struct drm_i915_private *dev_priv = to_i915(dev);
5525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5526         int pipe = intel_crtc->pipe;
5527
5528         /*
5529          * Sometimes spurious CPU pipe underruns happen when the
5530          * pipe is already disabled, but FDI RX/TX is still enabled.
5531          * Happens at least with VGA+HDMI cloning. Suppress them.
5532          */
5533         if (intel_crtc->config->has_pch_encoder) {
5534                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5535                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5536         }
5537
5538         intel_encoders_disable(crtc, old_crtc_state, old_state);
5539
5540         drm_crtc_vblank_off(crtc);
5541         assert_vblank_disabled(crtc);
5542
5543         intel_disable_pipe(intel_crtc);
5544
5545         ironlake_pfit_disable(intel_crtc, false);
5546
5547         if (intel_crtc->config->has_pch_encoder)
5548                 ironlake_fdi_disable(crtc);
5549
5550         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5551
5552         if (intel_crtc->config->has_pch_encoder) {
5553                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5554
5555                 if (HAS_PCH_CPT(dev_priv)) {
5556                         i915_reg_t reg;
5557                         u32 temp;
5558
5559                         /* disable TRANS_DP_CTL */
5560                         reg = TRANS_DP_CTL(pipe);
5561                         temp = I915_READ(reg);
5562                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5563                                   TRANS_DP_PORT_SEL_MASK);
5564                         temp |= TRANS_DP_PORT_SEL_NONE;
5565                         I915_WRITE(reg, temp);
5566
5567                         /* disable DPLL_SEL */
5568                         temp = I915_READ(PCH_DPLL_SEL);
5569                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5570                         I915_WRITE(PCH_DPLL_SEL, temp);
5571                 }
5572
5573                 ironlake_fdi_pll_disable(intel_crtc);
5574         }
5575
5576         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5577         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5578 }
5579
5580 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5581                                  struct drm_atomic_state *old_state)
5582 {
5583         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5584         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5586         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5587
5588         if (intel_crtc->config->has_pch_encoder)
5589                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5590                                                       false);
5591
5592         intel_encoders_disable(crtc, old_crtc_state, old_state);
5593
5594         drm_crtc_vblank_off(crtc);
5595         assert_vblank_disabled(crtc);
5596
5597         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5598         if (!transcoder_is_dsi(cpu_transcoder))
5599                 intel_disable_pipe(intel_crtc);
5600
5601         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5602                 intel_ddi_set_vc_payload_alloc(crtc, false);
5603
5604         if (!transcoder_is_dsi(cpu_transcoder))
5605                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5606
5607         if (INTEL_GEN(dev_priv) >= 9)
5608                 skylake_scaler_disable(intel_crtc);
5609         else
5610                 ironlake_pfit_disable(intel_crtc, false);
5611
5612         if (!transcoder_is_dsi(cpu_transcoder))
5613                 intel_ddi_disable_pipe_clock(intel_crtc);
5614
5615         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5616
5617         if (old_crtc_state->has_pch_encoder)
5618                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5619                                                       true);
5620 }
5621
5622 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5623 {
5624         struct drm_device *dev = crtc->base.dev;
5625         struct drm_i915_private *dev_priv = to_i915(dev);
5626         struct intel_crtc_state *pipe_config = crtc->config;
5627
5628         if (!pipe_config->gmch_pfit.control)
5629                 return;
5630
5631         /*
5632          * The panel fitter should only be adjusted whilst the pipe is disabled,
5633          * according to register description and PRM.
5634          */
5635         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5636         assert_pipe_disabled(dev_priv, crtc->pipe);
5637
5638         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5639         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5640
5641         /* Border color in case we don't scale up to the full screen. Black by
5642          * default, change to something else for debugging. */
5643         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5644 }
5645
5646 static enum intel_display_power_domain port_to_power_domain(enum port port)
5647 {
5648         switch (port) {
5649         case PORT_A:
5650                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5651         case PORT_B:
5652                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5653         case PORT_C:
5654                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5655         case PORT_D:
5656                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5657         case PORT_E:
5658                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5659         default:
5660                 MISSING_CASE(port);
5661                 return POWER_DOMAIN_PORT_OTHER;
5662         }
5663 }
5664
5665 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5666 {
5667         switch (port) {
5668         case PORT_A:
5669                 return POWER_DOMAIN_AUX_A;
5670         case PORT_B:
5671                 return POWER_DOMAIN_AUX_B;
5672         case PORT_C:
5673                 return POWER_DOMAIN_AUX_C;
5674         case PORT_D:
5675                 return POWER_DOMAIN_AUX_D;
5676         case PORT_E:
5677                 /* FIXME: Check VBT for actual wiring of PORT E */
5678                 return POWER_DOMAIN_AUX_D;
5679         default:
5680                 MISSING_CASE(port);
5681                 return POWER_DOMAIN_AUX_A;
5682         }
5683 }
5684
5685 enum intel_display_power_domain
5686 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5687 {
5688         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5689         struct intel_digital_port *intel_dig_port;
5690
5691         switch (intel_encoder->type) {
5692         case INTEL_OUTPUT_UNKNOWN:
5693                 /* Only DDI platforms should ever use this output type */
5694                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5695         case INTEL_OUTPUT_DP:
5696         case INTEL_OUTPUT_HDMI:
5697         case INTEL_OUTPUT_EDP:
5698                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5699                 return port_to_power_domain(intel_dig_port->port);
5700         case INTEL_OUTPUT_DP_MST:
5701                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5702                 return port_to_power_domain(intel_dig_port->port);
5703         case INTEL_OUTPUT_ANALOG:
5704                 return POWER_DOMAIN_PORT_CRT;
5705         case INTEL_OUTPUT_DSI:
5706                 return POWER_DOMAIN_PORT_DSI;
5707         default:
5708                 return POWER_DOMAIN_PORT_OTHER;
5709         }
5710 }
5711
5712 enum intel_display_power_domain
5713 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5714 {
5715         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5716         struct intel_digital_port *intel_dig_port;
5717
5718         switch (intel_encoder->type) {
5719         case INTEL_OUTPUT_UNKNOWN:
5720         case INTEL_OUTPUT_HDMI:
5721                 /*
5722                  * Only DDI platforms should ever use these output types.
5723                  * We can get here after the HDMI detect code has already set
5724                  * the type of the shared encoder. Since we can't be sure
5725                  * what's the status of the given connectors, play safe and
5726                  * run the DP detection too.
5727                  */
5728                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5729         case INTEL_OUTPUT_DP:
5730         case INTEL_OUTPUT_EDP:
5731                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5732                 return port_to_aux_power_domain(intel_dig_port->port);
5733         case INTEL_OUTPUT_DP_MST:
5734                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5735                 return port_to_aux_power_domain(intel_dig_port->port);
5736         default:
5737                 MISSING_CASE(intel_encoder->type);
5738                 return POWER_DOMAIN_AUX_A;
5739         }
5740 }
5741
5742 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5743                                             struct intel_crtc_state *crtc_state)
5744 {
5745         struct drm_device *dev = crtc->dev;
5746         struct drm_encoder *encoder;
5747         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5748         enum pipe pipe = intel_crtc->pipe;
5749         unsigned long mask;
5750         enum transcoder transcoder = crtc_state->cpu_transcoder;
5751
5752         if (!crtc_state->base.active)
5753                 return 0;
5754
5755         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5756         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5757         if (crtc_state->pch_pfit.enabled ||
5758             crtc_state->pch_pfit.force_thru)
5759                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5760
5761         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5762                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5763
5764                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5765         }
5766
5767         if (crtc_state->shared_dpll)
5768                 mask |= BIT(POWER_DOMAIN_PLLS);
5769
5770         return mask;
5771 }
5772
5773 static unsigned long
5774 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5775                                struct intel_crtc_state *crtc_state)
5776 {
5777         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5779         enum intel_display_power_domain domain;
5780         unsigned long domains, new_domains, old_domains;
5781
5782         old_domains = intel_crtc->enabled_power_domains;
5783         intel_crtc->enabled_power_domains = new_domains =
5784                 get_crtc_power_domains(crtc, crtc_state);
5785
5786         domains = new_domains & ~old_domains;
5787
5788         for_each_power_domain(domain, domains)
5789                 intel_display_power_get(dev_priv, domain);
5790
5791         return old_domains & ~new_domains;
5792 }
5793
5794 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5795                                       unsigned long domains)
5796 {
5797         enum intel_display_power_domain domain;
5798
5799         for_each_power_domain(domain, domains)
5800                 intel_display_power_put(dev_priv, domain);
5801 }
5802
5803 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5804 {
5805         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5806
5807         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5808             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5809                 return max_cdclk_freq;
5810         else if (IS_CHERRYVIEW(dev_priv))
5811                 return max_cdclk_freq*95/100;
5812         else if (INTEL_INFO(dev_priv)->gen < 4)
5813                 return 2*max_cdclk_freq*90/100;
5814         else
5815                 return max_cdclk_freq*90/100;
5816 }
5817
5818 static int skl_calc_cdclk(int max_pixclk, int vco);
5819
5820 static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
5821 {
5822         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5823                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5824                 int max_cdclk, vco;
5825
5826                 vco = dev_priv->skl_preferred_vco_freq;
5827                 WARN_ON(vco != 8100000 && vco != 8640000);
5828
5829                 /*
5830                  * Use the lower (vco 8640) cdclk values as a
5831                  * first guess. skl_calc_cdclk() will correct it
5832                  * if the preferred vco is 8100 instead.
5833                  */
5834                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5835                         max_cdclk = 617143;
5836                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5837                         max_cdclk = 540000;
5838                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5839                         max_cdclk = 432000;
5840                 else
5841                         max_cdclk = 308571;
5842
5843                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5844         } else if (IS_BROXTON(dev_priv)) {
5845                 dev_priv->max_cdclk_freq = 624000;
5846         } else if (IS_BROADWELL(dev_priv))  {
5847                 /*
5848                  * FIXME with extra cooling we can allow
5849                  * 540 MHz for ULX and 675 Mhz for ULT.
5850                  * How can we know if extra cooling is
5851                  * available? PCI ID, VTB, something else?
5852                  */
5853                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5854                         dev_priv->max_cdclk_freq = 450000;
5855                 else if (IS_BDW_ULX(dev_priv))
5856                         dev_priv->max_cdclk_freq = 450000;
5857                 else if (IS_BDW_ULT(dev_priv))
5858                         dev_priv->max_cdclk_freq = 540000;
5859                 else
5860                         dev_priv->max_cdclk_freq = 675000;
5861         } else if (IS_CHERRYVIEW(dev_priv)) {
5862                 dev_priv->max_cdclk_freq = 320000;
5863         } else if (IS_VALLEYVIEW(dev_priv)) {
5864                 dev_priv->max_cdclk_freq = 400000;
5865         } else {
5866                 /* otherwise assume cdclk is fixed */
5867                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5868         }
5869
5870         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5871
5872         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5873                          dev_priv->max_cdclk_freq);
5874
5875         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5876                          dev_priv->max_dotclk_freq);
5877 }
5878
5879 static void intel_update_cdclk(struct drm_i915_private *dev_priv)
5880 {
5881         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv);
5882
5883         if (INTEL_GEN(dev_priv) >= 9)
5884                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5885                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5886                                  dev_priv->cdclk_pll.ref);
5887         else
5888                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5889                                  dev_priv->cdclk_freq);
5890
5891         /*
5892          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5893          * Programmng [sic] note: bit[9:2] should be programmed to the number
5894          * of cdclk that generates 4MHz reference clock freq which is used to
5895          * generate GMBus clock. This will vary with the cdclk freq.
5896          */
5897         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5898                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5899 }
5900
5901 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5902 static int skl_cdclk_decimal(int cdclk)
5903 {
5904         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5905 }
5906
5907 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5908 {
5909         int ratio;
5910
5911         if (cdclk == dev_priv->cdclk_pll.ref)
5912                 return 0;
5913
5914         switch (cdclk) {
5915         default:
5916                 MISSING_CASE(cdclk);
5917         case 144000:
5918         case 288000:
5919         case 384000:
5920         case 576000:
5921                 ratio = 60;
5922                 break;
5923         case 624000:
5924                 ratio = 65;
5925                 break;
5926         }
5927
5928         return dev_priv->cdclk_pll.ref * ratio;
5929 }
5930
5931 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5932 {
5933         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5934
5935         /* Timeout 200us */
5936         if (intel_wait_for_register(dev_priv,
5937                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5938                                     1))
5939                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5940
5941         dev_priv->cdclk_pll.vco = 0;
5942 }
5943
5944 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5945 {
5946         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5947         u32 val;
5948
5949         val = I915_READ(BXT_DE_PLL_CTL);
5950         val &= ~BXT_DE_PLL_RATIO_MASK;
5951         val |= BXT_DE_PLL_RATIO(ratio);
5952         I915_WRITE(BXT_DE_PLL_CTL, val);
5953
5954         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5955
5956         /* Timeout 200us */
5957         if (intel_wait_for_register(dev_priv,
5958                                     BXT_DE_PLL_ENABLE,
5959                                     BXT_DE_PLL_LOCK,
5960                                     BXT_DE_PLL_LOCK,
5961                                     1))
5962                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5963
5964         dev_priv->cdclk_pll.vco = vco;
5965 }
5966
5967 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5968 {
5969         u32 val, divider;
5970         int vco, ret;
5971
5972         vco = bxt_de_pll_vco(dev_priv, cdclk);
5973
5974         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5975
5976         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5977         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5978         case 8:
5979                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5980                 break;
5981         case 4:
5982                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5983                 break;
5984         case 3:
5985                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5986                 break;
5987         case 2:
5988                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5989                 break;
5990         default:
5991                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5992                 WARN_ON(vco != 0);
5993
5994                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5995                 break;
5996         }
5997
5998         /* Inform power controller of upcoming frequency change */
5999         mutex_lock(&dev_priv->rps.hw_lock);
6000         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6001                                       0x80000000);
6002         mutex_unlock(&dev_priv->rps.hw_lock);
6003
6004         if (ret) {
6005                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6006                           ret, cdclk);
6007                 return;
6008         }
6009
6010         if (dev_priv->cdclk_pll.vco != 0 &&
6011             dev_priv->cdclk_pll.vco != vco)
6012                 bxt_de_pll_disable(dev_priv);
6013
6014         if (dev_priv->cdclk_pll.vco != vco)
6015                 bxt_de_pll_enable(dev_priv, vco);
6016
6017         val = divider | skl_cdclk_decimal(cdclk);
6018         /*
6019          * FIXME if only the cd2x divider needs changing, it could be done
6020          * without shutting off the pipe (if only one pipe is active).
6021          */
6022         val |= BXT_CDCLK_CD2X_PIPE_NONE;
6023         /*
6024          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6025          * enable otherwise.
6026          */
6027         if (cdclk >= 500000)
6028                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6029         I915_WRITE(CDCLK_CTL, val);
6030
6031         mutex_lock(&dev_priv->rps.hw_lock);
6032         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6033                                       DIV_ROUND_UP(cdclk, 25000));
6034         mutex_unlock(&dev_priv->rps.hw_lock);
6035
6036         if (ret) {
6037                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6038                           ret, cdclk);
6039                 return;
6040         }
6041
6042         intel_update_cdclk(dev_priv);
6043 }
6044
6045 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6046 {
6047         u32 cdctl, expected;
6048
6049         intel_update_cdclk(dev_priv);
6050
6051         if (dev_priv->cdclk_pll.vco == 0 ||
6052             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6053                 goto sanitize;
6054
6055         /* DPLL okay; verify the cdclock
6056          *
6057          * Some BIOS versions leave an incorrect decimal frequency value and
6058          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6059          * so sanitize this register.
6060          */
6061         cdctl = I915_READ(CDCLK_CTL);
6062         /*
6063          * Let's ignore the pipe field, since BIOS could have configured the
6064          * dividers both synching to an active pipe, or asynchronously
6065          * (PIPE_NONE).
6066          */
6067         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6068
6069         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6070                    skl_cdclk_decimal(dev_priv->cdclk_freq);
6071         /*
6072          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6073          * enable otherwise.
6074          */
6075         if (dev_priv->cdclk_freq >= 500000)
6076                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6077
6078         if (cdctl == expected)
6079                 /* All well; nothing to sanitize */
6080                 return;
6081
6082 sanitize:
6083         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6084
6085         /* force cdclk programming */
6086         dev_priv->cdclk_freq = 0;
6087
6088         /* force full PLL disable + enable */
6089         dev_priv->cdclk_pll.vco = -1;
6090 }
6091
6092 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6093 {
6094         bxt_sanitize_cdclk(dev_priv);
6095
6096         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6097                 return;
6098
6099         /*
6100          * FIXME:
6101          * - The initial CDCLK needs to be read from VBT.
6102          *   Need to make this change after VBT has changes for BXT.
6103          */
6104         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6105 }
6106
6107 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6108 {
6109         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6110 }
6111
6112 static int skl_calc_cdclk(int max_pixclk, int vco)
6113 {
6114         if (vco == 8640000) {
6115                 if (max_pixclk > 540000)
6116                         return 617143;
6117                 else if (max_pixclk > 432000)
6118                         return 540000;
6119                 else if (max_pixclk > 308571)
6120                         return 432000;
6121                 else
6122                         return 308571;
6123         } else {
6124                 if (max_pixclk > 540000)
6125                         return 675000;
6126                 else if (max_pixclk > 450000)
6127                         return 540000;
6128                 else if (max_pixclk > 337500)
6129                         return 450000;
6130                 else
6131                         return 337500;
6132         }
6133 }
6134
6135 static void
6136 skl_dpll0_update(struct drm_i915_private *dev_priv)
6137 {
6138         u32 val;
6139
6140         dev_priv->cdclk_pll.ref = 24000;
6141         dev_priv->cdclk_pll.vco = 0;
6142
6143         val = I915_READ(LCPLL1_CTL);
6144         if ((val & LCPLL_PLL_ENABLE) == 0)
6145                 return;
6146
6147         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6148                 return;
6149
6150         val = I915_READ(DPLL_CTRL1);
6151
6152         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6153                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6154                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6155                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6156                 return;
6157
6158         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6159         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6160         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6161         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6162         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6163                 dev_priv->cdclk_pll.vco = 8100000;
6164                 break;
6165         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6166         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6167                 dev_priv->cdclk_pll.vco = 8640000;
6168                 break;
6169         default:
6170                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6171                 break;
6172         }
6173 }
6174
6175 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6176 {
6177         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6178
6179         dev_priv->skl_preferred_vco_freq = vco;
6180
6181         if (changed)
6182                 intel_update_max_cdclk(dev_priv);
6183 }
6184
6185 static void
6186 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6187 {
6188         int min_cdclk = skl_calc_cdclk(0, vco);
6189         u32 val;
6190
6191         WARN_ON(vco != 8100000 && vco != 8640000);
6192
6193         /* select the minimum CDCLK before enabling DPLL 0 */
6194         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6195         I915_WRITE(CDCLK_CTL, val);
6196         POSTING_READ(CDCLK_CTL);
6197
6198         /*
6199          * We always enable DPLL0 with the lowest link rate possible, but still
6200          * taking into account the VCO required to operate the eDP panel at the
6201          * desired frequency. The usual DP link rates operate with a VCO of
6202          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6203          * The modeset code is responsible for the selection of the exact link
6204          * rate later on, with the constraint of choosing a frequency that
6205          * works with vco.
6206          */
6207         val = I915_READ(DPLL_CTRL1);
6208
6209         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6210                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6211         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6212         if (vco == 8640000)
6213                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6214                                             SKL_DPLL0);
6215         else
6216                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6217                                             SKL_DPLL0);
6218
6219         I915_WRITE(DPLL_CTRL1, val);
6220         POSTING_READ(DPLL_CTRL1);
6221
6222         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6223
6224         if (intel_wait_for_register(dev_priv,
6225                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6226                                     5))
6227                 DRM_ERROR("DPLL0 not locked\n");
6228
6229         dev_priv->cdclk_pll.vco = vco;
6230
6231         /* We'll want to keep using the current vco from now on. */
6232         skl_set_preferred_cdclk_vco(dev_priv, vco);
6233 }
6234
6235 static void
6236 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6237 {
6238         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6239         if (intel_wait_for_register(dev_priv,
6240                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6241                                    1))
6242                 DRM_ERROR("Couldn't disable DPLL0\n");
6243
6244         dev_priv->cdclk_pll.vco = 0;
6245 }
6246
6247 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6248 {
6249         int ret;
6250         u32 val;
6251
6252         /* inform PCU we want to change CDCLK */
6253         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6254         mutex_lock(&dev_priv->rps.hw_lock);
6255         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6256         mutex_unlock(&dev_priv->rps.hw_lock);
6257
6258         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6259 }
6260
6261 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6262 {
6263         return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6264 }
6265
6266 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6267 {
6268         u32 freq_select, pcu_ack;
6269
6270         WARN_ON((cdclk == 24000) != (vco == 0));
6271
6272         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6273
6274         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6275                 DRM_ERROR("failed to inform PCU about cdclk change\n");
6276                 return;
6277         }
6278
6279         /* set CDCLK_CTL */
6280         switch (cdclk) {
6281         case 450000:
6282         case 432000:
6283                 freq_select = CDCLK_FREQ_450_432;
6284                 pcu_ack = 1;
6285                 break;
6286         case 540000:
6287                 freq_select = CDCLK_FREQ_540;
6288                 pcu_ack = 2;
6289                 break;
6290         case 308571:
6291         case 337500:
6292         default:
6293                 freq_select = CDCLK_FREQ_337_308;
6294                 pcu_ack = 0;
6295                 break;
6296         case 617143:
6297         case 675000:
6298                 freq_select = CDCLK_FREQ_675_617;
6299                 pcu_ack = 3;
6300                 break;
6301         }
6302
6303         if (dev_priv->cdclk_pll.vco != 0 &&
6304             dev_priv->cdclk_pll.vco != vco)
6305                 skl_dpll0_disable(dev_priv);
6306
6307         if (dev_priv->cdclk_pll.vco != vco)
6308                 skl_dpll0_enable(dev_priv, vco);
6309
6310         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6311         POSTING_READ(CDCLK_CTL);
6312
6313         /* inform PCU of the change */
6314         mutex_lock(&dev_priv->rps.hw_lock);
6315         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6316         mutex_unlock(&dev_priv->rps.hw_lock);
6317
6318         intel_update_cdclk(dev_priv);
6319 }
6320
6321 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6322
6323 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6324 {
6325         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6326 }
6327
6328 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6329 {
6330         int cdclk, vco;
6331
6332         skl_sanitize_cdclk(dev_priv);
6333
6334         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6335                 /*
6336                  * Use the current vco as our initial
6337                  * guess as to what the preferred vco is.
6338                  */
6339                 if (dev_priv->skl_preferred_vco_freq == 0)
6340                         skl_set_preferred_cdclk_vco(dev_priv,
6341                                                     dev_priv->cdclk_pll.vco);
6342                 return;
6343         }
6344
6345         vco = dev_priv->skl_preferred_vco_freq;
6346         if (vco == 0)
6347                 vco = 8100000;
6348         cdclk = skl_calc_cdclk(0, vco);
6349
6350         skl_set_cdclk(dev_priv, cdclk, vco);
6351 }
6352
6353 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6354 {
6355         uint32_t cdctl, expected;
6356
6357         /*
6358          * check if the pre-os intialized the display
6359          * There is SWF18 scratchpad register defined which is set by the
6360          * pre-os which can be used by the OS drivers to check the status
6361          */
6362         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6363                 goto sanitize;
6364
6365         intel_update_cdclk(dev_priv);
6366         /* Is PLL enabled and locked ? */
6367         if (dev_priv->cdclk_pll.vco == 0 ||
6368             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6369                 goto sanitize;
6370
6371         /* DPLL okay; verify the cdclock
6372          *
6373          * Noticed in some instances that the freq selection is correct but
6374          * decimal part is programmed wrong from BIOS where pre-os does not
6375          * enable display. Verify the same as well.
6376          */
6377         cdctl = I915_READ(CDCLK_CTL);
6378         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6379                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6380         if (cdctl == expected)
6381                 /* All well; nothing to sanitize */
6382                 return;
6383
6384 sanitize:
6385         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6386
6387         /* force cdclk programming */
6388         dev_priv->cdclk_freq = 0;
6389         /* force full PLL disable + enable */
6390         dev_priv->cdclk_pll.vco = -1;
6391 }
6392
6393 /* Adjust CDclk dividers to allow high res or save power if possible */
6394 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6395 {
6396         struct drm_i915_private *dev_priv = to_i915(dev);
6397         u32 val, cmd;
6398
6399         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6400                                         != dev_priv->cdclk_freq);
6401
6402         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6403                 cmd = 2;
6404         else if (cdclk == 266667)
6405                 cmd = 1;
6406         else
6407                 cmd = 0;
6408
6409         mutex_lock(&dev_priv->rps.hw_lock);
6410         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6411         val &= ~DSPFREQGUAR_MASK;
6412         val |= (cmd << DSPFREQGUAR_SHIFT);
6413         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6414         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6415                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6416                      50)) {
6417                 DRM_ERROR("timed out waiting for CDclk change\n");
6418         }
6419         mutex_unlock(&dev_priv->rps.hw_lock);
6420
6421         mutex_lock(&dev_priv->sb_lock);
6422
6423         if (cdclk == 400000) {
6424                 u32 divider;
6425
6426                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6427
6428                 /* adjust cdclk divider */
6429                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6430                 val &= ~CCK_FREQUENCY_VALUES;
6431                 val |= divider;
6432                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6433
6434                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6435                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6436                              50))
6437                         DRM_ERROR("timed out waiting for CDclk change\n");
6438         }
6439
6440         /* adjust self-refresh exit latency value */
6441         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6442         val &= ~0x7f;
6443
6444         /*
6445          * For high bandwidth configs, we set a higher latency in the bunit
6446          * so that the core display fetch happens in time to avoid underruns.
6447          */
6448         if (cdclk == 400000)
6449                 val |= 4500 / 250; /* 4.5 usec */
6450         else
6451                 val |= 3000 / 250; /* 3.0 usec */
6452         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6453
6454         mutex_unlock(&dev_priv->sb_lock);
6455
6456         intel_update_cdclk(dev_priv);
6457 }
6458
6459 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6460 {
6461         struct drm_i915_private *dev_priv = to_i915(dev);
6462         u32 val, cmd;
6463
6464         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6465                                                 != dev_priv->cdclk_freq);
6466
6467         switch (cdclk) {
6468         case 333333:
6469         case 320000:
6470         case 266667:
6471         case 200000:
6472                 break;
6473         default:
6474                 MISSING_CASE(cdclk);
6475                 return;
6476         }
6477
6478         /*
6479          * Specs are full of misinformation, but testing on actual
6480          * hardware has shown that we just need to write the desired
6481          * CCK divider into the Punit register.
6482          */
6483         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6484
6485         mutex_lock(&dev_priv->rps.hw_lock);
6486         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6487         val &= ~DSPFREQGUAR_MASK_CHV;
6488         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6489         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6490         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6491                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6492                      50)) {
6493                 DRM_ERROR("timed out waiting for CDclk change\n");
6494         }
6495         mutex_unlock(&dev_priv->rps.hw_lock);
6496
6497         intel_update_cdclk(dev_priv);
6498 }
6499
6500 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6501                                  int max_pixclk)
6502 {
6503         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6504         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6505
6506         /*
6507          * Really only a few cases to deal with, as only 4 CDclks are supported:
6508          *   200MHz
6509          *   267MHz
6510          *   320/333MHz (depends on HPLL freq)
6511          *   400MHz (VLV only)
6512          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6513          * of the lower bin and adjust if needed.
6514          *
6515          * We seem to get an unstable or solid color picture at 200MHz.
6516          * Not sure what's wrong. For now use 200MHz only when all pipes
6517          * are off.
6518          */
6519         if (!IS_CHERRYVIEW(dev_priv) &&
6520             max_pixclk > freq_320*limit/100)
6521                 return 400000;
6522         else if (max_pixclk > 266667*limit/100)
6523                 return freq_320;
6524         else if (max_pixclk > 0)
6525                 return 266667;
6526         else
6527                 return 200000;
6528 }
6529
6530 static int bxt_calc_cdclk(int max_pixclk)
6531 {
6532         if (max_pixclk > 576000)
6533                 return 624000;
6534         else if (max_pixclk > 384000)
6535                 return 576000;
6536         else if (max_pixclk > 288000)
6537                 return 384000;
6538         else if (max_pixclk > 144000)
6539                 return 288000;
6540         else
6541                 return 144000;
6542 }
6543
6544 /* Compute the max pixel clock for new configuration. */
6545 static int intel_mode_max_pixclk(struct drm_device *dev,
6546                                  struct drm_atomic_state *state)
6547 {
6548         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6549         struct drm_i915_private *dev_priv = to_i915(dev);
6550         struct drm_crtc *crtc;
6551         struct drm_crtc_state *crtc_state;
6552         unsigned max_pixclk = 0, i;
6553         enum pipe pipe;
6554
6555         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6556                sizeof(intel_state->min_pixclk));
6557
6558         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6559                 int pixclk = 0;
6560
6561                 if (crtc_state->enable)
6562                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6563
6564                 intel_state->min_pixclk[i] = pixclk;
6565         }
6566
6567         for_each_pipe(dev_priv, pipe)
6568                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6569
6570         return max_pixclk;
6571 }
6572
6573 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6574 {
6575         struct drm_device *dev = state->dev;
6576         struct drm_i915_private *dev_priv = to_i915(dev);
6577         int max_pixclk = intel_mode_max_pixclk(dev, state);
6578         struct intel_atomic_state *intel_state =
6579                 to_intel_atomic_state(state);
6580
6581         intel_state->cdclk = intel_state->dev_cdclk =
6582                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6583
6584         if (!intel_state->active_crtcs)
6585                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6586
6587         return 0;
6588 }
6589
6590 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6591 {
6592         int max_pixclk = ilk_max_pixel_rate(state);
6593         struct intel_atomic_state *intel_state =
6594                 to_intel_atomic_state(state);
6595
6596         intel_state->cdclk = intel_state->dev_cdclk =
6597                 bxt_calc_cdclk(max_pixclk);
6598
6599         if (!intel_state->active_crtcs)
6600                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6601
6602         return 0;
6603 }
6604
6605 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6606 {
6607         unsigned int credits, default_credits;
6608
6609         if (IS_CHERRYVIEW(dev_priv))
6610                 default_credits = PFI_CREDIT(12);
6611         else
6612                 default_credits = PFI_CREDIT(8);
6613
6614         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6615                 /* CHV suggested value is 31 or 63 */
6616                 if (IS_CHERRYVIEW(dev_priv))
6617                         credits = PFI_CREDIT_63;
6618                 else
6619                         credits = PFI_CREDIT(15);
6620         } else {
6621                 credits = default_credits;
6622         }
6623
6624         /*
6625          * WA - write default credits before re-programming
6626          * FIXME: should we also set the resend bit here?
6627          */
6628         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6629                    default_credits);
6630
6631         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6632                    credits | PFI_CREDIT_RESEND);
6633
6634         /*
6635          * FIXME is this guaranteed to clear
6636          * immediately or should we poll for it?
6637          */
6638         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6639 }
6640
6641 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6642 {
6643         struct drm_device *dev = old_state->dev;
6644         struct drm_i915_private *dev_priv = to_i915(dev);
6645         struct intel_atomic_state *old_intel_state =
6646                 to_intel_atomic_state(old_state);
6647         unsigned req_cdclk = old_intel_state->dev_cdclk;
6648
6649         /*
6650          * FIXME: We can end up here with all power domains off, yet
6651          * with a CDCLK frequency other than the minimum. To account
6652          * for this take the PIPE-A power domain, which covers the HW
6653          * blocks needed for the following programming. This can be
6654          * removed once it's guaranteed that we get here either with
6655          * the minimum CDCLK set, or the required power domains
6656          * enabled.
6657          */
6658         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6659
6660         if (IS_CHERRYVIEW(dev_priv))
6661                 cherryview_set_cdclk(dev, req_cdclk);
6662         else
6663                 valleyview_set_cdclk(dev, req_cdclk);
6664
6665         vlv_program_pfi_credits(dev_priv);
6666
6667         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6668 }
6669
6670 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6671                                    struct drm_atomic_state *old_state)
6672 {
6673         struct drm_crtc *crtc = pipe_config->base.crtc;
6674         struct drm_device *dev = crtc->dev;
6675         struct drm_i915_private *dev_priv = to_i915(dev);
6676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6677         int pipe = intel_crtc->pipe;
6678
6679         if (WARN_ON(intel_crtc->active))
6680                 return;
6681
6682         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6683                 intel_dp_set_m_n(intel_crtc, M1_N1);
6684
6685         intel_set_pipe_timings(intel_crtc);
6686         intel_set_pipe_src_size(intel_crtc);
6687
6688         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6689                 struct drm_i915_private *dev_priv = to_i915(dev);
6690
6691                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6692                 I915_WRITE(CHV_CANVAS(pipe), 0);
6693         }
6694
6695         i9xx_set_pipeconf(intel_crtc);
6696
6697         intel_crtc->active = true;
6698
6699         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6700
6701         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6702
6703         if (IS_CHERRYVIEW(dev_priv)) {
6704                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6705                 chv_enable_pll(intel_crtc, intel_crtc->config);
6706         } else {
6707                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6708                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6709         }
6710
6711         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6712
6713         i9xx_pfit_enable(intel_crtc);
6714
6715         intel_color_load_luts(&pipe_config->base);
6716
6717         intel_update_watermarks(intel_crtc);
6718         intel_enable_pipe(intel_crtc);
6719
6720         assert_vblank_disabled(crtc);
6721         drm_crtc_vblank_on(crtc);
6722
6723         intel_encoders_enable(crtc, pipe_config, old_state);
6724 }
6725
6726 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6727 {
6728         struct drm_device *dev = crtc->base.dev;
6729         struct drm_i915_private *dev_priv = to_i915(dev);
6730
6731         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6732         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6733 }
6734
6735 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6736                              struct drm_atomic_state *old_state)
6737 {
6738         struct drm_crtc *crtc = pipe_config->base.crtc;
6739         struct drm_device *dev = crtc->dev;
6740         struct drm_i915_private *dev_priv = to_i915(dev);
6741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6742         enum pipe pipe = intel_crtc->pipe;
6743
6744         if (WARN_ON(intel_crtc->active))
6745                 return;
6746
6747         i9xx_set_pll_dividers(intel_crtc);
6748
6749         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6750                 intel_dp_set_m_n(intel_crtc, M1_N1);
6751
6752         intel_set_pipe_timings(intel_crtc);
6753         intel_set_pipe_src_size(intel_crtc);
6754
6755         i9xx_set_pipeconf(intel_crtc);
6756
6757         intel_crtc->active = true;
6758
6759         if (!IS_GEN2(dev_priv))
6760                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6761
6762         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6763
6764         i9xx_enable_pll(intel_crtc);
6765
6766         i9xx_pfit_enable(intel_crtc);
6767
6768         intel_color_load_luts(&pipe_config->base);
6769
6770         intel_update_watermarks(intel_crtc);
6771         intel_enable_pipe(intel_crtc);
6772
6773         assert_vblank_disabled(crtc);
6774         drm_crtc_vblank_on(crtc);
6775
6776         intel_encoders_enable(crtc, pipe_config, old_state);
6777 }
6778
6779 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6780 {
6781         struct drm_device *dev = crtc->base.dev;
6782         struct drm_i915_private *dev_priv = to_i915(dev);
6783
6784         if (!crtc->config->gmch_pfit.control)
6785                 return;
6786
6787         assert_pipe_disabled(dev_priv, crtc->pipe);
6788
6789         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6790                          I915_READ(PFIT_CONTROL));
6791         I915_WRITE(PFIT_CONTROL, 0);
6792 }
6793
6794 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6795                               struct drm_atomic_state *old_state)
6796 {
6797         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6798         struct drm_device *dev = crtc->dev;
6799         struct drm_i915_private *dev_priv = to_i915(dev);
6800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6801         int pipe = intel_crtc->pipe;
6802
6803         /*
6804          * On gen2 planes are double buffered but the pipe isn't, so we must
6805          * wait for planes to fully turn off before disabling the pipe.
6806          */
6807         if (IS_GEN2(dev_priv))
6808                 intel_wait_for_vblank(dev_priv, pipe);
6809
6810         intel_encoders_disable(crtc, old_crtc_state, old_state);
6811
6812         drm_crtc_vblank_off(crtc);
6813         assert_vblank_disabled(crtc);
6814
6815         intel_disable_pipe(intel_crtc);
6816
6817         i9xx_pfit_disable(intel_crtc);
6818
6819         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6820
6821         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6822                 if (IS_CHERRYVIEW(dev_priv))
6823                         chv_disable_pll(dev_priv, pipe);
6824                 else if (IS_VALLEYVIEW(dev_priv))
6825                         vlv_disable_pll(dev_priv, pipe);
6826                 else
6827                         i9xx_disable_pll(intel_crtc);
6828         }
6829
6830         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6831
6832         if (!IS_GEN2(dev_priv))
6833                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6834 }
6835
6836 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6837 {
6838         struct intel_encoder *encoder;
6839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6840         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6841         enum intel_display_power_domain domain;
6842         unsigned long domains;
6843         struct drm_atomic_state *state;
6844         struct intel_crtc_state *crtc_state;
6845         int ret;
6846
6847         if (!intel_crtc->active)
6848                 return;
6849
6850         if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6851                 WARN_ON(intel_crtc->flip_work);
6852
6853                 intel_pre_disable_primary_noatomic(crtc);
6854
6855                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6856                 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6857         }
6858
6859         state = drm_atomic_state_alloc(crtc->dev);
6860         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6861
6862         /* Everything's already locked, -EDEADLK can't happen. */
6863         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6864         ret = drm_atomic_add_affected_connectors(state, crtc);
6865
6866         WARN_ON(IS_ERR(crtc_state) || ret);
6867
6868         dev_priv->display.crtc_disable(crtc_state, state);
6869
6870         drm_atomic_state_put(state);
6871
6872         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6873                       crtc->base.id, crtc->name);
6874
6875         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6876         crtc->state->active = false;
6877         intel_crtc->active = false;
6878         crtc->enabled = false;
6879         crtc->state->connector_mask = 0;
6880         crtc->state->encoder_mask = 0;
6881
6882         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6883                 encoder->base.crtc = NULL;
6884
6885         intel_fbc_disable(intel_crtc);
6886         intel_update_watermarks(intel_crtc);
6887         intel_disable_shared_dpll(intel_crtc);
6888
6889         domains = intel_crtc->enabled_power_domains;
6890         for_each_power_domain(domain, domains)
6891                 intel_display_power_put(dev_priv, domain);
6892         intel_crtc->enabled_power_domains = 0;
6893
6894         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6895         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6896 }
6897
6898 /*
6899  * turn all crtc's off, but do not adjust state
6900  * This has to be paired with a call to intel_modeset_setup_hw_state.
6901  */
6902 int intel_display_suspend(struct drm_device *dev)
6903 {
6904         struct drm_i915_private *dev_priv = to_i915(dev);
6905         struct drm_atomic_state *state;
6906         int ret;
6907
6908         state = drm_atomic_helper_suspend(dev);
6909         ret = PTR_ERR_OR_ZERO(state);
6910         if (ret)
6911                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6912         else
6913                 dev_priv->modeset_restore_state = state;
6914         return ret;
6915 }
6916
6917 void intel_encoder_destroy(struct drm_encoder *encoder)
6918 {
6919         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6920
6921         drm_encoder_cleanup(encoder);
6922         kfree(intel_encoder);
6923 }
6924
6925 /* Cross check the actual hw state with our own modeset state tracking (and it's
6926  * internal consistency). */
6927 static void intel_connector_verify_state(struct intel_connector *connector)
6928 {
6929         struct drm_crtc *crtc = connector->base.state->crtc;
6930
6931         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6932                       connector->base.base.id,
6933                       connector->base.name);
6934
6935         if (connector->get_hw_state(connector)) {
6936                 struct intel_encoder *encoder = connector->encoder;
6937                 struct drm_connector_state *conn_state = connector->base.state;
6938
6939                 I915_STATE_WARN(!crtc,
6940                          "connector enabled without attached crtc\n");
6941
6942                 if (!crtc)
6943                         return;
6944
6945                 I915_STATE_WARN(!crtc->state->active,
6946                       "connector is active, but attached crtc isn't\n");
6947
6948                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6949                         return;
6950
6951                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6952                         "atomic encoder doesn't match attached encoder\n");
6953
6954                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6955                         "attached encoder crtc differs from connector crtc\n");
6956         } else {
6957                 I915_STATE_WARN(crtc && crtc->state->active,
6958                         "attached crtc is active, but connector isn't\n");
6959                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6960                         "best encoder set without crtc!\n");
6961         }
6962 }
6963
6964 int intel_connector_init(struct intel_connector *connector)
6965 {
6966         drm_atomic_helper_connector_reset(&connector->base);
6967
6968         if (!connector->base.state)
6969                 return -ENOMEM;
6970
6971         return 0;
6972 }
6973
6974 struct intel_connector *intel_connector_alloc(void)
6975 {
6976         struct intel_connector *connector;
6977
6978         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6979         if (!connector)
6980                 return NULL;
6981
6982         if (intel_connector_init(connector) < 0) {
6983                 kfree(connector);
6984                 return NULL;
6985         }
6986
6987         return connector;
6988 }
6989
6990 /* Simple connector->get_hw_state implementation for encoders that support only
6991  * one connector and no cloning and hence the encoder state determines the state
6992  * of the connector. */
6993 bool intel_connector_get_hw_state(struct intel_connector *connector)
6994 {
6995         enum pipe pipe = 0;
6996         struct intel_encoder *encoder = connector->encoder;
6997
6998         return encoder->get_hw_state(encoder, &pipe);
6999 }
7000
7001 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7002 {
7003         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7004                 return crtc_state->fdi_lanes;
7005
7006         return 0;
7007 }
7008
7009 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7010                                      struct intel_crtc_state *pipe_config)
7011 {
7012         struct drm_i915_private *dev_priv = to_i915(dev);
7013         struct drm_atomic_state *state = pipe_config->base.state;
7014         struct intel_crtc *other_crtc;
7015         struct intel_crtc_state *other_crtc_state;
7016
7017         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7018                       pipe_name(pipe), pipe_config->fdi_lanes);
7019         if (pipe_config->fdi_lanes > 4) {
7020                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7021                               pipe_name(pipe), pipe_config->fdi_lanes);
7022                 return -EINVAL;
7023         }
7024
7025         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7026                 if (pipe_config->fdi_lanes > 2) {
7027                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7028                                       pipe_config->fdi_lanes);
7029                         return -EINVAL;
7030                 } else {
7031                         return 0;
7032                 }
7033         }
7034
7035         if (INTEL_INFO(dev_priv)->num_pipes == 2)
7036                 return 0;
7037
7038         /* Ivybridge 3 pipe is really complicated */
7039         switch (pipe) {
7040         case PIPE_A:
7041                 return 0;
7042         case PIPE_B:
7043                 if (pipe_config->fdi_lanes <= 2)
7044                         return 0;
7045
7046                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7047                 other_crtc_state =
7048                         intel_atomic_get_crtc_state(state, other_crtc);
7049                 if (IS_ERR(other_crtc_state))
7050                         return PTR_ERR(other_crtc_state);
7051
7052                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7053                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7054                                       pipe_name(pipe), pipe_config->fdi_lanes);
7055                         return -EINVAL;
7056                 }
7057                 return 0;
7058         case PIPE_C:
7059                 if (pipe_config->fdi_lanes > 2) {
7060                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7061                                       pipe_name(pipe), pipe_config->fdi_lanes);
7062                         return -EINVAL;
7063                 }
7064
7065                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7066                 other_crtc_state =
7067                         intel_atomic_get_crtc_state(state, other_crtc);
7068                 if (IS_ERR(other_crtc_state))
7069                         return PTR_ERR(other_crtc_state);
7070
7071                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7072                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7073                         return -EINVAL;
7074                 }
7075                 return 0;
7076         default:
7077                 BUG();
7078         }
7079 }
7080
7081 #define RETRY 1
7082 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7083                                        struct intel_crtc_state *pipe_config)
7084 {
7085         struct drm_device *dev = intel_crtc->base.dev;
7086         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7087         int lane, link_bw, fdi_dotclock, ret;
7088         bool needs_recompute = false;
7089
7090 retry:
7091         /* FDI is a binary signal running at ~2.7GHz, encoding
7092          * each output octet as 10 bits. The actual frequency
7093          * is stored as a divider into a 100MHz clock, and the
7094          * mode pixel clock is stored in units of 1KHz.
7095          * Hence the bw of each lane in terms of the mode signal
7096          * is:
7097          */
7098         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7099
7100         fdi_dotclock = adjusted_mode->crtc_clock;
7101
7102         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7103                                            pipe_config->pipe_bpp);
7104
7105         pipe_config->fdi_lanes = lane;
7106
7107         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7108                                link_bw, &pipe_config->fdi_m_n);
7109
7110         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7111         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7112                 pipe_config->pipe_bpp -= 2*3;
7113                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7114                               pipe_config->pipe_bpp);
7115                 needs_recompute = true;
7116                 pipe_config->bw_constrained = true;
7117
7118                 goto retry;
7119         }
7120
7121         if (needs_recompute)
7122                 return RETRY;
7123
7124         return ret;
7125 }
7126
7127 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7128                                      struct intel_crtc_state *pipe_config)
7129 {
7130         if (pipe_config->pipe_bpp > 24)
7131                 return false;
7132
7133         /* HSW can handle pixel rate up to cdclk? */
7134         if (IS_HASWELL(dev_priv))
7135                 return true;
7136
7137         /*
7138          * We compare against max which means we must take
7139          * the increased cdclk requirement into account when
7140          * calculating the new cdclk.
7141          *
7142          * Should measure whether using a lower cdclk w/o IPS
7143          */
7144         return ilk_pipe_pixel_rate(pipe_config) <=
7145                 dev_priv->max_cdclk_freq * 95 / 100;
7146 }
7147
7148 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7149                                    struct intel_crtc_state *pipe_config)
7150 {
7151         struct drm_device *dev = crtc->base.dev;
7152         struct drm_i915_private *dev_priv = to_i915(dev);
7153
7154         pipe_config->ips_enabled = i915.enable_ips &&
7155                 hsw_crtc_supports_ips(crtc) &&
7156                 pipe_config_supports_ips(dev_priv, pipe_config);
7157 }
7158
7159 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7160 {
7161         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7162
7163         /* GDG double wide on either pipe, otherwise pipe A only */
7164         return INTEL_INFO(dev_priv)->gen < 4 &&
7165                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7166 }
7167
7168 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7169                                      struct intel_crtc_state *pipe_config)
7170 {
7171         struct drm_device *dev = crtc->base.dev;
7172         struct drm_i915_private *dev_priv = to_i915(dev);
7173         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7174         int clock_limit = dev_priv->max_dotclk_freq;
7175
7176         if (INTEL_GEN(dev_priv) < 4) {
7177                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7178
7179                 /*
7180                  * Enable double wide mode when the dot clock
7181                  * is > 90% of the (display) core speed.
7182                  */
7183                 if (intel_crtc_supports_double_wide(crtc) &&
7184                     adjusted_mode->crtc_clock > clock_limit) {
7185                         clock_limit = dev_priv->max_dotclk_freq;
7186                         pipe_config->double_wide = true;
7187                 }
7188         }
7189
7190         if (adjusted_mode->crtc_clock > clock_limit) {
7191                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7192                               adjusted_mode->crtc_clock, clock_limit,
7193                               yesno(pipe_config->double_wide));
7194                 return -EINVAL;
7195         }
7196
7197         /*
7198          * Pipe horizontal size must be even in:
7199          * - DVO ganged mode
7200          * - LVDS dual channel mode
7201          * - Double wide pipe
7202          */
7203         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7204              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7205                 pipe_config->pipe_src_w &= ~1;
7206
7207         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7208          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7209          */
7210         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7211                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7212                 return -EINVAL;
7213
7214         if (HAS_IPS(dev_priv))
7215                 hsw_compute_ips_config(crtc, pipe_config);
7216
7217         if (pipe_config->has_pch_encoder)
7218                 return ironlake_fdi_compute_config(crtc, pipe_config);
7219
7220         return 0;
7221 }
7222
7223 static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv)
7224 {
7225         u32 cdctl;
7226
7227         skl_dpll0_update(dev_priv);
7228
7229         if (dev_priv->cdclk_pll.vco == 0)
7230                 return dev_priv->cdclk_pll.ref;
7231
7232         cdctl = I915_READ(CDCLK_CTL);
7233
7234         if (dev_priv->cdclk_pll.vco == 8640000) {
7235                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7236                 case CDCLK_FREQ_450_432:
7237                         return 432000;
7238                 case CDCLK_FREQ_337_308:
7239                         return 308571;
7240                 case CDCLK_FREQ_540:
7241                         return 540000;
7242                 case CDCLK_FREQ_675_617:
7243                         return 617143;
7244                 default:
7245                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7246                 }
7247         } else {
7248                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7249                 case CDCLK_FREQ_450_432:
7250                         return 450000;
7251                 case CDCLK_FREQ_337_308:
7252                         return 337500;
7253                 case CDCLK_FREQ_540:
7254                         return 540000;
7255                 case CDCLK_FREQ_675_617:
7256                         return 675000;
7257                 default:
7258                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7259                 }
7260         }
7261
7262         return dev_priv->cdclk_pll.ref;
7263 }
7264
7265 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7266 {
7267         u32 val;
7268
7269         dev_priv->cdclk_pll.ref = 19200;
7270         dev_priv->cdclk_pll.vco = 0;
7271
7272         val = I915_READ(BXT_DE_PLL_ENABLE);
7273         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7274                 return;
7275
7276         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7277                 return;
7278
7279         val = I915_READ(BXT_DE_PLL_CTL);
7280         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7281                 dev_priv->cdclk_pll.ref;
7282 }
7283
7284 static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
7285 {
7286         u32 divider;
7287         int div, vco;
7288
7289         bxt_de_pll_update(dev_priv);
7290
7291         vco = dev_priv->cdclk_pll.vco;
7292         if (vco == 0)
7293                 return dev_priv->cdclk_pll.ref;
7294
7295         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7296
7297         switch (divider) {
7298         case BXT_CDCLK_CD2X_DIV_SEL_1:
7299                 div = 2;
7300                 break;
7301         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7302                 div = 3;
7303                 break;
7304         case BXT_CDCLK_CD2X_DIV_SEL_2:
7305                 div = 4;
7306                 break;
7307         case BXT_CDCLK_CD2X_DIV_SEL_4:
7308                 div = 8;
7309                 break;
7310         default:
7311                 MISSING_CASE(divider);
7312                 return dev_priv->cdclk_pll.ref;
7313         }
7314
7315         return DIV_ROUND_CLOSEST(vco, div);
7316 }
7317
7318 static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7319 {
7320         uint32_t lcpll = I915_READ(LCPLL_CTL);
7321         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7322
7323         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7324                 return 800000;
7325         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7326                 return 450000;
7327         else if (freq == LCPLL_CLK_FREQ_450)
7328                 return 450000;
7329         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7330                 return 540000;
7331         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7332                 return 337500;
7333         else
7334                 return 675000;
7335 }
7336
7337 static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7338 {
7339         uint32_t lcpll = I915_READ(LCPLL_CTL);
7340         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7341
7342         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7343                 return 800000;
7344         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7345                 return 450000;
7346         else if (freq == LCPLL_CLK_FREQ_450)
7347                 return 450000;
7348         else if (IS_HSW_ULT(dev_priv))
7349                 return 337500;
7350         else
7351                 return 540000;
7352 }
7353
7354 static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv)
7355 {
7356         return vlv_get_cck_clock_hpll(dev_priv, "cdclk",
7357                                       CCK_DISPLAY_CLOCK_CONTROL);
7358 }
7359
7360 static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv)
7361 {
7362         return 450000;
7363 }
7364
7365 static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv)
7366 {
7367         return 400000;
7368 }
7369
7370 static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv)
7371 {
7372         return 333333;
7373 }
7374
7375 static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv)
7376 {
7377         return 200000;
7378 }
7379
7380 static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv)
7381 {
7382         struct pci_dev *pdev = dev_priv->drm.pdev;
7383         u16 gcfgc = 0;
7384
7385         pci_read_config_word(pdev, GCFGC, &gcfgc);
7386
7387         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7388         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7389                 return 266667;
7390         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7391                 return 333333;
7392         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7393                 return 444444;
7394         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7395                 return 200000;
7396         default:
7397                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7398         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7399                 return 133333;
7400         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7401                 return 166667;
7402         }
7403 }
7404
7405 static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7406 {
7407         struct pci_dev *pdev = dev_priv->drm.pdev;
7408         u16 gcfgc = 0;
7409
7410         pci_read_config_word(pdev, GCFGC, &gcfgc);
7411
7412         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7413                 return 133333;
7414         else {
7415                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7416                 case GC_DISPLAY_CLOCK_333_MHZ:
7417                         return 333333;
7418                 default:
7419                 case GC_DISPLAY_CLOCK_190_200_MHZ:
7420                         return 190000;
7421                 }
7422         }
7423 }
7424
7425 static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv)
7426 {
7427         return 266667;
7428 }
7429
7430 static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv)
7431 {
7432         struct pci_dev *pdev = dev_priv->drm.pdev;
7433         u16 hpllcc = 0;
7434
7435         /*
7436          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7437          * encoding is different :(
7438          * FIXME is this the right way to detect 852GM/852GMV?
7439          */
7440         if (pdev->revision == 0x1)
7441                 return 133333;
7442
7443         pci_bus_read_config_word(pdev->bus,
7444                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7445
7446         /* Assume that the hardware is in the high speed state.  This
7447          * should be the default.
7448          */
7449         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7450         case GC_CLOCK_133_200:
7451         case GC_CLOCK_133_200_2:
7452         case GC_CLOCK_100_200:
7453                 return 200000;
7454         case GC_CLOCK_166_250:
7455                 return 250000;
7456         case GC_CLOCK_100_133:
7457                 return 133333;
7458         case GC_CLOCK_133_266:
7459         case GC_CLOCK_133_266_2:
7460         case GC_CLOCK_166_266:
7461                 return 266667;
7462         }
7463
7464         /* Shouldn't happen */
7465         return 0;
7466 }
7467
7468 static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv)
7469 {
7470         return 133333;
7471 }
7472
7473 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
7474 {
7475         static const unsigned int blb_vco[8] = {
7476                 [0] = 3200000,
7477                 [1] = 4000000,
7478                 [2] = 5333333,
7479                 [3] = 4800000,
7480                 [4] = 6400000,
7481         };
7482         static const unsigned int pnv_vco[8] = {
7483                 [0] = 3200000,
7484                 [1] = 4000000,
7485                 [2] = 5333333,
7486                 [3] = 4800000,
7487                 [4] = 2666667,
7488         };
7489         static const unsigned int cl_vco[8] = {
7490                 [0] = 3200000,
7491                 [1] = 4000000,
7492                 [2] = 5333333,
7493                 [3] = 6400000,
7494                 [4] = 3333333,
7495                 [5] = 3566667,
7496                 [6] = 4266667,
7497         };
7498         static const unsigned int elk_vco[8] = {
7499                 [0] = 3200000,
7500                 [1] = 4000000,
7501                 [2] = 5333333,
7502                 [3] = 4800000,
7503         };
7504         static const unsigned int ctg_vco[8] = {
7505                 [0] = 3200000,
7506                 [1] = 4000000,
7507                 [2] = 5333333,
7508                 [3] = 6400000,
7509                 [4] = 2666667,
7510                 [5] = 4266667,
7511         };
7512         const unsigned int *vco_table;
7513         unsigned int vco;
7514         uint8_t tmp = 0;
7515
7516         /* FIXME other chipsets? */
7517         if (IS_GM45(dev_priv))
7518                 vco_table = ctg_vco;
7519         else if (IS_G4X(dev_priv))
7520                 vco_table = elk_vco;
7521         else if (IS_CRESTLINE(dev_priv))
7522                 vco_table = cl_vco;
7523         else if (IS_PINEVIEW(dev_priv))
7524                 vco_table = pnv_vco;
7525         else if (IS_G33(dev_priv))
7526                 vco_table = blb_vco;
7527         else
7528                 return 0;
7529
7530         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
7531
7532         vco = vco_table[tmp & 0x7];
7533         if (vco == 0)
7534                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7535         else
7536                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7537
7538         return vco;
7539 }
7540
7541 static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv)
7542 {
7543         struct pci_dev *pdev = dev_priv->drm.pdev;
7544         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7545         uint16_t tmp = 0;
7546
7547         pci_read_config_word(pdev, GCFGC, &tmp);
7548
7549         cdclk_sel = (tmp >> 12) & 0x1;
7550
7551         switch (vco) {
7552         case 2666667:
7553         case 4000000:
7554         case 5333333:
7555                 return cdclk_sel ? 333333 : 222222;
7556         case 3200000:
7557                 return cdclk_sel ? 320000 : 228571;
7558         default:
7559                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7560                 return 222222;
7561         }
7562 }
7563
7564 static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7565 {
7566         struct pci_dev *pdev = dev_priv->drm.pdev;
7567         static const uint8_t div_3200[] = { 16, 10,  8 };
7568         static const uint8_t div_4000[] = { 20, 12, 10 };
7569         static const uint8_t div_5333[] = { 24, 16, 14 };
7570         const uint8_t *div_table;
7571         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7572         uint16_t tmp = 0;
7573
7574         pci_read_config_word(pdev, GCFGC, &tmp);
7575
7576         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7577
7578         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7579                 goto fail;
7580
7581         switch (vco) {
7582         case 3200000:
7583                 div_table = div_3200;
7584                 break;
7585         case 4000000:
7586                 div_table = div_4000;
7587                 break;
7588         case 5333333:
7589                 div_table = div_5333;
7590                 break;
7591         default:
7592                 goto fail;
7593         }
7594
7595         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7596
7597 fail:
7598         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7599         return 200000;
7600 }
7601
7602 static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv)
7603 {
7604         struct pci_dev *pdev = dev_priv->drm.pdev;
7605         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7606         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7607         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7608         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7609         const uint8_t *div_table;
7610         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7611         uint16_t tmp = 0;
7612
7613         pci_read_config_word(pdev, GCFGC, &tmp);
7614
7615         cdclk_sel = (tmp >> 4) & 0x7;
7616
7617         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7618                 goto fail;
7619
7620         switch (vco) {
7621         case 3200000:
7622                 div_table = div_3200;
7623                 break;
7624         case 4000000:
7625                 div_table = div_4000;
7626                 break;
7627         case 4800000:
7628                 div_table = div_4800;
7629                 break;
7630         case 5333333:
7631                 div_table = div_5333;
7632                 break;
7633         default:
7634                 goto fail;
7635         }
7636
7637         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7638
7639 fail:
7640         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7641         return 190476;
7642 }
7643
7644 static void
7645 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7646 {
7647         while (*num > DATA_LINK_M_N_MASK ||
7648                *den > DATA_LINK_M_N_MASK) {
7649                 *num >>= 1;
7650                 *den >>= 1;
7651         }
7652 }
7653
7654 static void compute_m_n(unsigned int m, unsigned int n,
7655                         uint32_t *ret_m, uint32_t *ret_n)
7656 {
7657         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7658         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7659         intel_reduce_m_n_ratio(ret_m, ret_n);
7660 }
7661
7662 void
7663 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7664                        int pixel_clock, int link_clock,
7665                        struct intel_link_m_n *m_n)
7666 {
7667         m_n->tu = 64;
7668
7669         compute_m_n(bits_per_pixel * pixel_clock,
7670                     link_clock * nlanes * 8,
7671                     &m_n->gmch_m, &m_n->gmch_n);
7672
7673         compute_m_n(pixel_clock, link_clock,
7674                     &m_n->link_m, &m_n->link_n);
7675 }
7676
7677 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7678 {
7679         if (i915.panel_use_ssc >= 0)
7680                 return i915.panel_use_ssc != 0;
7681         return dev_priv->vbt.lvds_use_ssc
7682                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7683 }
7684
7685 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7686 {
7687         return (1 << dpll->n) << 16 | dpll->m2;
7688 }
7689
7690 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7691 {
7692         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7693 }
7694
7695 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7696                                      struct intel_crtc_state *crtc_state,
7697                                      struct dpll *reduced_clock)
7698 {
7699         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7700         u32 fp, fp2 = 0;
7701
7702         if (IS_PINEVIEW(dev_priv)) {
7703                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7704                 if (reduced_clock)
7705                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7706         } else {
7707                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7708                 if (reduced_clock)
7709                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7710         }
7711
7712         crtc_state->dpll_hw_state.fp0 = fp;
7713
7714         crtc->lowfreq_avail = false;
7715         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7716             reduced_clock) {
7717                 crtc_state->dpll_hw_state.fp1 = fp2;
7718                 crtc->lowfreq_avail = true;
7719         } else {
7720                 crtc_state->dpll_hw_state.fp1 = fp;
7721         }
7722 }
7723
7724 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7725                 pipe)
7726 {
7727         u32 reg_val;
7728
7729         /*
7730          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7731          * and set it to a reasonable value instead.
7732          */
7733         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7734         reg_val &= 0xffffff00;
7735         reg_val |= 0x00000030;
7736         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7737
7738         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7739         reg_val &= 0x8cffffff;
7740         reg_val = 0x8c000000;
7741         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7742
7743         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7744         reg_val &= 0xffffff00;
7745         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7746
7747         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7748         reg_val &= 0x00ffffff;
7749         reg_val |= 0xb0000000;
7750         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7751 }
7752
7753 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7754                                          struct intel_link_m_n *m_n)
7755 {
7756         struct drm_device *dev = crtc->base.dev;
7757         struct drm_i915_private *dev_priv = to_i915(dev);
7758         int pipe = crtc->pipe;
7759
7760         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7761         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7762         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7763         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7764 }
7765
7766 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7767                                          struct intel_link_m_n *m_n,
7768                                          struct intel_link_m_n *m2_n2)
7769 {
7770         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7771         int pipe = crtc->pipe;
7772         enum transcoder transcoder = crtc->config->cpu_transcoder;
7773
7774         if (INTEL_GEN(dev_priv) >= 5) {
7775                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7776                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7777                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7778                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7779                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7780                  * for gen < 8) and if DRRS is supported (to make sure the
7781                  * registers are not unnecessarily accessed).
7782                  */
7783                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
7784                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
7785                         I915_WRITE(PIPE_DATA_M2(transcoder),
7786                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7787                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7788                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7789                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7790                 }
7791         } else {
7792                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7793                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7794                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7795                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7796         }
7797 }
7798
7799 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7800 {
7801         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7802
7803         if (m_n == M1_N1) {
7804                 dp_m_n = &crtc->config->dp_m_n;
7805                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7806         } else if (m_n == M2_N2) {
7807
7808                 /*
7809                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7810                  * needs to be programmed into M1_N1.
7811                  */
7812                 dp_m_n = &crtc->config->dp_m2_n2;
7813         } else {
7814                 DRM_ERROR("Unsupported divider value\n");
7815                 return;
7816         }
7817
7818         if (crtc->config->has_pch_encoder)
7819                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7820         else
7821                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7822 }
7823
7824 static void vlv_compute_dpll(struct intel_crtc *crtc,
7825                              struct intel_crtc_state *pipe_config)
7826 {
7827         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7828                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7829         if (crtc->pipe != PIPE_A)
7830                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7831
7832         /* DPLL not used with DSI, but still need the rest set up */
7833         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7834                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7835                         DPLL_EXT_BUFFER_ENABLE_VLV;
7836
7837         pipe_config->dpll_hw_state.dpll_md =
7838                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7839 }
7840
7841 static void chv_compute_dpll(struct intel_crtc *crtc,
7842                              struct intel_crtc_state *pipe_config)
7843 {
7844         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7845                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7846         if (crtc->pipe != PIPE_A)
7847                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7848
7849         /* DPLL not used with DSI, but still need the rest set up */
7850         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7851                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7852
7853         pipe_config->dpll_hw_state.dpll_md =
7854                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7855 }
7856
7857 static void vlv_prepare_pll(struct intel_crtc *crtc,
7858                             const struct intel_crtc_state *pipe_config)
7859 {
7860         struct drm_device *dev = crtc->base.dev;
7861         struct drm_i915_private *dev_priv = to_i915(dev);
7862         enum pipe pipe = crtc->pipe;
7863         u32 mdiv;
7864         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7865         u32 coreclk, reg_val;
7866
7867         /* Enable Refclk */
7868         I915_WRITE(DPLL(pipe),
7869                    pipe_config->dpll_hw_state.dpll &
7870                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7871
7872         /* No need to actually set up the DPLL with DSI */
7873         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7874                 return;
7875
7876         mutex_lock(&dev_priv->sb_lock);
7877
7878         bestn = pipe_config->dpll.n;
7879         bestm1 = pipe_config->dpll.m1;
7880         bestm2 = pipe_config->dpll.m2;
7881         bestp1 = pipe_config->dpll.p1;
7882         bestp2 = pipe_config->dpll.p2;
7883
7884         /* See eDP HDMI DPIO driver vbios notes doc */
7885
7886         /* PLL B needs special handling */
7887         if (pipe == PIPE_B)
7888                 vlv_pllb_recal_opamp(dev_priv, pipe);
7889
7890         /* Set up Tx target for periodic Rcomp update */
7891         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7892
7893         /* Disable target IRef on PLL */
7894         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7895         reg_val &= 0x00ffffff;
7896         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7897
7898         /* Disable fast lock */
7899         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7900
7901         /* Set idtafcrecal before PLL is enabled */
7902         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7903         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7904         mdiv |= ((bestn << DPIO_N_SHIFT));
7905         mdiv |= (1 << DPIO_K_SHIFT);
7906
7907         /*
7908          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7909          * but we don't support that).
7910          * Note: don't use the DAC post divider as it seems unstable.
7911          */
7912         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7913         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7914
7915         mdiv |= DPIO_ENABLE_CALIBRATION;
7916         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7917
7918         /* Set HBR and RBR LPF coefficients */
7919         if (pipe_config->port_clock == 162000 ||
7920             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7921             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7922                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7923                                  0x009f0003);
7924         else
7925                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7926                                  0x00d0000f);
7927
7928         if (intel_crtc_has_dp_encoder(pipe_config)) {
7929                 /* Use SSC source */
7930                 if (pipe == PIPE_A)
7931                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7932                                          0x0df40000);
7933                 else
7934                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7935                                          0x0df70000);
7936         } else { /* HDMI or VGA */
7937                 /* Use bend source */
7938                 if (pipe == PIPE_A)
7939                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7940                                          0x0df70000);
7941                 else
7942                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7943                                          0x0df40000);
7944         }
7945
7946         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7947         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7948         if (intel_crtc_has_dp_encoder(crtc->config))
7949                 coreclk |= 0x01000000;
7950         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7951
7952         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7953         mutex_unlock(&dev_priv->sb_lock);
7954 }
7955
7956 static void chv_prepare_pll(struct intel_crtc *crtc,
7957                             const struct intel_crtc_state *pipe_config)
7958 {
7959         struct drm_device *dev = crtc->base.dev;
7960         struct drm_i915_private *dev_priv = to_i915(dev);
7961         enum pipe pipe = crtc->pipe;
7962         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7963         u32 loopfilter, tribuf_calcntr;
7964         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7965         u32 dpio_val;
7966         int vco;
7967
7968         /* Enable Refclk and SSC */
7969         I915_WRITE(DPLL(pipe),
7970                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7971
7972         /* No need to actually set up the DPLL with DSI */
7973         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7974                 return;
7975
7976         bestn = pipe_config->dpll.n;
7977         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7978         bestm1 = pipe_config->dpll.m1;
7979         bestm2 = pipe_config->dpll.m2 >> 22;
7980         bestp1 = pipe_config->dpll.p1;
7981         bestp2 = pipe_config->dpll.p2;
7982         vco = pipe_config->dpll.vco;
7983         dpio_val = 0;
7984         loopfilter = 0;
7985
7986         mutex_lock(&dev_priv->sb_lock);
7987
7988         /* p1 and p2 divider */
7989         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7990                         5 << DPIO_CHV_S1_DIV_SHIFT |
7991                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7992                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7993                         1 << DPIO_CHV_K_DIV_SHIFT);
7994
7995         /* Feedback post-divider - m2 */
7996         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7997
7998         /* Feedback refclk divider - n and m1 */
7999         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8000                         DPIO_CHV_M1_DIV_BY_2 |
8001                         1 << DPIO_CHV_N_DIV_SHIFT);
8002
8003         /* M2 fraction division */
8004         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8005
8006         /* M2 fraction division enable */
8007         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8008         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8009         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8010         if (bestm2_frac)
8011                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8012         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8013
8014         /* Program digital lock detect threshold */
8015         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8016         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8017                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8018         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8019         if (!bestm2_frac)
8020                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8021         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8022
8023         /* Loop filter */
8024         if (vco == 5400000) {
8025                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8026                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8027                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8028                 tribuf_calcntr = 0x9;
8029         } else if (vco <= 6200000) {
8030                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8031                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8032                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8033                 tribuf_calcntr = 0x9;
8034         } else if (vco <= 6480000) {
8035                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8036                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8037                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8038                 tribuf_calcntr = 0x8;
8039         } else {
8040                 /* Not supported. Apply the same limits as in the max case */
8041                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8042                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8043                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8044                 tribuf_calcntr = 0;
8045         }
8046         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8047
8048         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8049         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8050         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8051         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8052
8053         /* AFC Recal */
8054         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8055                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8056                         DPIO_AFC_RECAL);
8057
8058         mutex_unlock(&dev_priv->sb_lock);
8059 }
8060
8061 /**
8062  * vlv_force_pll_on - forcibly enable just the PLL
8063  * @dev_priv: i915 private structure
8064  * @pipe: pipe PLL to enable
8065  * @dpll: PLL configuration
8066  *
8067  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8068  * in cases where we need the PLL enabled even when @pipe is not going to
8069  * be enabled.
8070  */
8071 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8072                      const struct dpll *dpll)
8073 {
8074         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8075         struct intel_crtc_state *pipe_config;
8076
8077         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8078         if (!pipe_config)
8079                 return -ENOMEM;
8080
8081         pipe_config->base.crtc = &crtc->base;
8082         pipe_config->pixel_multiplier = 1;
8083         pipe_config->dpll = *dpll;
8084
8085         if (IS_CHERRYVIEW(dev_priv)) {
8086                 chv_compute_dpll(crtc, pipe_config);
8087                 chv_prepare_pll(crtc, pipe_config);
8088                 chv_enable_pll(crtc, pipe_config);
8089         } else {
8090                 vlv_compute_dpll(crtc, pipe_config);
8091                 vlv_prepare_pll(crtc, pipe_config);
8092                 vlv_enable_pll(crtc, pipe_config);
8093         }
8094
8095         kfree(pipe_config);
8096
8097         return 0;
8098 }
8099
8100 /**
8101  * vlv_force_pll_off - forcibly disable just the PLL
8102  * @dev_priv: i915 private structure
8103  * @pipe: pipe PLL to disable
8104  *
8105  * Disable the PLL for @pipe. To be used in cases where we need
8106  * the PLL enabled even when @pipe is not going to be enabled.
8107  */
8108 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8109 {
8110         if (IS_CHERRYVIEW(dev_priv))
8111                 chv_disable_pll(dev_priv, pipe);
8112         else
8113                 vlv_disable_pll(dev_priv, pipe);
8114 }
8115
8116 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8117                               struct intel_crtc_state *crtc_state,
8118                               struct dpll *reduced_clock)
8119 {
8120         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8121         u32 dpll;
8122         struct dpll *clock = &crtc_state->dpll;
8123
8124         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8125
8126         dpll = DPLL_VGA_MODE_DIS;
8127
8128         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8129                 dpll |= DPLLB_MODE_LVDS;
8130         else
8131                 dpll |= DPLLB_MODE_DAC_SERIAL;
8132
8133         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) {
8134                 dpll |= (crtc_state->pixel_multiplier - 1)
8135                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8136         }
8137
8138         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8139             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8140                 dpll |= DPLL_SDVO_HIGH_SPEED;
8141
8142         if (intel_crtc_has_dp_encoder(crtc_state))
8143                 dpll |= DPLL_SDVO_HIGH_SPEED;
8144
8145         /* compute bitmask from p1 value */
8146         if (IS_PINEVIEW(dev_priv))
8147                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8148         else {
8149                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8150                 if (IS_G4X(dev_priv) && reduced_clock)
8151                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8152         }
8153         switch (clock->p2) {
8154         case 5:
8155                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8156                 break;
8157         case 7:
8158                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8159                 break;
8160         case 10:
8161                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8162                 break;
8163         case 14:
8164                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8165                 break;
8166         }
8167         if (INTEL_GEN(dev_priv) >= 4)
8168                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8169
8170         if (crtc_state->sdvo_tv_clock)
8171                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8172         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8173                  intel_panel_use_ssc(dev_priv))
8174                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8175         else
8176                 dpll |= PLL_REF_INPUT_DREFCLK;
8177
8178         dpll |= DPLL_VCO_ENABLE;
8179         crtc_state->dpll_hw_state.dpll = dpll;
8180
8181         if (INTEL_GEN(dev_priv) >= 4) {
8182                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8183                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8184                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8185         }
8186 }
8187
8188 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8189                               struct intel_crtc_state *crtc_state,
8190                               struct dpll *reduced_clock)
8191 {
8192         struct drm_device *dev = crtc->base.dev;
8193         struct drm_i915_private *dev_priv = to_i915(dev);
8194         u32 dpll;
8195         struct dpll *clock = &crtc_state->dpll;
8196
8197         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8198
8199         dpll = DPLL_VGA_MODE_DIS;
8200
8201         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8202                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8203         } else {
8204                 if (clock->p1 == 2)
8205                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8206                 else
8207                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8208                 if (clock->p2 == 4)
8209                         dpll |= PLL_P2_DIVIDE_BY_4;
8210         }
8211
8212         if (!IS_I830(dev_priv) &&
8213             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8214                 dpll |= DPLL_DVO_2X_MODE;
8215
8216         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8217             intel_panel_use_ssc(dev_priv))
8218                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8219         else
8220                 dpll |= PLL_REF_INPUT_DREFCLK;
8221
8222         dpll |= DPLL_VCO_ENABLE;
8223         crtc_state->dpll_hw_state.dpll = dpll;
8224 }
8225
8226 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8227 {
8228         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8229         enum pipe pipe = intel_crtc->pipe;
8230         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8231         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8232         uint32_t crtc_vtotal, crtc_vblank_end;
8233         int vsyncshift = 0;
8234
8235         /* We need to be careful not to changed the adjusted mode, for otherwise
8236          * the hw state checker will get angry at the mismatch. */
8237         crtc_vtotal = adjusted_mode->crtc_vtotal;
8238         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8239
8240         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8241                 /* the chip adds 2 halflines automatically */
8242                 crtc_vtotal -= 1;
8243                 crtc_vblank_end -= 1;
8244
8245                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8246                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8247                 else
8248                         vsyncshift = adjusted_mode->crtc_hsync_start -
8249                                 adjusted_mode->crtc_htotal / 2;
8250                 if (vsyncshift < 0)
8251                         vsyncshift += adjusted_mode->crtc_htotal;
8252         }
8253
8254         if (INTEL_GEN(dev_priv) > 3)
8255                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8256
8257         I915_WRITE(HTOTAL(cpu_transcoder),
8258                    (adjusted_mode->crtc_hdisplay - 1) |
8259                    ((adjusted_mode->crtc_htotal - 1) << 16));
8260         I915_WRITE(HBLANK(cpu_transcoder),
8261                    (adjusted_mode->crtc_hblank_start - 1) |
8262                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8263         I915_WRITE(HSYNC(cpu_transcoder),
8264                    (adjusted_mode->crtc_hsync_start - 1) |
8265                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8266
8267         I915_WRITE(VTOTAL(cpu_transcoder),
8268                    (adjusted_mode->crtc_vdisplay - 1) |
8269                    ((crtc_vtotal - 1) << 16));
8270         I915_WRITE(VBLANK(cpu_transcoder),
8271                    (adjusted_mode->crtc_vblank_start - 1) |
8272                    ((crtc_vblank_end - 1) << 16));
8273         I915_WRITE(VSYNC(cpu_transcoder),
8274                    (adjusted_mode->crtc_vsync_start - 1) |
8275                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8276
8277         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8278          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8279          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8280          * bits. */
8281         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8282             (pipe == PIPE_B || pipe == PIPE_C))
8283                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8284
8285 }
8286
8287 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8288 {
8289         struct drm_device *dev = intel_crtc->base.dev;
8290         struct drm_i915_private *dev_priv = to_i915(dev);
8291         enum pipe pipe = intel_crtc->pipe;
8292
8293         /* pipesrc controls the size that is scaled from, which should
8294          * always be the user's requested size.
8295          */
8296         I915_WRITE(PIPESRC(pipe),
8297                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
8298                    (intel_crtc->config->pipe_src_h - 1));
8299 }
8300
8301 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8302                                    struct intel_crtc_state *pipe_config)
8303 {
8304         struct drm_device *dev = crtc->base.dev;
8305         struct drm_i915_private *dev_priv = to_i915(dev);
8306         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8307         uint32_t tmp;
8308
8309         tmp = I915_READ(HTOTAL(cpu_transcoder));
8310         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8311         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8312         tmp = I915_READ(HBLANK(cpu_transcoder));
8313         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8314         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8315         tmp = I915_READ(HSYNC(cpu_transcoder));
8316         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8317         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8318
8319         tmp = I915_READ(VTOTAL(cpu_transcoder));
8320         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8321         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8322         tmp = I915_READ(VBLANK(cpu_transcoder));
8323         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8324         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8325         tmp = I915_READ(VSYNC(cpu_transcoder));
8326         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8327         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8328
8329         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8330                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8331                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8332                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8333         }
8334 }
8335
8336 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8337                                     struct intel_crtc_state *pipe_config)
8338 {
8339         struct drm_device *dev = crtc->base.dev;
8340         struct drm_i915_private *dev_priv = to_i915(dev);
8341         u32 tmp;
8342
8343         tmp = I915_READ(PIPESRC(crtc->pipe));
8344         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8345         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8346
8347         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8348         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8349 }
8350
8351 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8352                                  struct intel_crtc_state *pipe_config)
8353 {
8354         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8355         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8356         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8357         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8358
8359         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8360         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8361         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8362         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8363
8364         mode->flags = pipe_config->base.adjusted_mode.flags;
8365         mode->type = DRM_MODE_TYPE_DRIVER;
8366
8367         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8368         mode->flags |= pipe_config->base.adjusted_mode.flags;
8369
8370         mode->hsync = drm_mode_hsync(mode);
8371         mode->vrefresh = drm_mode_vrefresh(mode);
8372         drm_mode_set_name(mode);
8373 }
8374
8375 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8376 {
8377         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8378         uint32_t pipeconf;
8379
8380         pipeconf = 0;
8381
8382         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8383             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8384                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8385
8386         if (intel_crtc->config->double_wide)
8387                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8388
8389         /* only g4x and later have fancy bpc/dither controls */
8390         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8391             IS_CHERRYVIEW(dev_priv)) {
8392                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8393                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8394                         pipeconf |= PIPECONF_DITHER_EN |
8395                                     PIPECONF_DITHER_TYPE_SP;
8396
8397                 switch (intel_crtc->config->pipe_bpp) {
8398                 case 18:
8399                         pipeconf |= PIPECONF_6BPC;
8400                         break;
8401                 case 24:
8402                         pipeconf |= PIPECONF_8BPC;
8403                         break;
8404                 case 30:
8405                         pipeconf |= PIPECONF_10BPC;
8406                         break;
8407                 default:
8408                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8409                         BUG();
8410                 }
8411         }
8412
8413         if (HAS_PIPE_CXSR(dev_priv)) {
8414                 if (intel_crtc->lowfreq_avail) {
8415                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8416                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8417                 } else {
8418                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8419                 }
8420         }
8421
8422         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8423                 if (INTEL_GEN(dev_priv) < 4 ||
8424                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8425                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8426                 else
8427                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8428         } else
8429                 pipeconf |= PIPECONF_PROGRESSIVE;
8430
8431         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8432              intel_crtc->config->limited_color_range)
8433                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8434
8435         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8436         POSTING_READ(PIPECONF(intel_crtc->pipe));
8437 }
8438
8439 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8440                                    struct intel_crtc_state *crtc_state)
8441 {
8442         struct drm_device *dev = crtc->base.dev;
8443         struct drm_i915_private *dev_priv = to_i915(dev);
8444         const struct intel_limit *limit;
8445         int refclk = 48000;
8446
8447         memset(&crtc_state->dpll_hw_state, 0,
8448                sizeof(crtc_state->dpll_hw_state));
8449
8450         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8451                 if (intel_panel_use_ssc(dev_priv)) {
8452                         refclk = dev_priv->vbt.lvds_ssc_freq;
8453                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8454                 }
8455
8456                 limit = &intel_limits_i8xx_lvds;
8457         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8458                 limit = &intel_limits_i8xx_dvo;
8459         } else {
8460                 limit = &intel_limits_i8xx_dac;
8461         }
8462
8463         if (!crtc_state->clock_set &&
8464             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8465                                  refclk, NULL, &crtc_state->dpll)) {
8466                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8467                 return -EINVAL;
8468         }
8469
8470         i8xx_compute_dpll(crtc, crtc_state, NULL);
8471
8472         return 0;
8473 }
8474
8475 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8476                                   struct intel_crtc_state *crtc_state)
8477 {
8478         struct drm_device *dev = crtc->base.dev;
8479         struct drm_i915_private *dev_priv = to_i915(dev);
8480         const struct intel_limit *limit;
8481         int refclk = 96000;
8482
8483         memset(&crtc_state->dpll_hw_state, 0,
8484                sizeof(crtc_state->dpll_hw_state));
8485
8486         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8487                 if (intel_panel_use_ssc(dev_priv)) {
8488                         refclk = dev_priv->vbt.lvds_ssc_freq;
8489                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8490                 }
8491
8492                 if (intel_is_dual_link_lvds(dev))
8493                         limit = &intel_limits_g4x_dual_channel_lvds;
8494                 else
8495                         limit = &intel_limits_g4x_single_channel_lvds;
8496         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8497                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8498                 limit = &intel_limits_g4x_hdmi;
8499         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8500                 limit = &intel_limits_g4x_sdvo;
8501         } else {
8502                 /* The option is for other outputs */
8503                 limit = &intel_limits_i9xx_sdvo;
8504         }
8505
8506         if (!crtc_state->clock_set &&
8507             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8508                                 refclk, NULL, &crtc_state->dpll)) {
8509                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8510                 return -EINVAL;
8511         }
8512
8513         i9xx_compute_dpll(crtc, crtc_state, NULL);
8514
8515         return 0;
8516 }
8517
8518 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8519                                   struct intel_crtc_state *crtc_state)
8520 {
8521         struct drm_device *dev = crtc->base.dev;
8522         struct drm_i915_private *dev_priv = to_i915(dev);
8523         const struct intel_limit *limit;
8524         int refclk = 96000;
8525
8526         memset(&crtc_state->dpll_hw_state, 0,
8527                sizeof(crtc_state->dpll_hw_state));
8528
8529         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8530                 if (intel_panel_use_ssc(dev_priv)) {
8531                         refclk = dev_priv->vbt.lvds_ssc_freq;
8532                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8533                 }
8534
8535                 limit = &intel_limits_pineview_lvds;
8536         } else {
8537                 limit = &intel_limits_pineview_sdvo;
8538         }
8539
8540         if (!crtc_state->clock_set &&
8541             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8542                                 refclk, NULL, &crtc_state->dpll)) {
8543                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8544                 return -EINVAL;
8545         }
8546
8547         i9xx_compute_dpll(crtc, crtc_state, NULL);
8548
8549         return 0;
8550 }
8551
8552 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8553                                    struct intel_crtc_state *crtc_state)
8554 {
8555         struct drm_device *dev = crtc->base.dev;
8556         struct drm_i915_private *dev_priv = to_i915(dev);
8557         const struct intel_limit *limit;
8558         int refclk = 96000;
8559
8560         memset(&crtc_state->dpll_hw_state, 0,
8561                sizeof(crtc_state->dpll_hw_state));
8562
8563         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8564                 if (intel_panel_use_ssc(dev_priv)) {
8565                         refclk = dev_priv->vbt.lvds_ssc_freq;
8566                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8567                 }
8568
8569                 limit = &intel_limits_i9xx_lvds;
8570         } else {
8571                 limit = &intel_limits_i9xx_sdvo;
8572         }
8573
8574         if (!crtc_state->clock_set &&
8575             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8576                                  refclk, NULL, &crtc_state->dpll)) {
8577                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8578                 return -EINVAL;
8579         }
8580
8581         i9xx_compute_dpll(crtc, crtc_state, NULL);
8582
8583         return 0;
8584 }
8585
8586 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8587                                   struct intel_crtc_state *crtc_state)
8588 {
8589         int refclk = 100000;
8590         const struct intel_limit *limit = &intel_limits_chv;
8591
8592         memset(&crtc_state->dpll_hw_state, 0,
8593                sizeof(crtc_state->dpll_hw_state));
8594
8595         if (!crtc_state->clock_set &&
8596             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8597                                 refclk, NULL, &crtc_state->dpll)) {
8598                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8599                 return -EINVAL;
8600         }
8601
8602         chv_compute_dpll(crtc, crtc_state);
8603
8604         return 0;
8605 }
8606
8607 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8608                                   struct intel_crtc_state *crtc_state)
8609 {
8610         int refclk = 100000;
8611         const struct intel_limit *limit = &intel_limits_vlv;
8612
8613         memset(&crtc_state->dpll_hw_state, 0,
8614                sizeof(crtc_state->dpll_hw_state));
8615
8616         if (!crtc_state->clock_set &&
8617             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8618                                 refclk, NULL, &crtc_state->dpll)) {
8619                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8620                 return -EINVAL;
8621         }
8622
8623         vlv_compute_dpll(crtc, crtc_state);
8624
8625         return 0;
8626 }
8627
8628 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8629                                  struct intel_crtc_state *pipe_config)
8630 {
8631         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8632         uint32_t tmp;
8633
8634         if (INTEL_GEN(dev_priv) <= 3 &&
8635             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
8636                 return;
8637
8638         tmp = I915_READ(PFIT_CONTROL);
8639         if (!(tmp & PFIT_ENABLE))
8640                 return;
8641
8642         /* Check whether the pfit is attached to our pipe. */
8643         if (INTEL_GEN(dev_priv) < 4) {
8644                 if (crtc->pipe != PIPE_B)
8645                         return;
8646         } else {
8647                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8648                         return;
8649         }
8650
8651         pipe_config->gmch_pfit.control = tmp;
8652         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8653 }
8654
8655 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8656                                struct intel_crtc_state *pipe_config)
8657 {
8658         struct drm_device *dev = crtc->base.dev;
8659         struct drm_i915_private *dev_priv = to_i915(dev);
8660         int pipe = pipe_config->cpu_transcoder;
8661         struct dpll clock;
8662         u32 mdiv;
8663         int refclk = 100000;
8664
8665         /* In case of DSI, DPLL will not be used */
8666         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8667                 return;
8668
8669         mutex_lock(&dev_priv->sb_lock);
8670         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8671         mutex_unlock(&dev_priv->sb_lock);
8672
8673         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8674         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8675         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8676         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8677         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8678
8679         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8680 }
8681
8682 static void
8683 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8684                               struct intel_initial_plane_config *plane_config)
8685 {
8686         struct drm_device *dev = crtc->base.dev;
8687         struct drm_i915_private *dev_priv = to_i915(dev);
8688         u32 val, base, offset;
8689         int pipe = crtc->pipe, plane = crtc->plane;
8690         int fourcc, pixel_format;
8691         unsigned int aligned_height;
8692         struct drm_framebuffer *fb;
8693         struct intel_framebuffer *intel_fb;
8694
8695         val = I915_READ(DSPCNTR(plane));
8696         if (!(val & DISPLAY_PLANE_ENABLE))
8697                 return;
8698
8699         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8700         if (!intel_fb) {
8701                 DRM_DEBUG_KMS("failed to alloc fb\n");
8702                 return;
8703         }
8704
8705         fb = &intel_fb->base;
8706
8707         if (INTEL_GEN(dev_priv) >= 4) {
8708                 if (val & DISPPLANE_TILED) {
8709                         plane_config->tiling = I915_TILING_X;
8710                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8711                 }
8712         }
8713
8714         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8715         fourcc = i9xx_format_to_fourcc(pixel_format);
8716         fb->pixel_format = fourcc;
8717         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8718
8719         if (INTEL_GEN(dev_priv) >= 4) {
8720                 if (plane_config->tiling)
8721                         offset = I915_READ(DSPTILEOFF(plane));
8722                 else
8723                         offset = I915_READ(DSPLINOFF(plane));
8724                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8725         } else {
8726                 base = I915_READ(DSPADDR(plane));
8727         }
8728         plane_config->base = base;
8729
8730         val = I915_READ(PIPESRC(pipe));
8731         fb->width = ((val >> 16) & 0xfff) + 1;
8732         fb->height = ((val >> 0) & 0xfff) + 1;
8733
8734         val = I915_READ(DSPSTRIDE(pipe));
8735         fb->pitches[0] = val & 0xffffffc0;
8736
8737         aligned_height = intel_fb_align_height(dev, fb->height,
8738                                                fb->pixel_format,
8739                                                fb->modifier);
8740
8741         plane_config->size = fb->pitches[0] * aligned_height;
8742
8743         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8744                       pipe_name(pipe), plane, fb->width, fb->height,
8745                       fb->bits_per_pixel, base, fb->pitches[0],
8746                       plane_config->size);
8747
8748         plane_config->fb = intel_fb;
8749 }
8750
8751 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8752                                struct intel_crtc_state *pipe_config)
8753 {
8754         struct drm_device *dev = crtc->base.dev;
8755         struct drm_i915_private *dev_priv = to_i915(dev);
8756         int pipe = pipe_config->cpu_transcoder;
8757         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8758         struct dpll clock;
8759         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8760         int refclk = 100000;
8761
8762         /* In case of DSI, DPLL will not be used */
8763         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8764                 return;
8765
8766         mutex_lock(&dev_priv->sb_lock);
8767         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8768         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8769         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8770         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8771         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8772         mutex_unlock(&dev_priv->sb_lock);
8773
8774         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8775         clock.m2 = (pll_dw0 & 0xff) << 22;
8776         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8777                 clock.m2 |= pll_dw2 & 0x3fffff;
8778         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8779         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8780         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8781
8782         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8783 }
8784
8785 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8786                                  struct intel_crtc_state *pipe_config)
8787 {
8788         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8789         enum intel_display_power_domain power_domain;
8790         uint32_t tmp;
8791         bool ret;
8792
8793         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8794         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8795                 return false;
8796
8797         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8798         pipe_config->shared_dpll = NULL;
8799
8800         ret = false;
8801
8802         tmp = I915_READ(PIPECONF(crtc->pipe));
8803         if (!(tmp & PIPECONF_ENABLE))
8804                 goto out;
8805
8806         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8807             IS_CHERRYVIEW(dev_priv)) {
8808                 switch (tmp & PIPECONF_BPC_MASK) {
8809                 case PIPECONF_6BPC:
8810                         pipe_config->pipe_bpp = 18;
8811                         break;
8812                 case PIPECONF_8BPC:
8813                         pipe_config->pipe_bpp = 24;
8814                         break;
8815                 case PIPECONF_10BPC:
8816                         pipe_config->pipe_bpp = 30;
8817                         break;
8818                 default:
8819                         break;
8820                 }
8821         }
8822
8823         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8824             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8825                 pipe_config->limited_color_range = true;
8826
8827         if (INTEL_GEN(dev_priv) < 4)
8828                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8829
8830         intel_get_pipe_timings(crtc, pipe_config);
8831         intel_get_pipe_src_size(crtc, pipe_config);
8832
8833         i9xx_get_pfit_config(crtc, pipe_config);
8834
8835         if (INTEL_GEN(dev_priv) >= 4) {
8836                 /* No way to read it out on pipes B and C */
8837                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8838                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8839                 else
8840                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8841                 pipe_config->pixel_multiplier =
8842                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8843                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8844                 pipe_config->dpll_hw_state.dpll_md = tmp;
8845         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8846                    IS_G33(dev_priv)) {
8847                 tmp = I915_READ(DPLL(crtc->pipe));
8848                 pipe_config->pixel_multiplier =
8849                         ((tmp & SDVO_MULTIPLIER_MASK)
8850                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8851         } else {
8852                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8853                  * port and will be fixed up in the encoder->get_config
8854                  * function. */
8855                 pipe_config->pixel_multiplier = 1;
8856         }
8857         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8858         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8859                 /*
8860                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8861                  * on 830. Filter it out here so that we don't
8862                  * report errors due to that.
8863                  */
8864                 if (IS_I830(dev_priv))
8865                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8866
8867                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8868                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8869         } else {
8870                 /* Mask out read-only status bits. */
8871                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8872                                                      DPLL_PORTC_READY_MASK |
8873                                                      DPLL_PORTB_READY_MASK);
8874         }
8875
8876         if (IS_CHERRYVIEW(dev_priv))
8877                 chv_crtc_clock_get(crtc, pipe_config);
8878         else if (IS_VALLEYVIEW(dev_priv))
8879                 vlv_crtc_clock_get(crtc, pipe_config);
8880         else
8881                 i9xx_crtc_clock_get(crtc, pipe_config);
8882
8883         /*
8884          * Normally the dotclock is filled in by the encoder .get_config()
8885          * but in case the pipe is enabled w/o any ports we need a sane
8886          * default.
8887          */
8888         pipe_config->base.adjusted_mode.crtc_clock =
8889                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8890
8891         ret = true;
8892
8893 out:
8894         intel_display_power_put(dev_priv, power_domain);
8895
8896         return ret;
8897 }
8898
8899 static void ironlake_init_pch_refclk(struct drm_device *dev)
8900 {
8901         struct drm_i915_private *dev_priv = to_i915(dev);
8902         struct intel_encoder *encoder;
8903         int i;
8904         u32 val, final;
8905         bool has_lvds = false;
8906         bool has_cpu_edp = false;
8907         bool has_panel = false;
8908         bool has_ck505 = false;
8909         bool can_ssc = false;
8910         bool using_ssc_source = false;
8911
8912         /* We need to take the global config into account */
8913         for_each_intel_encoder(dev, encoder) {
8914                 switch (encoder->type) {
8915                 case INTEL_OUTPUT_LVDS:
8916                         has_panel = true;
8917                         has_lvds = true;
8918                         break;
8919                 case INTEL_OUTPUT_EDP:
8920                         has_panel = true;
8921                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8922                                 has_cpu_edp = true;
8923                         break;
8924                 default:
8925                         break;
8926                 }
8927         }
8928
8929         if (HAS_PCH_IBX(dev_priv)) {
8930                 has_ck505 = dev_priv->vbt.display_clock_mode;
8931                 can_ssc = has_ck505;
8932         } else {
8933                 has_ck505 = false;
8934                 can_ssc = true;
8935         }
8936
8937         /* Check if any DPLLs are using the SSC source */
8938         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8939                 u32 temp = I915_READ(PCH_DPLL(i));
8940
8941                 if (!(temp & DPLL_VCO_ENABLE))
8942                         continue;
8943
8944                 if ((temp & PLL_REF_INPUT_MASK) ==
8945                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8946                         using_ssc_source = true;
8947                         break;
8948                 }
8949         }
8950
8951         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8952                       has_panel, has_lvds, has_ck505, using_ssc_source);
8953
8954         /* Ironlake: try to setup display ref clock before DPLL
8955          * enabling. This is only under driver's control after
8956          * PCH B stepping, previous chipset stepping should be
8957          * ignoring this setting.
8958          */
8959         val = I915_READ(PCH_DREF_CONTROL);
8960
8961         /* As we must carefully and slowly disable/enable each source in turn,
8962          * compute the final state we want first and check if we need to
8963          * make any changes at all.
8964          */
8965         final = val;
8966         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8967         if (has_ck505)
8968                 final |= DREF_NONSPREAD_CK505_ENABLE;
8969         else
8970                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8971
8972         final &= ~DREF_SSC_SOURCE_MASK;
8973         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8974         final &= ~DREF_SSC1_ENABLE;
8975
8976         if (has_panel) {
8977                 final |= DREF_SSC_SOURCE_ENABLE;
8978
8979                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8980                         final |= DREF_SSC1_ENABLE;
8981
8982                 if (has_cpu_edp) {
8983                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8984                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8985                         else
8986                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8987                 } else
8988                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8989         } else if (using_ssc_source) {
8990                 final |= DREF_SSC_SOURCE_ENABLE;
8991                 final |= DREF_SSC1_ENABLE;
8992         }
8993
8994         if (final == val)
8995                 return;
8996
8997         /* Always enable nonspread source */
8998         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8999
9000         if (has_ck505)
9001                 val |= DREF_NONSPREAD_CK505_ENABLE;
9002         else
9003                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9004
9005         if (has_panel) {
9006                 val &= ~DREF_SSC_SOURCE_MASK;
9007                 val |= DREF_SSC_SOURCE_ENABLE;
9008
9009                 /* SSC must be turned on before enabling the CPU output  */
9010                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9011                         DRM_DEBUG_KMS("Using SSC on panel\n");
9012                         val |= DREF_SSC1_ENABLE;
9013                 } else
9014                         val &= ~DREF_SSC1_ENABLE;
9015
9016                 /* Get SSC going before enabling the outputs */
9017                 I915_WRITE(PCH_DREF_CONTROL, val);
9018                 POSTING_READ(PCH_DREF_CONTROL);
9019                 udelay(200);
9020
9021                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9022
9023                 /* Enable CPU source on CPU attached eDP */
9024                 if (has_cpu_edp) {
9025                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9026                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9027                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9028                         } else
9029                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9030                 } else
9031                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9032
9033                 I915_WRITE(PCH_DREF_CONTROL, val);
9034                 POSTING_READ(PCH_DREF_CONTROL);
9035                 udelay(200);
9036         } else {
9037                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9038
9039                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9040
9041                 /* Turn off CPU output */
9042                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9043
9044                 I915_WRITE(PCH_DREF_CONTROL, val);
9045                 POSTING_READ(PCH_DREF_CONTROL);
9046                 udelay(200);
9047
9048                 if (!using_ssc_source) {
9049                         DRM_DEBUG_KMS("Disabling SSC source\n");
9050
9051                         /* Turn off the SSC source */
9052                         val &= ~DREF_SSC_SOURCE_MASK;
9053                         val |= DREF_SSC_SOURCE_DISABLE;
9054
9055                         /* Turn off SSC1 */
9056                         val &= ~DREF_SSC1_ENABLE;
9057
9058                         I915_WRITE(PCH_DREF_CONTROL, val);
9059                         POSTING_READ(PCH_DREF_CONTROL);
9060                         udelay(200);
9061                 }
9062         }
9063
9064         BUG_ON(val != final);
9065 }
9066
9067 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9068 {
9069         uint32_t tmp;
9070
9071         tmp = I915_READ(SOUTH_CHICKEN2);
9072         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9073         I915_WRITE(SOUTH_CHICKEN2, tmp);
9074
9075         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9076                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9077                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9078
9079         tmp = I915_READ(SOUTH_CHICKEN2);
9080         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9081         I915_WRITE(SOUTH_CHICKEN2, tmp);
9082
9083         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9084                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9085                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9086 }
9087
9088 /* WaMPhyProgramming:hsw */
9089 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9090 {
9091         uint32_t tmp;
9092
9093         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9094         tmp &= ~(0xFF << 24);
9095         tmp |= (0x12 << 24);
9096         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9097
9098         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9099         tmp |= (1 << 11);
9100         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9101
9102         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9103         tmp |= (1 << 11);
9104         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9105
9106         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9107         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9108         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9109
9110         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9111         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9112         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9113
9114         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9115         tmp &= ~(7 << 13);
9116         tmp |= (5 << 13);
9117         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9118
9119         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9120         tmp &= ~(7 << 13);
9121         tmp |= (5 << 13);
9122         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9123
9124         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9125         tmp &= ~0xFF;
9126         tmp |= 0x1C;
9127         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9128
9129         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9130         tmp &= ~0xFF;
9131         tmp |= 0x1C;
9132         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9133
9134         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9135         tmp &= ~(0xFF << 16);
9136         tmp |= (0x1C << 16);
9137         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9138
9139         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9140         tmp &= ~(0xFF << 16);
9141         tmp |= (0x1C << 16);
9142         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9143
9144         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9145         tmp |= (1 << 27);
9146         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9147
9148         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9149         tmp |= (1 << 27);
9150         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9151
9152         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9153         tmp &= ~(0xF << 28);
9154         tmp |= (4 << 28);
9155         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9156
9157         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9158         tmp &= ~(0xF << 28);
9159         tmp |= (4 << 28);
9160         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9161 }
9162
9163 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9164  * Programming" based on the parameters passed:
9165  * - Sequence to enable CLKOUT_DP
9166  * - Sequence to enable CLKOUT_DP without spread
9167  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9168  */
9169 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9170                                  bool with_fdi)
9171 {
9172         struct drm_i915_private *dev_priv = to_i915(dev);
9173         uint32_t reg, tmp;
9174
9175         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9176                 with_spread = true;
9177         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9178             with_fdi, "LP PCH doesn't have FDI\n"))
9179                 with_fdi = false;
9180
9181         mutex_lock(&dev_priv->sb_lock);
9182
9183         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9184         tmp &= ~SBI_SSCCTL_DISABLE;
9185         tmp |= SBI_SSCCTL_PATHALT;
9186         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9187
9188         udelay(24);
9189
9190         if (with_spread) {
9191                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9192                 tmp &= ~SBI_SSCCTL_PATHALT;
9193                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9194
9195                 if (with_fdi) {
9196                         lpt_reset_fdi_mphy(dev_priv);
9197                         lpt_program_fdi_mphy(dev_priv);
9198                 }
9199         }
9200
9201         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9202         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9203         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9204         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9205
9206         mutex_unlock(&dev_priv->sb_lock);
9207 }
9208
9209 /* Sequence to disable CLKOUT_DP */
9210 static void lpt_disable_clkout_dp(struct drm_device *dev)
9211 {
9212         struct drm_i915_private *dev_priv = to_i915(dev);
9213         uint32_t reg, tmp;
9214
9215         mutex_lock(&dev_priv->sb_lock);
9216
9217         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9218         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9219         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9220         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9221
9222         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9223         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9224                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9225                         tmp |= SBI_SSCCTL_PATHALT;
9226                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9227                         udelay(32);
9228                 }
9229                 tmp |= SBI_SSCCTL_DISABLE;
9230                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9231         }
9232
9233         mutex_unlock(&dev_priv->sb_lock);
9234 }
9235
9236 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9237
9238 static const uint16_t sscdivintphase[] = {
9239         [BEND_IDX( 50)] = 0x3B23,
9240         [BEND_IDX( 45)] = 0x3B23,
9241         [BEND_IDX( 40)] = 0x3C23,
9242         [BEND_IDX( 35)] = 0x3C23,
9243         [BEND_IDX( 30)] = 0x3D23,
9244         [BEND_IDX( 25)] = 0x3D23,
9245         [BEND_IDX( 20)] = 0x3E23,
9246         [BEND_IDX( 15)] = 0x3E23,
9247         [BEND_IDX( 10)] = 0x3F23,
9248         [BEND_IDX(  5)] = 0x3F23,
9249         [BEND_IDX(  0)] = 0x0025,
9250         [BEND_IDX( -5)] = 0x0025,
9251         [BEND_IDX(-10)] = 0x0125,
9252         [BEND_IDX(-15)] = 0x0125,
9253         [BEND_IDX(-20)] = 0x0225,
9254         [BEND_IDX(-25)] = 0x0225,
9255         [BEND_IDX(-30)] = 0x0325,
9256         [BEND_IDX(-35)] = 0x0325,
9257         [BEND_IDX(-40)] = 0x0425,
9258         [BEND_IDX(-45)] = 0x0425,
9259         [BEND_IDX(-50)] = 0x0525,
9260 };
9261
9262 /*
9263  * Bend CLKOUT_DP
9264  * steps -50 to 50 inclusive, in steps of 5
9265  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9266  * change in clock period = -(steps / 10) * 5.787 ps
9267  */
9268 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9269 {
9270         uint32_t tmp;
9271         int idx = BEND_IDX(steps);
9272
9273         if (WARN_ON(steps % 5 != 0))
9274                 return;
9275
9276         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9277                 return;
9278
9279         mutex_lock(&dev_priv->sb_lock);
9280
9281         if (steps % 10 != 0)
9282                 tmp = 0xAAAAAAAB;
9283         else
9284                 tmp = 0x00000000;
9285         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9286
9287         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9288         tmp &= 0xffff0000;
9289         tmp |= sscdivintphase[idx];
9290         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9291
9292         mutex_unlock(&dev_priv->sb_lock);
9293 }
9294
9295 #undef BEND_IDX
9296
9297 static void lpt_init_pch_refclk(struct drm_device *dev)
9298 {
9299         struct intel_encoder *encoder;
9300         bool has_vga = false;
9301
9302         for_each_intel_encoder(dev, encoder) {
9303                 switch (encoder->type) {
9304                 case INTEL_OUTPUT_ANALOG:
9305                         has_vga = true;
9306                         break;
9307                 default:
9308                         break;
9309                 }
9310         }
9311
9312         if (has_vga) {
9313                 lpt_bend_clkout_dp(to_i915(dev), 0);
9314                 lpt_enable_clkout_dp(dev, true, true);
9315         } else {
9316                 lpt_disable_clkout_dp(dev);
9317         }
9318 }
9319
9320 /*
9321  * Initialize reference clocks when the driver loads
9322  */
9323 void intel_init_pch_refclk(struct drm_device *dev)
9324 {
9325         struct drm_i915_private *dev_priv = to_i915(dev);
9326
9327         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9328                 ironlake_init_pch_refclk(dev);
9329         else if (HAS_PCH_LPT(dev_priv))
9330                 lpt_init_pch_refclk(dev);
9331 }
9332
9333 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9334 {
9335         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9337         int pipe = intel_crtc->pipe;
9338         uint32_t val;
9339
9340         val = 0;
9341
9342         switch (intel_crtc->config->pipe_bpp) {
9343         case 18:
9344                 val |= PIPECONF_6BPC;
9345                 break;
9346         case 24:
9347                 val |= PIPECONF_8BPC;
9348                 break;
9349         case 30:
9350                 val |= PIPECONF_10BPC;
9351                 break;
9352         case 36:
9353                 val |= PIPECONF_12BPC;
9354                 break;
9355         default:
9356                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9357                 BUG();
9358         }
9359
9360         if (intel_crtc->config->dither)
9361                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9362
9363         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9364                 val |= PIPECONF_INTERLACED_ILK;
9365         else
9366                 val |= PIPECONF_PROGRESSIVE;
9367
9368         if (intel_crtc->config->limited_color_range)
9369                 val |= PIPECONF_COLOR_RANGE_SELECT;
9370
9371         I915_WRITE(PIPECONF(pipe), val);
9372         POSTING_READ(PIPECONF(pipe));
9373 }
9374
9375 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9376 {
9377         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9379         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9380         u32 val = 0;
9381
9382         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9383                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9384
9385         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9386                 val |= PIPECONF_INTERLACED_ILK;
9387         else
9388                 val |= PIPECONF_PROGRESSIVE;
9389
9390         I915_WRITE(PIPECONF(cpu_transcoder), val);
9391         POSTING_READ(PIPECONF(cpu_transcoder));
9392 }
9393
9394 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9395 {
9396         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9398
9399         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9400                 u32 val = 0;
9401
9402                 switch (intel_crtc->config->pipe_bpp) {
9403                 case 18:
9404                         val |= PIPEMISC_DITHER_6_BPC;
9405                         break;
9406                 case 24:
9407                         val |= PIPEMISC_DITHER_8_BPC;
9408                         break;
9409                 case 30:
9410                         val |= PIPEMISC_DITHER_10_BPC;
9411                         break;
9412                 case 36:
9413                         val |= PIPEMISC_DITHER_12_BPC;
9414                         break;
9415                 default:
9416                         /* Case prevented by pipe_config_set_bpp. */
9417                         BUG();
9418                 }
9419
9420                 if (intel_crtc->config->dither)
9421                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9422
9423                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9424         }
9425 }
9426
9427 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9428 {
9429         /*
9430          * Account for spread spectrum to avoid
9431          * oversubscribing the link. Max center spread
9432          * is 2.5%; use 5% for safety's sake.
9433          */
9434         u32 bps = target_clock * bpp * 21 / 20;
9435         return DIV_ROUND_UP(bps, link_bw * 8);
9436 }
9437
9438 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9439 {
9440         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9441 }
9442
9443 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9444                                   struct intel_crtc_state *crtc_state,
9445                                   struct dpll *reduced_clock)
9446 {
9447         struct drm_crtc *crtc = &intel_crtc->base;
9448         struct drm_device *dev = crtc->dev;
9449         struct drm_i915_private *dev_priv = to_i915(dev);
9450         u32 dpll, fp, fp2;
9451         int factor;
9452
9453         /* Enable autotuning of the PLL clock (if permissible) */
9454         factor = 21;
9455         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9456                 if ((intel_panel_use_ssc(dev_priv) &&
9457                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9458                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
9459                         factor = 25;
9460         } else if (crtc_state->sdvo_tv_clock)
9461                 factor = 20;
9462
9463         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9464
9465         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9466                 fp |= FP_CB_TUNE;
9467
9468         if (reduced_clock) {
9469                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9470
9471                 if (reduced_clock->m < factor * reduced_clock->n)
9472                         fp2 |= FP_CB_TUNE;
9473         } else {
9474                 fp2 = fp;
9475         }
9476
9477         dpll = 0;
9478
9479         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9480                 dpll |= DPLLB_MODE_LVDS;
9481         else
9482                 dpll |= DPLLB_MODE_DAC_SERIAL;
9483
9484         dpll |= (crtc_state->pixel_multiplier - 1)
9485                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9486
9487         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9488             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9489                 dpll |= DPLL_SDVO_HIGH_SPEED;
9490
9491         if (intel_crtc_has_dp_encoder(crtc_state))
9492                 dpll |= DPLL_SDVO_HIGH_SPEED;
9493
9494         /*
9495          * The high speed IO clock is only really required for
9496          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9497          * possible to share the DPLL between CRT and HDMI. Enabling
9498          * the clock needlessly does no real harm, except use up a
9499          * bit of power potentially.
9500          *
9501          * We'll limit this to IVB with 3 pipes, since it has only two
9502          * DPLLs and so DPLL sharing is the only way to get three pipes
9503          * driving PCH ports at the same time. On SNB we could do this,
9504          * and potentially avoid enabling the second DPLL, but it's not
9505          * clear if it''s a win or loss power wise. No point in doing
9506          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9507          */
9508         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9509             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9510                 dpll |= DPLL_SDVO_HIGH_SPEED;
9511
9512         /* compute bitmask from p1 value */
9513         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9514         /* also FPA1 */
9515         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9516
9517         switch (crtc_state->dpll.p2) {
9518         case 5:
9519                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9520                 break;
9521         case 7:
9522                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9523                 break;
9524         case 10:
9525                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9526                 break;
9527         case 14:
9528                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9529                 break;
9530         }
9531
9532         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9533             intel_panel_use_ssc(dev_priv))
9534                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9535         else
9536                 dpll |= PLL_REF_INPUT_DREFCLK;
9537
9538         dpll |= DPLL_VCO_ENABLE;
9539
9540         crtc_state->dpll_hw_state.dpll = dpll;
9541         crtc_state->dpll_hw_state.fp0 = fp;
9542         crtc_state->dpll_hw_state.fp1 = fp2;
9543 }
9544
9545 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9546                                        struct intel_crtc_state *crtc_state)
9547 {
9548         struct drm_device *dev = crtc->base.dev;
9549         struct drm_i915_private *dev_priv = to_i915(dev);
9550         struct dpll reduced_clock;
9551         bool has_reduced_clock = false;
9552         struct intel_shared_dpll *pll;
9553         const struct intel_limit *limit;
9554         int refclk = 120000;
9555
9556         memset(&crtc_state->dpll_hw_state, 0,
9557                sizeof(crtc_state->dpll_hw_state));
9558
9559         crtc->lowfreq_avail = false;
9560
9561         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9562         if (!crtc_state->has_pch_encoder)
9563                 return 0;
9564
9565         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9566                 if (intel_panel_use_ssc(dev_priv)) {
9567                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9568                                       dev_priv->vbt.lvds_ssc_freq);
9569                         refclk = dev_priv->vbt.lvds_ssc_freq;
9570                 }
9571
9572                 if (intel_is_dual_link_lvds(dev)) {
9573                         if (refclk == 100000)
9574                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9575                         else
9576                                 limit = &intel_limits_ironlake_dual_lvds;
9577                 } else {
9578                         if (refclk == 100000)
9579                                 limit = &intel_limits_ironlake_single_lvds_100m;
9580                         else
9581                                 limit = &intel_limits_ironlake_single_lvds;
9582                 }
9583         } else {
9584                 limit = &intel_limits_ironlake_dac;
9585         }
9586
9587         if (!crtc_state->clock_set &&
9588             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9589                                 refclk, NULL, &crtc_state->dpll)) {
9590                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9591                 return -EINVAL;
9592         }
9593
9594         ironlake_compute_dpll(crtc, crtc_state,
9595                               has_reduced_clock ? &reduced_clock : NULL);
9596
9597         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9598         if (pll == NULL) {
9599                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9600                                  pipe_name(crtc->pipe));
9601                 return -EINVAL;
9602         }
9603
9604         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9605             has_reduced_clock)
9606                 crtc->lowfreq_avail = true;
9607
9608         return 0;
9609 }
9610
9611 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9612                                          struct intel_link_m_n *m_n)
9613 {
9614         struct drm_device *dev = crtc->base.dev;
9615         struct drm_i915_private *dev_priv = to_i915(dev);
9616         enum pipe pipe = crtc->pipe;
9617
9618         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9619         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9620         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9621                 & ~TU_SIZE_MASK;
9622         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9623         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9624                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9625 }
9626
9627 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9628                                          enum transcoder transcoder,
9629                                          struct intel_link_m_n *m_n,
9630                                          struct intel_link_m_n *m2_n2)
9631 {
9632         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9633         enum pipe pipe = crtc->pipe;
9634
9635         if (INTEL_GEN(dev_priv) >= 5) {
9636                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9637                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9638                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9639                         & ~TU_SIZE_MASK;
9640                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9641                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9642                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9643                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9644                  * gen < 8) and if DRRS is supported (to make sure the
9645                  * registers are not unnecessarily read).
9646                  */
9647                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
9648                         crtc->config->has_drrs) {
9649                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9650                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9651                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9652                                         & ~TU_SIZE_MASK;
9653                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9654                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9655                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9656                 }
9657         } else {
9658                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9659                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9660                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9661                         & ~TU_SIZE_MASK;
9662                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9663                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9664                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9665         }
9666 }
9667
9668 void intel_dp_get_m_n(struct intel_crtc *crtc,
9669                       struct intel_crtc_state *pipe_config)
9670 {
9671         if (pipe_config->has_pch_encoder)
9672                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9673         else
9674                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9675                                              &pipe_config->dp_m_n,
9676                                              &pipe_config->dp_m2_n2);
9677 }
9678
9679 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9680                                         struct intel_crtc_state *pipe_config)
9681 {
9682         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9683                                      &pipe_config->fdi_m_n, NULL);
9684 }
9685
9686 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9687                                     struct intel_crtc_state *pipe_config)
9688 {
9689         struct drm_device *dev = crtc->base.dev;
9690         struct drm_i915_private *dev_priv = to_i915(dev);
9691         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9692         uint32_t ps_ctrl = 0;
9693         int id = -1;
9694         int i;
9695
9696         /* find scaler attached to this pipe */
9697         for (i = 0; i < crtc->num_scalers; i++) {
9698                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9699                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9700                         id = i;
9701                         pipe_config->pch_pfit.enabled = true;
9702                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9703                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9704                         break;
9705                 }
9706         }
9707
9708         scaler_state->scaler_id = id;
9709         if (id >= 0) {
9710                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9711         } else {
9712                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9713         }
9714 }
9715
9716 static void
9717 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9718                                  struct intel_initial_plane_config *plane_config)
9719 {
9720         struct drm_device *dev = crtc->base.dev;
9721         struct drm_i915_private *dev_priv = to_i915(dev);
9722         u32 val, base, offset, stride_mult, tiling;
9723         int pipe = crtc->pipe;
9724         int fourcc, pixel_format;
9725         unsigned int aligned_height;
9726         struct drm_framebuffer *fb;
9727         struct intel_framebuffer *intel_fb;
9728
9729         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9730         if (!intel_fb) {
9731                 DRM_DEBUG_KMS("failed to alloc fb\n");
9732                 return;
9733         }
9734
9735         fb = &intel_fb->base;
9736
9737         val = I915_READ(PLANE_CTL(pipe, 0));
9738         if (!(val & PLANE_CTL_ENABLE))
9739                 goto error;
9740
9741         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9742         fourcc = skl_format_to_fourcc(pixel_format,
9743                                       val & PLANE_CTL_ORDER_RGBX,
9744                                       val & PLANE_CTL_ALPHA_MASK);
9745         fb->pixel_format = fourcc;
9746         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9747
9748         tiling = val & PLANE_CTL_TILED_MASK;
9749         switch (tiling) {
9750         case PLANE_CTL_TILED_LINEAR:
9751                 fb->modifier = DRM_FORMAT_MOD_NONE;
9752                 break;
9753         case PLANE_CTL_TILED_X:
9754                 plane_config->tiling = I915_TILING_X;
9755                 fb->modifier = I915_FORMAT_MOD_X_TILED;
9756                 break;
9757         case PLANE_CTL_TILED_Y:
9758                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
9759                 break;
9760         case PLANE_CTL_TILED_YF:
9761                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9762                 break;
9763         default:
9764                 MISSING_CASE(tiling);
9765                 goto error;
9766         }
9767
9768         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9769         plane_config->base = base;
9770
9771         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9772
9773         val = I915_READ(PLANE_SIZE(pipe, 0));
9774         fb->height = ((val >> 16) & 0xfff) + 1;
9775         fb->width = ((val >> 0) & 0x1fff) + 1;
9776
9777         val = I915_READ(PLANE_STRIDE(pipe, 0));
9778         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier,
9779                                                 fb->pixel_format);
9780         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9781
9782         aligned_height = intel_fb_align_height(dev, fb->height,
9783                                                fb->pixel_format,
9784                                                fb->modifier);
9785
9786         plane_config->size = fb->pitches[0] * aligned_height;
9787
9788         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9789                       pipe_name(pipe), fb->width, fb->height,
9790                       fb->bits_per_pixel, base, fb->pitches[0],
9791                       plane_config->size);
9792
9793         plane_config->fb = intel_fb;
9794         return;
9795
9796 error:
9797         kfree(intel_fb);
9798 }
9799
9800 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9801                                      struct intel_crtc_state *pipe_config)
9802 {
9803         struct drm_device *dev = crtc->base.dev;
9804         struct drm_i915_private *dev_priv = to_i915(dev);
9805         uint32_t tmp;
9806
9807         tmp = I915_READ(PF_CTL(crtc->pipe));
9808
9809         if (tmp & PF_ENABLE) {
9810                 pipe_config->pch_pfit.enabled = true;
9811                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9812                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9813
9814                 /* We currently do not free assignements of panel fitters on
9815                  * ivb/hsw (since we don't use the higher upscaling modes which
9816                  * differentiates them) so just WARN about this case for now. */
9817                 if (IS_GEN7(dev_priv)) {
9818                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9819                                 PF_PIPE_SEL_IVB(crtc->pipe));
9820                 }
9821         }
9822 }
9823
9824 static void
9825 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9826                                   struct intel_initial_plane_config *plane_config)
9827 {
9828         struct drm_device *dev = crtc->base.dev;
9829         struct drm_i915_private *dev_priv = to_i915(dev);
9830         u32 val, base, offset;
9831         int pipe = crtc->pipe;
9832         int fourcc, pixel_format;
9833         unsigned int aligned_height;
9834         struct drm_framebuffer *fb;
9835         struct intel_framebuffer *intel_fb;
9836
9837         val = I915_READ(DSPCNTR(pipe));
9838         if (!(val & DISPLAY_PLANE_ENABLE))
9839                 return;
9840
9841         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9842         if (!intel_fb) {
9843                 DRM_DEBUG_KMS("failed to alloc fb\n");
9844                 return;
9845         }
9846
9847         fb = &intel_fb->base;
9848
9849         if (INTEL_GEN(dev_priv) >= 4) {
9850                 if (val & DISPPLANE_TILED) {
9851                         plane_config->tiling = I915_TILING_X;
9852                         fb->modifier = I915_FORMAT_MOD_X_TILED;
9853                 }
9854         }
9855
9856         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9857         fourcc = i9xx_format_to_fourcc(pixel_format);
9858         fb->pixel_format = fourcc;
9859         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9860
9861         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9862         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9863                 offset = I915_READ(DSPOFFSET(pipe));
9864         } else {
9865                 if (plane_config->tiling)
9866                         offset = I915_READ(DSPTILEOFF(pipe));
9867                 else
9868                         offset = I915_READ(DSPLINOFF(pipe));
9869         }
9870         plane_config->base = base;
9871
9872         val = I915_READ(PIPESRC(pipe));
9873         fb->width = ((val >> 16) & 0xfff) + 1;
9874         fb->height = ((val >> 0) & 0xfff) + 1;
9875
9876         val = I915_READ(DSPSTRIDE(pipe));
9877         fb->pitches[0] = val & 0xffffffc0;
9878
9879         aligned_height = intel_fb_align_height(dev, fb->height,
9880                                                fb->pixel_format,
9881                                                fb->modifier);
9882
9883         plane_config->size = fb->pitches[0] * aligned_height;
9884
9885         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9886                       pipe_name(pipe), fb->width, fb->height,
9887                       fb->bits_per_pixel, base, fb->pitches[0],
9888                       plane_config->size);
9889
9890         plane_config->fb = intel_fb;
9891 }
9892
9893 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9894                                      struct intel_crtc_state *pipe_config)
9895 {
9896         struct drm_device *dev = crtc->base.dev;
9897         struct drm_i915_private *dev_priv = to_i915(dev);
9898         enum intel_display_power_domain power_domain;
9899         uint32_t tmp;
9900         bool ret;
9901
9902         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9903         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9904                 return false;
9905
9906         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9907         pipe_config->shared_dpll = NULL;
9908
9909         ret = false;
9910         tmp = I915_READ(PIPECONF(crtc->pipe));
9911         if (!(tmp & PIPECONF_ENABLE))
9912                 goto out;
9913
9914         switch (tmp & PIPECONF_BPC_MASK) {
9915         case PIPECONF_6BPC:
9916                 pipe_config->pipe_bpp = 18;
9917                 break;
9918         case PIPECONF_8BPC:
9919                 pipe_config->pipe_bpp = 24;
9920                 break;
9921         case PIPECONF_10BPC:
9922                 pipe_config->pipe_bpp = 30;
9923                 break;
9924         case PIPECONF_12BPC:
9925                 pipe_config->pipe_bpp = 36;
9926                 break;
9927         default:
9928                 break;
9929         }
9930
9931         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9932                 pipe_config->limited_color_range = true;
9933
9934         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9935                 struct intel_shared_dpll *pll;
9936                 enum intel_dpll_id pll_id;
9937
9938                 pipe_config->has_pch_encoder = true;
9939
9940                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9941                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9942                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9943
9944                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9945
9946                 if (HAS_PCH_IBX(dev_priv)) {
9947                         /*
9948                          * The pipe->pch transcoder and pch transcoder->pll
9949                          * mapping is fixed.
9950                          */
9951                         pll_id = (enum intel_dpll_id) crtc->pipe;
9952                 } else {
9953                         tmp = I915_READ(PCH_DPLL_SEL);
9954                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9955                                 pll_id = DPLL_ID_PCH_PLL_B;
9956                         else
9957                                 pll_id= DPLL_ID_PCH_PLL_A;
9958                 }
9959
9960                 pipe_config->shared_dpll =
9961                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9962                 pll = pipe_config->shared_dpll;
9963
9964                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9965                                                  &pipe_config->dpll_hw_state));
9966
9967                 tmp = pipe_config->dpll_hw_state.dpll;
9968                 pipe_config->pixel_multiplier =
9969                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9970                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9971
9972                 ironlake_pch_clock_get(crtc, pipe_config);
9973         } else {
9974                 pipe_config->pixel_multiplier = 1;
9975         }
9976
9977         intel_get_pipe_timings(crtc, pipe_config);
9978         intel_get_pipe_src_size(crtc, pipe_config);
9979
9980         ironlake_get_pfit_config(crtc, pipe_config);
9981
9982         ret = true;
9983
9984 out:
9985         intel_display_power_put(dev_priv, power_domain);
9986
9987         return ret;
9988 }
9989
9990 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9991 {
9992         struct drm_device *dev = &dev_priv->drm;
9993         struct intel_crtc *crtc;
9994
9995         for_each_intel_crtc(dev, crtc)
9996                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9997                      pipe_name(crtc->pipe));
9998
9999         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10000         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10001         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10002         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10003         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10004         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10005              "CPU PWM1 enabled\n");
10006         if (IS_HASWELL(dev_priv))
10007                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10008                      "CPU PWM2 enabled\n");
10009         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10010              "PCH PWM1 enabled\n");
10011         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10012              "Utility pin enabled\n");
10013         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10014
10015         /*
10016          * In theory we can still leave IRQs enabled, as long as only the HPD
10017          * interrupts remain enabled. We used to check for that, but since it's
10018          * gen-specific and since we only disable LCPLL after we fully disable
10019          * the interrupts, the check below should be enough.
10020          */
10021         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10022 }
10023
10024 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10025 {
10026         if (IS_HASWELL(dev_priv))
10027                 return I915_READ(D_COMP_HSW);
10028         else
10029                 return I915_READ(D_COMP_BDW);
10030 }
10031
10032 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10033 {
10034         if (IS_HASWELL(dev_priv)) {
10035                 mutex_lock(&dev_priv->rps.hw_lock);
10036                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10037                                             val))
10038                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10039                 mutex_unlock(&dev_priv->rps.hw_lock);
10040         } else {
10041                 I915_WRITE(D_COMP_BDW, val);
10042                 POSTING_READ(D_COMP_BDW);
10043         }
10044 }
10045
10046 /*
10047  * This function implements pieces of two sequences from BSpec:
10048  * - Sequence for display software to disable LCPLL
10049  * - Sequence for display software to allow package C8+
10050  * The steps implemented here are just the steps that actually touch the LCPLL
10051  * register. Callers should take care of disabling all the display engine
10052  * functions, doing the mode unset, fixing interrupts, etc.
10053  */
10054 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10055                               bool switch_to_fclk, bool allow_power_down)
10056 {
10057         uint32_t val;
10058
10059         assert_can_disable_lcpll(dev_priv);
10060
10061         val = I915_READ(LCPLL_CTL);
10062
10063         if (switch_to_fclk) {
10064                 val |= LCPLL_CD_SOURCE_FCLK;
10065                 I915_WRITE(LCPLL_CTL, val);
10066
10067                 if (wait_for_us(I915_READ(LCPLL_CTL) &
10068                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10069                         DRM_ERROR("Switching to FCLK failed\n");
10070
10071                 val = I915_READ(LCPLL_CTL);
10072         }
10073
10074         val |= LCPLL_PLL_DISABLE;
10075         I915_WRITE(LCPLL_CTL, val);
10076         POSTING_READ(LCPLL_CTL);
10077
10078         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10079                 DRM_ERROR("LCPLL still locked\n");
10080
10081         val = hsw_read_dcomp(dev_priv);
10082         val |= D_COMP_COMP_DISABLE;
10083         hsw_write_dcomp(dev_priv, val);
10084         ndelay(100);
10085
10086         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10087                      1))
10088                 DRM_ERROR("D_COMP RCOMP still in progress\n");
10089
10090         if (allow_power_down) {
10091                 val = I915_READ(LCPLL_CTL);
10092                 val |= LCPLL_POWER_DOWN_ALLOW;
10093                 I915_WRITE(LCPLL_CTL, val);
10094                 POSTING_READ(LCPLL_CTL);
10095         }
10096 }
10097
10098 /*
10099  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10100  * source.
10101  */
10102 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10103 {
10104         uint32_t val;
10105
10106         val = I915_READ(LCPLL_CTL);
10107
10108         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10109                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10110                 return;
10111
10112         /*
10113          * Make sure we're not on PC8 state before disabling PC8, otherwise
10114          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10115          */
10116         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10117
10118         if (val & LCPLL_POWER_DOWN_ALLOW) {
10119                 val &= ~LCPLL_POWER_DOWN_ALLOW;
10120                 I915_WRITE(LCPLL_CTL, val);
10121                 POSTING_READ(LCPLL_CTL);
10122         }
10123
10124         val = hsw_read_dcomp(dev_priv);
10125         val |= D_COMP_COMP_FORCE;
10126         val &= ~D_COMP_COMP_DISABLE;
10127         hsw_write_dcomp(dev_priv, val);
10128
10129         val = I915_READ(LCPLL_CTL);
10130         val &= ~LCPLL_PLL_DISABLE;
10131         I915_WRITE(LCPLL_CTL, val);
10132
10133         if (intel_wait_for_register(dev_priv,
10134                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10135                                     5))
10136                 DRM_ERROR("LCPLL not locked yet\n");
10137
10138         if (val & LCPLL_CD_SOURCE_FCLK) {
10139                 val = I915_READ(LCPLL_CTL);
10140                 val &= ~LCPLL_CD_SOURCE_FCLK;
10141                 I915_WRITE(LCPLL_CTL, val);
10142
10143                 if (wait_for_us((I915_READ(LCPLL_CTL) &
10144                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10145                         DRM_ERROR("Switching back to LCPLL failed\n");
10146         }
10147
10148         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10149         intel_update_cdclk(dev_priv);
10150 }
10151
10152 /*
10153  * Package states C8 and deeper are really deep PC states that can only be
10154  * reached when all the devices on the system allow it, so even if the graphics
10155  * device allows PC8+, it doesn't mean the system will actually get to these
10156  * states. Our driver only allows PC8+ when going into runtime PM.
10157  *
10158  * The requirements for PC8+ are that all the outputs are disabled, the power
10159  * well is disabled and most interrupts are disabled, and these are also
10160  * requirements for runtime PM. When these conditions are met, we manually do
10161  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10162  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10163  * hang the machine.
10164  *
10165  * When we really reach PC8 or deeper states (not just when we allow it) we lose
10166  * the state of some registers, so when we come back from PC8+ we need to
10167  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10168  * need to take care of the registers kept by RC6. Notice that this happens even
10169  * if we don't put the device in PCI D3 state (which is what currently happens
10170  * because of the runtime PM support).
10171  *
10172  * For more, read "Display Sequences for Package C8" on the hardware
10173  * documentation.
10174  */
10175 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10176 {
10177         struct drm_device *dev = &dev_priv->drm;
10178         uint32_t val;
10179
10180         DRM_DEBUG_KMS("Enabling package C8+\n");
10181
10182         if (HAS_PCH_LPT_LP(dev_priv)) {
10183                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10184                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10185                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10186         }
10187
10188         lpt_disable_clkout_dp(dev);
10189         hsw_disable_lcpll(dev_priv, true, true);
10190 }
10191
10192 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10193 {
10194         struct drm_device *dev = &dev_priv->drm;
10195         uint32_t val;
10196
10197         DRM_DEBUG_KMS("Disabling package C8+\n");
10198
10199         hsw_restore_lcpll(dev_priv);
10200         lpt_init_pch_refclk(dev);
10201
10202         if (HAS_PCH_LPT_LP(dev_priv)) {
10203                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10204                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10205                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10206         }
10207 }
10208
10209 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10210 {
10211         struct drm_device *dev = old_state->dev;
10212         struct intel_atomic_state *old_intel_state =
10213                 to_intel_atomic_state(old_state);
10214         unsigned int req_cdclk = old_intel_state->dev_cdclk;
10215
10216         bxt_set_cdclk(to_i915(dev), req_cdclk);
10217 }
10218
10219 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
10220                                           int pixel_rate)
10221 {
10222         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
10223
10224         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10225         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10226                 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10227
10228         /* BSpec says "Do not use DisplayPort with CDCLK less than
10229          * 432 MHz, audio enabled, port width x4, and link rate
10230          * HBR2 (5.4 GHz), or else there may be audio corruption or
10231          * screen corruption."
10232          */
10233         if (intel_crtc_has_dp_encoder(crtc_state) &&
10234             crtc_state->has_audio &&
10235             crtc_state->port_clock >= 540000 &&
10236             crtc_state->lane_count == 4)
10237                 pixel_rate = max(432000, pixel_rate);
10238
10239         return pixel_rate;
10240 }
10241
10242 /* compute the max rate for new configuration */
10243 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10244 {
10245         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10246         struct drm_i915_private *dev_priv = to_i915(state->dev);
10247         struct drm_crtc *crtc;
10248         struct drm_crtc_state *cstate;
10249         struct intel_crtc_state *crtc_state;
10250         unsigned max_pixel_rate = 0, i;
10251         enum pipe pipe;
10252
10253         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10254                sizeof(intel_state->min_pixclk));
10255
10256         for_each_crtc_in_state(state, crtc, cstate, i) {
10257                 int pixel_rate;
10258
10259                 crtc_state = to_intel_crtc_state(cstate);
10260                 if (!crtc_state->base.enable) {
10261                         intel_state->min_pixclk[i] = 0;
10262                         continue;
10263                 }
10264
10265                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10266
10267                 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
10268                         pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
10269                                                                     pixel_rate);
10270
10271                 intel_state->min_pixclk[i] = pixel_rate;
10272         }
10273
10274         for_each_pipe(dev_priv, pipe)
10275                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10276
10277         return max_pixel_rate;
10278 }
10279
10280 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10281 {
10282         struct drm_i915_private *dev_priv = to_i915(dev);
10283         uint32_t val, data;
10284         int ret;
10285
10286         if (WARN((I915_READ(LCPLL_CTL) &
10287                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10288                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10289                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10290                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10291                  "trying to change cdclk frequency with cdclk not enabled\n"))
10292                 return;
10293
10294         mutex_lock(&dev_priv->rps.hw_lock);
10295         ret = sandybridge_pcode_write(dev_priv,
10296                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10297         mutex_unlock(&dev_priv->rps.hw_lock);
10298         if (ret) {
10299                 DRM_ERROR("failed to inform pcode about cdclk change\n");
10300                 return;
10301         }
10302
10303         val = I915_READ(LCPLL_CTL);
10304         val |= LCPLL_CD_SOURCE_FCLK;
10305         I915_WRITE(LCPLL_CTL, val);
10306
10307         if (wait_for_us(I915_READ(LCPLL_CTL) &
10308                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
10309                 DRM_ERROR("Switching to FCLK failed\n");
10310
10311         val = I915_READ(LCPLL_CTL);
10312         val &= ~LCPLL_CLK_FREQ_MASK;
10313
10314         switch (cdclk) {
10315         case 450000:
10316                 val |= LCPLL_CLK_FREQ_450;
10317                 data = 0;
10318                 break;
10319         case 540000:
10320                 val |= LCPLL_CLK_FREQ_54O_BDW;
10321                 data = 1;
10322                 break;
10323         case 337500:
10324                 val |= LCPLL_CLK_FREQ_337_5_BDW;
10325                 data = 2;
10326                 break;
10327         case 675000:
10328                 val |= LCPLL_CLK_FREQ_675_BDW;
10329                 data = 3;
10330                 break;
10331         default:
10332                 WARN(1, "invalid cdclk frequency\n");
10333                 return;
10334         }
10335
10336         I915_WRITE(LCPLL_CTL, val);
10337
10338         val = I915_READ(LCPLL_CTL);
10339         val &= ~LCPLL_CD_SOURCE_FCLK;
10340         I915_WRITE(LCPLL_CTL, val);
10341
10342         if (wait_for_us((I915_READ(LCPLL_CTL) &
10343                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10344                 DRM_ERROR("Switching back to LCPLL failed\n");
10345
10346         mutex_lock(&dev_priv->rps.hw_lock);
10347         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10348         mutex_unlock(&dev_priv->rps.hw_lock);
10349
10350         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10351
10352         intel_update_cdclk(dev_priv);
10353
10354         WARN(cdclk != dev_priv->cdclk_freq,
10355              "cdclk requested %d kHz but got %d kHz\n",
10356              cdclk, dev_priv->cdclk_freq);
10357 }
10358
10359 static int broadwell_calc_cdclk(int max_pixclk)
10360 {
10361         if (max_pixclk > 540000)
10362                 return 675000;
10363         else if (max_pixclk > 450000)
10364                 return 540000;
10365         else if (max_pixclk > 337500)
10366                 return 450000;
10367         else
10368                 return 337500;
10369 }
10370
10371 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10372 {
10373         struct drm_i915_private *dev_priv = to_i915(state->dev);
10374         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10375         int max_pixclk = ilk_max_pixel_rate(state);
10376         int cdclk;
10377
10378         /*
10379          * FIXME should also account for plane ratio
10380          * once 64bpp pixel formats are supported.
10381          */
10382         cdclk = broadwell_calc_cdclk(max_pixclk);
10383
10384         if (cdclk > dev_priv->max_cdclk_freq) {
10385                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10386                               cdclk, dev_priv->max_cdclk_freq);
10387                 return -EINVAL;
10388         }
10389
10390         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10391         if (!intel_state->active_crtcs)
10392                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10393
10394         return 0;
10395 }
10396
10397 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10398 {
10399         struct drm_device *dev = old_state->dev;
10400         struct intel_atomic_state *old_intel_state =
10401                 to_intel_atomic_state(old_state);
10402         unsigned req_cdclk = old_intel_state->dev_cdclk;
10403
10404         broadwell_set_cdclk(dev, req_cdclk);
10405 }
10406
10407 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10408 {
10409         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10410         struct drm_i915_private *dev_priv = to_i915(state->dev);
10411         const int max_pixclk = ilk_max_pixel_rate(state);
10412         int vco = intel_state->cdclk_pll_vco;
10413         int cdclk;
10414
10415         /*
10416          * FIXME should also account for plane ratio
10417          * once 64bpp pixel formats are supported.
10418          */
10419         cdclk = skl_calc_cdclk(max_pixclk, vco);
10420
10421         /*
10422          * FIXME move the cdclk caclulation to
10423          * compute_config() so we can fail gracegully.
10424          */
10425         if (cdclk > dev_priv->max_cdclk_freq) {
10426                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10427                           cdclk, dev_priv->max_cdclk_freq);
10428                 cdclk = dev_priv->max_cdclk_freq;
10429         }
10430
10431         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10432         if (!intel_state->active_crtcs)
10433                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10434
10435         return 0;
10436 }
10437
10438 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10439 {
10440         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10441         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10442         unsigned int req_cdclk = intel_state->dev_cdclk;
10443         unsigned int req_vco = intel_state->cdclk_pll_vco;
10444
10445         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10446 }
10447
10448 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10449                                       struct intel_crtc_state *crtc_state)
10450 {
10451         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10452                 if (!intel_ddi_pll_select(crtc, crtc_state))
10453                         return -EINVAL;
10454         }
10455
10456         crtc->lowfreq_avail = false;
10457
10458         return 0;
10459 }
10460
10461 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10462                                 enum port port,
10463                                 struct intel_crtc_state *pipe_config)
10464 {
10465         enum intel_dpll_id id;
10466
10467         switch (port) {
10468         case PORT_A:
10469                 id = DPLL_ID_SKL_DPLL0;
10470                 break;
10471         case PORT_B:
10472                 id = DPLL_ID_SKL_DPLL1;
10473                 break;
10474         case PORT_C:
10475                 id = DPLL_ID_SKL_DPLL2;
10476                 break;
10477         default:
10478                 DRM_ERROR("Incorrect port type\n");
10479                 return;
10480         }
10481
10482         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10483 }
10484
10485 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10486                                 enum port port,
10487                                 struct intel_crtc_state *pipe_config)
10488 {
10489         enum intel_dpll_id id;
10490         u32 temp;
10491
10492         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10493         id = temp >> (port * 3 + 1);
10494
10495         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10496                 return;
10497
10498         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10499 }
10500
10501 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10502                                 enum port port,
10503                                 struct intel_crtc_state *pipe_config)
10504 {
10505         enum intel_dpll_id id;
10506         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10507
10508         switch (ddi_pll_sel) {
10509         case PORT_CLK_SEL_WRPLL1:
10510                 id = DPLL_ID_WRPLL1;
10511                 break;
10512         case PORT_CLK_SEL_WRPLL2:
10513                 id = DPLL_ID_WRPLL2;
10514                 break;
10515         case PORT_CLK_SEL_SPLL:
10516                 id = DPLL_ID_SPLL;
10517                 break;
10518         case PORT_CLK_SEL_LCPLL_810:
10519                 id = DPLL_ID_LCPLL_810;
10520                 break;
10521         case PORT_CLK_SEL_LCPLL_1350:
10522                 id = DPLL_ID_LCPLL_1350;
10523                 break;
10524         case PORT_CLK_SEL_LCPLL_2700:
10525                 id = DPLL_ID_LCPLL_2700;
10526                 break;
10527         default:
10528                 MISSING_CASE(ddi_pll_sel);
10529                 /* fall through */
10530         case PORT_CLK_SEL_NONE:
10531                 return;
10532         }
10533
10534         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10535 }
10536
10537 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10538                                      struct intel_crtc_state *pipe_config,
10539                                      unsigned long *power_domain_mask)
10540 {
10541         struct drm_device *dev = crtc->base.dev;
10542         struct drm_i915_private *dev_priv = to_i915(dev);
10543         enum intel_display_power_domain power_domain;
10544         u32 tmp;
10545
10546         /*
10547          * The pipe->transcoder mapping is fixed with the exception of the eDP
10548          * transcoder handled below.
10549          */
10550         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10551
10552         /*
10553          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10554          * consistency and less surprising code; it's in always on power).
10555          */
10556         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10557         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10558                 enum pipe trans_edp_pipe;
10559                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10560                 default:
10561                         WARN(1, "unknown pipe linked to edp transcoder\n");
10562                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10563                 case TRANS_DDI_EDP_INPUT_A_ON:
10564                         trans_edp_pipe = PIPE_A;
10565                         break;
10566                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10567                         trans_edp_pipe = PIPE_B;
10568                         break;
10569                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10570                         trans_edp_pipe = PIPE_C;
10571                         break;
10572                 }
10573
10574                 if (trans_edp_pipe == crtc->pipe)
10575                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10576         }
10577
10578         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10579         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10580                 return false;
10581         *power_domain_mask |= BIT(power_domain);
10582
10583         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10584
10585         return tmp & PIPECONF_ENABLE;
10586 }
10587
10588 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10589                                          struct intel_crtc_state *pipe_config,
10590                                          unsigned long *power_domain_mask)
10591 {
10592         struct drm_device *dev = crtc->base.dev;
10593         struct drm_i915_private *dev_priv = to_i915(dev);
10594         enum intel_display_power_domain power_domain;
10595         enum port port;
10596         enum transcoder cpu_transcoder;
10597         u32 tmp;
10598
10599         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10600                 if (port == PORT_A)
10601                         cpu_transcoder = TRANSCODER_DSI_A;
10602                 else
10603                         cpu_transcoder = TRANSCODER_DSI_C;
10604
10605                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10606                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10607                         continue;
10608                 *power_domain_mask |= BIT(power_domain);
10609
10610                 /*
10611                  * The PLL needs to be enabled with a valid divider
10612                  * configuration, otherwise accessing DSI registers will hang
10613                  * the machine. See BSpec North Display Engine
10614                  * registers/MIPI[BXT]. We can break out here early, since we
10615                  * need the same DSI PLL to be enabled for both DSI ports.
10616                  */
10617                 if (!intel_dsi_pll_is_enabled(dev_priv))
10618                         break;
10619
10620                 /* XXX: this works for video mode only */
10621                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10622                 if (!(tmp & DPI_ENABLE))
10623                         continue;
10624
10625                 tmp = I915_READ(MIPI_CTRL(port));
10626                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10627                         continue;
10628
10629                 pipe_config->cpu_transcoder = cpu_transcoder;
10630                 break;
10631         }
10632
10633         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10634 }
10635
10636 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10637                                        struct intel_crtc_state *pipe_config)
10638 {
10639         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10640         struct intel_shared_dpll *pll;
10641         enum port port;
10642         uint32_t tmp;
10643
10644         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10645
10646         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10647
10648         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
10649                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10650         else if (IS_BROXTON(dev_priv))
10651                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10652         else
10653                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10654
10655         pll = pipe_config->shared_dpll;
10656         if (pll) {
10657                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10658                                                  &pipe_config->dpll_hw_state));
10659         }
10660
10661         /*
10662          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10663          * DDI E. So just check whether this pipe is wired to DDI E and whether
10664          * the PCH transcoder is on.
10665          */
10666         if (INTEL_GEN(dev_priv) < 9 &&
10667             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10668                 pipe_config->has_pch_encoder = true;
10669
10670                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10671                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10672                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10673
10674                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10675         }
10676 }
10677
10678 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10679                                     struct intel_crtc_state *pipe_config)
10680 {
10681         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10682         enum intel_display_power_domain power_domain;
10683         unsigned long power_domain_mask;
10684         bool active;
10685
10686         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10687         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10688                 return false;
10689         power_domain_mask = BIT(power_domain);
10690
10691         pipe_config->shared_dpll = NULL;
10692
10693         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10694
10695         if (IS_BROXTON(dev_priv) &&
10696             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10697                 WARN_ON(active);
10698                 active = true;
10699         }
10700
10701         if (!active)
10702                 goto out;
10703
10704         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10705                 haswell_get_ddi_port_state(crtc, pipe_config);
10706                 intel_get_pipe_timings(crtc, pipe_config);
10707         }
10708
10709         intel_get_pipe_src_size(crtc, pipe_config);
10710
10711         pipe_config->gamma_mode =
10712                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10713
10714         if (INTEL_GEN(dev_priv) >= 9) {
10715                 skl_init_scalers(dev_priv, crtc, pipe_config);
10716
10717                 pipe_config->scaler_state.scaler_id = -1;
10718                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10719         }
10720
10721         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10722         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10723                 power_domain_mask |= BIT(power_domain);
10724                 if (INTEL_GEN(dev_priv) >= 9)
10725                         skylake_get_pfit_config(crtc, pipe_config);
10726                 else
10727                         ironlake_get_pfit_config(crtc, pipe_config);
10728         }
10729
10730         if (IS_HASWELL(dev_priv))
10731                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10732                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10733
10734         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10735             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10736                 pipe_config->pixel_multiplier =
10737                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10738         } else {
10739                 pipe_config->pixel_multiplier = 1;
10740         }
10741
10742 out:
10743         for_each_power_domain(power_domain, power_domain_mask)
10744                 intel_display_power_put(dev_priv, power_domain);
10745
10746         return active;
10747 }
10748
10749 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10750                                const struct intel_plane_state *plane_state)
10751 {
10752         struct drm_device *dev = crtc->dev;
10753         struct drm_i915_private *dev_priv = to_i915(dev);
10754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10755         uint32_t cntl = 0, size = 0;
10756
10757         if (plane_state && plane_state->base.visible) {
10758                 unsigned int width = plane_state->base.crtc_w;
10759                 unsigned int height = plane_state->base.crtc_h;
10760                 unsigned int stride = roundup_pow_of_two(width) * 4;
10761
10762                 switch (stride) {
10763                 default:
10764                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10765                                   width, stride);
10766                         stride = 256;
10767                         /* fallthrough */
10768                 case 256:
10769                 case 512:
10770                 case 1024:
10771                 case 2048:
10772                         break;
10773                 }
10774
10775                 cntl |= CURSOR_ENABLE |
10776                         CURSOR_GAMMA_ENABLE |
10777                         CURSOR_FORMAT_ARGB |
10778                         CURSOR_STRIDE(stride);
10779
10780                 size = (height << 12) | width;
10781         }
10782
10783         if (intel_crtc->cursor_cntl != 0 &&
10784             (intel_crtc->cursor_base != base ||
10785              intel_crtc->cursor_size != size ||
10786              intel_crtc->cursor_cntl != cntl)) {
10787                 /* On these chipsets we can only modify the base/size/stride
10788                  * whilst the cursor is disabled.
10789                  */
10790                 I915_WRITE(CURCNTR(PIPE_A), 0);
10791                 POSTING_READ(CURCNTR(PIPE_A));
10792                 intel_crtc->cursor_cntl = 0;
10793         }
10794
10795         if (intel_crtc->cursor_base != base) {
10796                 I915_WRITE(CURBASE(PIPE_A), base);
10797                 intel_crtc->cursor_base = base;
10798         }
10799
10800         if (intel_crtc->cursor_size != size) {
10801                 I915_WRITE(CURSIZE, size);
10802                 intel_crtc->cursor_size = size;
10803         }
10804
10805         if (intel_crtc->cursor_cntl != cntl) {
10806                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10807                 POSTING_READ(CURCNTR(PIPE_A));
10808                 intel_crtc->cursor_cntl = cntl;
10809         }
10810 }
10811
10812 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10813                                const struct intel_plane_state *plane_state)
10814 {
10815         struct drm_device *dev = crtc->dev;
10816         struct drm_i915_private *dev_priv = to_i915(dev);
10817         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10818         int pipe = intel_crtc->pipe;
10819         uint32_t cntl = 0;
10820
10821         if (plane_state && plane_state->base.visible) {
10822                 cntl = MCURSOR_GAMMA_ENABLE;
10823                 switch (plane_state->base.crtc_w) {
10824                         case 64:
10825                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10826                                 break;
10827                         case 128:
10828                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10829                                 break;
10830                         case 256:
10831                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10832                                 break;
10833                         default:
10834                                 MISSING_CASE(plane_state->base.crtc_w);
10835                                 return;
10836                 }
10837                 cntl |= pipe << 28; /* Connect to correct pipe */
10838
10839                 if (HAS_DDI(dev_priv))
10840                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10841
10842                 if (plane_state->base.rotation & DRM_ROTATE_180)
10843                         cntl |= CURSOR_ROTATE_180;
10844         }
10845
10846         if (intel_crtc->cursor_cntl != cntl) {
10847                 I915_WRITE(CURCNTR(pipe), cntl);
10848                 POSTING_READ(CURCNTR(pipe));
10849                 intel_crtc->cursor_cntl = cntl;
10850         }
10851
10852         /* and commit changes on next vblank */
10853         I915_WRITE(CURBASE(pipe), base);
10854         POSTING_READ(CURBASE(pipe));
10855
10856         intel_crtc->cursor_base = base;
10857 }
10858
10859 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10860 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10861                                      const struct intel_plane_state *plane_state)
10862 {
10863         struct drm_device *dev = crtc->dev;
10864         struct drm_i915_private *dev_priv = to_i915(dev);
10865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10866         int pipe = intel_crtc->pipe;
10867         u32 base = intel_crtc->cursor_addr;
10868         u32 pos = 0;
10869
10870         if (plane_state) {
10871                 int x = plane_state->base.crtc_x;
10872                 int y = plane_state->base.crtc_y;
10873
10874                 if (x < 0) {
10875                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10876                         x = -x;
10877                 }
10878                 pos |= x << CURSOR_X_SHIFT;
10879
10880                 if (y < 0) {
10881                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10882                         y = -y;
10883                 }
10884                 pos |= y << CURSOR_Y_SHIFT;
10885
10886                 /* ILK+ do this automagically */
10887                 if (HAS_GMCH_DISPLAY(dev_priv) &&
10888                     plane_state->base.rotation & DRM_ROTATE_180) {
10889                         base += (plane_state->base.crtc_h *
10890                                  plane_state->base.crtc_w - 1) * 4;
10891                 }
10892         }
10893
10894         I915_WRITE(CURPOS(pipe), pos);
10895
10896         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
10897                 i845_update_cursor(crtc, base, plane_state);
10898         else
10899                 i9xx_update_cursor(crtc, base, plane_state);
10900 }
10901
10902 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
10903                            uint32_t width, uint32_t height)
10904 {
10905         if (width == 0 || height == 0)
10906                 return false;
10907
10908         /*
10909          * 845g/865g are special in that they are only limited by
10910          * the width of their cursors, the height is arbitrary up to
10911          * the precision of the register. Everything else requires
10912          * square cursors, limited to a few power-of-two sizes.
10913          */
10914         if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
10915                 if ((width & 63) != 0)
10916                         return false;
10917
10918                 if (width > (IS_845G(dev_priv) ? 64 : 512))
10919                         return false;
10920
10921                 if (height > 1023)
10922                         return false;
10923         } else {
10924                 switch (width | height) {
10925                 case 256:
10926                 case 128:
10927                         if (IS_GEN2(dev_priv))
10928                                 return false;
10929                 case 64:
10930                         break;
10931                 default:
10932                         return false;
10933                 }
10934         }
10935
10936         return true;
10937 }
10938
10939 /* VESA 640x480x72Hz mode to set on the pipe */
10940 static struct drm_display_mode load_detect_mode = {
10941         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10942                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10943 };
10944
10945 struct drm_framebuffer *
10946 __intel_framebuffer_create(struct drm_device *dev,
10947                            struct drm_mode_fb_cmd2 *mode_cmd,
10948                            struct drm_i915_gem_object *obj)
10949 {
10950         struct intel_framebuffer *intel_fb;
10951         int ret;
10952
10953         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10954         if (!intel_fb)
10955                 return ERR_PTR(-ENOMEM);
10956
10957         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10958         if (ret)
10959                 goto err;
10960
10961         return &intel_fb->base;
10962
10963 err:
10964         kfree(intel_fb);
10965         return ERR_PTR(ret);
10966 }
10967
10968 static struct drm_framebuffer *
10969 intel_framebuffer_create(struct drm_device *dev,
10970                          struct drm_mode_fb_cmd2 *mode_cmd,
10971                          struct drm_i915_gem_object *obj)
10972 {
10973         struct drm_framebuffer *fb;
10974         int ret;
10975
10976         ret = i915_mutex_lock_interruptible(dev);
10977         if (ret)
10978                 return ERR_PTR(ret);
10979         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10980         mutex_unlock(&dev->struct_mutex);
10981
10982         return fb;
10983 }
10984
10985 static u32
10986 intel_framebuffer_pitch_for_width(int width, int bpp)
10987 {
10988         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10989         return ALIGN(pitch, 64);
10990 }
10991
10992 static u32
10993 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10994 {
10995         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10996         return PAGE_ALIGN(pitch * mode->vdisplay);
10997 }
10998
10999 static struct drm_framebuffer *
11000 intel_framebuffer_create_for_mode(struct drm_device *dev,
11001                                   struct drm_display_mode *mode,
11002                                   int depth, int bpp)
11003 {
11004         struct drm_framebuffer *fb;
11005         struct drm_i915_gem_object *obj;
11006         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
11007
11008         obj = i915_gem_object_create(dev,
11009                                     intel_framebuffer_size_for_mode(mode, bpp));
11010         if (IS_ERR(obj))
11011                 return ERR_CAST(obj);
11012
11013         mode_cmd.width = mode->hdisplay;
11014         mode_cmd.height = mode->vdisplay;
11015         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11016                                                                 bpp);
11017         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11018
11019         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11020         if (IS_ERR(fb))
11021                 i915_gem_object_put(obj);
11022
11023         return fb;
11024 }
11025
11026 static struct drm_framebuffer *
11027 mode_fits_in_fbdev(struct drm_device *dev,
11028                    struct drm_display_mode *mode)
11029 {
11030 #ifdef CONFIG_DRM_FBDEV_EMULATION
11031         struct drm_i915_private *dev_priv = to_i915(dev);
11032         struct drm_i915_gem_object *obj;
11033         struct drm_framebuffer *fb;
11034
11035         if (!dev_priv->fbdev)
11036                 return NULL;
11037
11038         if (!dev_priv->fbdev->fb)
11039                 return NULL;
11040
11041         obj = dev_priv->fbdev->fb->obj;
11042         BUG_ON(!obj);
11043
11044         fb = &dev_priv->fbdev->fb->base;
11045         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11046                                                                fb->bits_per_pixel))
11047                 return NULL;
11048
11049         if (obj->base.size < mode->vdisplay * fb->pitches[0])
11050                 return NULL;
11051
11052         drm_framebuffer_reference(fb);
11053         return fb;
11054 #else
11055         return NULL;
11056 #endif
11057 }
11058
11059 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11060                                            struct drm_crtc *crtc,
11061                                            struct drm_display_mode *mode,
11062                                            struct drm_framebuffer *fb,
11063                                            int x, int y)
11064 {
11065         struct drm_plane_state *plane_state;
11066         int hdisplay, vdisplay;
11067         int ret;
11068
11069         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11070         if (IS_ERR(plane_state))
11071                 return PTR_ERR(plane_state);
11072
11073         if (mode)
11074                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11075         else
11076                 hdisplay = vdisplay = 0;
11077
11078         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11079         if (ret)
11080                 return ret;
11081         drm_atomic_set_fb_for_plane(plane_state, fb);
11082         plane_state->crtc_x = 0;
11083         plane_state->crtc_y = 0;
11084         plane_state->crtc_w = hdisplay;
11085         plane_state->crtc_h = vdisplay;
11086         plane_state->src_x = x << 16;
11087         plane_state->src_y = y << 16;
11088         plane_state->src_w = hdisplay << 16;
11089         plane_state->src_h = vdisplay << 16;
11090
11091         return 0;
11092 }
11093
11094 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11095                                 struct drm_display_mode *mode,
11096                                 struct intel_load_detect_pipe *old,
11097                                 struct drm_modeset_acquire_ctx *ctx)
11098 {
11099         struct intel_crtc *intel_crtc;
11100         struct intel_encoder *intel_encoder =
11101                 intel_attached_encoder(connector);
11102         struct drm_crtc *possible_crtc;
11103         struct drm_encoder *encoder = &intel_encoder->base;
11104         struct drm_crtc *crtc = NULL;
11105         struct drm_device *dev = encoder->dev;
11106         struct drm_i915_private *dev_priv = to_i915(dev);
11107         struct drm_framebuffer *fb;
11108         struct drm_mode_config *config = &dev->mode_config;
11109         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11110         struct drm_connector_state *connector_state;
11111         struct intel_crtc_state *crtc_state;
11112         int ret, i = -1;
11113
11114         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11115                       connector->base.id, connector->name,
11116                       encoder->base.id, encoder->name);
11117
11118         old->restore_state = NULL;
11119
11120 retry:
11121         ret = drm_modeset_lock(&config->connection_mutex, ctx);
11122         if (ret)
11123                 goto fail;
11124
11125         /*
11126          * Algorithm gets a little messy:
11127          *
11128          *   - if the connector already has an assigned crtc, use it (but make
11129          *     sure it's on first)
11130          *
11131          *   - try to find the first unused crtc that can drive this connector,
11132          *     and use that if we find one
11133          */
11134
11135         /* See if we already have a CRTC for this connector */
11136         if (connector->state->crtc) {
11137                 crtc = connector->state->crtc;
11138
11139                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11140                 if (ret)
11141                         goto fail;
11142
11143                 /* Make sure the crtc and connector are running */
11144                 goto found;
11145         }
11146
11147         /* Find an unused one (if possible) */
11148         for_each_crtc(dev, possible_crtc) {
11149                 i++;
11150                 if (!(encoder->possible_crtcs & (1 << i)))
11151                         continue;
11152
11153                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11154                 if (ret)
11155                         goto fail;
11156
11157                 if (possible_crtc->state->enable) {
11158                         drm_modeset_unlock(&possible_crtc->mutex);
11159                         continue;
11160                 }
11161
11162                 crtc = possible_crtc;
11163                 break;
11164         }
11165
11166         /*
11167          * If we didn't find an unused CRTC, don't use any.
11168          */
11169         if (!crtc) {
11170                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11171                 goto fail;
11172         }
11173
11174 found:
11175         intel_crtc = to_intel_crtc(crtc);
11176
11177         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11178         if (ret)
11179                 goto fail;
11180
11181         state = drm_atomic_state_alloc(dev);
11182         restore_state = drm_atomic_state_alloc(dev);
11183         if (!state || !restore_state) {
11184                 ret = -ENOMEM;
11185                 goto fail;
11186         }
11187
11188         state->acquire_ctx = ctx;
11189         restore_state->acquire_ctx = ctx;
11190
11191         connector_state = drm_atomic_get_connector_state(state, connector);
11192         if (IS_ERR(connector_state)) {
11193                 ret = PTR_ERR(connector_state);
11194                 goto fail;
11195         }
11196
11197         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11198         if (ret)
11199                 goto fail;
11200
11201         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11202         if (IS_ERR(crtc_state)) {
11203                 ret = PTR_ERR(crtc_state);
11204                 goto fail;
11205         }
11206
11207         crtc_state->base.active = crtc_state->base.enable = true;
11208
11209         if (!mode)
11210                 mode = &load_detect_mode;
11211
11212         /* We need a framebuffer large enough to accommodate all accesses
11213          * that the plane may generate whilst we perform load detection.
11214          * We can not rely on the fbcon either being present (we get called
11215          * during its initialisation to detect all boot displays, or it may
11216          * not even exist) or that it is large enough to satisfy the
11217          * requested mode.
11218          */
11219         fb = mode_fits_in_fbdev(dev, mode);
11220         if (fb == NULL) {
11221                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11222                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11223         } else
11224                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11225         if (IS_ERR(fb)) {
11226                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11227                 goto fail;
11228         }
11229
11230         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11231         if (ret)
11232                 goto fail;
11233
11234         drm_framebuffer_unreference(fb);
11235
11236         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11237         if (ret)
11238                 goto fail;
11239
11240         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11241         if (!ret)
11242                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11243         if (!ret)
11244                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11245         if (ret) {
11246                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11247                 goto fail;
11248         }
11249
11250         ret = drm_atomic_commit(state);
11251         if (ret) {
11252                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11253                 goto fail;
11254         }
11255
11256         old->restore_state = restore_state;
11257
11258         /* let the connector get through one full cycle before testing */
11259         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11260         return true;
11261
11262 fail:
11263         if (state) {
11264                 drm_atomic_state_put(state);
11265                 state = NULL;
11266         }
11267         if (restore_state) {
11268                 drm_atomic_state_put(restore_state);
11269                 restore_state = NULL;
11270         }
11271
11272         if (ret == -EDEADLK) {
11273                 drm_modeset_backoff(ctx);
11274                 goto retry;
11275         }
11276
11277         return false;
11278 }
11279
11280 void intel_release_load_detect_pipe(struct drm_connector *connector,
11281                                     struct intel_load_detect_pipe *old,
11282                                     struct drm_modeset_acquire_ctx *ctx)
11283 {
11284         struct intel_encoder *intel_encoder =
11285                 intel_attached_encoder(connector);
11286         struct drm_encoder *encoder = &intel_encoder->base;
11287         struct drm_atomic_state *state = old->restore_state;
11288         int ret;
11289
11290         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11291                       connector->base.id, connector->name,
11292                       encoder->base.id, encoder->name);
11293
11294         if (!state)
11295                 return;
11296
11297         ret = drm_atomic_commit(state);
11298         if (ret)
11299                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11300         drm_atomic_state_put(state);
11301 }
11302
11303 static int i9xx_pll_refclk(struct drm_device *dev,
11304                            const struct intel_crtc_state *pipe_config)
11305 {
11306         struct drm_i915_private *dev_priv = to_i915(dev);
11307         u32 dpll = pipe_config->dpll_hw_state.dpll;
11308
11309         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11310                 return dev_priv->vbt.lvds_ssc_freq;
11311         else if (HAS_PCH_SPLIT(dev_priv))
11312                 return 120000;
11313         else if (!IS_GEN2(dev_priv))
11314                 return 96000;
11315         else
11316                 return 48000;
11317 }
11318
11319 /* Returns the clock of the currently programmed mode of the given pipe. */
11320 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11321                                 struct intel_crtc_state *pipe_config)
11322 {
11323         struct drm_device *dev = crtc->base.dev;
11324         struct drm_i915_private *dev_priv = to_i915(dev);
11325         int pipe = pipe_config->cpu_transcoder;
11326         u32 dpll = pipe_config->dpll_hw_state.dpll;
11327         u32 fp;
11328         struct dpll clock;
11329         int port_clock;
11330         int refclk = i9xx_pll_refclk(dev, pipe_config);
11331
11332         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11333                 fp = pipe_config->dpll_hw_state.fp0;
11334         else
11335                 fp = pipe_config->dpll_hw_state.fp1;
11336
11337         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11338         if (IS_PINEVIEW(dev_priv)) {
11339                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11340                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11341         } else {
11342                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11343                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11344         }
11345
11346         if (!IS_GEN2(dev_priv)) {
11347                 if (IS_PINEVIEW(dev_priv))
11348                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11349                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11350                 else
11351                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11352                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11353
11354                 switch (dpll & DPLL_MODE_MASK) {
11355                 case DPLLB_MODE_DAC_SERIAL:
11356                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11357                                 5 : 10;
11358                         break;
11359                 case DPLLB_MODE_LVDS:
11360                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11361                                 7 : 14;
11362                         break;
11363                 default:
11364                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11365                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11366                         return;
11367                 }
11368
11369                 if (IS_PINEVIEW(dev_priv))
11370                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11371                 else
11372                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11373         } else {
11374                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11375                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11376
11377                 if (is_lvds) {
11378                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11379                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11380
11381                         if (lvds & LVDS_CLKB_POWER_UP)
11382                                 clock.p2 = 7;
11383                         else
11384                                 clock.p2 = 14;
11385                 } else {
11386                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11387                                 clock.p1 = 2;
11388                         else {
11389                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11390                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11391                         }
11392                         if (dpll & PLL_P2_DIVIDE_BY_4)
11393                                 clock.p2 = 4;
11394                         else
11395                                 clock.p2 = 2;
11396                 }
11397
11398                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11399         }
11400
11401         /*
11402          * This value includes pixel_multiplier. We will use
11403          * port_clock to compute adjusted_mode.crtc_clock in the
11404          * encoder's get_config() function.
11405          */
11406         pipe_config->port_clock = port_clock;
11407 }
11408
11409 int intel_dotclock_calculate(int link_freq,
11410                              const struct intel_link_m_n *m_n)
11411 {
11412         /*
11413          * The calculation for the data clock is:
11414          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11415          * But we want to avoid losing precison if possible, so:
11416          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11417          *
11418          * and the link clock is simpler:
11419          * link_clock = (m * link_clock) / n
11420          */
11421
11422         if (!m_n->link_n)
11423                 return 0;
11424
11425         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11426 }
11427
11428 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11429                                    struct intel_crtc_state *pipe_config)
11430 {
11431         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11432
11433         /* read out port_clock from the DPLL */
11434         i9xx_crtc_clock_get(crtc, pipe_config);
11435
11436         /*
11437          * In case there is an active pipe without active ports,
11438          * we may need some idea for the dotclock anyway.
11439          * Calculate one based on the FDI configuration.
11440          */
11441         pipe_config->base.adjusted_mode.crtc_clock =
11442                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11443                                          &pipe_config->fdi_m_n);
11444 }
11445
11446 /** Returns the currently programmed mode of the given pipe. */
11447 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11448                                              struct drm_crtc *crtc)
11449 {
11450         struct drm_i915_private *dev_priv = to_i915(dev);
11451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11452         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11453         struct drm_display_mode *mode;
11454         struct intel_crtc_state *pipe_config;
11455         int htot = I915_READ(HTOTAL(cpu_transcoder));
11456         int hsync = I915_READ(HSYNC(cpu_transcoder));
11457         int vtot = I915_READ(VTOTAL(cpu_transcoder));
11458         int vsync = I915_READ(VSYNC(cpu_transcoder));
11459         enum pipe pipe = intel_crtc->pipe;
11460
11461         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11462         if (!mode)
11463                 return NULL;
11464
11465         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11466         if (!pipe_config) {
11467                 kfree(mode);
11468                 return NULL;
11469         }
11470
11471         /*
11472          * Construct a pipe_config sufficient for getting the clock info
11473          * back out of crtc_clock_get.
11474          *
11475          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11476          * to use a real value here instead.
11477          */
11478         pipe_config->cpu_transcoder = (enum transcoder) pipe;
11479         pipe_config->pixel_multiplier = 1;
11480         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11481         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11482         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11483         i9xx_crtc_clock_get(intel_crtc, pipe_config);
11484
11485         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11486         mode->hdisplay = (htot & 0xffff) + 1;
11487         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11488         mode->hsync_start = (hsync & 0xffff) + 1;
11489         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11490         mode->vdisplay = (vtot & 0xffff) + 1;
11491         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11492         mode->vsync_start = (vsync & 0xffff) + 1;
11493         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11494
11495         drm_mode_set_name(mode);
11496
11497         kfree(pipe_config);
11498
11499         return mode;
11500 }
11501
11502 static void intel_crtc_destroy(struct drm_crtc *crtc)
11503 {
11504         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11505         struct drm_device *dev = crtc->dev;
11506         struct intel_flip_work *work;
11507
11508         spin_lock_irq(&dev->event_lock);
11509         work = intel_crtc->flip_work;
11510         intel_crtc->flip_work = NULL;
11511         spin_unlock_irq(&dev->event_lock);
11512
11513         if (work) {
11514                 cancel_work_sync(&work->mmio_work);
11515                 cancel_work_sync(&work->unpin_work);
11516                 kfree(work);
11517         }
11518
11519         drm_crtc_cleanup(crtc);
11520
11521         kfree(intel_crtc);
11522 }
11523
11524 static void intel_unpin_work_fn(struct work_struct *__work)
11525 {
11526         struct intel_flip_work *work =
11527                 container_of(__work, struct intel_flip_work, unpin_work);
11528         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11529         struct drm_device *dev = crtc->base.dev;
11530         struct drm_plane *primary = crtc->base.primary;
11531
11532         if (is_mmio_work(work))
11533                 flush_work(&work->mmio_work);
11534
11535         mutex_lock(&dev->struct_mutex);
11536         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11537         i915_gem_object_put(work->pending_flip_obj);
11538         mutex_unlock(&dev->struct_mutex);
11539
11540         i915_gem_request_put(work->flip_queued_req);
11541
11542         intel_frontbuffer_flip_complete(to_i915(dev),
11543                                         to_intel_plane(primary)->frontbuffer_bit);
11544         intel_fbc_post_update(crtc);
11545         drm_framebuffer_unreference(work->old_fb);
11546
11547         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11548         atomic_dec(&crtc->unpin_work_count);
11549
11550         kfree(work);
11551 }
11552
11553 /* Is 'a' after or equal to 'b'? */
11554 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11555 {
11556         return !((a - b) & 0x80000000);
11557 }
11558
11559 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11560                                    struct intel_flip_work *work)
11561 {
11562         struct drm_device *dev = crtc->base.dev;
11563         struct drm_i915_private *dev_priv = to_i915(dev);
11564
11565         if (abort_flip_on_reset(crtc))
11566                 return true;
11567
11568         /*
11569          * The relevant registers doen't exist on pre-ctg.
11570          * As the flip done interrupt doesn't trigger for mmio
11571          * flips on gmch platforms, a flip count check isn't
11572          * really needed there. But since ctg has the registers,
11573          * include it in the check anyway.
11574          */
11575         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11576                 return true;
11577
11578         /*
11579          * BDW signals flip done immediately if the plane
11580          * is disabled, even if the plane enable is already
11581          * armed to occur at the next vblank :(
11582          */
11583
11584         /*
11585          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11586          * used the same base address. In that case the mmio flip might
11587          * have completed, but the CS hasn't even executed the flip yet.
11588          *
11589          * A flip count check isn't enough as the CS might have updated
11590          * the base address just after start of vblank, but before we
11591          * managed to process the interrupt. This means we'd complete the
11592          * CS flip too soon.
11593          *
11594          * Combining both checks should get us a good enough result. It may
11595          * still happen that the CS flip has been executed, but has not
11596          * yet actually completed. But in case the base address is the same
11597          * anyway, we don't really care.
11598          */
11599         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11600                 crtc->flip_work->gtt_offset &&
11601                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11602                                     crtc->flip_work->flip_count);
11603 }
11604
11605 static bool
11606 __pageflip_finished_mmio(struct intel_crtc *crtc,
11607                                struct intel_flip_work *work)
11608 {
11609         /*
11610          * MMIO work completes when vblank is different from
11611          * flip_queued_vblank.
11612          *
11613          * Reset counter value doesn't matter, this is handled by
11614          * i915_wait_request finishing early, so no need to handle
11615          * reset here.
11616          */
11617         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11618 }
11619
11620
11621 static bool pageflip_finished(struct intel_crtc *crtc,
11622                               struct intel_flip_work *work)
11623 {
11624         if (!atomic_read(&work->pending))
11625                 return false;
11626
11627         smp_rmb();
11628
11629         if (is_mmio_work(work))
11630                 return __pageflip_finished_mmio(crtc, work);
11631         else
11632                 return __pageflip_finished_cs(crtc, work);
11633 }
11634
11635 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11636 {
11637         struct drm_device *dev = &dev_priv->drm;
11638         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11639         struct intel_flip_work *work;
11640         unsigned long flags;
11641
11642         /* Ignore early vblank irqs */
11643         if (!crtc)
11644                 return;
11645
11646         /*
11647          * This is called both by irq handlers and the reset code (to complete
11648          * lost pageflips) so needs the full irqsave spinlocks.
11649          */
11650         spin_lock_irqsave(&dev->event_lock, flags);
11651         work = crtc->flip_work;
11652
11653         if (work != NULL &&
11654             !is_mmio_work(work) &&
11655             pageflip_finished(crtc, work))
11656                 page_flip_completed(crtc);
11657
11658         spin_unlock_irqrestore(&dev->event_lock, flags);
11659 }
11660
11661 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11662 {
11663         struct drm_device *dev = &dev_priv->drm;
11664         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11665         struct intel_flip_work *work;
11666         unsigned long flags;
11667
11668         /* Ignore early vblank irqs */
11669         if (!crtc)
11670                 return;
11671
11672         /*
11673          * This is called both by irq handlers and the reset code (to complete
11674          * lost pageflips) so needs the full irqsave spinlocks.
11675          */
11676         spin_lock_irqsave(&dev->event_lock, flags);
11677         work = crtc->flip_work;
11678
11679         if (work != NULL &&
11680             is_mmio_work(work) &&
11681             pageflip_finished(crtc, work))
11682                 page_flip_completed(crtc);
11683
11684         spin_unlock_irqrestore(&dev->event_lock, flags);
11685 }
11686
11687 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11688                                                struct intel_flip_work *work)
11689 {
11690         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11691
11692         /* Ensure that the work item is consistent when activating it ... */
11693         smp_mb__before_atomic();
11694         atomic_set(&work->pending, 1);
11695 }
11696
11697 static int intel_gen2_queue_flip(struct drm_device *dev,
11698                                  struct drm_crtc *crtc,
11699                                  struct drm_framebuffer *fb,
11700                                  struct drm_i915_gem_object *obj,
11701                                  struct drm_i915_gem_request *req,
11702                                  uint32_t flags)
11703 {
11704         struct intel_ring *ring = req->ring;
11705         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11706         u32 flip_mask;
11707         int ret;
11708
11709         ret = intel_ring_begin(req, 6);
11710         if (ret)
11711                 return ret;
11712
11713         /* Can't queue multiple flips, so wait for the previous
11714          * one to finish before executing the next.
11715          */
11716         if (intel_crtc->plane)
11717                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11718         else
11719                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11720         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11721         intel_ring_emit(ring, MI_NOOP);
11722         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11723                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11724         intel_ring_emit(ring, fb->pitches[0]);
11725         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11726         intel_ring_emit(ring, 0); /* aux display base address, unused */
11727
11728         return 0;
11729 }
11730
11731 static int intel_gen3_queue_flip(struct drm_device *dev,
11732                                  struct drm_crtc *crtc,
11733                                  struct drm_framebuffer *fb,
11734                                  struct drm_i915_gem_object *obj,
11735                                  struct drm_i915_gem_request *req,
11736                                  uint32_t flags)
11737 {
11738         struct intel_ring *ring = req->ring;
11739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11740         u32 flip_mask;
11741         int ret;
11742
11743         ret = intel_ring_begin(req, 6);
11744         if (ret)
11745                 return ret;
11746
11747         if (intel_crtc->plane)
11748                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11749         else
11750                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11751         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11752         intel_ring_emit(ring, MI_NOOP);
11753         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11754                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11755         intel_ring_emit(ring, fb->pitches[0]);
11756         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11757         intel_ring_emit(ring, MI_NOOP);
11758
11759         return 0;
11760 }
11761
11762 static int intel_gen4_queue_flip(struct drm_device *dev,
11763                                  struct drm_crtc *crtc,
11764                                  struct drm_framebuffer *fb,
11765                                  struct drm_i915_gem_object *obj,
11766                                  struct drm_i915_gem_request *req,
11767                                  uint32_t flags)
11768 {
11769         struct intel_ring *ring = req->ring;
11770         struct drm_i915_private *dev_priv = to_i915(dev);
11771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11772         uint32_t pf, pipesrc;
11773         int ret;
11774
11775         ret = intel_ring_begin(req, 4);
11776         if (ret)
11777                 return ret;
11778
11779         /* i965+ uses the linear or tiled offsets from the
11780          * Display Registers (which do not change across a page-flip)
11781          * so we need only reprogram the base address.
11782          */
11783         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11784                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11785         intel_ring_emit(ring, fb->pitches[0]);
11786         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11787                         intel_fb_modifier_to_tiling(fb->modifier));
11788
11789         /* XXX Enabling the panel-fitter across page-flip is so far
11790          * untested on non-native modes, so ignore it for now.
11791          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11792          */
11793         pf = 0;
11794         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11795         intel_ring_emit(ring, pf | pipesrc);
11796
11797         return 0;
11798 }
11799
11800 static int intel_gen6_queue_flip(struct drm_device *dev,
11801                                  struct drm_crtc *crtc,
11802                                  struct drm_framebuffer *fb,
11803                                  struct drm_i915_gem_object *obj,
11804                                  struct drm_i915_gem_request *req,
11805                                  uint32_t flags)
11806 {
11807         struct intel_ring *ring = req->ring;
11808         struct drm_i915_private *dev_priv = to_i915(dev);
11809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11810         uint32_t pf, pipesrc;
11811         int ret;
11812
11813         ret = intel_ring_begin(req, 4);
11814         if (ret)
11815                 return ret;
11816
11817         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11818                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11819         intel_ring_emit(ring, fb->pitches[0] |
11820                         intel_fb_modifier_to_tiling(fb->modifier));
11821         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11822
11823         /* Contrary to the suggestions in the documentation,
11824          * "Enable Panel Fitter" does not seem to be required when page
11825          * flipping with a non-native mode, and worse causes a normal
11826          * modeset to fail.
11827          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11828          */
11829         pf = 0;
11830         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11831         intel_ring_emit(ring, pf | pipesrc);
11832
11833         return 0;
11834 }
11835
11836 static int intel_gen7_queue_flip(struct drm_device *dev,
11837                                  struct drm_crtc *crtc,
11838                                  struct drm_framebuffer *fb,
11839                                  struct drm_i915_gem_object *obj,
11840                                  struct drm_i915_gem_request *req,
11841                                  uint32_t flags)
11842 {
11843         struct drm_i915_private *dev_priv = to_i915(dev);
11844         struct intel_ring *ring = req->ring;
11845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11846         uint32_t plane_bit = 0;
11847         int len, ret;
11848
11849         switch (intel_crtc->plane) {
11850         case PLANE_A:
11851                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11852                 break;
11853         case PLANE_B:
11854                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11855                 break;
11856         case PLANE_C:
11857                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11858                 break;
11859         default:
11860                 WARN_ONCE(1, "unknown plane in flip command\n");
11861                 return -ENODEV;
11862         }
11863
11864         len = 4;
11865         if (req->engine->id == RCS) {
11866                 len += 6;
11867                 /*
11868                  * On Gen 8, SRM is now taking an extra dword to accommodate
11869                  * 48bits addresses, and we need a NOOP for the batch size to
11870                  * stay even.
11871                  */
11872                 if (IS_GEN8(dev_priv))
11873                         len += 2;
11874         }
11875
11876         /*
11877          * BSpec MI_DISPLAY_FLIP for IVB:
11878          * "The full packet must be contained within the same cache line."
11879          *
11880          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11881          * cacheline, if we ever start emitting more commands before
11882          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11883          * then do the cacheline alignment, and finally emit the
11884          * MI_DISPLAY_FLIP.
11885          */
11886         ret = intel_ring_cacheline_align(req);
11887         if (ret)
11888                 return ret;
11889
11890         ret = intel_ring_begin(req, len);
11891         if (ret)
11892                 return ret;
11893
11894         /* Unmask the flip-done completion message. Note that the bspec says that
11895          * we should do this for both the BCS and RCS, and that we must not unmask
11896          * more than one flip event at any time (or ensure that one flip message
11897          * can be sent by waiting for flip-done prior to queueing new flips).
11898          * Experimentation says that BCS works despite DERRMR masking all
11899          * flip-done completion events and that unmasking all planes at once
11900          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11901          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11902          */
11903         if (req->engine->id == RCS) {
11904                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11905                 intel_ring_emit_reg(ring, DERRMR);
11906                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11907                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11908                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11909                 if (IS_GEN8(dev_priv))
11910                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11911                                               MI_SRM_LRM_GLOBAL_GTT);
11912                 else
11913                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11914                                               MI_SRM_LRM_GLOBAL_GTT);
11915                 intel_ring_emit_reg(ring, DERRMR);
11916                 intel_ring_emit(ring,
11917                                 i915_ggtt_offset(req->engine->scratch) + 256);
11918                 if (IS_GEN8(dev_priv)) {
11919                         intel_ring_emit(ring, 0);
11920                         intel_ring_emit(ring, MI_NOOP);
11921                 }
11922         }
11923
11924         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11925         intel_ring_emit(ring, fb->pitches[0] |
11926                         intel_fb_modifier_to_tiling(fb->modifier));
11927         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11928         intel_ring_emit(ring, (MI_NOOP));
11929
11930         return 0;
11931 }
11932
11933 static bool use_mmio_flip(struct intel_engine_cs *engine,
11934                           struct drm_i915_gem_object *obj)
11935 {
11936         /*
11937          * This is not being used for older platforms, because
11938          * non-availability of flip done interrupt forces us to use
11939          * CS flips. Older platforms derive flip done using some clever
11940          * tricks involving the flip_pending status bits and vblank irqs.
11941          * So using MMIO flips there would disrupt this mechanism.
11942          */
11943
11944         if (engine == NULL)
11945                 return true;
11946
11947         if (INTEL_GEN(engine->i915) < 5)
11948                 return false;
11949
11950         if (i915.use_mmio_flip < 0)
11951                 return false;
11952         else if (i915.use_mmio_flip > 0)
11953                 return true;
11954         else if (i915.enable_execlists)
11955                 return true;
11956
11957         return engine != i915_gem_object_last_write_engine(obj);
11958 }
11959
11960 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11961                              unsigned int rotation,
11962                              struct intel_flip_work *work)
11963 {
11964         struct drm_device *dev = intel_crtc->base.dev;
11965         struct drm_i915_private *dev_priv = to_i915(dev);
11966         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11967         const enum pipe pipe = intel_crtc->pipe;
11968         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11969
11970         ctl = I915_READ(PLANE_CTL(pipe, 0));
11971         ctl &= ~PLANE_CTL_TILED_MASK;
11972         switch (fb->modifier) {
11973         case DRM_FORMAT_MOD_NONE:
11974                 break;
11975         case I915_FORMAT_MOD_X_TILED:
11976                 ctl |= PLANE_CTL_TILED_X;
11977                 break;
11978         case I915_FORMAT_MOD_Y_TILED:
11979                 ctl |= PLANE_CTL_TILED_Y;
11980                 break;
11981         case I915_FORMAT_MOD_Yf_TILED:
11982                 ctl |= PLANE_CTL_TILED_YF;
11983                 break;
11984         default:
11985                 MISSING_CASE(fb->modifier);
11986         }
11987
11988         /*
11989          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11990          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11991          */
11992         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11993         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11994
11995         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11996         POSTING_READ(PLANE_SURF(pipe, 0));
11997 }
11998
11999 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
12000                              struct intel_flip_work *work)
12001 {
12002         struct drm_device *dev = intel_crtc->base.dev;
12003         struct drm_i915_private *dev_priv = to_i915(dev);
12004         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12005         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12006         u32 dspcntr;
12007
12008         dspcntr = I915_READ(reg);
12009
12010         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
12011                 dspcntr |= DISPPLANE_TILED;
12012         else
12013                 dspcntr &= ~DISPPLANE_TILED;
12014
12015         I915_WRITE(reg, dspcntr);
12016
12017         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12018         POSTING_READ(DSPSURF(intel_crtc->plane));
12019 }
12020
12021 static void intel_mmio_flip_work_func(struct work_struct *w)
12022 {
12023         struct intel_flip_work *work =
12024                 container_of(w, struct intel_flip_work, mmio_work);
12025         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12026         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12027         struct intel_framebuffer *intel_fb =
12028                 to_intel_framebuffer(crtc->base.primary->fb);
12029         struct drm_i915_gem_object *obj = intel_fb->obj;
12030
12031         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
12032
12033         intel_pipe_update_start(crtc);
12034
12035         if (INTEL_GEN(dev_priv) >= 9)
12036                 skl_do_mmio_flip(crtc, work->rotation, work);
12037         else
12038                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12039                 ilk_do_mmio_flip(crtc, work);
12040
12041         intel_pipe_update_end(crtc, work);
12042 }
12043
12044 static int intel_default_queue_flip(struct drm_device *dev,
12045                                     struct drm_crtc *crtc,
12046                                     struct drm_framebuffer *fb,
12047                                     struct drm_i915_gem_object *obj,
12048                                     struct drm_i915_gem_request *req,
12049                                     uint32_t flags)
12050 {
12051         return -ENODEV;
12052 }
12053
12054 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12055                                       struct intel_crtc *intel_crtc,
12056                                       struct intel_flip_work *work)
12057 {
12058         u32 addr, vblank;
12059
12060         if (!atomic_read(&work->pending))
12061                 return false;
12062
12063         smp_rmb();
12064
12065         vblank = intel_crtc_get_vblank_counter(intel_crtc);
12066         if (work->flip_ready_vblank == 0) {
12067                 if (work->flip_queued_req &&
12068                     !i915_gem_request_completed(work->flip_queued_req))
12069                         return false;
12070
12071                 work->flip_ready_vblank = vblank;
12072         }
12073
12074         if (vblank - work->flip_ready_vblank < 3)
12075                 return false;
12076
12077         /* Potential stall - if we see that the flip has happened,
12078          * assume a missed interrupt. */
12079         if (INTEL_GEN(dev_priv) >= 4)
12080                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12081         else
12082                 addr = I915_READ(DSPADDR(intel_crtc->plane));
12083
12084         /* There is a potential issue here with a false positive after a flip
12085          * to the same address. We could address this by checking for a
12086          * non-incrementing frame counter.
12087          */
12088         return addr == work->gtt_offset;
12089 }
12090
12091 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12092 {
12093         struct drm_device *dev = &dev_priv->drm;
12094         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12095         struct intel_flip_work *work;
12096
12097         WARN_ON(!in_interrupt());
12098
12099         if (crtc == NULL)
12100                 return;
12101
12102         spin_lock(&dev->event_lock);
12103         work = crtc->flip_work;
12104
12105         if (work != NULL && !is_mmio_work(work) &&
12106             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
12107                 WARN_ONCE(1,
12108                           "Kicking stuck page flip: queued at %d, now %d\n",
12109                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
12110                 page_flip_completed(crtc);
12111                 work = NULL;
12112         }
12113
12114         if (work != NULL && !is_mmio_work(work) &&
12115             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
12116                 intel_queue_rps_boost_for_request(work->flip_queued_req);
12117         spin_unlock(&dev->event_lock);
12118 }
12119
12120 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12121                                 struct drm_framebuffer *fb,
12122                                 struct drm_pending_vblank_event *event,
12123                                 uint32_t page_flip_flags)
12124 {
12125         struct drm_device *dev = crtc->dev;
12126         struct drm_i915_private *dev_priv = to_i915(dev);
12127         struct drm_framebuffer *old_fb = crtc->primary->fb;
12128         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12130         struct drm_plane *primary = crtc->primary;
12131         enum pipe pipe = intel_crtc->pipe;
12132         struct intel_flip_work *work;
12133         struct intel_engine_cs *engine;
12134         bool mmio_flip;
12135         struct drm_i915_gem_request *request;
12136         struct i915_vma *vma;
12137         int ret;
12138
12139         /*
12140          * drm_mode_page_flip_ioctl() should already catch this, but double
12141          * check to be safe.  In the future we may enable pageflipping from
12142          * a disabled primary plane.
12143          */
12144         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12145                 return -EBUSY;
12146
12147         /* Can't change pixel format via MI display flips. */
12148         if (fb->pixel_format != crtc->primary->fb->pixel_format)
12149                 return -EINVAL;
12150
12151         /*
12152          * TILEOFF/LINOFF registers can't be changed via MI display flips.
12153          * Note that pitch changes could also affect these register.
12154          */
12155         if (INTEL_GEN(dev_priv) > 3 &&
12156             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12157              fb->pitches[0] != crtc->primary->fb->pitches[0]))
12158                 return -EINVAL;
12159
12160         if (i915_terminally_wedged(&dev_priv->gpu_error))
12161                 goto out_hang;
12162
12163         work = kzalloc(sizeof(*work), GFP_KERNEL);
12164         if (work == NULL)
12165                 return -ENOMEM;
12166
12167         work->event = event;
12168         work->crtc = crtc;
12169         work->old_fb = old_fb;
12170         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12171
12172         ret = drm_crtc_vblank_get(crtc);
12173         if (ret)
12174                 goto free_work;
12175
12176         /* We borrow the event spin lock for protecting flip_work */
12177         spin_lock_irq(&dev->event_lock);
12178         if (intel_crtc->flip_work) {
12179                 /* Before declaring the flip queue wedged, check if
12180                  * the hardware completed the operation behind our backs.
12181                  */
12182                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12183                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12184                         page_flip_completed(intel_crtc);
12185                 } else {
12186                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12187                         spin_unlock_irq(&dev->event_lock);
12188
12189                         drm_crtc_vblank_put(crtc);
12190                         kfree(work);
12191                         return -EBUSY;
12192                 }
12193         }
12194         intel_crtc->flip_work = work;
12195         spin_unlock_irq(&dev->event_lock);
12196
12197         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12198                 flush_workqueue(dev_priv->wq);
12199
12200         /* Reference the objects for the scheduled work. */
12201         drm_framebuffer_reference(work->old_fb);
12202
12203         crtc->primary->fb = fb;
12204         update_state_fb(crtc->primary);
12205
12206         work->pending_flip_obj = i915_gem_object_get(obj);
12207
12208         ret = i915_mutex_lock_interruptible(dev);
12209         if (ret)
12210                 goto cleanup;
12211
12212         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12213         if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12214                 ret = -EIO;
12215                 goto unlock;
12216         }
12217
12218         atomic_inc(&intel_crtc->unpin_work_count);
12219
12220         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12221                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12222
12223         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
12224                 engine = dev_priv->engine[BCS];
12225                 if (fb->modifier != old_fb->modifier)
12226                         /* vlv: DISPLAY_FLIP fails to change tiling */
12227                         engine = NULL;
12228         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
12229                 engine = dev_priv->engine[BCS];
12230         } else if (INTEL_GEN(dev_priv) >= 7) {
12231                 engine = i915_gem_object_last_write_engine(obj);
12232                 if (engine == NULL || engine->id != RCS)
12233                         engine = dev_priv->engine[BCS];
12234         } else {
12235                 engine = dev_priv->engine[RCS];
12236         }
12237
12238         mmio_flip = use_mmio_flip(engine, obj);
12239
12240         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12241         if (IS_ERR(vma)) {
12242                 ret = PTR_ERR(vma);
12243                 goto cleanup_pending;
12244         }
12245
12246         work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12247         work->gtt_offset += intel_crtc->dspaddr_offset;
12248         work->rotation = crtc->primary->state->rotation;
12249
12250         /*
12251          * There's the potential that the next frame will not be compatible with
12252          * FBC, so we want to call pre_update() before the actual page flip.
12253          * The problem is that pre_update() caches some information about the fb
12254          * object, so we want to do this only after the object is pinned. Let's
12255          * be on the safe side and do this immediately before scheduling the
12256          * flip.
12257          */
12258         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12259                              to_intel_plane_state(primary->state));
12260
12261         if (mmio_flip) {
12262                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12263                 queue_work(system_unbound_wq, &work->mmio_work);
12264         } else {
12265                 request = i915_gem_request_alloc(engine, engine->last_context);
12266                 if (IS_ERR(request)) {
12267                         ret = PTR_ERR(request);
12268                         goto cleanup_unpin;
12269                 }
12270
12271                 ret = i915_gem_request_await_object(request, obj, false);
12272                 if (ret)
12273                         goto cleanup_request;
12274
12275                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12276                                                    page_flip_flags);
12277                 if (ret)
12278                         goto cleanup_request;
12279
12280                 intel_mark_page_flip_active(intel_crtc, work);
12281
12282                 work->flip_queued_req = i915_gem_request_get(request);
12283                 i915_add_request_no_flush(request);
12284         }
12285
12286         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12287         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12288                           to_intel_plane(primary)->frontbuffer_bit);
12289         mutex_unlock(&dev->struct_mutex);
12290
12291         intel_frontbuffer_flip_prepare(to_i915(dev),
12292                                        to_intel_plane(primary)->frontbuffer_bit);
12293
12294         trace_i915_flip_request(intel_crtc->plane, obj);
12295
12296         return 0;
12297
12298 cleanup_request:
12299         i915_add_request_no_flush(request);
12300 cleanup_unpin:
12301         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12302 cleanup_pending:
12303         atomic_dec(&intel_crtc->unpin_work_count);
12304 unlock:
12305         mutex_unlock(&dev->struct_mutex);
12306 cleanup:
12307         crtc->primary->fb = old_fb;
12308         update_state_fb(crtc->primary);
12309
12310         i915_gem_object_put(obj);
12311         drm_framebuffer_unreference(work->old_fb);
12312
12313         spin_lock_irq(&dev->event_lock);
12314         intel_crtc->flip_work = NULL;
12315         spin_unlock_irq(&dev->event_lock);
12316
12317         drm_crtc_vblank_put(crtc);
12318 free_work:
12319         kfree(work);
12320
12321         if (ret == -EIO) {
12322                 struct drm_atomic_state *state;
12323                 struct drm_plane_state *plane_state;
12324
12325 out_hang:
12326                 state = drm_atomic_state_alloc(dev);
12327                 if (!state)
12328                         return -ENOMEM;
12329                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12330
12331 retry:
12332                 plane_state = drm_atomic_get_plane_state(state, primary);
12333                 ret = PTR_ERR_OR_ZERO(plane_state);
12334                 if (!ret) {
12335                         drm_atomic_set_fb_for_plane(plane_state, fb);
12336
12337                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12338                         if (!ret)
12339                                 ret = drm_atomic_commit(state);
12340                 }
12341
12342                 if (ret == -EDEADLK) {
12343                         drm_modeset_backoff(state->acquire_ctx);
12344                         drm_atomic_state_clear(state);
12345                         goto retry;
12346                 }
12347
12348                 drm_atomic_state_put(state);
12349
12350                 if (ret == 0 && event) {
12351                         spin_lock_irq(&dev->event_lock);
12352                         drm_crtc_send_vblank_event(crtc, event);
12353                         spin_unlock_irq(&dev->event_lock);
12354                 }
12355         }
12356         return ret;
12357 }
12358
12359
12360 /**
12361  * intel_wm_need_update - Check whether watermarks need updating
12362  * @plane: drm plane
12363  * @state: new plane state
12364  *
12365  * Check current plane state versus the new one to determine whether
12366  * watermarks need to be recalculated.
12367  *
12368  * Returns true or false.
12369  */
12370 static bool intel_wm_need_update(struct drm_plane *plane,
12371                                  struct drm_plane_state *state)
12372 {
12373         struct intel_plane_state *new = to_intel_plane_state(state);
12374         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12375
12376         /* Update watermarks on tiling or size changes. */
12377         if (new->base.visible != cur->base.visible)
12378                 return true;
12379
12380         if (!cur->base.fb || !new->base.fb)
12381                 return false;
12382
12383         if (cur->base.fb->modifier != new->base.fb->modifier ||
12384             cur->base.rotation != new->base.rotation ||
12385             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12386             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12387             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12388             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12389                 return true;
12390
12391         return false;
12392 }
12393
12394 static bool needs_scaling(struct intel_plane_state *state)
12395 {
12396         int src_w = drm_rect_width(&state->base.src) >> 16;
12397         int src_h = drm_rect_height(&state->base.src) >> 16;
12398         int dst_w = drm_rect_width(&state->base.dst);
12399         int dst_h = drm_rect_height(&state->base.dst);
12400
12401         return (src_w != dst_w || src_h != dst_h);
12402 }
12403
12404 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12405                                     struct drm_plane_state *plane_state)
12406 {
12407         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12408         struct drm_crtc *crtc = crtc_state->crtc;
12409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12410         struct drm_plane *plane = plane_state->plane;
12411         struct drm_device *dev = crtc->dev;
12412         struct drm_i915_private *dev_priv = to_i915(dev);
12413         struct intel_plane_state *old_plane_state =
12414                 to_intel_plane_state(plane->state);
12415         bool mode_changed = needs_modeset(crtc_state);
12416         bool was_crtc_enabled = crtc->state->active;
12417         bool is_crtc_enabled = crtc_state->active;
12418         bool turn_off, turn_on, visible, was_visible;
12419         struct drm_framebuffer *fb = plane_state->fb;
12420         int ret;
12421
12422         if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12423                 ret = skl_update_scaler_plane(
12424                         to_intel_crtc_state(crtc_state),
12425                         to_intel_plane_state(plane_state));
12426                 if (ret)
12427                         return ret;
12428         }
12429
12430         was_visible = old_plane_state->base.visible;
12431         visible = to_intel_plane_state(plane_state)->base.visible;
12432
12433         if (!was_crtc_enabled && WARN_ON(was_visible))
12434                 was_visible = false;
12435
12436         /*
12437          * Visibility is calculated as if the crtc was on, but
12438          * after scaler setup everything depends on it being off
12439          * when the crtc isn't active.
12440          *
12441          * FIXME this is wrong for watermarks. Watermarks should also
12442          * be computed as if the pipe would be active. Perhaps move
12443          * per-plane wm computation to the .check_plane() hook, and
12444          * only combine the results from all planes in the current place?
12445          */
12446         if (!is_crtc_enabled)
12447                 to_intel_plane_state(plane_state)->base.visible = visible = false;
12448
12449         if (!was_visible && !visible)
12450                 return 0;
12451
12452         if (fb != old_plane_state->base.fb)
12453                 pipe_config->fb_changed = true;
12454
12455         turn_off = was_visible && (!visible || mode_changed);
12456         turn_on = visible && (!was_visible || mode_changed);
12457
12458         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12459                          intel_crtc->base.base.id,
12460                          intel_crtc->base.name,
12461                          plane->base.id, plane->name,
12462                          fb ? fb->base.id : -1);
12463
12464         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12465                          plane->base.id, plane->name,
12466                          was_visible, visible,
12467                          turn_off, turn_on, mode_changed);
12468
12469         if (turn_on) {
12470                 pipe_config->update_wm_pre = true;
12471
12472                 /* must disable cxsr around plane enable/disable */
12473                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12474                         pipe_config->disable_cxsr = true;
12475         } else if (turn_off) {
12476                 pipe_config->update_wm_post = true;
12477
12478                 /* must disable cxsr around plane enable/disable */
12479                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12480                         pipe_config->disable_cxsr = true;
12481         } else if (intel_wm_need_update(plane, plane_state)) {
12482                 /* FIXME bollocks */
12483                 pipe_config->update_wm_pre = true;
12484                 pipe_config->update_wm_post = true;
12485         }
12486
12487         /* Pre-gen9 platforms need two-step watermark updates */
12488         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12489             INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks)
12490                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12491
12492         if (visible || was_visible)
12493                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12494
12495         /*
12496          * WaCxSRDisabledForSpriteScaling:ivb
12497          *
12498          * cstate->update_wm was already set above, so this flag will
12499          * take effect when we commit and program watermarks.
12500          */
12501         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
12502             needs_scaling(to_intel_plane_state(plane_state)) &&
12503             !needs_scaling(old_plane_state))
12504                 pipe_config->disable_lp_wm = true;
12505
12506         return 0;
12507 }
12508
12509 static bool encoders_cloneable(const struct intel_encoder *a,
12510                                const struct intel_encoder *b)
12511 {
12512         /* masks could be asymmetric, so check both ways */
12513         return a == b || (a->cloneable & (1 << b->type) &&
12514                           b->cloneable & (1 << a->type));
12515 }
12516
12517 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12518                                          struct intel_crtc *crtc,
12519                                          struct intel_encoder *encoder)
12520 {
12521         struct intel_encoder *source_encoder;
12522         struct drm_connector *connector;
12523         struct drm_connector_state *connector_state;
12524         int i;
12525
12526         for_each_connector_in_state(state, connector, connector_state, i) {
12527                 if (connector_state->crtc != &crtc->base)
12528                         continue;
12529
12530                 source_encoder =
12531                         to_intel_encoder(connector_state->best_encoder);
12532                 if (!encoders_cloneable(encoder, source_encoder))
12533                         return false;
12534         }
12535
12536         return true;
12537 }
12538
12539 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12540                                    struct drm_crtc_state *crtc_state)
12541 {
12542         struct drm_device *dev = crtc->dev;
12543         struct drm_i915_private *dev_priv = to_i915(dev);
12544         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12545         struct intel_crtc_state *pipe_config =
12546                 to_intel_crtc_state(crtc_state);
12547         struct drm_atomic_state *state = crtc_state->state;
12548         int ret;
12549         bool mode_changed = needs_modeset(crtc_state);
12550
12551         if (mode_changed && !crtc_state->active)
12552                 pipe_config->update_wm_post = true;
12553
12554         if (mode_changed && crtc_state->enable &&
12555             dev_priv->display.crtc_compute_clock &&
12556             !WARN_ON(pipe_config->shared_dpll)) {
12557                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12558                                                            pipe_config);
12559                 if (ret)
12560                         return ret;
12561         }
12562
12563         if (crtc_state->color_mgmt_changed) {
12564                 ret = intel_color_check(crtc, crtc_state);
12565                 if (ret)
12566                         return ret;
12567
12568                 /*
12569                  * Changing color management on Intel hardware is
12570                  * handled as part of planes update.
12571                  */
12572                 crtc_state->planes_changed = true;
12573         }
12574
12575         ret = 0;
12576         if (dev_priv->display.compute_pipe_wm) {
12577                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12578                 if (ret) {
12579                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12580                         return ret;
12581                 }
12582         }
12583
12584         if (dev_priv->display.compute_intermediate_wm &&
12585             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12586                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12587                         return 0;
12588
12589                 /*
12590                  * Calculate 'intermediate' watermarks that satisfy both the
12591                  * old state and the new state.  We can program these
12592                  * immediately.
12593                  */
12594                 ret = dev_priv->display.compute_intermediate_wm(dev,
12595                                                                 intel_crtc,
12596                                                                 pipe_config);
12597                 if (ret) {
12598                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12599                         return ret;
12600                 }
12601         } else if (dev_priv->display.compute_intermediate_wm) {
12602                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12603                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12604         }
12605
12606         if (INTEL_GEN(dev_priv) >= 9) {
12607                 if (mode_changed)
12608                         ret = skl_update_scaler_crtc(pipe_config);
12609
12610                 if (!ret)
12611                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12612                                                          pipe_config);
12613         }
12614
12615         return ret;
12616 }
12617
12618 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12619         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12620         .atomic_begin = intel_begin_crtc_commit,
12621         .atomic_flush = intel_finish_crtc_commit,
12622         .atomic_check = intel_crtc_atomic_check,
12623 };
12624
12625 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12626 {
12627         struct intel_connector *connector;
12628
12629         for_each_intel_connector(dev, connector) {
12630                 if (connector->base.state->crtc)
12631                         drm_connector_unreference(&connector->base);
12632
12633                 if (connector->base.encoder) {
12634                         connector->base.state->best_encoder =
12635                                 connector->base.encoder;
12636                         connector->base.state->crtc =
12637                                 connector->base.encoder->crtc;
12638
12639                         drm_connector_reference(&connector->base);
12640                 } else {
12641                         connector->base.state->best_encoder = NULL;
12642                         connector->base.state->crtc = NULL;
12643                 }
12644         }
12645 }
12646
12647 static void
12648 connected_sink_compute_bpp(struct intel_connector *connector,
12649                            struct intel_crtc_state *pipe_config)
12650 {
12651         const struct drm_display_info *info = &connector->base.display_info;
12652         int bpp = pipe_config->pipe_bpp;
12653
12654         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12655                       connector->base.base.id,
12656                       connector->base.name);
12657
12658         /* Don't use an invalid EDID bpc value */
12659         if (info->bpc != 0 && info->bpc * 3 < bpp) {
12660                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12661                               bpp, info->bpc * 3);
12662                 pipe_config->pipe_bpp = info->bpc * 3;
12663         }
12664
12665         /* Clamp bpp to 8 on screens without EDID 1.4 */
12666         if (info->bpc == 0 && bpp > 24) {
12667                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12668                               bpp);
12669                 pipe_config->pipe_bpp = 24;
12670         }
12671 }
12672
12673 static int
12674 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12675                           struct intel_crtc_state *pipe_config)
12676 {
12677         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12678         struct drm_atomic_state *state;
12679         struct drm_connector *connector;
12680         struct drm_connector_state *connector_state;
12681         int bpp, i;
12682
12683         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12684             IS_CHERRYVIEW(dev_priv)))
12685                 bpp = 10*3;
12686         else if (INTEL_GEN(dev_priv) >= 5)
12687                 bpp = 12*3;
12688         else
12689                 bpp = 8*3;
12690
12691
12692         pipe_config->pipe_bpp = bpp;
12693
12694         state = pipe_config->base.state;
12695
12696         /* Clamp display bpp to EDID value */
12697         for_each_connector_in_state(state, connector, connector_state, i) {
12698                 if (connector_state->crtc != &crtc->base)
12699                         continue;
12700
12701                 connected_sink_compute_bpp(to_intel_connector(connector),
12702                                            pipe_config);
12703         }
12704
12705         return bpp;
12706 }
12707
12708 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12709 {
12710         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12711                         "type: 0x%x flags: 0x%x\n",
12712                 mode->crtc_clock,
12713                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12714                 mode->crtc_hsync_end, mode->crtc_htotal,
12715                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12716                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12717 }
12718
12719 static inline void
12720 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
12721                       unsigned int lane_count, struct intel_link_m_n *m_n)
12722 {
12723         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12724                       id, lane_count,
12725                       m_n->gmch_m, m_n->gmch_n,
12726                       m_n->link_m, m_n->link_n, m_n->tu);
12727 }
12728
12729 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12730                                    struct intel_crtc_state *pipe_config,
12731                                    const char *context)
12732 {
12733         struct drm_device *dev = crtc->base.dev;
12734         struct drm_i915_private *dev_priv = to_i915(dev);
12735         struct drm_plane *plane;
12736         struct intel_plane *intel_plane;
12737         struct intel_plane_state *state;
12738         struct drm_framebuffer *fb;
12739
12740         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
12741                       crtc->base.base.id, crtc->base.name, context);
12742
12743         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12744                       transcoder_name(pipe_config->cpu_transcoder),
12745                       pipe_config->pipe_bpp, pipe_config->dither);
12746
12747         if (pipe_config->has_pch_encoder)
12748                 intel_dump_m_n_config(pipe_config, "fdi",
12749                                       pipe_config->fdi_lanes,
12750                                       &pipe_config->fdi_m_n);
12751
12752         if (intel_crtc_has_dp_encoder(pipe_config)) {
12753                 intel_dump_m_n_config(pipe_config, "dp m_n",
12754                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12755                 if (pipe_config->has_drrs)
12756                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12757                                               pipe_config->lane_count,
12758                                               &pipe_config->dp_m2_n2);
12759         }
12760
12761         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12762                       pipe_config->has_audio, pipe_config->has_infoframe);
12763
12764         DRM_DEBUG_KMS("requested mode:\n");
12765         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12766         DRM_DEBUG_KMS("adjusted mode:\n");
12767         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12768         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12769         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n",
12770                       pipe_config->port_clock,
12771                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12772
12773         if (INTEL_GEN(dev_priv) >= 9)
12774                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12775                               crtc->num_scalers,
12776                               pipe_config->scaler_state.scaler_users,
12777                               pipe_config->scaler_state.scaler_id);
12778
12779         if (HAS_GMCH_DISPLAY(dev_priv))
12780                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12781                               pipe_config->gmch_pfit.control,
12782                               pipe_config->gmch_pfit.pgm_ratios,
12783                               pipe_config->gmch_pfit.lvds_border_bits);
12784         else
12785                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12786                               pipe_config->pch_pfit.pos,
12787                               pipe_config->pch_pfit.size,
12788                               enableddisabled(pipe_config->pch_pfit.enabled));
12789
12790         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12791                       pipe_config->ips_enabled, pipe_config->double_wide);
12792
12793         if (IS_BROXTON(dev_priv)) {
12794                 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12795                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12796                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12797                               pipe_config->dpll_hw_state.ebb0,
12798                               pipe_config->dpll_hw_state.ebb4,
12799                               pipe_config->dpll_hw_state.pll0,
12800                               pipe_config->dpll_hw_state.pll1,
12801                               pipe_config->dpll_hw_state.pll2,
12802                               pipe_config->dpll_hw_state.pll3,
12803                               pipe_config->dpll_hw_state.pll6,
12804                               pipe_config->dpll_hw_state.pll8,
12805                               pipe_config->dpll_hw_state.pll9,
12806                               pipe_config->dpll_hw_state.pll10,
12807                               pipe_config->dpll_hw_state.pcsdw12);
12808         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
12809                 DRM_DEBUG_KMS("dpll_hw_state: "
12810                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12811                               pipe_config->dpll_hw_state.ctrl1,
12812                               pipe_config->dpll_hw_state.cfgcr1,
12813                               pipe_config->dpll_hw_state.cfgcr2);
12814         } else if (HAS_DDI(dev_priv)) {
12815                 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12816                               pipe_config->dpll_hw_state.wrpll,
12817                               pipe_config->dpll_hw_state.spll);
12818         } else {
12819                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12820                               "fp0: 0x%x, fp1: 0x%x\n",
12821                               pipe_config->dpll_hw_state.dpll,
12822                               pipe_config->dpll_hw_state.dpll_md,
12823                               pipe_config->dpll_hw_state.fp0,
12824                               pipe_config->dpll_hw_state.fp1);
12825         }
12826
12827         DRM_DEBUG_KMS("planes on this crtc\n");
12828         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12829                 struct drm_format_name_buf format_name;
12830                 intel_plane = to_intel_plane(plane);
12831                 if (intel_plane->pipe != crtc->pipe)
12832                         continue;
12833
12834                 state = to_intel_plane_state(plane->state);
12835                 fb = state->base.fb;
12836                 if (!fb) {
12837                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12838                                       plane->base.id, plane->name, state->scaler_id);
12839                         continue;
12840                 }
12841
12842                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
12843                               plane->base.id, plane->name,
12844                               fb->base.id, fb->width, fb->height,
12845                               drm_get_format_name(fb->pixel_format, &format_name));
12846                 if (INTEL_GEN(dev_priv) >= 9)
12847                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12848                                       state->scaler_id,
12849                                       state->base.src.x1 >> 16,
12850                                       state->base.src.y1 >> 16,
12851                                       drm_rect_width(&state->base.src) >> 16,
12852                                       drm_rect_height(&state->base.src) >> 16,
12853                                       state->base.dst.x1, state->base.dst.y1,
12854                                       drm_rect_width(&state->base.dst),
12855                                       drm_rect_height(&state->base.dst));
12856         }
12857 }
12858
12859 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12860 {
12861         struct drm_device *dev = state->dev;
12862         struct drm_connector *connector;
12863         unsigned int used_ports = 0;
12864         unsigned int used_mst_ports = 0;
12865
12866         /*
12867          * Walk the connector list instead of the encoder
12868          * list to detect the problem on ddi platforms
12869          * where there's just one encoder per digital port.
12870          */
12871         drm_for_each_connector(connector, dev) {
12872                 struct drm_connector_state *connector_state;
12873                 struct intel_encoder *encoder;
12874
12875                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12876                 if (!connector_state)
12877                         connector_state = connector->state;
12878
12879                 if (!connector_state->best_encoder)
12880                         continue;
12881
12882                 encoder = to_intel_encoder(connector_state->best_encoder);
12883
12884                 WARN_ON(!connector_state->crtc);
12885
12886                 switch (encoder->type) {
12887                         unsigned int port_mask;
12888                 case INTEL_OUTPUT_UNKNOWN:
12889                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12890                                 break;
12891                 case INTEL_OUTPUT_DP:
12892                 case INTEL_OUTPUT_HDMI:
12893                 case INTEL_OUTPUT_EDP:
12894                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12895
12896                         /* the same port mustn't appear more than once */
12897                         if (used_ports & port_mask)
12898                                 return false;
12899
12900                         used_ports |= port_mask;
12901                         break;
12902                 case INTEL_OUTPUT_DP_MST:
12903                         used_mst_ports |=
12904                                 1 << enc_to_mst(&encoder->base)->primary->port;
12905                         break;
12906                 default:
12907                         break;
12908                 }
12909         }
12910
12911         /* can't mix MST and SST/HDMI on the same port */
12912         if (used_ports & used_mst_ports)
12913                 return false;
12914
12915         return true;
12916 }
12917
12918 static void
12919 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12920 {
12921         struct drm_crtc_state tmp_state;
12922         struct intel_crtc_scaler_state scaler_state;
12923         struct intel_dpll_hw_state dpll_hw_state;
12924         struct intel_shared_dpll *shared_dpll;
12925         bool force_thru;
12926
12927         /* FIXME: before the switch to atomic started, a new pipe_config was
12928          * kzalloc'd. Code that depends on any field being zero should be
12929          * fixed, so that the crtc_state can be safely duplicated. For now,
12930          * only fields that are know to not cause problems are preserved. */
12931
12932         tmp_state = crtc_state->base;
12933         scaler_state = crtc_state->scaler_state;
12934         shared_dpll = crtc_state->shared_dpll;
12935         dpll_hw_state = crtc_state->dpll_hw_state;
12936         force_thru = crtc_state->pch_pfit.force_thru;
12937
12938         memset(crtc_state, 0, sizeof *crtc_state);
12939
12940         crtc_state->base = tmp_state;
12941         crtc_state->scaler_state = scaler_state;
12942         crtc_state->shared_dpll = shared_dpll;
12943         crtc_state->dpll_hw_state = dpll_hw_state;
12944         crtc_state->pch_pfit.force_thru = force_thru;
12945 }
12946
12947 static int
12948 intel_modeset_pipe_config(struct drm_crtc *crtc,
12949                           struct intel_crtc_state *pipe_config)
12950 {
12951         struct drm_atomic_state *state = pipe_config->base.state;
12952         struct intel_encoder *encoder;
12953         struct drm_connector *connector;
12954         struct drm_connector_state *connector_state;
12955         int base_bpp, ret = -EINVAL;
12956         int i;
12957         bool retry = true;
12958
12959         clear_intel_crtc_state(pipe_config);
12960
12961         pipe_config->cpu_transcoder =
12962                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12963
12964         /*
12965          * Sanitize sync polarity flags based on requested ones. If neither
12966          * positive or negative polarity is requested, treat this as meaning
12967          * negative polarity.
12968          */
12969         if (!(pipe_config->base.adjusted_mode.flags &
12970               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12971                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12972
12973         if (!(pipe_config->base.adjusted_mode.flags &
12974               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12975                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12976
12977         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12978                                              pipe_config);
12979         if (base_bpp < 0)
12980                 goto fail;
12981
12982         /*
12983          * Determine the real pipe dimensions. Note that stereo modes can
12984          * increase the actual pipe size due to the frame doubling and
12985          * insertion of additional space for blanks between the frame. This
12986          * is stored in the crtc timings. We use the requested mode to do this
12987          * computation to clearly distinguish it from the adjusted mode, which
12988          * can be changed by the connectors in the below retry loop.
12989          */
12990         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12991                                &pipe_config->pipe_src_w,
12992                                &pipe_config->pipe_src_h);
12993
12994         for_each_connector_in_state(state, connector, connector_state, i) {
12995                 if (connector_state->crtc != crtc)
12996                         continue;
12997
12998                 encoder = to_intel_encoder(connector_state->best_encoder);
12999
13000                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13001                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13002                         goto fail;
13003                 }
13004
13005                 /*
13006                  * Determine output_types before calling the .compute_config()
13007                  * hooks so that the hooks can use this information safely.
13008                  */
13009                 pipe_config->output_types |= 1 << encoder->type;
13010         }
13011
13012 encoder_retry:
13013         /* Ensure the port clock defaults are reset when retrying. */
13014         pipe_config->port_clock = 0;
13015         pipe_config->pixel_multiplier = 1;
13016
13017         /* Fill in default crtc timings, allow encoders to overwrite them. */
13018         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13019                               CRTC_STEREO_DOUBLE);
13020
13021         /* Pass our mode to the connectors and the CRTC to give them a chance to
13022          * adjust it according to limitations or connector properties, and also
13023          * a chance to reject the mode entirely.
13024          */
13025         for_each_connector_in_state(state, connector, connector_state, i) {
13026                 if (connector_state->crtc != crtc)
13027                         continue;
13028
13029                 encoder = to_intel_encoder(connector_state->best_encoder);
13030
13031                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13032                         DRM_DEBUG_KMS("Encoder config failure\n");
13033                         goto fail;
13034                 }
13035         }
13036
13037         /* Set default port clock if not overwritten by the encoder. Needs to be
13038          * done afterwards in case the encoder adjusts the mode. */
13039         if (!pipe_config->port_clock)
13040                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13041                         * pipe_config->pixel_multiplier;
13042
13043         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13044         if (ret < 0) {
13045                 DRM_DEBUG_KMS("CRTC fixup failed\n");
13046                 goto fail;
13047         }
13048
13049         if (ret == RETRY) {
13050                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13051                         ret = -EINVAL;
13052                         goto fail;
13053                 }
13054
13055                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13056                 retry = false;
13057                 goto encoder_retry;
13058         }
13059
13060         /* Dithering seems to not pass-through bits correctly when it should, so
13061          * only enable it on 6bpc panels. */
13062         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13063         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13064                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13065
13066 fail:
13067         return ret;
13068 }
13069
13070 static void
13071 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13072 {
13073         struct drm_crtc *crtc;
13074         struct drm_crtc_state *crtc_state;
13075         int i;
13076
13077         /* Double check state. */
13078         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13079                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13080
13081                 /* Update hwmode for vblank functions */
13082                 if (crtc->state->active)
13083                         crtc->hwmode = crtc->state->adjusted_mode;
13084                 else
13085                         crtc->hwmode.crtc_clock = 0;
13086
13087                 /*
13088                  * Update legacy state to satisfy fbc code. This can
13089                  * be removed when fbc uses the atomic state.
13090                  */
13091                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13092                         struct drm_plane_state *plane_state = crtc->primary->state;
13093
13094                         crtc->primary->fb = plane_state->fb;
13095                         crtc->x = plane_state->src_x >> 16;
13096                         crtc->y = plane_state->src_y >> 16;
13097                 }
13098         }
13099 }
13100
13101 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13102 {
13103         int diff;
13104
13105         if (clock1 == clock2)
13106                 return true;
13107
13108         if (!clock1 || !clock2)
13109                 return false;
13110
13111         diff = abs(clock1 - clock2);
13112
13113         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13114                 return true;
13115
13116         return false;
13117 }
13118
13119 static bool
13120 intel_compare_m_n(unsigned int m, unsigned int n,
13121                   unsigned int m2, unsigned int n2,
13122                   bool exact)
13123 {
13124         if (m == m2 && n == n2)
13125                 return true;
13126
13127         if (exact || !m || !n || !m2 || !n2)
13128                 return false;
13129
13130         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13131
13132         if (n > n2) {
13133                 while (n > n2) {
13134                         m2 <<= 1;
13135                         n2 <<= 1;
13136                 }
13137         } else if (n < n2) {
13138                 while (n < n2) {
13139                         m <<= 1;
13140                         n <<= 1;
13141                 }
13142         }
13143
13144         if (n != n2)
13145                 return false;
13146
13147         return intel_fuzzy_clock_check(m, m2);
13148 }
13149
13150 static bool
13151 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13152                        struct intel_link_m_n *m2_n2,
13153                        bool adjust)
13154 {
13155         if (m_n->tu == m2_n2->tu &&
13156             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13157                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13158             intel_compare_m_n(m_n->link_m, m_n->link_n,
13159                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
13160                 if (adjust)
13161                         *m2_n2 = *m_n;
13162
13163                 return true;
13164         }
13165
13166         return false;
13167 }
13168
13169 static bool
13170 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
13171                           struct intel_crtc_state *current_config,
13172                           struct intel_crtc_state *pipe_config,
13173                           bool adjust)
13174 {
13175         bool ret = true;
13176
13177 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13178         do { \
13179                 if (!adjust) \
13180                         DRM_ERROR(fmt, ##__VA_ARGS__); \
13181                 else \
13182                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13183         } while (0)
13184
13185 #define PIPE_CONF_CHECK_X(name) \
13186         if (current_config->name != pipe_config->name) { \
13187                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13188                           "(expected 0x%08x, found 0x%08x)\n", \
13189                           current_config->name, \
13190                           pipe_config->name); \
13191                 ret = false; \
13192         }
13193
13194 #define PIPE_CONF_CHECK_I(name) \
13195         if (current_config->name != pipe_config->name) { \
13196                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13197                           "(expected %i, found %i)\n", \
13198                           current_config->name, \
13199                           pipe_config->name); \
13200                 ret = false; \
13201         }
13202
13203 #define PIPE_CONF_CHECK_P(name) \
13204         if (current_config->name != pipe_config->name) { \
13205                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13206                           "(expected %p, found %p)\n", \
13207                           current_config->name, \
13208                           pipe_config->name); \
13209                 ret = false; \
13210         }
13211
13212 #define PIPE_CONF_CHECK_M_N(name) \
13213         if (!intel_compare_link_m_n(&current_config->name, \
13214                                     &pipe_config->name,\
13215                                     adjust)) { \
13216                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13217                           "(expected tu %i gmch %i/%i link %i/%i, " \
13218                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13219                           current_config->name.tu, \
13220                           current_config->name.gmch_m, \
13221                           current_config->name.gmch_n, \
13222                           current_config->name.link_m, \
13223                           current_config->name.link_n, \
13224                           pipe_config->name.tu, \
13225                           pipe_config->name.gmch_m, \
13226                           pipe_config->name.gmch_n, \
13227                           pipe_config->name.link_m, \
13228                           pipe_config->name.link_n); \
13229                 ret = false; \
13230         }
13231
13232 /* This is required for BDW+ where there is only one set of registers for
13233  * switching between high and low RR.
13234  * This macro can be used whenever a comparison has to be made between one
13235  * hw state and multiple sw state variables.
13236  */
13237 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13238         if (!intel_compare_link_m_n(&current_config->name, \
13239                                     &pipe_config->name, adjust) && \
13240             !intel_compare_link_m_n(&current_config->alt_name, \
13241                                     &pipe_config->name, adjust)) { \
13242                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13243                           "(expected tu %i gmch %i/%i link %i/%i, " \
13244                           "or tu %i gmch %i/%i link %i/%i, " \
13245                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13246                           current_config->name.tu, \
13247                           current_config->name.gmch_m, \
13248                           current_config->name.gmch_n, \
13249                           current_config->name.link_m, \
13250                           current_config->name.link_n, \
13251                           current_config->alt_name.tu, \
13252                           current_config->alt_name.gmch_m, \
13253                           current_config->alt_name.gmch_n, \
13254                           current_config->alt_name.link_m, \
13255                           current_config->alt_name.link_n, \
13256                           pipe_config->name.tu, \
13257                           pipe_config->name.gmch_m, \
13258                           pipe_config->name.gmch_n, \
13259                           pipe_config->name.link_m, \
13260                           pipe_config->name.link_n); \
13261                 ret = false; \
13262         }
13263
13264 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
13265         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13266                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13267                           "(expected %i, found %i)\n", \
13268                           current_config->name & (mask), \
13269                           pipe_config->name & (mask)); \
13270                 ret = false; \
13271         }
13272
13273 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13274         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13275                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13276                           "(expected %i, found %i)\n", \
13277                           current_config->name, \
13278                           pipe_config->name); \
13279                 ret = false; \
13280         }
13281
13282 #define PIPE_CONF_QUIRK(quirk)  \
13283         ((current_config->quirks | pipe_config->quirks) & (quirk))
13284
13285         PIPE_CONF_CHECK_I(cpu_transcoder);
13286
13287         PIPE_CONF_CHECK_I(has_pch_encoder);
13288         PIPE_CONF_CHECK_I(fdi_lanes);
13289         PIPE_CONF_CHECK_M_N(fdi_m_n);
13290
13291         PIPE_CONF_CHECK_I(lane_count);
13292         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13293
13294         if (INTEL_GEN(dev_priv) < 8) {
13295                 PIPE_CONF_CHECK_M_N(dp_m_n);
13296
13297                 if (current_config->has_drrs)
13298                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13299         } else
13300                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13301
13302         PIPE_CONF_CHECK_X(output_types);
13303
13304         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13305         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13306         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13307         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13308         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13309         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13310
13311         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13312         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13313         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13314         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13315         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13316         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13317
13318         PIPE_CONF_CHECK_I(pixel_multiplier);
13319         PIPE_CONF_CHECK_I(has_hdmi_sink);
13320         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13321             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13322                 PIPE_CONF_CHECK_I(limited_color_range);
13323         PIPE_CONF_CHECK_I(has_infoframe);
13324
13325         PIPE_CONF_CHECK_I(has_audio);
13326
13327         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13328                               DRM_MODE_FLAG_INTERLACE);
13329
13330         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13331                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13332                                       DRM_MODE_FLAG_PHSYNC);
13333                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13334                                       DRM_MODE_FLAG_NHSYNC);
13335                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13336                                       DRM_MODE_FLAG_PVSYNC);
13337                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13338                                       DRM_MODE_FLAG_NVSYNC);
13339         }
13340
13341         PIPE_CONF_CHECK_X(gmch_pfit.control);
13342         /* pfit ratios are autocomputed by the hw on gen4+ */
13343         if (INTEL_GEN(dev_priv) < 4)
13344                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13345         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13346
13347         if (!adjust) {
13348                 PIPE_CONF_CHECK_I(pipe_src_w);
13349                 PIPE_CONF_CHECK_I(pipe_src_h);
13350
13351                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13352                 if (current_config->pch_pfit.enabled) {
13353                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13354                         PIPE_CONF_CHECK_X(pch_pfit.size);
13355                 }
13356
13357                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13358         }
13359
13360         /* BDW+ don't expose a synchronous way to read the state */
13361         if (IS_HASWELL(dev_priv))
13362                 PIPE_CONF_CHECK_I(ips_enabled);
13363
13364         PIPE_CONF_CHECK_I(double_wide);
13365
13366         PIPE_CONF_CHECK_P(shared_dpll);
13367         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13368         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13369         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13370         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13371         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13372         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13373         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13374         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13375         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13376
13377         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13378         PIPE_CONF_CHECK_X(dsi_pll.div);
13379
13380         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13381                 PIPE_CONF_CHECK_I(pipe_bpp);
13382
13383         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13384         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13385
13386 #undef PIPE_CONF_CHECK_X
13387 #undef PIPE_CONF_CHECK_I
13388 #undef PIPE_CONF_CHECK_P
13389 #undef PIPE_CONF_CHECK_FLAGS
13390 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13391 #undef PIPE_CONF_QUIRK
13392 #undef INTEL_ERR_OR_DBG_KMS
13393
13394         return ret;
13395 }
13396
13397 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13398                                            const struct intel_crtc_state *pipe_config)
13399 {
13400         if (pipe_config->has_pch_encoder) {
13401                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13402                                                             &pipe_config->fdi_m_n);
13403                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13404
13405                 /*
13406                  * FDI already provided one idea for the dotclock.
13407                  * Yell if the encoder disagrees.
13408                  */
13409                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13410                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13411                      fdi_dotclock, dotclock);
13412         }
13413 }
13414
13415 static void verify_wm_state(struct drm_crtc *crtc,
13416                             struct drm_crtc_state *new_state)
13417 {
13418         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13419         struct skl_ddb_allocation hw_ddb, *sw_ddb;
13420         struct skl_pipe_wm hw_wm, *sw_wm;
13421         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13422         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13424         const enum pipe pipe = intel_crtc->pipe;
13425         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13426
13427         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
13428                 return;
13429
13430         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
13431         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
13432
13433         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13434         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13435
13436         /* planes */
13437         for_each_universal_plane(dev_priv, pipe, plane) {
13438                 hw_plane_wm = &hw_wm.planes[plane];
13439                 sw_plane_wm = &sw_wm->planes[plane];
13440
13441                 /* Watermarks */
13442                 for (level = 0; level <= max_level; level++) {
13443                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13444                                                 &sw_plane_wm->wm[level]))
13445                                 continue;
13446
13447                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13448                                   pipe_name(pipe), plane + 1, level,
13449                                   sw_plane_wm->wm[level].plane_en,
13450                                   sw_plane_wm->wm[level].plane_res_b,
13451                                   sw_plane_wm->wm[level].plane_res_l,
13452                                   hw_plane_wm->wm[level].plane_en,
13453                                   hw_plane_wm->wm[level].plane_res_b,
13454                                   hw_plane_wm->wm[level].plane_res_l);
13455                 }
13456
13457                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13458                                          &sw_plane_wm->trans_wm)) {
13459                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13460                                   pipe_name(pipe), plane + 1,
13461                                   sw_plane_wm->trans_wm.plane_en,
13462                                   sw_plane_wm->trans_wm.plane_res_b,
13463                                   sw_plane_wm->trans_wm.plane_res_l,
13464                                   hw_plane_wm->trans_wm.plane_en,
13465                                   hw_plane_wm->trans_wm.plane_res_b,
13466                                   hw_plane_wm->trans_wm.plane_res_l);
13467                 }
13468
13469                 /* DDB */
13470                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
13471                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
13472
13473                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13474                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13475                                   pipe_name(pipe), plane + 1,
13476                                   sw_ddb_entry->start, sw_ddb_entry->end,
13477                                   hw_ddb_entry->start, hw_ddb_entry->end);
13478                 }
13479         }
13480
13481         /*
13482          * cursor
13483          * If the cursor plane isn't active, we may not have updated it's ddb
13484          * allocation. In that case since the ddb allocation will be updated
13485          * once the plane becomes visible, we can skip this check
13486          */
13487         if (intel_crtc->cursor_addr) {
13488                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
13489                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13490
13491                 /* Watermarks */
13492                 for (level = 0; level <= max_level; level++) {
13493                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13494                                                 &sw_plane_wm->wm[level]))
13495                                 continue;
13496
13497                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13498                                   pipe_name(pipe), level,
13499                                   sw_plane_wm->wm[level].plane_en,
13500                                   sw_plane_wm->wm[level].plane_res_b,
13501                                   sw_plane_wm->wm[level].plane_res_l,
13502                                   hw_plane_wm->wm[level].plane_en,
13503                                   hw_plane_wm->wm[level].plane_res_b,
13504                                   hw_plane_wm->wm[level].plane_res_l);
13505                 }
13506
13507                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13508                                          &sw_plane_wm->trans_wm)) {
13509                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13510                                   pipe_name(pipe),
13511                                   sw_plane_wm->trans_wm.plane_en,
13512                                   sw_plane_wm->trans_wm.plane_res_b,
13513                                   sw_plane_wm->trans_wm.plane_res_l,
13514                                   hw_plane_wm->trans_wm.plane_en,
13515                                   hw_plane_wm->trans_wm.plane_res_b,
13516                                   hw_plane_wm->trans_wm.plane_res_l);
13517                 }
13518
13519                 /* DDB */
13520                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13521                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13522
13523                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13524                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13525                                   pipe_name(pipe),
13526                                   sw_ddb_entry->start, sw_ddb_entry->end,
13527                                   hw_ddb_entry->start, hw_ddb_entry->end);
13528                 }
13529         }
13530 }
13531
13532 static void
13533 verify_connector_state(struct drm_device *dev,
13534                        struct drm_atomic_state *state,
13535                        struct drm_crtc *crtc)
13536 {
13537         struct drm_connector *connector;
13538         struct drm_connector_state *old_conn_state;
13539         int i;
13540
13541         for_each_connector_in_state(state, connector, old_conn_state, i) {
13542                 struct drm_encoder *encoder = connector->encoder;
13543                 struct drm_connector_state *state = connector->state;
13544
13545                 if (state->crtc != crtc)
13546                         continue;
13547
13548                 intel_connector_verify_state(to_intel_connector(connector));
13549
13550                 I915_STATE_WARN(state->best_encoder != encoder,
13551                      "connector's atomic encoder doesn't match legacy encoder\n");
13552         }
13553 }
13554
13555 static void
13556 verify_encoder_state(struct drm_device *dev)
13557 {
13558         struct intel_encoder *encoder;
13559         struct intel_connector *connector;
13560
13561         for_each_intel_encoder(dev, encoder) {
13562                 bool enabled = false;
13563                 enum pipe pipe;
13564
13565                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13566                               encoder->base.base.id,
13567                               encoder->base.name);
13568
13569                 for_each_intel_connector(dev, connector) {
13570                         if (connector->base.state->best_encoder != &encoder->base)
13571                                 continue;
13572                         enabled = true;
13573
13574                         I915_STATE_WARN(connector->base.state->crtc !=
13575                                         encoder->base.crtc,
13576                              "connector's crtc doesn't match encoder crtc\n");
13577                 }
13578
13579                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13580                      "encoder's enabled state mismatch "
13581                      "(expected %i, found %i)\n",
13582                      !!encoder->base.crtc, enabled);
13583
13584                 if (!encoder->base.crtc) {
13585                         bool active;
13586
13587                         active = encoder->get_hw_state(encoder, &pipe);
13588                         I915_STATE_WARN(active,
13589                              "encoder detached but still enabled on pipe %c.\n",
13590                              pipe_name(pipe));
13591                 }
13592         }
13593 }
13594
13595 static void
13596 verify_crtc_state(struct drm_crtc *crtc,
13597                   struct drm_crtc_state *old_crtc_state,
13598                   struct drm_crtc_state *new_crtc_state)
13599 {
13600         struct drm_device *dev = crtc->dev;
13601         struct drm_i915_private *dev_priv = to_i915(dev);
13602         struct intel_encoder *encoder;
13603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13604         struct intel_crtc_state *pipe_config, *sw_config;
13605         struct drm_atomic_state *old_state;
13606         bool active;
13607
13608         old_state = old_crtc_state->state;
13609         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13610         pipe_config = to_intel_crtc_state(old_crtc_state);
13611         memset(pipe_config, 0, sizeof(*pipe_config));
13612         pipe_config->base.crtc = crtc;
13613         pipe_config->base.state = old_state;
13614
13615         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13616
13617         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13618
13619         /* hw state is inconsistent with the pipe quirk */
13620         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13621             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13622                 active = new_crtc_state->active;
13623
13624         I915_STATE_WARN(new_crtc_state->active != active,
13625              "crtc active state doesn't match with hw state "
13626              "(expected %i, found %i)\n", new_crtc_state->active, active);
13627
13628         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13629              "transitional active state does not match atomic hw state "
13630              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13631
13632         for_each_encoder_on_crtc(dev, crtc, encoder) {
13633                 enum pipe pipe;
13634
13635                 active = encoder->get_hw_state(encoder, &pipe);
13636                 I915_STATE_WARN(active != new_crtc_state->active,
13637                         "[ENCODER:%i] active %i with crtc active %i\n",
13638                         encoder->base.base.id, active, new_crtc_state->active);
13639
13640                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13641                                 "Encoder connected to wrong pipe %c\n",
13642                                 pipe_name(pipe));
13643
13644                 if (active) {
13645                         pipe_config->output_types |= 1 << encoder->type;
13646                         encoder->get_config(encoder, pipe_config);
13647                 }
13648         }
13649
13650         if (!new_crtc_state->active)
13651                 return;
13652
13653         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13654
13655         sw_config = to_intel_crtc_state(crtc->state);
13656         if (!intel_pipe_config_compare(dev_priv, sw_config,
13657                                        pipe_config, false)) {
13658                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13659                 intel_dump_pipe_config(intel_crtc, pipe_config,
13660                                        "[hw state]");
13661                 intel_dump_pipe_config(intel_crtc, sw_config,
13662                                        "[sw state]");
13663         }
13664 }
13665
13666 static void
13667 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13668                          struct intel_shared_dpll *pll,
13669                          struct drm_crtc *crtc,
13670                          struct drm_crtc_state *new_state)
13671 {
13672         struct intel_dpll_hw_state dpll_hw_state;
13673         unsigned crtc_mask;
13674         bool active;
13675
13676         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13677
13678         DRM_DEBUG_KMS("%s\n", pll->name);
13679
13680         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13681
13682         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13683                 I915_STATE_WARN(!pll->on && pll->active_mask,
13684                      "pll in active use but not on in sw tracking\n");
13685                 I915_STATE_WARN(pll->on && !pll->active_mask,
13686                      "pll is on but not used by any active crtc\n");
13687                 I915_STATE_WARN(pll->on != active,
13688                      "pll on state mismatch (expected %i, found %i)\n",
13689                      pll->on, active);
13690         }
13691
13692         if (!crtc) {
13693                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13694                                 "more active pll users than references: %x vs %x\n",
13695                                 pll->active_mask, pll->config.crtc_mask);
13696
13697                 return;
13698         }
13699
13700         crtc_mask = 1 << drm_crtc_index(crtc);
13701
13702         if (new_state->active)
13703                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13704                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13705                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13706         else
13707                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13708                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13709                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13710
13711         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13712                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13713                         crtc_mask, pll->config.crtc_mask);
13714
13715         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13716                                           &dpll_hw_state,
13717                                           sizeof(dpll_hw_state)),
13718                         "pll hw state mismatch\n");
13719 }
13720
13721 static void
13722 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13723                          struct drm_crtc_state *old_crtc_state,
13724                          struct drm_crtc_state *new_crtc_state)
13725 {
13726         struct drm_i915_private *dev_priv = to_i915(dev);
13727         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13728         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13729
13730         if (new_state->shared_dpll)
13731                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13732
13733         if (old_state->shared_dpll &&
13734             old_state->shared_dpll != new_state->shared_dpll) {
13735                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13736                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13737
13738                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13739                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13740                                 pipe_name(drm_crtc_index(crtc)));
13741                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13742                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13743                                 pipe_name(drm_crtc_index(crtc)));
13744         }
13745 }
13746
13747 static void
13748 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13749                           struct drm_atomic_state *state,
13750                           struct drm_crtc_state *old_state,
13751                           struct drm_crtc_state *new_state)
13752 {
13753         if (!needs_modeset(new_state) &&
13754             !to_intel_crtc_state(new_state)->update_pipe)
13755                 return;
13756
13757         verify_wm_state(crtc, new_state);
13758         verify_connector_state(crtc->dev, state, crtc);
13759         verify_crtc_state(crtc, old_state, new_state);
13760         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13761 }
13762
13763 static void
13764 verify_disabled_dpll_state(struct drm_device *dev)
13765 {
13766         struct drm_i915_private *dev_priv = to_i915(dev);
13767         int i;
13768
13769         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13770                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13771 }
13772
13773 static void
13774 intel_modeset_verify_disabled(struct drm_device *dev,
13775                               struct drm_atomic_state *state)
13776 {
13777         verify_encoder_state(dev);
13778         verify_connector_state(dev, state, NULL);
13779         verify_disabled_dpll_state(dev);
13780 }
13781
13782 static void update_scanline_offset(struct intel_crtc *crtc)
13783 {
13784         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13785
13786         /*
13787          * The scanline counter increments at the leading edge of hsync.
13788          *
13789          * On most platforms it starts counting from vtotal-1 on the
13790          * first active line. That means the scanline counter value is
13791          * always one less than what we would expect. Ie. just after
13792          * start of vblank, which also occurs at start of hsync (on the
13793          * last active line), the scanline counter will read vblank_start-1.
13794          *
13795          * On gen2 the scanline counter starts counting from 1 instead
13796          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13797          * to keep the value positive), instead of adding one.
13798          *
13799          * On HSW+ the behaviour of the scanline counter depends on the output
13800          * type. For DP ports it behaves like most other platforms, but on HDMI
13801          * there's an extra 1 line difference. So we need to add two instead of
13802          * one to the value.
13803          */
13804         if (IS_GEN2(dev_priv)) {
13805                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13806                 int vtotal;
13807
13808                 vtotal = adjusted_mode->crtc_vtotal;
13809                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13810                         vtotal /= 2;
13811
13812                 crtc->scanline_offset = vtotal - 1;
13813         } else if (HAS_DDI(dev_priv) &&
13814                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13815                 crtc->scanline_offset = 2;
13816         } else
13817                 crtc->scanline_offset = 1;
13818 }
13819
13820 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13821 {
13822         struct drm_device *dev = state->dev;
13823         struct drm_i915_private *dev_priv = to_i915(dev);
13824         struct intel_shared_dpll_config *shared_dpll = NULL;
13825         struct drm_crtc *crtc;
13826         struct drm_crtc_state *crtc_state;
13827         int i;
13828
13829         if (!dev_priv->display.crtc_compute_clock)
13830                 return;
13831
13832         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13833                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13834                 struct intel_shared_dpll *old_dpll =
13835                         to_intel_crtc_state(crtc->state)->shared_dpll;
13836
13837                 if (!needs_modeset(crtc_state))
13838                         continue;
13839
13840                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13841
13842                 if (!old_dpll)
13843                         continue;
13844
13845                 if (!shared_dpll)
13846                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13847
13848                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13849         }
13850 }
13851
13852 /*
13853  * This implements the workaround described in the "notes" section of the mode
13854  * set sequence documentation. When going from no pipes or single pipe to
13855  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13856  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13857  */
13858 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13859 {
13860         struct drm_crtc_state *crtc_state;
13861         struct intel_crtc *intel_crtc;
13862         struct drm_crtc *crtc;
13863         struct intel_crtc_state *first_crtc_state = NULL;
13864         struct intel_crtc_state *other_crtc_state = NULL;
13865         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13866         int i;
13867
13868         /* look at all crtc's that are going to be enabled in during modeset */
13869         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13870                 intel_crtc = to_intel_crtc(crtc);
13871
13872                 if (!crtc_state->active || !needs_modeset(crtc_state))
13873                         continue;
13874
13875                 if (first_crtc_state) {
13876                         other_crtc_state = to_intel_crtc_state(crtc_state);
13877                         break;
13878                 } else {
13879                         first_crtc_state = to_intel_crtc_state(crtc_state);
13880                         first_pipe = intel_crtc->pipe;
13881                 }
13882         }
13883
13884         /* No workaround needed? */
13885         if (!first_crtc_state)
13886                 return 0;
13887
13888         /* w/a possibly needed, check how many crtc's are already enabled. */
13889         for_each_intel_crtc(state->dev, intel_crtc) {
13890                 struct intel_crtc_state *pipe_config;
13891
13892                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13893                 if (IS_ERR(pipe_config))
13894                         return PTR_ERR(pipe_config);
13895
13896                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13897
13898                 if (!pipe_config->base.active ||
13899                     needs_modeset(&pipe_config->base))
13900                         continue;
13901
13902                 /* 2 or more enabled crtcs means no need for w/a */
13903                 if (enabled_pipe != INVALID_PIPE)
13904                         return 0;
13905
13906                 enabled_pipe = intel_crtc->pipe;
13907         }
13908
13909         if (enabled_pipe != INVALID_PIPE)
13910                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13911         else if (other_crtc_state)
13912                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13913
13914         return 0;
13915 }
13916
13917 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13918 {
13919         struct drm_crtc *crtc;
13920         struct drm_crtc_state *crtc_state;
13921         int ret = 0;
13922
13923         /* add all active pipes to the state */
13924         for_each_crtc(state->dev, crtc) {
13925                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13926                 if (IS_ERR(crtc_state))
13927                         return PTR_ERR(crtc_state);
13928
13929                 if (!crtc_state->active || needs_modeset(crtc_state))
13930                         continue;
13931
13932                 crtc_state->mode_changed = true;
13933
13934                 ret = drm_atomic_add_affected_connectors(state, crtc);
13935                 if (ret)
13936                         break;
13937
13938                 ret = drm_atomic_add_affected_planes(state, crtc);
13939                 if (ret)
13940                         break;
13941         }
13942
13943         return ret;
13944 }
13945
13946 static int intel_modeset_checks(struct drm_atomic_state *state)
13947 {
13948         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13949         struct drm_i915_private *dev_priv = to_i915(state->dev);
13950         struct drm_crtc *crtc;
13951         struct drm_crtc_state *crtc_state;
13952         int ret = 0, i;
13953
13954         if (!check_digital_port_conflicts(state)) {
13955                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13956                 return -EINVAL;
13957         }
13958
13959         intel_state->modeset = true;
13960         intel_state->active_crtcs = dev_priv->active_crtcs;
13961
13962         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13963                 if (crtc_state->active)
13964                         intel_state->active_crtcs |= 1 << i;
13965                 else
13966                         intel_state->active_crtcs &= ~(1 << i);
13967
13968                 if (crtc_state->active != crtc->state->active)
13969                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13970         }
13971
13972         /*
13973          * See if the config requires any additional preparation, e.g.
13974          * to adjust global state with pipes off.  We need to do this
13975          * here so we can get the modeset_pipe updated config for the new
13976          * mode set on this crtc.  For other crtcs we need to use the
13977          * adjusted_mode bits in the crtc directly.
13978          */
13979         if (dev_priv->display.modeset_calc_cdclk) {
13980                 if (!intel_state->cdclk_pll_vco)
13981                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13982                 if (!intel_state->cdclk_pll_vco)
13983                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13984
13985                 ret = dev_priv->display.modeset_calc_cdclk(state);
13986                 if (ret < 0)
13987                         return ret;
13988
13989                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13990                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13991                         ret = intel_modeset_all_pipes(state);
13992
13993                 if (ret < 0)
13994                         return ret;
13995
13996                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13997                               intel_state->cdclk, intel_state->dev_cdclk);
13998         } else {
13999                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
14000         }
14001
14002         intel_modeset_clear_plls(state);
14003
14004         if (IS_HASWELL(dev_priv))
14005                 return haswell_mode_set_planes_workaround(state);
14006
14007         return 0;
14008 }
14009
14010 /*
14011  * Handle calculation of various watermark data at the end of the atomic check
14012  * phase.  The code here should be run after the per-crtc and per-plane 'check'
14013  * handlers to ensure that all derived state has been updated.
14014  */
14015 static int calc_watermark_data(struct drm_atomic_state *state)
14016 {
14017         struct drm_device *dev = state->dev;
14018         struct drm_i915_private *dev_priv = to_i915(dev);
14019
14020         /* Is there platform-specific watermark information to calculate? */
14021         if (dev_priv->display.compute_global_watermarks)
14022                 return dev_priv->display.compute_global_watermarks(state);
14023
14024         return 0;
14025 }
14026
14027 /**
14028  * intel_atomic_check - validate state object
14029  * @dev: drm device
14030  * @state: state to validate
14031  */
14032 static int intel_atomic_check(struct drm_device *dev,
14033                               struct drm_atomic_state *state)
14034 {
14035         struct drm_i915_private *dev_priv = to_i915(dev);
14036         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14037         struct drm_crtc *crtc;
14038         struct drm_crtc_state *crtc_state;
14039         int ret, i;
14040         bool any_ms = false;
14041
14042         ret = drm_atomic_helper_check_modeset(dev, state);
14043         if (ret)
14044                 return ret;
14045
14046         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14047                 struct intel_crtc_state *pipe_config =
14048                         to_intel_crtc_state(crtc_state);
14049
14050                 /* Catch I915_MODE_FLAG_INHERITED */
14051                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14052                         crtc_state->mode_changed = true;
14053
14054                 if (!needs_modeset(crtc_state))
14055                         continue;
14056
14057                 if (!crtc_state->enable) {
14058                         any_ms = true;
14059                         continue;
14060                 }
14061
14062                 /* FIXME: For only active_changed we shouldn't need to do any
14063                  * state recomputation at all. */
14064
14065                 ret = drm_atomic_add_affected_connectors(state, crtc);
14066                 if (ret)
14067                         return ret;
14068
14069                 ret = intel_modeset_pipe_config(crtc, pipe_config);
14070                 if (ret) {
14071                         intel_dump_pipe_config(to_intel_crtc(crtc),
14072                                                pipe_config, "[failed]");
14073                         return ret;
14074                 }
14075
14076                 if (i915.fastboot &&
14077                     intel_pipe_config_compare(dev_priv,
14078                                         to_intel_crtc_state(crtc->state),
14079                                         pipe_config, true)) {
14080                         crtc_state->mode_changed = false;
14081                         to_intel_crtc_state(crtc_state)->update_pipe = true;
14082                 }
14083
14084                 if (needs_modeset(crtc_state))
14085                         any_ms = true;
14086
14087                 ret = drm_atomic_add_affected_planes(state, crtc);
14088                 if (ret)
14089                         return ret;
14090
14091                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14092                                        needs_modeset(crtc_state) ?
14093                                        "[modeset]" : "[fastset]");
14094         }
14095
14096         if (any_ms) {
14097                 ret = intel_modeset_checks(state);
14098
14099                 if (ret)
14100                         return ret;
14101         } else {
14102                 intel_state->cdclk = dev_priv->atomic_cdclk_freq;
14103         }
14104
14105         ret = drm_atomic_helper_check_planes(dev, state);
14106         if (ret)
14107                 return ret;
14108
14109         intel_fbc_choose_crtc(dev_priv, state);
14110         return calc_watermark_data(state);
14111 }
14112
14113 static int intel_atomic_prepare_commit(struct drm_device *dev,
14114                                        struct drm_atomic_state *state)
14115 {
14116         struct drm_i915_private *dev_priv = to_i915(dev);
14117         struct drm_crtc_state *crtc_state;
14118         struct drm_crtc *crtc;
14119         int i, ret;
14120
14121         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14122                 if (state->legacy_cursor_update)
14123                         continue;
14124
14125                 ret = intel_crtc_wait_for_pending_flips(crtc);
14126                 if (ret)
14127                         return ret;
14128
14129                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14130                         flush_workqueue(dev_priv->wq);
14131         }
14132
14133         ret = mutex_lock_interruptible(&dev->struct_mutex);
14134         if (ret)
14135                 return ret;
14136
14137         ret = drm_atomic_helper_prepare_planes(dev, state);
14138         mutex_unlock(&dev->struct_mutex);
14139
14140         return ret;
14141 }
14142
14143 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14144 {
14145         struct drm_device *dev = crtc->base.dev;
14146
14147         if (!dev->max_vblank_count)
14148                 return drm_accurate_vblank_count(&crtc->base);
14149
14150         return dev->driver->get_vblank_counter(dev, crtc->pipe);
14151 }
14152
14153 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14154                                           struct drm_i915_private *dev_priv,
14155                                           unsigned crtc_mask)
14156 {
14157         unsigned last_vblank_count[I915_MAX_PIPES];
14158         enum pipe pipe;
14159         int ret;
14160
14161         if (!crtc_mask)
14162                 return;
14163
14164         for_each_pipe(dev_priv, pipe) {
14165                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14166                                                                   pipe);
14167
14168                 if (!((1 << pipe) & crtc_mask))
14169                         continue;
14170
14171                 ret = drm_crtc_vblank_get(&crtc->base);
14172                 if (WARN_ON(ret != 0)) {
14173                         crtc_mask &= ~(1 << pipe);
14174                         continue;
14175                 }
14176
14177                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
14178         }
14179
14180         for_each_pipe(dev_priv, pipe) {
14181                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14182                                                                   pipe);
14183                 long lret;
14184
14185                 if (!((1 << pipe) & crtc_mask))
14186                         continue;
14187
14188                 lret = wait_event_timeout(dev->vblank[pipe].queue,
14189                                 last_vblank_count[pipe] !=
14190                                         drm_crtc_vblank_count(&crtc->base),
14191                                 msecs_to_jiffies(50));
14192
14193                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14194
14195                 drm_crtc_vblank_put(&crtc->base);
14196         }
14197 }
14198
14199 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14200 {
14201         /* fb updated, need to unpin old fb */
14202         if (crtc_state->fb_changed)
14203                 return true;
14204
14205         /* wm changes, need vblank before final wm's */
14206         if (crtc_state->update_wm_post)
14207                 return true;
14208
14209         /*
14210          * cxsr is re-enabled after vblank.
14211          * This is already handled by crtc_state->update_wm_post,
14212          * but added for clarity.
14213          */
14214         if (crtc_state->disable_cxsr)
14215                 return true;
14216
14217         return false;
14218 }
14219
14220 static void intel_update_crtc(struct drm_crtc *crtc,
14221                               struct drm_atomic_state *state,
14222                               struct drm_crtc_state *old_crtc_state,
14223                               unsigned int *crtc_vblank_mask)
14224 {
14225         struct drm_device *dev = crtc->dev;
14226         struct drm_i915_private *dev_priv = to_i915(dev);
14227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14228         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14229         bool modeset = needs_modeset(crtc->state);
14230
14231         if (modeset) {
14232                 update_scanline_offset(intel_crtc);
14233                 dev_priv->display.crtc_enable(pipe_config, state);
14234         } else {
14235                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14236         }
14237
14238         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14239                 intel_fbc_enable(
14240                     intel_crtc, pipe_config,
14241                     to_intel_plane_state(crtc->primary->state));
14242         }
14243
14244         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14245
14246         if (needs_vblank_wait(pipe_config))
14247                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14248 }
14249
14250 static void intel_update_crtcs(struct drm_atomic_state *state,
14251                                unsigned int *crtc_vblank_mask)
14252 {
14253         struct drm_crtc *crtc;
14254         struct drm_crtc_state *old_crtc_state;
14255         int i;
14256
14257         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14258                 if (!crtc->state->active)
14259                         continue;
14260
14261                 intel_update_crtc(crtc, state, old_crtc_state,
14262                                   crtc_vblank_mask);
14263         }
14264 }
14265
14266 static void skl_update_crtcs(struct drm_atomic_state *state,
14267                              unsigned int *crtc_vblank_mask)
14268 {
14269         struct drm_i915_private *dev_priv = to_i915(state->dev);
14270         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14271         struct drm_crtc *crtc;
14272         struct intel_crtc *intel_crtc;
14273         struct drm_crtc_state *old_crtc_state;
14274         struct intel_crtc_state *cstate;
14275         unsigned int updated = 0;
14276         bool progress;
14277         enum pipe pipe;
14278         int i;
14279
14280         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
14281
14282         for_each_crtc_in_state(state, crtc, old_crtc_state, i)
14283                 /* ignore allocations for crtc's that have been turned off. */
14284                 if (crtc->state->active)
14285                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
14286
14287         /*
14288          * Whenever the number of active pipes changes, we need to make sure we
14289          * update the pipes in the right order so that their ddb allocations
14290          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14291          * cause pipe underruns and other bad stuff.
14292          */
14293         do {
14294                 progress = false;
14295
14296                 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14297                         bool vbl_wait = false;
14298                         unsigned int cmask = drm_crtc_mask(crtc);
14299
14300                         intel_crtc = to_intel_crtc(crtc);
14301                         cstate = to_intel_crtc_state(crtc->state);
14302                         pipe = intel_crtc->pipe;
14303
14304                         if (updated & cmask || !cstate->base.active)
14305                                 continue;
14306
14307                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
14308                                 continue;
14309
14310                         updated |= cmask;
14311                         entries[i] = &cstate->wm.skl.ddb;
14312
14313                         /*
14314                          * If this is an already active pipe, it's DDB changed,
14315                          * and this isn't the last pipe that needs updating
14316                          * then we need to wait for a vblank to pass for the
14317                          * new ddb allocation to take effect.
14318                          */
14319                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
14320                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
14321                             !crtc->state->active_changed &&
14322                             intel_state->wm_results.dirty_pipes != updated)
14323                                 vbl_wait = true;
14324
14325                         intel_update_crtc(crtc, state, old_crtc_state,
14326                                           crtc_vblank_mask);
14327
14328                         if (vbl_wait)
14329                                 intel_wait_for_vblank(dev_priv, pipe);
14330
14331                         progress = true;
14332                 }
14333         } while (progress);
14334 }
14335
14336 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14337 {
14338         struct drm_device *dev = state->dev;
14339         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14340         struct drm_i915_private *dev_priv = to_i915(dev);
14341         struct drm_crtc_state *old_crtc_state;
14342         struct drm_crtc *crtc;
14343         struct intel_crtc_state *intel_cstate;
14344         bool hw_check = intel_state->modeset;
14345         unsigned long put_domains[I915_MAX_PIPES] = {};
14346         unsigned crtc_vblank_mask = 0;
14347         int i;
14348
14349         drm_atomic_helper_wait_for_dependencies(state);
14350
14351         if (intel_state->modeset)
14352                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14353
14354         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14355                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14356
14357                 if (needs_modeset(crtc->state) ||
14358                     to_intel_crtc_state(crtc->state)->update_pipe) {
14359                         hw_check = true;
14360
14361                         put_domains[to_intel_crtc(crtc)->pipe] =
14362                                 modeset_get_crtc_power_domains(crtc,
14363                                         to_intel_crtc_state(crtc->state));
14364                 }
14365
14366                 if (!needs_modeset(crtc->state))
14367                         continue;
14368
14369                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14370
14371                 if (old_crtc_state->active) {
14372                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14373                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14374                         intel_crtc->active = false;
14375                         intel_fbc_disable(intel_crtc);
14376                         intel_disable_shared_dpll(intel_crtc);
14377
14378                         /*
14379                          * Underruns don't always raise
14380                          * interrupts, so check manually.
14381                          */
14382                         intel_check_cpu_fifo_underruns(dev_priv);
14383                         intel_check_pch_fifo_underruns(dev_priv);
14384
14385                         if (!crtc->state->active) {
14386                                 /*
14387                                  * Make sure we don't call initial_watermarks
14388                                  * for ILK-style watermark updates.
14389                                  */
14390                                 if (dev_priv->display.atomic_update_watermarks)
14391                                         dev_priv->display.initial_watermarks(intel_state,
14392                                                                              to_intel_crtc_state(crtc->state));
14393                                 else
14394                                         intel_update_watermarks(intel_crtc);
14395                         }
14396                 }
14397         }
14398
14399         /* Only after disabling all output pipelines that will be changed can we
14400          * update the the output configuration. */
14401         intel_modeset_update_crtc_state(state);
14402
14403         if (intel_state->modeset) {
14404                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14405
14406                 if (dev_priv->display.modeset_commit_cdclk &&
14407                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14408                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14409                         dev_priv->display.modeset_commit_cdclk(state);
14410
14411                 /*
14412                  * SKL workaround: bspec recommends we disable the SAGV when we
14413                  * have more then one pipe enabled
14414                  */
14415                 if (!intel_can_enable_sagv(state))
14416                         intel_disable_sagv(dev_priv);
14417
14418                 intel_modeset_verify_disabled(dev, state);
14419         }
14420
14421         /* Complete the events for pipes that have now been disabled */
14422         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14423                 bool modeset = needs_modeset(crtc->state);
14424
14425                 /* Complete events for now disable pipes here. */
14426                 if (modeset && !crtc->state->active && crtc->state->event) {
14427                         spin_lock_irq(&dev->event_lock);
14428                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
14429                         spin_unlock_irq(&dev->event_lock);
14430
14431                         crtc->state->event = NULL;
14432                 }
14433         }
14434
14435         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14436         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14437
14438         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14439          * already, but still need the state for the delayed optimization. To
14440          * fix this:
14441          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14442          * - schedule that vblank worker _before_ calling hw_done
14443          * - at the start of commit_tail, cancel it _synchrously
14444          * - switch over to the vblank wait helper in the core after that since
14445          *   we don't need out special handling any more.
14446          */
14447         if (!state->legacy_cursor_update)
14448                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14449
14450         /*
14451          * Now that the vblank has passed, we can go ahead and program the
14452          * optimal watermarks on platforms that need two-step watermark
14453          * programming.
14454          *
14455          * TODO: Move this (and other cleanup) to an async worker eventually.
14456          */
14457         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14458                 intel_cstate = to_intel_crtc_state(crtc->state);
14459
14460                 if (dev_priv->display.optimize_watermarks)
14461                         dev_priv->display.optimize_watermarks(intel_state,
14462                                                               intel_cstate);
14463         }
14464
14465         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14466                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14467
14468                 if (put_domains[i])
14469                         modeset_put_power_domains(dev_priv, put_domains[i]);
14470
14471                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state);
14472         }
14473
14474         if (intel_state->modeset && intel_can_enable_sagv(state))
14475                 intel_enable_sagv(dev_priv);
14476
14477         drm_atomic_helper_commit_hw_done(state);
14478
14479         if (intel_state->modeset)
14480                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14481
14482         mutex_lock(&dev->struct_mutex);
14483         drm_atomic_helper_cleanup_planes(dev, state);
14484         mutex_unlock(&dev->struct_mutex);
14485
14486         drm_atomic_helper_commit_cleanup_done(state);
14487
14488         drm_atomic_state_put(state);
14489
14490         /* As one of the primary mmio accessors, KMS has a high likelihood
14491          * of triggering bugs in unclaimed access. After we finish
14492          * modesetting, see if an error has been flagged, and if so
14493          * enable debugging for the next modeset - and hope we catch
14494          * the culprit.
14495          *
14496          * XXX note that we assume display power is on at this point.
14497          * This might hold true now but we need to add pm helper to check
14498          * unclaimed only when the hardware is on, as atomic commits
14499          * can happen also when the device is completely off.
14500          */
14501         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14502 }
14503
14504 static void intel_atomic_commit_work(struct work_struct *work)
14505 {
14506         struct drm_atomic_state *state =
14507                 container_of(work, struct drm_atomic_state, commit_work);
14508
14509         intel_atomic_commit_tail(state);
14510 }
14511
14512 static int __i915_sw_fence_call
14513 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14514                           enum i915_sw_fence_notify notify)
14515 {
14516         struct intel_atomic_state *state =
14517                 container_of(fence, struct intel_atomic_state, commit_ready);
14518
14519         switch (notify) {
14520         case FENCE_COMPLETE:
14521                 if (state->base.commit_work.func)
14522                         queue_work(system_unbound_wq, &state->base.commit_work);
14523                 break;
14524
14525         case FENCE_FREE:
14526                 drm_atomic_state_put(&state->base);
14527                 break;
14528         }
14529
14530         return NOTIFY_DONE;
14531 }
14532
14533 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14534 {
14535         struct drm_plane_state *old_plane_state;
14536         struct drm_plane *plane;
14537         int i;
14538
14539         for_each_plane_in_state(state, plane, old_plane_state, i)
14540                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14541                                   intel_fb_obj(plane->state->fb),
14542                                   to_intel_plane(plane)->frontbuffer_bit);
14543 }
14544
14545 /**
14546  * intel_atomic_commit - commit validated state object
14547  * @dev: DRM device
14548  * @state: the top-level driver state object
14549  * @nonblock: nonblocking commit
14550  *
14551  * This function commits a top-level state object that has been validated
14552  * with drm_atomic_helper_check().
14553  *
14554  * RETURNS
14555  * Zero for success or -errno.
14556  */
14557 static int intel_atomic_commit(struct drm_device *dev,
14558                                struct drm_atomic_state *state,
14559                                bool nonblock)
14560 {
14561         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14562         struct drm_i915_private *dev_priv = to_i915(dev);
14563         int ret = 0;
14564
14565         ret = drm_atomic_helper_setup_commit(state, nonblock);
14566         if (ret)
14567                 return ret;
14568
14569         drm_atomic_state_get(state);
14570         i915_sw_fence_init(&intel_state->commit_ready,
14571                            intel_atomic_commit_ready);
14572
14573         ret = intel_atomic_prepare_commit(dev, state);
14574         if (ret) {
14575                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14576                 i915_sw_fence_commit(&intel_state->commit_ready);
14577                 return ret;
14578         }
14579
14580         drm_atomic_helper_swap_state(state, true);
14581         dev_priv->wm.distrust_bios_wm = false;
14582         intel_shared_dpll_commit(state);
14583         intel_atomic_track_fbs(state);
14584
14585         if (intel_state->modeset) {
14586                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14587                        sizeof(intel_state->min_pixclk));
14588                 dev_priv->active_crtcs = intel_state->active_crtcs;
14589                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14590         }
14591
14592         drm_atomic_state_get(state);
14593         INIT_WORK(&state->commit_work,
14594                   nonblock ? intel_atomic_commit_work : NULL);
14595
14596         i915_sw_fence_commit(&intel_state->commit_ready);
14597         if (!nonblock) {
14598                 i915_sw_fence_wait(&intel_state->commit_ready);
14599                 intel_atomic_commit_tail(state);
14600         }
14601
14602         return 0;
14603 }
14604
14605 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14606 {
14607         struct drm_device *dev = crtc->dev;
14608         struct drm_atomic_state *state;
14609         struct drm_crtc_state *crtc_state;
14610         int ret;
14611
14612         state = drm_atomic_state_alloc(dev);
14613         if (!state) {
14614                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14615                               crtc->base.id, crtc->name);
14616                 return;
14617         }
14618
14619         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14620
14621 retry:
14622         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14623         ret = PTR_ERR_OR_ZERO(crtc_state);
14624         if (!ret) {
14625                 if (!crtc_state->active)
14626                         goto out;
14627
14628                 crtc_state->mode_changed = true;
14629                 ret = drm_atomic_commit(state);
14630         }
14631
14632         if (ret == -EDEADLK) {
14633                 drm_atomic_state_clear(state);
14634                 drm_modeset_backoff(state->acquire_ctx);
14635                 goto retry;
14636         }
14637
14638 out:
14639         drm_atomic_state_put(state);
14640 }
14641
14642 /*
14643  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14644  *        drm_atomic_helper_legacy_gamma_set() directly.
14645  */
14646 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14647                                          u16 *red, u16 *green, u16 *blue,
14648                                          uint32_t size)
14649 {
14650         struct drm_device *dev = crtc->dev;
14651         struct drm_mode_config *config = &dev->mode_config;
14652         struct drm_crtc_state *state;
14653         int ret;
14654
14655         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14656         if (ret)
14657                 return ret;
14658
14659         /*
14660          * Make sure we update the legacy properties so this works when
14661          * atomic is not enabled.
14662          */
14663
14664         state = crtc->state;
14665
14666         drm_object_property_set_value(&crtc->base,
14667                                       config->degamma_lut_property,
14668                                       (state->degamma_lut) ?
14669                                       state->degamma_lut->base.id : 0);
14670
14671         drm_object_property_set_value(&crtc->base,
14672                                       config->ctm_property,
14673                                       (state->ctm) ?
14674                                       state->ctm->base.id : 0);
14675
14676         drm_object_property_set_value(&crtc->base,
14677                                       config->gamma_lut_property,
14678                                       (state->gamma_lut) ?
14679                                       state->gamma_lut->base.id : 0);
14680
14681         return 0;
14682 }
14683
14684 static const struct drm_crtc_funcs intel_crtc_funcs = {
14685         .gamma_set = intel_atomic_legacy_gamma_set,
14686         .set_config = drm_atomic_helper_set_config,
14687         .set_property = drm_atomic_helper_crtc_set_property,
14688         .destroy = intel_crtc_destroy,
14689         .page_flip = intel_crtc_page_flip,
14690         .atomic_duplicate_state = intel_crtc_duplicate_state,
14691         .atomic_destroy_state = intel_crtc_destroy_state,
14692 };
14693
14694 /**
14695  * intel_prepare_plane_fb - Prepare fb for usage on plane
14696  * @plane: drm plane to prepare for
14697  * @fb: framebuffer to prepare for presentation
14698  *
14699  * Prepares a framebuffer for usage on a display plane.  Generally this
14700  * involves pinning the underlying object and updating the frontbuffer tracking
14701  * bits.  Some older platforms need special physical address handling for
14702  * cursor planes.
14703  *
14704  * Must be called with struct_mutex held.
14705  *
14706  * Returns 0 on success, negative error code on failure.
14707  */
14708 int
14709 intel_prepare_plane_fb(struct drm_plane *plane,
14710                        struct drm_plane_state *new_state)
14711 {
14712         struct intel_atomic_state *intel_state =
14713                 to_intel_atomic_state(new_state->state);
14714         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14715         struct drm_framebuffer *fb = new_state->fb;
14716         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14717         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14718         int ret;
14719
14720         if (!obj && !old_obj)
14721                 return 0;
14722
14723         if (old_obj) {
14724                 struct drm_crtc_state *crtc_state =
14725                         drm_atomic_get_existing_crtc_state(new_state->state,
14726                                                            plane->state->crtc);
14727
14728                 /* Big Hammer, we also need to ensure that any pending
14729                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14730                  * current scanout is retired before unpinning the old
14731                  * framebuffer. Note that we rely on userspace rendering
14732                  * into the buffer attached to the pipe they are waiting
14733                  * on. If not, userspace generates a GPU hang with IPEHR
14734                  * point to the MI_WAIT_FOR_EVENT.
14735                  *
14736                  * This should only fail upon a hung GPU, in which case we
14737                  * can safely continue.
14738                  */
14739                 if (needs_modeset(crtc_state)) {
14740                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14741                                                               old_obj->resv, NULL,
14742                                                               false, 0,
14743                                                               GFP_KERNEL);
14744                         if (ret < 0)
14745                                 return ret;
14746                 }
14747         }
14748
14749         if (new_state->fence) { /* explicit fencing */
14750                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
14751                                                     new_state->fence,
14752                                                     I915_FENCE_TIMEOUT,
14753                                                     GFP_KERNEL);
14754                 if (ret < 0)
14755                         return ret;
14756         }
14757
14758         if (!obj)
14759                 return 0;
14760
14761         if (!new_state->fence) { /* implicit fencing */
14762                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14763                                                       obj->resv, NULL,
14764                                                       false, I915_FENCE_TIMEOUT,
14765                                                       GFP_KERNEL);
14766                 if (ret < 0)
14767                         return ret;
14768
14769                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
14770         }
14771
14772         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14773             INTEL_INFO(dev_priv)->cursor_needs_physical) {
14774                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
14775                 ret = i915_gem_object_attach_phys(obj, align);
14776                 if (ret) {
14777                         DRM_DEBUG_KMS("failed to attach phys object\n");
14778                         return ret;
14779                 }
14780         } else {
14781                 struct i915_vma *vma;
14782
14783                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14784                 if (IS_ERR(vma)) {
14785                         DRM_DEBUG_KMS("failed to pin object\n");
14786                         return PTR_ERR(vma);
14787                 }
14788         }
14789
14790         return 0;
14791 }
14792
14793 /**
14794  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14795  * @plane: drm plane to clean up for
14796  * @fb: old framebuffer that was on plane
14797  *
14798  * Cleans up a framebuffer that has just been removed from a plane.
14799  *
14800  * Must be called with struct_mutex held.
14801  */
14802 void
14803 intel_cleanup_plane_fb(struct drm_plane *plane,
14804                        struct drm_plane_state *old_state)
14805 {
14806         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14807         struct intel_plane_state *old_intel_state;
14808         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14809         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14810
14811         old_intel_state = to_intel_plane_state(old_state);
14812
14813         if (!obj && !old_obj)
14814                 return;
14815
14816         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14817             !INTEL_INFO(dev_priv)->cursor_needs_physical))
14818                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14819 }
14820
14821 int
14822 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14823 {
14824         int max_scale;
14825         int crtc_clock, cdclk;
14826
14827         if (!intel_crtc || !crtc_state->base.enable)
14828                 return DRM_PLANE_HELPER_NO_SCALING;
14829
14830         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14831         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14832
14833         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14834                 return DRM_PLANE_HELPER_NO_SCALING;
14835
14836         /*
14837          * skl max scale is lower of:
14838          *    close to 3 but not 3, -1 is for that purpose
14839          *            or
14840          *    cdclk/crtc_clock
14841          */
14842         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14843
14844         return max_scale;
14845 }
14846
14847 static int
14848 intel_check_primary_plane(struct drm_plane *plane,
14849                           struct intel_crtc_state *crtc_state,
14850                           struct intel_plane_state *state)
14851 {
14852         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14853         struct drm_crtc *crtc = state->base.crtc;
14854         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14855         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14856         bool can_position = false;
14857         int ret;
14858
14859         if (INTEL_GEN(dev_priv) >= 9) {
14860                 /* use scaler when colorkey is not required */
14861                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14862                         min_scale = 1;
14863                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14864                 }
14865                 can_position = true;
14866         }
14867
14868         ret = drm_plane_helper_check_state(&state->base,
14869                                            &state->clip,
14870                                            min_scale, max_scale,
14871                                            can_position, true);
14872         if (ret)
14873                 return ret;
14874
14875         if (!state->base.fb)
14876                 return 0;
14877
14878         if (INTEL_GEN(dev_priv) >= 9) {
14879                 ret = skl_check_plane_surface(state);
14880                 if (ret)
14881                         return ret;
14882         }
14883
14884         return 0;
14885 }
14886
14887 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14888                                     struct drm_crtc_state *old_crtc_state)
14889 {
14890         struct drm_device *dev = crtc->dev;
14891         struct drm_i915_private *dev_priv = to_i915(dev);
14892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14893         struct intel_crtc_state *intel_cstate =
14894                 to_intel_crtc_state(crtc->state);
14895         struct intel_crtc_state *old_intel_cstate =
14896                 to_intel_crtc_state(old_crtc_state);
14897         struct intel_atomic_state *old_intel_state =
14898                 to_intel_atomic_state(old_crtc_state->state);
14899         bool modeset = needs_modeset(crtc->state);
14900
14901         /* Perform vblank evasion around commit operation */
14902         intel_pipe_update_start(intel_crtc);
14903
14904         if (modeset)
14905                 goto out;
14906
14907         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14908                 intel_color_set_csc(crtc->state);
14909                 intel_color_load_luts(crtc->state);
14910         }
14911
14912         if (intel_cstate->update_pipe)
14913                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
14914         else if (INTEL_GEN(dev_priv) >= 9)
14915                 skl_detach_scalers(intel_crtc);
14916
14917 out:
14918         if (dev_priv->display.atomic_update_watermarks)
14919                 dev_priv->display.atomic_update_watermarks(old_intel_state,
14920                                                            intel_cstate);
14921 }
14922
14923 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14924                                      struct drm_crtc_state *old_crtc_state)
14925 {
14926         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14927
14928         intel_pipe_update_end(intel_crtc, NULL);
14929 }
14930
14931 /**
14932  * intel_plane_destroy - destroy a plane
14933  * @plane: plane to destroy
14934  *
14935  * Common destruction function for all types of planes (primary, cursor,
14936  * sprite).
14937  */
14938 void intel_plane_destroy(struct drm_plane *plane)
14939 {
14940         drm_plane_cleanup(plane);
14941         kfree(to_intel_plane(plane));
14942 }
14943
14944 const struct drm_plane_funcs intel_plane_funcs = {
14945         .update_plane = drm_atomic_helper_update_plane,
14946         .disable_plane = drm_atomic_helper_disable_plane,
14947         .destroy = intel_plane_destroy,
14948         .set_property = drm_atomic_helper_plane_set_property,
14949         .atomic_get_property = intel_plane_atomic_get_property,
14950         .atomic_set_property = intel_plane_atomic_set_property,
14951         .atomic_duplicate_state = intel_plane_duplicate_state,
14952         .atomic_destroy_state = intel_plane_destroy_state,
14953 };
14954
14955 static struct intel_plane *
14956 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
14957 {
14958         struct intel_plane *primary = NULL;
14959         struct intel_plane_state *state = NULL;
14960         const uint32_t *intel_primary_formats;
14961         unsigned int supported_rotations;
14962         unsigned int num_formats;
14963         int ret;
14964
14965         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14966         if (!primary) {
14967                 ret = -ENOMEM;
14968                 goto fail;
14969         }
14970
14971         state = intel_create_plane_state(&primary->base);
14972         if (!state) {
14973                 ret = -ENOMEM;
14974                 goto fail;
14975         }
14976
14977         primary->base.state = &state->base;
14978
14979         primary->can_scale = false;
14980         primary->max_downscale = 1;
14981         if (INTEL_GEN(dev_priv) >= 9) {
14982                 primary->can_scale = true;
14983                 state->scaler_id = -1;
14984         }
14985         primary->pipe = pipe;
14986         /*
14987          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14988          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14989          */
14990         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
14991                 primary->plane = (enum plane) !pipe;
14992         else
14993                 primary->plane = (enum plane) pipe;
14994         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14995         primary->check_plane = intel_check_primary_plane;
14996
14997         if (INTEL_GEN(dev_priv) >= 9) {
14998                 intel_primary_formats = skl_primary_formats;
14999                 num_formats = ARRAY_SIZE(skl_primary_formats);
15000
15001                 primary->update_plane = skylake_update_primary_plane;
15002                 primary->disable_plane = skylake_disable_primary_plane;
15003         } else if (HAS_PCH_SPLIT(dev_priv)) {
15004                 intel_primary_formats = i965_primary_formats;
15005                 num_formats = ARRAY_SIZE(i965_primary_formats);
15006
15007                 primary->update_plane = ironlake_update_primary_plane;
15008                 primary->disable_plane = i9xx_disable_primary_plane;
15009         } else if (INTEL_GEN(dev_priv) >= 4) {
15010                 intel_primary_formats = i965_primary_formats;
15011                 num_formats = ARRAY_SIZE(i965_primary_formats);
15012
15013                 primary->update_plane = i9xx_update_primary_plane;
15014                 primary->disable_plane = i9xx_disable_primary_plane;
15015         } else {
15016                 intel_primary_formats = i8xx_primary_formats;
15017                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15018
15019                 primary->update_plane = i9xx_update_primary_plane;
15020                 primary->disable_plane = i9xx_disable_primary_plane;
15021         }
15022
15023         if (INTEL_GEN(dev_priv) >= 9)
15024                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15025                                                0, &intel_plane_funcs,
15026                                                intel_primary_formats, num_formats,
15027                                                DRM_PLANE_TYPE_PRIMARY,
15028                                                "plane 1%c", pipe_name(pipe));
15029         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15030                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15031                                                0, &intel_plane_funcs,
15032                                                intel_primary_formats, num_formats,
15033                                                DRM_PLANE_TYPE_PRIMARY,
15034                                                "primary %c", pipe_name(pipe));
15035         else
15036                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15037                                                0, &intel_plane_funcs,
15038                                                intel_primary_formats, num_formats,
15039                                                DRM_PLANE_TYPE_PRIMARY,
15040                                                "plane %c", plane_name(primary->plane));
15041         if (ret)
15042                 goto fail;
15043
15044         if (INTEL_GEN(dev_priv) >= 9) {
15045                 supported_rotations =
15046                         DRM_ROTATE_0 | DRM_ROTATE_90 |
15047                         DRM_ROTATE_180 | DRM_ROTATE_270;
15048         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15049                 supported_rotations =
15050                         DRM_ROTATE_0 | DRM_ROTATE_180 |
15051                         DRM_REFLECT_X;
15052         } else if (INTEL_GEN(dev_priv) >= 4) {
15053                 supported_rotations =
15054                         DRM_ROTATE_0 | DRM_ROTATE_180;
15055         } else {
15056                 supported_rotations = DRM_ROTATE_0;
15057         }
15058
15059         if (INTEL_GEN(dev_priv) >= 4)
15060                 drm_plane_create_rotation_property(&primary->base,
15061                                                    DRM_ROTATE_0,
15062                                                    supported_rotations);
15063
15064         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
15065
15066         return primary;
15067
15068 fail:
15069         kfree(state);
15070         kfree(primary);
15071
15072         return ERR_PTR(ret);
15073 }
15074
15075 static int
15076 intel_check_cursor_plane(struct drm_plane *plane,
15077                          struct intel_crtc_state *crtc_state,
15078                          struct intel_plane_state *state)
15079 {
15080         struct drm_framebuffer *fb = state->base.fb;
15081         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15082         enum pipe pipe = to_intel_plane(plane)->pipe;
15083         unsigned stride;
15084         int ret;
15085
15086         ret = drm_plane_helper_check_state(&state->base,
15087                                            &state->clip,
15088                                            DRM_PLANE_HELPER_NO_SCALING,
15089                                            DRM_PLANE_HELPER_NO_SCALING,
15090                                            true, true);
15091         if (ret)
15092                 return ret;
15093
15094         /* if we want to turn off the cursor ignore width and height */
15095         if (!obj)
15096                 return 0;
15097
15098         /* Check for which cursor types we support */
15099         if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
15100                             state->base.crtc_h)) {
15101                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15102                           state->base.crtc_w, state->base.crtc_h);
15103                 return -EINVAL;
15104         }
15105
15106         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15107         if (obj->base.size < stride * state->base.crtc_h) {
15108                 DRM_DEBUG_KMS("buffer is too small\n");
15109                 return -ENOMEM;
15110         }
15111
15112         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
15113                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15114                 return -EINVAL;
15115         }
15116
15117         /*
15118          * There's something wrong with the cursor on CHV pipe C.
15119          * If it straddles the left edge of the screen then
15120          * moving it away from the edge or disabling it often
15121          * results in a pipe underrun, and often that can lead to
15122          * dead pipe (constant underrun reported, and it scans
15123          * out just a solid color). To recover from that, the
15124          * display power well must be turned off and on again.
15125          * Refuse the put the cursor into that compromised position.
15126          */
15127         if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
15128             state->base.visible && state->base.crtc_x < 0) {
15129                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15130                 return -EINVAL;
15131         }
15132
15133         return 0;
15134 }
15135
15136 static void
15137 intel_disable_cursor_plane(struct drm_plane *plane,
15138                            struct drm_crtc *crtc)
15139 {
15140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15141
15142         intel_crtc->cursor_addr = 0;
15143         intel_crtc_update_cursor(crtc, NULL);
15144 }
15145
15146 static void
15147 intel_update_cursor_plane(struct drm_plane *plane,
15148                           const struct intel_crtc_state *crtc_state,
15149                           const struct intel_plane_state *state)
15150 {
15151         struct drm_crtc *crtc = crtc_state->base.crtc;
15152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15153         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15154         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15155         uint32_t addr;
15156
15157         if (!obj)
15158                 addr = 0;
15159         else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
15160                 addr = i915_gem_object_ggtt_offset(obj, NULL);
15161         else
15162                 addr = obj->phys_handle->busaddr;
15163
15164         intel_crtc->cursor_addr = addr;
15165         intel_crtc_update_cursor(crtc, state);
15166 }
15167
15168 static struct intel_plane *
15169 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15170 {
15171         struct intel_plane *cursor = NULL;
15172         struct intel_plane_state *state = NULL;
15173         int ret;
15174
15175         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15176         if (!cursor) {
15177                 ret = -ENOMEM;
15178                 goto fail;
15179         }
15180
15181         state = intel_create_plane_state(&cursor->base);
15182         if (!state) {
15183                 ret = -ENOMEM;
15184                 goto fail;
15185         }
15186
15187         cursor->base.state = &state->base;
15188
15189         cursor->can_scale = false;
15190         cursor->max_downscale = 1;
15191         cursor->pipe = pipe;
15192         cursor->plane = pipe;
15193         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15194         cursor->check_plane = intel_check_cursor_plane;
15195         cursor->update_plane = intel_update_cursor_plane;
15196         cursor->disable_plane = intel_disable_cursor_plane;
15197
15198         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15199                                        0, &intel_plane_funcs,
15200                                        intel_cursor_formats,
15201                                        ARRAY_SIZE(intel_cursor_formats),
15202                                        DRM_PLANE_TYPE_CURSOR,
15203                                        "cursor %c", pipe_name(pipe));
15204         if (ret)
15205                 goto fail;
15206
15207         if (INTEL_GEN(dev_priv) >= 4)
15208                 drm_plane_create_rotation_property(&cursor->base,
15209                                                    DRM_ROTATE_0,
15210                                                    DRM_ROTATE_0 |
15211                                                    DRM_ROTATE_180);
15212
15213         if (INTEL_GEN(dev_priv) >= 9)
15214                 state->scaler_id = -1;
15215
15216         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15217
15218         return cursor;
15219
15220 fail:
15221         kfree(state);
15222         kfree(cursor);
15223
15224         return ERR_PTR(ret);
15225 }
15226
15227 static void skl_init_scalers(struct drm_i915_private *dev_priv,
15228                              struct intel_crtc *crtc,
15229                              struct intel_crtc_state *crtc_state)
15230 {
15231         struct intel_crtc_scaler_state *scaler_state =
15232                 &crtc_state->scaler_state;
15233         int i;
15234
15235         for (i = 0; i < crtc->num_scalers; i++) {
15236                 struct intel_scaler *scaler = &scaler_state->scalers[i];
15237
15238                 scaler->in_use = 0;
15239                 scaler->mode = PS_SCALER_MODE_DYN;
15240         }
15241
15242         scaler_state->scaler_id = -1;
15243 }
15244
15245 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15246 {
15247         struct intel_crtc *intel_crtc;
15248         struct intel_crtc_state *crtc_state = NULL;
15249         struct intel_plane *primary = NULL;
15250         struct intel_plane *cursor = NULL;
15251         int sprite, ret;
15252
15253         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15254         if (!intel_crtc)
15255                 return -ENOMEM;
15256
15257         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15258         if (!crtc_state) {
15259                 ret = -ENOMEM;
15260                 goto fail;
15261         }
15262         intel_crtc->config = crtc_state;
15263         intel_crtc->base.state = &crtc_state->base;
15264         crtc_state->base.crtc = &intel_crtc->base;
15265
15266         /* initialize shared scalers */
15267         if (INTEL_GEN(dev_priv) >= 9) {
15268                 if (pipe == PIPE_C)
15269                         intel_crtc->num_scalers = 1;
15270                 else
15271                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
15272
15273                 skl_init_scalers(dev_priv, intel_crtc, crtc_state);
15274         }
15275
15276         primary = intel_primary_plane_create(dev_priv, pipe);
15277         if (IS_ERR(primary)) {
15278                 ret = PTR_ERR(primary);
15279                 goto fail;
15280         }
15281
15282         for_each_sprite(dev_priv, pipe, sprite) {
15283                 struct intel_plane *plane;
15284
15285                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15286                 if (IS_ERR(plane)) {
15287                         ret = PTR_ERR(plane);
15288                         goto fail;
15289                 }
15290         }
15291
15292         cursor = intel_cursor_plane_create(dev_priv, pipe);
15293         if (IS_ERR(cursor)) {
15294                 ret = PTR_ERR(cursor);
15295                 goto fail;
15296         }
15297
15298         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15299                                         &primary->base, &cursor->base,
15300                                         &intel_crtc_funcs,
15301                                         "pipe %c", pipe_name(pipe));
15302         if (ret)
15303                 goto fail;
15304
15305         intel_crtc->pipe = pipe;
15306         intel_crtc->plane = primary->plane;
15307
15308         intel_crtc->cursor_base = ~0;
15309         intel_crtc->cursor_cntl = ~0;
15310         intel_crtc->cursor_size = ~0;
15311
15312         intel_crtc->wm.cxsr_allowed = true;
15313
15314         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15315                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15316         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
15317         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
15318
15319         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15320
15321         intel_color_init(&intel_crtc->base);
15322
15323         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15324
15325         return 0;
15326
15327 fail:
15328         /*
15329          * drm_mode_config_cleanup() will free up any
15330          * crtcs/planes already initialized.
15331          */
15332         kfree(crtc_state);
15333         kfree(intel_crtc);
15334
15335         return ret;
15336 }
15337
15338 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15339 {
15340         struct drm_encoder *encoder = connector->base.encoder;
15341         struct drm_device *dev = connector->base.dev;
15342
15343         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15344
15345         if (!encoder || WARN_ON(!encoder->crtc))
15346                 return INVALID_PIPE;
15347
15348         return to_intel_crtc(encoder->crtc)->pipe;
15349 }
15350
15351 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15352                                 struct drm_file *file)
15353 {
15354         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15355         struct drm_crtc *drmmode_crtc;
15356         struct intel_crtc *crtc;
15357
15358         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15359         if (!drmmode_crtc)
15360                 return -ENOENT;
15361
15362         crtc = to_intel_crtc(drmmode_crtc);
15363         pipe_from_crtc_id->pipe = crtc->pipe;
15364
15365         return 0;
15366 }
15367
15368 static int intel_encoder_clones(struct intel_encoder *encoder)
15369 {
15370         struct drm_device *dev = encoder->base.dev;
15371         struct intel_encoder *source_encoder;
15372         int index_mask = 0;
15373         int entry = 0;
15374
15375         for_each_intel_encoder(dev, source_encoder) {
15376                 if (encoders_cloneable(encoder, source_encoder))
15377                         index_mask |= (1 << entry);
15378
15379                 entry++;
15380         }
15381
15382         return index_mask;
15383 }
15384
15385 static bool has_edp_a(struct drm_i915_private *dev_priv)
15386 {
15387         if (!IS_MOBILE(dev_priv))
15388                 return false;
15389
15390         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15391                 return false;
15392
15393         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15394                 return false;
15395
15396         return true;
15397 }
15398
15399 static bool intel_crt_present(struct drm_i915_private *dev_priv)
15400 {
15401         if (INTEL_GEN(dev_priv) >= 9)
15402                 return false;
15403
15404         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15405                 return false;
15406
15407         if (IS_CHERRYVIEW(dev_priv))
15408                 return false;
15409
15410         if (HAS_PCH_LPT_H(dev_priv) &&
15411             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15412                 return false;
15413
15414         /* DDI E can't be used if DDI A requires 4 lanes */
15415         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15416                 return false;
15417
15418         if (!dev_priv->vbt.int_crt_support)
15419                 return false;
15420
15421         return true;
15422 }
15423
15424 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15425 {
15426         int pps_num;
15427         int pps_idx;
15428
15429         if (HAS_DDI(dev_priv))
15430                 return;
15431         /*
15432          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15433          * everywhere where registers can be write protected.
15434          */
15435         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15436                 pps_num = 2;
15437         else
15438                 pps_num = 1;
15439
15440         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15441                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15442
15443                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15444                 I915_WRITE(PP_CONTROL(pps_idx), val);
15445         }
15446 }
15447
15448 static void intel_pps_init(struct drm_i915_private *dev_priv)
15449 {
15450         if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15451                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15452         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15453                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15454         else
15455                 dev_priv->pps_mmio_base = PPS_BASE;
15456
15457         intel_pps_unlock_regs_wa(dev_priv);
15458 }
15459
15460 static void intel_setup_outputs(struct drm_device *dev)
15461 {
15462         struct drm_i915_private *dev_priv = to_i915(dev);
15463         struct intel_encoder *encoder;
15464         bool dpd_is_edp = false;
15465
15466         intel_pps_init(dev_priv);
15467
15468         /*
15469          * intel_edp_init_connector() depends on this completing first, to
15470          * prevent the registeration of both eDP and LVDS and the incorrect
15471          * sharing of the PPS.
15472          */
15473         intel_lvds_init(dev);
15474
15475         if (intel_crt_present(dev_priv))
15476                 intel_crt_init(dev);
15477
15478         if (IS_BROXTON(dev_priv)) {
15479                 /*
15480                  * FIXME: Broxton doesn't support port detection via the
15481                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15482                  * detect the ports.
15483                  */
15484                 intel_ddi_init(dev, PORT_A);
15485                 intel_ddi_init(dev, PORT_B);
15486                 intel_ddi_init(dev, PORT_C);
15487
15488                 intel_dsi_init(dev);
15489         } else if (HAS_DDI(dev_priv)) {
15490                 int found;
15491
15492                 /*
15493                  * Haswell uses DDI functions to detect digital outputs.
15494                  * On SKL pre-D0 the strap isn't connected, so we assume
15495                  * it's there.
15496                  */
15497                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15498                 /* WaIgnoreDDIAStrap: skl */
15499                 if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15500                         intel_ddi_init(dev, PORT_A);
15501
15502                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15503                  * register */
15504                 found = I915_READ(SFUSE_STRAP);
15505
15506                 if (found & SFUSE_STRAP_DDIB_DETECTED)
15507                         intel_ddi_init(dev, PORT_B);
15508                 if (found & SFUSE_STRAP_DDIC_DETECTED)
15509                         intel_ddi_init(dev, PORT_C);
15510                 if (found & SFUSE_STRAP_DDID_DETECTED)
15511                         intel_ddi_init(dev, PORT_D);
15512                 /*
15513                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15514                  */
15515                 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
15516                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15517                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15518                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15519                         intel_ddi_init(dev, PORT_E);
15520
15521         } else if (HAS_PCH_SPLIT(dev_priv)) {
15522                 int found;
15523                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
15524
15525                 if (has_edp_a(dev_priv))
15526                         intel_dp_init(dev, DP_A, PORT_A);
15527
15528                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15529                         /* PCH SDVOB multiplex with HDMIB */
15530                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15531                         if (!found)
15532                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15533                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15534                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
15535                 }
15536
15537                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15538                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15539
15540                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15541                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15542
15543                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15544                         intel_dp_init(dev, PCH_DP_C, PORT_C);
15545
15546                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15547                         intel_dp_init(dev, PCH_DP_D, PORT_D);
15548         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15549                 bool has_edp, has_port;
15550
15551                 /*
15552                  * The DP_DETECTED bit is the latched state of the DDC
15553                  * SDA pin at boot. However since eDP doesn't require DDC
15554                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
15555                  * eDP ports may have been muxed to an alternate function.
15556                  * Thus we can't rely on the DP_DETECTED bit alone to detect
15557                  * eDP ports. Consult the VBT as well as DP_DETECTED to
15558                  * detect eDP ports.
15559                  *
15560                  * Sadly the straps seem to be missing sometimes even for HDMI
15561                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15562                  * and VBT for the presence of the port. Additionally we can't
15563                  * trust the port type the VBT declares as we've seen at least
15564                  * HDMI ports that the VBT claim are DP or eDP.
15565                  */
15566                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
15567                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15568                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15569                         has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15570                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15571                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15572
15573                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
15574                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15575                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15576                         has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15577                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15578                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15579
15580                 if (IS_CHERRYVIEW(dev_priv)) {
15581                         /*
15582                          * eDP not supported on port D,
15583                          * so no need to worry about it
15584                          */
15585                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15586                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15587                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
15588                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15589                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15590                 }
15591
15592                 intel_dsi_init(dev);
15593         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
15594                 bool found = false;
15595
15596                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15597                         DRM_DEBUG_KMS("probing SDVOB\n");
15598                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15599                         if (!found && IS_G4X(dev_priv)) {
15600                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15601                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15602                         }
15603
15604                         if (!found && IS_G4X(dev_priv))
15605                                 intel_dp_init(dev, DP_B, PORT_B);
15606                 }
15607
15608                 /* Before G4X SDVOC doesn't have its own detect register */
15609
15610                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15611                         DRM_DEBUG_KMS("probing SDVOC\n");
15612                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15613                 }
15614
15615                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15616
15617                         if (IS_G4X(dev_priv)) {
15618                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15619                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15620                         }
15621                         if (IS_G4X(dev_priv))
15622                                 intel_dp_init(dev, DP_C, PORT_C);
15623                 }
15624
15625                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
15626                         intel_dp_init(dev, DP_D, PORT_D);
15627         } else if (IS_GEN2(dev_priv))
15628                 intel_dvo_init(dev);
15629
15630         if (SUPPORTS_TV(dev_priv))
15631                 intel_tv_init(dev);
15632
15633         intel_psr_init(dev);
15634
15635         for_each_intel_encoder(dev, encoder) {
15636                 encoder->base.possible_crtcs = encoder->crtc_mask;
15637                 encoder->base.possible_clones =
15638                         intel_encoder_clones(encoder);
15639         }
15640
15641         intel_init_pch_refclk(dev);
15642
15643         drm_helper_move_panel_connectors_to_head(dev);
15644 }
15645
15646 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15647 {
15648         struct drm_device *dev = fb->dev;
15649         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15650
15651         drm_framebuffer_cleanup(fb);
15652         mutex_lock(&dev->struct_mutex);
15653         WARN_ON(!intel_fb->obj->framebuffer_references--);
15654         i915_gem_object_put(intel_fb->obj);
15655         mutex_unlock(&dev->struct_mutex);
15656         kfree(intel_fb);
15657 }
15658
15659 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15660                                                 struct drm_file *file,
15661                                                 unsigned int *handle)
15662 {
15663         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15664         struct drm_i915_gem_object *obj = intel_fb->obj;
15665
15666         if (obj->userptr.mm) {
15667                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15668                 return -EINVAL;
15669         }
15670
15671         return drm_gem_handle_create(file, &obj->base, handle);
15672 }
15673
15674 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15675                                         struct drm_file *file,
15676                                         unsigned flags, unsigned color,
15677                                         struct drm_clip_rect *clips,
15678                                         unsigned num_clips)
15679 {
15680         struct drm_device *dev = fb->dev;
15681         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15682         struct drm_i915_gem_object *obj = intel_fb->obj;
15683
15684         mutex_lock(&dev->struct_mutex);
15685         if (obj->pin_display && obj->cache_dirty)
15686                 i915_gem_clflush_object(obj, true);
15687         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15688         mutex_unlock(&dev->struct_mutex);
15689
15690         return 0;
15691 }
15692
15693 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15694         .destroy = intel_user_framebuffer_destroy,
15695         .create_handle = intel_user_framebuffer_create_handle,
15696         .dirty = intel_user_framebuffer_dirty,
15697 };
15698
15699 static
15700 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
15701                          uint64_t fb_modifier, uint32_t pixel_format)
15702 {
15703         u32 gen = INTEL_INFO(dev_priv)->gen;
15704
15705         if (gen >= 9) {
15706                 int cpp = drm_format_plane_cpp(pixel_format, 0);
15707
15708                 /* "The stride in bytes must not exceed the of the size of 8K
15709                  *  pixels and 32K bytes."
15710                  */
15711                 return min(8192 * cpp, 32768);
15712         } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
15713                    !IS_CHERRYVIEW(dev_priv)) {
15714                 return 32*1024;
15715         } else if (gen >= 4) {
15716                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15717                         return 16*1024;
15718                 else
15719                         return 32*1024;
15720         } else if (gen >= 3) {
15721                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15722                         return 8*1024;
15723                 else
15724                         return 16*1024;
15725         } else {
15726                 /* XXX DSPC is limited to 4k tiled */
15727                 return 8*1024;
15728         }
15729 }
15730
15731 static int intel_framebuffer_init(struct drm_device *dev,
15732                                   struct intel_framebuffer *intel_fb,
15733                                   struct drm_mode_fb_cmd2 *mode_cmd,
15734                                   struct drm_i915_gem_object *obj)
15735 {
15736         struct drm_i915_private *dev_priv = to_i915(dev);
15737         unsigned int tiling = i915_gem_object_get_tiling(obj);
15738         int ret;
15739         u32 pitch_limit, stride_alignment;
15740         struct drm_format_name_buf format_name;
15741
15742         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15743
15744         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15745                 /*
15746                  * If there's a fence, enforce that
15747                  * the fb modifier and tiling mode match.
15748                  */
15749                 if (tiling != I915_TILING_NONE &&
15750                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15751                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15752                         return -EINVAL;
15753                 }
15754         } else {
15755                 if (tiling == I915_TILING_X) {
15756                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15757                 } else if (tiling == I915_TILING_Y) {
15758                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15759                         return -EINVAL;
15760                 }
15761         }
15762
15763         /* Passed in modifier sanity checking. */
15764         switch (mode_cmd->modifier[0]) {
15765         case I915_FORMAT_MOD_Y_TILED:
15766         case I915_FORMAT_MOD_Yf_TILED:
15767                 if (INTEL_GEN(dev_priv) < 9) {
15768                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15769                                   mode_cmd->modifier[0]);
15770                         return -EINVAL;
15771                 }
15772         case DRM_FORMAT_MOD_NONE:
15773         case I915_FORMAT_MOD_X_TILED:
15774                 break;
15775         default:
15776                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15777                           mode_cmd->modifier[0]);
15778                 return -EINVAL;
15779         }
15780
15781         /*
15782          * gen2/3 display engine uses the fence if present,
15783          * so the tiling mode must match the fb modifier exactly.
15784          */
15785         if (INTEL_INFO(dev_priv)->gen < 4 &&
15786             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15787                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15788                 return -EINVAL;
15789         }
15790
15791         stride_alignment = intel_fb_stride_alignment(dev_priv,
15792                                                      mode_cmd->modifier[0],
15793                                                      mode_cmd->pixel_format);
15794         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15795                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15796                           mode_cmd->pitches[0], stride_alignment);
15797                 return -EINVAL;
15798         }
15799
15800         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
15801                                            mode_cmd->pixel_format);
15802         if (mode_cmd->pitches[0] > pitch_limit) {
15803                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15804                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15805                           "tiled" : "linear",
15806                           mode_cmd->pitches[0], pitch_limit);
15807                 return -EINVAL;
15808         }
15809
15810         /*
15811          * If there's a fence, enforce that
15812          * the fb pitch and fence stride match.
15813          */
15814         if (tiling != I915_TILING_NONE &&
15815             mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15816                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15817                           mode_cmd->pitches[0],
15818                           i915_gem_object_get_stride(obj));
15819                 return -EINVAL;
15820         }
15821
15822         /* Reject formats not supported by any plane early. */
15823         switch (mode_cmd->pixel_format) {
15824         case DRM_FORMAT_C8:
15825         case DRM_FORMAT_RGB565:
15826         case DRM_FORMAT_XRGB8888:
15827         case DRM_FORMAT_ARGB8888:
15828                 break;
15829         case DRM_FORMAT_XRGB1555:
15830                 if (INTEL_GEN(dev_priv) > 3) {
15831                         DRM_DEBUG("unsupported pixel format: %s\n",
15832                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15833                         return -EINVAL;
15834                 }
15835                 break;
15836         case DRM_FORMAT_ABGR8888:
15837                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
15838                     INTEL_GEN(dev_priv) < 9) {
15839                         DRM_DEBUG("unsupported pixel format: %s\n",
15840                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15841                         return -EINVAL;
15842                 }
15843                 break;
15844         case DRM_FORMAT_XBGR8888:
15845         case DRM_FORMAT_XRGB2101010:
15846         case DRM_FORMAT_XBGR2101010:
15847                 if (INTEL_GEN(dev_priv) < 4) {
15848                         DRM_DEBUG("unsupported pixel format: %s\n",
15849                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15850                         return -EINVAL;
15851                 }
15852                 break;
15853         case DRM_FORMAT_ABGR2101010:
15854                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
15855                         DRM_DEBUG("unsupported pixel format: %s\n",
15856                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15857                         return -EINVAL;
15858                 }
15859                 break;
15860         case DRM_FORMAT_YUYV:
15861         case DRM_FORMAT_UYVY:
15862         case DRM_FORMAT_YVYU:
15863         case DRM_FORMAT_VYUY:
15864                 if (INTEL_GEN(dev_priv) < 5) {
15865                         DRM_DEBUG("unsupported pixel format: %s\n",
15866                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15867                         return -EINVAL;
15868                 }
15869                 break;
15870         default:
15871                 DRM_DEBUG("unsupported pixel format: %s\n",
15872                           drm_get_format_name(mode_cmd->pixel_format, &format_name));
15873                 return -EINVAL;
15874         }
15875
15876         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15877         if (mode_cmd->offsets[0] != 0)
15878                 return -EINVAL;
15879
15880         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15881         intel_fb->obj = obj;
15882
15883         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15884         if (ret)
15885                 return ret;
15886
15887         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15888         if (ret) {
15889                 DRM_ERROR("framebuffer init failed %d\n", ret);
15890                 return ret;
15891         }
15892
15893         intel_fb->obj->framebuffer_references++;
15894
15895         return 0;
15896 }
15897
15898 static struct drm_framebuffer *
15899 intel_user_framebuffer_create(struct drm_device *dev,
15900                               struct drm_file *filp,
15901                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15902 {
15903         struct drm_framebuffer *fb;
15904         struct drm_i915_gem_object *obj;
15905         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15906
15907         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15908         if (!obj)
15909                 return ERR_PTR(-ENOENT);
15910
15911         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15912         if (IS_ERR(fb))
15913                 i915_gem_object_put(obj);
15914
15915         return fb;
15916 }
15917
15918 static const struct drm_mode_config_funcs intel_mode_funcs = {
15919         .fb_create = intel_user_framebuffer_create,
15920         .output_poll_changed = intel_fbdev_output_poll_changed,
15921         .atomic_check = intel_atomic_check,
15922         .atomic_commit = intel_atomic_commit,
15923         .atomic_state_alloc = intel_atomic_state_alloc,
15924         .atomic_state_clear = intel_atomic_state_clear,
15925 };
15926
15927 /**
15928  * intel_init_display_hooks - initialize the display modesetting hooks
15929  * @dev_priv: device private
15930  */
15931 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15932 {
15933         if (INTEL_INFO(dev_priv)->gen >= 9) {
15934                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15935                 dev_priv->display.get_initial_plane_config =
15936                         skylake_get_initial_plane_config;
15937                 dev_priv->display.crtc_compute_clock =
15938                         haswell_crtc_compute_clock;
15939                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15940                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15941         } else if (HAS_DDI(dev_priv)) {
15942                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15943                 dev_priv->display.get_initial_plane_config =
15944                         ironlake_get_initial_plane_config;
15945                 dev_priv->display.crtc_compute_clock =
15946                         haswell_crtc_compute_clock;
15947                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15948                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15949         } else if (HAS_PCH_SPLIT(dev_priv)) {
15950                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15951                 dev_priv->display.get_initial_plane_config =
15952                         ironlake_get_initial_plane_config;
15953                 dev_priv->display.crtc_compute_clock =
15954                         ironlake_crtc_compute_clock;
15955                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15956                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15957         } else if (IS_CHERRYVIEW(dev_priv)) {
15958                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15959                 dev_priv->display.get_initial_plane_config =
15960                         i9xx_get_initial_plane_config;
15961                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15962                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15963                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15964         } else if (IS_VALLEYVIEW(dev_priv)) {
15965                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15966                 dev_priv->display.get_initial_plane_config =
15967                         i9xx_get_initial_plane_config;
15968                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15969                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15970                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15971         } else if (IS_G4X(dev_priv)) {
15972                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15973                 dev_priv->display.get_initial_plane_config =
15974                         i9xx_get_initial_plane_config;
15975                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15976                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15977                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15978         } else if (IS_PINEVIEW(dev_priv)) {
15979                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15980                 dev_priv->display.get_initial_plane_config =
15981                         i9xx_get_initial_plane_config;
15982                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15983                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15984                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15985         } else if (!IS_GEN2(dev_priv)) {
15986                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15987                 dev_priv->display.get_initial_plane_config =
15988                         i9xx_get_initial_plane_config;
15989                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15990                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15991                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15992         } else {
15993                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15994                 dev_priv->display.get_initial_plane_config =
15995                         i9xx_get_initial_plane_config;
15996                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15997                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15998                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15999         }
16000
16001         /* Returns the core display clock speed */
16002         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
16003                 dev_priv->display.get_display_clock_speed =
16004                         skylake_get_display_clock_speed;
16005         else if (IS_BROXTON(dev_priv))
16006                 dev_priv->display.get_display_clock_speed =
16007                         broxton_get_display_clock_speed;
16008         else if (IS_BROADWELL(dev_priv))
16009                 dev_priv->display.get_display_clock_speed =
16010                         broadwell_get_display_clock_speed;
16011         else if (IS_HASWELL(dev_priv))
16012                 dev_priv->display.get_display_clock_speed =
16013                         haswell_get_display_clock_speed;
16014         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16015                 dev_priv->display.get_display_clock_speed =
16016                         valleyview_get_display_clock_speed;
16017         else if (IS_GEN5(dev_priv))
16018                 dev_priv->display.get_display_clock_speed =
16019                         ilk_get_display_clock_speed;
16020         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
16021                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
16022                 dev_priv->display.get_display_clock_speed =
16023                         i945_get_display_clock_speed;
16024         else if (IS_GM45(dev_priv))
16025                 dev_priv->display.get_display_clock_speed =
16026                         gm45_get_display_clock_speed;
16027         else if (IS_CRESTLINE(dev_priv))
16028                 dev_priv->display.get_display_clock_speed =
16029                         i965gm_get_display_clock_speed;
16030         else if (IS_PINEVIEW(dev_priv))
16031                 dev_priv->display.get_display_clock_speed =
16032                         pnv_get_display_clock_speed;
16033         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
16034                 dev_priv->display.get_display_clock_speed =
16035                         g33_get_display_clock_speed;
16036         else if (IS_I915G(dev_priv))
16037                 dev_priv->display.get_display_clock_speed =
16038                         i915_get_display_clock_speed;
16039         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
16040                 dev_priv->display.get_display_clock_speed =
16041                         i9xx_misc_get_display_clock_speed;
16042         else if (IS_I915GM(dev_priv))
16043                 dev_priv->display.get_display_clock_speed =
16044                         i915gm_get_display_clock_speed;
16045         else if (IS_I865G(dev_priv))
16046                 dev_priv->display.get_display_clock_speed =
16047                         i865_get_display_clock_speed;
16048         else if (IS_I85X(dev_priv))
16049                 dev_priv->display.get_display_clock_speed =
16050                         i85x_get_display_clock_speed;
16051         else { /* 830 */
16052                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
16053                 dev_priv->display.get_display_clock_speed =
16054                         i830_get_display_clock_speed;
16055         }
16056
16057         if (IS_GEN5(dev_priv)) {
16058                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16059         } else if (IS_GEN6(dev_priv)) {
16060                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16061         } else if (IS_IVYBRIDGE(dev_priv)) {
16062                 /* FIXME: detect B0+ stepping and use auto training */
16063                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16064         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16065                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16066         }
16067
16068         if (IS_BROADWELL(dev_priv)) {
16069                 dev_priv->display.modeset_commit_cdclk =
16070                         broadwell_modeset_commit_cdclk;
16071                 dev_priv->display.modeset_calc_cdclk =
16072                         broadwell_modeset_calc_cdclk;
16073         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16074                 dev_priv->display.modeset_commit_cdclk =
16075                         valleyview_modeset_commit_cdclk;
16076                 dev_priv->display.modeset_calc_cdclk =
16077                         valleyview_modeset_calc_cdclk;
16078         } else if (IS_BROXTON(dev_priv)) {
16079                 dev_priv->display.modeset_commit_cdclk =
16080                         bxt_modeset_commit_cdclk;
16081                 dev_priv->display.modeset_calc_cdclk =
16082                         bxt_modeset_calc_cdclk;
16083         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16084                 dev_priv->display.modeset_commit_cdclk =
16085                         skl_modeset_commit_cdclk;
16086                 dev_priv->display.modeset_calc_cdclk =
16087                         skl_modeset_calc_cdclk;
16088         }
16089
16090         if (dev_priv->info.gen >= 9)
16091                 dev_priv->display.update_crtcs = skl_update_crtcs;
16092         else
16093                 dev_priv->display.update_crtcs = intel_update_crtcs;
16094
16095         switch (INTEL_INFO(dev_priv)->gen) {
16096         case 2:
16097                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16098                 break;
16099
16100         case 3:
16101                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16102                 break;
16103
16104         case 4:
16105         case 5:
16106                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16107                 break;
16108
16109         case 6:
16110                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16111                 break;
16112         case 7:
16113         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16114                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16115                 break;
16116         case 9:
16117                 /* Drop through - unsupported since execlist only. */
16118         default:
16119                 /* Default just returns -ENODEV to indicate unsupported */
16120                 dev_priv->display.queue_flip = intel_default_queue_flip;
16121         }
16122 }
16123
16124 /*
16125  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16126  * resume, or other times.  This quirk makes sure that's the case for
16127  * affected systems.
16128  */
16129 static void quirk_pipea_force(struct drm_device *dev)
16130 {
16131         struct drm_i915_private *dev_priv = to_i915(dev);
16132
16133         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16134         DRM_INFO("applying pipe a force quirk\n");
16135 }
16136
16137 static void quirk_pipeb_force(struct drm_device *dev)
16138 {
16139         struct drm_i915_private *dev_priv = to_i915(dev);
16140
16141         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16142         DRM_INFO("applying pipe b force quirk\n");
16143 }
16144
16145 /*
16146  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16147  */
16148 static void quirk_ssc_force_disable(struct drm_device *dev)
16149 {
16150         struct drm_i915_private *dev_priv = to_i915(dev);
16151         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16152         DRM_INFO("applying lvds SSC disable quirk\n");
16153 }
16154
16155 /*
16156  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16157  * brightness value
16158  */
16159 static void quirk_invert_brightness(struct drm_device *dev)
16160 {
16161         struct drm_i915_private *dev_priv = to_i915(dev);
16162         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16163         DRM_INFO("applying inverted panel brightness quirk\n");
16164 }
16165
16166 /* Some VBT's incorrectly indicate no backlight is present */
16167 static void quirk_backlight_present(struct drm_device *dev)
16168 {
16169         struct drm_i915_private *dev_priv = to_i915(dev);
16170         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16171         DRM_INFO("applying backlight present quirk\n");
16172 }
16173
16174 struct intel_quirk {
16175         int device;
16176         int subsystem_vendor;
16177         int subsystem_device;
16178         void (*hook)(struct drm_device *dev);
16179 };
16180
16181 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16182 struct intel_dmi_quirk {
16183         void (*hook)(struct drm_device *dev);
16184         const struct dmi_system_id (*dmi_id_list)[];
16185 };
16186
16187 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16188 {
16189         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16190         return 1;
16191 }
16192
16193 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16194         {
16195                 .dmi_id_list = &(const struct dmi_system_id[]) {
16196                         {
16197                                 .callback = intel_dmi_reverse_brightness,
16198                                 .ident = "NCR Corporation",
16199                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16200                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
16201                                 },
16202                         },
16203                         { }  /* terminating entry */
16204                 },
16205                 .hook = quirk_invert_brightness,
16206         },
16207 };
16208
16209 static struct intel_quirk intel_quirks[] = {
16210         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16211         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16212
16213         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16214         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16215
16216         /* 830 needs to leave pipe A & dpll A up */
16217         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16218
16219         /* 830 needs to leave pipe B & dpll B up */
16220         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16221
16222         /* Lenovo U160 cannot use SSC on LVDS */
16223         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16224
16225         /* Sony Vaio Y cannot use SSC on LVDS */
16226         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16227
16228         /* Acer Aspire 5734Z must invert backlight brightness */
16229         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16230
16231         /* Acer/eMachines G725 */
16232         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16233
16234         /* Acer/eMachines e725 */
16235         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16236
16237         /* Acer/Packard Bell NCL20 */
16238         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16239
16240         /* Acer Aspire 4736Z */
16241         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16242
16243         /* Acer Aspire 5336 */
16244         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16245
16246         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16247         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16248
16249         /* Acer C720 Chromebook (Core i3 4005U) */
16250         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16251
16252         /* Apple Macbook 2,1 (Core 2 T7400) */
16253         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16254
16255         /* Apple Macbook 4,1 */
16256         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16257
16258         /* Toshiba CB35 Chromebook (Celeron 2955U) */
16259         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16260
16261         /* HP Chromebook 14 (Celeron 2955U) */
16262         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16263
16264         /* Dell Chromebook 11 */
16265         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16266
16267         /* Dell Chromebook 11 (2015 version) */
16268         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16269 };
16270
16271 static void intel_init_quirks(struct drm_device *dev)
16272 {
16273         struct pci_dev *d = dev->pdev;
16274         int i;
16275
16276         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16277                 struct intel_quirk *q = &intel_quirks[i];
16278
16279                 if (d->device == q->device &&
16280                     (d->subsystem_vendor == q->subsystem_vendor ||
16281                      q->subsystem_vendor == PCI_ANY_ID) &&
16282                     (d->subsystem_device == q->subsystem_device ||
16283                      q->subsystem_device == PCI_ANY_ID))
16284                         q->hook(dev);
16285         }
16286         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16287                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16288                         intel_dmi_quirks[i].hook(dev);
16289         }
16290 }
16291
16292 /* Disable the VGA plane that we never use */
16293 static void i915_disable_vga(struct drm_i915_private *dev_priv)
16294 {
16295         struct pci_dev *pdev = dev_priv->drm.pdev;
16296         u8 sr1;
16297         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16298
16299         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16300         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16301         outb(SR01, VGA_SR_INDEX);
16302         sr1 = inb(VGA_SR_DATA);
16303         outb(sr1 | 1<<5, VGA_SR_DATA);
16304         vga_put(pdev, VGA_RSRC_LEGACY_IO);
16305         udelay(300);
16306
16307         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16308         POSTING_READ(vga_reg);
16309 }
16310
16311 void intel_modeset_init_hw(struct drm_device *dev)
16312 {
16313         struct drm_i915_private *dev_priv = to_i915(dev);
16314
16315         intel_update_cdclk(dev_priv);
16316
16317         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16318
16319         intel_init_clock_gating(dev_priv);
16320 }
16321
16322 /*
16323  * Calculate what we think the watermarks should be for the state we've read
16324  * out of the hardware and then immediately program those watermarks so that
16325  * we ensure the hardware settings match our internal state.
16326  *
16327  * We can calculate what we think WM's should be by creating a duplicate of the
16328  * current state (which was constructed during hardware readout) and running it
16329  * through the atomic check code to calculate new watermark values in the
16330  * state object.
16331  */
16332 static void sanitize_watermarks(struct drm_device *dev)
16333 {
16334         struct drm_i915_private *dev_priv = to_i915(dev);
16335         struct drm_atomic_state *state;
16336         struct intel_atomic_state *intel_state;
16337         struct drm_crtc *crtc;
16338         struct drm_crtc_state *cstate;
16339         struct drm_modeset_acquire_ctx ctx;
16340         int ret;
16341         int i;
16342
16343         /* Only supported on platforms that use atomic watermark design */
16344         if (!dev_priv->display.optimize_watermarks)
16345                 return;
16346
16347         /*
16348          * We need to hold connection_mutex before calling duplicate_state so
16349          * that the connector loop is protected.
16350          */
16351         drm_modeset_acquire_init(&ctx, 0);
16352 retry:
16353         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16354         if (ret == -EDEADLK) {
16355                 drm_modeset_backoff(&ctx);
16356                 goto retry;
16357         } else if (WARN_ON(ret)) {
16358                 goto fail;
16359         }
16360
16361         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16362         if (WARN_ON(IS_ERR(state)))
16363                 goto fail;
16364
16365         intel_state = to_intel_atomic_state(state);
16366
16367         /*
16368          * Hardware readout is the only time we don't want to calculate
16369          * intermediate watermarks (since we don't trust the current
16370          * watermarks).
16371          */
16372         intel_state->skip_intermediate_wm = true;
16373
16374         ret = intel_atomic_check(dev, state);
16375         if (ret) {
16376                 /*
16377                  * If we fail here, it means that the hardware appears to be
16378                  * programmed in a way that shouldn't be possible, given our
16379                  * understanding of watermark requirements.  This might mean a
16380                  * mistake in the hardware readout code or a mistake in the
16381                  * watermark calculations for a given platform.  Raise a WARN
16382                  * so that this is noticeable.
16383                  *
16384                  * If this actually happens, we'll have to just leave the
16385                  * BIOS-programmed watermarks untouched and hope for the best.
16386                  */
16387                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16388                 goto put_state;
16389         }
16390
16391         /* Write calculated watermark values back */
16392         for_each_crtc_in_state(state, crtc, cstate, i) {
16393                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16394
16395                 cs->wm.need_postvbl_update = true;
16396                 dev_priv->display.optimize_watermarks(intel_state, cs);
16397         }
16398
16399 put_state:
16400         drm_atomic_state_put(state);
16401 fail:
16402         drm_modeset_drop_locks(&ctx);
16403         drm_modeset_acquire_fini(&ctx);
16404 }
16405
16406 int intel_modeset_init(struct drm_device *dev)
16407 {
16408         struct drm_i915_private *dev_priv = to_i915(dev);
16409         struct i915_ggtt *ggtt = &dev_priv->ggtt;
16410         enum pipe pipe;
16411         struct intel_crtc *crtc;
16412
16413         drm_mode_config_init(dev);
16414
16415         dev->mode_config.min_width = 0;
16416         dev->mode_config.min_height = 0;
16417
16418         dev->mode_config.preferred_depth = 24;
16419         dev->mode_config.prefer_shadow = 1;
16420
16421         dev->mode_config.allow_fb_modifiers = true;
16422
16423         dev->mode_config.funcs = &intel_mode_funcs;
16424
16425         intel_init_quirks(dev);
16426
16427         intel_init_pm(dev_priv);
16428
16429         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16430                 return 0;
16431
16432         /*
16433          * There may be no VBT; and if the BIOS enabled SSC we can
16434          * just keep using it to avoid unnecessary flicker.  Whereas if the
16435          * BIOS isn't using it, don't assume it will work even if the VBT
16436          * indicates as much.
16437          */
16438         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
16439                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16440                                             DREF_SSC1_ENABLE);
16441
16442                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16443                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16444                                      bios_lvds_use_ssc ? "en" : "dis",
16445                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16446                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16447                 }
16448         }
16449
16450         if (IS_GEN2(dev_priv)) {
16451                 dev->mode_config.max_width = 2048;
16452                 dev->mode_config.max_height = 2048;
16453         } else if (IS_GEN3(dev_priv)) {
16454                 dev->mode_config.max_width = 4096;
16455                 dev->mode_config.max_height = 4096;
16456         } else {
16457                 dev->mode_config.max_width = 8192;
16458                 dev->mode_config.max_height = 8192;
16459         }
16460
16461         if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
16462                 dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
16463                 dev->mode_config.cursor_height = 1023;
16464         } else if (IS_GEN2(dev_priv)) {
16465                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16466                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16467         } else {
16468                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16469                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16470         }
16471
16472         dev->mode_config.fb_base = ggtt->mappable_base;
16473
16474         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16475                       INTEL_INFO(dev_priv)->num_pipes,
16476                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
16477
16478         for_each_pipe(dev_priv, pipe) {
16479                 int ret;
16480
16481                 ret = intel_crtc_init(dev_priv, pipe);
16482                 if (ret) {
16483                         drm_mode_config_cleanup(dev);
16484                         return ret;
16485                 }
16486         }
16487
16488         intel_update_czclk(dev_priv);
16489         intel_update_cdclk(dev_priv);
16490         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16491
16492         intel_shared_dpll_init(dev);
16493
16494         if (dev_priv->max_cdclk_freq == 0)
16495                 intel_update_max_cdclk(dev_priv);
16496
16497         /* Just disable it once at startup */
16498         i915_disable_vga(dev_priv);
16499         intel_setup_outputs(dev);
16500
16501         drm_modeset_lock_all(dev);
16502         intel_modeset_setup_hw_state(dev);
16503         drm_modeset_unlock_all(dev);
16504
16505         for_each_intel_crtc(dev, crtc) {
16506                 struct intel_initial_plane_config plane_config = {};
16507
16508                 if (!crtc->active)
16509                         continue;
16510
16511                 /*
16512                  * Note that reserving the BIOS fb up front prevents us
16513                  * from stuffing other stolen allocations like the ring
16514                  * on top.  This prevents some ugliness at boot time, and
16515                  * can even allow for smooth boot transitions if the BIOS
16516                  * fb is large enough for the active pipe configuration.
16517                  */
16518                 dev_priv->display.get_initial_plane_config(crtc,
16519                                                            &plane_config);
16520
16521                 /*
16522                  * If the fb is shared between multiple heads, we'll
16523                  * just get the first one.
16524                  */
16525                 intel_find_initial_plane_obj(crtc, &plane_config);
16526         }
16527
16528         /*
16529          * Make sure hardware watermarks really match the state we read out.
16530          * Note that we need to do this after reconstructing the BIOS fb's
16531          * since the watermark calculation done here will use pstate->fb.
16532          */
16533         sanitize_watermarks(dev);
16534
16535         return 0;
16536 }
16537
16538 static void intel_enable_pipe_a(struct drm_device *dev)
16539 {
16540         struct intel_connector *connector;
16541         struct drm_connector *crt = NULL;
16542         struct intel_load_detect_pipe load_detect_temp;
16543         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16544
16545         /* We can't just switch on the pipe A, we need to set things up with a
16546          * proper mode and output configuration. As a gross hack, enable pipe A
16547          * by enabling the load detect pipe once. */
16548         for_each_intel_connector(dev, connector) {
16549                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16550                         crt = &connector->base;
16551                         break;
16552                 }
16553         }
16554
16555         if (!crt)
16556                 return;
16557
16558         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16559                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16560 }
16561
16562 static bool
16563 intel_check_plane_mapping(struct intel_crtc *crtc)
16564 {
16565         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
16566         u32 val;
16567
16568         if (INTEL_INFO(dev_priv)->num_pipes == 1)
16569                 return true;
16570
16571         val = I915_READ(DSPCNTR(!crtc->plane));
16572
16573         if ((val & DISPLAY_PLANE_ENABLE) &&
16574             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16575                 return false;
16576
16577         return true;
16578 }
16579
16580 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16581 {
16582         struct drm_device *dev = crtc->base.dev;
16583         struct intel_encoder *encoder;
16584
16585         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16586                 return true;
16587
16588         return false;
16589 }
16590
16591 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16592 {
16593         struct drm_device *dev = encoder->base.dev;
16594         struct intel_connector *connector;
16595
16596         for_each_connector_on_encoder(dev, &encoder->base, connector)
16597                 return connector;
16598
16599         return NULL;
16600 }
16601
16602 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16603                               enum transcoder pch_transcoder)
16604 {
16605         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16606                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16607 }
16608
16609 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16610 {
16611         struct drm_device *dev = crtc->base.dev;
16612         struct drm_i915_private *dev_priv = to_i915(dev);
16613         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16614
16615         /* Clear any frame start delays used for debugging left by the BIOS */
16616         if (!transcoder_is_dsi(cpu_transcoder)) {
16617                 i915_reg_t reg = PIPECONF(cpu_transcoder);
16618
16619                 I915_WRITE(reg,
16620                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16621         }
16622
16623         /* restore vblank interrupts to correct state */
16624         drm_crtc_vblank_reset(&crtc->base);
16625         if (crtc->active) {
16626                 struct intel_plane *plane;
16627
16628                 drm_crtc_vblank_on(&crtc->base);
16629
16630                 /* Disable everything but the primary plane */
16631                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16632                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16633                                 continue;
16634
16635                         plane->disable_plane(&plane->base, &crtc->base);
16636                 }
16637         }
16638
16639         /* We need to sanitize the plane -> pipe mapping first because this will
16640          * disable the crtc (and hence change the state) if it is wrong. Note
16641          * that gen4+ has a fixed plane -> pipe mapping.  */
16642         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
16643                 bool plane;
16644
16645                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16646                               crtc->base.base.id, crtc->base.name);
16647
16648                 /* Pipe has the wrong plane attached and the plane is active.
16649                  * Temporarily change the plane mapping and disable everything
16650                  * ...  */
16651                 plane = crtc->plane;
16652                 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16653                 crtc->plane = !plane;
16654                 intel_crtc_disable_noatomic(&crtc->base);
16655                 crtc->plane = plane;
16656         }
16657
16658         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16659             crtc->pipe == PIPE_A && !crtc->active) {
16660                 /* BIOS forgot to enable pipe A, this mostly happens after
16661                  * resume. Force-enable the pipe to fix this, the update_dpms
16662                  * call below we restore the pipe to the right state, but leave
16663                  * the required bits on. */
16664                 intel_enable_pipe_a(dev);
16665         }
16666
16667         /* Adjust the state of the output pipe according to whether we
16668          * have active connectors/encoders. */
16669         if (crtc->active && !intel_crtc_has_encoders(crtc))
16670                 intel_crtc_disable_noatomic(&crtc->base);
16671
16672         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
16673                 /*
16674                  * We start out with underrun reporting disabled to avoid races.
16675                  * For correct bookkeeping mark this on active crtcs.
16676                  *
16677                  * Also on gmch platforms we dont have any hardware bits to
16678                  * disable the underrun reporting. Which means we need to start
16679                  * out with underrun reporting disabled also on inactive pipes,
16680                  * since otherwise we'll complain about the garbage we read when
16681                  * e.g. coming up after runtime pm.
16682                  *
16683                  * No protection against concurrent access is required - at
16684                  * worst a fifo underrun happens which also sets this to false.
16685                  */
16686                 crtc->cpu_fifo_underrun_disabled = true;
16687                 /*
16688                  * We track the PCH trancoder underrun reporting state
16689                  * within the crtc. With crtc for pipe A housing the underrun
16690                  * reporting state for PCH transcoder A, crtc for pipe B housing
16691                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16692                  * and marking underrun reporting as disabled for the non-existing
16693                  * PCH transcoders B and C would prevent enabling the south
16694                  * error interrupt (see cpt_can_enable_serr_int()).
16695                  */
16696                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16697                         crtc->pch_fifo_underrun_disabled = true;
16698         }
16699 }
16700
16701 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16702 {
16703         struct intel_connector *connector;
16704
16705         /* We need to check both for a crtc link (meaning that the
16706          * encoder is active and trying to read from a pipe) and the
16707          * pipe itself being active. */
16708         bool has_active_crtc = encoder->base.crtc &&
16709                 to_intel_crtc(encoder->base.crtc)->active;
16710
16711         connector = intel_encoder_find_connector(encoder);
16712         if (connector && !has_active_crtc) {
16713                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16714                               encoder->base.base.id,
16715                               encoder->base.name);
16716
16717                 /* Connector is active, but has no active pipe. This is
16718                  * fallout from our resume register restoring. Disable
16719                  * the encoder manually again. */
16720                 if (encoder->base.crtc) {
16721                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16722
16723                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16724                                       encoder->base.base.id,
16725                                       encoder->base.name);
16726                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16727                         if (encoder->post_disable)
16728                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16729                 }
16730                 encoder->base.crtc = NULL;
16731
16732                 /* Inconsistent output/port/pipe state happens presumably due to
16733                  * a bug in one of the get_hw_state functions. Or someplace else
16734                  * in our code, like the register restore mess on resume. Clamp
16735                  * things to off as a safer default. */
16736
16737                 connector->base.dpms = DRM_MODE_DPMS_OFF;
16738                 connector->base.encoder = NULL;
16739         }
16740         /* Enabled encoders without active connectors will be fixed in
16741          * the crtc fixup. */
16742 }
16743
16744 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
16745 {
16746         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16747
16748         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16749                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16750                 i915_disable_vga(dev_priv);
16751         }
16752 }
16753
16754 void i915_redisable_vga(struct drm_i915_private *dev_priv)
16755 {
16756         /* This function can be called both from intel_modeset_setup_hw_state or
16757          * at a very early point in our resume sequence, where the power well
16758          * structures are not yet restored. Since this function is at a very
16759          * paranoid "someone might have enabled VGA while we were not looking"
16760          * level, just check if the power well is enabled instead of trying to
16761          * follow the "don't touch the power well if we don't need it" policy
16762          * the rest of the driver uses. */
16763         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16764                 return;
16765
16766         i915_redisable_vga_power_on(dev_priv);
16767
16768         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16769 }
16770
16771 static bool primary_get_hw_state(struct intel_plane *plane)
16772 {
16773         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16774
16775         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16776 }
16777
16778 /* FIXME read out full plane state for all planes */
16779 static void readout_plane_state(struct intel_crtc *crtc)
16780 {
16781         struct drm_plane *primary = crtc->base.primary;
16782         struct intel_plane_state *plane_state =
16783                 to_intel_plane_state(primary->state);
16784
16785         plane_state->base.visible = crtc->active &&
16786                 primary_get_hw_state(to_intel_plane(primary));
16787
16788         if (plane_state->base.visible)
16789                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16790 }
16791
16792 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16793 {
16794         struct drm_i915_private *dev_priv = to_i915(dev);
16795         enum pipe pipe;
16796         struct intel_crtc *crtc;
16797         struct intel_encoder *encoder;
16798         struct intel_connector *connector;
16799         int i;
16800
16801         dev_priv->active_crtcs = 0;
16802
16803         for_each_intel_crtc(dev, crtc) {
16804                 struct intel_crtc_state *crtc_state = crtc->config;
16805                 int pixclk = 0;
16806
16807                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16808                 memset(crtc_state, 0, sizeof(*crtc_state));
16809                 crtc_state->base.crtc = &crtc->base;
16810
16811                 crtc_state->base.active = crtc_state->base.enable =
16812                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16813
16814                 crtc->base.enabled = crtc_state->base.enable;
16815                 crtc->active = crtc_state->base.active;
16816
16817                 if (crtc_state->base.active) {
16818                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16819
16820                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16821                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
16822                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16823                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16824                         else
16825                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16826
16827                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16828                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16829                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16830                 }
16831
16832                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16833
16834                 readout_plane_state(crtc);
16835
16836                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16837                               crtc->base.base.id, crtc->base.name,
16838                               enableddisabled(crtc->active));
16839         }
16840
16841         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16842                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16843
16844                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16845                                                   &pll->config.hw_state);
16846                 pll->config.crtc_mask = 0;
16847                 for_each_intel_crtc(dev, crtc) {
16848                         if (crtc->active && crtc->config->shared_dpll == pll)
16849                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16850                 }
16851                 pll->active_mask = pll->config.crtc_mask;
16852
16853                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16854                               pll->name, pll->config.crtc_mask, pll->on);
16855         }
16856
16857         for_each_intel_encoder(dev, encoder) {
16858                 pipe = 0;
16859
16860                 if (encoder->get_hw_state(encoder, &pipe)) {
16861                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16862
16863                         encoder->base.crtc = &crtc->base;
16864                         crtc->config->output_types |= 1 << encoder->type;
16865                         encoder->get_config(encoder, crtc->config);
16866                 } else {
16867                         encoder->base.crtc = NULL;
16868                 }
16869
16870                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16871                               encoder->base.base.id, encoder->base.name,
16872                               enableddisabled(encoder->base.crtc),
16873                               pipe_name(pipe));
16874         }
16875
16876         for_each_intel_connector(dev, connector) {
16877                 if (connector->get_hw_state(connector)) {
16878                         connector->base.dpms = DRM_MODE_DPMS_ON;
16879
16880                         encoder = connector->encoder;
16881                         connector->base.encoder = &encoder->base;
16882
16883                         if (encoder->base.crtc &&
16884                             encoder->base.crtc->state->active) {
16885                                 /*
16886                                  * This has to be done during hardware readout
16887                                  * because anything calling .crtc_disable may
16888                                  * rely on the connector_mask being accurate.
16889                                  */
16890                                 encoder->base.crtc->state->connector_mask |=
16891                                         1 << drm_connector_index(&connector->base);
16892                                 encoder->base.crtc->state->encoder_mask |=
16893                                         1 << drm_encoder_index(&encoder->base);
16894                         }
16895
16896                 } else {
16897                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16898                         connector->base.encoder = NULL;
16899                 }
16900                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16901                               connector->base.base.id, connector->base.name,
16902                               enableddisabled(connector->base.encoder));
16903         }
16904
16905         for_each_intel_crtc(dev, crtc) {
16906                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16907
16908                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16909                 if (crtc->base.state->active) {
16910                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16911                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16912                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16913
16914                         /*
16915                          * The initial mode needs to be set in order to keep
16916                          * the atomic core happy. It wants a valid mode if the
16917                          * crtc's enabled, so we do the above call.
16918                          *
16919                          * At this point some state updated by the connectors
16920                          * in their ->detect() callback has not run yet, so
16921                          * no recalculation can be done yet.
16922                          *
16923                          * Even if we could do a recalculation and modeset
16924                          * right now it would cause a double modeset if
16925                          * fbdev or userspace chooses a different initial mode.
16926                          *
16927                          * If that happens, someone indicated they wanted a
16928                          * mode change, which means it's safe to do a full
16929                          * recalculation.
16930                          */
16931                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16932
16933                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16934                         update_scanline_offset(crtc);
16935                 }
16936
16937                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16938         }
16939 }
16940
16941 /* Scan out the current hw modeset state,
16942  * and sanitizes it to the current state
16943  */
16944 static void
16945 intel_modeset_setup_hw_state(struct drm_device *dev)
16946 {
16947         struct drm_i915_private *dev_priv = to_i915(dev);
16948         enum pipe pipe;
16949         struct intel_crtc *crtc;
16950         struct intel_encoder *encoder;
16951         int i;
16952
16953         intel_modeset_readout_hw_state(dev);
16954
16955         /* HW state is read out, now we need to sanitize this mess. */
16956         for_each_intel_encoder(dev, encoder) {
16957                 intel_sanitize_encoder(encoder);
16958         }
16959
16960         for_each_pipe(dev_priv, pipe) {
16961                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16962
16963                 intel_sanitize_crtc(crtc);
16964                 intel_dump_pipe_config(crtc, crtc->config,
16965                                        "[setup_hw_state]");
16966         }
16967
16968         intel_modeset_update_connector_atomic_state(dev);
16969
16970         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16971                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16972
16973                 if (!pll->on || pll->active_mask)
16974                         continue;
16975
16976                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16977
16978                 pll->funcs.disable(dev_priv, pll);
16979                 pll->on = false;
16980         }
16981
16982         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16983                 vlv_wm_get_hw_state(dev);
16984         else if (IS_GEN9(dev_priv))
16985                 skl_wm_get_hw_state(dev);
16986         else if (HAS_PCH_SPLIT(dev_priv))
16987                 ilk_wm_get_hw_state(dev);
16988
16989         for_each_intel_crtc(dev, crtc) {
16990                 unsigned long put_domains;
16991
16992                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16993                 if (WARN_ON(put_domains))
16994                         modeset_put_power_domains(dev_priv, put_domains);
16995         }
16996         intel_display_set_init_power(dev_priv, false);
16997
16998         intel_fbc_init_pipe_state(dev_priv);
16999 }
17000
17001 void intel_display_resume(struct drm_device *dev)
17002 {
17003         struct drm_i915_private *dev_priv = to_i915(dev);
17004         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17005         struct drm_modeset_acquire_ctx ctx;
17006         int ret;
17007
17008         dev_priv->modeset_restore_state = NULL;
17009         if (state)
17010                 state->acquire_ctx = &ctx;
17011
17012         /*
17013          * This is a cludge because with real atomic modeset mode_config.mutex
17014          * won't be taken. Unfortunately some probed state like
17015          * audio_codec_enable is still protected by mode_config.mutex, so lock
17016          * it here for now.
17017          */
17018         mutex_lock(&dev->mode_config.mutex);
17019         drm_modeset_acquire_init(&ctx, 0);
17020
17021         while (1) {
17022                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17023                 if (ret != -EDEADLK)
17024                         break;
17025
17026                 drm_modeset_backoff(&ctx);
17027         }
17028
17029         if (!ret)
17030                 ret = __intel_display_resume(dev, state);
17031
17032         drm_modeset_drop_locks(&ctx);
17033         drm_modeset_acquire_fini(&ctx);
17034         mutex_unlock(&dev->mode_config.mutex);
17035
17036         if (ret)
17037                 DRM_ERROR("Restoring old state failed with %i\n", ret);
17038         drm_atomic_state_put(state);
17039 }
17040
17041 void intel_modeset_gem_init(struct drm_device *dev)
17042 {
17043         struct drm_i915_private *dev_priv = to_i915(dev);
17044         struct drm_crtc *c;
17045         struct drm_i915_gem_object *obj;
17046
17047         intel_init_gt_powersave(dev_priv);
17048
17049         intel_modeset_init_hw(dev);
17050
17051         intel_setup_overlay(dev_priv);
17052
17053         /*
17054          * Make sure any fbs we allocated at startup are properly
17055          * pinned & fenced.  When we do the allocation it's too early
17056          * for this.
17057          */
17058         for_each_crtc(dev, c) {
17059                 struct i915_vma *vma;
17060
17061                 obj = intel_fb_obj(c->primary->fb);
17062                 if (obj == NULL)
17063                         continue;
17064
17065                 mutex_lock(&dev->struct_mutex);
17066                 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
17067                                                  c->primary->state->rotation);
17068                 mutex_unlock(&dev->struct_mutex);
17069                 if (IS_ERR(vma)) {
17070                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
17071                                   to_intel_crtc(c)->pipe);
17072                         drm_framebuffer_unreference(c->primary->fb);
17073                         c->primary->fb = NULL;
17074                         c->primary->crtc = c->primary->state->crtc = NULL;
17075                         update_state_fb(c->primary);
17076                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
17077                 }
17078         }
17079 }
17080
17081 int intel_connector_register(struct drm_connector *connector)
17082 {
17083         struct intel_connector *intel_connector = to_intel_connector(connector);
17084         int ret;
17085
17086         ret = intel_backlight_device_register(intel_connector);
17087         if (ret)
17088                 goto err;
17089
17090         return 0;
17091
17092 err:
17093         return ret;
17094 }
17095
17096 void intel_connector_unregister(struct drm_connector *connector)
17097 {
17098         struct intel_connector *intel_connector = to_intel_connector(connector);
17099
17100         intel_backlight_device_unregister(intel_connector);
17101         intel_panel_destroy_backlight(connector);
17102 }
17103
17104 void intel_modeset_cleanup(struct drm_device *dev)
17105 {
17106         struct drm_i915_private *dev_priv = to_i915(dev);
17107
17108         intel_disable_gt_powersave(dev_priv);
17109
17110         /*
17111          * Interrupts and polling as the first thing to avoid creating havoc.
17112          * Too much stuff here (turning of connectors, ...) would
17113          * experience fancy races otherwise.
17114          */
17115         intel_irq_uninstall(dev_priv);
17116
17117         /*
17118          * Due to the hpd irq storm handling the hotplug work can re-arm the
17119          * poll handlers. Hence disable polling after hpd handling is shut down.
17120          */
17121         drm_kms_helper_poll_fini(dev);
17122
17123         intel_unregister_dsm_handler();
17124
17125         intel_fbc_global_disable(dev_priv);
17126
17127         /* flush any delayed tasks or pending work */
17128         flush_scheduled_work();
17129
17130         drm_mode_config_cleanup(dev);
17131
17132         intel_cleanup_overlay(dev_priv);
17133
17134         intel_cleanup_gt_powersave(dev_priv);
17135
17136         intel_teardown_gmbus(dev);
17137 }
17138
17139 void intel_connector_attach_encoder(struct intel_connector *connector,
17140                                     struct intel_encoder *encoder)
17141 {
17142         connector->encoder = encoder;
17143         drm_mode_connector_attach_encoder(&connector->base,
17144                                           &encoder->base);
17145 }
17146
17147 /*
17148  * set vga decode state - true == enable VGA decode
17149  */
17150 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
17151 {
17152         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17153         u16 gmch_ctrl;
17154
17155         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17156                 DRM_ERROR("failed to read control word\n");
17157                 return -EIO;
17158         }
17159
17160         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17161                 return 0;
17162
17163         if (state)
17164                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17165         else
17166                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17167
17168         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17169                 DRM_ERROR("failed to write control word\n");
17170                 return -EIO;
17171         }
17172
17173         return 0;
17174 }
17175
17176 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17177
17178 struct intel_display_error_state {
17179
17180         u32 power_well_driver;
17181
17182         int num_transcoders;
17183
17184         struct intel_cursor_error_state {
17185                 u32 control;
17186                 u32 position;
17187                 u32 base;
17188                 u32 size;
17189         } cursor[I915_MAX_PIPES];
17190
17191         struct intel_pipe_error_state {
17192                 bool power_domain_on;
17193                 u32 source;
17194                 u32 stat;
17195         } pipe[I915_MAX_PIPES];
17196
17197         struct intel_plane_error_state {
17198                 u32 control;
17199                 u32 stride;
17200                 u32 size;
17201                 u32 pos;
17202                 u32 addr;
17203                 u32 surface;
17204                 u32 tile_offset;
17205         } plane[I915_MAX_PIPES];
17206
17207         struct intel_transcoder_error_state {
17208                 bool power_domain_on;
17209                 enum transcoder cpu_transcoder;
17210
17211                 u32 conf;
17212
17213                 u32 htotal;
17214                 u32 hblank;
17215                 u32 hsync;
17216                 u32 vtotal;
17217                 u32 vblank;
17218                 u32 vsync;
17219         } transcoder[4];
17220 };
17221
17222 struct intel_display_error_state *
17223 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17224 {
17225         struct intel_display_error_state *error;
17226         int transcoders[] = {
17227                 TRANSCODER_A,
17228                 TRANSCODER_B,
17229                 TRANSCODER_C,
17230                 TRANSCODER_EDP,
17231         };
17232         int i;
17233
17234         if (INTEL_INFO(dev_priv)->num_pipes == 0)
17235                 return NULL;
17236
17237         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17238         if (error == NULL)
17239                 return NULL;
17240
17241         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17242                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17243
17244         for_each_pipe(dev_priv, i) {
17245                 error->pipe[i].power_domain_on =
17246                         __intel_display_power_is_enabled(dev_priv,
17247                                                          POWER_DOMAIN_PIPE(i));
17248                 if (!error->pipe[i].power_domain_on)
17249                         continue;
17250
17251                 error->cursor[i].control = I915_READ(CURCNTR(i));
17252                 error->cursor[i].position = I915_READ(CURPOS(i));
17253                 error->cursor[i].base = I915_READ(CURBASE(i));
17254
17255                 error->plane[i].control = I915_READ(DSPCNTR(i));
17256                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17257                 if (INTEL_GEN(dev_priv) <= 3) {
17258                         error->plane[i].size = I915_READ(DSPSIZE(i));
17259                         error->plane[i].pos = I915_READ(DSPPOS(i));
17260                 }
17261                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17262                         error->plane[i].addr = I915_READ(DSPADDR(i));
17263                 if (INTEL_GEN(dev_priv) >= 4) {
17264                         error->plane[i].surface = I915_READ(DSPSURF(i));
17265                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17266                 }
17267
17268                 error->pipe[i].source = I915_READ(PIPESRC(i));
17269
17270                 if (HAS_GMCH_DISPLAY(dev_priv))
17271                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17272         }
17273
17274         /* Note: this does not include DSI transcoders. */
17275         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17276         if (HAS_DDI(dev_priv))
17277                 error->num_transcoders++; /* Account for eDP. */
17278
17279         for (i = 0; i < error->num_transcoders; i++) {
17280                 enum transcoder cpu_transcoder = transcoders[i];
17281
17282                 error->transcoder[i].power_domain_on =
17283                         __intel_display_power_is_enabled(dev_priv,
17284                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17285                 if (!error->transcoder[i].power_domain_on)
17286                         continue;
17287
17288                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17289
17290                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17291                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17292                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17293                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17294                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17295                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17296                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17297         }
17298
17299         return error;
17300 }
17301
17302 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17303
17304 void
17305 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17306                                 struct drm_i915_private *dev_priv,
17307                                 struct intel_display_error_state *error)
17308 {
17309         int i;
17310
17311         if (!error)
17312                 return;
17313
17314         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
17315         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17316                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17317                            error->power_well_driver);
17318         for_each_pipe(dev_priv, i) {
17319                 err_printf(m, "Pipe [%d]:\n", i);
17320                 err_printf(m, "  Power: %s\n",
17321                            onoff(error->pipe[i].power_domain_on));
17322                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17323                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17324
17325                 err_printf(m, "Plane [%d]:\n", i);
17326                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17327                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17328                 if (INTEL_GEN(dev_priv) <= 3) {
17329                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17330                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17331                 }
17332                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17333                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17334                 if (INTEL_GEN(dev_priv) >= 4) {
17335                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17336                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17337                 }
17338
17339                 err_printf(m, "Cursor [%d]:\n", i);
17340                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17341                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17342                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17343         }
17344
17345         for (i = 0; i < error->num_transcoders; i++) {
17346                 err_printf(m, "CPU transcoder: %s\n",
17347                            transcoder_name(error->transcoder[i].cpu_transcoder));
17348                 err_printf(m, "  Power: %s\n",
17349                            onoff(error->transcoder[i].power_domain_on));
17350                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17351                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17352                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17353                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17354                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17355                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17356                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17357         }
17358 }
17359
17360 #endif