drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "intel_dsi.h"
  41 #include "i915_trace.h"
  42 #include <drm/drm_atomic.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_dp_helper.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_plane_helper.h>
  47 #include <drm/drm_rect.h>
  48 #include <linux/dma_remapping.h>
  49 #include <linux/reservation.h>
  50
  51 static bool is_mmio_work(struct intel_flip_work *work)
  52 {
  53         return work->mmio_work.func;
  54 }
  55
  56 /* Primary plane formats for gen <= 3 */
  57 static const uint32_t i8xx_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB1555,
  61         DRM_FORMAT_XRGB8888,
  62 };
  63
  64 /* Primary plane formats for gen >= 4 */
  65 static const uint32_t i965_primary_formats[] = {
  66         DRM_FORMAT_C8,
  67         DRM_FORMAT_RGB565,
  68         DRM_FORMAT_XRGB8888,
  69         DRM_FORMAT_XBGR8888,
  70         DRM_FORMAT_XRGB2101010,
  71         DRM_FORMAT_XBGR2101010,
  72 };
  73
  74 static const uint32_t skl_primary_formats[] = {
  75         DRM_FORMAT_C8,
  76         DRM_FORMAT_RGB565,
  77         DRM_FORMAT_XRGB8888,
  78         DRM_FORMAT_XBGR8888,
  79         DRM_FORMAT_ARGB8888,
  80         DRM_FORMAT_ABGR8888,
  81         DRM_FORMAT_XRGB2101010,
  82         DRM_FORMAT_XBGR2101010,
  83         DRM_FORMAT_YUYV,
  84         DRM_FORMAT_YVYU,
  85         DRM_FORMAT_UYVY,
  86         DRM_FORMAT_VYUY,
  87 };
  88
  89 /* Cursor formats */
  90 static const uint32_t intel_cursor_formats[] = {
  91         DRM_FORMAT_ARGB8888,
  92 };
  93
  94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  95                                 struct intel_crtc_state *pipe_config);
  96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  97                                    struct intel_crtc_state *pipe_config);
  98
  99 static int intel_framebuffer_init(struct drm_device *dev,
 100                                   struct intel_framebuffer *ifb,
 101                                   struct drm_mode_fb_cmd2 *mode_cmd,
 102                                   struct drm_i915_gem_object *obj);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void skl_init_scalers(struct drm_i915_private *dev_priv,
 119                              struct intel_crtc *crtc,
 120                              struct intel_crtc_state *crtc_state);
 121 static void skylake_pfit_enable(struct intel_crtc *crtc);
 122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 127 static int glk_calc_cdclk(int max_pixclk);
 128 static int bxt_calc_cdclk(int max_pixclk);
 129
 130 struct intel_limit {
 131         struct {
 132                 int min, max;
 133         } dot, vco, n, m, m1, m2, p, p1;
 134
 135         struct {
 136                 int dot_limit;
 137                 int p2_slow, p2_fast;
 138         } p2;
 139 };
 140
 141 /* returns HPLL frequency in kHz */
 142 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 143 {
 144         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 145
 146         /* Obtain SKU information */
 147         mutex_lock(&dev_priv->sb_lock);
 148         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 149                 CCK_FUSE_HPLL_FREQ_MASK;
 150         mutex_unlock(&dev_priv->sb_lock);
 151
 152         return vco_freq[hpll_freq] * 1000;
 153 }
 154
 155 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 156                       const char *name, u32 reg, int ref_freq)
 157 {
 158         u32 val;
 159         int divider;
 160
 161         mutex_lock(&dev_priv->sb_lock);
 162         val = vlv_cck_read(dev_priv, reg);
 163         mutex_unlock(&dev_priv->sb_lock);
 164
 165         divider = val & CCK_FREQUENCY_VALUES;
 166
 167         WARN((val & CCK_FREQUENCY_STATUS) !=
 168              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 169              "%s change in progress\n", name);
 170
 171         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 172 }
 173
 174 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 175                                   const char *name, u32 reg)
 176 {
 177         if (dev_priv->hpll_freq == 0)
 178                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 179
 180         return vlv_get_cck_clock(dev_priv, name, reg,
 181                                  dev_priv->hpll_freq);
 182 }
 183
 184 static int
 185 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 186 {
 187         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 188 }
 189
 190 static int
 191 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 192 {
 193         /* RAWCLK_FREQ_VLV register updated from power well code */
 194         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 195                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 196 }
 197
 198 static int
 199 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 200 {
 201         uint32_t clkcfg;
 202
 203         /* hrawclock is 1/4 the FSB frequency */
 204         clkcfg = I915_READ(CLKCFG);
 205         switch (clkcfg & CLKCFG_FSB_MASK) {
 206         case CLKCFG_FSB_400:
 207                 return 100000;
 208         case CLKCFG_FSB_533:
 209                 return 133333;
 210         case CLKCFG_FSB_667:
 211                 return 166667;
 212         case CLKCFG_FSB_800:
 213                 return 200000;
 214         case CLKCFG_FSB_1067:
 215                 return 266667;
 216         case CLKCFG_FSB_1333:
 217                 return 333333;
 218         /* these two are just a guess; one of them might be right */
 219         case CLKCFG_FSB_1600:
 220         case CLKCFG_FSB_1600_ALT:
 221                 return 400000;
 222         default:
 223                 return 133333;
 224         }
 225 }
 226
 227 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 228 {
 229         if (HAS_PCH_SPLIT(dev_priv))
 230                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 231         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 232                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 233         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 234                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 235         else
 236                 return; /* no rawclk on other platforms, or no need to know it */
 237
 238         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 239 }
 240
 241 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 242 {
 243         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 244                 return;
 245
 246         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 247                                                       CCK_CZ_CLOCK_CONTROL);
 248
 249         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 250 }
 251
 252 static inline u32 /* units of 100MHz */
 253 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 254                     const struct intel_crtc_state *pipe_config)
 255 {
 256         if (HAS_DDI(dev_priv))
 257                 return pipe_config->port_clock; /* SPLL */
 258         else if (IS_GEN5(dev_priv))
 259                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 260         else
 261                 return 270000;
 262 }
 263
 264 static const struct intel_limit intel_limits_i8xx_dac = {
 265         .dot = { .min = 25000, .max = 350000 },
 266         .vco = { .min = 908000, .max = 1512000 },
 267         .n = { .min = 2, .max = 16 },
 268         .m = { .min = 96, .max = 140 },
 269         .m1 = { .min = 18, .max = 26 },
 270         .m2 = { .min = 6, .max = 16 },
 271         .p = { .min = 4, .max = 128 },
 272         .p1 = { .min = 2, .max = 33 },
 273         .p2 = { .dot_limit = 165000,
 274                 .p2_slow = 4, .p2_fast = 2 },
 275 };
 276
 277 static const struct intel_limit intel_limits_i8xx_dvo = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 908000, .max = 1512000 },
 280         .n = { .min = 2, .max = 16 },
 281         .m = { .min = 96, .max = 140 },
 282         .m1 = { .min = 18, .max = 26 },
 283         .m2 = { .min = 6, .max = 16 },
 284         .p = { .min = 4, .max = 128 },
 285         .p1 = { .min = 2, .max = 33 },
 286         .p2 = { .dot_limit = 165000,
 287                 .p2_slow = 4, .p2_fast = 4 },
 288 };
 289
 290 static const struct intel_limit intel_limits_i8xx_lvds = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 908000, .max = 1512000 },
 293         .n = { .min = 2, .max = 16 },
 294         .m = { .min = 96, .max = 140 },
 295         .m1 = { .min = 18, .max = 26 },
 296         .m2 = { .min = 6, .max = 16 },
 297         .p = { .min = 4, .max = 128 },
 298         .p1 = { .min = 1, .max = 6 },
 299         .p2 = { .dot_limit = 165000,
 300                 .p2_slow = 14, .p2_fast = 7 },
 301 };
 302
 303 static const struct intel_limit intel_limits_i9xx_sdvo = {
 304         .dot = { .min = 20000, .max = 400000 },
 305         .vco = { .min = 1400000, .max = 2800000 },
 306         .n = { .min = 1, .max = 6 },
 307         .m = { .min = 70, .max = 120 },
 308         .m1 = { .min = 8, .max = 18 },
 309         .m2 = { .min = 3, .max = 7 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 200000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const struct intel_limit intel_limits_i9xx_lvds = {
 317         .dot = { .min = 20000, .max = 400000 },
 318         .vco = { .min = 1400000, .max = 2800000 },
 319         .n = { .min = 1, .max = 6 },
 320         .m = { .min = 70, .max = 120 },
 321         .m1 = { .min = 8, .max = 18 },
 322         .m2 = { .min = 3, .max = 7 },
 323         .p = { .min = 7, .max = 98 },
 324         .p1 = { .min = 1, .max = 8 },
 325         .p2 = { .dot_limit = 112000,
 326                 .p2_slow = 14, .p2_fast = 7 },
 327 };
 328
 329
 330 static const struct intel_limit intel_limits_g4x_sdvo = {
 331         .dot = { .min = 25000, .max = 270000 },
 332         .vco = { .min = 1750000, .max = 3500000},
 333         .n = { .min = 1, .max = 4 },
 334         .m = { .min = 104, .max = 138 },
 335         .m1 = { .min = 17, .max = 23 },
 336         .m2 = { .min = 5, .max = 11 },
 337         .p = { .min = 10, .max = 30 },
 338         .p1 = { .min = 1, .max = 3},
 339         .p2 = { .dot_limit = 270000,
 340                 .p2_slow = 10,
 341                 .p2_fast = 10
 342         },
 343 };
 344
 345 static const struct intel_limit intel_limits_g4x_hdmi = {
 346         .dot = { .min = 22000, .max = 400000 },
 347         .vco = { .min = 1750000, .max = 3500000},
 348         .n = { .min = 1, .max = 4 },
 349         .m = { .min = 104, .max = 138 },
 350         .m1 = { .min = 16, .max = 23 },
 351         .m2 = { .min = 5, .max = 11 },
 352         .p = { .min = 5, .max = 80 },
 353         .p1 = { .min = 1, .max = 8},
 354         .p2 = { .dot_limit = 165000,
 355                 .p2_slow = 10, .p2_fast = 5 },
 356 };
 357
 358 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 359         .dot = { .min = 20000, .max = 115000 },
 360         .vco = { .min = 1750000, .max = 3500000 },
 361         .n = { .min = 1, .max = 3 },
 362         .m = { .min = 104, .max = 138 },
 363         .m1 = { .min = 17, .max = 23 },
 364         .m2 = { .min = 5, .max = 11 },
 365         .p = { .min = 28, .max = 112 },
 366         .p1 = { .min = 2, .max = 8 },
 367         .p2 = { .dot_limit = 0,
 368                 .p2_slow = 14, .p2_fast = 14
 369         },
 370 };
 371
 372 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 373         .dot = { .min = 80000, .max = 224000 },
 374         .vco = { .min = 1750000, .max = 3500000 },
 375         .n = { .min = 1, .max = 3 },
 376         .m = { .min = 104, .max = 138 },
 377         .m1 = { .min = 17, .max = 23 },
 378         .m2 = { .min = 5, .max = 11 },
 379         .p = { .min = 14, .max = 42 },
 380         .p1 = { .min = 2, .max = 6 },
 381         .p2 = { .dot_limit = 0,
 382                 .p2_slow = 7, .p2_fast = 7
 383         },
 384 };
 385
 386 static const struct intel_limit intel_limits_pineview_sdvo = {
 387         .dot = { .min = 20000, .max = 400000},
 388         .vco = { .min = 1700000, .max = 3500000 },
 389         /* Pineview's Ncounter is a ring counter */
 390         .n = { .min = 3, .max = 6 },
 391         .m = { .min = 2, .max = 256 },
 392         /* Pineview only has one combined m divider, which we treat as m2. */
 393         .m1 = { .min = 0, .max = 0 },
 394         .m2 = { .min = 0, .max = 254 },
 395         .p = { .min = 5, .max = 80 },
 396         .p1 = { .min = 1, .max = 8 },
 397         .p2 = { .dot_limit = 200000,
 398                 .p2_slow = 10, .p2_fast = 5 },
 399 };
 400
 401 static const struct intel_limit intel_limits_pineview_lvds = {
 402         .dot = { .min = 20000, .max = 400000 },
 403         .vco = { .min = 1700000, .max = 3500000 },
 404         .n = { .min = 3, .max = 6 },
 405         .m = { .min = 2, .max = 256 },
 406         .m1 = { .min = 0, .max = 0 },
 407         .m2 = { .min = 0, .max = 254 },
 408         .p = { .min = 7, .max = 112 },
 409         .p1 = { .min = 1, .max = 8 },
 410         .p2 = { .dot_limit = 112000,
 411                 .p2_slow = 14, .p2_fast = 14 },
 412 };
 413
 414 /* Ironlake / Sandybridge
 415  *
 416  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 417  * the range value for them is (actual_value - 2).
 418  */
 419 static const struct intel_limit intel_limits_ironlake_dac = {
 420         .dot = { .min = 25000, .max = 350000 },
 421         .vco = { .min = 1760000, .max = 3510000 },
 422         .n = { .min = 1, .max = 5 },
 423         .m = { .min = 79, .max = 127 },
 424         .m1 = { .min = 12, .max = 22 },
 425         .m2 = { .min = 5, .max = 9 },
 426         .p = { .min = 5, .max = 80 },
 427         .p1 = { .min = 1, .max = 8 },
 428         .p2 = { .dot_limit = 225000,
 429                 .p2_slow = 10, .p2_fast = 5 },
 430 };
 431
 432 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 433         .dot = { .min = 25000, .max = 350000 },
 434         .vco = { .min = 1760000, .max = 3510000 },
 435         .n = { .min = 1, .max = 3 },
 436         .m = { .min = 79, .max = 118 },
 437         .m1 = { .min = 12, .max = 22 },
 438         .m2 = { .min = 5, .max = 9 },
 439         .p = { .min = 28, .max = 112 },
 440         .p1 = { .min = 2, .max = 8 },
 441         .p2 = { .dot_limit = 225000,
 442                 .p2_slow = 14, .p2_fast = 14 },
 443 };
 444
 445 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 446         .dot = { .min = 25000, .max = 350000 },
 447         .vco = { .min = 1760000, .max = 3510000 },
 448         .n = { .min = 1, .max = 3 },
 449         .m = { .min = 79, .max = 127 },
 450         .m1 = { .min = 12, .max = 22 },
 451         .m2 = { .min = 5, .max = 9 },
 452         .p = { .min = 14, .max = 56 },
 453         .p1 = { .min = 2, .max = 8 },
 454         .p2 = { .dot_limit = 225000,
 455                 .p2_slow = 7, .p2_fast = 7 },
 456 };
 457
 458 /* LVDS 100mhz refclk limits. */
 459 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 460         .dot = { .min = 25000, .max = 350000 },
 461         .vco = { .min = 1760000, .max = 3510000 },
 462         .n = { .min = 1, .max = 2 },
 463         .m = { .min = 79, .max = 126 },
 464         .m1 = { .min = 12, .max = 22 },
 465         .m2 = { .min = 5, .max = 9 },
 466         .p = { .min = 28, .max = 112 },
 467         .p1 = { .min = 2, .max = 8 },
 468         .p2 = { .dot_limit = 225000,
 469                 .p2_slow = 14, .p2_fast = 14 },
 470 };
 471
 472 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 473         .dot = { .min = 25000, .max = 350000 },
 474         .vco = { .min = 1760000, .max = 3510000 },
 475         .n = { .min = 1, .max = 3 },
 476         .m = { .min = 79, .max = 126 },
 477         .m1 = { .min = 12, .max = 22 },
 478         .m2 = { .min = 5, .max = 9 },
 479         .p = { .min = 14, .max = 42 },
 480         .p1 = { .min = 2, .max = 6 },
 481         .p2 = { .dot_limit = 225000,
 482                 .p2_slow = 7, .p2_fast = 7 },
 483 };
 484
 485 static const struct intel_limit intel_limits_vlv = {
 486          /*
 487           * These are the data rate limits (measured in fast clocks)
 488           * since those are the strictest limits we have. The fast
 489           * clock and actual rate limits are more relaxed, so checking
 490           * them would make no difference.
 491           */
 492         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 493         .vco = { .min = 4000000, .max = 6000000 },
 494         .n = { .min = 1, .max = 7 },
 495         .m1 = { .min = 2, .max = 3 },
 496         .m2 = { .min = 11, .max = 156 },
 497         .p1 = { .min = 2, .max = 3 },
 498         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 499 };
 500
 501 static const struct intel_limit intel_limits_chv = {
 502         /*
 503          * These are the data rate limits (measured in fast clocks)
 504          * since those are the strictest limits we have.  The fast
 505          * clock and actual rate limits are more relaxed, so checking
 506          * them would make no difference.
 507          */
 508         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 509         .vco = { .min = 4800000, .max = 6480000 },
 510         .n = { .min = 1, .max = 1 },
 511         .m1 = { .min = 2, .max = 2 },
 512         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 513         .p1 = { .min = 2, .max = 4 },
 514         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 515 };
 516
 517 static const struct intel_limit intel_limits_bxt = {
 518         /* FIXME: find real dot limits */
 519         .dot = { .min = 0, .max = INT_MAX },
 520         .vco = { .min = 4800000, .max = 6700000 },
 521         .n = { .min = 1, .max = 1 },
 522         .m1 = { .min = 2, .max = 2 },
 523         /* FIXME: find real m2 limits */
 524         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 525         .p1 = { .min = 2, .max = 4 },
 526         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 527 };
 528
 529 static bool
 530 needs_modeset(struct drm_crtc_state *state)
 531 {
 532         return drm_atomic_crtc_needs_modeset(state);
 533 }
 534
 535 /*
 536  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 537  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 538  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 539  * The helpers' return value is the rate of the clock that is fed to the
 540  * display engine's pipe which can be the above fast dot clock rate or a
 541  * divided-down version of it.
 542  */
 543 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 544 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 545 {
 546         clock->m = clock->m2 + 2;
 547         clock->p = clock->p1 * clock->p2;
 548         if (WARN_ON(clock->n == 0 || clock->p == 0))
 549                 return 0;
 550         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 551         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 552
 553         return clock->dot;
 554 }
 555
 556 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 557 {
 558         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 559 }
 560
 561 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 562 {
 563         clock->m = i9xx_dpll_compute_m(clock);
 564         clock->p = clock->p1 * clock->p2;
 565         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 566                 return 0;
 567         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 568         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 569
 570         return clock->dot;
 571 }
 572
 573 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 574 {
 575         clock->m = clock->m1 * clock->m2;
 576         clock->p = clock->p1 * clock->p2;
 577         if (WARN_ON(clock->n == 0 || clock->p == 0))
 578                 return 0;
 579         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 580         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 581
 582         return clock->dot / 5;
 583 }
 584
 585 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 586 {
 587         clock->m = clock->m1 * clock->m2;
 588         clock->p = clock->p1 * clock->p2;
 589         if (WARN_ON(clock->n == 0 || clock->p == 0))
 590                 return 0;
 591         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 592                         clock->n << 22);
 593         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 594
 595         return clock->dot / 5;
 596 }
 597
 598 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 599 /**
 600  * Returns whether the given set of divisors are valid for a given refclk with
 601  * the given connectors.
 602  */
 603
 604 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 605                                const struct intel_limit *limit,
 606                                const struct dpll *clock)
 607 {
 608         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 609                 INTELPllInvalid("n out of range\n");
 610         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 611                 INTELPllInvalid("p1 out of range\n");
 612         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 613                 INTELPllInvalid("m2 out of range\n");
 614         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 615                 INTELPllInvalid("m1 out of range\n");
 616
 617         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 618             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 619                 if (clock->m1 <= clock->m2)
 620                         INTELPllInvalid("m1 <= m2\n");
 621
 622         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 623             !IS_GEN9_LP(dev_priv)) {
 624                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 625                         INTELPllInvalid("p out of range\n");
 626                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 627                         INTELPllInvalid("m out of range\n");
 628         }
 629
 630         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 631                 INTELPllInvalid("vco out of range\n");
 632         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 633          * connector, etc., rather than just a single range.
 634          */
 635         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 636                 INTELPllInvalid("dot out of range\n");
 637
 638         return true;
 639 }
 640
 641 static int
 642 i9xx_select_p2_div(const struct intel_limit *limit,
 643                    const struct intel_crtc_state *crtc_state,
 644                    int target)
 645 {
 646         struct drm_device *dev = crtc_state->base.crtc->dev;
 647
 648         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 649                 /*
 650                  * For LVDS just rely on its current settings for dual-channel.
 651                  * We haven't figured out how to reliably set up different
 652                  * single/dual channel state, if we even can.
 653                  */
 654                 if (intel_is_dual_link_lvds(dev))
 655                         return limit->p2.p2_fast;
 656                 else
 657                         return limit->p2.p2_slow;
 658         } else {
 659                 if (target < limit->p2.dot_limit)
 660                         return limit->p2.p2_slow;
 661                 else
 662                         return limit->p2.p2_fast;
 663         }
 664 }
 665
 666 /*
 667  * Returns a set of divisors for the desired target clock with the given
 668  * refclk, or FALSE.  The returned values represent the clock equation:
 669  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 670  *
 671  * Target and reference clocks are specified in kHz.
 672  *
 673  * If match_clock is provided, then best_clock P divider must match the P
 674  * divider from @match_clock used for LVDS downclocking.
 675  */
 676 static bool
 677 i9xx_find_best_dpll(const struct intel_limit *limit,
 678                     struct intel_crtc_state *crtc_state,
 679                     int target, int refclk, struct dpll *match_clock,
 680                     struct dpll *best_clock)
 681 {
 682         struct drm_device *dev = crtc_state->base.crtc->dev;
 683         struct dpll clock;
 684         int err = target;
 685
 686         memset(best_clock, 0, sizeof(*best_clock));
 687
 688         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 689
 690         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 691              clock.m1++) {
 692                 for (clock.m2 = limit->m2.min;
 693                      clock.m2 <= limit->m2.max; clock.m2++) {
 694                         if (clock.m2 >= clock.m1)
 695                                 break;
 696                         for (clock.n = limit->n.min;
 697                              clock.n <= limit->n.max; clock.n++) {
 698                                 for (clock.p1 = limit->p1.min;
 699                                         clock.p1 <= limit->p1.max; clock.p1++) {
 700                                         int this_err;
 701
 702                                         i9xx_calc_dpll_params(refclk, &clock);
 703                                         if (!intel_PLL_is_valid(to_i915(dev),
 704                                                                 limit,
 705                                                                 &clock))
 706                                                 continue;
 707                                         if (match_clock &&
 708                                             clock.p != match_clock->p)
 709                                                 continue;
 710
 711                                         this_err = abs(clock.dot - target);
 712                                         if (this_err < err) {
 713                                                 *best_clock = clock;
 714                                                 err = this_err;
 715                                         }
 716                                 }
 717                         }
 718                 }
 719         }
 720
 721         return (err != target);
 722 }
 723
 724 /*
 725  * Returns a set of divisors for the desired target clock with the given
 726  * refclk, or FALSE.  The returned values represent the clock equation:
 727  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 728  *
 729  * Target and reference clocks are specified in kHz.
 730  *
 731  * If match_clock is provided, then best_clock P divider must match the P
 732  * divider from @match_clock used for LVDS downclocking.
 733  */
 734 static bool
 735 pnv_find_best_dpll(const struct intel_limit *limit,
 736                    struct intel_crtc_state *crtc_state,
 737                    int target, int refclk, struct dpll *match_clock,
 738                    struct dpll *best_clock)
 739 {
 740         struct drm_device *dev = crtc_state->base.crtc->dev;
 741         struct dpll clock;
 742         int err = target;
 743
 744         memset(best_clock, 0, sizeof(*best_clock));
 745
 746         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 747
 748         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 749              clock.m1++) {
 750                 for (clock.m2 = limit->m2.min;
 751                      clock.m2 <= limit->m2.max; clock.m2++) {
 752                         for (clock.n = limit->n.min;
 753                              clock.n <= limit->n.max; clock.n++) {
 754                                 for (clock.p1 = limit->p1.min;
 755                                         clock.p1 <= limit->p1.max; clock.p1++) {
 756                                         int this_err;
 757
 758                                         pnv_calc_dpll_params(refclk, &clock);
 759                                         if (!intel_PLL_is_valid(to_i915(dev),
 760                                                                 limit,
 761                                                                 &clock))
 762                                                 continue;
 763                                         if (match_clock &&
 764                                             clock.p != match_clock->p)
 765                                                 continue;
 766
 767                                         this_err = abs(clock.dot - target);
 768                                         if (this_err < err) {
 769                                                 *best_clock = clock;
 770                                                 err = this_err;
 771                                         }
 772                                 }
 773                         }
 774                 }
 775         }
 776
 777         return (err != target);
 778 }
 779
 780 /*
 781  * Returns a set of divisors for the desired target clock with the given
 782  * refclk, or FALSE.  The returned values represent the clock equation:
 783  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 784  *
 785  * Target and reference clocks are specified in kHz.
 786  *
 787  * If match_clock is provided, then best_clock P divider must match the P
 788  * divider from @match_clock used for LVDS downclocking.
 789  */
 790 static bool
 791 g4x_find_best_dpll(const struct intel_limit *limit,
 792                    struct intel_crtc_state *crtc_state,
 793                    int target, int refclk, struct dpll *match_clock,
 794                    struct dpll *best_clock)
 795 {
 796         struct drm_device *dev = crtc_state->base.crtc->dev;
 797         struct dpll clock;
 798         int max_n;
 799         bool found = false;
 800         /* approximately equals target * 0.00585 */
 801         int err_most = (target >> 8) + (target >> 9);
 802
 803         memset(best_clock, 0, sizeof(*best_clock));
 804
 805         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 806
 807         max_n = limit->n.max;
 808         /* based on hardware requirement, prefer smaller n to precision */
 809         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 810                 /* based on hardware requirement, prefere larger m1,m2 */
 811                 for (clock.m1 = limit->m1.max;
 812                      clock.m1 >= limit->m1.min; clock.m1--) {
 813                         for (clock.m2 = limit->m2.max;
 814                              clock.m2 >= limit->m2.min; clock.m2--) {
 815                                 for (clock.p1 = limit->p1.max;
 816                                      clock.p1 >= limit->p1.min; clock.p1--) {
 817                                         int this_err;
 818
 819                                         i9xx_calc_dpll_params(refclk, &clock);
 820                                         if (!intel_PLL_is_valid(to_i915(dev),
 821                                                                 limit,
 822                                                                 &clock))
 823                                                 continue;
 824
 825                                         this_err = abs(clock.dot - target);
 826                                         if (this_err < err_most) {
 827                                                 *best_clock = clock;
 828                                                 err_most = this_err;
 829                                                 max_n = clock.n;
 830                                                 found = true;
 831                                         }
 832                                 }
 833                         }
 834                 }
 835         }
 836         return found;
 837 }
 838
 839 /*
 840  * Check if the calculated PLL configuration is more optimal compared to the
 841  * best configuration and error found so far. Return the calculated error.
 842  */
 843 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 844                                const struct dpll *calculated_clock,
 845                                const struct dpll *best_clock,
 846                                unsigned int best_error_ppm,
 847                                unsigned int *error_ppm)
 848 {
 849         /*
 850          * For CHV ignore the error and consider only the P value.
 851          * Prefer a bigger P value based on HW requirements.
 852          */
 853         if (IS_CHERRYVIEW(to_i915(dev))) {
 854                 *error_ppm = 0;
 855
 856                 return calculated_clock->p > best_clock->p;
 857         }
 858
 859         if (WARN_ON_ONCE(!target_freq))
 860                 return false;
 861
 862         *error_ppm = div_u64(1000000ULL *
 863                                 abs(target_freq - calculated_clock->dot),
 864                              target_freq);
 865         /*
 866          * Prefer a better P value over a better (smaller) error if the error
 867          * is small. Ensure this preference for future configurations too by
 868          * setting the error to 0.
 869          */
 870         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 871                 *error_ppm = 0;
 872
 873                 return true;
 874         }
 875
 876         return *error_ppm + 10 < best_error_ppm;
 877 }
 878
 879 /*
 880  * Returns a set of divisors for the desired target clock with the given
 881  * refclk, or FALSE.  The returned values represent the clock equation:
 882  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 883  */
 884 static bool
 885 vlv_find_best_dpll(const struct intel_limit *limit,
 886                    struct intel_crtc_state *crtc_state,
 887                    int target, int refclk, struct dpll *match_clock,
 888                    struct dpll *best_clock)
 889 {
 890         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 891         struct drm_device *dev = crtc->base.dev;
 892         struct dpll clock;
 893         unsigned int bestppm = 1000000;
 894         /* min update 19.2 MHz */
 895         int max_n = min(limit->n.max, refclk / 19200);
 896         bool found = false;
 897
 898         target *= 5; /* fast clock */
 899
 900         memset(best_clock, 0, sizeof(*best_clock));
 901
 902         /* based on hardware requirement, prefer smaller n to precision */
 903         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 904                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 905                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 906                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 907                                 clock.p = clock.p1 * clock.p2;
 908                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 909                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 910                                         unsigned int ppm;
 911
 912                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 913                                                                      refclk * clock.m1);
 914
 915                                         vlv_calc_dpll_params(refclk, &clock);
 916
 917                                         if (!intel_PLL_is_valid(to_i915(dev),
 918                                                                 limit,
 919                                                                 &clock))
 920                                                 continue;
 921
 922                                         if (!vlv_PLL_is_optimal(dev, target,
 923                                                                 &clock,
 924                                                                 best_clock,
 925                                                                 bestppm, &ppm))
 926                                                 continue;
 927
 928                                         *best_clock = clock;
 929                                         bestppm = ppm;
 930                                         found = true;
 931                                 }
 932                         }
 933                 }
 934         }
 935
 936         return found;
 937 }
 938
 939 /*
 940  * Returns a set of divisors for the desired target clock with the given
 941  * refclk, or FALSE.  The returned values represent the clock equation:
 942  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 943  */
 944 static bool
 945 chv_find_best_dpll(const struct intel_limit *limit,
 946                    struct intel_crtc_state *crtc_state,
 947                    int target, int refclk, struct dpll *match_clock,
 948                    struct dpll *best_clock)
 949 {
 950         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 951         struct drm_device *dev = crtc->base.dev;
 952         unsigned int best_error_ppm;
 953         struct dpll clock;
 954         uint64_t m2;
 955         int found = false;
 956
 957         memset(best_clock, 0, sizeof(*best_clock));
 958         best_error_ppm = 1000000;
 959
 960         /*
 961          * Based on hardware doc, the n always set to 1, and m1 always
 962          * set to 2.  If requires to support 200Mhz refclk, we need to
 963          * revisit this because n may not 1 anymore.
 964          */
 965         clock.n = 1, clock.m1 = 2;
 966         target *= 5;    /* fast clock */
 967
 968         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 969                 for (clock.p2 = limit->p2.p2_fast;
 970                                 clock.p2 >= limit->p2.p2_slow;
 971                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 972                         unsigned int error_ppm;
 973
 974                         clock.p = clock.p1 * clock.p2;
 975
 976                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 977                                         clock.n) << 22, refclk * clock.m1);
 978
 979                         if (m2 > INT_MAX/clock.m1)
 980                                 continue;
 981
 982                         clock.m2 = m2;
 983
 984                         chv_calc_dpll_params(refclk, &clock);
 985
 986                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 987                                 continue;
 988
 989                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 990                                                 best_error_ppm, &error_ppm))
 991                                 continue;
 992
 993                         *best_clock = clock;
 994                         best_error_ppm = error_ppm;
 995                         found = true;
 996                 }
 997         }
 998
 999         return found;
1000 }
1001
1002 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1003                         struct dpll *best_clock)
1004 {
1005         int refclk = 100000;
1006         const struct intel_limit *limit = &intel_limits_bxt;
1007
1008         return chv_find_best_dpll(limit, crtc_state,
1009                                   target_clock, refclk, NULL, best_clock);
1010 }
1011
1012 bool intel_crtc_active(struct intel_crtc *crtc)
1013 {
1014         /* Be paranoid as we can arrive here with only partial
1015          * state retrieved from the hardware during setup.
1016          *
1017          * We can ditch the adjusted_mode.crtc_clock check as soon
1018          * as Haswell has gained clock readout/fastboot support.
1019          *
1020          * We can ditch the crtc->primary->fb check as soon as we can
1021          * properly reconstruct framebuffers.
1022          *
1023          * FIXME: The intel_crtc->active here should be switched to
1024          * crtc->state->active once we have proper CRTC states wired up
1025          * for atomic.
1026          */
1027         return crtc->active && crtc->base.primary->state->fb &&
1028                 crtc->config->base.adjusted_mode.crtc_clock;
1029 }
1030
1031 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1032                                              enum pipe pipe)
1033 {
1034         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1035
1036         return crtc->config->cpu_transcoder;
1037 }
1038
1039 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1040 {
1041         i915_reg_t reg = PIPEDSL(pipe);
1042         u32 line1, line2;
1043         u32 line_mask;
1044
1045         if (IS_GEN2(dev_priv))
1046                 line_mask = DSL_LINEMASK_GEN2;
1047         else
1048                 line_mask = DSL_LINEMASK_GEN3;
1049
1050         line1 = I915_READ(reg) & line_mask;
1051         msleep(5);
1052         line2 = I915_READ(reg) & line_mask;
1053
1054         return line1 == line2;
1055 }
1056
1057 /*
1058  * intel_wait_for_pipe_off - wait for pipe to turn off
1059  * @crtc: crtc whose pipe to wait for
1060  *
1061  * After disabling a pipe, we can't wait for vblank in the usual way,
1062  * spinning on the vblank interrupt status bit, since we won't actually
1063  * see an interrupt when the pipe is disabled.
1064  *
1065  * On Gen4 and above:
1066  *   wait for the pipe register state bit to turn off
1067  *
1068  * Otherwise:
1069  *   wait for the display line value to settle (it usually
1070  *   ends up stopping at the start of the next frame).
1071  *
1072  */
1073 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1074 {
1075         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1076         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1077         enum pipe pipe = crtc->pipe;
1078
1079         if (INTEL_GEN(dev_priv) >= 4) {
1080                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1081
1082                 /* Wait for the Pipe State to go off */
1083                 if (intel_wait_for_register(dev_priv,
1084                                             reg, I965_PIPECONF_ACTIVE, 0,
1085                                             100))
1086                         WARN(1, "pipe_off wait timed out\n");
1087         } else {
1088                 /* Wait for the display line to settle */
1089                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1090                         WARN(1, "pipe_off wait timed out\n");
1091         }
1092 }
1093
1094 /* Only for pre-ILK configs */
1095 void assert_pll(struct drm_i915_private *dev_priv,
1096                 enum pipe pipe, bool state)
1097 {
1098         u32 val;
1099         bool cur_state;
1100
1101         val = I915_READ(DPLL(pipe));
1102         cur_state = !!(val & DPLL_VCO_ENABLE);
1103         I915_STATE_WARN(cur_state != state,
1104              "PLL state assertion failure (expected %s, current %s)\n",
1105                         onoff(state), onoff(cur_state));
1106 }
1107
1108 /* XXX: the dsi pll is shared between MIPI DSI ports */
1109 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1110 {
1111         u32 val;
1112         bool cur_state;
1113
1114         mutex_lock(&dev_priv->sb_lock);
1115         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1116         mutex_unlock(&dev_priv->sb_lock);
1117
1118         cur_state = val & DSI_PLL_VCO_EN;
1119         I915_STATE_WARN(cur_state != state,
1120              "DSI PLL state assertion failure (expected %s, current %s)\n",
1121                         onoff(state), onoff(cur_state));
1122 }
1123
1124 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1125                           enum pipe pipe, bool state)
1126 {
1127         bool cur_state;
1128         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1129                                                                       pipe);
1130
1131         if (HAS_DDI(dev_priv)) {
1132                 /* DDI does not have a specific FDI_TX register */
1133                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1134                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135         } else {
1136                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1137                 cur_state = !!(val & FDI_TX_ENABLE);
1138         }
1139         I915_STATE_WARN(cur_state != state,
1140              "FDI TX state assertion failure (expected %s, current %s)\n",
1141                         onoff(state), onoff(cur_state));
1142 }
1143 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1144 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1145
1146 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1147                           enum pipe pipe, bool state)
1148 {
1149         u32 val;
1150         bool cur_state;
1151
1152         val = I915_READ(FDI_RX_CTL(pipe));
1153         cur_state = !!(val & FDI_RX_ENABLE);
1154         I915_STATE_WARN(cur_state != state,
1155              "FDI RX state assertion failure (expected %s, current %s)\n",
1156                         onoff(state), onoff(cur_state));
1157 }
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1162                                       enum pipe pipe)
1163 {
1164         u32 val;
1165
1166         /* ILK FDI PLL is always enabled */
1167         if (IS_GEN5(dev_priv))
1168                 return;
1169
1170         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1171         if (HAS_DDI(dev_priv))
1172                 return;
1173
1174         val = I915_READ(FDI_TX_CTL(pipe));
1175         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1176 }
1177
1178 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1179                        enum pipe pipe, bool state)
1180 {
1181         u32 val;
1182         bool cur_state;
1183
1184         val = I915_READ(FDI_RX_CTL(pipe));
1185         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1186         I915_STATE_WARN(cur_state != state,
1187              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1188                         onoff(state), onoff(cur_state));
1189 }
1190
1191 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1192 {
1193         i915_reg_t pp_reg;
1194         u32 val;
1195         enum pipe panel_pipe = PIPE_A;
1196         bool locked = true;
1197
1198         if (WARN_ON(HAS_DDI(dev_priv)))
1199                 return;
1200
1201         if (HAS_PCH_SPLIT(dev_priv)) {
1202                 u32 port_sel;
1203
1204                 pp_reg = PP_CONTROL(0);
1205                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1206
1207                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1208                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1209                         panel_pipe = PIPE_B;
1210                 /* XXX: else fix for eDP */
1211         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1212                 /* presumably write lock depends on pipe, not port select */
1213                 pp_reg = PP_CONTROL(pipe);
1214                 panel_pipe = pipe;
1215         } else {
1216                 pp_reg = PP_CONTROL(0);
1217                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1218                         panel_pipe = PIPE_B;
1219         }
1220
1221         val = I915_READ(pp_reg);
1222         if (!(val & PANEL_POWER_ON) ||
1223             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1224                 locked = false;
1225
1226         I915_STATE_WARN(panel_pipe == pipe && locked,
1227              "panel assertion failure, pipe %c regs locked\n",
1228              pipe_name(pipe));
1229 }
1230
1231 static void assert_cursor(struct drm_i915_private *dev_priv,
1232                           enum pipe pipe, bool state)
1233 {
1234         bool cur_state;
1235
1236         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1237                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1238         else
1239                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1240
1241         I915_STATE_WARN(cur_state != state,
1242              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1243                         pipe_name(pipe), onoff(state), onoff(cur_state));
1244 }
1245 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1246 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1247
1248 void assert_pipe(struct drm_i915_private *dev_priv,
1249                  enum pipe pipe, bool state)
1250 {
1251         bool cur_state;
1252         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1253                                                                       pipe);
1254         enum intel_display_power_domain power_domain;
1255
1256         /* if we need the pipe quirk it must be always on */
1257         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1258             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1259                 state = true;
1260
1261         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1262         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1263                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1264                 cur_state = !!(val & PIPECONF_ENABLE);
1265
1266                 intel_display_power_put(dev_priv, power_domain);
1267         } else {
1268                 cur_state = false;
1269         }
1270
1271         I915_STATE_WARN(cur_state != state,
1272              "pipe %c assertion failure (expected %s, current %s)\n",
1273                         pipe_name(pipe), onoff(state), onoff(cur_state));
1274 }
1275
1276 static void assert_plane(struct drm_i915_private *dev_priv,
1277                          enum plane plane, bool state)
1278 {
1279         u32 val;
1280         bool cur_state;
1281
1282         val = I915_READ(DSPCNTR(plane));
1283         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1284         I915_STATE_WARN(cur_state != state,
1285              "plane %c assertion failure (expected %s, current %s)\n",
1286                         plane_name(plane), onoff(state), onoff(cur_state));
1287 }
1288
1289 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1290 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1291
1292 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1293                                    enum pipe pipe)
1294 {
1295         int i;
1296
1297         /* Primary planes are fixed to pipes on gen4+ */
1298         if (INTEL_GEN(dev_priv) >= 4) {
1299                 u32 val = I915_READ(DSPCNTR(pipe));
1300                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1301                      "plane %c assertion failure, should be disabled but not\n",
1302                      plane_name(pipe));
1303                 return;
1304         }
1305
1306         /* Need to check both planes against the pipe */
1307         for_each_pipe(dev_priv, i) {
1308                 u32 val = I915_READ(DSPCNTR(i));
1309                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1310                         DISPPLANE_SEL_PIPE_SHIFT;
1311                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1312                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1313                      plane_name(i), pipe_name(pipe));
1314         }
1315 }
1316
1317 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1318                                     enum pipe pipe)
1319 {
1320         int sprite;
1321
1322         if (INTEL_GEN(dev_priv) >= 9) {
1323                 for_each_sprite(dev_priv, pipe, sprite) {
1324                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1325                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1326                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1327                              sprite, pipe_name(pipe));
1328                 }
1329         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1330                 for_each_sprite(dev_priv, pipe, sprite) {
1331                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1332                         I915_STATE_WARN(val & SP_ENABLE,
1333                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1334                              sprite_name(pipe, sprite), pipe_name(pipe));
1335                 }
1336         } else if (INTEL_GEN(dev_priv) >= 7) {
1337                 u32 val = I915_READ(SPRCTL(pipe));
1338                 I915_STATE_WARN(val & SPRITE_ENABLE,
1339                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1340                      plane_name(pipe), pipe_name(pipe));
1341         } else if (INTEL_GEN(dev_priv) >= 5) {
1342                 u32 val = I915_READ(DVSCNTR(pipe));
1343                 I915_STATE_WARN(val & DVS_ENABLE,
1344                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1345                      plane_name(pipe), pipe_name(pipe));
1346         }
1347 }
1348
1349 static void assert_vblank_disabled(struct drm_crtc *crtc)
1350 {
1351         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1352                 drm_crtc_vblank_put(crtc);
1353 }
1354
1355 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1356                                     enum pipe pipe)
1357 {
1358         u32 val;
1359         bool enabled;
1360
1361         val = I915_READ(PCH_TRANSCONF(pipe));
1362         enabled = !!(val & TRANS_ENABLE);
1363         I915_STATE_WARN(enabled,
1364              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1365              pipe_name(pipe));
1366 }
1367
1368 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1369                             enum pipe pipe, u32 port_sel, u32 val)
1370 {
1371         if ((val & DP_PORT_EN) == 0)
1372                 return false;
1373
1374         if (HAS_PCH_CPT(dev_priv)) {
1375                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1376                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1377                         return false;
1378         } else if (IS_CHERRYVIEW(dev_priv)) {
1379                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1380                         return false;
1381         } else {
1382                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1383                         return false;
1384         }
1385         return true;
1386 }
1387
1388 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1389                               enum pipe pipe, u32 val)
1390 {
1391         if ((val & SDVO_ENABLE) == 0)
1392                 return false;
1393
1394         if (HAS_PCH_CPT(dev_priv)) {
1395                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1396                         return false;
1397         } else if (IS_CHERRYVIEW(dev_priv)) {
1398                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1399                         return false;
1400         } else {
1401                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1402                         return false;
1403         }
1404         return true;
1405 }
1406
1407 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1408                               enum pipe pipe, u32 val)
1409 {
1410         if ((val & LVDS_PORT_EN) == 0)
1411                 return false;
1412
1413         if (HAS_PCH_CPT(dev_priv)) {
1414                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1415                         return false;
1416         } else {
1417                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1418                         return false;
1419         }
1420         return true;
1421 }
1422
1423 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1424                               enum pipe pipe, u32 val)
1425 {
1426         if ((val & ADPA_DAC_ENABLE) == 0)
1427                 return false;
1428         if (HAS_PCH_CPT(dev_priv)) {
1429                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1430                         return false;
1431         } else {
1432                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1433                         return false;
1434         }
1435         return true;
1436 }
1437
1438 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1439                                    enum pipe pipe, i915_reg_t reg,
1440                                    u32 port_sel)
1441 {
1442         u32 val = I915_READ(reg);
1443         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1444              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1445              i915_mmio_reg_offset(reg), pipe_name(pipe));
1446
1447         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1448              && (val & DP_PIPEB_SELECT),
1449              "IBX PCH dp port still using transcoder B\n");
1450 }
1451
1452 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1453                                      enum pipe pipe, i915_reg_t reg)
1454 {
1455         u32 val = I915_READ(reg);
1456         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1457              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1458              i915_mmio_reg_offset(reg), pipe_name(pipe));
1459
1460         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1461              && (val & SDVO_PIPE_B_SELECT),
1462              "IBX PCH hdmi port still using transcoder B\n");
1463 }
1464
1465 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1466                                       enum pipe pipe)
1467 {
1468         u32 val;
1469
1470         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1471         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1472         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1473
1474         val = I915_READ(PCH_ADPA);
1475         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476              "PCH VGA enabled on transcoder %c, should be disabled\n",
1477              pipe_name(pipe));
1478
1479         val = I915_READ(PCH_LVDS);
1480         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1481              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1482              pipe_name(pipe));
1483
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1485         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1486         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1487 }
1488
1489 static void _vlv_enable_pll(struct intel_crtc *crtc,
1490                             const struct intel_crtc_state *pipe_config)
1491 {
1492         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1493         enum pipe pipe = crtc->pipe;
1494
1495         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1496         POSTING_READ(DPLL(pipe));
1497         udelay(150);
1498
1499         if (intel_wait_for_register(dev_priv,
1500                                     DPLL(pipe),
1501                                     DPLL_LOCK_VLV,
1502                                     DPLL_LOCK_VLV,
1503                                     1))
1504                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508                            const struct intel_crtc_state *pipe_config)
1509 {
1510         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1511         enum pipe pipe = crtc->pipe;
1512
1513         assert_pipe_disabled(dev_priv, pipe);
1514
1515         /* PLL is protected by panel, make sure we can write it */
1516         assert_panel_unlocked(dev_priv, pipe);
1517
1518         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1519                 _vlv_enable_pll(crtc, pipe_config);
1520
1521         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1522         POSTING_READ(DPLL_MD(pipe));
1523 }
1524
1525
1526 static void _chv_enable_pll(struct intel_crtc *crtc,
1527                             const struct intel_crtc_state *pipe_config)
1528 {
1529         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1530         enum pipe pipe = crtc->pipe;
1531         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1532         u32 tmp;
1533
1534         mutex_lock(&dev_priv->sb_lock);
1535
1536         /* Enable back the 10bit clock to display controller */
1537         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1538         tmp |= DPIO_DCLKP_EN;
1539         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1540
1541         mutex_unlock(&dev_priv->sb_lock);
1542
1543         /*
1544          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1545          */
1546         udelay(1);
1547
1548         /* Enable PLL */
1549         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1550
1551         /* Check PLL is locked */
1552         if (intel_wait_for_register(dev_priv,
1553                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1554                                     1))
1555                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1556 }
1557
1558 static void chv_enable_pll(struct intel_crtc *crtc,
1559                            const struct intel_crtc_state *pipe_config)
1560 {
1561         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1562         enum pipe pipe = crtc->pipe;
1563
1564         assert_pipe_disabled(dev_priv, pipe);
1565
1566         /* PLL is protected by panel, make sure we can write it */
1567         assert_panel_unlocked(dev_priv, pipe);
1568
1569         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1570                 _chv_enable_pll(crtc, pipe_config);
1571
1572         if (pipe != PIPE_A) {
1573                 /*
1574                  * WaPixelRepeatModeFixForC0:chv
1575                  *
1576                  * DPLLCMD is AWOL. Use chicken bits to propagate
1577                  * the value from DPLLBMD to either pipe B or C.
1578                  */
1579                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1580                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1581                 I915_WRITE(CBR4_VLV, 0);
1582                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1583
1584                 /*
1585                  * DPLLB VGA mode also seems to cause problems.
1586                  * We should always have it disabled.
1587                  */
1588                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1589         } else {
1590                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1591                 POSTING_READ(DPLL_MD(pipe));
1592         }
1593 }
1594
1595 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1596 {
1597         struct intel_crtc *crtc;
1598         int count = 0;
1599
1600         for_each_intel_crtc(&dev_priv->drm, crtc) {
1601                 count += crtc->base.state->active &&
1602                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1603         }
1604
1605         return count;
1606 }
1607
1608 static void i9xx_enable_pll(struct intel_crtc *crtc)
1609 {
1610         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1611         i915_reg_t reg = DPLL(crtc->pipe);
1612         u32 dpll = crtc->config->dpll_hw_state.dpll;
1613
1614         assert_pipe_disabled(dev_priv, crtc->pipe);
1615
1616         /* PLL is protected by panel, make sure we can write it */
1617         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1618                 assert_panel_unlocked(dev_priv, crtc->pipe);
1619
1620         /* Enable DVO 2x clock on both PLLs if necessary */
1621         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1622                 /*
1623                  * It appears to be important that we don't enable this
1624                  * for the current pipe before otherwise configuring the
1625                  * PLL. No idea how this should be handled if multiple
1626                  * DVO outputs are enabled simultaneosly.
1627                  */
1628                 dpll |= DPLL_DVO_2X_MODE;
1629                 I915_WRITE(DPLL(!crtc->pipe),
1630                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1631         }
1632
1633         /*
1634          * Apparently we need to have VGA mode enabled prior to changing
1635          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1636          * dividers, even though the register value does change.
1637          */
1638         I915_WRITE(reg, 0);
1639
1640         I915_WRITE(reg, dpll);
1641
1642         /* Wait for the clocks to stabilize. */
1643         POSTING_READ(reg);
1644         udelay(150);
1645
1646         if (INTEL_GEN(dev_priv) >= 4) {
1647                 I915_WRITE(DPLL_MD(crtc->pipe),
1648                            crtc->config->dpll_hw_state.dpll_md);
1649         } else {
1650                 /* The pixel multiplier can only be updated once the
1651                  * DPLL is enabled and the clocks are stable.
1652                  *
1653                  * So write it again.
1654                  */
1655                 I915_WRITE(reg, dpll);
1656         }
1657
1658         /* We do this three times for luck */
1659         I915_WRITE(reg, dpll);
1660         POSTING_READ(reg);
1661         udelay(150); /* wait for warmup */
1662         I915_WRITE(reg, dpll);
1663         POSTING_READ(reg);
1664         udelay(150); /* wait for warmup */
1665         I915_WRITE(reg, dpll);
1666         POSTING_READ(reg);
1667         udelay(150); /* wait for warmup */
1668 }
1669
1670 /**
1671  * i9xx_disable_pll - disable a PLL
1672  * @dev_priv: i915 private structure
1673  * @pipe: pipe PLL to disable
1674  *
1675  * Disable the PLL for @pipe, making sure the pipe is off first.
1676  *
1677  * Note!  This is for pre-ILK only.
1678  */
1679 static void i9xx_disable_pll(struct intel_crtc *crtc)
1680 {
1681         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1682         enum pipe pipe = crtc->pipe;
1683
1684         /* Disable DVO 2x clock on both PLLs if necessary */
1685         if (IS_I830(dev_priv) &&
1686             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1687             !intel_num_dvo_pipes(dev_priv)) {
1688                 I915_WRITE(DPLL(PIPE_B),
1689                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1690                 I915_WRITE(DPLL(PIPE_A),
1691                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1692         }
1693
1694         /* Don't disable pipe or pipe PLLs if needed */
1695         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1696             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1697                 return;
1698
1699         /* Make sure the pipe isn't still relying on us */
1700         assert_pipe_disabled(dev_priv, pipe);
1701
1702         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1703         POSTING_READ(DPLL(pipe));
1704 }
1705
1706 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1707 {
1708         u32 val;
1709
1710         /* Make sure the pipe isn't still relying on us */
1711         assert_pipe_disabled(dev_priv, pipe);
1712
1713         val = DPLL_INTEGRATED_REF_CLK_VLV |
1714                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1715         if (pipe != PIPE_A)
1716                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1717
1718         I915_WRITE(DPLL(pipe), val);
1719         POSTING_READ(DPLL(pipe));
1720 }
1721
1722 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1723 {
1724         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1725         u32 val;
1726
1727         /* Make sure the pipe isn't still relying on us */
1728         assert_pipe_disabled(dev_priv, pipe);
1729
1730         val = DPLL_SSC_REF_CLK_CHV |
1731                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1732         if (pipe != PIPE_A)
1733                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1734
1735         I915_WRITE(DPLL(pipe), val);
1736         POSTING_READ(DPLL(pipe));
1737
1738         mutex_lock(&dev_priv->sb_lock);
1739
1740         /* Disable 10bit clock to display controller */
1741         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1742         val &= ~DPIO_DCLKP_EN;
1743         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1744
1745         mutex_unlock(&dev_priv->sb_lock);
1746 }
1747
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749                          struct intel_digital_port *dport,
1750                          unsigned int expected_mask)
1751 {
1752         u32 port_mask;
1753         i915_reg_t dpll_reg;
1754
1755         switch (dport->port) {
1756         case PORT_B:
1757                 port_mask = DPLL_PORTB_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_C:
1761                 port_mask = DPLL_PORTC_READY_MASK;
1762                 dpll_reg = DPLL(0);
1763                 expected_mask <<= 4;
1764                 break;
1765         case PORT_D:
1766                 port_mask = DPLL_PORTD_READY_MASK;
1767                 dpll_reg = DPIO_PHY_STATUS;
1768                 break;
1769         default:
1770                 BUG();
1771         }
1772
1773         if (intel_wait_for_register(dev_priv,
1774                                     dpll_reg, port_mask, expected_mask,
1775                                     1000))
1776                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1777                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1778 }
1779
1780 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1781                                            enum pipe pipe)
1782 {
1783         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1784                                                                 pipe);
1785         i915_reg_t reg;
1786         uint32_t val, pipeconf_val;
1787
1788         /* Make sure PCH DPLL is enabled */
1789         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1790
1791         /* FDI must be feeding us bits for PCH ports */
1792         assert_fdi_tx_enabled(dev_priv, pipe);
1793         assert_fdi_rx_enabled(dev_priv, pipe);
1794
1795         if (HAS_PCH_CPT(dev_priv)) {
1796                 /* Workaround: Set the timing override bit before enabling the
1797                  * pch transcoder. */
1798                 reg = TRANS_CHICKEN2(pipe);
1799                 val = I915_READ(reg);
1800                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1801                 I915_WRITE(reg, val);
1802         }
1803
1804         reg = PCH_TRANSCONF(pipe);
1805         val = I915_READ(reg);
1806         pipeconf_val = I915_READ(PIPECONF(pipe));
1807
1808         if (HAS_PCH_IBX(dev_priv)) {
1809                 /*
1810                  * Make the BPC in transcoder be consistent with
1811                  * that in pipeconf reg. For HDMI we must use 8bpc
1812                  * here for both 8bpc and 12bpc.
1813                  */
1814                 val &= ~PIPECONF_BPC_MASK;
1815                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1816                         val |= PIPECONF_8BPC;
1817                 else
1818                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1819         }
1820
1821         val &= ~TRANS_INTERLACE_MASK;
1822         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1823                 if (HAS_PCH_IBX(dev_priv) &&
1824                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1825                         val |= TRANS_LEGACY_INTERLACED_ILK;
1826                 else
1827                         val |= TRANS_INTERLACED;
1828         else
1829                 val |= TRANS_PROGRESSIVE;
1830
1831         I915_WRITE(reg, val | TRANS_ENABLE);
1832         if (intel_wait_for_register(dev_priv,
1833                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1834                                     100))
1835                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1836 }
1837
1838 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1839                                       enum transcoder cpu_transcoder)
1840 {
1841         u32 val, pipeconf_val;
1842
1843         /* FDI must be feeding us bits for PCH ports */
1844         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1845         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1846
1847         /* Workaround: set timing override bit. */
1848         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1849         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1850         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1851
1852         val = TRANS_ENABLE;
1853         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1854
1855         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1856             PIPECONF_INTERLACED_ILK)
1857                 val |= TRANS_INTERLACED;
1858         else
1859                 val |= TRANS_PROGRESSIVE;
1860
1861         I915_WRITE(LPT_TRANSCONF, val);
1862         if (intel_wait_for_register(dev_priv,
1863                                     LPT_TRANSCONF,
1864                                     TRANS_STATE_ENABLE,
1865                                     TRANS_STATE_ENABLE,
1866                                     100))
1867                 DRM_ERROR("Failed to enable PCH transcoder\n");
1868 }
1869
1870 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1871                                             enum pipe pipe)
1872 {
1873         i915_reg_t reg;
1874         uint32_t val;
1875
1876         /* FDI relies on the transcoder */
1877         assert_fdi_tx_disabled(dev_priv, pipe);
1878         assert_fdi_rx_disabled(dev_priv, pipe);
1879
1880         /* Ports must be off as well */
1881         assert_pch_ports_disabled(dev_priv, pipe);
1882
1883         reg = PCH_TRANSCONF(pipe);
1884         val = I915_READ(reg);
1885         val &= ~TRANS_ENABLE;
1886         I915_WRITE(reg, val);
1887         /* wait for PCH transcoder off, transcoder state */
1888         if (intel_wait_for_register(dev_priv,
1889                                     reg, TRANS_STATE_ENABLE, 0,
1890                                     50))
1891                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1892
1893         if (HAS_PCH_CPT(dev_priv)) {
1894                 /* Workaround: Clear the timing override chicken bit again. */
1895                 reg = TRANS_CHICKEN2(pipe);
1896                 val = I915_READ(reg);
1897                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1898                 I915_WRITE(reg, val);
1899         }
1900 }
1901
1902 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1903 {
1904         u32 val;
1905
1906         val = I915_READ(LPT_TRANSCONF);
1907         val &= ~TRANS_ENABLE;
1908         I915_WRITE(LPT_TRANSCONF, val);
1909         /* wait for PCH transcoder off, transcoder state */
1910         if (intel_wait_for_register(dev_priv,
1911                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1912                                     50))
1913                 DRM_ERROR("Failed to disable PCH transcoder\n");
1914
1915         /* Workaround: clear timing override bit. */
1916         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1917         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1918         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1919 }
1920
1921 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1922 {
1923         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1924
1925         WARN_ON(!crtc->config->has_pch_encoder);
1926
1927         if (HAS_PCH_LPT(dev_priv))
1928                 return TRANSCODER_A;
1929         else
1930                 return (enum transcoder) crtc->pipe;
1931 }
1932
1933 /**
1934  * intel_enable_pipe - enable a pipe, asserting requirements
1935  * @crtc: crtc responsible for the pipe
1936  *
1937  * Enable @crtc's pipe, making sure that various hardware specific requirements
1938  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1939  */
1940 static void intel_enable_pipe(struct intel_crtc *crtc)
1941 {
1942         struct drm_device *dev = crtc->base.dev;
1943         struct drm_i915_private *dev_priv = to_i915(dev);
1944         enum pipe pipe = crtc->pipe;
1945         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1946         i915_reg_t reg;
1947         u32 val;
1948
1949         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1950
1951         assert_planes_disabled(dev_priv, pipe);
1952         assert_cursor_disabled(dev_priv, pipe);
1953         assert_sprites_disabled(dev_priv, pipe);
1954
1955         /*
1956          * A pipe without a PLL won't actually be able to drive bits from
1957          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1958          * need the check.
1959          */
1960         if (HAS_GMCH_DISPLAY(dev_priv)) {
1961                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1962                         assert_dsi_pll_enabled(dev_priv);
1963                 else
1964                         assert_pll_enabled(dev_priv, pipe);
1965         } else {
1966                 if (crtc->config->has_pch_encoder) {
1967                         /* if driving the PCH, we need FDI enabled */
1968                         assert_fdi_rx_pll_enabled(dev_priv,
1969                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1970                         assert_fdi_tx_pll_enabled(dev_priv,
1971                                                   (enum pipe) cpu_transcoder);
1972                 }
1973                 /* FIXME: assert CPU port conditions for SNB+ */
1974         }
1975
1976         reg = PIPECONF(cpu_transcoder);
1977         val = I915_READ(reg);
1978         if (val & PIPECONF_ENABLE) {
1979                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1980                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1981                 return;
1982         }
1983
1984         I915_WRITE(reg, val | PIPECONF_ENABLE);
1985         POSTING_READ(reg);
1986
1987         /*
1988          * Until the pipe starts DSL will read as 0, which would cause
1989          * an apparent vblank timestamp jump, which messes up also the
1990          * frame count when it's derived from the timestamps. So let's
1991          * wait for the pipe to start properly before we call
1992          * drm_crtc_vblank_on()
1993          */
1994         if (dev->max_vblank_count == 0 &&
1995             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1996                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1997 }
1998
1999 /**
2000  * intel_disable_pipe - disable a pipe, asserting requirements
2001  * @crtc: crtc whose pipes is to be disabled
2002  *
2003  * Disable the pipe of @crtc, making sure that various hardware
2004  * specific requirements are met, if applicable, e.g. plane
2005  * disabled, panel fitter off, etc.
2006  *
2007  * Will wait until the pipe has shut down before returning.
2008  */
2009 static void intel_disable_pipe(struct intel_crtc *crtc)
2010 {
2011         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2012         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2013         enum pipe pipe = crtc->pipe;
2014         i915_reg_t reg;
2015         u32 val;
2016
2017         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2018
2019         /*
2020          * Make sure planes won't keep trying to pump pixels to us,
2021          * or we might hang the display.
2022          */
2023         assert_planes_disabled(dev_priv, pipe);
2024         assert_cursor_disabled(dev_priv, pipe);
2025         assert_sprites_disabled(dev_priv, pipe);
2026
2027         reg = PIPECONF(cpu_transcoder);
2028         val = I915_READ(reg);
2029         if ((val & PIPECONF_ENABLE) == 0)
2030                 return;
2031
2032         /*
2033          * Double wide has implications for planes
2034          * so best keep it disabled when not needed.
2035          */
2036         if (crtc->config->double_wide)
2037                 val &= ~PIPECONF_DOUBLE_WIDE;
2038
2039         /* Don't disable pipe or pipe PLLs if needed */
2040         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2041             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2042                 val &= ~PIPECONF_ENABLE;
2043
2044         I915_WRITE(reg, val);
2045         if ((val & PIPECONF_ENABLE) == 0)
2046                 intel_wait_for_pipe_off(crtc);
2047 }
2048
2049 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2050 {
2051         return IS_GEN2(dev_priv) ? 2048 : 4096;
2052 }
2053
2054 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2055                                            uint64_t fb_modifier, unsigned int cpp)
2056 {
2057         switch (fb_modifier) {
2058         case DRM_FORMAT_MOD_NONE:
2059                 return cpp;
2060         case I915_FORMAT_MOD_X_TILED:
2061                 if (IS_GEN2(dev_priv))
2062                         return 128;
2063                 else
2064                         return 512;
2065         case I915_FORMAT_MOD_Y_TILED:
2066                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2067                         return 128;
2068                 else
2069                         return 512;
2070         case I915_FORMAT_MOD_Yf_TILED:
2071                 switch (cpp) {
2072                 case 1:
2073                         return 64;
2074                 case 2:
2075                 case 4:
2076                         return 128;
2077                 case 8:
2078                 case 16:
2079                         return 256;
2080                 default:
2081                         MISSING_CASE(cpp);
2082                         return cpp;
2083                 }
2084                 break;
2085         default:
2086                 MISSING_CASE(fb_modifier);
2087                 return cpp;
2088         }
2089 }
2090
2091 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2092                                uint64_t fb_modifier, unsigned int cpp)
2093 {
2094         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2095                 return 1;
2096         else
2097                 return intel_tile_size(dev_priv) /
2098                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2099 }
2100
2101 /* Return the tile dimensions in pixel units */
2102 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2103                             unsigned int *tile_width,
2104                             unsigned int *tile_height,
2105                             uint64_t fb_modifier,
2106                             unsigned int cpp)
2107 {
2108         unsigned int tile_width_bytes =
2109                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2110
2111         *tile_width = tile_width_bytes / cpp;
2112         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2113 }
2114
2115 unsigned int
2116 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2117                       uint32_t pixel_format, uint64_t fb_modifier)
2118 {
2119         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2120         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2121
2122         return ALIGN(height, tile_height);
2123 }
2124
2125 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2126 {
2127         unsigned int size = 0;
2128         int i;
2129
2130         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2131                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2132
2133         return size;
2134 }
2135
2136 static void
2137 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2138                         const struct drm_framebuffer *fb,
2139                         unsigned int rotation)
2140 {
2141         if (drm_rotation_90_or_270(rotation)) {
2142                 *view = i915_ggtt_view_rotated;
2143                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2144         } else {
2145                 *view = i915_ggtt_view_normal;
2146         }
2147 }
2148
2149 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2150 {
2151         if (INTEL_INFO(dev_priv)->gen >= 9)
2152                 return 256 * 1024;
2153         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2154                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2155                 return 128 * 1024;
2156         else if (INTEL_INFO(dev_priv)->gen >= 4)
2157                 return 4 * 1024;
2158         else
2159                 return 0;
2160 }
2161
2162 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2163                                          uint64_t fb_modifier)
2164 {
2165         switch (fb_modifier) {
2166         case DRM_FORMAT_MOD_NONE:
2167                 return intel_linear_alignment(dev_priv);
2168         case I915_FORMAT_MOD_X_TILED:
2169                 if (INTEL_INFO(dev_priv)->gen >= 9)
2170                         return 256 * 1024;
2171                 return 0;
2172         case I915_FORMAT_MOD_Y_TILED:
2173         case I915_FORMAT_MOD_Yf_TILED:
2174                 return 1 * 1024 * 1024;
2175         default:
2176                 MISSING_CASE(fb_modifier);
2177                 return 0;
2178         }
2179 }
2180
2181 struct i915_vma *
2182 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2183 {
2184         struct drm_device *dev = fb->dev;
2185         struct drm_i915_private *dev_priv = to_i915(dev);
2186         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2187         struct i915_ggtt_view view;
2188         struct i915_vma *vma;
2189         u32 alignment;
2190
2191         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2192
2193         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2194
2195         intel_fill_fb_ggtt_view(&view, fb, rotation);
2196
2197         /* Note that the w/a also requires 64 PTE of padding following the
2198          * bo. We currently fill all unused PTE with the shadow page and so
2199          * we should always have valid PTE following the scanout preventing
2200          * the VT-d warning.
2201          */
2202         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2203                 alignment = 256 * 1024;
2204
2205         /*
2206          * Global gtt pte registers are special registers which actually forward
2207          * writes to a chunk of system memory. Which means that there is no risk
2208          * that the register values disappear as soon as we call
2209          * intel_runtime_pm_put(), so it is correct to wrap only the
2210          * pin/unpin/fence and not more.
2211          */
2212         intel_runtime_pm_get(dev_priv);
2213
2214         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2215         if (IS_ERR(vma))
2216                 goto err;
2217
2218         if (i915_vma_is_map_and_fenceable(vma)) {
2219                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2220                  * fence, whereas 965+ only requires a fence if using
2221                  * framebuffer compression.  For simplicity, we always, when
2222                  * possible, install a fence as the cost is not that onerous.
2223                  *
2224                  * If we fail to fence the tiled scanout, then either the
2225                  * modeset will reject the change (which is highly unlikely as
2226                  * the affected systems, all but one, do not have unmappable
2227                  * space) or we will not be able to enable full powersaving
2228                  * techniques (also likely not to apply due to various limits
2229                  * FBC and the like impose on the size of the buffer, which
2230                  * presumably we violated anyway with this unmappable buffer).
2231                  * Anyway, it is presumably better to stumble onwards with
2232                  * something and try to run the system in a "less than optimal"
2233                  * mode that matches the user configuration.
2234                  */
2235                 if (i915_vma_get_fence(vma) == 0)
2236                         i915_vma_pin_fence(vma);
2237         }
2238
2239 err:
2240         intel_runtime_pm_put(dev_priv);
2241         return vma;
2242 }
2243
2244 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2245 {
2246         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2247         struct i915_ggtt_view view;
2248         struct i915_vma *vma;
2249
2250         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2251
2252         intel_fill_fb_ggtt_view(&view, fb, rotation);
2253         vma = i915_gem_object_to_ggtt(obj, &view);
2254
2255         i915_vma_unpin_fence(vma);
2256         i915_gem_object_unpin_from_display_plane(vma);
2257 }
2258
2259 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2260                           unsigned int rotation)
2261 {
2262         if (drm_rotation_90_or_270(rotation))
2263                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2264         else
2265                 return fb->pitches[plane];
2266 }
2267
2268 /*
2269  * Convert the x/y offsets into a linear offset.
2270  * Only valid with 0/180 degree rotation, which is fine since linear
2271  * offset is only used with linear buffers on pre-hsw and tiled buffers
2272  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2273  */
2274 u32 intel_fb_xy_to_linear(int x, int y,
2275                           const struct intel_plane_state *state,
2276                           int plane)
2277 {
2278         const struct drm_framebuffer *fb = state->base.fb;
2279         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2280         unsigned int pitch = fb->pitches[plane];
2281
2282         return y * pitch + x * cpp;
2283 }
2284
2285 /*
2286  * Add the x/y offsets derived from fb->offsets[] to the user
2287  * specified plane src x/y offsets. The resulting x/y offsets
2288  * specify the start of scanout from the beginning of the gtt mapping.
2289  */
2290 void intel_add_fb_offsets(int *x, int *y,
2291                           const struct intel_plane_state *state,
2292                           int plane)
2293
2294 {
2295         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2296         unsigned int rotation = state->base.rotation;
2297
2298         if (drm_rotation_90_or_270(rotation)) {
2299                 *x += intel_fb->rotated[plane].x;
2300                 *y += intel_fb->rotated[plane].y;
2301         } else {
2302                 *x += intel_fb->normal[plane].x;
2303                 *y += intel_fb->normal[plane].y;
2304         }
2305 }
2306
2307 /*
2308  * Input tile dimensions and pitch must already be
2309  * rotated to match x and y, and in pixel units.
2310  */
2311 static u32 _intel_adjust_tile_offset(int *x, int *y,
2312                                      unsigned int tile_width,
2313                                      unsigned int tile_height,
2314                                      unsigned int tile_size,
2315                                      unsigned int pitch_tiles,
2316                                      u32 old_offset,
2317                                      u32 new_offset)
2318 {
2319         unsigned int pitch_pixels = pitch_tiles * tile_width;
2320         unsigned int tiles;
2321
2322         WARN_ON(old_offset & (tile_size - 1));
2323         WARN_ON(new_offset & (tile_size - 1));
2324         WARN_ON(new_offset > old_offset);
2325
2326         tiles = (old_offset - new_offset) / tile_size;
2327
2328         *y += tiles / pitch_tiles * tile_height;
2329         *x += tiles % pitch_tiles * tile_width;
2330
2331         /* minimize x in case it got needlessly big */
2332         *y += *x / pitch_pixels * tile_height;
2333         *x %= pitch_pixels;
2334
2335         return new_offset;
2336 }
2337
2338 /*
2339  * Adjust the tile offset by moving the difference into
2340  * the x/y offsets.
2341  */
2342 static u32 intel_adjust_tile_offset(int *x, int *y,
2343                                     const struct intel_plane_state *state, int plane,
2344                                     u32 old_offset, u32 new_offset)
2345 {
2346         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2347         const struct drm_framebuffer *fb = state->base.fb;
2348         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2349         unsigned int rotation = state->base.rotation;
2350         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2351
2352         WARN_ON(new_offset > old_offset);
2353
2354         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2355                 unsigned int tile_size, tile_width, tile_height;
2356                 unsigned int pitch_tiles;
2357
2358                 tile_size = intel_tile_size(dev_priv);
2359                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2360                                 fb->modifier, cpp);
2361
2362                 if (drm_rotation_90_or_270(rotation)) {
2363                         pitch_tiles = pitch / tile_height;
2364                         swap(tile_width, tile_height);
2365                 } else {
2366                         pitch_tiles = pitch / (tile_width * cpp);
2367                 }
2368
2369                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2370                                           tile_size, pitch_tiles,
2371                                           old_offset, new_offset);
2372         } else {
2373                 old_offset += *y * pitch + *x * cpp;
2374
2375                 *y = (old_offset - new_offset) / pitch;
2376                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2377         }
2378
2379         return new_offset;
2380 }
2381
2382 /*
2383  * Computes the linear offset to the base tile and adjusts
2384  * x, y. bytes per pixel is assumed to be a power-of-two.
2385  *
2386  * In the 90/270 rotated case, x and y are assumed
2387  * to be already rotated to match the rotated GTT view, and
2388  * pitch is the tile_height aligned framebuffer height.
2389  *
2390  * This function is used when computing the derived information
2391  * under intel_framebuffer, so using any of that information
2392  * here is not allowed. Anything under drm_framebuffer can be
2393  * used. This is why the user has to pass in the pitch since it
2394  * is specified in the rotated orientation.
2395  */
2396 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2397                                       int *x, int *y,
2398                                       const struct drm_framebuffer *fb, int plane,
2399                                       unsigned int pitch,
2400                                       unsigned int rotation,
2401                                       u32 alignment)
2402 {
2403         uint64_t fb_modifier = fb->modifier;
2404         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2405         u32 offset, offset_aligned;
2406
2407         if (alignment)
2408                 alignment--;
2409
2410         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2411                 unsigned int tile_size, tile_width, tile_height;
2412                 unsigned int tile_rows, tiles, pitch_tiles;
2413
2414                 tile_size = intel_tile_size(dev_priv);
2415                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2416                                 fb_modifier, cpp);
2417
2418                 if (drm_rotation_90_or_270(rotation)) {
2419                         pitch_tiles = pitch / tile_height;
2420                         swap(tile_width, tile_height);
2421                 } else {
2422                         pitch_tiles = pitch / (tile_width * cpp);
2423                 }
2424
2425                 tile_rows = *y / tile_height;
2426                 *y %= tile_height;
2427
2428                 tiles = *x / tile_width;
2429                 *x %= tile_width;
2430
2431                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2432                 offset_aligned = offset & ~alignment;
2433
2434                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2435                                           tile_size, pitch_tiles,
2436                                           offset, offset_aligned);
2437         } else {
2438                 offset = *y * pitch + *x * cpp;
2439                 offset_aligned = offset & ~alignment;
2440
2441                 *y = (offset & alignment) / pitch;
2442                 *x = ((offset & alignment) - *y * pitch) / cpp;
2443         }
2444
2445         return offset_aligned;
2446 }
2447
2448 u32 intel_compute_tile_offset(int *x, int *y,
2449                               const struct intel_plane_state *state,
2450                               int plane)
2451 {
2452         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2453         const struct drm_framebuffer *fb = state->base.fb;
2454         unsigned int rotation = state->base.rotation;
2455         int pitch = intel_fb_pitch(fb, plane, rotation);
2456         u32 alignment;
2457
2458         /* AUX_DIST needs only 4K alignment */
2459         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2460                 alignment = 4096;
2461         else
2462                 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2463
2464         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2465                                           rotation, alignment);
2466 }
2467
2468 /* Convert the fb->offset[] linear offset into x/y offsets */
2469 static void intel_fb_offset_to_xy(int *x, int *y,
2470                                   const struct drm_framebuffer *fb, int plane)
2471 {
2472         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2473         unsigned int pitch = fb->pitches[plane];
2474         u32 linear_offset = fb->offsets[plane];
2475
2476         *y = linear_offset / pitch;
2477         *x = linear_offset % pitch / cpp;
2478 }
2479
2480 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2481 {
2482         switch (fb_modifier) {
2483         case I915_FORMAT_MOD_X_TILED:
2484                 return I915_TILING_X;
2485         case I915_FORMAT_MOD_Y_TILED:
2486                 return I915_TILING_Y;
2487         default:
2488                 return I915_TILING_NONE;
2489         }
2490 }
2491
2492 static int
2493 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2494                    struct drm_framebuffer *fb)
2495 {
2496         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2497         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2498         u32 gtt_offset_rotated = 0;
2499         unsigned int max_size = 0;
2500         uint32_t format = fb->pixel_format;
2501         int i, num_planes = drm_format_num_planes(format);
2502         unsigned int tile_size = intel_tile_size(dev_priv);
2503
2504         for (i = 0; i < num_planes; i++) {
2505                 unsigned int width, height;
2506                 unsigned int cpp, size;
2507                 u32 offset;
2508                 int x, y;
2509
2510                 cpp = drm_format_plane_cpp(format, i);
2511                 width = drm_format_plane_width(fb->width, format, i);
2512                 height = drm_format_plane_height(fb->height, format, i);
2513
2514                 intel_fb_offset_to_xy(&x, &y, fb, i);
2515
2516                 /*
2517                  * The fence (if used) is aligned to the start of the object
2518                  * so having the framebuffer wrap around across the edge of the
2519                  * fenced region doesn't really work. We have no API to configure
2520                  * the fence start offset within the object (nor could we probably
2521                  * on gen2/3). So it's just easier if we just require that the
2522                  * fb layout agrees with the fence layout. We already check that the
2523                  * fb stride matches the fence stride elsewhere.
2524                  */
2525                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2526                     (x + width) * cpp > fb->pitches[i]) {
2527                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2528                                   i, fb->offsets[i]);
2529                         return -EINVAL;
2530                 }
2531
2532                 /*
2533                  * First pixel of the framebuffer from
2534                  * the start of the normal gtt mapping.
2535                  */
2536                 intel_fb->normal[i].x = x;
2537                 intel_fb->normal[i].y = y;
2538
2539                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2540                                                     fb, 0, fb->pitches[i],
2541                                                     DRM_ROTATE_0, tile_size);
2542                 offset /= tile_size;
2543
2544                 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2545                         unsigned int tile_width, tile_height;
2546                         unsigned int pitch_tiles;
2547                         struct drm_rect r;
2548
2549                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2550                                         fb->modifier, cpp);
2551
2552                         rot_info->plane[i].offset = offset;
2553                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2554                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2555                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2556
2557                         intel_fb->rotated[i].pitch =
2558                                 rot_info->plane[i].height * tile_height;
2559
2560                         /* how many tiles does this plane need */
2561                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2562                         /*
2563                          * If the plane isn't horizontally tile aligned,
2564                          * we need one more tile.
2565                          */
2566                         if (x != 0)
2567                                 size++;
2568
2569                         /* rotate the x/y offsets to match the GTT view */
2570                         r.x1 = x;
2571                         r.y1 = y;
2572                         r.x2 = x + width;
2573                         r.y2 = y + height;
2574                         drm_rect_rotate(&r,
2575                                         rot_info->plane[i].width * tile_width,
2576                                         rot_info->plane[i].height * tile_height,
2577                                         DRM_ROTATE_270);
2578                         x = r.x1;
2579                         y = r.y1;
2580
2581                         /* rotate the tile dimensions to match the GTT view */
2582                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2583                         swap(tile_width, tile_height);
2584
2585                         /*
2586                          * We only keep the x/y offsets, so push all of the
2587                          * gtt offset into the x/y offsets.
2588                          */
2589                         _intel_adjust_tile_offset(&x, &y, tile_size,
2590                                                   tile_width, tile_height, pitch_tiles,
2591                                                   gtt_offset_rotated * tile_size, 0);
2592
2593                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2594
2595                         /*
2596                          * First pixel of the framebuffer from
2597                          * the start of the rotated gtt mapping.
2598                          */
2599                         intel_fb->rotated[i].x = x;
2600                         intel_fb->rotated[i].y = y;
2601                 } else {
2602                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2603                                             x * cpp, tile_size);
2604                 }
2605
2606                 /* how many tiles in total needed in the bo */
2607                 max_size = max(max_size, offset + size);
2608         }
2609
2610         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2611                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2612                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2613                 return -EINVAL;
2614         }
2615
2616         return 0;
2617 }
2618
2619 static int i9xx_format_to_fourcc(int format)
2620 {
2621         switch (format) {
2622         case DISPPLANE_8BPP:
2623                 return DRM_FORMAT_C8;
2624         case DISPPLANE_BGRX555:
2625                 return DRM_FORMAT_XRGB1555;
2626         case DISPPLANE_BGRX565:
2627                 return DRM_FORMAT_RGB565;
2628         default:
2629         case DISPPLANE_BGRX888:
2630                 return DRM_FORMAT_XRGB8888;
2631         case DISPPLANE_RGBX888:
2632                 return DRM_FORMAT_XBGR8888;
2633         case DISPPLANE_BGRX101010:
2634                 return DRM_FORMAT_XRGB2101010;
2635         case DISPPLANE_RGBX101010:
2636                 return DRM_FORMAT_XBGR2101010;
2637         }
2638 }
2639
2640 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2641 {
2642         switch (format) {
2643         case PLANE_CTL_FORMAT_RGB_565:
2644                 return DRM_FORMAT_RGB565;
2645         default:
2646         case PLANE_CTL_FORMAT_XRGB_8888:
2647                 if (rgb_order) {
2648                         if (alpha)
2649                                 return DRM_FORMAT_ABGR8888;
2650                         else
2651                                 return DRM_FORMAT_XBGR8888;
2652                 } else {
2653                         if (alpha)
2654                                 return DRM_FORMAT_ARGB8888;
2655                         else
2656                                 return DRM_FORMAT_XRGB8888;
2657                 }
2658         case PLANE_CTL_FORMAT_XRGB_2101010:
2659                 if (rgb_order)
2660                         return DRM_FORMAT_XBGR2101010;
2661                 else
2662                         return DRM_FORMAT_XRGB2101010;
2663         }
2664 }
2665
2666 static bool
2667 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2668                               struct intel_initial_plane_config *plane_config)
2669 {
2670         struct drm_device *dev = crtc->base.dev;
2671         struct drm_i915_private *dev_priv = to_i915(dev);
2672         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2673         struct drm_i915_gem_object *obj = NULL;
2674         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2675         struct drm_framebuffer *fb = &plane_config->fb->base;
2676         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2677         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2678                                     PAGE_SIZE);
2679
2680         size_aligned -= base_aligned;
2681
2682         if (plane_config->size == 0)
2683                 return false;
2684
2685         /* If the FB is too big, just don't use it since fbdev is not very
2686          * important and we should probably use that space with FBC or other
2687          * features. */
2688         if (size_aligned * 2 > ggtt->stolen_usable_size)
2689                 return false;
2690
2691         mutex_lock(&dev->struct_mutex);
2692
2693         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2694                                                              base_aligned,
2695                                                              base_aligned,
2696                                                              size_aligned);
2697         if (!obj) {
2698                 mutex_unlock(&dev->struct_mutex);
2699                 return false;
2700         }
2701
2702         if (plane_config->tiling == I915_TILING_X)
2703                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2704
2705         mode_cmd.pixel_format = fb->pixel_format;
2706         mode_cmd.width = fb->width;
2707         mode_cmd.height = fb->height;
2708         mode_cmd.pitches[0] = fb->pitches[0];
2709         mode_cmd.modifier[0] = fb->modifier;
2710         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2711
2712         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2713                                    &mode_cmd, obj)) {
2714                 DRM_DEBUG_KMS("intel fb init failed\n");
2715                 goto out_unref_obj;
2716         }
2717
2718         mutex_unlock(&dev->struct_mutex);
2719
2720         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2721         return true;
2722
2723 out_unref_obj:
2724         i915_gem_object_put(obj);
2725         mutex_unlock(&dev->struct_mutex);
2726         return false;
2727 }
2728
2729 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2730 static void
2731 update_state_fb(struct drm_plane *plane)
2732 {
2733         if (plane->fb == plane->state->fb)
2734                 return;
2735
2736         if (plane->state->fb)
2737                 drm_framebuffer_unreference(plane->state->fb);
2738         plane->state->fb = plane->fb;
2739         if (plane->state->fb)
2740                 drm_framebuffer_reference(plane->state->fb);
2741 }
2742
2743 static void
2744 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2745                              struct intel_initial_plane_config *plane_config)
2746 {
2747         struct drm_device *dev = intel_crtc->base.dev;
2748         struct drm_i915_private *dev_priv = to_i915(dev);
2749         struct drm_crtc *c;
2750         struct intel_crtc *i;
2751         struct drm_i915_gem_object *obj;
2752         struct drm_plane *primary = intel_crtc->base.primary;
2753         struct drm_plane_state *plane_state = primary->state;
2754         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2755         struct intel_plane *intel_plane = to_intel_plane(primary);
2756         struct intel_plane_state *intel_state =
2757                 to_intel_plane_state(plane_state);
2758         struct drm_framebuffer *fb;
2759
2760         if (!plane_config->fb)
2761                 return;
2762
2763         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2764                 fb = &plane_config->fb->base;
2765                 goto valid_fb;
2766         }
2767
2768         kfree(plane_config->fb);
2769
2770         /*
2771          * Failed to alloc the obj, check to see if we should share
2772          * an fb with another CRTC instead
2773          */
2774         for_each_crtc(dev, c) {
2775                 i = to_intel_crtc(c);
2776
2777                 if (c == &intel_crtc->base)
2778                         continue;
2779
2780                 if (!i->active)
2781                         continue;
2782
2783                 fb = c->primary->fb;
2784                 if (!fb)
2785                         continue;
2786
2787                 obj = intel_fb_obj(fb);
2788                 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2789                         drm_framebuffer_reference(fb);
2790                         goto valid_fb;
2791                 }
2792         }
2793
2794         /*
2795          * We've failed to reconstruct the BIOS FB.  Current display state
2796          * indicates that the primary plane is visible, but has a NULL FB,
2797          * which will lead to problems later if we don't fix it up.  The
2798          * simplest solution is to just disable the primary plane now and
2799          * pretend the BIOS never had it enabled.
2800          */
2801         to_intel_plane_state(plane_state)->base.visible = false;
2802         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2803         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2804         intel_plane->disable_plane(primary, &intel_crtc->base);
2805
2806         return;
2807
2808 valid_fb:
2809         plane_state->src_x = 0;
2810         plane_state->src_y = 0;
2811         plane_state->src_w = fb->width << 16;
2812         plane_state->src_h = fb->height << 16;
2813
2814         plane_state->crtc_x = 0;
2815         plane_state->crtc_y = 0;
2816         plane_state->crtc_w = fb->width;
2817         plane_state->crtc_h = fb->height;
2818
2819         intel_state->base.src = drm_plane_state_src(plane_state);
2820         intel_state->base.dst = drm_plane_state_dest(plane_state);
2821
2822         obj = intel_fb_obj(fb);
2823         if (i915_gem_object_is_tiled(obj))
2824                 dev_priv->preserve_bios_swizzle = true;
2825
2826         drm_framebuffer_reference(fb);
2827         primary->fb = primary->state->fb = fb;
2828         primary->crtc = primary->state->crtc = &intel_crtc->base;
2829         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2830         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2831                   &obj->frontbuffer_bits);
2832 }
2833
2834 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2835                                unsigned int rotation)
2836 {
2837         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2838
2839         switch (fb->modifier) {
2840         case DRM_FORMAT_MOD_NONE:
2841         case I915_FORMAT_MOD_X_TILED:
2842                 switch (cpp) {
2843                 case 8:
2844                         return 4096;
2845                 case 4:
2846                 case 2:
2847                 case 1:
2848                         return 8192;
2849                 default:
2850                         MISSING_CASE(cpp);
2851                         break;
2852                 }
2853                 break;
2854         case I915_FORMAT_MOD_Y_TILED:
2855         case I915_FORMAT_MOD_Yf_TILED:
2856                 switch (cpp) {
2857                 case 8:
2858                         return 2048;
2859                 case 4:
2860                         return 4096;
2861                 case 2:
2862                 case 1:
2863                         return 8192;
2864                 default:
2865                         MISSING_CASE(cpp);
2866                         break;
2867                 }
2868                 break;
2869         default:
2870                 MISSING_CASE(fb->modifier);
2871         }
2872
2873         return 2048;
2874 }
2875
2876 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2877 {
2878         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2879         const struct drm_framebuffer *fb = plane_state->base.fb;
2880         unsigned int rotation = plane_state->base.rotation;
2881         int x = plane_state->base.src.x1 >> 16;
2882         int y = plane_state->base.src.y1 >> 16;
2883         int w = drm_rect_width(&plane_state->base.src) >> 16;
2884         int h = drm_rect_height(&plane_state->base.src) >> 16;
2885         int max_width = skl_max_plane_width(fb, 0, rotation);
2886         int max_height = 4096;
2887         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2888
2889         if (w > max_width || h > max_height) {
2890                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2891                               w, h, max_width, max_height);
2892                 return -EINVAL;
2893         }
2894
2895         intel_add_fb_offsets(&x, &y, plane_state, 0);
2896         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2897
2898         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2899
2900         /*
2901          * AUX surface offset is specified as the distance from the
2902          * main surface offset, and it must be non-negative. Make
2903          * sure that is what we will get.
2904          */
2905         if (offset > aux_offset)
2906                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2907                                                   offset, aux_offset & ~(alignment - 1));
2908
2909         /*
2910          * When using an X-tiled surface, the plane blows up
2911          * if the x offset + width exceed the stride.
2912          *
2913          * TODO: linear and Y-tiled seem fine, Yf untested,
2914          */
2915         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2916                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2917
2918                 while ((x + w) * cpp > fb->pitches[0]) {
2919                         if (offset == 0) {
2920                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2921                                 return -EINVAL;
2922                         }
2923
2924                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2925                                                           offset, offset - alignment);
2926                 }
2927         }
2928
2929         plane_state->main.offset = offset;
2930         plane_state->main.x = x;
2931         plane_state->main.y = y;
2932
2933         return 0;
2934 }
2935
2936 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2937 {
2938         const struct drm_framebuffer *fb = plane_state->base.fb;
2939         unsigned int rotation = plane_state->base.rotation;
2940         int max_width = skl_max_plane_width(fb, 1, rotation);
2941         int max_height = 4096;
2942         int x = plane_state->base.src.x1 >> 17;
2943         int y = plane_state->base.src.y1 >> 17;
2944         int w = drm_rect_width(&plane_state->base.src) >> 17;
2945         int h = drm_rect_height(&plane_state->base.src) >> 17;
2946         u32 offset;
2947
2948         intel_add_fb_offsets(&x, &y, plane_state, 1);
2949         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2950
2951         /* FIXME not quite sure how/if these apply to the chroma plane */
2952         if (w > max_width || h > max_height) {
2953                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2954                               w, h, max_width, max_height);
2955                 return -EINVAL;
2956         }
2957
2958         plane_state->aux.offset = offset;
2959         plane_state->aux.x = x;
2960         plane_state->aux.y = y;
2961
2962         return 0;
2963 }
2964
2965 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2966 {
2967         const struct drm_framebuffer *fb = plane_state->base.fb;
2968         unsigned int rotation = plane_state->base.rotation;
2969         int ret;
2970
2971         /* Rotate src coordinates to match rotated GTT view */
2972         if (drm_rotation_90_or_270(rotation))
2973                 drm_rect_rotate(&plane_state->base.src,
2974                                 fb->width << 16, fb->height << 16,
2975                                 DRM_ROTATE_270);
2976
2977         /*
2978          * Handle the AUX surface first since
2979          * the main surface setup depends on it.
2980          */
2981         if (fb->pixel_format == DRM_FORMAT_NV12) {
2982                 ret = skl_check_nv12_aux_surface(plane_state);
2983                 if (ret)
2984                         return ret;
2985         } else {
2986                 plane_state->aux.offset = ~0xfff;
2987                 plane_state->aux.x = 0;
2988                 plane_state->aux.y = 0;
2989         }
2990
2991         ret = skl_check_main_surface(plane_state);
2992         if (ret)
2993                 return ret;
2994
2995         return 0;
2996 }
2997
2998 static void i9xx_update_primary_plane(struct drm_plane *primary,
2999                                       const struct intel_crtc_state *crtc_state,
3000                                       const struct intel_plane_state *plane_state)
3001 {
3002         struct drm_i915_private *dev_priv = to_i915(primary->dev);
3003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3004         struct drm_framebuffer *fb = plane_state->base.fb;
3005         int plane = intel_crtc->plane;
3006         u32 linear_offset;
3007         u32 dspcntr;
3008         i915_reg_t reg = DSPCNTR(plane);
3009         unsigned int rotation = plane_state->base.rotation;
3010         int x = plane_state->base.src.x1 >> 16;
3011         int y = plane_state->base.src.y1 >> 16;
3012
3013         dspcntr = DISPPLANE_GAMMA_ENABLE;
3014
3015         dspcntr |= DISPLAY_PLANE_ENABLE;
3016
3017         if (INTEL_GEN(dev_priv) < 4) {
3018                 if (intel_crtc->pipe == PIPE_B)
3019                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3020
3021                 /* pipesrc and dspsize control the size that is scaled from,
3022                  * which should always be the user's requested size.
3023                  */
3024                 I915_WRITE(DSPSIZE(plane),
3025                            ((crtc_state->pipe_src_h - 1) << 16) |
3026                            (crtc_state->pipe_src_w - 1));
3027                 I915_WRITE(DSPPOS(plane), 0);
3028         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3029                 I915_WRITE(PRIMSIZE(plane),
3030                            ((crtc_state->pipe_src_h - 1) << 16) |
3031                            (crtc_state->pipe_src_w - 1));
3032                 I915_WRITE(PRIMPOS(plane), 0);
3033                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3034         }
3035
3036         switch (fb->pixel_format) {
3037         case DRM_FORMAT_C8:
3038                 dspcntr |= DISPPLANE_8BPP;
3039                 break;
3040         case DRM_FORMAT_XRGB1555:
3041                 dspcntr |= DISPPLANE_BGRX555;
3042                 break;
3043         case DRM_FORMAT_RGB565:
3044                 dspcntr |= DISPPLANE_BGRX565;
3045                 break;
3046         case DRM_FORMAT_XRGB8888:
3047                 dspcntr |= DISPPLANE_BGRX888;
3048                 break;
3049         case DRM_FORMAT_XBGR8888:
3050                 dspcntr |= DISPPLANE_RGBX888;
3051                 break;
3052         case DRM_FORMAT_XRGB2101010:
3053                 dspcntr |= DISPPLANE_BGRX101010;
3054                 break;
3055         case DRM_FORMAT_XBGR2101010:
3056                 dspcntr |= DISPPLANE_RGBX101010;
3057                 break;
3058         default:
3059                 BUG();
3060         }
3061
3062         if (INTEL_GEN(dev_priv) >= 4 &&
3063             fb->modifier == I915_FORMAT_MOD_X_TILED)
3064                 dspcntr |= DISPPLANE_TILED;
3065
3066         if (rotation & DRM_ROTATE_180)
3067                 dspcntr |= DISPPLANE_ROTATE_180;
3068
3069         if (rotation & DRM_REFLECT_X)
3070                 dspcntr |= DISPPLANE_MIRROR;
3071
3072         if (IS_G4X(dev_priv))
3073                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3074
3075         intel_add_fb_offsets(&x, &y, plane_state, 0);
3076
3077         if (INTEL_GEN(dev_priv) >= 4)
3078                 intel_crtc->dspaddr_offset =
3079                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3080
3081         if (rotation & DRM_ROTATE_180) {
3082                 x += crtc_state->pipe_src_w - 1;
3083                 y += crtc_state->pipe_src_h - 1;
3084         } else if (rotation & DRM_REFLECT_X) {
3085                 x += crtc_state->pipe_src_w - 1;
3086         }
3087
3088         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3089
3090         if (INTEL_GEN(dev_priv) < 4)
3091                 intel_crtc->dspaddr_offset = linear_offset;
3092
3093         intel_crtc->adjusted_x = x;
3094         intel_crtc->adjusted_y = y;
3095
3096         I915_WRITE(reg, dspcntr);
3097
3098         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3099         if (INTEL_GEN(dev_priv) >= 4) {
3100                 I915_WRITE(DSPSURF(plane),
3101                            intel_fb_gtt_offset(fb, rotation) +
3102                            intel_crtc->dspaddr_offset);
3103                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3104                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3105         } else {
3106                 I915_WRITE(DSPADDR(plane),
3107                            intel_fb_gtt_offset(fb, rotation) +
3108                            intel_crtc->dspaddr_offset);
3109         }
3110         POSTING_READ(reg);
3111 }
3112
3113 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3114                                        struct drm_crtc *crtc)
3115 {
3116         struct drm_device *dev = crtc->dev;
3117         struct drm_i915_private *dev_priv = to_i915(dev);
3118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3119         int plane = intel_crtc->plane;
3120
3121         I915_WRITE(DSPCNTR(plane), 0);
3122         if (INTEL_INFO(dev_priv)->gen >= 4)
3123                 I915_WRITE(DSPSURF(plane), 0);
3124         else
3125                 I915_WRITE(DSPADDR(plane), 0);
3126         POSTING_READ(DSPCNTR(plane));
3127 }
3128
3129 static void ironlake_update_primary_plane(struct drm_plane *primary,
3130                                           const struct intel_crtc_state *crtc_state,
3131                                           const struct intel_plane_state *plane_state)
3132 {
3133         struct drm_device *dev = primary->dev;
3134         struct drm_i915_private *dev_priv = to_i915(dev);
3135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3136         struct drm_framebuffer *fb = plane_state->base.fb;
3137         int plane = intel_crtc->plane;
3138         u32 linear_offset;
3139         u32 dspcntr;
3140         i915_reg_t reg = DSPCNTR(plane);
3141         unsigned int rotation = plane_state->base.rotation;
3142         int x = plane_state->base.src.x1 >> 16;
3143         int y = plane_state->base.src.y1 >> 16;
3144
3145         dspcntr = DISPPLANE_GAMMA_ENABLE;
3146         dspcntr |= DISPLAY_PLANE_ENABLE;
3147
3148         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3149                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3150
3151         switch (fb->pixel_format) {
3152         case DRM_FORMAT_C8:
3153                 dspcntr |= DISPPLANE_8BPP;
3154                 break;
3155         case DRM_FORMAT_RGB565:
3156                 dspcntr |= DISPPLANE_BGRX565;
3157                 break;
3158         case DRM_FORMAT_XRGB8888:
3159                 dspcntr |= DISPPLANE_BGRX888;
3160                 break;
3161         case DRM_FORMAT_XBGR8888:
3162                 dspcntr |= DISPPLANE_RGBX888;
3163                 break;
3164         case DRM_FORMAT_XRGB2101010:
3165                 dspcntr |= DISPPLANE_BGRX101010;
3166                 break;
3167         case DRM_FORMAT_XBGR2101010:
3168                 dspcntr |= DISPPLANE_RGBX101010;
3169                 break;
3170         default:
3171                 BUG();
3172         }
3173
3174         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3175                 dspcntr |= DISPPLANE_TILED;
3176
3177         if (rotation & DRM_ROTATE_180)
3178                 dspcntr |= DISPPLANE_ROTATE_180;
3179
3180         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3181                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3182
3183         intel_add_fb_offsets(&x, &y, plane_state, 0);
3184
3185         intel_crtc->dspaddr_offset =
3186                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3187
3188         /* HSW+ does this automagically in hardware */
3189         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3190             rotation & DRM_ROTATE_180) {
3191                 x += crtc_state->pipe_src_w - 1;
3192                 y += crtc_state->pipe_src_h - 1;
3193         }
3194
3195         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3196
3197         intel_crtc->adjusted_x = x;
3198         intel_crtc->adjusted_y = y;
3199
3200         I915_WRITE(reg, dspcntr);
3201
3202         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3203         I915_WRITE(DSPSURF(plane),
3204                    intel_fb_gtt_offset(fb, rotation) +
3205                    intel_crtc->dspaddr_offset);
3206         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3207                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3208         } else {
3209                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3210                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3211         }
3212         POSTING_READ(reg);
3213 }
3214
3215 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3216                               uint64_t fb_modifier, uint32_t pixel_format)
3217 {
3218         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3219                 return 64;
3220         } else {
3221                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3222
3223                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3224         }
3225 }
3226
3227 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3228                         unsigned int rotation)
3229 {
3230         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3231         struct i915_ggtt_view view;
3232         struct i915_vma *vma;
3233
3234         intel_fill_fb_ggtt_view(&view, fb, rotation);
3235
3236         vma = i915_gem_object_to_ggtt(obj, &view);
3237         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3238                  view.type))
3239                 return -1;
3240
3241         return i915_ggtt_offset(vma);
3242 }
3243
3244 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3245 {
3246         struct drm_device *dev = intel_crtc->base.dev;
3247         struct drm_i915_private *dev_priv = to_i915(dev);
3248
3249         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3250         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3251         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3252 }
3253
3254 /*
3255  * This function detaches (aka. unbinds) unused scalers in hardware
3256  */
3257 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3258 {
3259         struct intel_crtc_scaler_state *scaler_state;
3260         int i;
3261
3262         scaler_state = &intel_crtc->config->scaler_state;
3263
3264         /* loop through and disable scalers that aren't in use */
3265         for (i = 0; i < intel_crtc->num_scalers; i++) {
3266                 if (!scaler_state->scalers[i].in_use)
3267                         skl_detach_scaler(intel_crtc, i);
3268         }
3269 }
3270
3271 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3272                      unsigned int rotation)
3273 {
3274         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3275         u32 stride = intel_fb_pitch(fb, plane, rotation);
3276
3277         /*
3278          * The stride is either expressed as a multiple of 64 bytes chunks for
3279          * linear buffers or in number of tiles for tiled buffers.
3280          */
3281         if (drm_rotation_90_or_270(rotation)) {
3282                 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3283
3284                 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
3285         } else {
3286                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
3287                                                     fb->pixel_format);
3288         }
3289
3290         return stride;
3291 }
3292
3293 u32 skl_plane_ctl_format(uint32_t pixel_format)
3294 {
3295         switch (pixel_format) {
3296         case DRM_FORMAT_C8:
3297                 return PLANE_CTL_FORMAT_INDEXED;
3298         case DRM_FORMAT_RGB565:
3299                 return PLANE_CTL_FORMAT_RGB_565;
3300         case DRM_FORMAT_XBGR8888:
3301                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3302         case DRM_FORMAT_XRGB8888:
3303                 return PLANE_CTL_FORMAT_XRGB_8888;
3304         /*
3305          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3306          * to be already pre-multiplied. We need to add a knob (or a different
3307          * DRM_FORMAT) for user-space to configure that.
3308          */
3309         case DRM_FORMAT_ABGR8888:
3310                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3311                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3312         case DRM_FORMAT_ARGB8888:
3313                 return PLANE_CTL_FORMAT_XRGB_8888 |
3314                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3315         case DRM_FORMAT_XRGB2101010:
3316                 return PLANE_CTL_FORMAT_XRGB_2101010;
3317         case DRM_FORMAT_XBGR2101010:
3318                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3319         case DRM_FORMAT_YUYV:
3320                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3321         case DRM_FORMAT_YVYU:
3322                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3323         case DRM_FORMAT_UYVY:
3324                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3325         case DRM_FORMAT_VYUY:
3326                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3327         default:
3328                 MISSING_CASE(pixel_format);
3329         }
3330
3331         return 0;
3332 }
3333
3334 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3335 {
3336         switch (fb_modifier) {
3337         case DRM_FORMAT_MOD_NONE:
3338                 break;
3339         case I915_FORMAT_MOD_X_TILED:
3340                 return PLANE_CTL_TILED_X;
3341         case I915_FORMAT_MOD_Y_TILED:
3342                 return PLANE_CTL_TILED_Y;
3343         case I915_FORMAT_MOD_Yf_TILED:
3344                 return PLANE_CTL_TILED_YF;
3345         default:
3346                 MISSING_CASE(fb_modifier);
3347         }
3348
3349         return 0;
3350 }
3351
3352 u32 skl_plane_ctl_rotation(unsigned int rotation)
3353 {
3354         switch (rotation) {
3355         case DRM_ROTATE_0:
3356                 break;
3357         /*
3358          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3359          * while i915 HW rotation is clockwise, thats why this swapping.
3360          */
3361         case DRM_ROTATE_90:
3362                 return PLANE_CTL_ROTATE_270;
3363         case DRM_ROTATE_180:
3364                 return PLANE_CTL_ROTATE_180;
3365         case DRM_ROTATE_270:
3366                 return PLANE_CTL_ROTATE_90;
3367         default:
3368                 MISSING_CASE(rotation);
3369         }
3370
3371         return 0;
3372 }
3373
3374 static void skylake_update_primary_plane(struct drm_plane *plane,
3375                                          const struct intel_crtc_state *crtc_state,
3376                                          const struct intel_plane_state *plane_state)
3377 {
3378         struct drm_device *dev = plane->dev;
3379         struct drm_i915_private *dev_priv = to_i915(dev);
3380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3381         struct drm_framebuffer *fb = plane_state->base.fb;
3382         enum plane_id plane_id = to_intel_plane(plane)->id;
3383         enum pipe pipe = to_intel_plane(plane)->pipe;
3384         u32 plane_ctl;
3385         unsigned int rotation = plane_state->base.rotation;
3386         u32 stride = skl_plane_stride(fb, 0, rotation);
3387         u32 surf_addr = plane_state->main.offset;
3388         int scaler_id = plane_state->scaler_id;
3389         int src_x = plane_state->main.x;
3390         int src_y = plane_state->main.y;
3391         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3392         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3393         int dst_x = plane_state->base.dst.x1;
3394         int dst_y = plane_state->base.dst.y1;
3395         int dst_w = drm_rect_width(&plane_state->base.dst);
3396         int dst_h = drm_rect_height(&plane_state->base.dst);
3397
3398         plane_ctl = PLANE_CTL_ENABLE |
3399                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3400                     PLANE_CTL_PIPE_CSC_ENABLE;
3401
3402         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3403         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3404         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3405         plane_ctl |= skl_plane_ctl_rotation(rotation);
3406
3407         /* Sizes are 0 based */
3408         src_w--;
3409         src_h--;
3410         dst_w--;
3411         dst_h--;
3412
3413         intel_crtc->dspaddr_offset = surf_addr;
3414
3415         intel_crtc->adjusted_x = src_x;
3416         intel_crtc->adjusted_y = src_y;
3417
3418         I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
3419         I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3420         I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
3421         I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3422
3423         if (scaler_id >= 0) {
3424                 uint32_t ps_ctrl = 0;
3425
3426                 WARN_ON(!dst_w || !dst_h);
3427                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3428                         crtc_state->scaler_state.scalers[scaler_id].mode;
3429                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3430                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3431                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3432                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3433                 I915_WRITE(PLANE_POS(pipe, plane_id), 0);
3434         } else {
3435                 I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3436         }
3437
3438         I915_WRITE(PLANE_SURF(pipe, plane_id),
3439                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
3440
3441         POSTING_READ(PLANE_SURF(pipe, plane_id));
3442 }
3443
3444 static void skylake_disable_primary_plane(struct drm_plane *primary,
3445                                           struct drm_crtc *crtc)
3446 {
3447         struct drm_device *dev = crtc->dev;
3448         struct drm_i915_private *dev_priv = to_i915(dev);
3449         enum plane_id plane_id = to_intel_plane(primary)->id;
3450         enum pipe pipe = to_intel_plane(primary)->pipe;
3451
3452         I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
3453         I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
3454         POSTING_READ(PLANE_SURF(pipe, plane_id));
3455 }
3456
3457 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3458 static int
3459 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3460                            int x, int y, enum mode_set_atomic state)
3461 {
3462         /* Support for kgdboc is disabled, this needs a major rework. */
3463         DRM_ERROR("legacy panic handler not supported any more.\n");
3464
3465         return -ENODEV;
3466 }
3467
3468 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3469 {
3470         struct intel_crtc *crtc;
3471
3472         for_each_intel_crtc(&dev_priv->drm, crtc)
3473                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3474 }
3475
3476 static void intel_update_primary_planes(struct drm_device *dev)
3477 {
3478         struct drm_crtc *crtc;
3479
3480         for_each_crtc(dev, crtc) {
3481                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3482                 struct intel_plane_state *plane_state =
3483                         to_intel_plane_state(plane->base.state);
3484
3485                 if (plane_state->base.visible)
3486                         plane->update_plane(&plane->base,
3487                                             to_intel_crtc_state(crtc->state),
3488                                             plane_state);
3489         }
3490 }
3491
3492 static int
3493 __intel_display_resume(struct drm_device *dev,
3494                        struct drm_atomic_state *state)
3495 {
3496         struct drm_crtc_state *crtc_state;
3497         struct drm_crtc *crtc;
3498         int i, ret;
3499
3500         intel_modeset_setup_hw_state(dev);
3501         i915_redisable_vga(to_i915(dev));
3502
3503         if (!state)
3504                 return 0;
3505
3506         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3507                 /*
3508                  * Force recalculation even if we restore
3509                  * current state. With fast modeset this may not result
3510                  * in a modeset when the state is compatible.
3511                  */
3512                 crtc_state->mode_changed = true;
3513         }
3514
3515         /* ignore any reset values/BIOS leftovers in the WM registers */
3516         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3517
3518         ret = drm_atomic_commit(state);
3519
3520         WARN_ON(ret == -EDEADLK);
3521         return ret;
3522 }
3523
3524 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3525 {
3526         return intel_has_gpu_reset(dev_priv) &&
3527                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3528 }
3529
3530 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3531 {
3532         struct drm_device *dev = &dev_priv->drm;
3533         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3534         struct drm_atomic_state *state;
3535         int ret;
3536
3537         /*
3538          * Need mode_config.mutex so that we don't
3539          * trample ongoing ->detect() and whatnot.
3540          */
3541         mutex_lock(&dev->mode_config.mutex);
3542         drm_modeset_acquire_init(ctx, 0);
3543         while (1) {
3544                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3545                 if (ret != -EDEADLK)
3546                         break;
3547
3548                 drm_modeset_backoff(ctx);
3549         }
3550
3551         /* reset doesn't touch the display, but flips might get nuked anyway, */
3552         if (!i915.force_reset_modeset_test &&
3553             !gpu_reset_clobbers_display(dev_priv))
3554                 return;
3555
3556         /*
3557          * Disabling the crtcs gracefully seems nicer. Also the
3558          * g33 docs say we should at least disable all the planes.
3559          */
3560         state = drm_atomic_helper_duplicate_state(dev, ctx);
3561         if (IS_ERR(state)) {
3562                 ret = PTR_ERR(state);
3563                 state = NULL;
3564                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3565                 goto err;
3566         }
3567
3568         ret = drm_atomic_helper_disable_all(dev, ctx);
3569         if (ret) {
3570                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3571                 goto err;
3572         }
3573
3574         dev_priv->modeset_restore_state = state;
3575         state->acquire_ctx = ctx;
3576         return;
3577
3578 err:
3579         drm_atomic_state_put(state);
3580 }
3581
3582 void intel_finish_reset(struct drm_i915_private *dev_priv)
3583 {
3584         struct drm_device *dev = &dev_priv->drm;
3585         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3586         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3587         int ret;
3588
3589         /*
3590          * Flips in the rings will be nuked by the reset,
3591          * so complete all pending flips so that user space
3592          * will get its events and not get stuck.
3593          */
3594         intel_complete_page_flips(dev_priv);
3595
3596         dev_priv->modeset_restore_state = NULL;
3597
3598         /* reset doesn't touch the display */
3599         if (!gpu_reset_clobbers_display(dev_priv)) {
3600                 if (!state) {
3601                         /*
3602                          * Flips in the rings have been nuked by the reset,
3603                          * so update the base address of all primary
3604                          * planes to the the last fb to make sure we're
3605                          * showing the correct fb after a reset.
3606                          *
3607                          * FIXME: Atomic will make this obsolete since we won't schedule
3608                          * CS-based flips (which might get lost in gpu resets) any more.
3609                          */
3610                         intel_update_primary_planes(dev);
3611                 } else {
3612                         ret = __intel_display_resume(dev, state);
3613                         if (ret)
3614                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3615                 }
3616         } else {
3617                 /*
3618                  * The display has been reset as well,
3619                  * so need a full re-initialization.
3620                  */
3621                 intel_runtime_pm_disable_interrupts(dev_priv);
3622                 intel_runtime_pm_enable_interrupts(dev_priv);
3623
3624                 intel_pps_unlock_regs_wa(dev_priv);
3625                 intel_modeset_init_hw(dev);
3626
3627                 spin_lock_irq(&dev_priv->irq_lock);
3628                 if (dev_priv->display.hpd_irq_setup)
3629                         dev_priv->display.hpd_irq_setup(dev_priv);
3630                 spin_unlock_irq(&dev_priv->irq_lock);
3631
3632                 ret = __intel_display_resume(dev, state);
3633                 if (ret)
3634                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3635
3636                 intel_hpd_init(dev_priv);
3637         }
3638
3639         if (state)
3640                 drm_atomic_state_put(state);
3641         drm_modeset_drop_locks(ctx);
3642         drm_modeset_acquire_fini(ctx);
3643         mutex_unlock(&dev->mode_config.mutex);
3644 }
3645
3646 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3647 {
3648         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3649
3650         if (i915_reset_in_progress(error))
3651                 return true;
3652
3653         if (crtc->reset_count != i915_reset_count(error))
3654                 return true;
3655
3656         return false;
3657 }
3658
3659 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3660 {
3661         struct drm_device *dev = crtc->dev;
3662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3663         bool pending;
3664
3665         if (abort_flip_on_reset(intel_crtc))
3666                 return false;
3667
3668         spin_lock_irq(&dev->event_lock);
3669         pending = to_intel_crtc(crtc)->flip_work != NULL;
3670         spin_unlock_irq(&dev->event_lock);
3671
3672         return pending;
3673 }
3674
3675 static void intel_update_pipe_config(struct intel_crtc *crtc,
3676                                      struct intel_crtc_state *old_crtc_state)
3677 {
3678         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3679         struct intel_crtc_state *pipe_config =
3680                 to_intel_crtc_state(crtc->base.state);
3681
3682         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3683         crtc->base.mode = crtc->base.state->mode;
3684
3685         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3686                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3687                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3688
3689         /*
3690          * Update pipe size and adjust fitter if needed: the reason for this is
3691          * that in compute_mode_changes we check the native mode (not the pfit
3692          * mode) to see if we can flip rather than do a full mode set. In the
3693          * fastboot case, we'll flip, but if we don't update the pipesrc and
3694          * pfit state, we'll end up with a big fb scanned out into the wrong
3695          * sized surface.
3696          */
3697
3698         I915_WRITE(PIPESRC(crtc->pipe),
3699                    ((pipe_config->pipe_src_w - 1) << 16) |
3700                    (pipe_config->pipe_src_h - 1));
3701
3702         /* on skylake this is done by detaching scalers */
3703         if (INTEL_GEN(dev_priv) >= 9) {
3704                 skl_detach_scalers(crtc);
3705
3706                 if (pipe_config->pch_pfit.enabled)
3707                         skylake_pfit_enable(crtc);
3708         } else if (HAS_PCH_SPLIT(dev_priv)) {
3709                 if (pipe_config->pch_pfit.enabled)
3710                         ironlake_pfit_enable(crtc);
3711                 else if (old_crtc_state->pch_pfit.enabled)
3712                         ironlake_pfit_disable(crtc, true);
3713         }
3714 }
3715
3716 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3717 {
3718         struct drm_device *dev = crtc->dev;
3719         struct drm_i915_private *dev_priv = to_i915(dev);
3720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3721         int pipe = intel_crtc->pipe;
3722         i915_reg_t reg;
3723         u32 temp;
3724
3725         /* enable normal train */
3726         reg = FDI_TX_CTL(pipe);
3727         temp = I915_READ(reg);
3728         if (IS_IVYBRIDGE(dev_priv)) {
3729                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3730                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3731         } else {
3732                 temp &= ~FDI_LINK_TRAIN_NONE;
3733                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3734         }
3735         I915_WRITE(reg, temp);
3736
3737         reg = FDI_RX_CTL(pipe);
3738         temp = I915_READ(reg);
3739         if (HAS_PCH_CPT(dev_priv)) {
3740                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3741                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3742         } else {
3743                 temp &= ~FDI_LINK_TRAIN_NONE;
3744                 temp |= FDI_LINK_TRAIN_NONE;
3745         }
3746         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3747
3748         /* wait one idle pattern time */
3749         POSTING_READ(reg);
3750         udelay(1000);
3751
3752         /* IVB wants error correction enabled */
3753         if (IS_IVYBRIDGE(dev_priv))
3754                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3755                            FDI_FE_ERRC_ENABLE);
3756 }
3757
3758 /* The FDI link training functions for ILK/Ibexpeak. */
3759 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3760 {
3761         struct drm_device *dev = crtc->dev;
3762         struct drm_i915_private *dev_priv = to_i915(dev);
3763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3764         int pipe = intel_crtc->pipe;
3765         i915_reg_t reg;
3766         u32 temp, tries;
3767
3768         /* FDI needs bits from pipe first */
3769         assert_pipe_enabled(dev_priv, pipe);
3770
3771         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3772            for train result */
3773         reg = FDI_RX_IMR(pipe);
3774         temp = I915_READ(reg);
3775         temp &= ~FDI_RX_SYMBOL_LOCK;
3776         temp &= ~FDI_RX_BIT_LOCK;
3777         I915_WRITE(reg, temp);
3778         I915_READ(reg);
3779         udelay(150);
3780
3781         /* enable CPU FDI TX and PCH FDI RX */
3782         reg = FDI_TX_CTL(pipe);
3783         temp = I915_READ(reg);
3784         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3785         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3786         temp &= ~FDI_LINK_TRAIN_NONE;
3787         temp |= FDI_LINK_TRAIN_PATTERN_1;
3788         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3789
3790         reg = FDI_RX_CTL(pipe);
3791         temp = I915_READ(reg);
3792         temp &= ~FDI_LINK_TRAIN_NONE;
3793         temp |= FDI_LINK_TRAIN_PATTERN_1;
3794         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3795
3796         POSTING_READ(reg);
3797         udelay(150);
3798
3799         /* Ironlake workaround, enable clock pointer after FDI enable*/
3800         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3801         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3802                    FDI_RX_PHASE_SYNC_POINTER_EN);
3803
3804         reg = FDI_RX_IIR(pipe);
3805         for (tries = 0; tries < 5; tries++) {
3806                 temp = I915_READ(reg);
3807                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3808
3809                 if ((temp & FDI_RX_BIT_LOCK)) {
3810                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3811                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3812                         break;
3813                 }
3814         }
3815         if (tries == 5)
3816                 DRM_ERROR("FDI train 1 fail!\n");
3817
3818         /* Train 2 */
3819         reg = FDI_TX_CTL(pipe);
3820         temp = I915_READ(reg);
3821         temp &= ~FDI_LINK_TRAIN_NONE;
3822         temp |= FDI_LINK_TRAIN_PATTERN_2;
3823         I915_WRITE(reg, temp);
3824
3825         reg = FDI_RX_CTL(pipe);
3826         temp = I915_READ(reg);
3827         temp &= ~FDI_LINK_TRAIN_NONE;
3828         temp |= FDI_LINK_TRAIN_PATTERN_2;
3829         I915_WRITE(reg, temp);
3830
3831         POSTING_READ(reg);
3832         udelay(150);
3833
3834         reg = FDI_RX_IIR(pipe);
3835         for (tries = 0; tries < 5; tries++) {
3836                 temp = I915_READ(reg);
3837                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3838
3839                 if (temp & FDI_RX_SYMBOL_LOCK) {
3840                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3841                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3842                         break;
3843                 }
3844         }
3845         if (tries == 5)
3846                 DRM_ERROR("FDI train 2 fail!\n");
3847
3848         DRM_DEBUG_KMS("FDI train done\n");
3849
3850 }
3851
3852 static const int snb_b_fdi_train_param[] = {
3853         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3854         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3855         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3856         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3857 };
3858
3859 /* The FDI link training functions for SNB/Cougarpoint. */
3860 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3861 {
3862         struct drm_device *dev = crtc->dev;
3863         struct drm_i915_private *dev_priv = to_i915(dev);
3864         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3865         int pipe = intel_crtc->pipe;
3866         i915_reg_t reg;
3867         u32 temp, i, retry;
3868
3869         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3870            for train result */
3871         reg = FDI_RX_IMR(pipe);
3872         temp = I915_READ(reg);
3873         temp &= ~FDI_RX_SYMBOL_LOCK;
3874         temp &= ~FDI_RX_BIT_LOCK;
3875         I915_WRITE(reg, temp);
3876
3877         POSTING_READ(reg);
3878         udelay(150);
3879
3880         /* enable CPU FDI TX and PCH FDI RX */
3881         reg = FDI_TX_CTL(pipe);
3882         temp = I915_READ(reg);
3883         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3884         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3885         temp &= ~FDI_LINK_TRAIN_NONE;
3886         temp |= FDI_LINK_TRAIN_PATTERN_1;
3887         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3888         /* SNB-B */
3889         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3890         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3891
3892         I915_WRITE(FDI_RX_MISC(pipe),
3893                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3894
3895         reg = FDI_RX_CTL(pipe);
3896         temp = I915_READ(reg);
3897         if (HAS_PCH_CPT(dev_priv)) {
3898                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3899                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3900         } else {
3901                 temp &= ~FDI_LINK_TRAIN_NONE;
3902                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3903         }
3904         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3905
3906         POSTING_READ(reg);
3907         udelay(150);
3908
3909         for (i = 0; i < 4; i++) {
3910                 reg = FDI_TX_CTL(pipe);
3911                 temp = I915_READ(reg);
3912                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3913                 temp |= snb_b_fdi_train_param[i];
3914                 I915_WRITE(reg, temp);
3915
3916                 POSTING_READ(reg);
3917                 udelay(500);
3918
3919                 for (retry = 0; retry < 5; retry++) {
3920                         reg = FDI_RX_IIR(pipe);
3921                         temp = I915_READ(reg);
3922                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3923                         if (temp & FDI_RX_BIT_LOCK) {
3924                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3925                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3926                                 break;
3927                         }
3928                         udelay(50);
3929                 }
3930                 if (retry < 5)
3931                         break;
3932         }
3933         if (i == 4)
3934                 DRM_ERROR("FDI train 1 fail!\n");
3935
3936         /* Train 2 */
3937         reg = FDI_TX_CTL(pipe);
3938         temp = I915_READ(reg);
3939         temp &= ~FDI_LINK_TRAIN_NONE;
3940         temp |= FDI_LINK_TRAIN_PATTERN_2;
3941         if (IS_GEN6(dev_priv)) {
3942                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3943                 /* SNB-B */
3944                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3945         }
3946         I915_WRITE(reg, temp);
3947
3948         reg = FDI_RX_CTL(pipe);
3949         temp = I915_READ(reg);
3950         if (HAS_PCH_CPT(dev_priv)) {
3951                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3952                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3953         } else {
3954                 temp &= ~FDI_LINK_TRAIN_NONE;
3955                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3956         }
3957         I915_WRITE(reg, temp);
3958
3959         POSTING_READ(reg);
3960         udelay(150);
3961
3962         for (i = 0; i < 4; i++) {
3963                 reg = FDI_TX_CTL(pipe);
3964                 temp = I915_READ(reg);
3965                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3966                 temp |= snb_b_fdi_train_param[i];
3967                 I915_WRITE(reg, temp);
3968
3969                 POSTING_READ(reg);
3970                 udelay(500);
3971
3972                 for (retry = 0; retry < 5; retry++) {
3973                         reg = FDI_RX_IIR(pipe);
3974                         temp = I915_READ(reg);
3975                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3976                         if (temp & FDI_RX_SYMBOL_LOCK) {
3977                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3978                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3979                                 break;
3980                         }
3981                         udelay(50);
3982                 }
3983                 if (retry < 5)
3984                         break;
3985         }
3986         if (i == 4)
3987                 DRM_ERROR("FDI train 2 fail!\n");
3988
3989         DRM_DEBUG_KMS("FDI train done.\n");
3990 }
3991
3992 /* Manual link training for Ivy Bridge A0 parts */
3993 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3994 {
3995         struct drm_device *dev = crtc->dev;
3996         struct drm_i915_private *dev_priv = to_i915(dev);
3997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3998         int pipe = intel_crtc->pipe;
3999         i915_reg_t reg;
4000         u32 temp, i, j;
4001
4002         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4003            for train result */
4004         reg = FDI_RX_IMR(pipe);
4005         temp = I915_READ(reg);
4006         temp &= ~FDI_RX_SYMBOL_LOCK;
4007         temp &= ~FDI_RX_BIT_LOCK;
4008         I915_WRITE(reg, temp);
4009
4010         POSTING_READ(reg);
4011         udelay(150);
4012
4013         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4014                       I915_READ(FDI_RX_IIR(pipe)));
4015
4016         /* Try each vswing and preemphasis setting twice before moving on */
4017         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4018                 /* disable first in case we need to retry */
4019                 reg = FDI_TX_CTL(pipe);
4020                 temp = I915_READ(reg);
4021                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4022                 temp &= ~FDI_TX_ENABLE;
4023                 I915_WRITE(reg, temp);
4024
4025                 reg = FDI_RX_CTL(pipe);
4026                 temp = I915_READ(reg);
4027                 temp &= ~FDI_LINK_TRAIN_AUTO;
4028                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4029                 temp &= ~FDI_RX_ENABLE;
4030                 I915_WRITE(reg, temp);
4031
4032                 /* enable CPU FDI TX and PCH FDI RX */
4033                 reg = FDI_TX_CTL(pipe);
4034                 temp = I915_READ(reg);
4035                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4036                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4037                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4038                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4039                 temp |= snb_b_fdi_train_param[j/2];
4040                 temp |= FDI_COMPOSITE_SYNC;
4041                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4042
4043                 I915_WRITE(FDI_RX_MISC(pipe),
4044                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4045
4046                 reg = FDI_RX_CTL(pipe);
4047                 temp = I915_READ(reg);
4048                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4049                 temp |= FDI_COMPOSITE_SYNC;
4050                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4051
4052                 POSTING_READ(reg);
4053                 udelay(1); /* should be 0.5us */
4054
4055                 for (i = 0; i < 4; i++) {
4056                         reg = FDI_RX_IIR(pipe);
4057                         temp = I915_READ(reg);
4058                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4059
4060                         if (temp & FDI_RX_BIT_LOCK ||
4061                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4062                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4063                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4064                                               i);
4065                                 break;
4066                         }
4067                         udelay(1); /* should be 0.5us */
4068                 }
4069                 if (i == 4) {
4070                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4071                         continue;
4072                 }
4073
4074                 /* Train 2 */
4075                 reg = FDI_TX_CTL(pipe);
4076                 temp = I915_READ(reg);
4077                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4078                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4079                 I915_WRITE(reg, temp);
4080
4081                 reg = FDI_RX_CTL(pipe);
4082                 temp = I915_READ(reg);
4083                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4084                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4085                 I915_WRITE(reg, temp);
4086
4087                 POSTING_READ(reg);
4088                 udelay(2); /* should be 1.5us */
4089
4090                 for (i = 0; i < 4; i++) {
4091                         reg = FDI_RX_IIR(pipe);
4092                         temp = I915_READ(reg);
4093                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4094
4095                         if (temp & FDI_RX_SYMBOL_LOCK ||
4096                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4097                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4098                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4099                                               i);
4100                                 goto train_done;
4101                         }
4102                         udelay(2); /* should be 1.5us */
4103                 }
4104                 if (i == 4)
4105                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4106         }
4107
4108 train_done:
4109         DRM_DEBUG_KMS("FDI train done.\n");
4110 }
4111
4112 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4113 {
4114         struct drm_device *dev = intel_crtc->base.dev;
4115         struct drm_i915_private *dev_priv = to_i915(dev);
4116         int pipe = intel_crtc->pipe;
4117         i915_reg_t reg;
4118         u32 temp;
4119
4120         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4121         reg = FDI_RX_CTL(pipe);
4122         temp = I915_READ(reg);
4123         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4124         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4125         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4126         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4127
4128         POSTING_READ(reg);
4129         udelay(200);
4130
4131         /* Switch from Rawclk to PCDclk */
4132         temp = I915_READ(reg);
4133         I915_WRITE(reg, temp | FDI_PCDCLK);
4134
4135         POSTING_READ(reg);
4136         udelay(200);
4137
4138         /* Enable CPU FDI TX PLL, always on for Ironlake */
4139         reg = FDI_TX_CTL(pipe);
4140         temp = I915_READ(reg);
4141         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4142                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4143
4144                 POSTING_READ(reg);
4145                 udelay(100);
4146         }
4147 }
4148
4149 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4150 {
4151         struct drm_device *dev = intel_crtc->base.dev;
4152         struct drm_i915_private *dev_priv = to_i915(dev);
4153         int pipe = intel_crtc->pipe;
4154         i915_reg_t reg;
4155         u32 temp;
4156
4157         /* Switch from PCDclk to Rawclk */
4158         reg = FDI_RX_CTL(pipe);
4159         temp = I915_READ(reg);
4160         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4161
4162         /* Disable CPU FDI TX PLL */
4163         reg = FDI_TX_CTL(pipe);
4164         temp = I915_READ(reg);
4165         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4166
4167         POSTING_READ(reg);
4168         udelay(100);
4169
4170         reg = FDI_RX_CTL(pipe);
4171         temp = I915_READ(reg);
4172         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4173
4174         /* Wait for the clocks to turn off. */
4175         POSTING_READ(reg);
4176         udelay(100);
4177 }
4178
4179 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4180 {
4181         struct drm_device *dev = crtc->dev;
4182         struct drm_i915_private *dev_priv = to_i915(dev);
4183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4184         int pipe = intel_crtc->pipe;
4185         i915_reg_t reg;
4186         u32 temp;
4187
4188         /* disable CPU FDI tx and PCH FDI rx */
4189         reg = FDI_TX_CTL(pipe);
4190         temp = I915_READ(reg);
4191         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4192         POSTING_READ(reg);
4193
4194         reg = FDI_RX_CTL(pipe);
4195         temp = I915_READ(reg);
4196         temp &= ~(0x7 << 16);
4197         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4198         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4199
4200         POSTING_READ(reg);
4201         udelay(100);
4202
4203         /* Ironlake workaround, disable clock pointer after downing FDI */
4204         if (HAS_PCH_IBX(dev_priv))
4205                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4206
4207         /* still set train pattern 1 */
4208         reg = FDI_TX_CTL(pipe);
4209         temp = I915_READ(reg);
4210         temp &= ~FDI_LINK_TRAIN_NONE;
4211         temp |= FDI_LINK_TRAIN_PATTERN_1;
4212         I915_WRITE(reg, temp);
4213
4214         reg = FDI_RX_CTL(pipe);
4215         temp = I915_READ(reg);
4216         if (HAS_PCH_CPT(dev_priv)) {
4217                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4218                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4219         } else {
4220                 temp &= ~FDI_LINK_TRAIN_NONE;
4221                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4222         }
4223         /* BPC in FDI rx is consistent with that in PIPECONF */
4224         temp &= ~(0x07 << 16);
4225         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4226         I915_WRITE(reg, temp);
4227
4228         POSTING_READ(reg);
4229         udelay(100);
4230 }
4231
4232 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4233 {
4234         struct intel_crtc *crtc;
4235
4236         /* Note that we don't need to be called with mode_config.lock here
4237          * as our list of CRTC objects is static for the lifetime of the
4238          * device and so cannot disappear as we iterate. Similarly, we can
4239          * happily treat the predicates as racy, atomic checks as userspace
4240          * cannot claim and pin a new fb without at least acquring the
4241          * struct_mutex and so serialising with us.
4242          */
4243         for_each_intel_crtc(&dev_priv->drm, crtc) {
4244                 if (atomic_read(&crtc->unpin_work_count) == 0)
4245                         continue;
4246
4247                 if (crtc->flip_work)
4248                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4249
4250                 return true;
4251         }
4252
4253         return false;
4254 }
4255
4256 static void page_flip_completed(struct intel_crtc *intel_crtc)
4257 {
4258         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4259         struct intel_flip_work *work = intel_crtc->flip_work;
4260
4261         intel_crtc->flip_work = NULL;
4262
4263         if (work->event)
4264                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4265
4266         drm_crtc_vblank_put(&intel_crtc->base);
4267
4268         wake_up_all(&dev_priv->pending_flip_queue);
4269         queue_work(dev_priv->wq, &work->unpin_work);
4270
4271         trace_i915_flip_complete(intel_crtc->plane,
4272                                  work->pending_flip_obj);
4273 }
4274
4275 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4276 {
4277         struct drm_device *dev = crtc->dev;
4278         struct drm_i915_private *dev_priv = to_i915(dev);
4279         long ret;
4280
4281         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4282
4283         ret = wait_event_interruptible_timeout(
4284                                         dev_priv->pending_flip_queue,
4285                                         !intel_crtc_has_pending_flip(crtc),
4286                                         60*HZ);
4287
4288         if (ret < 0)
4289                 return ret;
4290
4291         if (ret == 0) {
4292                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4293                 struct intel_flip_work *work;
4294
4295                 spin_lock_irq(&dev->event_lock);
4296                 work = intel_crtc->flip_work;
4297                 if (work && !is_mmio_work(work)) {
4298                         WARN_ONCE(1, "Removing stuck page flip\n");
4299                         page_flip_completed(intel_crtc);
4300                 }
4301                 spin_unlock_irq(&dev->event_lock);
4302         }
4303
4304         return 0;
4305 }
4306
4307 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4308 {
4309         u32 temp;
4310
4311         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4312
4313         mutex_lock(&dev_priv->sb_lock);
4314
4315         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4316         temp |= SBI_SSCCTL_DISABLE;
4317         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4318
4319         mutex_unlock(&dev_priv->sb_lock);
4320 }
4321
4322 /* Program iCLKIP clock to the desired frequency */
4323 static void lpt_program_iclkip(struct drm_crtc *crtc)
4324 {
4325         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4326         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4327         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4328         u32 temp;
4329
4330         lpt_disable_iclkip(dev_priv);
4331
4332         /* The iCLK virtual clock root frequency is in MHz,
4333          * but the adjusted_mode->crtc_clock in in KHz. To get the
4334          * divisors, it is necessary to divide one by another, so we
4335          * convert the virtual clock precision to KHz here for higher
4336          * precision.
4337          */
4338         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4339                 u32 iclk_virtual_root_freq = 172800 * 1000;
4340                 u32 iclk_pi_range = 64;
4341                 u32 desired_divisor;
4342
4343                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4344                                                     clock << auxdiv);
4345                 divsel = (desired_divisor / iclk_pi_range) - 2;
4346                 phaseinc = desired_divisor % iclk_pi_range;
4347
4348                 /*
4349                  * Near 20MHz is a corner case which is
4350                  * out of range for the 7-bit divisor
4351                  */
4352                 if (divsel <= 0x7f)
4353                         break;
4354         }
4355
4356         /* This should not happen with any sane values */
4357         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4358                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4359         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4360                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4361
4362         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4363                         clock,
4364                         auxdiv,
4365                         divsel,
4366                         phasedir,
4367                         phaseinc);
4368
4369         mutex_lock(&dev_priv->sb_lock);
4370
4371         /* Program SSCDIVINTPHASE6 */
4372         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4373         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4374         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4375         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4376         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4377         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4378         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4379         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4380
4381         /* Program SSCAUXDIV */
4382         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4383         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4384         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4385         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4386
4387         /* Enable modulator and associated divider */
4388         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4389         temp &= ~SBI_SSCCTL_DISABLE;
4390         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4391
4392         mutex_unlock(&dev_priv->sb_lock);
4393
4394         /* Wait for initialization time */
4395         udelay(24);
4396
4397         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4398 }
4399
4400 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4401 {
4402         u32 divsel, phaseinc, auxdiv;
4403         u32 iclk_virtual_root_freq = 172800 * 1000;
4404         u32 iclk_pi_range = 64;
4405         u32 desired_divisor;
4406         u32 temp;
4407
4408         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4409                 return 0;
4410
4411         mutex_lock(&dev_priv->sb_lock);
4412
4413         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4414         if (temp & SBI_SSCCTL_DISABLE) {
4415                 mutex_unlock(&dev_priv->sb_lock);
4416                 return 0;
4417         }
4418
4419         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4420         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4421                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4422         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4423                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4424
4425         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4426         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4427                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4428
4429         mutex_unlock(&dev_priv->sb_lock);
4430
4431         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4432
4433         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4434                                  desired_divisor << auxdiv);
4435 }
4436
4437 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4438                                                 enum pipe pch_transcoder)
4439 {
4440         struct drm_device *dev = crtc->base.dev;
4441         struct drm_i915_private *dev_priv = to_i915(dev);
4442         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4443
4444         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4445                    I915_READ(HTOTAL(cpu_transcoder)));
4446         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4447                    I915_READ(HBLANK(cpu_transcoder)));
4448         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4449                    I915_READ(HSYNC(cpu_transcoder)));
4450
4451         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4452                    I915_READ(VTOTAL(cpu_transcoder)));
4453         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4454                    I915_READ(VBLANK(cpu_transcoder)));
4455         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4456                    I915_READ(VSYNC(cpu_transcoder)));
4457         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4458                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4459 }
4460
4461 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4462 {
4463         struct drm_i915_private *dev_priv = to_i915(dev);
4464         uint32_t temp;
4465
4466         temp = I915_READ(SOUTH_CHICKEN1);
4467         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4468                 return;
4469
4470         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4471         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4472
4473         temp &= ~FDI_BC_BIFURCATION_SELECT;
4474         if (enable)
4475                 temp |= FDI_BC_BIFURCATION_SELECT;
4476
4477         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4478         I915_WRITE(SOUTH_CHICKEN1, temp);
4479         POSTING_READ(SOUTH_CHICKEN1);
4480 }
4481
4482 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4483 {
4484         struct drm_device *dev = intel_crtc->base.dev;
4485
4486         switch (intel_crtc->pipe) {
4487         case PIPE_A:
4488                 break;
4489         case PIPE_B:
4490                 if (intel_crtc->config->fdi_lanes > 2)
4491                         cpt_set_fdi_bc_bifurcation(dev, false);
4492                 else
4493                         cpt_set_fdi_bc_bifurcation(dev, true);
4494
4495                 break;
4496         case PIPE_C:
4497                 cpt_set_fdi_bc_bifurcation(dev, true);
4498
4499                 break;
4500         default:
4501                 BUG();
4502         }
4503 }
4504
4505 /* Return which DP Port should be selected for Transcoder DP control */
4506 static enum port
4507 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4508 {
4509         struct drm_device *dev = crtc->dev;
4510         struct intel_encoder *encoder;
4511
4512         for_each_encoder_on_crtc(dev, crtc, encoder) {
4513                 if (encoder->type == INTEL_OUTPUT_DP ||
4514                     encoder->type == INTEL_OUTPUT_EDP)
4515                         return enc_to_dig_port(&encoder->base)->port;
4516         }
4517
4518         return -1;
4519 }
4520
4521 /*
4522  * Enable PCH resources required for PCH ports:
4523  *   - PCH PLLs
4524  *   - FDI training & RX/TX
4525  *   - update transcoder timings
4526  *   - DP transcoding bits
4527  *   - transcoder
4528  */
4529 static void ironlake_pch_enable(struct drm_crtc *crtc)
4530 {
4531         struct drm_device *dev = crtc->dev;
4532         struct drm_i915_private *dev_priv = to_i915(dev);
4533         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4534         int pipe = intel_crtc->pipe;
4535         u32 temp;
4536
4537         assert_pch_transcoder_disabled(dev_priv, pipe);
4538
4539         if (IS_IVYBRIDGE(dev_priv))
4540                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4541
4542         /* Write the TU size bits before fdi link training, so that error
4543          * detection works. */
4544         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4545                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4546
4547         /* For PCH output, training FDI link */
4548         dev_priv->display.fdi_link_train(crtc);
4549
4550         /* We need to program the right clock selection before writing the pixel
4551          * mutliplier into the DPLL. */
4552         if (HAS_PCH_CPT(dev_priv)) {
4553                 u32 sel;
4554
4555                 temp = I915_READ(PCH_DPLL_SEL);
4556                 temp |= TRANS_DPLL_ENABLE(pipe);
4557                 sel = TRANS_DPLLB_SEL(pipe);
4558                 if (intel_crtc->config->shared_dpll ==
4559                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4560                         temp |= sel;
4561                 else
4562                         temp &= ~sel;
4563                 I915_WRITE(PCH_DPLL_SEL, temp);
4564         }
4565
4566         /* XXX: pch pll's can be enabled any time before we enable the PCH
4567          * transcoder, and we actually should do this to not upset any PCH
4568          * transcoder that already use the clock when we share it.
4569          *
4570          * Note that enable_shared_dpll tries to do the right thing, but
4571          * get_shared_dpll unconditionally resets the pll - we need that to have
4572          * the right LVDS enable sequence. */
4573         intel_enable_shared_dpll(intel_crtc);
4574
4575         /* set transcoder timing, panel must allow it */
4576         assert_panel_unlocked(dev_priv, pipe);
4577         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4578
4579         intel_fdi_normal_train(crtc);
4580
4581         /* For PCH DP, enable TRANS_DP_CTL */
4582         if (HAS_PCH_CPT(dev_priv) &&
4583             intel_crtc_has_dp_encoder(intel_crtc->config)) {
4584                 const struct drm_display_mode *adjusted_mode =
4585                         &intel_crtc->config->base.adjusted_mode;
4586                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4587                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4588                 temp = I915_READ(reg);
4589                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4590                           TRANS_DP_SYNC_MASK |
4591                           TRANS_DP_BPC_MASK);
4592                 temp |= TRANS_DP_OUTPUT_ENABLE;
4593                 temp |= bpc << 9; /* same format but at 11:9 */
4594
4595                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4596                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4597                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4598                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4599
4600                 switch (intel_trans_dp_port_sel(crtc)) {
4601                 case PORT_B:
4602                         temp |= TRANS_DP_PORT_SEL_B;
4603                         break;
4604                 case PORT_C:
4605                         temp |= TRANS_DP_PORT_SEL_C;
4606                         break;
4607                 case PORT_D:
4608                         temp |= TRANS_DP_PORT_SEL_D;
4609                         break;
4610                 default:
4611                         BUG();
4612                 }
4613
4614                 I915_WRITE(reg, temp);
4615         }
4616
4617         ironlake_enable_pch_transcoder(dev_priv, pipe);
4618 }
4619
4620 static void lpt_pch_enable(struct drm_crtc *crtc)
4621 {
4622         struct drm_device *dev = crtc->dev;
4623         struct drm_i915_private *dev_priv = to_i915(dev);
4624         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4625         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4626
4627         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4628
4629         lpt_program_iclkip(crtc);
4630
4631         /* Set transcoder timing. */
4632         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4633
4634         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4635 }
4636
4637 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4638 {
4639         struct drm_i915_private *dev_priv = to_i915(dev);
4640         i915_reg_t dslreg = PIPEDSL(pipe);
4641         u32 temp;
4642
4643         temp = I915_READ(dslreg);
4644         udelay(500);
4645         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4646                 if (wait_for(I915_READ(dslreg) != temp, 5))
4647                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4648         }
4649 }
4650
4651 static int
4652 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4653                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4654                   int src_w, int src_h, int dst_w, int dst_h)
4655 {
4656         struct intel_crtc_scaler_state *scaler_state =
4657                 &crtc_state->scaler_state;
4658         struct intel_crtc *intel_crtc =
4659                 to_intel_crtc(crtc_state->base.crtc);
4660         int need_scaling;
4661
4662         need_scaling = drm_rotation_90_or_270(rotation) ?
4663                 (src_h != dst_w || src_w != dst_h):
4664                 (src_w != dst_w || src_h != dst_h);
4665
4666         /*
4667          * if plane is being disabled or scaler is no more required or force detach
4668          *  - free scaler binded to this plane/crtc
4669          *  - in order to do this, update crtc->scaler_usage
4670          *
4671          * Here scaler state in crtc_state is set free so that
4672          * scaler can be assigned to other user. Actual register
4673          * update to free the scaler is done in plane/panel-fit programming.
4674          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4675          */
4676         if (force_detach || !need_scaling) {
4677                 if (*scaler_id >= 0) {
4678                         scaler_state->scaler_users &= ~(1 << scaler_user);
4679                         scaler_state->scalers[*scaler_id].in_use = 0;
4680
4681                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4682                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4683                                 intel_crtc->pipe, scaler_user, *scaler_id,
4684                                 scaler_state->scaler_users);
4685                         *scaler_id = -1;
4686                 }
4687                 return 0;
4688         }
4689
4690         /* range checks */
4691         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4692                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4693
4694                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4695                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4696                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4697                         "size is out of scaler range\n",
4698                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4699                 return -EINVAL;
4700         }
4701
4702         /* mark this plane as a scaler user in crtc_state */
4703         scaler_state->scaler_users |= (1 << scaler_user);
4704         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4705                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4706                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4707                 scaler_state->scaler_users);
4708
4709         return 0;
4710 }
4711
4712 /**
4713  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4714  *
4715  * @state: crtc's scaler state
4716  *
4717  * Return
4718  *     0 - scaler_usage updated successfully
4719  *    error - requested scaling cannot be supported or other error condition
4720  */
4721 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4722 {
4723         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4724
4725         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4726                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4727                 state->pipe_src_w, state->pipe_src_h,
4728                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4729 }
4730
4731 /**
4732  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4733  *
4734  * @state: crtc's scaler state
4735  * @plane_state: atomic plane state to update
4736  *
4737  * Return
4738  *     0 - scaler_usage updated successfully
4739  *    error - requested scaling cannot be supported or other error condition
4740  */
4741 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4742                                    struct intel_plane_state *plane_state)
4743 {
4744
4745         struct intel_plane *intel_plane =
4746                 to_intel_plane(plane_state->base.plane);
4747         struct drm_framebuffer *fb = plane_state->base.fb;
4748         int ret;
4749
4750         bool force_detach = !fb || !plane_state->base.visible;
4751
4752         ret = skl_update_scaler(crtc_state, force_detach,
4753                                 drm_plane_index(&intel_plane->base),
4754                                 &plane_state->scaler_id,
4755                                 plane_state->base.rotation,
4756                                 drm_rect_width(&plane_state->base.src) >> 16,
4757                                 drm_rect_height(&plane_state->base.src) >> 16,
4758                                 drm_rect_width(&plane_state->base.dst),
4759                                 drm_rect_height(&plane_state->base.dst));
4760
4761         if (ret || plane_state->scaler_id < 0)
4762                 return ret;
4763
4764         /* check colorkey */
4765         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4766                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4767                               intel_plane->base.base.id,
4768                               intel_plane->base.name);
4769                 return -EINVAL;
4770         }
4771
4772         /* Check src format */
4773         switch (fb->pixel_format) {
4774         case DRM_FORMAT_RGB565:
4775         case DRM_FORMAT_XBGR8888:
4776         case DRM_FORMAT_XRGB8888:
4777         case DRM_FORMAT_ABGR8888:
4778         case DRM_FORMAT_ARGB8888:
4779         case DRM_FORMAT_XRGB2101010:
4780         case DRM_FORMAT_XBGR2101010:
4781         case DRM_FORMAT_YUYV:
4782         case DRM_FORMAT_YVYU:
4783         case DRM_FORMAT_UYVY:
4784         case DRM_FORMAT_VYUY:
4785                 break;
4786         default:
4787                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4788                               intel_plane->base.base.id, intel_plane->base.name,
4789                               fb->base.id, fb->pixel_format);
4790                 return -EINVAL;
4791         }
4792
4793         return 0;
4794 }
4795
4796 static void skylake_scaler_disable(struct intel_crtc *crtc)
4797 {
4798         int i;
4799
4800         for (i = 0; i < crtc->num_scalers; i++)
4801                 skl_detach_scaler(crtc, i);
4802 }
4803
4804 static void skylake_pfit_enable(struct intel_crtc *crtc)
4805 {
4806         struct drm_device *dev = crtc->base.dev;
4807         struct drm_i915_private *dev_priv = to_i915(dev);
4808         int pipe = crtc->pipe;
4809         struct intel_crtc_scaler_state *scaler_state =
4810                 &crtc->config->scaler_state;
4811
4812         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4813
4814         if (crtc->config->pch_pfit.enabled) {
4815                 int id;
4816
4817                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4818                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4819                         return;
4820                 }
4821
4822                 id = scaler_state->scaler_id;
4823                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4824                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4825                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4826                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4827
4828                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4829         }
4830 }
4831
4832 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4833 {
4834         struct drm_device *dev = crtc->base.dev;
4835         struct drm_i915_private *dev_priv = to_i915(dev);
4836         int pipe = crtc->pipe;
4837
4838         if (crtc->config->pch_pfit.enabled) {
4839                 /* Force use of hard-coded filter coefficients
4840                  * as some pre-programmed values are broken,
4841                  * e.g. x201.
4842                  */
4843                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4844                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4845                                                  PF_PIPE_SEL_IVB(pipe));
4846                 else
4847                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4848                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4849                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4850         }
4851 }
4852
4853 void hsw_enable_ips(struct intel_crtc *crtc)
4854 {
4855         struct drm_device *dev = crtc->base.dev;
4856         struct drm_i915_private *dev_priv = to_i915(dev);
4857
4858         if (!crtc->config->ips_enabled)
4859                 return;
4860
4861         /*
4862          * We can only enable IPS after we enable a plane and wait for a vblank
4863          * This function is called from post_plane_update, which is run after
4864          * a vblank wait.
4865          */
4866
4867         assert_plane_enabled(dev_priv, crtc->plane);
4868         if (IS_BROADWELL(dev_priv)) {
4869                 mutex_lock(&dev_priv->rps.hw_lock);
4870                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4871                 mutex_unlock(&dev_priv->rps.hw_lock);
4872                 /* Quoting Art Runyan: "its not safe to expect any particular
4873                  * value in IPS_CTL bit 31 after enabling IPS through the
4874                  * mailbox." Moreover, the mailbox may return a bogus state,
4875                  * so we need to just enable it and continue on.
4876                  */
4877         } else {
4878                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4879                 /* The bit only becomes 1 in the next vblank, so this wait here
4880                  * is essentially intel_wait_for_vblank. If we don't have this
4881                  * and don't wait for vblanks until the end of crtc_enable, then
4882                  * the HW state readout code will complain that the expected
4883                  * IPS_CTL value is not the one we read. */
4884                 if (intel_wait_for_register(dev_priv,
4885                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4886                                             50))
4887                         DRM_ERROR("Timed out waiting for IPS enable\n");
4888         }
4889 }
4890
4891 void hsw_disable_ips(struct intel_crtc *crtc)
4892 {
4893         struct drm_device *dev = crtc->base.dev;
4894         struct drm_i915_private *dev_priv = to_i915(dev);
4895
4896         if (!crtc->config->ips_enabled)
4897                 return;
4898
4899         assert_plane_enabled(dev_priv, crtc->plane);
4900         if (IS_BROADWELL(dev_priv)) {
4901                 mutex_lock(&dev_priv->rps.hw_lock);
4902                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4903                 mutex_unlock(&dev_priv->rps.hw_lock);
4904                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4905                 if (intel_wait_for_register(dev_priv,
4906                                             IPS_CTL, IPS_ENABLE, 0,
4907                                             42))
4908                         DRM_ERROR("Timed out waiting for IPS disable\n");
4909         } else {
4910                 I915_WRITE(IPS_CTL, 0);
4911                 POSTING_READ(IPS_CTL);
4912         }
4913
4914         /* We need to wait for a vblank before we can disable the plane. */
4915         intel_wait_for_vblank(dev_priv, crtc->pipe);
4916 }
4917
4918 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4919 {
4920         if (intel_crtc->overlay) {
4921                 struct drm_device *dev = intel_crtc->base.dev;
4922                 struct drm_i915_private *dev_priv = to_i915(dev);
4923
4924                 mutex_lock(&dev->struct_mutex);
4925                 dev_priv->mm.interruptible = false;
4926                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4927                 dev_priv->mm.interruptible = true;
4928                 mutex_unlock(&dev->struct_mutex);
4929         }
4930
4931         /* Let userspace switch the overlay on again. In most cases userspace
4932          * has to recompute where to put it anyway.
4933          */
4934 }
4935
4936 /**
4937  * intel_post_enable_primary - Perform operations after enabling primary plane
4938  * @crtc: the CRTC whose primary plane was just enabled
4939  *
4940  * Performs potentially sleeping operations that must be done after the primary
4941  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4942  * called due to an explicit primary plane update, or due to an implicit
4943  * re-enable that is caused when a sprite plane is updated to no longer
4944  * completely hide the primary plane.
4945  */
4946 static void
4947 intel_post_enable_primary(struct drm_crtc *crtc)
4948 {
4949         struct drm_device *dev = crtc->dev;
4950         struct drm_i915_private *dev_priv = to_i915(dev);
4951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4952         int pipe = intel_crtc->pipe;
4953
4954         /*
4955          * FIXME IPS should be fine as long as one plane is
4956          * enabled, but in practice it seems to have problems
4957          * when going from primary only to sprite only and vice
4958          * versa.
4959          */
4960         hsw_enable_ips(intel_crtc);
4961
4962         /*
4963          * Gen2 reports pipe underruns whenever all planes are disabled.
4964          * So don't enable underrun reporting before at least some planes
4965          * are enabled.
4966          * FIXME: Need to fix the logic to work when we turn off all planes
4967          * but leave the pipe running.
4968          */
4969         if (IS_GEN2(dev_priv))
4970                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4971
4972         /* Underruns don't always raise interrupts, so check manually. */
4973         intel_check_cpu_fifo_underruns(dev_priv);
4974         intel_check_pch_fifo_underruns(dev_priv);
4975 }
4976
4977 /* FIXME move all this to pre_plane_update() with proper state tracking */
4978 static void
4979 intel_pre_disable_primary(struct drm_crtc *crtc)
4980 {
4981         struct drm_device *dev = crtc->dev;
4982         struct drm_i915_private *dev_priv = to_i915(dev);
4983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4984         int pipe = intel_crtc->pipe;
4985
4986         /*
4987          * Gen2 reports pipe underruns whenever all planes are disabled.
4988          * So diasble underrun reporting before all the planes get disabled.
4989          * FIXME: Need to fix the logic to work when we turn off all planes
4990          * but leave the pipe running.
4991          */
4992         if (IS_GEN2(dev_priv))
4993                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4994
4995         /*
4996          * FIXME IPS should be fine as long as one plane is
4997          * enabled, but in practice it seems to have problems
4998          * when going from primary only to sprite only and vice
4999          * versa.
5000          */
5001         hsw_disable_ips(intel_crtc);
5002 }
5003
5004 /* FIXME get rid of this and use pre_plane_update */
5005 static void
5006 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5007 {
5008         struct drm_device *dev = crtc->dev;
5009         struct drm_i915_private *dev_priv = to_i915(dev);
5010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5011         int pipe = intel_crtc->pipe;
5012
5013         intel_pre_disable_primary(crtc);
5014
5015         /*
5016          * Vblank time updates from the shadow to live plane control register
5017          * are blocked if the memory self-refresh mode is active at that
5018          * moment. So to make sure the plane gets truly disabled, disable
5019          * first the self-refresh mode. The self-refresh enable bit in turn
5020          * will be checked/applied by the HW only at the next frame start
5021          * event which is after the vblank start event, so we need to have a
5022          * wait-for-vblank between disabling the plane and the pipe.
5023          */
5024         if (HAS_GMCH_DISPLAY(dev_priv) &&
5025             intel_set_memory_cxsr(dev_priv, false))
5026                 intel_wait_for_vblank(dev_priv, pipe);
5027 }
5028
5029 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5030 {
5031         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5032         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5033         struct intel_crtc_state *pipe_config =
5034                 to_intel_crtc_state(crtc->base.state);
5035         struct drm_plane *primary = crtc->base.primary;
5036         struct drm_plane_state *old_pri_state =
5037                 drm_atomic_get_existing_plane_state(old_state, primary);
5038
5039         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5040
5041         crtc->wm.cxsr_allowed = true;
5042
5043         if (pipe_config->update_wm_post && pipe_config->base.active)
5044                 intel_update_watermarks(crtc);
5045
5046         if (old_pri_state) {
5047                 struct intel_plane_state *primary_state =
5048                         to_intel_plane_state(primary->state);
5049                 struct intel_plane_state *old_primary_state =
5050                         to_intel_plane_state(old_pri_state);
5051
5052                 intel_fbc_post_update(crtc);
5053
5054                 if (primary_state->base.visible &&
5055                     (needs_modeset(&pipe_config->base) ||
5056                      !old_primary_state->base.visible))
5057                         intel_post_enable_primary(&crtc->base);
5058         }
5059 }
5060
5061 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5062 {
5063         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5064         struct drm_device *dev = crtc->base.dev;
5065         struct drm_i915_private *dev_priv = to_i915(dev);
5066         struct intel_crtc_state *pipe_config =
5067                 to_intel_crtc_state(crtc->base.state);
5068         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5069         struct drm_plane *primary = crtc->base.primary;
5070         struct drm_plane_state *old_pri_state =
5071                 drm_atomic_get_existing_plane_state(old_state, primary);
5072         bool modeset = needs_modeset(&pipe_config->base);
5073         struct intel_atomic_state *old_intel_state =
5074                 to_intel_atomic_state(old_state);
5075
5076         if (old_pri_state) {
5077                 struct intel_plane_state *primary_state =
5078                         to_intel_plane_state(primary->state);
5079                 struct intel_plane_state *old_primary_state =
5080                         to_intel_plane_state(old_pri_state);
5081
5082                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5083
5084                 if (old_primary_state->base.visible &&
5085                     (modeset || !primary_state->base.visible))
5086                         intel_pre_disable_primary(&crtc->base);
5087         }
5088
5089         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5090                 crtc->wm.cxsr_allowed = false;
5091
5092                 /*
5093                  * Vblank time updates from the shadow to live plane control register
5094                  * are blocked if the memory self-refresh mode is active at that
5095                  * moment. So to make sure the plane gets truly disabled, disable
5096                  * first the self-refresh mode. The self-refresh enable bit in turn
5097                  * will be checked/applied by the HW only at the next frame start
5098                  * event which is after the vblank start event, so we need to have a
5099                  * wait-for-vblank between disabling the plane and the pipe.
5100                  */
5101                 if (old_crtc_state->base.active &&
5102                     intel_set_memory_cxsr(dev_priv, false))
5103                         intel_wait_for_vblank(dev_priv, crtc->pipe);
5104         }
5105
5106         /*
5107          * IVB workaround: must disable low power watermarks for at least
5108          * one frame before enabling scaling.  LP watermarks can be re-enabled
5109          * when scaling is disabled.
5110          *
5111          * WaCxSRDisabledForSpriteScaling:ivb
5112          */
5113         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5114                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5115
5116         /*
5117          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5118          * watermark programming here.
5119          */
5120         if (needs_modeset(&pipe_config->base))
5121                 return;
5122
5123         /*
5124          * For platforms that support atomic watermarks, program the
5125          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5126          * will be the intermediate values that are safe for both pre- and
5127          * post- vblank; when vblank happens, the 'active' values will be set
5128          * to the final 'target' values and we'll do this again to get the
5129          * optimal watermarks.  For gen9+ platforms, the values we program here
5130          * will be the final target values which will get automatically latched
5131          * at vblank time; no further programming will be necessary.
5132          *
5133          * If a platform hasn't been transitioned to atomic watermarks yet,
5134          * we'll continue to update watermarks the old way, if flags tell
5135          * us to.
5136          */
5137         if (dev_priv->display.initial_watermarks != NULL)
5138                 dev_priv->display.initial_watermarks(old_intel_state,
5139                                                      pipe_config);
5140         else if (pipe_config->update_wm_pre)
5141                 intel_update_watermarks(crtc);
5142 }
5143
5144 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5145 {
5146         struct drm_device *dev = crtc->dev;
5147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5148         struct drm_plane *p;
5149         int pipe = intel_crtc->pipe;
5150
5151         intel_crtc_dpms_overlay_disable(intel_crtc);
5152
5153         drm_for_each_plane_mask(p, dev, plane_mask)
5154                 to_intel_plane(p)->disable_plane(p, crtc);
5155
5156         /*
5157          * FIXME: Once we grow proper nuclear flip support out of this we need
5158          * to compute the mask of flip planes precisely. For the time being
5159          * consider this a flip to a NULL plane.
5160          */
5161         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5162 }
5163
5164 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5165                                           struct intel_crtc_state *crtc_state,
5166                                           struct drm_atomic_state *old_state)
5167 {
5168         struct drm_connector_state *old_conn_state;
5169         struct drm_connector *conn;
5170         int i;
5171
5172         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5173                 struct drm_connector_state *conn_state = conn->state;
5174                 struct intel_encoder *encoder =
5175                         to_intel_encoder(conn_state->best_encoder);
5176
5177                 if (conn_state->crtc != crtc)
5178                         continue;
5179
5180                 if (encoder->pre_pll_enable)
5181                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5182         }
5183 }
5184
5185 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5186                                       struct intel_crtc_state *crtc_state,
5187                                       struct drm_atomic_state *old_state)
5188 {
5189         struct drm_connector_state *old_conn_state;
5190         struct drm_connector *conn;
5191         int i;
5192
5193         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5194                 struct drm_connector_state *conn_state = conn->state;
5195                 struct intel_encoder *encoder =
5196                         to_intel_encoder(conn_state->best_encoder);
5197
5198                 if (conn_state->crtc != crtc)
5199                         continue;
5200
5201                 if (encoder->pre_enable)
5202                         encoder->pre_enable(encoder, crtc_state, conn_state);
5203         }
5204 }
5205
5206 static void intel_encoders_enable(struct drm_crtc *crtc,
5207                                   struct intel_crtc_state *crtc_state,
5208                                   struct drm_atomic_state *old_state)
5209 {
5210         struct drm_connector_state *old_conn_state;
5211         struct drm_connector *conn;
5212         int i;
5213
5214         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5215                 struct drm_connector_state *conn_state = conn->state;
5216                 struct intel_encoder *encoder =
5217                         to_intel_encoder(conn_state->best_encoder);
5218
5219                 if (conn_state->crtc != crtc)
5220                         continue;
5221
5222                 encoder->enable(encoder, crtc_state, conn_state);
5223                 intel_opregion_notify_encoder(encoder, true);
5224         }
5225 }
5226
5227 static void intel_encoders_disable(struct drm_crtc *crtc,
5228                                    struct intel_crtc_state *old_crtc_state,
5229                                    struct drm_atomic_state *old_state)
5230 {
5231         struct drm_connector_state *old_conn_state;
5232         struct drm_connector *conn;
5233         int i;
5234
5235         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5236                 struct intel_encoder *encoder =
5237                         to_intel_encoder(old_conn_state->best_encoder);
5238
5239                 if (old_conn_state->crtc != crtc)
5240                         continue;
5241
5242                 intel_opregion_notify_encoder(encoder, false);
5243                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5244         }
5245 }
5246
5247 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5248                                         struct intel_crtc_state *old_crtc_state,
5249                                         struct drm_atomic_state *old_state)
5250 {
5251         struct drm_connector_state *old_conn_state;
5252         struct drm_connector *conn;
5253         int i;
5254
5255         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5256                 struct intel_encoder *encoder =
5257                         to_intel_encoder(old_conn_state->best_encoder);
5258
5259                 if (old_conn_state->crtc != crtc)
5260                         continue;
5261
5262                 if (encoder->post_disable)
5263                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5264         }
5265 }
5266
5267 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5268                                             struct intel_crtc_state *old_crtc_state,
5269                                             struct drm_atomic_state *old_state)
5270 {
5271         struct drm_connector_state *old_conn_state;
5272         struct drm_connector *conn;
5273         int i;
5274
5275         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5276                 struct intel_encoder *encoder =
5277                         to_intel_encoder(old_conn_state->best_encoder);
5278
5279                 if (old_conn_state->crtc != crtc)
5280                         continue;
5281
5282                 if (encoder->post_pll_disable)
5283                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5284         }
5285 }
5286
5287 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5288                                  struct drm_atomic_state *old_state)
5289 {
5290         struct drm_crtc *crtc = pipe_config->base.crtc;
5291         struct drm_device *dev = crtc->dev;
5292         struct drm_i915_private *dev_priv = to_i915(dev);
5293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5294         int pipe = intel_crtc->pipe;
5295         struct intel_atomic_state *old_intel_state =
5296                 to_intel_atomic_state(old_state);
5297
5298         if (WARN_ON(intel_crtc->active))
5299                 return;
5300
5301         /*
5302          * Sometimes spurious CPU pipe underruns happen during FDI
5303          * training, at least with VGA+HDMI cloning. Suppress them.
5304          *
5305          * On ILK we get an occasional spurious CPU pipe underruns
5306          * between eDP port A enable and vdd enable. Also PCH port
5307          * enable seems to result in the occasional CPU pipe underrun.
5308          *
5309          * Spurious PCH underruns also occur during PCH enabling.
5310          */
5311         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5312                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5313         if (intel_crtc->config->has_pch_encoder)
5314                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5315
5316         if (intel_crtc->config->has_pch_encoder)
5317                 intel_prepare_shared_dpll(intel_crtc);
5318
5319         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5320                 intel_dp_set_m_n(intel_crtc, M1_N1);
5321
5322         intel_set_pipe_timings(intel_crtc);
5323         intel_set_pipe_src_size(intel_crtc);
5324
5325         if (intel_crtc->config->has_pch_encoder) {
5326                 intel_cpu_transcoder_set_m_n(intel_crtc,
5327                                      &intel_crtc->config->fdi_m_n, NULL);
5328         }
5329
5330         ironlake_set_pipeconf(crtc);
5331
5332         intel_crtc->active = true;
5333
5334         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5335
5336         if (intel_crtc->config->has_pch_encoder) {
5337                 /* Note: FDI PLL enabling _must_ be done before we enable the
5338                  * cpu pipes, hence this is separate from all the other fdi/pch
5339                  * enabling. */
5340                 ironlake_fdi_pll_enable(intel_crtc);
5341         } else {
5342                 assert_fdi_tx_disabled(dev_priv, pipe);
5343                 assert_fdi_rx_disabled(dev_priv, pipe);
5344         }
5345
5346         ironlake_pfit_enable(intel_crtc);
5347
5348         /*
5349          * On ILK+ LUT must be loaded before the pipe is running but with
5350          * clocks enabled
5351          */
5352         intel_color_load_luts(&pipe_config->base);
5353
5354         if (dev_priv->display.initial_watermarks != NULL)
5355                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5356         intel_enable_pipe(intel_crtc);
5357
5358         if (intel_crtc->config->has_pch_encoder)
5359                 ironlake_pch_enable(crtc);
5360
5361         assert_vblank_disabled(crtc);
5362         drm_crtc_vblank_on(crtc);
5363
5364         intel_encoders_enable(crtc, pipe_config, old_state);
5365
5366         if (HAS_PCH_CPT(dev_priv))
5367                 cpt_verify_modeset(dev, intel_crtc->pipe);
5368
5369         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5370         if (intel_crtc->config->has_pch_encoder)
5371                 intel_wait_for_vblank(dev_priv, pipe);
5372         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5373         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5374 }
5375
5376 /* IPS only exists on ULT machines and is tied to pipe A. */
5377 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5378 {
5379         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5380 }
5381
5382 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5383                                 struct drm_atomic_state *old_state)
5384 {
5385         struct drm_crtc *crtc = pipe_config->base.crtc;
5386         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5388         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5389         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5390         struct intel_atomic_state *old_intel_state =
5391                 to_intel_atomic_state(old_state);
5392
5393         if (WARN_ON(intel_crtc->active))
5394                 return;
5395
5396         if (intel_crtc->config->has_pch_encoder)
5397                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5398                                                       false);
5399
5400         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5401
5402         if (intel_crtc->config->shared_dpll)
5403                 intel_enable_shared_dpll(intel_crtc);
5404
5405         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5406                 intel_dp_set_m_n(intel_crtc, M1_N1);
5407
5408         if (!transcoder_is_dsi(cpu_transcoder))
5409                 intel_set_pipe_timings(intel_crtc);
5410
5411         intel_set_pipe_src_size(intel_crtc);
5412
5413         if (cpu_transcoder != TRANSCODER_EDP &&
5414             !transcoder_is_dsi(cpu_transcoder)) {
5415                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5416                            intel_crtc->config->pixel_multiplier - 1);
5417         }
5418
5419         if (intel_crtc->config->has_pch_encoder) {
5420                 intel_cpu_transcoder_set_m_n(intel_crtc,
5421                                      &intel_crtc->config->fdi_m_n, NULL);
5422         }
5423
5424         if (!transcoder_is_dsi(cpu_transcoder))
5425                 haswell_set_pipeconf(crtc);
5426
5427         haswell_set_pipemisc(crtc);
5428
5429         intel_color_set_csc(&pipe_config->base);
5430
5431         intel_crtc->active = true;
5432
5433         if (intel_crtc->config->has_pch_encoder)
5434                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5435         else
5436                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5437
5438         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5439
5440         if (intel_crtc->config->has_pch_encoder)
5441                 dev_priv->display.fdi_link_train(crtc);
5442
5443         if (!transcoder_is_dsi(cpu_transcoder))
5444                 intel_ddi_enable_pipe_clock(intel_crtc);
5445
5446         if (INTEL_GEN(dev_priv) >= 9)
5447                 skylake_pfit_enable(intel_crtc);
5448         else
5449                 ironlake_pfit_enable(intel_crtc);
5450
5451         /*
5452          * On ILK+ LUT must be loaded before the pipe is running but with
5453          * clocks enabled
5454          */
5455         intel_color_load_luts(&pipe_config->base);
5456
5457         intel_ddi_set_pipe_settings(crtc);
5458         if (!transcoder_is_dsi(cpu_transcoder))
5459                 intel_ddi_enable_transcoder_func(crtc);
5460
5461         if (dev_priv->display.initial_watermarks != NULL)
5462                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5463
5464         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5465         if (!transcoder_is_dsi(cpu_transcoder))
5466                 intel_enable_pipe(intel_crtc);
5467
5468         if (intel_crtc->config->has_pch_encoder)
5469                 lpt_pch_enable(crtc);
5470
5471         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5472                 intel_ddi_set_vc_payload_alloc(crtc, true);
5473
5474         assert_vblank_disabled(crtc);
5475         drm_crtc_vblank_on(crtc);
5476
5477         intel_encoders_enable(crtc, pipe_config, old_state);
5478
5479         if (intel_crtc->config->has_pch_encoder) {
5480                 intel_wait_for_vblank(dev_priv, pipe);
5481                 intel_wait_for_vblank(dev_priv, pipe);
5482                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5483                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5484                                                       true);
5485         }
5486
5487         /* If we change the relative order between pipe/planes enabling, we need
5488          * to change the workaround. */
5489         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5490         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5491                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5492                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5493         }
5494 }
5495
5496 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5497 {
5498         struct drm_device *dev = crtc->base.dev;
5499         struct drm_i915_private *dev_priv = to_i915(dev);
5500         int pipe = crtc->pipe;
5501
5502         /* To avoid upsetting the power well on haswell only disable the pfit if
5503          * it's in use. The hw state code will make sure we get this right. */
5504         if (force || crtc->config->pch_pfit.enabled) {
5505                 I915_WRITE(PF_CTL(pipe), 0);
5506                 I915_WRITE(PF_WIN_POS(pipe), 0);
5507                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5508         }
5509 }
5510
5511 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5512                                   struct drm_atomic_state *old_state)
5513 {
5514         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5515         struct drm_device *dev = crtc->dev;
5516         struct drm_i915_private *dev_priv = to_i915(dev);
5517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5518         int pipe = intel_crtc->pipe;
5519
5520         /*
5521          * Sometimes spurious CPU pipe underruns happen when the
5522          * pipe is already disabled, but FDI RX/TX is still enabled.
5523          * Happens at least with VGA+HDMI cloning. Suppress them.
5524          */
5525         if (intel_crtc->config->has_pch_encoder) {
5526                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5527                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5528         }
5529
5530         intel_encoders_disable(crtc, old_crtc_state, old_state);
5531
5532         drm_crtc_vblank_off(crtc);
5533         assert_vblank_disabled(crtc);
5534
5535         intel_disable_pipe(intel_crtc);
5536
5537         ironlake_pfit_disable(intel_crtc, false);
5538
5539         if (intel_crtc->config->has_pch_encoder)
5540                 ironlake_fdi_disable(crtc);
5541
5542         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5543
5544         if (intel_crtc->config->has_pch_encoder) {
5545                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5546
5547                 if (HAS_PCH_CPT(dev_priv)) {
5548                         i915_reg_t reg;
5549                         u32 temp;
5550
5551                         /* disable TRANS_DP_CTL */
5552                         reg = TRANS_DP_CTL(pipe);
5553                         temp = I915_READ(reg);
5554                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5555                                   TRANS_DP_PORT_SEL_MASK);
5556                         temp |= TRANS_DP_PORT_SEL_NONE;
5557                         I915_WRITE(reg, temp);
5558
5559                         /* disable DPLL_SEL */
5560                         temp = I915_READ(PCH_DPLL_SEL);
5561                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5562                         I915_WRITE(PCH_DPLL_SEL, temp);
5563                 }
5564
5565                 ironlake_fdi_pll_disable(intel_crtc);
5566         }
5567
5568         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5569         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5570 }
5571
5572 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5573                                  struct drm_atomic_state *old_state)
5574 {
5575         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5576         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5578         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5579
5580         if (intel_crtc->config->has_pch_encoder)
5581                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5582                                                       false);
5583
5584         intel_encoders_disable(crtc, old_crtc_state, old_state);
5585
5586         drm_crtc_vblank_off(crtc);
5587         assert_vblank_disabled(crtc);
5588
5589         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5590         if (!transcoder_is_dsi(cpu_transcoder))
5591                 intel_disable_pipe(intel_crtc);
5592
5593         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5594                 intel_ddi_set_vc_payload_alloc(crtc, false);
5595
5596         if (!transcoder_is_dsi(cpu_transcoder))
5597                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5598
5599         if (INTEL_GEN(dev_priv) >= 9)
5600                 skylake_scaler_disable(intel_crtc);
5601         else
5602                 ironlake_pfit_disable(intel_crtc, false);
5603
5604         if (!transcoder_is_dsi(cpu_transcoder))
5605                 intel_ddi_disable_pipe_clock(intel_crtc);
5606
5607         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5608
5609         if (old_crtc_state->has_pch_encoder)
5610                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5611                                                       true);
5612 }
5613
5614 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5615 {
5616         struct drm_device *dev = crtc->base.dev;
5617         struct drm_i915_private *dev_priv = to_i915(dev);
5618         struct intel_crtc_state *pipe_config = crtc->config;
5619
5620         if (!pipe_config->gmch_pfit.control)
5621                 return;
5622
5623         /*
5624          * The panel fitter should only be adjusted whilst the pipe is disabled,
5625          * according to register description and PRM.
5626          */
5627         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5628         assert_pipe_disabled(dev_priv, crtc->pipe);
5629
5630         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5631         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5632
5633         /* Border color in case we don't scale up to the full screen. Black by
5634          * default, change to something else for debugging. */
5635         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5636 }
5637
5638 static enum intel_display_power_domain port_to_power_domain(enum port port)
5639 {
5640         switch (port) {
5641         case PORT_A:
5642                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5643         case PORT_B:
5644                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5645         case PORT_C:
5646                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5647         case PORT_D:
5648                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5649         case PORT_E:
5650                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5651         default:
5652                 MISSING_CASE(port);
5653                 return POWER_DOMAIN_PORT_OTHER;
5654         }
5655 }
5656
5657 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5658 {
5659         switch (port) {
5660         case PORT_A:
5661                 return POWER_DOMAIN_AUX_A;
5662         case PORT_B:
5663                 return POWER_DOMAIN_AUX_B;
5664         case PORT_C:
5665                 return POWER_DOMAIN_AUX_C;
5666         case PORT_D:
5667                 return POWER_DOMAIN_AUX_D;
5668         case PORT_E:
5669                 /* FIXME: Check VBT for actual wiring of PORT E */
5670                 return POWER_DOMAIN_AUX_D;
5671         default:
5672                 MISSING_CASE(port);
5673                 return POWER_DOMAIN_AUX_A;
5674         }
5675 }
5676
5677 enum intel_display_power_domain
5678 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5679 {
5680         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5681         struct intel_digital_port *intel_dig_port;
5682
5683         switch (intel_encoder->type) {
5684         case INTEL_OUTPUT_UNKNOWN:
5685                 /* Only DDI platforms should ever use this output type */
5686                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5687         case INTEL_OUTPUT_DP:
5688         case INTEL_OUTPUT_HDMI:
5689         case INTEL_OUTPUT_EDP:
5690                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5691                 return port_to_power_domain(intel_dig_port->port);
5692         case INTEL_OUTPUT_DP_MST:
5693                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5694                 return port_to_power_domain(intel_dig_port->port);
5695         case INTEL_OUTPUT_ANALOG:
5696                 return POWER_DOMAIN_PORT_CRT;
5697         case INTEL_OUTPUT_DSI:
5698                 return POWER_DOMAIN_PORT_DSI;
5699         default:
5700                 return POWER_DOMAIN_PORT_OTHER;
5701         }
5702 }
5703
5704 enum intel_display_power_domain
5705 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5706 {
5707         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5708         struct intel_digital_port *intel_dig_port;
5709
5710         switch (intel_encoder->type) {
5711         case INTEL_OUTPUT_UNKNOWN:
5712         case INTEL_OUTPUT_HDMI:
5713                 /*
5714                  * Only DDI platforms should ever use these output types.
5715                  * We can get here after the HDMI detect code has already set
5716                  * the type of the shared encoder. Since we can't be sure
5717                  * what's the status of the given connectors, play safe and
5718                  * run the DP detection too.
5719                  */
5720                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5721         case INTEL_OUTPUT_DP:
5722         case INTEL_OUTPUT_EDP:
5723                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5724                 return port_to_aux_power_domain(intel_dig_port->port);
5725         case INTEL_OUTPUT_DP_MST:
5726                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5727                 return port_to_aux_power_domain(intel_dig_port->port);
5728         default:
5729                 MISSING_CASE(intel_encoder->type);
5730                 return POWER_DOMAIN_AUX_A;
5731         }
5732 }
5733
5734 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5735                                             struct intel_crtc_state *crtc_state)
5736 {
5737         struct drm_device *dev = crtc->dev;
5738         struct drm_encoder *encoder;
5739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5740         enum pipe pipe = intel_crtc->pipe;
5741         unsigned long mask;
5742         enum transcoder transcoder = crtc_state->cpu_transcoder;
5743
5744         if (!crtc_state->base.active)
5745                 return 0;
5746
5747         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5748         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5749         if (crtc_state->pch_pfit.enabled ||
5750             crtc_state->pch_pfit.force_thru)
5751                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5752
5753         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5754                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5755
5756                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5757         }
5758
5759         if (crtc_state->shared_dpll)
5760                 mask |= BIT(POWER_DOMAIN_PLLS);
5761
5762         return mask;
5763 }
5764
5765 static unsigned long
5766 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5767                                struct intel_crtc_state *crtc_state)
5768 {
5769         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5771         enum intel_display_power_domain domain;
5772         unsigned long domains, new_domains, old_domains;
5773
5774         old_domains = intel_crtc->enabled_power_domains;
5775         intel_crtc->enabled_power_domains = new_domains =
5776                 get_crtc_power_domains(crtc, crtc_state);
5777
5778         domains = new_domains & ~old_domains;
5779
5780         for_each_power_domain(domain, domains)
5781                 intel_display_power_get(dev_priv, domain);
5782
5783         return old_domains & ~new_domains;
5784 }
5785
5786 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5787                                       unsigned long domains)
5788 {
5789         enum intel_display_power_domain domain;
5790
5791         for_each_power_domain(domain, domains)
5792                 intel_display_power_put(dev_priv, domain);
5793 }
5794
5795 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5796 {
5797         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5798
5799         if (IS_GEMINILAKE(dev_priv))
5800                 return 2 * max_cdclk_freq;
5801         else if (INTEL_INFO(dev_priv)->gen >= 9 ||
5802                  IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5803                 return max_cdclk_freq;
5804         else if (IS_CHERRYVIEW(dev_priv))
5805                 return max_cdclk_freq*95/100;
5806         else if (INTEL_INFO(dev_priv)->gen < 4)
5807                 return 2*max_cdclk_freq*90/100;
5808         else
5809                 return max_cdclk_freq*90/100;
5810 }
5811
5812 static int skl_calc_cdclk(int max_pixclk, int vco);
5813
5814 static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
5815 {
5816         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5817                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5818                 int max_cdclk, vco;
5819
5820                 vco = dev_priv->skl_preferred_vco_freq;
5821                 WARN_ON(vco != 8100000 && vco != 8640000);
5822
5823                 /*
5824                  * Use the lower (vco 8640) cdclk values as a
5825                  * first guess. skl_calc_cdclk() will correct it
5826                  * if the preferred vco is 8100 instead.
5827                  */
5828                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5829                         max_cdclk = 617143;
5830                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5831                         max_cdclk = 540000;
5832                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5833                         max_cdclk = 432000;
5834                 else
5835                         max_cdclk = 308571;
5836
5837                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5838         } else if (IS_GEMINILAKE(dev_priv)) {
5839                 dev_priv->max_cdclk_freq = 316800;
5840         } else if (IS_BROXTON(dev_priv)) {
5841                 dev_priv->max_cdclk_freq = 624000;
5842         } else if (IS_BROADWELL(dev_priv))  {
5843                 /*
5844                  * FIXME with extra cooling we can allow
5845                  * 540 MHz for ULX and 675 Mhz for ULT.
5846                  * How can we know if extra cooling is
5847                  * available? PCI ID, VTB, something else?
5848                  */
5849                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5850                         dev_priv->max_cdclk_freq = 450000;
5851                 else if (IS_BDW_ULX(dev_priv))
5852                         dev_priv->max_cdclk_freq = 450000;
5853                 else if (IS_BDW_ULT(dev_priv))
5854                         dev_priv->max_cdclk_freq = 540000;
5855                 else
5856                         dev_priv->max_cdclk_freq = 675000;
5857         } else if (IS_CHERRYVIEW(dev_priv)) {
5858                 dev_priv->max_cdclk_freq = 320000;
5859         } else if (IS_VALLEYVIEW(dev_priv)) {
5860                 dev_priv->max_cdclk_freq = 400000;
5861         } else {
5862                 /* otherwise assume cdclk is fixed */
5863                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5864         }
5865
5866         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5867
5868         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5869                          dev_priv->max_cdclk_freq);
5870
5871         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5872                          dev_priv->max_dotclk_freq);
5873 }
5874
5875 static void intel_update_cdclk(struct drm_i915_private *dev_priv)
5876 {
5877         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv);
5878
5879         if (INTEL_GEN(dev_priv) >= 9)
5880                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5881                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5882                                  dev_priv->cdclk_pll.ref);
5883         else
5884                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5885                                  dev_priv->cdclk_freq);
5886
5887         /*
5888          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5889          * Programmng [sic] note: bit[9:2] should be programmed to the number
5890          * of cdclk that generates 4MHz reference clock freq which is used to
5891          * generate GMBus clock. This will vary with the cdclk freq.
5892          */
5893         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5894                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5895 }
5896
5897 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5898 static int skl_cdclk_decimal(int cdclk)
5899 {
5900         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5901 }
5902
5903 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5904 {
5905         int ratio;
5906
5907         if (cdclk == dev_priv->cdclk_pll.ref)
5908                 return 0;
5909
5910         switch (cdclk) {
5911         default:
5912                 MISSING_CASE(cdclk);
5913         case 144000:
5914         case 288000:
5915         case 384000:
5916         case 576000:
5917                 ratio = 60;
5918                 break;
5919         case 624000:
5920                 ratio = 65;
5921                 break;
5922         }
5923
5924         return dev_priv->cdclk_pll.ref * ratio;
5925 }
5926
5927 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5928 {
5929         int ratio;
5930
5931         if (cdclk == dev_priv->cdclk_pll.ref)
5932                 return 0;
5933
5934         switch (cdclk) {
5935         default:
5936                 MISSING_CASE(cdclk);
5937         case  79200:
5938         case 158400:
5939         case 316800:
5940                 ratio = 33;
5941                 break;
5942         }
5943
5944         return dev_priv->cdclk_pll.ref * ratio;
5945 }
5946
5947 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5948 {
5949         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5950
5951         /* Timeout 200us */
5952         if (intel_wait_for_register(dev_priv,
5953                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5954                                     1))
5955                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5956
5957         dev_priv->cdclk_pll.vco = 0;
5958 }
5959
5960 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5961 {
5962         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5963         u32 val;
5964
5965         val = I915_READ(BXT_DE_PLL_CTL);
5966         val &= ~BXT_DE_PLL_RATIO_MASK;
5967         val |= BXT_DE_PLL_RATIO(ratio);
5968         I915_WRITE(BXT_DE_PLL_CTL, val);
5969
5970         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5971
5972         /* Timeout 200us */
5973         if (intel_wait_for_register(dev_priv,
5974                                     BXT_DE_PLL_ENABLE,
5975                                     BXT_DE_PLL_LOCK,
5976                                     BXT_DE_PLL_LOCK,
5977                                     1))
5978                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5979
5980         dev_priv->cdclk_pll.vco = vco;
5981 }
5982
5983 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5984 {
5985         u32 val, divider;
5986         int vco, ret;
5987
5988         if (IS_GEMINILAKE(dev_priv))
5989                 vco = glk_de_pll_vco(dev_priv, cdclk);
5990         else
5991                 vco = bxt_de_pll_vco(dev_priv, cdclk);
5992
5993         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5994
5995         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5996         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5997         case 8:
5998                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5999                 break;
6000         case 4:
6001                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
6002                 break;
6003         case 3:
6004                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
6005                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
6006                 break;
6007         case 2:
6008                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6009                 break;
6010         default:
6011                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6012                 WARN_ON(vco != 0);
6013
6014                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6015                 break;
6016         }
6017
6018         /* Inform power controller of upcoming frequency change */
6019         mutex_lock(&dev_priv->rps.hw_lock);
6020         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6021                                       0x80000000);
6022         mutex_unlock(&dev_priv->rps.hw_lock);
6023
6024         if (ret) {
6025                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6026                           ret, cdclk);
6027                 return;
6028         }
6029
6030         if (dev_priv->cdclk_pll.vco != 0 &&
6031             dev_priv->cdclk_pll.vco != vco)
6032                 bxt_de_pll_disable(dev_priv);
6033
6034         if (dev_priv->cdclk_pll.vco != vco)
6035                 bxt_de_pll_enable(dev_priv, vco);
6036
6037         val = divider | skl_cdclk_decimal(cdclk);
6038         /*
6039          * FIXME if only the cd2x divider needs changing, it could be done
6040          * without shutting off the pipe (if only one pipe is active).
6041          */
6042         val |= BXT_CDCLK_CD2X_PIPE_NONE;
6043         /*
6044          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6045          * enable otherwise.
6046          */
6047         if (cdclk >= 500000)
6048                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6049         I915_WRITE(CDCLK_CTL, val);
6050
6051         mutex_lock(&dev_priv->rps.hw_lock);
6052         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6053                                       DIV_ROUND_UP(cdclk, 25000));
6054         mutex_unlock(&dev_priv->rps.hw_lock);
6055
6056         if (ret) {
6057                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6058                           ret, cdclk);
6059                 return;
6060         }
6061
6062         intel_update_cdclk(dev_priv);
6063 }
6064
6065 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6066 {
6067         u32 cdctl, expected;
6068
6069         intel_update_cdclk(dev_priv);
6070
6071         if (dev_priv->cdclk_pll.vco == 0 ||
6072             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6073                 goto sanitize;
6074
6075         /* DPLL okay; verify the cdclock
6076          *
6077          * Some BIOS versions leave an incorrect decimal frequency value and
6078          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6079          * so sanitize this register.
6080          */
6081         cdctl = I915_READ(CDCLK_CTL);
6082         /*
6083          * Let's ignore the pipe field, since BIOS could have configured the
6084          * dividers both synching to an active pipe, or asynchronously
6085          * (PIPE_NONE).
6086          */
6087         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6088
6089         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6090                    skl_cdclk_decimal(dev_priv->cdclk_freq);
6091         /*
6092          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6093          * enable otherwise.
6094          */
6095         if (dev_priv->cdclk_freq >= 500000)
6096                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6097
6098         if (cdctl == expected)
6099                 /* All well; nothing to sanitize */
6100                 return;
6101
6102 sanitize:
6103         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6104
6105         /* force cdclk programming */
6106         dev_priv->cdclk_freq = 0;
6107
6108         /* force full PLL disable + enable */
6109         dev_priv->cdclk_pll.vco = -1;
6110 }
6111
6112 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6113 {
6114         int cdclk;
6115
6116         bxt_sanitize_cdclk(dev_priv);
6117
6118         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6119                 return;
6120
6121         /*
6122          * FIXME:
6123          * - The initial CDCLK needs to be read from VBT.
6124          *   Need to make this change after VBT has changes for BXT.
6125          */
6126         if (IS_GEMINILAKE(dev_priv))
6127                 cdclk = glk_calc_cdclk(0);
6128         else
6129                 cdclk = bxt_calc_cdclk(0);
6130
6131         bxt_set_cdclk(dev_priv, cdclk);
6132 }
6133
6134 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6135 {
6136         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6137 }
6138
6139 static int skl_calc_cdclk(int max_pixclk, int vco)
6140 {
6141         if (vco == 8640000) {
6142                 if (max_pixclk > 540000)
6143                         return 617143;
6144                 else if (max_pixclk > 432000)
6145                         return 540000;
6146                 else if (max_pixclk > 308571)
6147                         return 432000;
6148                 else
6149                         return 308571;
6150         } else {
6151                 if (max_pixclk > 540000)
6152                         return 675000;
6153                 else if (max_pixclk > 450000)
6154                         return 540000;
6155                 else if (max_pixclk > 337500)
6156                         return 450000;
6157                 else
6158                         return 337500;
6159         }
6160 }
6161
6162 static void
6163 skl_dpll0_update(struct drm_i915_private *dev_priv)
6164 {
6165         u32 val;
6166
6167         dev_priv->cdclk_pll.ref = 24000;
6168         dev_priv->cdclk_pll.vco = 0;
6169
6170         val = I915_READ(LCPLL1_CTL);
6171         if ((val & LCPLL_PLL_ENABLE) == 0)
6172                 return;
6173
6174         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6175                 return;
6176
6177         val = I915_READ(DPLL_CTRL1);
6178
6179         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6180                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6181                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6182                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6183                 return;
6184
6185         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6186         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6187         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6188         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6189         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6190                 dev_priv->cdclk_pll.vco = 8100000;
6191                 break;
6192         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6193         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6194                 dev_priv->cdclk_pll.vco = 8640000;
6195                 break;
6196         default:
6197                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6198                 break;
6199         }
6200 }
6201
6202 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6203 {
6204         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6205
6206         dev_priv->skl_preferred_vco_freq = vco;
6207
6208         if (changed)
6209                 intel_update_max_cdclk(dev_priv);
6210 }
6211
6212 static void
6213 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6214 {
6215         int min_cdclk = skl_calc_cdclk(0, vco);
6216         u32 val;
6217
6218         WARN_ON(vco != 8100000 && vco != 8640000);
6219
6220         /* select the minimum CDCLK before enabling DPLL 0 */
6221         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6222         I915_WRITE(CDCLK_CTL, val);
6223         POSTING_READ(CDCLK_CTL);
6224
6225         /*
6226          * We always enable DPLL0 with the lowest link rate possible, but still
6227          * taking into account the VCO required to operate the eDP panel at the
6228          * desired frequency. The usual DP link rates operate with a VCO of
6229          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6230          * The modeset code is responsible for the selection of the exact link
6231          * rate later on, with the constraint of choosing a frequency that
6232          * works with vco.
6233          */
6234         val = I915_READ(DPLL_CTRL1);
6235
6236         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6237                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6238         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6239         if (vco == 8640000)
6240                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6241                                             SKL_DPLL0);
6242         else
6243                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6244                                             SKL_DPLL0);
6245
6246         I915_WRITE(DPLL_CTRL1, val);
6247         POSTING_READ(DPLL_CTRL1);
6248
6249         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6250
6251         if (intel_wait_for_register(dev_priv,
6252                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6253                                     5))
6254                 DRM_ERROR("DPLL0 not locked\n");
6255
6256         dev_priv->cdclk_pll.vco = vco;
6257
6258         /* We'll want to keep using the current vco from now on. */
6259         skl_set_preferred_cdclk_vco(dev_priv, vco);
6260 }
6261
6262 static void
6263 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6264 {
6265         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6266         if (intel_wait_for_register(dev_priv,
6267                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6268                                    1))
6269                 DRM_ERROR("Couldn't disable DPLL0\n");
6270
6271         dev_priv->cdclk_pll.vco = 0;
6272 }
6273
6274 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6275 {
6276         u32 freq_select, pcu_ack;
6277         int ret;
6278
6279         WARN_ON((cdclk == 24000) != (vco == 0));
6280
6281         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6282
6283         mutex_lock(&dev_priv->rps.hw_lock);
6284         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
6285                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
6286                                 SKL_CDCLK_READY_FOR_CHANGE,
6287                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
6288         mutex_unlock(&dev_priv->rps.hw_lock);
6289         if (ret) {
6290                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
6291                           ret);
6292                 return;
6293         }
6294
6295         /* set CDCLK_CTL */
6296         switch (cdclk) {
6297         case 450000:
6298         case 432000:
6299                 freq_select = CDCLK_FREQ_450_432;
6300                 pcu_ack = 1;
6301                 break;
6302         case 540000:
6303                 freq_select = CDCLK_FREQ_540;
6304                 pcu_ack = 2;
6305                 break;
6306         case 308571:
6307         case 337500:
6308         default:
6309                 freq_select = CDCLK_FREQ_337_308;
6310                 pcu_ack = 0;
6311                 break;
6312         case 617143:
6313         case 675000:
6314                 freq_select = CDCLK_FREQ_675_617;
6315                 pcu_ack = 3;
6316                 break;
6317         }
6318
6319         if (dev_priv->cdclk_pll.vco != 0 &&
6320             dev_priv->cdclk_pll.vco != vco)
6321                 skl_dpll0_disable(dev_priv);
6322
6323         if (dev_priv->cdclk_pll.vco != vco)
6324                 skl_dpll0_enable(dev_priv, vco);
6325
6326         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6327         POSTING_READ(CDCLK_CTL);
6328
6329         /* inform PCU of the change */
6330         mutex_lock(&dev_priv->rps.hw_lock);
6331         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6332         mutex_unlock(&dev_priv->rps.hw_lock);
6333
6334         intel_update_cdclk(dev_priv);
6335 }
6336
6337 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6338
6339 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6340 {
6341         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6342 }
6343
6344 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6345 {
6346         int cdclk, vco;
6347
6348         skl_sanitize_cdclk(dev_priv);
6349
6350         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6351                 /*
6352                  * Use the current vco as our initial
6353                  * guess as to what the preferred vco is.
6354                  */
6355                 if (dev_priv->skl_preferred_vco_freq == 0)
6356                         skl_set_preferred_cdclk_vco(dev_priv,
6357                                                     dev_priv->cdclk_pll.vco);
6358                 return;
6359         }
6360
6361         vco = dev_priv->skl_preferred_vco_freq;
6362         if (vco == 0)
6363                 vco = 8100000;
6364         cdclk = skl_calc_cdclk(0, vco);
6365
6366         skl_set_cdclk(dev_priv, cdclk, vco);
6367 }
6368
6369 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6370 {
6371         uint32_t cdctl, expected;
6372
6373         /*
6374          * check if the pre-os intialized the display
6375          * There is SWF18 scratchpad register defined which is set by the
6376          * pre-os which can be used by the OS drivers to check the status
6377          */
6378         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6379                 goto sanitize;
6380
6381         intel_update_cdclk(dev_priv);
6382         /* Is PLL enabled and locked ? */
6383         if (dev_priv->cdclk_pll.vco == 0 ||
6384             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6385                 goto sanitize;
6386
6387         /* DPLL okay; verify the cdclock
6388          *
6389          * Noticed in some instances that the freq selection is correct but
6390          * decimal part is programmed wrong from BIOS where pre-os does not
6391          * enable display. Verify the same as well.
6392          */
6393         cdctl = I915_READ(CDCLK_CTL);
6394         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6395                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6396         if (cdctl == expected)
6397                 /* All well; nothing to sanitize */
6398                 return;
6399
6400 sanitize:
6401         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6402
6403         /* force cdclk programming */
6404         dev_priv->cdclk_freq = 0;
6405         /* force full PLL disable + enable */
6406         dev_priv->cdclk_pll.vco = -1;
6407 }
6408
6409 /* Adjust CDclk dividers to allow high res or save power if possible */
6410 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6411 {
6412         struct drm_i915_private *dev_priv = to_i915(dev);
6413         u32 val, cmd;
6414
6415         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6416                                         != dev_priv->cdclk_freq);
6417
6418         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6419                 cmd = 2;
6420         else if (cdclk == 266667)
6421                 cmd = 1;
6422         else
6423                 cmd = 0;
6424
6425         mutex_lock(&dev_priv->rps.hw_lock);
6426         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6427         val &= ~DSPFREQGUAR_MASK;
6428         val |= (cmd << DSPFREQGUAR_SHIFT);
6429         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6430         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6431                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6432                      50)) {
6433                 DRM_ERROR("timed out waiting for CDclk change\n");
6434         }
6435         mutex_unlock(&dev_priv->rps.hw_lock);
6436
6437         mutex_lock(&dev_priv->sb_lock);
6438
6439         if (cdclk == 400000) {
6440                 u32 divider;
6441
6442                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6443
6444                 /* adjust cdclk divider */
6445                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6446                 val &= ~CCK_FREQUENCY_VALUES;
6447                 val |= divider;
6448                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6449
6450                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6451                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6452                              50))
6453                         DRM_ERROR("timed out waiting for CDclk change\n");
6454         }
6455
6456         /* adjust self-refresh exit latency value */
6457         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6458         val &= ~0x7f;
6459
6460         /*
6461          * For high bandwidth configs, we set a higher latency in the bunit
6462          * so that the core display fetch happens in time to avoid underruns.
6463          */
6464         if (cdclk == 400000)
6465                 val |= 4500 / 250; /* 4.5 usec */
6466         else
6467                 val |= 3000 / 250; /* 3.0 usec */
6468         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6469
6470         mutex_unlock(&dev_priv->sb_lock);
6471
6472         intel_update_cdclk(dev_priv);
6473 }
6474
6475 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6476 {
6477         struct drm_i915_private *dev_priv = to_i915(dev);
6478         u32 val, cmd;
6479
6480         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6481                                                 != dev_priv->cdclk_freq);
6482
6483         switch (cdclk) {
6484         case 333333:
6485         case 320000:
6486         case 266667:
6487         case 200000:
6488                 break;
6489         default:
6490                 MISSING_CASE(cdclk);
6491                 return;
6492         }
6493
6494         /*
6495          * Specs are full of misinformation, but testing on actual
6496          * hardware has shown that we just need to write the desired
6497          * CCK divider into the Punit register.
6498          */
6499         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6500
6501         mutex_lock(&dev_priv->rps.hw_lock);
6502         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6503         val &= ~DSPFREQGUAR_MASK_CHV;
6504         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6505         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6506         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6507                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6508                      50)) {
6509                 DRM_ERROR("timed out waiting for CDclk change\n");
6510         }
6511         mutex_unlock(&dev_priv->rps.hw_lock);
6512
6513         intel_update_cdclk(dev_priv);
6514 }
6515
6516 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6517                                  int max_pixclk)
6518 {
6519         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6520         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6521
6522         /*
6523          * Really only a few cases to deal with, as only 4 CDclks are supported:
6524          *   200MHz
6525          *   267MHz
6526          *   320/333MHz (depends on HPLL freq)
6527          *   400MHz (VLV only)
6528          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6529          * of the lower bin and adjust if needed.
6530          *
6531          * We seem to get an unstable or solid color picture at 200MHz.
6532          * Not sure what's wrong. For now use 200MHz only when all pipes
6533          * are off.
6534          */
6535         if (!IS_CHERRYVIEW(dev_priv) &&
6536             max_pixclk > freq_320*limit/100)
6537                 return 400000;
6538         else if (max_pixclk > 266667*limit/100)
6539                 return freq_320;
6540         else if (max_pixclk > 0)
6541                 return 266667;
6542         else
6543                 return 200000;
6544 }
6545
6546 static int glk_calc_cdclk(int max_pixclk)
6547 {
6548         if (max_pixclk > 2 * 158400)
6549                 return 316800;
6550         else if (max_pixclk > 2 * 79200)
6551                 return 158400;
6552         else
6553                 return 79200;
6554 }
6555
6556 static int bxt_calc_cdclk(int max_pixclk)
6557 {
6558         if (max_pixclk > 576000)
6559                 return 624000;
6560         else if (max_pixclk > 384000)
6561                 return 576000;
6562         else if (max_pixclk > 288000)
6563                 return 384000;
6564         else if (max_pixclk > 144000)
6565                 return 288000;
6566         else
6567                 return 144000;
6568 }
6569
6570 /* Compute the max pixel clock for new configuration. */
6571 static int intel_mode_max_pixclk(struct drm_device *dev,
6572                                  struct drm_atomic_state *state)
6573 {
6574         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6575         struct drm_i915_private *dev_priv = to_i915(dev);
6576         struct drm_crtc *crtc;
6577         struct drm_crtc_state *crtc_state;
6578         unsigned max_pixclk = 0, i;
6579         enum pipe pipe;
6580
6581         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6582                sizeof(intel_state->min_pixclk));
6583
6584         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6585                 int pixclk = 0;
6586
6587                 if (crtc_state->enable)
6588                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6589
6590                 intel_state->min_pixclk[i] = pixclk;
6591         }
6592
6593         for_each_pipe(dev_priv, pipe)
6594                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6595
6596         return max_pixclk;
6597 }
6598
6599 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6600 {
6601         struct drm_device *dev = state->dev;
6602         struct drm_i915_private *dev_priv = to_i915(dev);
6603         int max_pixclk = intel_mode_max_pixclk(dev, state);
6604         struct intel_atomic_state *intel_state =
6605                 to_intel_atomic_state(state);
6606
6607         intel_state->cdclk = intel_state->dev_cdclk =
6608                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6609
6610         if (!intel_state->active_crtcs)
6611                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6612
6613         return 0;
6614 }
6615
6616 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6617 {
6618         struct drm_i915_private *dev_priv = to_i915(state->dev);
6619         int max_pixclk = ilk_max_pixel_rate(state);
6620         struct intel_atomic_state *intel_state =
6621                 to_intel_atomic_state(state);
6622         int cdclk;
6623
6624         if (IS_GEMINILAKE(dev_priv))
6625                 cdclk = glk_calc_cdclk(max_pixclk);
6626         else
6627                 cdclk = bxt_calc_cdclk(max_pixclk);
6628
6629         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
6630
6631         if (!intel_state->active_crtcs) {
6632                 if (IS_GEMINILAKE(dev_priv))
6633                         cdclk = glk_calc_cdclk(0);
6634                 else
6635                         cdclk = bxt_calc_cdclk(0);
6636
6637                 intel_state->dev_cdclk = cdclk;
6638         }
6639
6640         return 0;
6641 }
6642
6643 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6644 {
6645         unsigned int credits, default_credits;
6646
6647         if (IS_CHERRYVIEW(dev_priv))
6648                 default_credits = PFI_CREDIT(12);
6649         else
6650                 default_credits = PFI_CREDIT(8);
6651
6652         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6653                 /* CHV suggested value is 31 or 63 */
6654                 if (IS_CHERRYVIEW(dev_priv))
6655                         credits = PFI_CREDIT_63;
6656                 else
6657                         credits = PFI_CREDIT(15);
6658         } else {
6659                 credits = default_credits;
6660         }
6661
6662         /*
6663          * WA - write default credits before re-programming
6664          * FIXME: should we also set the resend bit here?
6665          */
6666         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6667                    default_credits);
6668
6669         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6670                    credits | PFI_CREDIT_RESEND);
6671
6672         /*
6673          * FIXME is this guaranteed to clear
6674          * immediately or should we poll for it?
6675          */
6676         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6677 }
6678
6679 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6680 {
6681         struct drm_device *dev = old_state->dev;
6682         struct drm_i915_private *dev_priv = to_i915(dev);
6683         struct intel_atomic_state *old_intel_state =
6684                 to_intel_atomic_state(old_state);
6685         unsigned req_cdclk = old_intel_state->dev_cdclk;
6686
6687         /*
6688          * FIXME: We can end up here with all power domains off, yet
6689          * with a CDCLK frequency other than the minimum. To account
6690          * for this take the PIPE-A power domain, which covers the HW
6691          * blocks needed for the following programming. This can be
6692          * removed once it's guaranteed that we get here either with
6693          * the minimum CDCLK set, or the required power domains
6694          * enabled.
6695          */
6696         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6697
6698         if (IS_CHERRYVIEW(dev_priv))
6699                 cherryview_set_cdclk(dev, req_cdclk);
6700         else
6701                 valleyview_set_cdclk(dev, req_cdclk);
6702
6703         vlv_program_pfi_credits(dev_priv);
6704
6705         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6706 }
6707
6708 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6709                                    struct drm_atomic_state *old_state)
6710 {
6711         struct drm_crtc *crtc = pipe_config->base.crtc;
6712         struct drm_device *dev = crtc->dev;
6713         struct drm_i915_private *dev_priv = to_i915(dev);
6714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6715         int pipe = intel_crtc->pipe;
6716
6717         if (WARN_ON(intel_crtc->active))
6718                 return;
6719
6720         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6721                 intel_dp_set_m_n(intel_crtc, M1_N1);
6722
6723         intel_set_pipe_timings(intel_crtc);
6724         intel_set_pipe_src_size(intel_crtc);
6725
6726         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6727                 struct drm_i915_private *dev_priv = to_i915(dev);
6728
6729                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6730                 I915_WRITE(CHV_CANVAS(pipe), 0);
6731         }
6732
6733         i9xx_set_pipeconf(intel_crtc);
6734
6735         intel_crtc->active = true;
6736
6737         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6738
6739         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6740
6741         if (IS_CHERRYVIEW(dev_priv)) {
6742                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6743                 chv_enable_pll(intel_crtc, intel_crtc->config);
6744         } else {
6745                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6746                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6747         }
6748
6749         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6750
6751         i9xx_pfit_enable(intel_crtc);
6752
6753         intel_color_load_luts(&pipe_config->base);
6754
6755         intel_update_watermarks(intel_crtc);
6756         intel_enable_pipe(intel_crtc);
6757
6758         assert_vblank_disabled(crtc);
6759         drm_crtc_vblank_on(crtc);
6760
6761         intel_encoders_enable(crtc, pipe_config, old_state);
6762 }
6763
6764 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6765 {
6766         struct drm_device *dev = crtc->base.dev;
6767         struct drm_i915_private *dev_priv = to_i915(dev);
6768
6769         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6770         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6771 }
6772
6773 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6774                              struct drm_atomic_state *old_state)
6775 {
6776         struct drm_crtc *crtc = pipe_config->base.crtc;
6777         struct drm_device *dev = crtc->dev;
6778         struct drm_i915_private *dev_priv = to_i915(dev);
6779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6780         enum pipe pipe = intel_crtc->pipe;
6781
6782         if (WARN_ON(intel_crtc->active))
6783                 return;
6784
6785         i9xx_set_pll_dividers(intel_crtc);
6786
6787         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6788                 intel_dp_set_m_n(intel_crtc, M1_N1);
6789
6790         intel_set_pipe_timings(intel_crtc);
6791         intel_set_pipe_src_size(intel_crtc);
6792
6793         i9xx_set_pipeconf(intel_crtc);
6794
6795         intel_crtc->active = true;
6796
6797         if (!IS_GEN2(dev_priv))
6798                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6799
6800         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6801
6802         i9xx_enable_pll(intel_crtc);
6803
6804         i9xx_pfit_enable(intel_crtc);
6805
6806         intel_color_load_luts(&pipe_config->base);
6807
6808         intel_update_watermarks(intel_crtc);
6809         intel_enable_pipe(intel_crtc);
6810
6811         assert_vblank_disabled(crtc);
6812         drm_crtc_vblank_on(crtc);
6813
6814         intel_encoders_enable(crtc, pipe_config, old_state);
6815 }
6816
6817 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6818 {
6819         struct drm_device *dev = crtc->base.dev;
6820         struct drm_i915_private *dev_priv = to_i915(dev);
6821
6822         if (!crtc->config->gmch_pfit.control)
6823                 return;
6824
6825         assert_pipe_disabled(dev_priv, crtc->pipe);
6826
6827         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6828                          I915_READ(PFIT_CONTROL));
6829         I915_WRITE(PFIT_CONTROL, 0);
6830 }
6831
6832 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6833                               struct drm_atomic_state *old_state)
6834 {
6835         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6836         struct drm_device *dev = crtc->dev;
6837         struct drm_i915_private *dev_priv = to_i915(dev);
6838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6839         int pipe = intel_crtc->pipe;
6840
6841         /*
6842          * On gen2 planes are double buffered but the pipe isn't, so we must
6843          * wait for planes to fully turn off before disabling the pipe.
6844          */
6845         if (IS_GEN2(dev_priv))
6846                 intel_wait_for_vblank(dev_priv, pipe);
6847
6848         intel_encoders_disable(crtc, old_crtc_state, old_state);
6849
6850         drm_crtc_vblank_off(crtc);
6851         assert_vblank_disabled(crtc);
6852
6853         intel_disable_pipe(intel_crtc);
6854
6855         i9xx_pfit_disable(intel_crtc);
6856
6857         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6858
6859         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6860                 if (IS_CHERRYVIEW(dev_priv))
6861                         chv_disable_pll(dev_priv, pipe);
6862                 else if (IS_VALLEYVIEW(dev_priv))
6863                         vlv_disable_pll(dev_priv, pipe);
6864                 else
6865                         i9xx_disable_pll(intel_crtc);
6866         }
6867
6868         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6869
6870         if (!IS_GEN2(dev_priv))
6871                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6872 }
6873
6874 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6875 {
6876         struct intel_encoder *encoder;
6877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6878         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6879         enum intel_display_power_domain domain;
6880         unsigned long domains;
6881         struct drm_atomic_state *state;
6882         struct intel_crtc_state *crtc_state;
6883         int ret;
6884
6885         if (!intel_crtc->active)
6886                 return;
6887
6888         if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6889                 WARN_ON(intel_crtc->flip_work);
6890
6891                 intel_pre_disable_primary_noatomic(crtc);
6892
6893                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6894                 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6895         }
6896
6897         state = drm_atomic_state_alloc(crtc->dev);
6898         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6899
6900         /* Everything's already locked, -EDEADLK can't happen. */
6901         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6902         ret = drm_atomic_add_affected_connectors(state, crtc);
6903
6904         WARN_ON(IS_ERR(crtc_state) || ret);
6905
6906         dev_priv->display.crtc_disable(crtc_state, state);
6907
6908         drm_atomic_state_put(state);
6909
6910         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6911                       crtc->base.id, crtc->name);
6912
6913         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6914         crtc->state->active = false;
6915         intel_crtc->active = false;
6916         crtc->enabled = false;
6917         crtc->state->connector_mask = 0;
6918         crtc->state->encoder_mask = 0;
6919
6920         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6921                 encoder->base.crtc = NULL;
6922
6923         intel_fbc_disable(intel_crtc);
6924         intel_update_watermarks(intel_crtc);
6925         intel_disable_shared_dpll(intel_crtc);
6926
6927         domains = intel_crtc->enabled_power_domains;
6928         for_each_power_domain(domain, domains)
6929                 intel_display_power_put(dev_priv, domain);
6930         intel_crtc->enabled_power_domains = 0;
6931
6932         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6933         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6934 }
6935
6936 /*
6937  * turn all crtc's off, but do not adjust state
6938  * This has to be paired with a call to intel_modeset_setup_hw_state.
6939  */
6940 int intel_display_suspend(struct drm_device *dev)
6941 {
6942         struct drm_i915_private *dev_priv = to_i915(dev);
6943         struct drm_atomic_state *state;
6944         int ret;
6945
6946         state = drm_atomic_helper_suspend(dev);
6947         ret = PTR_ERR_OR_ZERO(state);
6948         if (ret)
6949                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6950         else
6951                 dev_priv->modeset_restore_state = state;
6952         return ret;
6953 }
6954
6955 void intel_encoder_destroy(struct drm_encoder *encoder)
6956 {
6957         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6958
6959         drm_encoder_cleanup(encoder);
6960         kfree(intel_encoder);
6961 }
6962
6963 /* Cross check the actual hw state with our own modeset state tracking (and it's
6964  * internal consistency). */
6965 static void intel_connector_verify_state(struct intel_connector *connector)
6966 {
6967         struct drm_crtc *crtc = connector->base.state->crtc;
6968
6969         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6970                       connector->base.base.id,
6971                       connector->base.name);
6972
6973         if (connector->get_hw_state(connector)) {
6974                 struct intel_encoder *encoder = connector->encoder;
6975                 struct drm_connector_state *conn_state = connector->base.state;
6976
6977                 I915_STATE_WARN(!crtc,
6978                          "connector enabled without attached crtc\n");
6979
6980                 if (!crtc)
6981                         return;
6982
6983                 I915_STATE_WARN(!crtc->state->active,
6984                       "connector is active, but attached crtc isn't\n");
6985
6986                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6987                         return;
6988
6989                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6990                         "atomic encoder doesn't match attached encoder\n");
6991
6992                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6993                         "attached encoder crtc differs from connector crtc\n");
6994         } else {
6995                 I915_STATE_WARN(crtc && crtc->state->active,
6996                         "attached crtc is active, but connector isn't\n");
6997                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6998                         "best encoder set without crtc!\n");
6999         }
7000 }
7001
7002 int intel_connector_init(struct intel_connector *connector)
7003 {
7004         drm_atomic_helper_connector_reset(&connector->base);
7005
7006         if (!connector->base.state)
7007                 return -ENOMEM;
7008
7009         return 0;
7010 }
7011
7012 struct intel_connector *intel_connector_alloc(void)
7013 {
7014         struct intel_connector *connector;
7015
7016         connector = kzalloc(sizeof *connector, GFP_KERNEL);
7017         if (!connector)
7018                 return NULL;
7019
7020         if (intel_connector_init(connector) < 0) {
7021                 kfree(connector);
7022                 return NULL;
7023         }
7024
7025         return connector;
7026 }
7027
7028 /* Simple connector->get_hw_state implementation for encoders that support only
7029  * one connector and no cloning and hence the encoder state determines the state
7030  * of the connector. */
7031 bool intel_connector_get_hw_state(struct intel_connector *connector)
7032 {
7033         enum pipe pipe = 0;
7034         struct intel_encoder *encoder = connector->encoder;
7035
7036         return encoder->get_hw_state(encoder, &pipe);
7037 }
7038
7039 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7040 {
7041         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7042                 return crtc_state->fdi_lanes;
7043
7044         return 0;
7045 }
7046
7047 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7048                                      struct intel_crtc_state *pipe_config)
7049 {
7050         struct drm_i915_private *dev_priv = to_i915(dev);
7051         struct drm_atomic_state *state = pipe_config->base.state;
7052         struct intel_crtc *other_crtc;
7053         struct intel_crtc_state *other_crtc_state;
7054
7055         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7056                       pipe_name(pipe), pipe_config->fdi_lanes);
7057         if (pipe_config->fdi_lanes > 4) {
7058                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7059                               pipe_name(pipe), pipe_config->fdi_lanes);
7060                 return -EINVAL;
7061         }
7062
7063         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7064                 if (pipe_config->fdi_lanes > 2) {
7065                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7066                                       pipe_config->fdi_lanes);
7067                         return -EINVAL;
7068                 } else {
7069                         return 0;
7070                 }
7071         }
7072
7073         if (INTEL_INFO(dev_priv)->num_pipes == 2)
7074                 return 0;
7075
7076         /* Ivybridge 3 pipe is really complicated */
7077         switch (pipe) {
7078         case PIPE_A:
7079                 return 0;
7080         case PIPE_B:
7081                 if (pipe_config->fdi_lanes <= 2)
7082                         return 0;
7083
7084                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7085                 other_crtc_state =
7086                         intel_atomic_get_crtc_state(state, other_crtc);
7087                 if (IS_ERR(other_crtc_state))
7088                         return PTR_ERR(other_crtc_state);
7089
7090                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7091                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7092                                       pipe_name(pipe), pipe_config->fdi_lanes);
7093                         return -EINVAL;
7094                 }
7095                 return 0;
7096         case PIPE_C:
7097                 if (pipe_config->fdi_lanes > 2) {
7098                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7099                                       pipe_name(pipe), pipe_config->fdi_lanes);
7100                         return -EINVAL;
7101                 }
7102
7103                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7104                 other_crtc_state =
7105                         intel_atomic_get_crtc_state(state, other_crtc);
7106                 if (IS_ERR(other_crtc_state))
7107                         return PTR_ERR(other_crtc_state);
7108
7109                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7110                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7111                         return -EINVAL;
7112                 }
7113                 return 0;
7114         default:
7115                 BUG();
7116         }
7117 }
7118
7119 #define RETRY 1
7120 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7121                                        struct intel_crtc_state *pipe_config)
7122 {
7123         struct drm_device *dev = intel_crtc->base.dev;
7124         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7125         int lane, link_bw, fdi_dotclock, ret;
7126         bool needs_recompute = false;
7127
7128 retry:
7129         /* FDI is a binary signal running at ~2.7GHz, encoding
7130          * each output octet as 10 bits. The actual frequency
7131          * is stored as a divider into a 100MHz clock, and the
7132          * mode pixel clock is stored in units of 1KHz.
7133          * Hence the bw of each lane in terms of the mode signal
7134          * is:
7135          */
7136         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7137
7138         fdi_dotclock = adjusted_mode->crtc_clock;
7139
7140         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7141                                            pipe_config->pipe_bpp);
7142
7143         pipe_config->fdi_lanes = lane;
7144
7145         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7146                                link_bw, &pipe_config->fdi_m_n);
7147
7148         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7149         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7150                 pipe_config->pipe_bpp -= 2*3;
7151                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7152                               pipe_config->pipe_bpp);
7153                 needs_recompute = true;
7154                 pipe_config->bw_constrained = true;
7155
7156                 goto retry;
7157         }
7158
7159         if (needs_recompute)
7160                 return RETRY;
7161
7162         return ret;
7163 }
7164
7165 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7166                                      struct intel_crtc_state *pipe_config)
7167 {
7168         if (pipe_config->pipe_bpp > 24)
7169                 return false;
7170
7171         /* HSW can handle pixel rate up to cdclk? */
7172         if (IS_HASWELL(dev_priv))
7173                 return true;
7174
7175         /*
7176          * We compare against max which means we must take
7177          * the increased cdclk requirement into account when
7178          * calculating the new cdclk.
7179          *
7180          * Should measure whether using a lower cdclk w/o IPS
7181          */
7182         return ilk_pipe_pixel_rate(pipe_config) <=
7183                 dev_priv->max_cdclk_freq * 95 / 100;
7184 }
7185
7186 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7187                                    struct intel_crtc_state *pipe_config)
7188 {
7189         struct drm_device *dev = crtc->base.dev;
7190         struct drm_i915_private *dev_priv = to_i915(dev);
7191
7192         pipe_config->ips_enabled = i915.enable_ips &&
7193                 hsw_crtc_supports_ips(crtc) &&
7194                 pipe_config_supports_ips(dev_priv, pipe_config);
7195 }
7196
7197 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7198 {
7199         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7200
7201         /* GDG double wide on either pipe, otherwise pipe A only */
7202         return INTEL_INFO(dev_priv)->gen < 4 &&
7203                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7204 }
7205
7206 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7207                                      struct intel_crtc_state *pipe_config)
7208 {
7209         struct drm_device *dev = crtc->base.dev;
7210         struct drm_i915_private *dev_priv = to_i915(dev);
7211         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7212         int clock_limit = dev_priv->max_dotclk_freq;
7213
7214         if (INTEL_GEN(dev_priv) < 4) {
7215                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7216
7217                 /*
7218                  * Enable double wide mode when the dot clock
7219                  * is > 90% of the (display) core speed.
7220                  */
7221                 if (intel_crtc_supports_double_wide(crtc) &&
7222                     adjusted_mode->crtc_clock > clock_limit) {
7223                         clock_limit = dev_priv->max_dotclk_freq;
7224                         pipe_config->double_wide = true;
7225                 }
7226         }
7227
7228         if (adjusted_mode->crtc_clock > clock_limit) {
7229                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7230                               adjusted_mode->crtc_clock, clock_limit,
7231                               yesno(pipe_config->double_wide));
7232                 return -EINVAL;
7233         }
7234
7235         /*
7236          * Pipe horizontal size must be even in:
7237          * - DVO ganged mode
7238          * - LVDS dual channel mode
7239          * - Double wide pipe
7240          */
7241         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7242              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7243                 pipe_config->pipe_src_w &= ~1;
7244
7245         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7246          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7247          */
7248         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7249                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7250                 return -EINVAL;
7251
7252         if (HAS_IPS(dev_priv))
7253                 hsw_compute_ips_config(crtc, pipe_config);
7254
7255         if (pipe_config->has_pch_encoder)
7256                 return ironlake_fdi_compute_config(crtc, pipe_config);
7257
7258         return 0;
7259 }
7260
7261 static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv)
7262 {
7263         u32 cdctl;
7264
7265         skl_dpll0_update(dev_priv);
7266
7267         if (dev_priv->cdclk_pll.vco == 0)
7268                 return dev_priv->cdclk_pll.ref;
7269
7270         cdctl = I915_READ(CDCLK_CTL);
7271
7272         if (dev_priv->cdclk_pll.vco == 8640000) {
7273                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7274                 case CDCLK_FREQ_450_432:
7275                         return 432000;
7276                 case CDCLK_FREQ_337_308:
7277                         return 308571;
7278                 case CDCLK_FREQ_540:
7279                         return 540000;
7280                 case CDCLK_FREQ_675_617:
7281                         return 617143;
7282                 default:
7283                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7284                 }
7285         } else {
7286                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7287                 case CDCLK_FREQ_450_432:
7288                         return 450000;
7289                 case CDCLK_FREQ_337_308:
7290                         return 337500;
7291                 case CDCLK_FREQ_540:
7292                         return 540000;
7293                 case CDCLK_FREQ_675_617:
7294                         return 675000;
7295                 default:
7296                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7297                 }
7298         }
7299
7300         return dev_priv->cdclk_pll.ref;
7301 }
7302
7303 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7304 {
7305         u32 val;
7306
7307         dev_priv->cdclk_pll.ref = 19200;
7308         dev_priv->cdclk_pll.vco = 0;
7309
7310         val = I915_READ(BXT_DE_PLL_ENABLE);
7311         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7312                 return;
7313
7314         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7315                 return;
7316
7317         val = I915_READ(BXT_DE_PLL_CTL);
7318         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7319                 dev_priv->cdclk_pll.ref;
7320 }
7321
7322 static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
7323 {
7324         u32 divider;
7325         int div, vco;
7326
7327         bxt_de_pll_update(dev_priv);
7328
7329         vco = dev_priv->cdclk_pll.vco;
7330         if (vco == 0)
7331                 return dev_priv->cdclk_pll.ref;
7332
7333         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7334
7335         switch (divider) {
7336         case BXT_CDCLK_CD2X_DIV_SEL_1:
7337                 div = 2;
7338                 break;
7339         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7340                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
7341                 div = 3;
7342                 break;
7343         case BXT_CDCLK_CD2X_DIV_SEL_2:
7344                 div = 4;
7345                 break;
7346         case BXT_CDCLK_CD2X_DIV_SEL_4:
7347                 div = 8;
7348                 break;
7349         default:
7350                 MISSING_CASE(divider);
7351                 return dev_priv->cdclk_pll.ref;
7352         }
7353
7354         return DIV_ROUND_CLOSEST(vco, div);
7355 }
7356
7357 static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7358 {
7359         uint32_t lcpll = I915_READ(LCPLL_CTL);
7360         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7361
7362         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7363                 return 800000;
7364         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7365                 return 450000;
7366         else if (freq == LCPLL_CLK_FREQ_450)
7367                 return 450000;
7368         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7369                 return 540000;
7370         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7371                 return 337500;
7372         else
7373                 return 675000;
7374 }
7375
7376 static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7377 {
7378         uint32_t lcpll = I915_READ(LCPLL_CTL);
7379         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7380
7381         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7382                 return 800000;
7383         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7384                 return 450000;
7385         else if (freq == LCPLL_CLK_FREQ_450)
7386                 return 450000;
7387         else if (IS_HSW_ULT(dev_priv))
7388                 return 337500;
7389         else
7390                 return 540000;
7391 }
7392
7393 static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv)
7394 {
7395         return vlv_get_cck_clock_hpll(dev_priv, "cdclk",
7396                                       CCK_DISPLAY_CLOCK_CONTROL);
7397 }
7398
7399 static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv)
7400 {
7401         return 450000;
7402 }
7403
7404 static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv)
7405 {
7406         return 400000;
7407 }
7408
7409 static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv)
7410 {
7411         return 333333;
7412 }
7413
7414 static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv)
7415 {
7416         return 200000;
7417 }
7418
7419 static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv)
7420 {
7421         struct pci_dev *pdev = dev_priv->drm.pdev;
7422         u16 gcfgc = 0;
7423
7424         pci_read_config_word(pdev, GCFGC, &gcfgc);
7425
7426         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7427         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7428                 return 266667;
7429         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7430                 return 333333;
7431         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7432                 return 444444;
7433         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7434                 return 200000;
7435         default:
7436                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7437         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7438                 return 133333;
7439         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7440                 return 166667;
7441         }
7442 }
7443
7444 static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7445 {
7446         struct pci_dev *pdev = dev_priv->drm.pdev;
7447         u16 gcfgc = 0;
7448
7449         pci_read_config_word(pdev, GCFGC, &gcfgc);
7450
7451         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7452                 return 133333;
7453         else {
7454                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7455                 case GC_DISPLAY_CLOCK_333_MHZ:
7456                         return 333333;
7457                 default:
7458                 case GC_DISPLAY_CLOCK_190_200_MHZ:
7459                         return 190000;
7460                 }
7461         }
7462 }
7463
7464 static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv)
7465 {
7466         return 266667;
7467 }
7468
7469 static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv)
7470 {
7471         struct pci_dev *pdev = dev_priv->drm.pdev;
7472         u16 hpllcc = 0;
7473
7474         /*
7475          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7476          * encoding is different :(
7477          * FIXME is this the right way to detect 852GM/852GMV?
7478          */
7479         if (pdev->revision == 0x1)
7480                 return 133333;
7481
7482         pci_bus_read_config_word(pdev->bus,
7483                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7484
7485         /* Assume that the hardware is in the high speed state.  This
7486          * should be the default.
7487          */
7488         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7489         case GC_CLOCK_133_200:
7490         case GC_CLOCK_133_200_2:
7491         case GC_CLOCK_100_200:
7492                 return 200000;
7493         case GC_CLOCK_166_250:
7494                 return 250000;
7495         case GC_CLOCK_100_133:
7496                 return 133333;
7497         case GC_CLOCK_133_266:
7498         case GC_CLOCK_133_266_2:
7499         case GC_CLOCK_166_266:
7500                 return 266667;
7501         }
7502
7503         /* Shouldn't happen */
7504         return 0;
7505 }
7506
7507 static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv)
7508 {
7509         return 133333;
7510 }
7511
7512 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
7513 {
7514         static const unsigned int blb_vco[8] = {
7515                 [0] = 3200000,
7516                 [1] = 4000000,
7517                 [2] = 5333333,
7518                 [3] = 4800000,
7519                 [4] = 6400000,
7520         };
7521         static const unsigned int pnv_vco[8] = {
7522                 [0] = 3200000,
7523                 [1] = 4000000,
7524                 [2] = 5333333,
7525                 [3] = 4800000,
7526                 [4] = 2666667,
7527         };
7528         static const unsigned int cl_vco[8] = {
7529                 [0] = 3200000,
7530                 [1] = 4000000,
7531                 [2] = 5333333,
7532                 [3] = 6400000,
7533                 [4] = 3333333,
7534                 [5] = 3566667,
7535                 [6] = 4266667,
7536         };
7537         static const unsigned int elk_vco[8] = {
7538                 [0] = 3200000,
7539                 [1] = 4000000,
7540                 [2] = 5333333,
7541                 [3] = 4800000,
7542         };
7543         static const unsigned int ctg_vco[8] = {
7544                 [0] = 3200000,
7545                 [1] = 4000000,
7546                 [2] = 5333333,
7547                 [3] = 6400000,
7548                 [4] = 2666667,
7549                 [5] = 4266667,
7550         };
7551         const unsigned int *vco_table;
7552         unsigned int vco;
7553         uint8_t tmp = 0;
7554
7555         /* FIXME other chipsets? */
7556         if (IS_GM45(dev_priv))
7557                 vco_table = ctg_vco;
7558         else if (IS_G4X(dev_priv))
7559                 vco_table = elk_vco;
7560         else if (IS_I965GM(dev_priv))
7561                 vco_table = cl_vco;
7562         else if (IS_PINEVIEW(dev_priv))
7563                 vco_table = pnv_vco;
7564         else if (IS_G33(dev_priv))
7565                 vco_table = blb_vco;
7566         else
7567                 return 0;
7568
7569         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
7570
7571         vco = vco_table[tmp & 0x7];
7572         if (vco == 0)
7573                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7574         else
7575                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7576
7577         return vco;
7578 }
7579
7580 static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv)
7581 {
7582         struct pci_dev *pdev = dev_priv->drm.pdev;
7583         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7584         uint16_t tmp = 0;
7585
7586         pci_read_config_word(pdev, GCFGC, &tmp);
7587
7588         cdclk_sel = (tmp >> 12) & 0x1;
7589
7590         switch (vco) {
7591         case 2666667:
7592         case 4000000:
7593         case 5333333:
7594                 return cdclk_sel ? 333333 : 222222;
7595         case 3200000:
7596                 return cdclk_sel ? 320000 : 228571;
7597         default:
7598                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7599                 return 222222;
7600         }
7601 }
7602
7603 static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7604 {
7605         struct pci_dev *pdev = dev_priv->drm.pdev;
7606         static const uint8_t div_3200[] = { 16, 10,  8 };
7607         static const uint8_t div_4000[] = { 20, 12, 10 };
7608         static const uint8_t div_5333[] = { 24, 16, 14 };
7609         const uint8_t *div_table;
7610         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7611         uint16_t tmp = 0;
7612
7613         pci_read_config_word(pdev, GCFGC, &tmp);
7614
7615         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7616
7617         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7618                 goto fail;
7619
7620         switch (vco) {
7621         case 3200000:
7622                 div_table = div_3200;
7623                 break;
7624         case 4000000:
7625                 div_table = div_4000;
7626                 break;
7627         case 5333333:
7628                 div_table = div_5333;
7629                 break;
7630         default:
7631                 goto fail;
7632         }
7633
7634         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7635
7636 fail:
7637         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7638         return 200000;
7639 }
7640
7641 static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv)
7642 {
7643         struct pci_dev *pdev = dev_priv->drm.pdev;
7644         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7645         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7646         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7647         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7648         const uint8_t *div_table;
7649         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7650         uint16_t tmp = 0;
7651
7652         pci_read_config_word(pdev, GCFGC, &tmp);
7653
7654         cdclk_sel = (tmp >> 4) & 0x7;
7655
7656         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7657                 goto fail;
7658
7659         switch (vco) {
7660         case 3200000:
7661                 div_table = div_3200;
7662                 break;
7663         case 4000000:
7664                 div_table = div_4000;
7665                 break;
7666         case 4800000:
7667                 div_table = div_4800;
7668                 break;
7669         case 5333333:
7670                 div_table = div_5333;
7671                 break;
7672         default:
7673                 goto fail;
7674         }
7675
7676         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7677
7678 fail:
7679         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7680         return 190476;
7681 }
7682
7683 static void
7684 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7685 {
7686         while (*num > DATA_LINK_M_N_MASK ||
7687                *den > DATA_LINK_M_N_MASK) {
7688                 *num >>= 1;
7689                 *den >>= 1;
7690         }
7691 }
7692
7693 static void compute_m_n(unsigned int m, unsigned int n,
7694                         uint32_t *ret_m, uint32_t *ret_n)
7695 {
7696         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7697         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7698         intel_reduce_m_n_ratio(ret_m, ret_n);
7699 }
7700
7701 void
7702 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7703                        int pixel_clock, int link_clock,
7704                        struct intel_link_m_n *m_n)
7705 {
7706         m_n->tu = 64;
7707
7708         compute_m_n(bits_per_pixel * pixel_clock,
7709                     link_clock * nlanes * 8,
7710                     &m_n->gmch_m, &m_n->gmch_n);
7711
7712         compute_m_n(pixel_clock, link_clock,
7713                     &m_n->link_m, &m_n->link_n);
7714 }
7715
7716 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7717 {
7718         if (i915.panel_use_ssc >= 0)
7719                 return i915.panel_use_ssc != 0;
7720         return dev_priv->vbt.lvds_use_ssc
7721                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7722 }
7723
7724 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7725 {
7726         return (1 << dpll->n) << 16 | dpll->m2;
7727 }
7728
7729 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7730 {
7731         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7732 }
7733
7734 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7735                                      struct intel_crtc_state *crtc_state,
7736                                      struct dpll *reduced_clock)
7737 {
7738         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7739         u32 fp, fp2 = 0;
7740
7741         if (IS_PINEVIEW(dev_priv)) {
7742                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7743                 if (reduced_clock)
7744                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7745         } else {
7746                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7747                 if (reduced_clock)
7748                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7749         }
7750
7751         crtc_state->dpll_hw_state.fp0 = fp;
7752
7753         crtc->lowfreq_avail = false;
7754         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7755             reduced_clock) {
7756                 crtc_state->dpll_hw_state.fp1 = fp2;
7757                 crtc->lowfreq_avail = true;
7758         } else {
7759                 crtc_state->dpll_hw_state.fp1 = fp;
7760         }
7761 }
7762
7763 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7764                 pipe)
7765 {
7766         u32 reg_val;
7767
7768         /*
7769          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7770          * and set it to a reasonable value instead.
7771          */
7772         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7773         reg_val &= 0xffffff00;
7774         reg_val |= 0x00000030;
7775         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7776
7777         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7778         reg_val &= 0x8cffffff;
7779         reg_val = 0x8c000000;
7780         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7781
7782         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7783         reg_val &= 0xffffff00;
7784         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7785
7786         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7787         reg_val &= 0x00ffffff;
7788         reg_val |= 0xb0000000;
7789         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7790 }
7791
7792 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7793                                          struct intel_link_m_n *m_n)
7794 {
7795         struct drm_device *dev = crtc->base.dev;
7796         struct drm_i915_private *dev_priv = to_i915(dev);
7797         int pipe = crtc->pipe;
7798
7799         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7800         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7801         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7802         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7803 }
7804
7805 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7806                                          struct intel_link_m_n *m_n,
7807                                          struct intel_link_m_n *m2_n2)
7808 {
7809         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7810         int pipe = crtc->pipe;
7811         enum transcoder transcoder = crtc->config->cpu_transcoder;
7812
7813         if (INTEL_GEN(dev_priv) >= 5) {
7814                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7815                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7816                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7817                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7818                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7819                  * for gen < 8) and if DRRS is supported (to make sure the
7820                  * registers are not unnecessarily accessed).
7821                  */
7822                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
7823                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
7824                         I915_WRITE(PIPE_DATA_M2(transcoder),
7825                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7826                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7827                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7828                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7829                 }
7830         } else {
7831                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7832                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7833                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7834                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7835         }
7836 }
7837
7838 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7839 {
7840         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7841
7842         if (m_n == M1_N1) {
7843                 dp_m_n = &crtc->config->dp_m_n;
7844                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7845         } else if (m_n == M2_N2) {
7846
7847                 /*
7848                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7849                  * needs to be programmed into M1_N1.
7850                  */
7851                 dp_m_n = &crtc->config->dp_m2_n2;
7852         } else {
7853                 DRM_ERROR("Unsupported divider value\n");
7854                 return;
7855         }
7856
7857         if (crtc->config->has_pch_encoder)
7858                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7859         else
7860                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7861 }
7862
7863 static void vlv_compute_dpll(struct intel_crtc *crtc,
7864                              struct intel_crtc_state *pipe_config)
7865 {
7866         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7867                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7868         if (crtc->pipe != PIPE_A)
7869                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7870
7871         /* DPLL not used with DSI, but still need the rest set up */
7872         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7873                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7874                         DPLL_EXT_BUFFER_ENABLE_VLV;
7875
7876         pipe_config->dpll_hw_state.dpll_md =
7877                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7878 }
7879
7880 static void chv_compute_dpll(struct intel_crtc *crtc,
7881                              struct intel_crtc_state *pipe_config)
7882 {
7883         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7884                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7885         if (crtc->pipe != PIPE_A)
7886                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7887
7888         /* DPLL not used with DSI, but still need the rest set up */
7889         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7890                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7891
7892         pipe_config->dpll_hw_state.dpll_md =
7893                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7894 }
7895
7896 static void vlv_prepare_pll(struct intel_crtc *crtc,
7897                             const struct intel_crtc_state *pipe_config)
7898 {
7899         struct drm_device *dev = crtc->base.dev;
7900         struct drm_i915_private *dev_priv = to_i915(dev);
7901         enum pipe pipe = crtc->pipe;
7902         u32 mdiv;
7903         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7904         u32 coreclk, reg_val;
7905
7906         /* Enable Refclk */
7907         I915_WRITE(DPLL(pipe),
7908                    pipe_config->dpll_hw_state.dpll &
7909                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7910
7911         /* No need to actually set up the DPLL with DSI */
7912         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7913                 return;
7914
7915         mutex_lock(&dev_priv->sb_lock);
7916
7917         bestn = pipe_config->dpll.n;
7918         bestm1 = pipe_config->dpll.m1;
7919         bestm2 = pipe_config->dpll.m2;
7920         bestp1 = pipe_config->dpll.p1;
7921         bestp2 = pipe_config->dpll.p2;
7922
7923         /* See eDP HDMI DPIO driver vbios notes doc */
7924
7925         /* PLL B needs special handling */
7926         if (pipe == PIPE_B)
7927                 vlv_pllb_recal_opamp(dev_priv, pipe);
7928
7929         /* Set up Tx target for periodic Rcomp update */
7930         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7931
7932         /* Disable target IRef on PLL */
7933         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7934         reg_val &= 0x00ffffff;
7935         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7936
7937         /* Disable fast lock */
7938         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7939
7940         /* Set idtafcrecal before PLL is enabled */
7941         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7942         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7943         mdiv |= ((bestn << DPIO_N_SHIFT));
7944         mdiv |= (1 << DPIO_K_SHIFT);
7945
7946         /*
7947          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7948          * but we don't support that).
7949          * Note: don't use the DAC post divider as it seems unstable.
7950          */
7951         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7952         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7953
7954         mdiv |= DPIO_ENABLE_CALIBRATION;
7955         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7956
7957         /* Set HBR and RBR LPF coefficients */
7958         if (pipe_config->port_clock == 162000 ||
7959             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7960             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7961                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7962                                  0x009f0003);
7963         else
7964                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7965                                  0x00d0000f);
7966
7967         if (intel_crtc_has_dp_encoder(pipe_config)) {
7968                 /* Use SSC source */
7969                 if (pipe == PIPE_A)
7970                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7971                                          0x0df40000);
7972                 else
7973                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7974                                          0x0df70000);
7975         } else { /* HDMI or VGA */
7976                 /* Use bend source */
7977                 if (pipe == PIPE_A)
7978                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7979                                          0x0df70000);
7980                 else
7981                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7982                                          0x0df40000);
7983         }
7984
7985         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7986         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7987         if (intel_crtc_has_dp_encoder(crtc->config))
7988                 coreclk |= 0x01000000;
7989         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7990
7991         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7992         mutex_unlock(&dev_priv->sb_lock);
7993 }
7994
7995 static void chv_prepare_pll(struct intel_crtc *crtc,
7996                             const struct intel_crtc_state *pipe_config)
7997 {
7998         struct drm_device *dev = crtc->base.dev;
7999         struct drm_i915_private *dev_priv = to_i915(dev);
8000         enum pipe pipe = crtc->pipe;
8001         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8002         u32 loopfilter, tribuf_calcntr;
8003         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8004         u32 dpio_val;
8005         int vco;
8006
8007         /* Enable Refclk and SSC */
8008         I915_WRITE(DPLL(pipe),
8009                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8010
8011         /* No need to actually set up the DPLL with DSI */
8012         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8013                 return;
8014
8015         bestn = pipe_config->dpll.n;
8016         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8017         bestm1 = pipe_config->dpll.m1;
8018         bestm2 = pipe_config->dpll.m2 >> 22;
8019         bestp1 = pipe_config->dpll.p1;
8020         bestp2 = pipe_config->dpll.p2;
8021         vco = pipe_config->dpll.vco;
8022         dpio_val = 0;
8023         loopfilter = 0;
8024
8025         mutex_lock(&dev_priv->sb_lock);
8026
8027         /* p1 and p2 divider */
8028         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8029                         5 << DPIO_CHV_S1_DIV_SHIFT |
8030                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8031                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8032                         1 << DPIO_CHV_K_DIV_SHIFT);
8033
8034         /* Feedback post-divider - m2 */
8035         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8036
8037         /* Feedback refclk divider - n and m1 */
8038         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8039                         DPIO_CHV_M1_DIV_BY_2 |
8040                         1 << DPIO_CHV_N_DIV_SHIFT);
8041
8042         /* M2 fraction division */
8043         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8044
8045         /* M2 fraction division enable */
8046         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8047         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8048         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8049         if (bestm2_frac)
8050                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8051         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8052
8053         /* Program digital lock detect threshold */
8054         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8055         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8056                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8057         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8058         if (!bestm2_frac)
8059                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8060         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8061
8062         /* Loop filter */
8063         if (vco == 5400000) {
8064                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8065                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8066                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8067                 tribuf_calcntr = 0x9;
8068         } else if (vco <= 6200000) {
8069                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8070                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8071                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8072                 tribuf_calcntr = 0x9;
8073         } else if (vco <= 6480000) {
8074                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8075                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8076                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8077                 tribuf_calcntr = 0x8;
8078         } else {
8079                 /* Not supported. Apply the same limits as in the max case */
8080                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8081                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8082                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8083                 tribuf_calcntr = 0;
8084         }
8085         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8086
8087         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8088         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8089         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8090         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8091
8092         /* AFC Recal */
8093         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8094                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8095                         DPIO_AFC_RECAL);
8096
8097         mutex_unlock(&dev_priv->sb_lock);
8098 }
8099
8100 /**
8101  * vlv_force_pll_on - forcibly enable just the PLL
8102  * @dev_priv: i915 private structure
8103  * @pipe: pipe PLL to enable
8104  * @dpll: PLL configuration
8105  *
8106  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8107  * in cases where we need the PLL enabled even when @pipe is not going to
8108  * be enabled.
8109  */
8110 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8111                      const struct dpll *dpll)
8112 {
8113         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8114         struct intel_crtc_state *pipe_config;
8115
8116         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8117         if (!pipe_config)
8118                 return -ENOMEM;
8119
8120         pipe_config->base.crtc = &crtc->base;
8121         pipe_config->pixel_multiplier = 1;
8122         pipe_config->dpll = *dpll;
8123
8124         if (IS_CHERRYVIEW(dev_priv)) {
8125                 chv_compute_dpll(crtc, pipe_config);
8126                 chv_prepare_pll(crtc, pipe_config);
8127                 chv_enable_pll(crtc, pipe_config);
8128         } else {
8129                 vlv_compute_dpll(crtc, pipe_config);
8130                 vlv_prepare_pll(crtc, pipe_config);
8131                 vlv_enable_pll(crtc, pipe_config);
8132         }
8133
8134         kfree(pipe_config);
8135
8136         return 0;
8137 }
8138
8139 /**
8140  * vlv_force_pll_off - forcibly disable just the PLL
8141  * @dev_priv: i915 private structure
8142  * @pipe: pipe PLL to disable
8143  *
8144  * Disable the PLL for @pipe. To be used in cases where we need
8145  * the PLL enabled even when @pipe is not going to be enabled.
8146  */
8147 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8148 {
8149         if (IS_CHERRYVIEW(dev_priv))
8150                 chv_disable_pll(dev_priv, pipe);
8151         else
8152                 vlv_disable_pll(dev_priv, pipe);
8153 }
8154
8155 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8156                               struct intel_crtc_state *crtc_state,
8157                               struct dpll *reduced_clock)
8158 {
8159         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8160         u32 dpll;
8161         struct dpll *clock = &crtc_state->dpll;
8162
8163         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8164
8165         dpll = DPLL_VGA_MODE_DIS;
8166
8167         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8168                 dpll |= DPLLB_MODE_LVDS;
8169         else
8170                 dpll |= DPLLB_MODE_DAC_SERIAL;
8171
8172         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8173             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8174                 dpll |= (crtc_state->pixel_multiplier - 1)
8175                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8176         }
8177
8178         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8179             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8180                 dpll |= DPLL_SDVO_HIGH_SPEED;
8181
8182         if (intel_crtc_has_dp_encoder(crtc_state))
8183                 dpll |= DPLL_SDVO_HIGH_SPEED;
8184
8185         /* compute bitmask from p1 value */
8186         if (IS_PINEVIEW(dev_priv))
8187                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8188         else {
8189                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8190                 if (IS_G4X(dev_priv) && reduced_clock)
8191                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8192         }
8193         switch (clock->p2) {
8194         case 5:
8195                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8196                 break;
8197         case 7:
8198                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8199                 break;
8200         case 10:
8201                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8202                 break;
8203         case 14:
8204                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8205                 break;
8206         }
8207         if (INTEL_GEN(dev_priv) >= 4)
8208                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8209
8210         if (crtc_state->sdvo_tv_clock)
8211                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8212         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8213                  intel_panel_use_ssc(dev_priv))
8214                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8215         else
8216                 dpll |= PLL_REF_INPUT_DREFCLK;
8217
8218         dpll |= DPLL_VCO_ENABLE;
8219         crtc_state->dpll_hw_state.dpll = dpll;
8220
8221         if (INTEL_GEN(dev_priv) >= 4) {
8222                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8223                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8224                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8225         }
8226 }
8227
8228 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8229                               struct intel_crtc_state *crtc_state,
8230                               struct dpll *reduced_clock)
8231 {
8232         struct drm_device *dev = crtc->base.dev;
8233         struct drm_i915_private *dev_priv = to_i915(dev);
8234         u32 dpll;
8235         struct dpll *clock = &crtc_state->dpll;
8236
8237         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8238
8239         dpll = DPLL_VGA_MODE_DIS;
8240
8241         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8242                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8243         } else {
8244                 if (clock->p1 == 2)
8245                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8246                 else
8247                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8248                 if (clock->p2 == 4)
8249                         dpll |= PLL_P2_DIVIDE_BY_4;
8250         }
8251
8252         if (!IS_I830(dev_priv) &&
8253             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8254                 dpll |= DPLL_DVO_2X_MODE;
8255
8256         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8257             intel_panel_use_ssc(dev_priv))
8258                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8259         else
8260                 dpll |= PLL_REF_INPUT_DREFCLK;
8261
8262         dpll |= DPLL_VCO_ENABLE;
8263         crtc_state->dpll_hw_state.dpll = dpll;
8264 }
8265
8266 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8267 {
8268         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8269         enum pipe pipe = intel_crtc->pipe;
8270         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8271         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8272         uint32_t crtc_vtotal, crtc_vblank_end;
8273         int vsyncshift = 0;
8274
8275         /* We need to be careful not to changed the adjusted mode, for otherwise
8276          * the hw state checker will get angry at the mismatch. */
8277         crtc_vtotal = adjusted_mode->crtc_vtotal;
8278         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8279
8280         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8281                 /* the chip adds 2 halflines automatically */
8282                 crtc_vtotal -= 1;
8283                 crtc_vblank_end -= 1;
8284
8285                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8286                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8287                 else
8288                         vsyncshift = adjusted_mode->crtc_hsync_start -
8289                                 adjusted_mode->crtc_htotal / 2;
8290                 if (vsyncshift < 0)
8291                         vsyncshift += adjusted_mode->crtc_htotal;
8292         }
8293
8294         if (INTEL_GEN(dev_priv) > 3)
8295                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8296
8297         I915_WRITE(HTOTAL(cpu_transcoder),
8298                    (adjusted_mode->crtc_hdisplay - 1) |
8299                    ((adjusted_mode->crtc_htotal - 1) << 16));
8300         I915_WRITE(HBLANK(cpu_transcoder),
8301                    (adjusted_mode->crtc_hblank_start - 1) |
8302                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8303         I915_WRITE(HSYNC(cpu_transcoder),
8304                    (adjusted_mode->crtc_hsync_start - 1) |
8305                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8306
8307         I915_WRITE(VTOTAL(cpu_transcoder),
8308                    (adjusted_mode->crtc_vdisplay - 1) |
8309                    ((crtc_vtotal - 1) << 16));
8310         I915_WRITE(VBLANK(cpu_transcoder),
8311                    (adjusted_mode->crtc_vblank_start - 1) |
8312                    ((crtc_vblank_end - 1) << 16));
8313         I915_WRITE(VSYNC(cpu_transcoder),
8314                    (adjusted_mode->crtc_vsync_start - 1) |
8315                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8316
8317         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8318          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8319          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8320          * bits. */
8321         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8322             (pipe == PIPE_B || pipe == PIPE_C))
8323                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8324
8325 }
8326
8327 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8328 {
8329         struct drm_device *dev = intel_crtc->base.dev;
8330         struct drm_i915_private *dev_priv = to_i915(dev);
8331         enum pipe pipe = intel_crtc->pipe;
8332
8333         /* pipesrc controls the size that is scaled from, which should
8334          * always be the user's requested size.
8335          */
8336         I915_WRITE(PIPESRC(pipe),
8337                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
8338                    (intel_crtc->config->pipe_src_h - 1));
8339 }
8340
8341 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8342                                    struct intel_crtc_state *pipe_config)
8343 {
8344         struct drm_device *dev = crtc->base.dev;
8345         struct drm_i915_private *dev_priv = to_i915(dev);
8346         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8347         uint32_t tmp;
8348
8349         tmp = I915_READ(HTOTAL(cpu_transcoder));
8350         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8351         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8352         tmp = I915_READ(HBLANK(cpu_transcoder));
8353         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8354         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8355         tmp = I915_READ(HSYNC(cpu_transcoder));
8356         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8357         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8358
8359         tmp = I915_READ(VTOTAL(cpu_transcoder));
8360         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8361         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8362         tmp = I915_READ(VBLANK(cpu_transcoder));
8363         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8364         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8365         tmp = I915_READ(VSYNC(cpu_transcoder));
8366         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8367         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8368
8369         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8370                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8371                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8372                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8373         }
8374 }
8375
8376 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8377                                     struct intel_crtc_state *pipe_config)
8378 {
8379         struct drm_device *dev = crtc->base.dev;
8380         struct drm_i915_private *dev_priv = to_i915(dev);
8381         u32 tmp;
8382
8383         tmp = I915_READ(PIPESRC(crtc->pipe));
8384         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8385         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8386
8387         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8388         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8389 }
8390
8391 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8392                                  struct intel_crtc_state *pipe_config)
8393 {
8394         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8395         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8396         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8397         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8398
8399         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8400         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8401         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8402         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8403
8404         mode->flags = pipe_config->base.adjusted_mode.flags;
8405         mode->type = DRM_MODE_TYPE_DRIVER;
8406
8407         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8408         mode->flags |= pipe_config->base.adjusted_mode.flags;
8409
8410         mode->hsync = drm_mode_hsync(mode);
8411         mode->vrefresh = drm_mode_vrefresh(mode);
8412         drm_mode_set_name(mode);
8413 }
8414
8415 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8416 {
8417         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8418         uint32_t pipeconf;
8419
8420         pipeconf = 0;
8421
8422         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8423             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8424                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8425
8426         if (intel_crtc->config->double_wide)
8427                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8428
8429         /* only g4x and later have fancy bpc/dither controls */
8430         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8431             IS_CHERRYVIEW(dev_priv)) {
8432                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8433                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8434                         pipeconf |= PIPECONF_DITHER_EN |
8435                                     PIPECONF_DITHER_TYPE_SP;
8436
8437                 switch (intel_crtc->config->pipe_bpp) {
8438                 case 18:
8439                         pipeconf |= PIPECONF_6BPC;
8440                         break;
8441                 case 24:
8442                         pipeconf |= PIPECONF_8BPC;
8443                         break;
8444                 case 30:
8445                         pipeconf |= PIPECONF_10BPC;
8446                         break;
8447                 default:
8448                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8449                         BUG();
8450                 }
8451         }
8452
8453         if (HAS_PIPE_CXSR(dev_priv)) {
8454                 if (intel_crtc->lowfreq_avail) {
8455                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8456                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8457                 } else {
8458                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8459                 }
8460         }
8461
8462         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8463                 if (INTEL_GEN(dev_priv) < 4 ||
8464                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8465                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8466                 else
8467                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8468         } else
8469                 pipeconf |= PIPECONF_PROGRESSIVE;
8470
8471         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8472              intel_crtc->config->limited_color_range)
8473                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8474
8475         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8476         POSTING_READ(PIPECONF(intel_crtc->pipe));
8477 }
8478
8479 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8480                                    struct intel_crtc_state *crtc_state)
8481 {
8482         struct drm_device *dev = crtc->base.dev;
8483         struct drm_i915_private *dev_priv = to_i915(dev);
8484         const struct intel_limit *limit;
8485         int refclk = 48000;
8486
8487         memset(&crtc_state->dpll_hw_state, 0,
8488                sizeof(crtc_state->dpll_hw_state));
8489
8490         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8491                 if (intel_panel_use_ssc(dev_priv)) {
8492                         refclk = dev_priv->vbt.lvds_ssc_freq;
8493                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8494                 }
8495
8496                 limit = &intel_limits_i8xx_lvds;
8497         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8498                 limit = &intel_limits_i8xx_dvo;
8499         } else {
8500                 limit = &intel_limits_i8xx_dac;
8501         }
8502
8503         if (!crtc_state->clock_set &&
8504             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8505                                  refclk, NULL, &crtc_state->dpll)) {
8506                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8507                 return -EINVAL;
8508         }
8509
8510         i8xx_compute_dpll(crtc, crtc_state, NULL);
8511
8512         return 0;
8513 }
8514
8515 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8516                                   struct intel_crtc_state *crtc_state)
8517 {
8518         struct drm_device *dev = crtc->base.dev;
8519         struct drm_i915_private *dev_priv = to_i915(dev);
8520         const struct intel_limit *limit;
8521         int refclk = 96000;
8522
8523         memset(&crtc_state->dpll_hw_state, 0,
8524                sizeof(crtc_state->dpll_hw_state));
8525
8526         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8527                 if (intel_panel_use_ssc(dev_priv)) {
8528                         refclk = dev_priv->vbt.lvds_ssc_freq;
8529                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8530                 }
8531
8532                 if (intel_is_dual_link_lvds(dev))
8533                         limit = &intel_limits_g4x_dual_channel_lvds;
8534                 else
8535                         limit = &intel_limits_g4x_single_channel_lvds;
8536         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8537                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8538                 limit = &intel_limits_g4x_hdmi;
8539         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8540                 limit = &intel_limits_g4x_sdvo;
8541         } else {
8542                 /* The option is for other outputs */
8543                 limit = &intel_limits_i9xx_sdvo;
8544         }
8545
8546         if (!crtc_state->clock_set &&
8547             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8548                                 refclk, NULL, &crtc_state->dpll)) {
8549                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8550                 return -EINVAL;
8551         }
8552
8553         i9xx_compute_dpll(crtc, crtc_state, NULL);
8554
8555         return 0;
8556 }
8557
8558 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8559                                   struct intel_crtc_state *crtc_state)
8560 {
8561         struct drm_device *dev = crtc->base.dev;
8562         struct drm_i915_private *dev_priv = to_i915(dev);
8563         const struct intel_limit *limit;
8564         int refclk = 96000;
8565
8566         memset(&crtc_state->dpll_hw_state, 0,
8567                sizeof(crtc_state->dpll_hw_state));
8568
8569         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8570                 if (intel_panel_use_ssc(dev_priv)) {
8571                         refclk = dev_priv->vbt.lvds_ssc_freq;
8572                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8573                 }
8574
8575                 limit = &intel_limits_pineview_lvds;
8576         } else {
8577                 limit = &intel_limits_pineview_sdvo;
8578         }
8579
8580         if (!crtc_state->clock_set &&
8581             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8582                                 refclk, NULL, &crtc_state->dpll)) {
8583                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8584                 return -EINVAL;
8585         }
8586
8587         i9xx_compute_dpll(crtc, crtc_state, NULL);
8588
8589         return 0;
8590 }
8591
8592 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8593                                    struct intel_crtc_state *crtc_state)
8594 {
8595         struct drm_device *dev = crtc->base.dev;
8596         struct drm_i915_private *dev_priv = to_i915(dev);
8597         const struct intel_limit *limit;
8598         int refclk = 96000;
8599
8600         memset(&crtc_state->dpll_hw_state, 0,
8601                sizeof(crtc_state->dpll_hw_state));
8602
8603         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8604                 if (intel_panel_use_ssc(dev_priv)) {
8605                         refclk = dev_priv->vbt.lvds_ssc_freq;
8606                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8607                 }
8608
8609                 limit = &intel_limits_i9xx_lvds;
8610         } else {
8611                 limit = &intel_limits_i9xx_sdvo;
8612         }
8613
8614         if (!crtc_state->clock_set &&
8615             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8616                                  refclk, NULL, &crtc_state->dpll)) {
8617                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8618                 return -EINVAL;
8619         }
8620
8621         i9xx_compute_dpll(crtc, crtc_state, NULL);
8622
8623         return 0;
8624 }
8625
8626 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8627                                   struct intel_crtc_state *crtc_state)
8628 {
8629         int refclk = 100000;
8630         const struct intel_limit *limit = &intel_limits_chv;
8631
8632         memset(&crtc_state->dpll_hw_state, 0,
8633                sizeof(crtc_state->dpll_hw_state));
8634
8635         if (!crtc_state->clock_set &&
8636             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8637                                 refclk, NULL, &crtc_state->dpll)) {
8638                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8639                 return -EINVAL;
8640         }
8641
8642         chv_compute_dpll(crtc, crtc_state);
8643
8644         return 0;
8645 }
8646
8647 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8648                                   struct intel_crtc_state *crtc_state)
8649 {
8650         int refclk = 100000;
8651         const struct intel_limit *limit = &intel_limits_vlv;
8652
8653         memset(&crtc_state->dpll_hw_state, 0,
8654                sizeof(crtc_state->dpll_hw_state));
8655
8656         if (!crtc_state->clock_set &&
8657             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8658                                 refclk, NULL, &crtc_state->dpll)) {
8659                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8660                 return -EINVAL;
8661         }
8662
8663         vlv_compute_dpll(crtc, crtc_state);
8664
8665         return 0;
8666 }
8667
8668 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8669                                  struct intel_crtc_state *pipe_config)
8670 {
8671         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8672         uint32_t tmp;
8673
8674         if (INTEL_GEN(dev_priv) <= 3 &&
8675             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
8676                 return;
8677
8678         tmp = I915_READ(PFIT_CONTROL);
8679         if (!(tmp & PFIT_ENABLE))
8680                 return;
8681
8682         /* Check whether the pfit is attached to our pipe. */
8683         if (INTEL_GEN(dev_priv) < 4) {
8684                 if (crtc->pipe != PIPE_B)
8685                         return;
8686         } else {
8687                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8688                         return;
8689         }
8690
8691         pipe_config->gmch_pfit.control = tmp;
8692         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8693 }
8694
8695 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8696                                struct intel_crtc_state *pipe_config)
8697 {
8698         struct drm_device *dev = crtc->base.dev;
8699         struct drm_i915_private *dev_priv = to_i915(dev);
8700         int pipe = pipe_config->cpu_transcoder;
8701         struct dpll clock;
8702         u32 mdiv;
8703         int refclk = 100000;
8704
8705         /* In case of DSI, DPLL will not be used */
8706         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8707                 return;
8708
8709         mutex_lock(&dev_priv->sb_lock);
8710         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8711         mutex_unlock(&dev_priv->sb_lock);
8712
8713         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8714         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8715         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8716         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8717         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8718
8719         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8720 }
8721
8722 static void
8723 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8724                               struct intel_initial_plane_config *plane_config)
8725 {
8726         struct drm_device *dev = crtc->base.dev;
8727         struct drm_i915_private *dev_priv = to_i915(dev);
8728         u32 val, base, offset;
8729         int pipe = crtc->pipe, plane = crtc->plane;
8730         int fourcc, pixel_format;
8731         unsigned int aligned_height;
8732         struct drm_framebuffer *fb;
8733         struct intel_framebuffer *intel_fb;
8734
8735         val = I915_READ(DSPCNTR(plane));
8736         if (!(val & DISPLAY_PLANE_ENABLE))
8737                 return;
8738
8739         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8740         if (!intel_fb) {
8741                 DRM_DEBUG_KMS("failed to alloc fb\n");
8742                 return;
8743         }
8744
8745         fb = &intel_fb->base;
8746
8747         if (INTEL_GEN(dev_priv) >= 4) {
8748                 if (val & DISPPLANE_TILED) {
8749                         plane_config->tiling = I915_TILING_X;
8750                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8751                 }
8752         }
8753
8754         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8755         fourcc = i9xx_format_to_fourcc(pixel_format);
8756         fb->pixel_format = fourcc;
8757         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8758
8759         if (INTEL_GEN(dev_priv) >= 4) {
8760                 if (plane_config->tiling)
8761                         offset = I915_READ(DSPTILEOFF(plane));
8762                 else
8763                         offset = I915_READ(DSPLINOFF(plane));
8764                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8765         } else {
8766                 base = I915_READ(DSPADDR(plane));
8767         }
8768         plane_config->base = base;
8769
8770         val = I915_READ(PIPESRC(pipe));
8771         fb->width = ((val >> 16) & 0xfff) + 1;
8772         fb->height = ((val >> 0) & 0xfff) + 1;
8773
8774         val = I915_READ(DSPSTRIDE(pipe));
8775         fb->pitches[0] = val & 0xffffffc0;
8776
8777         aligned_height = intel_fb_align_height(dev, fb->height,
8778                                                fb->pixel_format,
8779                                                fb->modifier);
8780
8781         plane_config->size = fb->pitches[0] * aligned_height;
8782
8783         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8784                       pipe_name(pipe), plane, fb->width, fb->height,
8785                       fb->bits_per_pixel, base, fb->pitches[0],
8786                       plane_config->size);
8787
8788         plane_config->fb = intel_fb;
8789 }
8790
8791 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8792                                struct intel_crtc_state *pipe_config)
8793 {
8794         struct drm_device *dev = crtc->base.dev;
8795         struct drm_i915_private *dev_priv = to_i915(dev);
8796         int pipe = pipe_config->cpu_transcoder;
8797         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8798         struct dpll clock;
8799         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8800         int refclk = 100000;
8801
8802         /* In case of DSI, DPLL will not be used */
8803         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8804                 return;
8805
8806         mutex_lock(&dev_priv->sb_lock);
8807         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8808         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8809         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8810         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8811         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8812         mutex_unlock(&dev_priv->sb_lock);
8813
8814         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8815         clock.m2 = (pll_dw0 & 0xff) << 22;
8816         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8817                 clock.m2 |= pll_dw2 & 0x3fffff;
8818         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8819         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8820         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8821
8822         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8823 }
8824
8825 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8826                                  struct intel_crtc_state *pipe_config)
8827 {
8828         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8829         enum intel_display_power_domain power_domain;
8830         uint32_t tmp;
8831         bool ret;
8832
8833         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8834         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8835                 return false;
8836
8837         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8838         pipe_config->shared_dpll = NULL;
8839
8840         ret = false;
8841
8842         tmp = I915_READ(PIPECONF(crtc->pipe));
8843         if (!(tmp & PIPECONF_ENABLE))
8844                 goto out;
8845
8846         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8847             IS_CHERRYVIEW(dev_priv)) {
8848                 switch (tmp & PIPECONF_BPC_MASK) {
8849                 case PIPECONF_6BPC:
8850                         pipe_config->pipe_bpp = 18;
8851                         break;
8852                 case PIPECONF_8BPC:
8853                         pipe_config->pipe_bpp = 24;
8854                         break;
8855                 case PIPECONF_10BPC:
8856                         pipe_config->pipe_bpp = 30;
8857                         break;
8858                 default:
8859                         break;
8860                 }
8861         }
8862
8863         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8864             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8865                 pipe_config->limited_color_range = true;
8866
8867         if (INTEL_GEN(dev_priv) < 4)
8868                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8869
8870         intel_get_pipe_timings(crtc, pipe_config);
8871         intel_get_pipe_src_size(crtc, pipe_config);
8872
8873         i9xx_get_pfit_config(crtc, pipe_config);
8874
8875         if (INTEL_GEN(dev_priv) >= 4) {
8876                 /* No way to read it out on pipes B and C */
8877                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8878                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8879                 else
8880                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8881                 pipe_config->pixel_multiplier =
8882                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8883                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8884                 pipe_config->dpll_hw_state.dpll_md = tmp;
8885         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8886                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8887                 tmp = I915_READ(DPLL(crtc->pipe));
8888                 pipe_config->pixel_multiplier =
8889                         ((tmp & SDVO_MULTIPLIER_MASK)
8890                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8891         } else {
8892                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8893                  * port and will be fixed up in the encoder->get_config
8894                  * function. */
8895                 pipe_config->pixel_multiplier = 1;
8896         }
8897         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8898         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8899                 /*
8900                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8901                  * on 830. Filter it out here so that we don't
8902                  * report errors due to that.
8903                  */
8904                 if (IS_I830(dev_priv))
8905                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8906
8907                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8908                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8909         } else {
8910                 /* Mask out read-only status bits. */
8911                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8912                                                      DPLL_PORTC_READY_MASK |
8913                                                      DPLL_PORTB_READY_MASK);
8914         }
8915
8916         if (IS_CHERRYVIEW(dev_priv))
8917                 chv_crtc_clock_get(crtc, pipe_config);
8918         else if (IS_VALLEYVIEW(dev_priv))
8919                 vlv_crtc_clock_get(crtc, pipe_config);
8920         else
8921                 i9xx_crtc_clock_get(crtc, pipe_config);
8922
8923         /*
8924          * Normally the dotclock is filled in by the encoder .get_config()
8925          * but in case the pipe is enabled w/o any ports we need a sane
8926          * default.
8927          */
8928         pipe_config->base.adjusted_mode.crtc_clock =
8929                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8930
8931         ret = true;
8932
8933 out:
8934         intel_display_power_put(dev_priv, power_domain);
8935
8936         return ret;
8937 }
8938
8939 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
8940 {
8941         struct intel_encoder *encoder;
8942         int i;
8943         u32 val, final;
8944         bool has_lvds = false;
8945         bool has_cpu_edp = false;
8946         bool has_panel = false;
8947         bool has_ck505 = false;
8948         bool can_ssc = false;
8949         bool using_ssc_source = false;
8950
8951         /* We need to take the global config into account */
8952         for_each_intel_encoder(&dev_priv->drm, encoder) {
8953                 switch (encoder->type) {
8954                 case INTEL_OUTPUT_LVDS:
8955                         has_panel = true;
8956                         has_lvds = true;
8957                         break;
8958                 case INTEL_OUTPUT_EDP:
8959                         has_panel = true;
8960                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8961                                 has_cpu_edp = true;
8962                         break;
8963                 default:
8964                         break;
8965                 }
8966         }
8967
8968         if (HAS_PCH_IBX(dev_priv)) {
8969                 has_ck505 = dev_priv->vbt.display_clock_mode;
8970                 can_ssc = has_ck505;
8971         } else {
8972                 has_ck505 = false;
8973                 can_ssc = true;
8974         }
8975
8976         /* Check if any DPLLs are using the SSC source */
8977         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8978                 u32 temp = I915_READ(PCH_DPLL(i));
8979
8980                 if (!(temp & DPLL_VCO_ENABLE))
8981                         continue;
8982
8983                 if ((temp & PLL_REF_INPUT_MASK) ==
8984                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8985                         using_ssc_source = true;
8986                         break;
8987                 }
8988         }
8989
8990         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8991                       has_panel, has_lvds, has_ck505, using_ssc_source);
8992
8993         /* Ironlake: try to setup display ref clock before DPLL
8994          * enabling. This is only under driver's control after
8995          * PCH B stepping, previous chipset stepping should be
8996          * ignoring this setting.
8997          */
8998         val = I915_READ(PCH_DREF_CONTROL);
8999
9000         /* As we must carefully and slowly disable/enable each source in turn,
9001          * compute the final state we want first and check if we need to
9002          * make any changes at all.
9003          */
9004         final = val;
9005         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9006         if (has_ck505)
9007                 final |= DREF_NONSPREAD_CK505_ENABLE;
9008         else
9009                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9010
9011         final &= ~DREF_SSC_SOURCE_MASK;
9012         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9013         final &= ~DREF_SSC1_ENABLE;
9014
9015         if (has_panel) {
9016                 final |= DREF_SSC_SOURCE_ENABLE;
9017
9018                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9019                         final |= DREF_SSC1_ENABLE;
9020
9021                 if (has_cpu_edp) {
9022                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9023                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9024                         else
9025                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9026                 } else
9027                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9028         } else if (using_ssc_source) {
9029                 final |= DREF_SSC_SOURCE_ENABLE;
9030                 final |= DREF_SSC1_ENABLE;
9031         }
9032
9033         if (final == val)
9034                 return;
9035
9036         /* Always enable nonspread source */
9037         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9038
9039         if (has_ck505)
9040                 val |= DREF_NONSPREAD_CK505_ENABLE;
9041         else
9042                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9043
9044         if (has_panel) {
9045                 val &= ~DREF_SSC_SOURCE_MASK;
9046                 val |= DREF_SSC_SOURCE_ENABLE;
9047
9048                 /* SSC must be turned on before enabling the CPU output  */
9049                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9050                         DRM_DEBUG_KMS("Using SSC on panel\n");
9051                         val |= DREF_SSC1_ENABLE;
9052                 } else
9053                         val &= ~DREF_SSC1_ENABLE;
9054
9055                 /* Get SSC going before enabling the outputs */
9056                 I915_WRITE(PCH_DREF_CONTROL, val);
9057                 POSTING_READ(PCH_DREF_CONTROL);
9058                 udelay(200);
9059
9060                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9061
9062                 /* Enable CPU source on CPU attached eDP */
9063                 if (has_cpu_edp) {
9064                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9065                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9066                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9067                         } else
9068                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9069                 } else
9070                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9071
9072                 I915_WRITE(PCH_DREF_CONTROL, val);
9073                 POSTING_READ(PCH_DREF_CONTROL);
9074                 udelay(200);
9075         } else {
9076                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9077
9078                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9079
9080                 /* Turn off CPU output */
9081                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9082
9083                 I915_WRITE(PCH_DREF_CONTROL, val);
9084                 POSTING_READ(PCH_DREF_CONTROL);
9085                 udelay(200);
9086
9087                 if (!using_ssc_source) {
9088                         DRM_DEBUG_KMS("Disabling SSC source\n");
9089
9090                         /* Turn off the SSC source */
9091                         val &= ~DREF_SSC_SOURCE_MASK;
9092                         val |= DREF_SSC_SOURCE_DISABLE;
9093
9094                         /* Turn off SSC1 */
9095                         val &= ~DREF_SSC1_ENABLE;
9096
9097                         I915_WRITE(PCH_DREF_CONTROL, val);
9098                         POSTING_READ(PCH_DREF_CONTROL);
9099                         udelay(200);
9100                 }
9101         }
9102
9103         BUG_ON(val != final);
9104 }
9105
9106 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9107 {
9108         uint32_t tmp;
9109
9110         tmp = I915_READ(SOUTH_CHICKEN2);
9111         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9112         I915_WRITE(SOUTH_CHICKEN2, tmp);
9113
9114         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9115                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9116                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9117
9118         tmp = I915_READ(SOUTH_CHICKEN2);
9119         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9120         I915_WRITE(SOUTH_CHICKEN2, tmp);
9121
9122         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9123                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9124                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9125 }
9126
9127 /* WaMPhyProgramming:hsw */
9128 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9129 {
9130         uint32_t tmp;
9131
9132         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9133         tmp &= ~(0xFF << 24);
9134         tmp |= (0x12 << 24);
9135         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9136
9137         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9138         tmp |= (1 << 11);
9139         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9140
9141         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9142         tmp |= (1 << 11);
9143         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9144
9145         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9146         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9147         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9148
9149         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9150         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9151         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9152
9153         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9154         tmp &= ~(7 << 13);
9155         tmp |= (5 << 13);
9156         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9157
9158         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9159         tmp &= ~(7 << 13);
9160         tmp |= (5 << 13);
9161         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9162
9163         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9164         tmp &= ~0xFF;
9165         tmp |= 0x1C;
9166         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9167
9168         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9169         tmp &= ~0xFF;
9170         tmp |= 0x1C;
9171         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9172
9173         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9174         tmp &= ~(0xFF << 16);
9175         tmp |= (0x1C << 16);
9176         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9177
9178         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9179         tmp &= ~(0xFF << 16);
9180         tmp |= (0x1C << 16);
9181         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9182
9183         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9184         tmp |= (1 << 27);
9185         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9186
9187         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9188         tmp |= (1 << 27);
9189         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9190
9191         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9192         tmp &= ~(0xF << 28);
9193         tmp |= (4 << 28);
9194         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9195
9196         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9197         tmp &= ~(0xF << 28);
9198         tmp |= (4 << 28);
9199         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9200 }
9201
9202 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9203  * Programming" based on the parameters passed:
9204  * - Sequence to enable CLKOUT_DP
9205  * - Sequence to enable CLKOUT_DP without spread
9206  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9207  */
9208 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9209                                  bool with_spread, bool with_fdi)
9210 {
9211         uint32_t reg, tmp;
9212
9213         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9214                 with_spread = true;
9215         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9216             with_fdi, "LP PCH doesn't have FDI\n"))
9217                 with_fdi = false;
9218
9219         mutex_lock(&dev_priv->sb_lock);
9220
9221         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9222         tmp &= ~SBI_SSCCTL_DISABLE;
9223         tmp |= SBI_SSCCTL_PATHALT;
9224         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9225
9226         udelay(24);
9227
9228         if (with_spread) {
9229                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9230                 tmp &= ~SBI_SSCCTL_PATHALT;
9231                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9232
9233                 if (with_fdi) {
9234                         lpt_reset_fdi_mphy(dev_priv);
9235                         lpt_program_fdi_mphy(dev_priv);
9236                 }
9237         }
9238
9239         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9240         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9241         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9242         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9243
9244         mutex_unlock(&dev_priv->sb_lock);
9245 }
9246
9247 /* Sequence to disable CLKOUT_DP */
9248 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9249 {
9250         uint32_t reg, tmp;
9251
9252         mutex_lock(&dev_priv->sb_lock);
9253
9254         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9255         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9256         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9257         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9258
9259         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9260         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9261                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9262                         tmp |= SBI_SSCCTL_PATHALT;
9263                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9264                         udelay(32);
9265                 }
9266                 tmp |= SBI_SSCCTL_DISABLE;
9267                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9268         }
9269
9270         mutex_unlock(&dev_priv->sb_lock);
9271 }
9272
9273 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9274
9275 static const uint16_t sscdivintphase[] = {
9276         [BEND_IDX( 50)] = 0x3B23,
9277         [BEND_IDX( 45)] = 0x3B23,
9278         [BEND_IDX( 40)] = 0x3C23,
9279         [BEND_IDX( 35)] = 0x3C23,
9280         [BEND_IDX( 30)] = 0x3D23,
9281         [BEND_IDX( 25)] = 0x3D23,
9282         [BEND_IDX( 20)] = 0x3E23,
9283         [BEND_IDX( 15)] = 0x3E23,
9284         [BEND_IDX( 10)] = 0x3F23,
9285         [BEND_IDX(  5)] = 0x3F23,
9286         [BEND_IDX(  0)] = 0x0025,
9287         [BEND_IDX( -5)] = 0x0025,
9288         [BEND_IDX(-10)] = 0x0125,
9289         [BEND_IDX(-15)] = 0x0125,
9290         [BEND_IDX(-20)] = 0x0225,
9291         [BEND_IDX(-25)] = 0x0225,
9292         [BEND_IDX(-30)] = 0x0325,
9293         [BEND_IDX(-35)] = 0x0325,
9294         [BEND_IDX(-40)] = 0x0425,
9295         [BEND_IDX(-45)] = 0x0425,
9296         [BEND_IDX(-50)] = 0x0525,
9297 };
9298
9299 /*
9300  * Bend CLKOUT_DP
9301  * steps -50 to 50 inclusive, in steps of 5
9302  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9303  * change in clock period = -(steps / 10) * 5.787 ps
9304  */
9305 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9306 {
9307         uint32_t tmp;
9308         int idx = BEND_IDX(steps);
9309
9310         if (WARN_ON(steps % 5 != 0))
9311                 return;
9312
9313         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9314                 return;
9315
9316         mutex_lock(&dev_priv->sb_lock);
9317
9318         if (steps % 10 != 0)
9319                 tmp = 0xAAAAAAAB;
9320         else
9321                 tmp = 0x00000000;
9322         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9323
9324         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9325         tmp &= 0xffff0000;
9326         tmp |= sscdivintphase[idx];
9327         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9328
9329         mutex_unlock(&dev_priv->sb_lock);
9330 }
9331
9332 #undef BEND_IDX
9333
9334 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9335 {
9336         struct intel_encoder *encoder;
9337         bool has_vga = false;
9338
9339         for_each_intel_encoder(&dev_priv->drm, encoder) {
9340                 switch (encoder->type) {
9341                 case INTEL_OUTPUT_ANALOG:
9342                         has_vga = true;
9343                         break;
9344                 default:
9345                         break;
9346                 }
9347         }
9348
9349         if (has_vga) {
9350                 lpt_bend_clkout_dp(dev_priv, 0);
9351                 lpt_enable_clkout_dp(dev_priv, true, true);
9352         } else {
9353                 lpt_disable_clkout_dp(dev_priv);
9354         }
9355 }
9356
9357 /*
9358  * Initialize reference clocks when the driver loads
9359  */
9360 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9361 {
9362         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9363                 ironlake_init_pch_refclk(dev_priv);
9364         else if (HAS_PCH_LPT(dev_priv))
9365                 lpt_init_pch_refclk(dev_priv);
9366 }
9367
9368 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9369 {
9370         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9372         int pipe = intel_crtc->pipe;
9373         uint32_t val;
9374
9375         val = 0;
9376
9377         switch (intel_crtc->config->pipe_bpp) {
9378         case 18:
9379                 val |= PIPECONF_6BPC;
9380                 break;
9381         case 24:
9382                 val |= PIPECONF_8BPC;
9383                 break;
9384         case 30:
9385                 val |= PIPECONF_10BPC;
9386                 break;
9387         case 36:
9388                 val |= PIPECONF_12BPC;
9389                 break;
9390         default:
9391                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9392                 BUG();
9393         }
9394
9395         if (intel_crtc->config->dither)
9396                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9397
9398         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9399                 val |= PIPECONF_INTERLACED_ILK;
9400         else
9401                 val |= PIPECONF_PROGRESSIVE;
9402
9403         if (intel_crtc->config->limited_color_range)
9404                 val |= PIPECONF_COLOR_RANGE_SELECT;
9405
9406         I915_WRITE(PIPECONF(pipe), val);
9407         POSTING_READ(PIPECONF(pipe));
9408 }
9409
9410 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9411 {
9412         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9414         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9415         u32 val = 0;
9416
9417         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9418                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9419
9420         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9421                 val |= PIPECONF_INTERLACED_ILK;
9422         else
9423                 val |= PIPECONF_PROGRESSIVE;
9424
9425         I915_WRITE(PIPECONF(cpu_transcoder), val);
9426         POSTING_READ(PIPECONF(cpu_transcoder));
9427 }
9428
9429 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9430 {
9431         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9432         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9433
9434         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9435                 u32 val = 0;
9436
9437                 switch (intel_crtc->config->pipe_bpp) {
9438                 case 18:
9439                         val |= PIPEMISC_DITHER_6_BPC;
9440                         break;
9441                 case 24:
9442                         val |= PIPEMISC_DITHER_8_BPC;
9443                         break;
9444                 case 30:
9445                         val |= PIPEMISC_DITHER_10_BPC;
9446                         break;
9447                 case 36:
9448                         val |= PIPEMISC_DITHER_12_BPC;
9449                         break;
9450                 default:
9451                         /* Case prevented by pipe_config_set_bpp. */
9452                         BUG();
9453                 }
9454
9455                 if (intel_crtc->config->dither)
9456                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9457
9458                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9459         }
9460 }
9461
9462 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9463 {
9464         /*
9465          * Account for spread spectrum to avoid
9466          * oversubscribing the link. Max center spread
9467          * is 2.5%; use 5% for safety's sake.
9468          */
9469         u32 bps = target_clock * bpp * 21 / 20;
9470         return DIV_ROUND_UP(bps, link_bw * 8);
9471 }
9472
9473 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9474 {
9475         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9476 }
9477
9478 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9479                                   struct intel_crtc_state *crtc_state,
9480                                   struct dpll *reduced_clock)
9481 {
9482         struct drm_crtc *crtc = &intel_crtc->base;
9483         struct drm_device *dev = crtc->dev;
9484         struct drm_i915_private *dev_priv = to_i915(dev);
9485         u32 dpll, fp, fp2;
9486         int factor;
9487
9488         /* Enable autotuning of the PLL clock (if permissible) */
9489         factor = 21;
9490         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9491                 if ((intel_panel_use_ssc(dev_priv) &&
9492                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9493                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
9494                         factor = 25;
9495         } else if (crtc_state->sdvo_tv_clock)
9496                 factor = 20;
9497
9498         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9499
9500         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9501                 fp |= FP_CB_TUNE;
9502
9503         if (reduced_clock) {
9504                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9505
9506                 if (reduced_clock->m < factor * reduced_clock->n)
9507                         fp2 |= FP_CB_TUNE;
9508         } else {
9509                 fp2 = fp;
9510         }
9511
9512         dpll = 0;
9513
9514         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9515                 dpll |= DPLLB_MODE_LVDS;
9516         else
9517                 dpll |= DPLLB_MODE_DAC_SERIAL;
9518
9519         dpll |= (crtc_state->pixel_multiplier - 1)
9520                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9521
9522         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9523             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9524                 dpll |= DPLL_SDVO_HIGH_SPEED;
9525
9526         if (intel_crtc_has_dp_encoder(crtc_state))
9527                 dpll |= DPLL_SDVO_HIGH_SPEED;
9528
9529         /*
9530          * The high speed IO clock is only really required for
9531          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9532          * possible to share the DPLL between CRT and HDMI. Enabling
9533          * the clock needlessly does no real harm, except use up a
9534          * bit of power potentially.
9535          *
9536          * We'll limit this to IVB with 3 pipes, since it has only two
9537          * DPLLs and so DPLL sharing is the only way to get three pipes
9538          * driving PCH ports at the same time. On SNB we could do this,
9539          * and potentially avoid enabling the second DPLL, but it's not
9540          * clear if it''s a win or loss power wise. No point in doing
9541          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9542          */
9543         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9544             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9545                 dpll |= DPLL_SDVO_HIGH_SPEED;
9546
9547         /* compute bitmask from p1 value */
9548         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9549         /* also FPA1 */
9550         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9551
9552         switch (crtc_state->dpll.p2) {
9553         case 5:
9554                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9555                 break;
9556         case 7:
9557                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9558                 break;
9559         case 10:
9560                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9561                 break;
9562         case 14:
9563                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9564                 break;
9565         }
9566
9567         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9568             intel_panel_use_ssc(dev_priv))
9569                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9570         else
9571                 dpll |= PLL_REF_INPUT_DREFCLK;
9572
9573         dpll |= DPLL_VCO_ENABLE;
9574
9575         crtc_state->dpll_hw_state.dpll = dpll;
9576         crtc_state->dpll_hw_state.fp0 = fp;
9577         crtc_state->dpll_hw_state.fp1 = fp2;
9578 }
9579
9580 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9581                                        struct intel_crtc_state *crtc_state)
9582 {
9583         struct drm_device *dev = crtc->base.dev;
9584         struct drm_i915_private *dev_priv = to_i915(dev);
9585         struct dpll reduced_clock;
9586         bool has_reduced_clock = false;
9587         struct intel_shared_dpll *pll;
9588         const struct intel_limit *limit;
9589         int refclk = 120000;
9590
9591         memset(&crtc_state->dpll_hw_state, 0,
9592                sizeof(crtc_state->dpll_hw_state));
9593
9594         crtc->lowfreq_avail = false;
9595
9596         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9597         if (!crtc_state->has_pch_encoder)
9598                 return 0;
9599
9600         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9601                 if (intel_panel_use_ssc(dev_priv)) {
9602                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9603                                       dev_priv->vbt.lvds_ssc_freq);
9604                         refclk = dev_priv->vbt.lvds_ssc_freq;
9605                 }
9606
9607                 if (intel_is_dual_link_lvds(dev)) {
9608                         if (refclk == 100000)
9609                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9610                         else
9611                                 limit = &intel_limits_ironlake_dual_lvds;
9612                 } else {
9613                         if (refclk == 100000)
9614                                 limit = &intel_limits_ironlake_single_lvds_100m;
9615                         else
9616                                 limit = &intel_limits_ironlake_single_lvds;
9617                 }
9618         } else {
9619                 limit = &intel_limits_ironlake_dac;
9620         }
9621
9622         if (!crtc_state->clock_set &&
9623             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9624                                 refclk, NULL, &crtc_state->dpll)) {
9625                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9626                 return -EINVAL;
9627         }
9628
9629         ironlake_compute_dpll(crtc, crtc_state,
9630                               has_reduced_clock ? &reduced_clock : NULL);
9631
9632         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9633         if (pll == NULL) {
9634                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9635                                  pipe_name(crtc->pipe));
9636                 return -EINVAL;
9637         }
9638
9639         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9640             has_reduced_clock)
9641                 crtc->lowfreq_avail = true;
9642
9643         return 0;
9644 }
9645
9646 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9647                                          struct intel_link_m_n *m_n)
9648 {
9649         struct drm_device *dev = crtc->base.dev;
9650         struct drm_i915_private *dev_priv = to_i915(dev);
9651         enum pipe pipe = crtc->pipe;
9652
9653         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9654         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9655         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9656                 & ~TU_SIZE_MASK;
9657         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9658         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9659                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9660 }
9661
9662 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9663                                          enum transcoder transcoder,
9664                                          struct intel_link_m_n *m_n,
9665                                          struct intel_link_m_n *m2_n2)
9666 {
9667         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9668         enum pipe pipe = crtc->pipe;
9669
9670         if (INTEL_GEN(dev_priv) >= 5) {
9671                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9672                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9673                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9674                         & ~TU_SIZE_MASK;
9675                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9676                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9677                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9678                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9679                  * gen < 8) and if DRRS is supported (to make sure the
9680                  * registers are not unnecessarily read).
9681                  */
9682                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
9683                         crtc->config->has_drrs) {
9684                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9685                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9686                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9687                                         & ~TU_SIZE_MASK;
9688                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9689                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9690                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9691                 }
9692         } else {
9693                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9694                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9695                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9696                         & ~TU_SIZE_MASK;
9697                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9698                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9699                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9700         }
9701 }
9702
9703 void intel_dp_get_m_n(struct intel_crtc *crtc,
9704                       struct intel_crtc_state *pipe_config)
9705 {
9706         if (pipe_config->has_pch_encoder)
9707                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9708         else
9709                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9710                                              &pipe_config->dp_m_n,
9711                                              &pipe_config->dp_m2_n2);
9712 }
9713
9714 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9715                                         struct intel_crtc_state *pipe_config)
9716 {
9717         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9718                                      &pipe_config->fdi_m_n, NULL);
9719 }
9720
9721 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9722                                     struct intel_crtc_state *pipe_config)
9723 {
9724         struct drm_device *dev = crtc->base.dev;
9725         struct drm_i915_private *dev_priv = to_i915(dev);
9726         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9727         uint32_t ps_ctrl = 0;
9728         int id = -1;
9729         int i;
9730
9731         /* find scaler attached to this pipe */
9732         for (i = 0; i < crtc->num_scalers; i++) {
9733                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9734                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9735                         id = i;
9736                         pipe_config->pch_pfit.enabled = true;
9737                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9738                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9739                         break;
9740                 }
9741         }
9742
9743         scaler_state->scaler_id = id;
9744         if (id >= 0) {
9745                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9746         } else {
9747                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9748         }
9749 }
9750
9751 static void
9752 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9753                                  struct intel_initial_plane_config *plane_config)
9754 {
9755         struct drm_device *dev = crtc->base.dev;
9756         struct drm_i915_private *dev_priv = to_i915(dev);
9757         u32 val, base, offset, stride_mult, tiling;
9758         int pipe = crtc->pipe;
9759         int fourcc, pixel_format;
9760         unsigned int aligned_height;
9761         struct drm_framebuffer *fb;
9762         struct intel_framebuffer *intel_fb;
9763
9764         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9765         if (!intel_fb) {
9766                 DRM_DEBUG_KMS("failed to alloc fb\n");
9767                 return;
9768         }
9769
9770         fb = &intel_fb->base;
9771
9772         val = I915_READ(PLANE_CTL(pipe, 0));
9773         if (!(val & PLANE_CTL_ENABLE))
9774                 goto error;
9775
9776         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9777         fourcc = skl_format_to_fourcc(pixel_format,
9778                                       val & PLANE_CTL_ORDER_RGBX,
9779                                       val & PLANE_CTL_ALPHA_MASK);
9780         fb->pixel_format = fourcc;
9781         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9782
9783         tiling = val & PLANE_CTL_TILED_MASK;
9784         switch (tiling) {
9785         case PLANE_CTL_TILED_LINEAR:
9786                 fb->modifier = DRM_FORMAT_MOD_NONE;
9787                 break;
9788         case PLANE_CTL_TILED_X:
9789                 plane_config->tiling = I915_TILING_X;
9790                 fb->modifier = I915_FORMAT_MOD_X_TILED;
9791                 break;
9792         case PLANE_CTL_TILED_Y:
9793                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
9794                 break;
9795         case PLANE_CTL_TILED_YF:
9796                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9797                 break;
9798         default:
9799                 MISSING_CASE(tiling);
9800                 goto error;
9801         }
9802
9803         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9804         plane_config->base = base;
9805
9806         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9807
9808         val = I915_READ(PLANE_SIZE(pipe, 0));
9809         fb->height = ((val >> 16) & 0xfff) + 1;
9810         fb->width = ((val >> 0) & 0x1fff) + 1;
9811
9812         val = I915_READ(PLANE_STRIDE(pipe, 0));
9813         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier,
9814                                                 fb->pixel_format);
9815         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9816
9817         aligned_height = intel_fb_align_height(dev, fb->height,
9818                                                fb->pixel_format,
9819                                                fb->modifier);
9820
9821         plane_config->size = fb->pitches[0] * aligned_height;
9822
9823         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9824                       pipe_name(pipe), fb->width, fb->height,
9825                       fb->bits_per_pixel, base, fb->pitches[0],
9826                       plane_config->size);
9827
9828         plane_config->fb = intel_fb;
9829         return;
9830
9831 error:
9832         kfree(intel_fb);
9833 }
9834
9835 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9836                                      struct intel_crtc_state *pipe_config)
9837 {
9838         struct drm_device *dev = crtc->base.dev;
9839         struct drm_i915_private *dev_priv = to_i915(dev);
9840         uint32_t tmp;
9841
9842         tmp = I915_READ(PF_CTL(crtc->pipe));
9843
9844         if (tmp & PF_ENABLE) {
9845                 pipe_config->pch_pfit.enabled = true;
9846                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9847                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9848
9849                 /* We currently do not free assignements of panel fitters on
9850                  * ivb/hsw (since we don't use the higher upscaling modes which
9851                  * differentiates them) so just WARN about this case for now. */
9852                 if (IS_GEN7(dev_priv)) {
9853                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9854                                 PF_PIPE_SEL_IVB(crtc->pipe));
9855                 }
9856         }
9857 }
9858
9859 static void
9860 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9861                                   struct intel_initial_plane_config *plane_config)
9862 {
9863         struct drm_device *dev = crtc->base.dev;
9864         struct drm_i915_private *dev_priv = to_i915(dev);
9865         u32 val, base, offset;
9866         int pipe = crtc->pipe;
9867         int fourcc, pixel_format;
9868         unsigned int aligned_height;
9869         struct drm_framebuffer *fb;
9870         struct intel_framebuffer *intel_fb;
9871
9872         val = I915_READ(DSPCNTR(pipe));
9873         if (!(val & DISPLAY_PLANE_ENABLE))
9874                 return;
9875
9876         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9877         if (!intel_fb) {
9878                 DRM_DEBUG_KMS("failed to alloc fb\n");
9879                 return;
9880         }
9881
9882         fb = &intel_fb->base;
9883
9884         if (INTEL_GEN(dev_priv) >= 4) {
9885                 if (val & DISPPLANE_TILED) {
9886                         plane_config->tiling = I915_TILING_X;
9887                         fb->modifier = I915_FORMAT_MOD_X_TILED;
9888                 }
9889         }
9890
9891         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9892         fourcc = i9xx_format_to_fourcc(pixel_format);
9893         fb->pixel_format = fourcc;
9894         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9895
9896         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9897         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9898                 offset = I915_READ(DSPOFFSET(pipe));
9899         } else {
9900                 if (plane_config->tiling)
9901                         offset = I915_READ(DSPTILEOFF(pipe));
9902                 else
9903                         offset = I915_READ(DSPLINOFF(pipe));
9904         }
9905         plane_config->base = base;
9906
9907         val = I915_READ(PIPESRC(pipe));
9908         fb->width = ((val >> 16) & 0xfff) + 1;
9909         fb->height = ((val >> 0) & 0xfff) + 1;
9910
9911         val = I915_READ(DSPSTRIDE(pipe));
9912         fb->pitches[0] = val & 0xffffffc0;
9913
9914         aligned_height = intel_fb_align_height(dev, fb->height,
9915                                                fb->pixel_format,
9916                                                fb->modifier);
9917
9918         plane_config->size = fb->pitches[0] * aligned_height;
9919
9920         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9921                       pipe_name(pipe), fb->width, fb->height,
9922                       fb->bits_per_pixel, base, fb->pitches[0],
9923                       plane_config->size);
9924
9925         plane_config->fb = intel_fb;
9926 }
9927
9928 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9929                                      struct intel_crtc_state *pipe_config)
9930 {
9931         struct drm_device *dev = crtc->base.dev;
9932         struct drm_i915_private *dev_priv = to_i915(dev);
9933         enum intel_display_power_domain power_domain;
9934         uint32_t tmp;
9935         bool ret;
9936
9937         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9938         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9939                 return false;
9940
9941         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9942         pipe_config->shared_dpll = NULL;
9943
9944         ret = false;
9945         tmp = I915_READ(PIPECONF(crtc->pipe));
9946         if (!(tmp & PIPECONF_ENABLE))
9947                 goto out;
9948
9949         switch (tmp & PIPECONF_BPC_MASK) {
9950         case PIPECONF_6BPC:
9951                 pipe_config->pipe_bpp = 18;
9952                 break;
9953         case PIPECONF_8BPC:
9954                 pipe_config->pipe_bpp = 24;
9955                 break;
9956         case PIPECONF_10BPC:
9957                 pipe_config->pipe_bpp = 30;
9958                 break;
9959         case PIPECONF_12BPC:
9960                 pipe_config->pipe_bpp = 36;
9961                 break;
9962         default:
9963                 break;
9964         }
9965
9966         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9967                 pipe_config->limited_color_range = true;
9968
9969         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9970                 struct intel_shared_dpll *pll;
9971                 enum intel_dpll_id pll_id;
9972
9973                 pipe_config->has_pch_encoder = true;
9974
9975                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9976                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9977                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9978
9979                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9980
9981                 if (HAS_PCH_IBX(dev_priv)) {
9982                         /*
9983                          * The pipe->pch transcoder and pch transcoder->pll
9984                          * mapping is fixed.
9985                          */
9986                         pll_id = (enum intel_dpll_id) crtc->pipe;
9987                 } else {
9988                         tmp = I915_READ(PCH_DPLL_SEL);
9989                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9990                                 pll_id = DPLL_ID_PCH_PLL_B;
9991                         else
9992                                 pll_id= DPLL_ID_PCH_PLL_A;
9993                 }
9994
9995                 pipe_config->shared_dpll =
9996                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9997                 pll = pipe_config->shared_dpll;
9998
9999                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10000                                                  &pipe_config->dpll_hw_state));
10001
10002                 tmp = pipe_config->dpll_hw_state.dpll;
10003                 pipe_config->pixel_multiplier =
10004                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10005                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10006
10007                 ironlake_pch_clock_get(crtc, pipe_config);
10008         } else {
10009                 pipe_config->pixel_multiplier = 1;
10010         }
10011
10012         intel_get_pipe_timings(crtc, pipe_config);
10013         intel_get_pipe_src_size(crtc, pipe_config);
10014
10015         ironlake_get_pfit_config(crtc, pipe_config);
10016
10017         ret = true;
10018
10019 out:
10020         intel_display_power_put(dev_priv, power_domain);
10021
10022         return ret;
10023 }
10024
10025 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
10026 {
10027         struct drm_device *dev = &dev_priv->drm;
10028         struct intel_crtc *crtc;
10029
10030         for_each_intel_crtc(dev, crtc)
10031                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
10032                      pipe_name(crtc->pipe));
10033
10034         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10035         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10036         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10037         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10038         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10039         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10040              "CPU PWM1 enabled\n");
10041         if (IS_HASWELL(dev_priv))
10042                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10043                      "CPU PWM2 enabled\n");
10044         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10045              "PCH PWM1 enabled\n");
10046         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10047              "Utility pin enabled\n");
10048         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10049
10050         /*
10051          * In theory we can still leave IRQs enabled, as long as only the HPD
10052          * interrupts remain enabled. We used to check for that, but since it's
10053          * gen-specific and since we only disable LCPLL after we fully disable
10054          * the interrupts, the check below should be enough.
10055          */
10056         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10057 }
10058
10059 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10060 {
10061         if (IS_HASWELL(dev_priv))
10062                 return I915_READ(D_COMP_HSW);
10063         else
10064                 return I915_READ(D_COMP_BDW);
10065 }
10066
10067 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10068 {
10069         if (IS_HASWELL(dev_priv)) {
10070                 mutex_lock(&dev_priv->rps.hw_lock);
10071                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10072                                             val))
10073                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10074                 mutex_unlock(&dev_priv->rps.hw_lock);
10075         } else {
10076                 I915_WRITE(D_COMP_BDW, val);
10077                 POSTING_READ(D_COMP_BDW);
10078         }
10079 }
10080
10081 /*
10082  * This function implements pieces of two sequences from BSpec:
10083  * - Sequence for display software to disable LCPLL
10084  * - Sequence for display software to allow package C8+
10085  * The steps implemented here are just the steps that actually touch the LCPLL
10086  * register. Callers should take care of disabling all the display engine
10087  * functions, doing the mode unset, fixing interrupts, etc.
10088  */
10089 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10090                               bool switch_to_fclk, bool allow_power_down)
10091 {
10092         uint32_t val;
10093
10094         assert_can_disable_lcpll(dev_priv);
10095
10096         val = I915_READ(LCPLL_CTL);
10097
10098         if (switch_to_fclk) {
10099                 val |= LCPLL_CD_SOURCE_FCLK;
10100                 I915_WRITE(LCPLL_CTL, val);
10101
10102                 if (wait_for_us(I915_READ(LCPLL_CTL) &
10103                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10104                         DRM_ERROR("Switching to FCLK failed\n");
10105
10106                 val = I915_READ(LCPLL_CTL);
10107         }
10108
10109         val |= LCPLL_PLL_DISABLE;
10110         I915_WRITE(LCPLL_CTL, val);
10111         POSTING_READ(LCPLL_CTL);
10112
10113         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10114                 DRM_ERROR("LCPLL still locked\n");
10115
10116         val = hsw_read_dcomp(dev_priv);
10117         val |= D_COMP_COMP_DISABLE;
10118         hsw_write_dcomp(dev_priv, val);
10119         ndelay(100);
10120
10121         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10122                      1))
10123                 DRM_ERROR("D_COMP RCOMP still in progress\n");
10124
10125         if (allow_power_down) {
10126                 val = I915_READ(LCPLL_CTL);
10127                 val |= LCPLL_POWER_DOWN_ALLOW;
10128                 I915_WRITE(LCPLL_CTL, val);
10129                 POSTING_READ(LCPLL_CTL);
10130         }
10131 }
10132
10133 /*
10134  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10135  * source.
10136  */
10137 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10138 {
10139         uint32_t val;
10140
10141         val = I915_READ(LCPLL_CTL);
10142
10143         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10144                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10145                 return;
10146
10147         /*
10148          * Make sure we're not on PC8 state before disabling PC8, otherwise
10149          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10150          */
10151         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10152
10153         if (val & LCPLL_POWER_DOWN_ALLOW) {
10154                 val &= ~LCPLL_POWER_DOWN_ALLOW;
10155                 I915_WRITE(LCPLL_CTL, val);
10156                 POSTING_READ(LCPLL_CTL);
10157         }
10158
10159         val = hsw_read_dcomp(dev_priv);
10160         val |= D_COMP_COMP_FORCE;
10161         val &= ~D_COMP_COMP_DISABLE;
10162         hsw_write_dcomp(dev_priv, val);
10163
10164         val = I915_READ(LCPLL_CTL);
10165         val &= ~LCPLL_PLL_DISABLE;
10166         I915_WRITE(LCPLL_CTL, val);
10167
10168         if (intel_wait_for_register(dev_priv,
10169                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10170                                     5))
10171                 DRM_ERROR("LCPLL not locked yet\n");
10172
10173         if (val & LCPLL_CD_SOURCE_FCLK) {
10174                 val = I915_READ(LCPLL_CTL);
10175                 val &= ~LCPLL_CD_SOURCE_FCLK;
10176                 I915_WRITE(LCPLL_CTL, val);
10177
10178                 if (wait_for_us((I915_READ(LCPLL_CTL) &
10179                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10180                         DRM_ERROR("Switching back to LCPLL failed\n");
10181         }
10182
10183         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10184         intel_update_cdclk(dev_priv);
10185 }
10186
10187 /*
10188  * Package states C8 and deeper are really deep PC states that can only be
10189  * reached when all the devices on the system allow it, so even if the graphics
10190  * device allows PC8+, it doesn't mean the system will actually get to these
10191  * states. Our driver only allows PC8+ when going into runtime PM.
10192  *
10193  * The requirements for PC8+ are that all the outputs are disabled, the power
10194  * well is disabled and most interrupts are disabled, and these are also
10195  * requirements for runtime PM. When these conditions are met, we manually do
10196  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10197  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10198  * hang the machine.
10199  *
10200  * When we really reach PC8 or deeper states (not just when we allow it) we lose
10201  * the state of some registers, so when we come back from PC8+ we need to
10202  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10203  * need to take care of the registers kept by RC6. Notice that this happens even
10204  * if we don't put the device in PCI D3 state (which is what currently happens
10205  * because of the runtime PM support).
10206  *
10207  * For more, read "Display Sequences for Package C8" on the hardware
10208  * documentation.
10209  */
10210 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10211 {
10212         uint32_t val;
10213
10214         DRM_DEBUG_KMS("Enabling package C8+\n");
10215
10216         if (HAS_PCH_LPT_LP(dev_priv)) {
10217                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10218                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10219                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10220         }
10221
10222         lpt_disable_clkout_dp(dev_priv);
10223         hsw_disable_lcpll(dev_priv, true, true);
10224 }
10225
10226 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10227 {
10228         uint32_t val;
10229
10230         DRM_DEBUG_KMS("Disabling package C8+\n");
10231
10232         hsw_restore_lcpll(dev_priv);
10233         lpt_init_pch_refclk(dev_priv);
10234
10235         if (HAS_PCH_LPT_LP(dev_priv)) {
10236                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10237                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10238                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10239         }
10240 }
10241
10242 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10243 {
10244         struct drm_device *dev = old_state->dev;
10245         struct intel_atomic_state *old_intel_state =
10246                 to_intel_atomic_state(old_state);
10247         unsigned int req_cdclk = old_intel_state->dev_cdclk;
10248
10249         bxt_set_cdclk(to_i915(dev), req_cdclk);
10250 }
10251
10252 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
10253                                           int pixel_rate)
10254 {
10255         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
10256
10257         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10258         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10259                 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10260
10261         /* BSpec says "Do not use DisplayPort with CDCLK less than
10262          * 432 MHz, audio enabled, port width x4, and link rate
10263          * HBR2 (5.4 GHz), or else there may be audio corruption or
10264          * screen corruption."
10265          */
10266         if (intel_crtc_has_dp_encoder(crtc_state) &&
10267             crtc_state->has_audio &&
10268             crtc_state->port_clock >= 540000 &&
10269             crtc_state->lane_count == 4)
10270                 pixel_rate = max(432000, pixel_rate);
10271
10272         return pixel_rate;
10273 }
10274
10275 /* compute the max rate for new configuration */
10276 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10277 {
10278         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10279         struct drm_i915_private *dev_priv = to_i915(state->dev);
10280         struct drm_crtc *crtc;
10281         struct drm_crtc_state *cstate;
10282         struct intel_crtc_state *crtc_state;
10283         unsigned max_pixel_rate = 0, i;
10284         enum pipe pipe;
10285
10286         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10287                sizeof(intel_state->min_pixclk));
10288
10289         for_each_crtc_in_state(state, crtc, cstate, i) {
10290                 int pixel_rate;
10291
10292                 crtc_state = to_intel_crtc_state(cstate);
10293                 if (!crtc_state->base.enable) {
10294                         intel_state->min_pixclk[i] = 0;
10295                         continue;
10296                 }
10297
10298                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10299
10300                 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
10301                         pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
10302                                                                     pixel_rate);
10303
10304                 intel_state->min_pixclk[i] = pixel_rate;
10305         }
10306
10307         for_each_pipe(dev_priv, pipe)
10308                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10309
10310         return max_pixel_rate;
10311 }
10312
10313 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10314 {
10315         struct drm_i915_private *dev_priv = to_i915(dev);
10316         uint32_t val, data;
10317         int ret;
10318
10319         if (WARN((I915_READ(LCPLL_CTL) &
10320                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10321                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10322                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10323                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10324                  "trying to change cdclk frequency with cdclk not enabled\n"))
10325                 return;
10326
10327         mutex_lock(&dev_priv->rps.hw_lock);
10328         ret = sandybridge_pcode_write(dev_priv,
10329                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10330         mutex_unlock(&dev_priv->rps.hw_lock);
10331         if (ret) {
10332                 DRM_ERROR("failed to inform pcode about cdclk change\n");
10333                 return;
10334         }
10335
10336         val = I915_READ(LCPLL_CTL);
10337         val |= LCPLL_CD_SOURCE_FCLK;
10338         I915_WRITE(LCPLL_CTL, val);
10339
10340         if (wait_for_us(I915_READ(LCPLL_CTL) &
10341                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
10342                 DRM_ERROR("Switching to FCLK failed\n");
10343
10344         val = I915_READ(LCPLL_CTL);
10345         val &= ~LCPLL_CLK_FREQ_MASK;
10346
10347         switch (cdclk) {
10348         case 450000:
10349                 val |= LCPLL_CLK_FREQ_450;
10350                 data = 0;
10351                 break;
10352         case 540000:
10353                 val |= LCPLL_CLK_FREQ_54O_BDW;
10354                 data = 1;
10355                 break;
10356         case 337500:
10357                 val |= LCPLL_CLK_FREQ_337_5_BDW;
10358                 data = 2;
10359                 break;
10360         case 675000:
10361                 val |= LCPLL_CLK_FREQ_675_BDW;
10362                 data = 3;
10363                 break;
10364         default:
10365                 WARN(1, "invalid cdclk frequency\n");
10366                 return;
10367         }
10368
10369         I915_WRITE(LCPLL_CTL, val);
10370
10371         val = I915_READ(LCPLL_CTL);
10372         val &= ~LCPLL_CD_SOURCE_FCLK;
10373         I915_WRITE(LCPLL_CTL, val);
10374
10375         if (wait_for_us((I915_READ(LCPLL_CTL) &
10376                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10377                 DRM_ERROR("Switching back to LCPLL failed\n");
10378
10379         mutex_lock(&dev_priv->rps.hw_lock);
10380         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10381         mutex_unlock(&dev_priv->rps.hw_lock);
10382
10383         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10384
10385         intel_update_cdclk(dev_priv);
10386
10387         WARN(cdclk != dev_priv->cdclk_freq,
10388              "cdclk requested %d kHz but got %d kHz\n",
10389              cdclk, dev_priv->cdclk_freq);
10390 }
10391
10392 static int broadwell_calc_cdclk(int max_pixclk)
10393 {
10394         if (max_pixclk > 540000)
10395                 return 675000;
10396         else if (max_pixclk > 450000)
10397                 return 540000;
10398         else if (max_pixclk > 337500)
10399                 return 450000;
10400         else
10401                 return 337500;
10402 }
10403
10404 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10405 {
10406         struct drm_i915_private *dev_priv = to_i915(state->dev);
10407         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10408         int max_pixclk = ilk_max_pixel_rate(state);
10409         int cdclk;
10410
10411         /*
10412          * FIXME should also account for plane ratio
10413          * once 64bpp pixel formats are supported.
10414          */
10415         cdclk = broadwell_calc_cdclk(max_pixclk);
10416
10417         if (cdclk > dev_priv->max_cdclk_freq) {
10418                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10419                               cdclk, dev_priv->max_cdclk_freq);
10420                 return -EINVAL;
10421         }
10422
10423         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10424         if (!intel_state->active_crtcs)
10425                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10426
10427         return 0;
10428 }
10429
10430 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10431 {
10432         struct drm_device *dev = old_state->dev;
10433         struct intel_atomic_state *old_intel_state =
10434                 to_intel_atomic_state(old_state);
10435         unsigned req_cdclk = old_intel_state->dev_cdclk;
10436
10437         broadwell_set_cdclk(dev, req_cdclk);
10438 }
10439
10440 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10441 {
10442         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10443         struct drm_i915_private *dev_priv = to_i915(state->dev);
10444         const int max_pixclk = ilk_max_pixel_rate(state);
10445         int vco = intel_state->cdclk_pll_vco;
10446         int cdclk;
10447
10448         /*
10449          * FIXME should also account for plane ratio
10450          * once 64bpp pixel formats are supported.
10451          */
10452         cdclk = skl_calc_cdclk(max_pixclk, vco);
10453
10454         /*
10455          * FIXME move the cdclk caclulation to
10456          * compute_config() so we can fail gracegully.
10457          */
10458         if (cdclk > dev_priv->max_cdclk_freq) {
10459                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10460                           cdclk, dev_priv->max_cdclk_freq);
10461                 cdclk = dev_priv->max_cdclk_freq;
10462         }
10463
10464         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10465         if (!intel_state->active_crtcs)
10466                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10467
10468         return 0;
10469 }
10470
10471 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10472 {
10473         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10474         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10475         unsigned int req_cdclk = intel_state->dev_cdclk;
10476         unsigned int req_vco = intel_state->cdclk_pll_vco;
10477
10478         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10479 }
10480
10481 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10482                                       struct intel_crtc_state *crtc_state)
10483 {
10484         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10485                 if (!intel_ddi_pll_select(crtc, crtc_state))
10486                         return -EINVAL;
10487         }
10488
10489         crtc->lowfreq_avail = false;
10490
10491         return 0;
10492 }
10493
10494 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10495                                 enum port port,
10496                                 struct intel_crtc_state *pipe_config)
10497 {
10498         enum intel_dpll_id id;
10499
10500         switch (port) {
10501         case PORT_A:
10502                 id = DPLL_ID_SKL_DPLL0;
10503                 break;
10504         case PORT_B:
10505                 id = DPLL_ID_SKL_DPLL1;
10506                 break;
10507         case PORT_C:
10508                 id = DPLL_ID_SKL_DPLL2;
10509                 break;
10510         default:
10511                 DRM_ERROR("Incorrect port type\n");
10512                 return;
10513         }
10514
10515         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10516 }
10517
10518 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10519                                 enum port port,
10520                                 struct intel_crtc_state *pipe_config)
10521 {
10522         enum intel_dpll_id id;
10523         u32 temp;
10524
10525         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10526         id = temp >> (port * 3 + 1);
10527
10528         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10529                 return;
10530
10531         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10532 }
10533
10534 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10535                                 enum port port,
10536                                 struct intel_crtc_state *pipe_config)
10537 {
10538         enum intel_dpll_id id;
10539         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10540
10541         switch (ddi_pll_sel) {
10542         case PORT_CLK_SEL_WRPLL1:
10543                 id = DPLL_ID_WRPLL1;
10544                 break;
10545         case PORT_CLK_SEL_WRPLL2:
10546                 id = DPLL_ID_WRPLL2;
10547                 break;
10548         case PORT_CLK_SEL_SPLL:
10549                 id = DPLL_ID_SPLL;
10550                 break;
10551         case PORT_CLK_SEL_LCPLL_810:
10552                 id = DPLL_ID_LCPLL_810;
10553                 break;
10554         case PORT_CLK_SEL_LCPLL_1350:
10555                 id = DPLL_ID_LCPLL_1350;
10556                 break;
10557         case PORT_CLK_SEL_LCPLL_2700:
10558                 id = DPLL_ID_LCPLL_2700;
10559                 break;
10560         default:
10561                 MISSING_CASE(ddi_pll_sel);
10562                 /* fall through */
10563         case PORT_CLK_SEL_NONE:
10564                 return;
10565         }
10566
10567         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10568 }
10569
10570 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10571                                      struct intel_crtc_state *pipe_config,
10572                                      unsigned long *power_domain_mask)
10573 {
10574         struct drm_device *dev = crtc->base.dev;
10575         struct drm_i915_private *dev_priv = to_i915(dev);
10576         enum intel_display_power_domain power_domain;
10577         u32 tmp;
10578
10579         /*
10580          * The pipe->transcoder mapping is fixed with the exception of the eDP
10581          * transcoder handled below.
10582          */
10583         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10584
10585         /*
10586          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10587          * consistency and less surprising code; it's in always on power).
10588          */
10589         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10590         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10591                 enum pipe trans_edp_pipe;
10592                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10593                 default:
10594                         WARN(1, "unknown pipe linked to edp transcoder\n");
10595                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10596                 case TRANS_DDI_EDP_INPUT_A_ON:
10597                         trans_edp_pipe = PIPE_A;
10598                         break;
10599                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10600                         trans_edp_pipe = PIPE_B;
10601                         break;
10602                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10603                         trans_edp_pipe = PIPE_C;
10604                         break;
10605                 }
10606
10607                 if (trans_edp_pipe == crtc->pipe)
10608                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10609         }
10610
10611         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10612         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10613                 return false;
10614         *power_domain_mask |= BIT(power_domain);
10615
10616         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10617
10618         return tmp & PIPECONF_ENABLE;
10619 }
10620
10621 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10622                                          struct intel_crtc_state *pipe_config,
10623                                          unsigned long *power_domain_mask)
10624 {
10625         struct drm_device *dev = crtc->base.dev;
10626         struct drm_i915_private *dev_priv = to_i915(dev);
10627         enum intel_display_power_domain power_domain;
10628         enum port port;
10629         enum transcoder cpu_transcoder;
10630         u32 tmp;
10631
10632         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10633                 if (port == PORT_A)
10634                         cpu_transcoder = TRANSCODER_DSI_A;
10635                 else
10636                         cpu_transcoder = TRANSCODER_DSI_C;
10637
10638                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10639                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10640                         continue;
10641                 *power_domain_mask |= BIT(power_domain);
10642
10643                 /*
10644                  * The PLL needs to be enabled with a valid divider
10645                  * configuration, otherwise accessing DSI registers will hang
10646                  * the machine. See BSpec North Display Engine
10647                  * registers/MIPI[BXT]. We can break out here early, since we
10648                  * need the same DSI PLL to be enabled for both DSI ports.
10649                  */
10650                 if (!intel_dsi_pll_is_enabled(dev_priv))
10651                         break;
10652
10653                 /* XXX: this works for video mode only */
10654                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10655                 if (!(tmp & DPI_ENABLE))
10656                         continue;
10657
10658                 tmp = I915_READ(MIPI_CTRL(port));
10659                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10660                         continue;
10661
10662                 pipe_config->cpu_transcoder = cpu_transcoder;
10663                 break;
10664         }
10665
10666         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10667 }
10668
10669 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10670                                        struct intel_crtc_state *pipe_config)
10671 {
10672         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10673         struct intel_shared_dpll *pll;
10674         enum port port;
10675         uint32_t tmp;
10676
10677         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10678
10679         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10680
10681         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
10682                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10683         else if (IS_GEN9_LP(dev_priv))
10684                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10685         else
10686                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10687
10688         pll = pipe_config->shared_dpll;
10689         if (pll) {
10690                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10691                                                  &pipe_config->dpll_hw_state));
10692         }
10693
10694         /*
10695          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10696          * DDI E. So just check whether this pipe is wired to DDI E and whether
10697          * the PCH transcoder is on.
10698          */
10699         if (INTEL_GEN(dev_priv) < 9 &&
10700             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10701                 pipe_config->has_pch_encoder = true;
10702
10703                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10704                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10705                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10706
10707                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10708         }
10709 }
10710
10711 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10712                                     struct intel_crtc_state *pipe_config)
10713 {
10714         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10715         enum intel_display_power_domain power_domain;
10716         unsigned long power_domain_mask;
10717         bool active;
10718
10719         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10720         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10721                 return false;
10722         power_domain_mask = BIT(power_domain);
10723
10724         pipe_config->shared_dpll = NULL;
10725
10726         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10727
10728         if (IS_GEN9_LP(dev_priv) &&
10729             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10730                 WARN_ON(active);
10731                 active = true;
10732         }
10733
10734         if (!active)
10735                 goto out;
10736
10737         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10738                 haswell_get_ddi_port_state(crtc, pipe_config);
10739                 intel_get_pipe_timings(crtc, pipe_config);
10740         }
10741
10742         intel_get_pipe_src_size(crtc, pipe_config);
10743
10744         pipe_config->gamma_mode =
10745                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10746
10747         if (INTEL_GEN(dev_priv) >= 9) {
10748                 skl_init_scalers(dev_priv, crtc, pipe_config);
10749
10750                 pipe_config->scaler_state.scaler_id = -1;
10751                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10752         }
10753
10754         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10755         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10756                 power_domain_mask |= BIT(power_domain);
10757                 if (INTEL_GEN(dev_priv) >= 9)
10758                         skylake_get_pfit_config(crtc, pipe_config);
10759                 else
10760                         ironlake_get_pfit_config(crtc, pipe_config);
10761         }
10762
10763         if (IS_HASWELL(dev_priv))
10764                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10765                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10766
10767         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10768             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10769                 pipe_config->pixel_multiplier =
10770                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10771         } else {
10772                 pipe_config->pixel_multiplier = 1;
10773         }
10774
10775 out:
10776         for_each_power_domain(power_domain, power_domain_mask)
10777                 intel_display_power_put(dev_priv, power_domain);
10778
10779         return active;
10780 }
10781
10782 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10783                                const struct intel_plane_state *plane_state)
10784 {
10785         struct drm_device *dev = crtc->dev;
10786         struct drm_i915_private *dev_priv = to_i915(dev);
10787         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10788         uint32_t cntl = 0, size = 0;
10789
10790         if (plane_state && plane_state->base.visible) {
10791                 unsigned int width = plane_state->base.crtc_w;
10792                 unsigned int height = plane_state->base.crtc_h;
10793                 unsigned int stride = roundup_pow_of_two(width) * 4;
10794
10795                 switch (stride) {
10796                 default:
10797                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10798                                   width, stride);
10799                         stride = 256;
10800                         /* fallthrough */
10801                 case 256:
10802                 case 512:
10803                 case 1024:
10804                 case 2048:
10805                         break;
10806                 }
10807
10808                 cntl |= CURSOR_ENABLE |
10809                         CURSOR_GAMMA_ENABLE |
10810                         CURSOR_FORMAT_ARGB |
10811                         CURSOR_STRIDE(stride);
10812
10813                 size = (height << 12) | width;
10814         }
10815
10816         if (intel_crtc->cursor_cntl != 0 &&
10817             (intel_crtc->cursor_base != base ||
10818              intel_crtc->cursor_size != size ||
10819              intel_crtc->cursor_cntl != cntl)) {
10820                 /* On these chipsets we can only modify the base/size/stride
10821                  * whilst the cursor is disabled.
10822                  */
10823                 I915_WRITE(CURCNTR(PIPE_A), 0);
10824                 POSTING_READ(CURCNTR(PIPE_A));
10825                 intel_crtc->cursor_cntl = 0;
10826         }
10827
10828         if (intel_crtc->cursor_base != base) {
10829                 I915_WRITE(CURBASE(PIPE_A), base);
10830                 intel_crtc->cursor_base = base;
10831         }
10832
10833         if (intel_crtc->cursor_size != size) {
10834                 I915_WRITE(CURSIZE, size);
10835                 intel_crtc->cursor_size = size;
10836         }
10837
10838         if (intel_crtc->cursor_cntl != cntl) {
10839                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10840                 POSTING_READ(CURCNTR(PIPE_A));
10841                 intel_crtc->cursor_cntl = cntl;
10842         }
10843 }
10844
10845 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10846                                const struct intel_plane_state *plane_state)
10847 {
10848         struct drm_device *dev = crtc->dev;
10849         struct drm_i915_private *dev_priv = to_i915(dev);
10850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10851         int pipe = intel_crtc->pipe;
10852         uint32_t cntl = 0;
10853
10854         if (plane_state && plane_state->base.visible) {
10855                 cntl = MCURSOR_GAMMA_ENABLE;
10856                 switch (plane_state->base.crtc_w) {
10857                         case 64:
10858                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10859                                 break;
10860                         case 128:
10861                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10862                                 break;
10863                         case 256:
10864                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10865                                 break;
10866                         default:
10867                                 MISSING_CASE(plane_state->base.crtc_w);
10868                                 return;
10869                 }
10870                 cntl |= pipe << 28; /* Connect to correct pipe */
10871
10872                 if (HAS_DDI(dev_priv))
10873                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10874
10875                 if (plane_state->base.rotation & DRM_ROTATE_180)
10876                         cntl |= CURSOR_ROTATE_180;
10877         }
10878
10879         if (intel_crtc->cursor_cntl != cntl) {
10880                 I915_WRITE(CURCNTR(pipe), cntl);
10881                 POSTING_READ(CURCNTR(pipe));
10882                 intel_crtc->cursor_cntl = cntl;
10883         }
10884
10885         /* and commit changes on next vblank */
10886         I915_WRITE(CURBASE(pipe), base);
10887         POSTING_READ(CURBASE(pipe));
10888
10889         intel_crtc->cursor_base = base;
10890 }
10891
10892 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10893 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10894                                      const struct intel_plane_state *plane_state)
10895 {
10896         struct drm_device *dev = crtc->dev;
10897         struct drm_i915_private *dev_priv = to_i915(dev);
10898         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10899         int pipe = intel_crtc->pipe;
10900         u32 base = intel_crtc->cursor_addr;
10901         u32 pos = 0;
10902
10903         if (plane_state) {
10904                 int x = plane_state->base.crtc_x;
10905                 int y = plane_state->base.crtc_y;
10906
10907                 if (x < 0) {
10908                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10909                         x = -x;
10910                 }
10911                 pos |= x << CURSOR_X_SHIFT;
10912
10913                 if (y < 0) {
10914                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10915                         y = -y;
10916                 }
10917                 pos |= y << CURSOR_Y_SHIFT;
10918
10919                 /* ILK+ do this automagically */
10920                 if (HAS_GMCH_DISPLAY(dev_priv) &&
10921                     plane_state->base.rotation & DRM_ROTATE_180) {
10922                         base += (plane_state->base.crtc_h *
10923                                  plane_state->base.crtc_w - 1) * 4;
10924                 }
10925         }
10926
10927         I915_WRITE(CURPOS(pipe), pos);
10928
10929         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
10930                 i845_update_cursor(crtc, base, plane_state);
10931         else
10932                 i9xx_update_cursor(crtc, base, plane_state);
10933 }
10934
10935 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
10936                            uint32_t width, uint32_t height)
10937 {
10938         if (width == 0 || height == 0)
10939                 return false;
10940
10941         /*
10942          * 845g/865g are special in that they are only limited by
10943          * the width of their cursors, the height is arbitrary up to
10944          * the precision of the register. Everything else requires
10945          * square cursors, limited to a few power-of-two sizes.
10946          */
10947         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
10948                 if ((width & 63) != 0)
10949                         return false;
10950
10951                 if (width > (IS_I845G(dev_priv) ? 64 : 512))
10952                         return false;
10953
10954                 if (height > 1023)
10955                         return false;
10956         } else {
10957                 switch (width | height) {
10958                 case 256:
10959                 case 128:
10960                         if (IS_GEN2(dev_priv))
10961                                 return false;
10962                 case 64:
10963                         break;
10964                 default:
10965                         return false;
10966                 }
10967         }
10968
10969         return true;
10970 }
10971
10972 /* VESA 640x480x72Hz mode to set on the pipe */
10973 static struct drm_display_mode load_detect_mode = {
10974         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10975                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10976 };
10977
10978 struct drm_framebuffer *
10979 __intel_framebuffer_create(struct drm_device *dev,
10980                            struct drm_mode_fb_cmd2 *mode_cmd,
10981                            struct drm_i915_gem_object *obj)
10982 {
10983         struct intel_framebuffer *intel_fb;
10984         int ret;
10985
10986         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10987         if (!intel_fb)
10988                 return ERR_PTR(-ENOMEM);
10989
10990         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10991         if (ret)
10992                 goto err;
10993
10994         return &intel_fb->base;
10995
10996 err:
10997         kfree(intel_fb);
10998         return ERR_PTR(ret);
10999 }
11000
11001 static struct drm_framebuffer *
11002 intel_framebuffer_create(struct drm_device *dev,
11003                          struct drm_mode_fb_cmd2 *mode_cmd,
11004                          struct drm_i915_gem_object *obj)
11005 {
11006         struct drm_framebuffer *fb;
11007         int ret;
11008
11009         ret = i915_mutex_lock_interruptible(dev);
11010         if (ret)
11011                 return ERR_PTR(ret);
11012         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
11013         mutex_unlock(&dev->struct_mutex);
11014
11015         return fb;
11016 }
11017
11018 static u32
11019 intel_framebuffer_pitch_for_width(int width, int bpp)
11020 {
11021         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
11022         return ALIGN(pitch, 64);
11023 }
11024
11025 static u32
11026 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
11027 {
11028         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
11029         return PAGE_ALIGN(pitch * mode->vdisplay);
11030 }
11031
11032 static struct drm_framebuffer *
11033 intel_framebuffer_create_for_mode(struct drm_device *dev,
11034                                   struct drm_display_mode *mode,
11035                                   int depth, int bpp)
11036 {
11037         struct drm_framebuffer *fb;
11038         struct drm_i915_gem_object *obj;
11039         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
11040
11041         obj = i915_gem_object_create(to_i915(dev),
11042                                     intel_framebuffer_size_for_mode(mode, bpp));
11043         if (IS_ERR(obj))
11044                 return ERR_CAST(obj);
11045
11046         mode_cmd.width = mode->hdisplay;
11047         mode_cmd.height = mode->vdisplay;
11048         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11049                                                                 bpp);
11050         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11051
11052         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11053         if (IS_ERR(fb))
11054                 i915_gem_object_put(obj);
11055
11056         return fb;
11057 }
11058
11059 static struct drm_framebuffer *
11060 mode_fits_in_fbdev(struct drm_device *dev,
11061                    struct drm_display_mode *mode)
11062 {
11063 #ifdef CONFIG_DRM_FBDEV_EMULATION
11064         struct drm_i915_private *dev_priv = to_i915(dev);
11065         struct drm_i915_gem_object *obj;
11066         struct drm_framebuffer *fb;
11067
11068         if (!dev_priv->fbdev)
11069                 return NULL;
11070
11071         if (!dev_priv->fbdev->fb)
11072                 return NULL;
11073
11074         obj = dev_priv->fbdev->fb->obj;
11075         BUG_ON(!obj);
11076
11077         fb = &dev_priv->fbdev->fb->base;
11078         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11079                                                                fb->bits_per_pixel))
11080                 return NULL;
11081
11082         if (obj->base.size < mode->vdisplay * fb->pitches[0])
11083                 return NULL;
11084
11085         drm_framebuffer_reference(fb);
11086         return fb;
11087 #else
11088         return NULL;
11089 #endif
11090 }
11091
11092 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11093                                            struct drm_crtc *crtc,
11094                                            struct drm_display_mode *mode,
11095                                            struct drm_framebuffer *fb,
11096                                            int x, int y)
11097 {
11098         struct drm_plane_state *plane_state;
11099         int hdisplay, vdisplay;
11100         int ret;
11101
11102         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11103         if (IS_ERR(plane_state))
11104                 return PTR_ERR(plane_state);
11105
11106         if (mode)
11107                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11108         else
11109                 hdisplay = vdisplay = 0;
11110
11111         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11112         if (ret)
11113                 return ret;
11114         drm_atomic_set_fb_for_plane(plane_state, fb);
11115         plane_state->crtc_x = 0;
11116         plane_state->crtc_y = 0;
11117         plane_state->crtc_w = hdisplay;
11118         plane_state->crtc_h = vdisplay;
11119         plane_state->src_x = x << 16;
11120         plane_state->src_y = y << 16;
11121         plane_state->src_w = hdisplay << 16;
11122         plane_state->src_h = vdisplay << 16;
11123
11124         return 0;
11125 }
11126
11127 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11128                                 struct drm_display_mode *mode,
11129                                 struct intel_load_detect_pipe *old,
11130                                 struct drm_modeset_acquire_ctx *ctx)
11131 {
11132         struct intel_crtc *intel_crtc;
11133         struct intel_encoder *intel_encoder =
11134                 intel_attached_encoder(connector);
11135         struct drm_crtc *possible_crtc;
11136         struct drm_encoder *encoder = &intel_encoder->base;
11137         struct drm_crtc *crtc = NULL;
11138         struct drm_device *dev = encoder->dev;
11139         struct drm_i915_private *dev_priv = to_i915(dev);
11140         struct drm_framebuffer *fb;
11141         struct drm_mode_config *config = &dev->mode_config;
11142         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11143         struct drm_connector_state *connector_state;
11144         struct intel_crtc_state *crtc_state;
11145         int ret, i = -1;
11146
11147         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11148                       connector->base.id, connector->name,
11149                       encoder->base.id, encoder->name);
11150
11151         old->restore_state = NULL;
11152
11153 retry:
11154         ret = drm_modeset_lock(&config->connection_mutex, ctx);
11155         if (ret)
11156                 goto fail;
11157
11158         /*
11159          * Algorithm gets a little messy:
11160          *
11161          *   - if the connector already has an assigned crtc, use it (but make
11162          *     sure it's on first)
11163          *
11164          *   - try to find the first unused crtc that can drive this connector,
11165          *     and use that if we find one
11166          */
11167
11168         /* See if we already have a CRTC for this connector */
11169         if (connector->state->crtc) {
11170                 crtc = connector->state->crtc;
11171
11172                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11173                 if (ret)
11174                         goto fail;
11175
11176                 /* Make sure the crtc and connector are running */
11177                 goto found;
11178         }
11179
11180         /* Find an unused one (if possible) */
11181         for_each_crtc(dev, possible_crtc) {
11182                 i++;
11183                 if (!(encoder->possible_crtcs & (1 << i)))
11184                         continue;
11185
11186                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11187                 if (ret)
11188                         goto fail;
11189
11190                 if (possible_crtc->state->enable) {
11191                         drm_modeset_unlock(&possible_crtc->mutex);
11192                         continue;
11193                 }
11194
11195                 crtc = possible_crtc;
11196                 break;
11197         }
11198
11199         /*
11200          * If we didn't find an unused CRTC, don't use any.
11201          */
11202         if (!crtc) {
11203                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11204                 goto fail;
11205         }
11206
11207 found:
11208         intel_crtc = to_intel_crtc(crtc);
11209
11210         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11211         if (ret)
11212                 goto fail;
11213
11214         state = drm_atomic_state_alloc(dev);
11215         restore_state = drm_atomic_state_alloc(dev);
11216         if (!state || !restore_state) {
11217                 ret = -ENOMEM;
11218                 goto fail;
11219         }
11220
11221         state->acquire_ctx = ctx;
11222         restore_state->acquire_ctx = ctx;
11223
11224         connector_state = drm_atomic_get_connector_state(state, connector);
11225         if (IS_ERR(connector_state)) {
11226                 ret = PTR_ERR(connector_state);
11227                 goto fail;
11228         }
11229
11230         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11231         if (ret)
11232                 goto fail;
11233
11234         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11235         if (IS_ERR(crtc_state)) {
11236                 ret = PTR_ERR(crtc_state);
11237                 goto fail;
11238         }
11239
11240         crtc_state->base.active = crtc_state->base.enable = true;
11241
11242         if (!mode)
11243                 mode = &load_detect_mode;
11244
11245         /* We need a framebuffer large enough to accommodate all accesses
11246          * that the plane may generate whilst we perform load detection.
11247          * We can not rely on the fbcon either being present (we get called
11248          * during its initialisation to detect all boot displays, or it may
11249          * not even exist) or that it is large enough to satisfy the
11250          * requested mode.
11251          */
11252         fb = mode_fits_in_fbdev(dev, mode);
11253         if (fb == NULL) {
11254                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11255                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11256         } else
11257                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11258         if (IS_ERR(fb)) {
11259                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11260                 goto fail;
11261         }
11262
11263         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11264         if (ret)
11265                 goto fail;
11266
11267         drm_framebuffer_unreference(fb);
11268
11269         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11270         if (ret)
11271                 goto fail;
11272
11273         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11274         if (!ret)
11275                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11276         if (!ret)
11277                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11278         if (ret) {
11279                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11280                 goto fail;
11281         }
11282
11283         ret = drm_atomic_commit(state);
11284         if (ret) {
11285                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11286                 goto fail;
11287         }
11288
11289         old->restore_state = restore_state;
11290
11291         /* let the connector get through one full cycle before testing */
11292         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11293         return true;
11294
11295 fail:
11296         if (state) {
11297                 drm_atomic_state_put(state);
11298                 state = NULL;
11299         }
11300         if (restore_state) {
11301                 drm_atomic_state_put(restore_state);
11302                 restore_state = NULL;
11303         }
11304
11305         if (ret == -EDEADLK) {
11306                 drm_modeset_backoff(ctx);
11307                 goto retry;
11308         }
11309
11310         return false;
11311 }
11312
11313 void intel_release_load_detect_pipe(struct drm_connector *connector,
11314                                     struct intel_load_detect_pipe *old,
11315                                     struct drm_modeset_acquire_ctx *ctx)
11316 {
11317         struct intel_encoder *intel_encoder =
11318                 intel_attached_encoder(connector);
11319         struct drm_encoder *encoder = &intel_encoder->base;
11320         struct drm_atomic_state *state = old->restore_state;
11321         int ret;
11322
11323         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11324                       connector->base.id, connector->name,
11325                       encoder->base.id, encoder->name);
11326
11327         if (!state)
11328                 return;
11329
11330         ret = drm_atomic_commit(state);
11331         if (ret)
11332                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11333         drm_atomic_state_put(state);
11334 }
11335
11336 static int i9xx_pll_refclk(struct drm_device *dev,
11337                            const struct intel_crtc_state *pipe_config)
11338 {
11339         struct drm_i915_private *dev_priv = to_i915(dev);
11340         u32 dpll = pipe_config->dpll_hw_state.dpll;
11341
11342         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11343                 return dev_priv->vbt.lvds_ssc_freq;
11344         else if (HAS_PCH_SPLIT(dev_priv))
11345                 return 120000;
11346         else if (!IS_GEN2(dev_priv))
11347                 return 96000;
11348         else
11349                 return 48000;
11350 }
11351
11352 /* Returns the clock of the currently programmed mode of the given pipe. */
11353 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11354                                 struct intel_crtc_state *pipe_config)
11355 {
11356         struct drm_device *dev = crtc->base.dev;
11357         struct drm_i915_private *dev_priv = to_i915(dev);
11358         int pipe = pipe_config->cpu_transcoder;
11359         u32 dpll = pipe_config->dpll_hw_state.dpll;
11360         u32 fp;
11361         struct dpll clock;
11362         int port_clock;
11363         int refclk = i9xx_pll_refclk(dev, pipe_config);
11364
11365         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11366                 fp = pipe_config->dpll_hw_state.fp0;
11367         else
11368                 fp = pipe_config->dpll_hw_state.fp1;
11369
11370         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11371         if (IS_PINEVIEW(dev_priv)) {
11372                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11373                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11374         } else {
11375                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11376                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11377         }
11378
11379         if (!IS_GEN2(dev_priv)) {
11380                 if (IS_PINEVIEW(dev_priv))
11381                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11382                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11383                 else
11384                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11385                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11386
11387                 switch (dpll & DPLL_MODE_MASK) {
11388                 case DPLLB_MODE_DAC_SERIAL:
11389                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11390                                 5 : 10;
11391                         break;
11392                 case DPLLB_MODE_LVDS:
11393                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11394                                 7 : 14;
11395                         break;
11396                 default:
11397                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11398                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11399                         return;
11400                 }
11401
11402                 if (IS_PINEVIEW(dev_priv))
11403                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11404                 else
11405                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11406         } else {
11407                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11408                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11409
11410                 if (is_lvds) {
11411                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11412                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11413
11414                         if (lvds & LVDS_CLKB_POWER_UP)
11415                                 clock.p2 = 7;
11416                         else
11417                                 clock.p2 = 14;
11418                 } else {
11419                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11420                                 clock.p1 = 2;
11421                         else {
11422                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11423                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11424                         }
11425                         if (dpll & PLL_P2_DIVIDE_BY_4)
11426                                 clock.p2 = 4;
11427                         else
11428                                 clock.p2 = 2;
11429                 }
11430
11431                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11432         }
11433
11434         /*
11435          * This value includes pixel_multiplier. We will use
11436          * port_clock to compute adjusted_mode.crtc_clock in the
11437          * encoder's get_config() function.
11438          */
11439         pipe_config->port_clock = port_clock;
11440 }
11441
11442 int intel_dotclock_calculate(int link_freq,
11443                              const struct intel_link_m_n *m_n)
11444 {
11445         /*
11446          * The calculation for the data clock is:
11447          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11448          * But we want to avoid losing precison if possible, so:
11449          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11450          *
11451          * and the link clock is simpler:
11452          * link_clock = (m * link_clock) / n
11453          */
11454
11455         if (!m_n->link_n)
11456                 return 0;
11457
11458         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11459 }
11460
11461 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11462                                    struct intel_crtc_state *pipe_config)
11463 {
11464         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11465
11466         /* read out port_clock from the DPLL */
11467         i9xx_crtc_clock_get(crtc, pipe_config);
11468
11469         /*
11470          * In case there is an active pipe without active ports,
11471          * we may need some idea for the dotclock anyway.
11472          * Calculate one based on the FDI configuration.
11473          */
11474         pipe_config->base.adjusted_mode.crtc_clock =
11475                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11476                                          &pipe_config->fdi_m_n);
11477 }
11478
11479 /** Returns the currently programmed mode of the given pipe. */
11480 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11481                                              struct drm_crtc *crtc)
11482 {
11483         struct drm_i915_private *dev_priv = to_i915(dev);
11484         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11485         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11486         struct drm_display_mode *mode;
11487         struct intel_crtc_state *pipe_config;
11488         int htot = I915_READ(HTOTAL(cpu_transcoder));
11489         int hsync = I915_READ(HSYNC(cpu_transcoder));
11490         int vtot = I915_READ(VTOTAL(cpu_transcoder));
11491         int vsync = I915_READ(VSYNC(cpu_transcoder));
11492         enum pipe pipe = intel_crtc->pipe;
11493
11494         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11495         if (!mode)
11496                 return NULL;
11497
11498         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11499         if (!pipe_config) {
11500                 kfree(mode);
11501                 return NULL;
11502         }
11503
11504         /*
11505          * Construct a pipe_config sufficient for getting the clock info
11506          * back out of crtc_clock_get.
11507          *
11508          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11509          * to use a real value here instead.
11510          */
11511         pipe_config->cpu_transcoder = (enum transcoder) pipe;
11512         pipe_config->pixel_multiplier = 1;
11513         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11514         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11515         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11516         i9xx_crtc_clock_get(intel_crtc, pipe_config);
11517
11518         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11519         mode->hdisplay = (htot & 0xffff) + 1;
11520         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11521         mode->hsync_start = (hsync & 0xffff) + 1;
11522         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11523         mode->vdisplay = (vtot & 0xffff) + 1;
11524         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11525         mode->vsync_start = (vsync & 0xffff) + 1;
11526         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11527
11528         drm_mode_set_name(mode);
11529
11530         kfree(pipe_config);
11531
11532         return mode;
11533 }
11534
11535 static void intel_crtc_destroy(struct drm_crtc *crtc)
11536 {
11537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11538         struct drm_device *dev = crtc->dev;
11539         struct intel_flip_work *work;
11540
11541         spin_lock_irq(&dev->event_lock);
11542         work = intel_crtc->flip_work;
11543         intel_crtc->flip_work = NULL;
11544         spin_unlock_irq(&dev->event_lock);
11545
11546         if (work) {
11547                 cancel_work_sync(&work->mmio_work);
11548                 cancel_work_sync(&work->unpin_work);
11549                 kfree(work);
11550         }
11551
11552         drm_crtc_cleanup(crtc);
11553
11554         kfree(intel_crtc);
11555 }
11556
11557 static void intel_unpin_work_fn(struct work_struct *__work)
11558 {
11559         struct intel_flip_work *work =
11560                 container_of(__work, struct intel_flip_work, unpin_work);
11561         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11562         struct drm_device *dev = crtc->base.dev;
11563         struct drm_plane *primary = crtc->base.primary;
11564
11565         if (is_mmio_work(work))
11566                 flush_work(&work->mmio_work);
11567
11568         mutex_lock(&dev->struct_mutex);
11569         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11570         i915_gem_object_put(work->pending_flip_obj);
11571         mutex_unlock(&dev->struct_mutex);
11572
11573         i915_gem_request_put(work->flip_queued_req);
11574
11575         intel_frontbuffer_flip_complete(to_i915(dev),
11576                                         to_intel_plane(primary)->frontbuffer_bit);
11577         intel_fbc_post_update(crtc);
11578         drm_framebuffer_unreference(work->old_fb);
11579
11580         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11581         atomic_dec(&crtc->unpin_work_count);
11582
11583         kfree(work);
11584 }
11585
11586 /* Is 'a' after or equal to 'b'? */
11587 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11588 {
11589         return !((a - b) & 0x80000000);
11590 }
11591
11592 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11593                                    struct intel_flip_work *work)
11594 {
11595         struct drm_device *dev = crtc->base.dev;
11596         struct drm_i915_private *dev_priv = to_i915(dev);
11597
11598         if (abort_flip_on_reset(crtc))
11599                 return true;
11600
11601         /*
11602          * The relevant registers doen't exist on pre-ctg.
11603          * As the flip done interrupt doesn't trigger for mmio
11604          * flips on gmch platforms, a flip count check isn't
11605          * really needed there. But since ctg has the registers,
11606          * include it in the check anyway.
11607          */
11608         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11609                 return true;
11610
11611         /*
11612          * BDW signals flip done immediately if the plane
11613          * is disabled, even if the plane enable is already
11614          * armed to occur at the next vblank :(
11615          */
11616
11617         /*
11618          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11619          * used the same base address. In that case the mmio flip might
11620          * have completed, but the CS hasn't even executed the flip yet.
11621          *
11622          * A flip count check isn't enough as the CS might have updated
11623          * the base address just after start of vblank, but before we
11624          * managed to process the interrupt. This means we'd complete the
11625          * CS flip too soon.
11626          *
11627          * Combining both checks should get us a good enough result. It may
11628          * still happen that the CS flip has been executed, but has not
11629          * yet actually completed. But in case the base address is the same
11630          * anyway, we don't really care.
11631          */
11632         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11633                 crtc->flip_work->gtt_offset &&
11634                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11635                                     crtc->flip_work->flip_count);
11636 }
11637
11638 static bool
11639 __pageflip_finished_mmio(struct intel_crtc *crtc,
11640                                struct intel_flip_work *work)
11641 {
11642         /*
11643          * MMIO work completes when vblank is different from
11644          * flip_queued_vblank.
11645          *
11646          * Reset counter value doesn't matter, this is handled by
11647          * i915_wait_request finishing early, so no need to handle
11648          * reset here.
11649          */
11650         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11651 }
11652
11653
11654 static bool pageflip_finished(struct intel_crtc *crtc,
11655                               struct intel_flip_work *work)
11656 {
11657         if (!atomic_read(&work->pending))
11658                 return false;
11659
11660         smp_rmb();
11661
11662         if (is_mmio_work(work))
11663                 return __pageflip_finished_mmio(crtc, work);
11664         else
11665                 return __pageflip_finished_cs(crtc, work);
11666 }
11667
11668 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11669 {
11670         struct drm_device *dev = &dev_priv->drm;
11671         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11672         struct intel_flip_work *work;
11673         unsigned long flags;
11674
11675         /* Ignore early vblank irqs */
11676         if (!crtc)
11677                 return;
11678
11679         /*
11680          * This is called both by irq handlers and the reset code (to complete
11681          * lost pageflips) so needs the full irqsave spinlocks.
11682          */
11683         spin_lock_irqsave(&dev->event_lock, flags);
11684         work = crtc->flip_work;
11685
11686         if (work != NULL &&
11687             !is_mmio_work(work) &&
11688             pageflip_finished(crtc, work))
11689                 page_flip_completed(crtc);
11690
11691         spin_unlock_irqrestore(&dev->event_lock, flags);
11692 }
11693
11694 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11695 {
11696         struct drm_device *dev = &dev_priv->drm;
11697         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11698         struct intel_flip_work *work;
11699         unsigned long flags;
11700
11701         /* Ignore early vblank irqs */
11702         if (!crtc)
11703                 return;
11704
11705         /*
11706          * This is called both by irq handlers and the reset code (to complete
11707          * lost pageflips) so needs the full irqsave spinlocks.
11708          */
11709         spin_lock_irqsave(&dev->event_lock, flags);
11710         work = crtc->flip_work;
11711
11712         if (work != NULL &&
11713             is_mmio_work(work) &&
11714             pageflip_finished(crtc, work))
11715                 page_flip_completed(crtc);
11716
11717         spin_unlock_irqrestore(&dev->event_lock, flags);
11718 }
11719
11720 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11721                                                struct intel_flip_work *work)
11722 {
11723         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11724
11725         /* Ensure that the work item is consistent when activating it ... */
11726         smp_mb__before_atomic();
11727         atomic_set(&work->pending, 1);
11728 }
11729
11730 static int intel_gen2_queue_flip(struct drm_device *dev,
11731                                  struct drm_crtc *crtc,
11732                                  struct drm_framebuffer *fb,
11733                                  struct drm_i915_gem_object *obj,
11734                                  struct drm_i915_gem_request *req,
11735                                  uint32_t flags)
11736 {
11737         struct intel_ring *ring = req->ring;
11738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11739         u32 flip_mask;
11740         int ret;
11741
11742         ret = intel_ring_begin(req, 6);
11743         if (ret)
11744                 return ret;
11745
11746         /* Can't queue multiple flips, so wait for the previous
11747          * one to finish before executing the next.
11748          */
11749         if (intel_crtc->plane)
11750                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11751         else
11752                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11753         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11754         intel_ring_emit(ring, MI_NOOP);
11755         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11756                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11757         intel_ring_emit(ring, fb->pitches[0]);
11758         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11759         intel_ring_emit(ring, 0); /* aux display base address, unused */
11760
11761         return 0;
11762 }
11763
11764 static int intel_gen3_queue_flip(struct drm_device *dev,
11765                                  struct drm_crtc *crtc,
11766                                  struct drm_framebuffer *fb,
11767                                  struct drm_i915_gem_object *obj,
11768                                  struct drm_i915_gem_request *req,
11769                                  uint32_t flags)
11770 {
11771         struct intel_ring *ring = req->ring;
11772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11773         u32 flip_mask;
11774         int ret;
11775
11776         ret = intel_ring_begin(req, 6);
11777         if (ret)
11778                 return ret;
11779
11780         if (intel_crtc->plane)
11781                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11782         else
11783                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11784         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11785         intel_ring_emit(ring, MI_NOOP);
11786         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11787                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11788         intel_ring_emit(ring, fb->pitches[0]);
11789         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11790         intel_ring_emit(ring, MI_NOOP);
11791
11792         return 0;
11793 }
11794
11795 static int intel_gen4_queue_flip(struct drm_device *dev,
11796                                  struct drm_crtc *crtc,
11797                                  struct drm_framebuffer *fb,
11798                                  struct drm_i915_gem_object *obj,
11799                                  struct drm_i915_gem_request *req,
11800                                  uint32_t flags)
11801 {
11802         struct intel_ring *ring = req->ring;
11803         struct drm_i915_private *dev_priv = to_i915(dev);
11804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11805         uint32_t pf, pipesrc;
11806         int ret;
11807
11808         ret = intel_ring_begin(req, 4);
11809         if (ret)
11810                 return ret;
11811
11812         /* i965+ uses the linear or tiled offsets from the
11813          * Display Registers (which do not change across a page-flip)
11814          * so we need only reprogram the base address.
11815          */
11816         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11817                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11818         intel_ring_emit(ring, fb->pitches[0]);
11819         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11820                         intel_fb_modifier_to_tiling(fb->modifier));
11821
11822         /* XXX Enabling the panel-fitter across page-flip is so far
11823          * untested on non-native modes, so ignore it for now.
11824          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11825          */
11826         pf = 0;
11827         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11828         intel_ring_emit(ring, pf | pipesrc);
11829
11830         return 0;
11831 }
11832
11833 static int intel_gen6_queue_flip(struct drm_device *dev,
11834                                  struct drm_crtc *crtc,
11835                                  struct drm_framebuffer *fb,
11836                                  struct drm_i915_gem_object *obj,
11837                                  struct drm_i915_gem_request *req,
11838                                  uint32_t flags)
11839 {
11840         struct intel_ring *ring = req->ring;
11841         struct drm_i915_private *dev_priv = to_i915(dev);
11842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11843         uint32_t pf, pipesrc;
11844         int ret;
11845
11846         ret = intel_ring_begin(req, 4);
11847         if (ret)
11848                 return ret;
11849
11850         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11851                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11852         intel_ring_emit(ring, fb->pitches[0] |
11853                         intel_fb_modifier_to_tiling(fb->modifier));
11854         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11855
11856         /* Contrary to the suggestions in the documentation,
11857          * "Enable Panel Fitter" does not seem to be required when page
11858          * flipping with a non-native mode, and worse causes a normal
11859          * modeset to fail.
11860          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11861          */
11862         pf = 0;
11863         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11864         intel_ring_emit(ring, pf | pipesrc);
11865
11866         return 0;
11867 }
11868
11869 static int intel_gen7_queue_flip(struct drm_device *dev,
11870                                  struct drm_crtc *crtc,
11871                                  struct drm_framebuffer *fb,
11872                                  struct drm_i915_gem_object *obj,
11873                                  struct drm_i915_gem_request *req,
11874                                  uint32_t flags)
11875 {
11876         struct drm_i915_private *dev_priv = to_i915(dev);
11877         struct intel_ring *ring = req->ring;
11878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11879         uint32_t plane_bit = 0;
11880         int len, ret;
11881
11882         switch (intel_crtc->plane) {
11883         case PLANE_A:
11884                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11885                 break;
11886         case PLANE_B:
11887                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11888                 break;
11889         case PLANE_C:
11890                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11891                 break;
11892         default:
11893                 WARN_ONCE(1, "unknown plane in flip command\n");
11894                 return -ENODEV;
11895         }
11896
11897         len = 4;
11898         if (req->engine->id == RCS) {
11899                 len += 6;
11900                 /*
11901                  * On Gen 8, SRM is now taking an extra dword to accommodate
11902                  * 48bits addresses, and we need a NOOP for the batch size to
11903                  * stay even.
11904                  */
11905                 if (IS_GEN8(dev_priv))
11906                         len += 2;
11907         }
11908
11909         /*
11910          * BSpec MI_DISPLAY_FLIP for IVB:
11911          * "The full packet must be contained within the same cache line."
11912          *
11913          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11914          * cacheline, if we ever start emitting more commands before
11915          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11916          * then do the cacheline alignment, and finally emit the
11917          * MI_DISPLAY_FLIP.
11918          */
11919         ret = intel_ring_cacheline_align(req);
11920         if (ret)
11921                 return ret;
11922
11923         ret = intel_ring_begin(req, len);
11924         if (ret)
11925                 return ret;
11926
11927         /* Unmask the flip-done completion message. Note that the bspec says that
11928          * we should do this for both the BCS and RCS, and that we must not unmask
11929          * more than one flip event at any time (or ensure that one flip message
11930          * can be sent by waiting for flip-done prior to queueing new flips).
11931          * Experimentation says that BCS works despite DERRMR masking all
11932          * flip-done completion events and that unmasking all planes at once
11933          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11934          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11935          */
11936         if (req->engine->id == RCS) {
11937                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11938                 intel_ring_emit_reg(ring, DERRMR);
11939                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11940                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11941                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11942                 if (IS_GEN8(dev_priv))
11943                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11944                                               MI_SRM_LRM_GLOBAL_GTT);
11945                 else
11946                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11947                                               MI_SRM_LRM_GLOBAL_GTT);
11948                 intel_ring_emit_reg(ring, DERRMR);
11949                 intel_ring_emit(ring,
11950                                 i915_ggtt_offset(req->engine->scratch) + 256);
11951                 if (IS_GEN8(dev_priv)) {
11952                         intel_ring_emit(ring, 0);
11953                         intel_ring_emit(ring, MI_NOOP);
11954                 }
11955         }
11956
11957         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11958         intel_ring_emit(ring, fb->pitches[0] |
11959                         intel_fb_modifier_to_tiling(fb->modifier));
11960         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11961         intel_ring_emit(ring, (MI_NOOP));
11962
11963         return 0;
11964 }
11965
11966 static bool use_mmio_flip(struct intel_engine_cs *engine,
11967                           struct drm_i915_gem_object *obj)
11968 {
11969         /*
11970          * This is not being used for older platforms, because
11971          * non-availability of flip done interrupt forces us to use
11972          * CS flips. Older platforms derive flip done using some clever
11973          * tricks involving the flip_pending status bits and vblank irqs.
11974          * So using MMIO flips there would disrupt this mechanism.
11975          */
11976
11977         if (engine == NULL)
11978                 return true;
11979
11980         if (INTEL_GEN(engine->i915) < 5)
11981                 return false;
11982
11983         if (i915.use_mmio_flip < 0)
11984                 return false;
11985         else if (i915.use_mmio_flip > 0)
11986                 return true;
11987         else if (i915.enable_execlists)
11988                 return true;
11989
11990         return engine != i915_gem_object_last_write_engine(obj);
11991 }
11992
11993 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11994                              unsigned int rotation,
11995                              struct intel_flip_work *work)
11996 {
11997         struct drm_device *dev = intel_crtc->base.dev;
11998         struct drm_i915_private *dev_priv = to_i915(dev);
11999         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12000         const enum pipe pipe = intel_crtc->pipe;
12001         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
12002
12003         ctl = I915_READ(PLANE_CTL(pipe, 0));
12004         ctl &= ~PLANE_CTL_TILED_MASK;
12005         switch (fb->modifier) {
12006         case DRM_FORMAT_MOD_NONE:
12007                 break;
12008         case I915_FORMAT_MOD_X_TILED:
12009                 ctl |= PLANE_CTL_TILED_X;
12010                 break;
12011         case I915_FORMAT_MOD_Y_TILED:
12012                 ctl |= PLANE_CTL_TILED_Y;
12013                 break;
12014         case I915_FORMAT_MOD_Yf_TILED:
12015                 ctl |= PLANE_CTL_TILED_YF;
12016                 break;
12017         default:
12018                 MISSING_CASE(fb->modifier);
12019         }
12020
12021         /*
12022          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
12023          * PLANE_SURF updates, the update is then guaranteed to be atomic.
12024          */
12025         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
12026         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
12027
12028         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
12029         POSTING_READ(PLANE_SURF(pipe, 0));
12030 }
12031
12032 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
12033                              struct intel_flip_work *work)
12034 {
12035         struct drm_device *dev = intel_crtc->base.dev;
12036         struct drm_i915_private *dev_priv = to_i915(dev);
12037         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12038         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12039         u32 dspcntr;
12040
12041         dspcntr = I915_READ(reg);
12042
12043         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
12044                 dspcntr |= DISPPLANE_TILED;
12045         else
12046                 dspcntr &= ~DISPPLANE_TILED;
12047
12048         I915_WRITE(reg, dspcntr);
12049
12050         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12051         POSTING_READ(DSPSURF(intel_crtc->plane));
12052 }
12053
12054 static void intel_mmio_flip_work_func(struct work_struct *w)
12055 {
12056         struct intel_flip_work *work =
12057                 container_of(w, struct intel_flip_work, mmio_work);
12058         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12059         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12060         struct intel_framebuffer *intel_fb =
12061                 to_intel_framebuffer(crtc->base.primary->fb);
12062         struct drm_i915_gem_object *obj = intel_fb->obj;
12063
12064         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
12065
12066         intel_pipe_update_start(crtc);
12067
12068         if (INTEL_GEN(dev_priv) >= 9)
12069                 skl_do_mmio_flip(crtc, work->rotation, work);
12070         else
12071                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12072                 ilk_do_mmio_flip(crtc, work);
12073
12074         intel_pipe_update_end(crtc, work);
12075 }
12076
12077 static int intel_default_queue_flip(struct drm_device *dev,
12078                                     struct drm_crtc *crtc,
12079                                     struct drm_framebuffer *fb,
12080                                     struct drm_i915_gem_object *obj,
12081                                     struct drm_i915_gem_request *req,
12082                                     uint32_t flags)
12083 {
12084         return -ENODEV;
12085 }
12086
12087 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12088                                       struct intel_crtc *intel_crtc,
12089                                       struct intel_flip_work *work)
12090 {
12091         u32 addr, vblank;
12092
12093         if (!atomic_read(&work->pending))
12094                 return false;
12095
12096         smp_rmb();
12097
12098         vblank = intel_crtc_get_vblank_counter(intel_crtc);
12099         if (work->flip_ready_vblank == 0) {
12100                 if (work->flip_queued_req &&
12101                     !i915_gem_request_completed(work->flip_queued_req))
12102                         return false;
12103
12104                 work->flip_ready_vblank = vblank;
12105         }
12106
12107         if (vblank - work->flip_ready_vblank < 3)
12108                 return false;
12109
12110         /* Potential stall - if we see that the flip has happened,
12111          * assume a missed interrupt. */
12112         if (INTEL_GEN(dev_priv) >= 4)
12113                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12114         else
12115                 addr = I915_READ(DSPADDR(intel_crtc->plane));
12116
12117         /* There is a potential issue here with a false positive after a flip
12118          * to the same address. We could address this by checking for a
12119          * non-incrementing frame counter.
12120          */
12121         return addr == work->gtt_offset;
12122 }
12123
12124 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12125 {
12126         struct drm_device *dev = &dev_priv->drm;
12127         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12128         struct intel_flip_work *work;
12129
12130         WARN_ON(!in_interrupt());
12131
12132         if (crtc == NULL)
12133                 return;
12134
12135         spin_lock(&dev->event_lock);
12136         work = crtc->flip_work;
12137
12138         if (work != NULL && !is_mmio_work(work) &&
12139             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
12140                 WARN_ONCE(1,
12141                           "Kicking stuck page flip: queued at %d, now %d\n",
12142                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
12143                 page_flip_completed(crtc);
12144                 work = NULL;
12145         }
12146
12147         if (work != NULL && !is_mmio_work(work) &&
12148             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
12149                 intel_queue_rps_boost_for_request(work->flip_queued_req);
12150         spin_unlock(&dev->event_lock);
12151 }
12152
12153 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12154                                 struct drm_framebuffer *fb,
12155                                 struct drm_pending_vblank_event *event,
12156                                 uint32_t page_flip_flags)
12157 {
12158         struct drm_device *dev = crtc->dev;
12159         struct drm_i915_private *dev_priv = to_i915(dev);
12160         struct drm_framebuffer *old_fb = crtc->primary->fb;
12161         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12163         struct drm_plane *primary = crtc->primary;
12164         enum pipe pipe = intel_crtc->pipe;
12165         struct intel_flip_work *work;
12166         struct intel_engine_cs *engine;
12167         bool mmio_flip;
12168         struct drm_i915_gem_request *request;
12169         struct i915_vma *vma;
12170         int ret;
12171
12172         /*
12173          * drm_mode_page_flip_ioctl() should already catch this, but double
12174          * check to be safe.  In the future we may enable pageflipping from
12175          * a disabled primary plane.
12176          */
12177         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12178                 return -EBUSY;
12179
12180         /* Can't change pixel format via MI display flips. */
12181         if (fb->pixel_format != crtc->primary->fb->pixel_format)
12182                 return -EINVAL;
12183
12184         /*
12185          * TILEOFF/LINOFF registers can't be changed via MI display flips.
12186          * Note that pitch changes could also affect these register.
12187          */
12188         if (INTEL_GEN(dev_priv) > 3 &&
12189             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12190              fb->pitches[0] != crtc->primary->fb->pitches[0]))
12191                 return -EINVAL;
12192
12193         if (i915_terminally_wedged(&dev_priv->gpu_error))
12194                 goto out_hang;
12195
12196         work = kzalloc(sizeof(*work), GFP_KERNEL);
12197         if (work == NULL)
12198                 return -ENOMEM;
12199
12200         work->event = event;
12201         work->crtc = crtc;
12202         work->old_fb = old_fb;
12203         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12204
12205         ret = drm_crtc_vblank_get(crtc);
12206         if (ret)
12207                 goto free_work;
12208
12209         /* We borrow the event spin lock for protecting flip_work */
12210         spin_lock_irq(&dev->event_lock);
12211         if (intel_crtc->flip_work) {
12212                 /* Before declaring the flip queue wedged, check if
12213                  * the hardware completed the operation behind our backs.
12214                  */
12215                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12216                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12217                         page_flip_completed(intel_crtc);
12218                 } else {
12219                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12220                         spin_unlock_irq(&dev->event_lock);
12221
12222                         drm_crtc_vblank_put(crtc);
12223                         kfree(work);
12224                         return -EBUSY;
12225                 }
12226         }
12227         intel_crtc->flip_work = work;
12228         spin_unlock_irq(&dev->event_lock);
12229
12230         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12231                 flush_workqueue(dev_priv->wq);
12232
12233         /* Reference the objects for the scheduled work. */
12234         drm_framebuffer_reference(work->old_fb);
12235
12236         crtc->primary->fb = fb;
12237         update_state_fb(crtc->primary);
12238
12239         work->pending_flip_obj = i915_gem_object_get(obj);
12240
12241         ret = i915_mutex_lock_interruptible(dev);
12242         if (ret)
12243                 goto cleanup;
12244
12245         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12246         if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12247                 ret = -EIO;
12248                 goto unlock;
12249         }
12250
12251         atomic_inc(&intel_crtc->unpin_work_count);
12252
12253         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12254                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12255
12256         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
12257                 engine = dev_priv->engine[BCS];
12258                 if (fb->modifier != old_fb->modifier)
12259                         /* vlv: DISPLAY_FLIP fails to change tiling */
12260                         engine = NULL;
12261         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
12262                 engine = dev_priv->engine[BCS];
12263         } else if (INTEL_GEN(dev_priv) >= 7) {
12264                 engine = i915_gem_object_last_write_engine(obj);
12265                 if (engine == NULL || engine->id != RCS)
12266                         engine = dev_priv->engine[BCS];
12267         } else {
12268                 engine = dev_priv->engine[RCS];
12269         }
12270
12271         mmio_flip = use_mmio_flip(engine, obj);
12272
12273         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12274         if (IS_ERR(vma)) {
12275                 ret = PTR_ERR(vma);
12276                 goto cleanup_pending;
12277         }
12278
12279         work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12280         work->gtt_offset += intel_crtc->dspaddr_offset;
12281         work->rotation = crtc->primary->state->rotation;
12282
12283         /*
12284          * There's the potential that the next frame will not be compatible with
12285          * FBC, so we want to call pre_update() before the actual page flip.
12286          * The problem is that pre_update() caches some information about the fb
12287          * object, so we want to do this only after the object is pinned. Let's
12288          * be on the safe side and do this immediately before scheduling the
12289          * flip.
12290          */
12291         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12292                              to_intel_plane_state(primary->state));
12293
12294         if (mmio_flip) {
12295                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12296                 queue_work(system_unbound_wq, &work->mmio_work);
12297         } else {
12298                 request = i915_gem_request_alloc(engine,
12299                                                  dev_priv->kernel_context);
12300                 if (IS_ERR(request)) {
12301                         ret = PTR_ERR(request);
12302                         goto cleanup_unpin;
12303                 }
12304
12305                 ret = i915_gem_request_await_object(request, obj, false);
12306                 if (ret)
12307                         goto cleanup_request;
12308
12309                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12310                                                    page_flip_flags);
12311                 if (ret)
12312                         goto cleanup_request;
12313
12314                 intel_mark_page_flip_active(intel_crtc, work);
12315
12316                 work->flip_queued_req = i915_gem_request_get(request);
12317                 i915_add_request_no_flush(request);
12318         }
12319
12320         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12321         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12322                           to_intel_plane(primary)->frontbuffer_bit);
12323         mutex_unlock(&dev->struct_mutex);
12324
12325         intel_frontbuffer_flip_prepare(to_i915(dev),
12326                                        to_intel_plane(primary)->frontbuffer_bit);
12327
12328         trace_i915_flip_request(intel_crtc->plane, obj);
12329
12330         return 0;
12331
12332 cleanup_request:
12333         i915_add_request_no_flush(request);
12334 cleanup_unpin:
12335         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12336 cleanup_pending:
12337         atomic_dec(&intel_crtc->unpin_work_count);
12338 unlock:
12339         mutex_unlock(&dev->struct_mutex);
12340 cleanup:
12341         crtc->primary->fb = old_fb;
12342         update_state_fb(crtc->primary);
12343
12344         i915_gem_object_put(obj);
12345         drm_framebuffer_unreference(work->old_fb);
12346
12347         spin_lock_irq(&dev->event_lock);
12348         intel_crtc->flip_work = NULL;
12349         spin_unlock_irq(&dev->event_lock);
12350
12351         drm_crtc_vblank_put(crtc);
12352 free_work:
12353         kfree(work);
12354
12355         if (ret == -EIO) {
12356                 struct drm_atomic_state *state;
12357                 struct drm_plane_state *plane_state;
12358
12359 out_hang:
12360                 state = drm_atomic_state_alloc(dev);
12361                 if (!state)
12362                         return -ENOMEM;
12363                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12364
12365 retry:
12366                 plane_state = drm_atomic_get_plane_state(state, primary);
12367                 ret = PTR_ERR_OR_ZERO(plane_state);
12368                 if (!ret) {
12369                         drm_atomic_set_fb_for_plane(plane_state, fb);
12370
12371                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12372                         if (!ret)
12373                                 ret = drm_atomic_commit(state);
12374                 }
12375
12376                 if (ret == -EDEADLK) {
12377                         drm_modeset_backoff(state->acquire_ctx);
12378                         drm_atomic_state_clear(state);
12379                         goto retry;
12380                 }
12381
12382                 drm_atomic_state_put(state);
12383
12384                 if (ret == 0 && event) {
12385                         spin_lock_irq(&dev->event_lock);
12386                         drm_crtc_send_vblank_event(crtc, event);
12387                         spin_unlock_irq(&dev->event_lock);
12388                 }
12389         }
12390         return ret;
12391 }
12392
12393
12394 /**
12395  * intel_wm_need_update - Check whether watermarks need updating
12396  * @plane: drm plane
12397  * @state: new plane state
12398  *
12399  * Check current plane state versus the new one to determine whether
12400  * watermarks need to be recalculated.
12401  *
12402  * Returns true or false.
12403  */
12404 static bool intel_wm_need_update(struct drm_plane *plane,
12405                                  struct drm_plane_state *state)
12406 {
12407         struct intel_plane_state *new = to_intel_plane_state(state);
12408         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12409
12410         /* Update watermarks on tiling or size changes. */
12411         if (new->base.visible != cur->base.visible)
12412                 return true;
12413
12414         if (!cur->base.fb || !new->base.fb)
12415                 return false;
12416
12417         if (cur->base.fb->modifier != new->base.fb->modifier ||
12418             cur->base.rotation != new->base.rotation ||
12419             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12420             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12421             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12422             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12423                 return true;
12424
12425         return false;
12426 }
12427
12428 static bool needs_scaling(struct intel_plane_state *state)
12429 {
12430         int src_w = drm_rect_width(&state->base.src) >> 16;
12431         int src_h = drm_rect_height(&state->base.src) >> 16;
12432         int dst_w = drm_rect_width(&state->base.dst);
12433         int dst_h = drm_rect_height(&state->base.dst);
12434
12435         return (src_w != dst_w || src_h != dst_h);
12436 }
12437
12438 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12439                                     struct drm_plane_state *plane_state)
12440 {
12441         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12442         struct drm_crtc *crtc = crtc_state->crtc;
12443         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12444         struct drm_plane *plane = plane_state->plane;
12445         struct drm_device *dev = crtc->dev;
12446         struct drm_i915_private *dev_priv = to_i915(dev);
12447         struct intel_plane_state *old_plane_state =
12448                 to_intel_plane_state(plane->state);
12449         bool mode_changed = needs_modeset(crtc_state);
12450         bool was_crtc_enabled = crtc->state->active;
12451         bool is_crtc_enabled = crtc_state->active;
12452         bool turn_off, turn_on, visible, was_visible;
12453         struct drm_framebuffer *fb = plane_state->fb;
12454         int ret;
12455
12456         if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12457                 ret = skl_update_scaler_plane(
12458                         to_intel_crtc_state(crtc_state),
12459                         to_intel_plane_state(plane_state));
12460                 if (ret)
12461                         return ret;
12462         }
12463
12464         was_visible = old_plane_state->base.visible;
12465         visible = to_intel_plane_state(plane_state)->base.visible;
12466
12467         if (!was_crtc_enabled && WARN_ON(was_visible))
12468                 was_visible = false;
12469
12470         /*
12471          * Visibility is calculated as if the crtc was on, but
12472          * after scaler setup everything depends on it being off
12473          * when the crtc isn't active.
12474          *
12475          * FIXME this is wrong for watermarks. Watermarks should also
12476          * be computed as if the pipe would be active. Perhaps move
12477          * per-plane wm computation to the .check_plane() hook, and
12478          * only combine the results from all planes in the current place?
12479          */
12480         if (!is_crtc_enabled)
12481                 to_intel_plane_state(plane_state)->base.visible = visible = false;
12482
12483         if (!was_visible && !visible)
12484                 return 0;
12485
12486         if (fb != old_plane_state->base.fb)
12487                 pipe_config->fb_changed = true;
12488
12489         turn_off = was_visible && (!visible || mode_changed);
12490         turn_on = visible && (!was_visible || mode_changed);
12491
12492         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12493                          intel_crtc->base.base.id,
12494                          intel_crtc->base.name,
12495                          plane->base.id, plane->name,
12496                          fb ? fb->base.id : -1);
12497
12498         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12499                          plane->base.id, plane->name,
12500                          was_visible, visible,
12501                          turn_off, turn_on, mode_changed);
12502
12503         if (turn_on) {
12504                 pipe_config->update_wm_pre = true;
12505
12506                 /* must disable cxsr around plane enable/disable */
12507                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12508                         pipe_config->disable_cxsr = true;
12509         } else if (turn_off) {
12510                 pipe_config->update_wm_post = true;
12511
12512                 /* must disable cxsr around plane enable/disable */
12513                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12514                         pipe_config->disable_cxsr = true;
12515         } else if (intel_wm_need_update(plane, plane_state)) {
12516                 /* FIXME bollocks */
12517                 pipe_config->update_wm_pre = true;
12518                 pipe_config->update_wm_post = true;
12519         }
12520
12521         /* Pre-gen9 platforms need two-step watermark updates */
12522         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12523             INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks)
12524                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12525
12526         if (visible || was_visible)
12527                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12528
12529         /*
12530          * WaCxSRDisabledForSpriteScaling:ivb
12531          *
12532          * cstate->update_wm was already set above, so this flag will
12533          * take effect when we commit and program watermarks.
12534          */
12535         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
12536             needs_scaling(to_intel_plane_state(plane_state)) &&
12537             !needs_scaling(old_plane_state))
12538                 pipe_config->disable_lp_wm = true;
12539
12540         return 0;
12541 }
12542
12543 static bool encoders_cloneable(const struct intel_encoder *a,
12544                                const struct intel_encoder *b)
12545 {
12546         /* masks could be asymmetric, so check both ways */
12547         return a == b || (a->cloneable & (1 << b->type) &&
12548                           b->cloneable & (1 << a->type));
12549 }
12550
12551 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12552                                          struct intel_crtc *crtc,
12553                                          struct intel_encoder *encoder)
12554 {
12555         struct intel_encoder *source_encoder;
12556         struct drm_connector *connector;
12557         struct drm_connector_state *connector_state;
12558         int i;
12559
12560         for_each_connector_in_state(state, connector, connector_state, i) {
12561                 if (connector_state->crtc != &crtc->base)
12562                         continue;
12563
12564                 source_encoder =
12565                         to_intel_encoder(connector_state->best_encoder);
12566                 if (!encoders_cloneable(encoder, source_encoder))
12567                         return false;
12568         }
12569
12570         return true;
12571 }
12572
12573 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12574                                    struct drm_crtc_state *crtc_state)
12575 {
12576         struct drm_device *dev = crtc->dev;
12577         struct drm_i915_private *dev_priv = to_i915(dev);
12578         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12579         struct intel_crtc_state *pipe_config =
12580                 to_intel_crtc_state(crtc_state);
12581         struct drm_atomic_state *state = crtc_state->state;
12582         int ret;
12583         bool mode_changed = needs_modeset(crtc_state);
12584
12585         if (mode_changed && !crtc_state->active)
12586                 pipe_config->update_wm_post = true;
12587
12588         if (mode_changed && crtc_state->enable &&
12589             dev_priv->display.crtc_compute_clock &&
12590             !WARN_ON(pipe_config->shared_dpll)) {
12591                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12592                                                            pipe_config);
12593                 if (ret)
12594                         return ret;
12595         }
12596
12597         if (crtc_state->color_mgmt_changed) {
12598                 ret = intel_color_check(crtc, crtc_state);
12599                 if (ret)
12600                         return ret;
12601
12602                 /*
12603                  * Changing color management on Intel hardware is
12604                  * handled as part of planes update.
12605                  */
12606                 crtc_state->planes_changed = true;
12607         }
12608
12609         ret = 0;
12610         if (dev_priv->display.compute_pipe_wm) {
12611                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12612                 if (ret) {
12613                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12614                         return ret;
12615                 }
12616         }
12617
12618         if (dev_priv->display.compute_intermediate_wm &&
12619             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12620                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12621                         return 0;
12622
12623                 /*
12624                  * Calculate 'intermediate' watermarks that satisfy both the
12625                  * old state and the new state.  We can program these
12626                  * immediately.
12627                  */
12628                 ret = dev_priv->display.compute_intermediate_wm(dev,
12629                                                                 intel_crtc,
12630                                                                 pipe_config);
12631                 if (ret) {
12632                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12633                         return ret;
12634                 }
12635         } else if (dev_priv->display.compute_intermediate_wm) {
12636                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12637                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12638         }
12639
12640         if (INTEL_GEN(dev_priv) >= 9) {
12641                 if (mode_changed)
12642                         ret = skl_update_scaler_crtc(pipe_config);
12643
12644                 if (!ret)
12645                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12646                                                          pipe_config);
12647         }
12648
12649         return ret;
12650 }
12651
12652 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12653         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12654         .atomic_begin = intel_begin_crtc_commit,
12655         .atomic_flush = intel_finish_crtc_commit,
12656         .atomic_check = intel_crtc_atomic_check,
12657 };
12658
12659 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12660 {
12661         struct intel_connector *connector;
12662
12663         for_each_intel_connector(dev, connector) {
12664                 if (connector->base.state->crtc)
12665                         drm_connector_unreference(&connector->base);
12666
12667                 if (connector->base.encoder) {
12668                         connector->base.state->best_encoder =
12669                                 connector->base.encoder;
12670                         connector->base.state->crtc =
12671                                 connector->base.encoder->crtc;
12672
12673                         drm_connector_reference(&connector->base);
12674                 } else {
12675                         connector->base.state->best_encoder = NULL;
12676                         connector->base.state->crtc = NULL;
12677                 }
12678         }
12679 }
12680
12681 static void
12682 connected_sink_compute_bpp(struct intel_connector *connector,
12683                            struct intel_crtc_state *pipe_config)
12684 {
12685         const struct drm_display_info *info = &connector->base.display_info;
12686         int bpp = pipe_config->pipe_bpp;
12687
12688         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12689                       connector->base.base.id,
12690                       connector->base.name);
12691
12692         /* Don't use an invalid EDID bpc value */
12693         if (info->bpc != 0 && info->bpc * 3 < bpp) {
12694                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12695                               bpp, info->bpc * 3);
12696                 pipe_config->pipe_bpp = info->bpc * 3;
12697         }
12698
12699         /* Clamp bpp to 8 on screens without EDID 1.4 */
12700         if (info->bpc == 0 && bpp > 24) {
12701                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12702                               bpp);
12703                 pipe_config->pipe_bpp = 24;
12704         }
12705 }
12706
12707 static int
12708 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12709                           struct intel_crtc_state *pipe_config)
12710 {
12711         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12712         struct drm_atomic_state *state;
12713         struct drm_connector *connector;
12714         struct drm_connector_state *connector_state;
12715         int bpp, i;
12716
12717         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12718             IS_CHERRYVIEW(dev_priv)))
12719                 bpp = 10*3;
12720         else if (INTEL_GEN(dev_priv) >= 5)
12721                 bpp = 12*3;
12722         else
12723                 bpp = 8*3;
12724
12725
12726         pipe_config->pipe_bpp = bpp;
12727
12728         state = pipe_config->base.state;
12729
12730         /* Clamp display bpp to EDID value */
12731         for_each_connector_in_state(state, connector, connector_state, i) {
12732                 if (connector_state->crtc != &crtc->base)
12733                         continue;
12734
12735                 connected_sink_compute_bpp(to_intel_connector(connector),
12736                                            pipe_config);
12737         }
12738
12739         return bpp;
12740 }
12741
12742 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12743 {
12744         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12745                         "type: 0x%x flags: 0x%x\n",
12746                 mode->crtc_clock,
12747                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12748                 mode->crtc_hsync_end, mode->crtc_htotal,
12749                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12750                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12751 }
12752
12753 static inline void
12754 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
12755                       unsigned int lane_count, struct intel_link_m_n *m_n)
12756 {
12757         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12758                       id, lane_count,
12759                       m_n->gmch_m, m_n->gmch_n,
12760                       m_n->link_m, m_n->link_n, m_n->tu);
12761 }
12762
12763 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12764                                    struct intel_crtc_state *pipe_config,
12765                                    const char *context)
12766 {
12767         struct drm_device *dev = crtc->base.dev;
12768         struct drm_i915_private *dev_priv = to_i915(dev);
12769         struct drm_plane *plane;
12770         struct intel_plane *intel_plane;
12771         struct intel_plane_state *state;
12772         struct drm_framebuffer *fb;
12773
12774         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
12775                       crtc->base.base.id, crtc->base.name, context);
12776
12777         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12778                       transcoder_name(pipe_config->cpu_transcoder),
12779                       pipe_config->pipe_bpp, pipe_config->dither);
12780
12781         if (pipe_config->has_pch_encoder)
12782                 intel_dump_m_n_config(pipe_config, "fdi",
12783                                       pipe_config->fdi_lanes,
12784                                       &pipe_config->fdi_m_n);
12785
12786         if (intel_crtc_has_dp_encoder(pipe_config)) {
12787                 intel_dump_m_n_config(pipe_config, "dp m_n",
12788                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12789                 if (pipe_config->has_drrs)
12790                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12791                                               pipe_config->lane_count,
12792                                               &pipe_config->dp_m2_n2);
12793         }
12794
12795         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12796                       pipe_config->has_audio, pipe_config->has_infoframe);
12797
12798         DRM_DEBUG_KMS("requested mode:\n");
12799         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12800         DRM_DEBUG_KMS("adjusted mode:\n");
12801         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12802         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12803         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n",
12804                       pipe_config->port_clock,
12805                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12806
12807         if (INTEL_GEN(dev_priv) >= 9)
12808                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12809                               crtc->num_scalers,
12810                               pipe_config->scaler_state.scaler_users,
12811                               pipe_config->scaler_state.scaler_id);
12812
12813         if (HAS_GMCH_DISPLAY(dev_priv))
12814                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12815                               pipe_config->gmch_pfit.control,
12816                               pipe_config->gmch_pfit.pgm_ratios,
12817                               pipe_config->gmch_pfit.lvds_border_bits);
12818         else
12819                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12820                               pipe_config->pch_pfit.pos,
12821                               pipe_config->pch_pfit.size,
12822                               enableddisabled(pipe_config->pch_pfit.enabled));
12823
12824         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12825                       pipe_config->ips_enabled, pipe_config->double_wide);
12826
12827         if (IS_GEN9_LP(dev_priv)) {
12828                 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12829                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12830                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12831                               pipe_config->dpll_hw_state.ebb0,
12832                               pipe_config->dpll_hw_state.ebb4,
12833                               pipe_config->dpll_hw_state.pll0,
12834                               pipe_config->dpll_hw_state.pll1,
12835                               pipe_config->dpll_hw_state.pll2,
12836                               pipe_config->dpll_hw_state.pll3,
12837                               pipe_config->dpll_hw_state.pll6,
12838                               pipe_config->dpll_hw_state.pll8,
12839                               pipe_config->dpll_hw_state.pll9,
12840                               pipe_config->dpll_hw_state.pll10,
12841                               pipe_config->dpll_hw_state.pcsdw12);
12842         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
12843                 DRM_DEBUG_KMS("dpll_hw_state: "
12844                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12845                               pipe_config->dpll_hw_state.ctrl1,
12846                               pipe_config->dpll_hw_state.cfgcr1,
12847                               pipe_config->dpll_hw_state.cfgcr2);
12848         } else if (HAS_DDI(dev_priv)) {
12849                 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12850                               pipe_config->dpll_hw_state.wrpll,
12851                               pipe_config->dpll_hw_state.spll);
12852         } else {
12853                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12854                               "fp0: 0x%x, fp1: 0x%x\n",
12855                               pipe_config->dpll_hw_state.dpll,
12856                               pipe_config->dpll_hw_state.dpll_md,
12857                               pipe_config->dpll_hw_state.fp0,
12858                               pipe_config->dpll_hw_state.fp1);
12859         }
12860
12861         DRM_DEBUG_KMS("planes on this crtc\n");
12862         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12863                 struct drm_format_name_buf format_name;
12864                 intel_plane = to_intel_plane(plane);
12865                 if (intel_plane->pipe != crtc->pipe)
12866                         continue;
12867
12868                 state = to_intel_plane_state(plane->state);
12869                 fb = state->base.fb;
12870                 if (!fb) {
12871                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12872                                       plane->base.id, plane->name, state->scaler_id);
12873                         continue;
12874                 }
12875
12876                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
12877                               plane->base.id, plane->name,
12878                               fb->base.id, fb->width, fb->height,
12879                               drm_get_format_name(fb->pixel_format, &format_name));
12880                 if (INTEL_GEN(dev_priv) >= 9)
12881                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12882                                       state->scaler_id,
12883                                       state->base.src.x1 >> 16,
12884                                       state->base.src.y1 >> 16,
12885                                       drm_rect_width(&state->base.src) >> 16,
12886                                       drm_rect_height(&state->base.src) >> 16,
12887                                       state->base.dst.x1, state->base.dst.y1,
12888                                       drm_rect_width(&state->base.dst),
12889                                       drm_rect_height(&state->base.dst));
12890         }
12891 }
12892
12893 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12894 {
12895         struct drm_device *dev = state->dev;
12896         struct drm_connector *connector;
12897         unsigned int used_ports = 0;
12898         unsigned int used_mst_ports = 0;
12899
12900         /*
12901          * Walk the connector list instead of the encoder
12902          * list to detect the problem on ddi platforms
12903          * where there's just one encoder per digital port.
12904          */
12905         drm_for_each_connector(connector, dev) {
12906                 struct drm_connector_state *connector_state;
12907                 struct intel_encoder *encoder;
12908
12909                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12910                 if (!connector_state)
12911                         connector_state = connector->state;
12912
12913                 if (!connector_state->best_encoder)
12914                         continue;
12915
12916                 encoder = to_intel_encoder(connector_state->best_encoder);
12917
12918                 WARN_ON(!connector_state->crtc);
12919
12920                 switch (encoder->type) {
12921                         unsigned int port_mask;
12922                 case INTEL_OUTPUT_UNKNOWN:
12923                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12924                                 break;
12925                 case INTEL_OUTPUT_DP:
12926                 case INTEL_OUTPUT_HDMI:
12927                 case INTEL_OUTPUT_EDP:
12928                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12929
12930                         /* the same port mustn't appear more than once */
12931                         if (used_ports & port_mask)
12932                                 return false;
12933
12934                         used_ports |= port_mask;
12935                         break;
12936                 case INTEL_OUTPUT_DP_MST:
12937                         used_mst_ports |=
12938                                 1 << enc_to_mst(&encoder->base)->primary->port;
12939                         break;
12940                 default:
12941                         break;
12942                 }
12943         }
12944
12945         /* can't mix MST and SST/HDMI on the same port */
12946         if (used_ports & used_mst_ports)
12947                 return false;
12948
12949         return true;
12950 }
12951
12952 static void
12953 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12954 {
12955         struct drm_crtc_state tmp_state;
12956         struct intel_crtc_scaler_state scaler_state;
12957         struct intel_dpll_hw_state dpll_hw_state;
12958         struct intel_shared_dpll *shared_dpll;
12959         bool force_thru;
12960
12961         /* FIXME: before the switch to atomic started, a new pipe_config was
12962          * kzalloc'd. Code that depends on any field being zero should be
12963          * fixed, so that the crtc_state can be safely duplicated. For now,
12964          * only fields that are know to not cause problems are preserved. */
12965
12966         tmp_state = crtc_state->base;
12967         scaler_state = crtc_state->scaler_state;
12968         shared_dpll = crtc_state->shared_dpll;
12969         dpll_hw_state = crtc_state->dpll_hw_state;
12970         force_thru = crtc_state->pch_pfit.force_thru;
12971
12972         memset(crtc_state, 0, sizeof *crtc_state);
12973
12974         crtc_state->base = tmp_state;
12975         crtc_state->scaler_state = scaler_state;
12976         crtc_state->shared_dpll = shared_dpll;
12977         crtc_state->dpll_hw_state = dpll_hw_state;
12978         crtc_state->pch_pfit.force_thru = force_thru;
12979 }
12980
12981 static int
12982 intel_modeset_pipe_config(struct drm_crtc *crtc,
12983                           struct intel_crtc_state *pipe_config)
12984 {
12985         struct drm_atomic_state *state = pipe_config->base.state;
12986         struct intel_encoder *encoder;
12987         struct drm_connector *connector;
12988         struct drm_connector_state *connector_state;
12989         int base_bpp, ret = -EINVAL;
12990         int i;
12991         bool retry = true;
12992
12993         clear_intel_crtc_state(pipe_config);
12994
12995         pipe_config->cpu_transcoder =
12996                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12997
12998         /*
12999          * Sanitize sync polarity flags based on requested ones. If neither
13000          * positive or negative polarity is requested, treat this as meaning
13001          * negative polarity.
13002          */
13003         if (!(pipe_config->base.adjusted_mode.flags &
13004               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13005                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13006
13007         if (!(pipe_config->base.adjusted_mode.flags &
13008               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13009                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13010
13011         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13012                                              pipe_config);
13013         if (base_bpp < 0)
13014                 goto fail;
13015
13016         /*
13017          * Determine the real pipe dimensions. Note that stereo modes can
13018          * increase the actual pipe size due to the frame doubling and
13019          * insertion of additional space for blanks between the frame. This
13020          * is stored in the crtc timings. We use the requested mode to do this
13021          * computation to clearly distinguish it from the adjusted mode, which
13022          * can be changed by the connectors in the below retry loop.
13023          */
13024         drm_crtc_get_hv_timing(&pipe_config->base.mode,
13025                                &pipe_config->pipe_src_w,
13026                                &pipe_config->pipe_src_h);
13027
13028         for_each_connector_in_state(state, connector, connector_state, i) {
13029                 if (connector_state->crtc != crtc)
13030                         continue;
13031
13032                 encoder = to_intel_encoder(connector_state->best_encoder);
13033
13034                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13035                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13036                         goto fail;
13037                 }
13038
13039                 /*
13040                  * Determine output_types before calling the .compute_config()
13041                  * hooks so that the hooks can use this information safely.
13042                  */
13043                 pipe_config->output_types |= 1 << encoder->type;
13044         }
13045
13046 encoder_retry:
13047         /* Ensure the port clock defaults are reset when retrying. */
13048         pipe_config->port_clock = 0;
13049         pipe_config->pixel_multiplier = 1;
13050
13051         /* Fill in default crtc timings, allow encoders to overwrite them. */
13052         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13053                               CRTC_STEREO_DOUBLE);
13054
13055         /* Pass our mode to the connectors and the CRTC to give them a chance to
13056          * adjust it according to limitations or connector properties, and also
13057          * a chance to reject the mode entirely.
13058          */
13059         for_each_connector_in_state(state, connector, connector_state, i) {
13060                 if (connector_state->crtc != crtc)
13061                         continue;
13062
13063                 encoder = to_intel_encoder(connector_state->best_encoder);
13064
13065                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13066                         DRM_DEBUG_KMS("Encoder config failure\n");
13067                         goto fail;
13068                 }
13069         }
13070
13071         /* Set default port clock if not overwritten by the encoder. Needs to be
13072          * done afterwards in case the encoder adjusts the mode. */
13073         if (!pipe_config->port_clock)
13074                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13075                         * pipe_config->pixel_multiplier;
13076
13077         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13078         if (ret < 0) {
13079                 DRM_DEBUG_KMS("CRTC fixup failed\n");
13080                 goto fail;
13081         }
13082
13083         if (ret == RETRY) {
13084                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13085                         ret = -EINVAL;
13086                         goto fail;
13087                 }
13088
13089                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13090                 retry = false;
13091                 goto encoder_retry;
13092         }
13093
13094         /* Dithering seems to not pass-through bits correctly when it should, so
13095          * only enable it on 6bpc panels. */
13096         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13097         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13098                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13099
13100 fail:
13101         return ret;
13102 }
13103
13104 static void
13105 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13106 {
13107         struct drm_crtc *crtc;
13108         struct drm_crtc_state *crtc_state;
13109         int i;
13110
13111         /* Double check state. */
13112         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13113                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13114
13115                 /* Update hwmode for vblank functions */
13116                 if (crtc->state->active)
13117                         crtc->hwmode = crtc->state->adjusted_mode;
13118                 else
13119                         crtc->hwmode.crtc_clock = 0;
13120
13121                 /*
13122                  * Update legacy state to satisfy fbc code. This can
13123                  * be removed when fbc uses the atomic state.
13124                  */
13125                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13126                         struct drm_plane_state *plane_state = crtc->primary->state;
13127
13128                         crtc->primary->fb = plane_state->fb;
13129                         crtc->x = plane_state->src_x >> 16;
13130                         crtc->y = plane_state->src_y >> 16;
13131                 }
13132         }
13133 }
13134
13135 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13136 {
13137         int diff;
13138
13139         if (clock1 == clock2)
13140                 return true;
13141
13142         if (!clock1 || !clock2)
13143                 return false;
13144
13145         diff = abs(clock1 - clock2);
13146
13147         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13148                 return true;
13149
13150         return false;
13151 }
13152
13153 static bool
13154 intel_compare_m_n(unsigned int m, unsigned int n,
13155                   unsigned int m2, unsigned int n2,
13156                   bool exact)
13157 {
13158         if (m == m2 && n == n2)
13159                 return true;
13160
13161         if (exact || !m || !n || !m2 || !n2)
13162                 return false;
13163
13164         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13165
13166         if (n > n2) {
13167                 while (n > n2) {
13168                         m2 <<= 1;
13169                         n2 <<= 1;
13170                 }
13171         } else if (n < n2) {
13172                 while (n < n2) {
13173                         m <<= 1;
13174                         n <<= 1;
13175                 }
13176         }
13177
13178         if (n != n2)
13179                 return false;
13180
13181         return intel_fuzzy_clock_check(m, m2);
13182 }
13183
13184 static bool
13185 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13186                        struct intel_link_m_n *m2_n2,
13187                        bool adjust)
13188 {
13189         if (m_n->tu == m2_n2->tu &&
13190             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13191                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13192             intel_compare_m_n(m_n->link_m, m_n->link_n,
13193                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
13194                 if (adjust)
13195                         *m2_n2 = *m_n;
13196
13197                 return true;
13198         }
13199
13200         return false;
13201 }
13202
13203 static void __printf(3, 4)
13204 pipe_config_err(bool adjust, const char *name, const char *format, ...)
13205 {
13206         char *level;
13207         unsigned int category;
13208         struct va_format vaf;
13209         va_list args;
13210
13211         if (adjust) {
13212                 level = KERN_DEBUG;
13213                 category = DRM_UT_KMS;
13214         } else {
13215                 level = KERN_ERR;
13216                 category = DRM_UT_NONE;
13217         }
13218
13219         va_start(args, format);
13220         vaf.fmt = format;
13221         vaf.va = &args;
13222
13223         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
13224
13225         va_end(args);
13226 }
13227
13228 static bool
13229 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
13230                           struct intel_crtc_state *current_config,
13231                           struct intel_crtc_state *pipe_config,
13232                           bool adjust)
13233 {
13234         bool ret = true;
13235
13236 #define PIPE_CONF_CHECK_X(name) \
13237         if (current_config->name != pipe_config->name) { \
13238                 pipe_config_err(adjust, __stringify(name), \
13239                           "(expected 0x%08x, found 0x%08x)\n", \
13240                           current_config->name, \
13241                           pipe_config->name); \
13242                 ret = false; \
13243         }
13244
13245 #define PIPE_CONF_CHECK_I(name) \
13246         if (current_config->name != pipe_config->name) { \
13247                 pipe_config_err(adjust, __stringify(name), \
13248                           "(expected %i, found %i)\n", \
13249                           current_config->name, \
13250                           pipe_config->name); \
13251                 ret = false; \
13252         }
13253
13254 #define PIPE_CONF_CHECK_P(name) \
13255         if (current_config->name != pipe_config->name) { \
13256                 pipe_config_err(adjust, __stringify(name), \
13257                           "(expected %p, found %p)\n", \
13258                           current_config->name, \
13259                           pipe_config->name); \
13260                 ret = false; \
13261         }
13262
13263 #define PIPE_CONF_CHECK_M_N(name) \
13264         if (!intel_compare_link_m_n(&current_config->name, \
13265                                     &pipe_config->name,\
13266                                     adjust)) { \
13267                 pipe_config_err(adjust, __stringify(name), \
13268                           "(expected tu %i gmch %i/%i link %i/%i, " \
13269                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13270                           current_config->name.tu, \
13271                           current_config->name.gmch_m, \
13272                           current_config->name.gmch_n, \
13273                           current_config->name.link_m, \
13274                           current_config->name.link_n, \
13275                           pipe_config->name.tu, \
13276                           pipe_config->name.gmch_m, \
13277                           pipe_config->name.gmch_n, \
13278                           pipe_config->name.link_m, \
13279                           pipe_config->name.link_n); \
13280                 ret = false; \
13281         }
13282
13283 /* This is required for BDW+ where there is only one set of registers for
13284  * switching between high and low RR.
13285  * This macro can be used whenever a comparison has to be made between one
13286  * hw state and multiple sw state variables.
13287  */
13288 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13289         if (!intel_compare_link_m_n(&current_config->name, \
13290                                     &pipe_config->name, adjust) && \
13291             !intel_compare_link_m_n(&current_config->alt_name, \
13292                                     &pipe_config->name, adjust)) { \
13293                 pipe_config_err(adjust, __stringify(name), \
13294                           "(expected tu %i gmch %i/%i link %i/%i, " \
13295                           "or tu %i gmch %i/%i link %i/%i, " \
13296                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13297                           current_config->name.tu, \
13298                           current_config->name.gmch_m, \
13299                           current_config->name.gmch_n, \
13300                           current_config->name.link_m, \
13301                           current_config->name.link_n, \
13302                           current_config->alt_name.tu, \
13303                           current_config->alt_name.gmch_m, \
13304                           current_config->alt_name.gmch_n, \
13305                           current_config->alt_name.link_m, \
13306                           current_config->alt_name.link_n, \
13307                           pipe_config->name.tu, \
13308                           pipe_config->name.gmch_m, \
13309                           pipe_config->name.gmch_n, \
13310                           pipe_config->name.link_m, \
13311                           pipe_config->name.link_n); \
13312                 ret = false; \
13313         }
13314
13315 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
13316         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13317                 pipe_config_err(adjust, __stringify(name), \
13318                           "(%x) (expected %i, found %i)\n", \
13319                           (mask), \
13320                           current_config->name & (mask), \
13321                           pipe_config->name & (mask)); \
13322                 ret = false; \
13323         }
13324
13325 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13326         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13327                 pipe_config_err(adjust, __stringify(name), \
13328                           "(expected %i, found %i)\n", \
13329                           current_config->name, \
13330                           pipe_config->name); \
13331                 ret = false; \
13332         }
13333
13334 #define PIPE_CONF_QUIRK(quirk)  \
13335         ((current_config->quirks | pipe_config->quirks) & (quirk))
13336
13337         PIPE_CONF_CHECK_I(cpu_transcoder);
13338
13339         PIPE_CONF_CHECK_I(has_pch_encoder);
13340         PIPE_CONF_CHECK_I(fdi_lanes);
13341         PIPE_CONF_CHECK_M_N(fdi_m_n);
13342
13343         PIPE_CONF_CHECK_I(lane_count);
13344         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13345
13346         if (INTEL_GEN(dev_priv) < 8) {
13347                 PIPE_CONF_CHECK_M_N(dp_m_n);
13348
13349                 if (current_config->has_drrs)
13350                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13351         } else
13352                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13353
13354         PIPE_CONF_CHECK_X(output_types);
13355
13356         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13357         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13358         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13359         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13360         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13361         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13362
13363         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13364         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13365         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13366         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13367         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13368         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13369
13370         PIPE_CONF_CHECK_I(pixel_multiplier);
13371         PIPE_CONF_CHECK_I(has_hdmi_sink);
13372         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13373             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13374                 PIPE_CONF_CHECK_I(limited_color_range);
13375         PIPE_CONF_CHECK_I(has_infoframe);
13376
13377         PIPE_CONF_CHECK_I(has_audio);
13378
13379         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13380                               DRM_MODE_FLAG_INTERLACE);
13381
13382         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13383                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13384                                       DRM_MODE_FLAG_PHSYNC);
13385                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13386                                       DRM_MODE_FLAG_NHSYNC);
13387                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13388                                       DRM_MODE_FLAG_PVSYNC);
13389                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13390                                       DRM_MODE_FLAG_NVSYNC);
13391         }
13392
13393         PIPE_CONF_CHECK_X(gmch_pfit.control);
13394         /* pfit ratios are autocomputed by the hw on gen4+ */
13395         if (INTEL_GEN(dev_priv) < 4)
13396                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13397         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13398
13399         if (!adjust) {
13400                 PIPE_CONF_CHECK_I(pipe_src_w);
13401                 PIPE_CONF_CHECK_I(pipe_src_h);
13402
13403                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13404                 if (current_config->pch_pfit.enabled) {
13405                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13406                         PIPE_CONF_CHECK_X(pch_pfit.size);
13407                 }
13408
13409                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13410         }
13411
13412         /* BDW+ don't expose a synchronous way to read the state */
13413         if (IS_HASWELL(dev_priv))
13414                 PIPE_CONF_CHECK_I(ips_enabled);
13415
13416         PIPE_CONF_CHECK_I(double_wide);
13417
13418         PIPE_CONF_CHECK_P(shared_dpll);
13419         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13420         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13421         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13422         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13423         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13424         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13425         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13426         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13427         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13428
13429         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13430         PIPE_CONF_CHECK_X(dsi_pll.div);
13431
13432         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13433                 PIPE_CONF_CHECK_I(pipe_bpp);
13434
13435         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13436         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13437
13438 #undef PIPE_CONF_CHECK_X
13439 #undef PIPE_CONF_CHECK_I
13440 #undef PIPE_CONF_CHECK_P
13441 #undef PIPE_CONF_CHECK_FLAGS
13442 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13443 #undef PIPE_CONF_QUIRK
13444
13445         return ret;
13446 }
13447
13448 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13449                                            const struct intel_crtc_state *pipe_config)
13450 {
13451         if (pipe_config->has_pch_encoder) {
13452                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13453                                                             &pipe_config->fdi_m_n);
13454                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13455
13456                 /*
13457                  * FDI already provided one idea for the dotclock.
13458                  * Yell if the encoder disagrees.
13459                  */
13460                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13461                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13462                      fdi_dotclock, dotclock);
13463         }
13464 }
13465
13466 static void verify_wm_state(struct drm_crtc *crtc,
13467                             struct drm_crtc_state *new_state)
13468 {
13469         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13470         struct skl_ddb_allocation hw_ddb, *sw_ddb;
13471         struct skl_pipe_wm hw_wm, *sw_wm;
13472         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13473         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13475         const enum pipe pipe = intel_crtc->pipe;
13476         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13477
13478         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
13479                 return;
13480
13481         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
13482         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
13483
13484         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13485         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13486
13487         /* planes */
13488         for_each_universal_plane(dev_priv, pipe, plane) {
13489                 hw_plane_wm = &hw_wm.planes[plane];
13490                 sw_plane_wm = &sw_wm->planes[plane];
13491
13492                 /* Watermarks */
13493                 for (level = 0; level <= max_level; level++) {
13494                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13495                                                 &sw_plane_wm->wm[level]))
13496                                 continue;
13497
13498                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13499                                   pipe_name(pipe), plane + 1, level,
13500                                   sw_plane_wm->wm[level].plane_en,
13501                                   sw_plane_wm->wm[level].plane_res_b,
13502                                   sw_plane_wm->wm[level].plane_res_l,
13503                                   hw_plane_wm->wm[level].plane_en,
13504                                   hw_plane_wm->wm[level].plane_res_b,
13505                                   hw_plane_wm->wm[level].plane_res_l);
13506                 }
13507
13508                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13509                                          &sw_plane_wm->trans_wm)) {
13510                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13511                                   pipe_name(pipe), plane + 1,
13512                                   sw_plane_wm->trans_wm.plane_en,
13513                                   sw_plane_wm->trans_wm.plane_res_b,
13514                                   sw_plane_wm->trans_wm.plane_res_l,
13515                                   hw_plane_wm->trans_wm.plane_en,
13516                                   hw_plane_wm->trans_wm.plane_res_b,
13517                                   hw_plane_wm->trans_wm.plane_res_l);
13518                 }
13519
13520                 /* DDB */
13521                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
13522                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
13523
13524                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13525                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13526                                   pipe_name(pipe), plane + 1,
13527                                   sw_ddb_entry->start, sw_ddb_entry->end,
13528                                   hw_ddb_entry->start, hw_ddb_entry->end);
13529                 }
13530         }
13531
13532         /*
13533          * cursor
13534          * If the cursor plane isn't active, we may not have updated it's ddb
13535          * allocation. In that case since the ddb allocation will be updated
13536          * once the plane becomes visible, we can skip this check
13537          */
13538         if (intel_crtc->cursor_addr) {
13539                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
13540                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13541
13542                 /* Watermarks */
13543                 for (level = 0; level <= max_level; level++) {
13544                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13545                                                 &sw_plane_wm->wm[level]))
13546                                 continue;
13547
13548                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13549                                   pipe_name(pipe), level,
13550                                   sw_plane_wm->wm[level].plane_en,
13551                                   sw_plane_wm->wm[level].plane_res_b,
13552                                   sw_plane_wm->wm[level].plane_res_l,
13553                                   hw_plane_wm->wm[level].plane_en,
13554                                   hw_plane_wm->wm[level].plane_res_b,
13555                                   hw_plane_wm->wm[level].plane_res_l);
13556                 }
13557
13558                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13559                                          &sw_plane_wm->trans_wm)) {
13560                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13561                                   pipe_name(pipe),
13562                                   sw_plane_wm->trans_wm.plane_en,
13563                                   sw_plane_wm->trans_wm.plane_res_b,
13564                                   sw_plane_wm->trans_wm.plane_res_l,
13565                                   hw_plane_wm->trans_wm.plane_en,
13566                                   hw_plane_wm->trans_wm.plane_res_b,
13567                                   hw_plane_wm->trans_wm.plane_res_l);
13568                 }
13569
13570                 /* DDB */
13571                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13572                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13573
13574                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13575                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13576                                   pipe_name(pipe),
13577                                   sw_ddb_entry->start, sw_ddb_entry->end,
13578                                   hw_ddb_entry->start, hw_ddb_entry->end);
13579                 }
13580         }
13581 }
13582
13583 static void
13584 verify_connector_state(struct drm_device *dev,
13585                        struct drm_atomic_state *state,
13586                        struct drm_crtc *crtc)
13587 {
13588         struct drm_connector *connector;
13589         struct drm_connector_state *old_conn_state;
13590         int i;
13591
13592         for_each_connector_in_state(state, connector, old_conn_state, i) {
13593                 struct drm_encoder *encoder = connector->encoder;
13594                 struct drm_connector_state *state = connector->state;
13595
13596                 if (state->crtc != crtc)
13597                         continue;
13598
13599                 intel_connector_verify_state(to_intel_connector(connector));
13600
13601                 I915_STATE_WARN(state->best_encoder != encoder,
13602                      "connector's atomic encoder doesn't match legacy encoder\n");
13603         }
13604 }
13605
13606 static void
13607 verify_encoder_state(struct drm_device *dev)
13608 {
13609         struct intel_encoder *encoder;
13610         struct intel_connector *connector;
13611
13612         for_each_intel_encoder(dev, encoder) {
13613                 bool enabled = false;
13614                 enum pipe pipe;
13615
13616                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13617                               encoder->base.base.id,
13618                               encoder->base.name);
13619
13620                 for_each_intel_connector(dev, connector) {
13621                         if (connector->base.state->best_encoder != &encoder->base)
13622                                 continue;
13623                         enabled = true;
13624
13625                         I915_STATE_WARN(connector->base.state->crtc !=
13626                                         encoder->base.crtc,
13627                              "connector's crtc doesn't match encoder crtc\n");
13628                 }
13629
13630                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13631                      "encoder's enabled state mismatch "
13632                      "(expected %i, found %i)\n",
13633                      !!encoder->base.crtc, enabled);
13634
13635                 if (!encoder->base.crtc) {
13636                         bool active;
13637
13638                         active = encoder->get_hw_state(encoder, &pipe);
13639                         I915_STATE_WARN(active,
13640                              "encoder detached but still enabled on pipe %c.\n",
13641                              pipe_name(pipe));
13642                 }
13643         }
13644 }
13645
13646 static void
13647 verify_crtc_state(struct drm_crtc *crtc,
13648                   struct drm_crtc_state *old_crtc_state,
13649                   struct drm_crtc_state *new_crtc_state)
13650 {
13651         struct drm_device *dev = crtc->dev;
13652         struct drm_i915_private *dev_priv = to_i915(dev);
13653         struct intel_encoder *encoder;
13654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13655         struct intel_crtc_state *pipe_config, *sw_config;
13656         struct drm_atomic_state *old_state;
13657         bool active;
13658
13659         old_state = old_crtc_state->state;
13660         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13661         pipe_config = to_intel_crtc_state(old_crtc_state);
13662         memset(pipe_config, 0, sizeof(*pipe_config));
13663         pipe_config->base.crtc = crtc;
13664         pipe_config->base.state = old_state;
13665
13666         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13667
13668         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13669
13670         /* hw state is inconsistent with the pipe quirk */
13671         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13672             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13673                 active = new_crtc_state->active;
13674
13675         I915_STATE_WARN(new_crtc_state->active != active,
13676              "crtc active state doesn't match with hw state "
13677              "(expected %i, found %i)\n", new_crtc_state->active, active);
13678
13679         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13680              "transitional active state does not match atomic hw state "
13681              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13682
13683         for_each_encoder_on_crtc(dev, crtc, encoder) {
13684                 enum pipe pipe;
13685
13686                 active = encoder->get_hw_state(encoder, &pipe);
13687                 I915_STATE_WARN(active != new_crtc_state->active,
13688                         "[ENCODER:%i] active %i with crtc active %i\n",
13689                         encoder->base.base.id, active, new_crtc_state->active);
13690
13691                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13692                                 "Encoder connected to wrong pipe %c\n",
13693                                 pipe_name(pipe));
13694
13695                 if (active) {
13696                         pipe_config->output_types |= 1 << encoder->type;
13697                         encoder->get_config(encoder, pipe_config);
13698                 }
13699         }
13700
13701         if (!new_crtc_state->active)
13702                 return;
13703
13704         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13705
13706         sw_config = to_intel_crtc_state(crtc->state);
13707         if (!intel_pipe_config_compare(dev_priv, sw_config,
13708                                        pipe_config, false)) {
13709                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13710                 intel_dump_pipe_config(intel_crtc, pipe_config,
13711                                        "[hw state]");
13712                 intel_dump_pipe_config(intel_crtc, sw_config,
13713                                        "[sw state]");
13714         }
13715 }
13716
13717 static void
13718 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13719                          struct intel_shared_dpll *pll,
13720                          struct drm_crtc *crtc,
13721                          struct drm_crtc_state *new_state)
13722 {
13723         struct intel_dpll_hw_state dpll_hw_state;
13724         unsigned crtc_mask;
13725         bool active;
13726
13727         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13728
13729         DRM_DEBUG_KMS("%s\n", pll->name);
13730
13731         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13732
13733         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13734                 I915_STATE_WARN(!pll->on && pll->active_mask,
13735                      "pll in active use but not on in sw tracking\n");
13736                 I915_STATE_WARN(pll->on && !pll->active_mask,
13737                      "pll is on but not used by any active crtc\n");
13738                 I915_STATE_WARN(pll->on != active,
13739                      "pll on state mismatch (expected %i, found %i)\n",
13740                      pll->on, active);
13741         }
13742
13743         if (!crtc) {
13744                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13745                                 "more active pll users than references: %x vs %x\n",
13746                                 pll->active_mask, pll->config.crtc_mask);
13747
13748                 return;
13749         }
13750
13751         crtc_mask = 1 << drm_crtc_index(crtc);
13752
13753         if (new_state->active)
13754                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13755                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13756                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13757         else
13758                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13759                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13760                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13761
13762         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13763                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13764                         crtc_mask, pll->config.crtc_mask);
13765
13766         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13767                                           &dpll_hw_state,
13768                                           sizeof(dpll_hw_state)),
13769                         "pll hw state mismatch\n");
13770 }
13771
13772 static void
13773 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13774                          struct drm_crtc_state *old_crtc_state,
13775                          struct drm_crtc_state *new_crtc_state)
13776 {
13777         struct drm_i915_private *dev_priv = to_i915(dev);
13778         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13779         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13780
13781         if (new_state->shared_dpll)
13782                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13783
13784         if (old_state->shared_dpll &&
13785             old_state->shared_dpll != new_state->shared_dpll) {
13786                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13787                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13788
13789                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13790                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13791                                 pipe_name(drm_crtc_index(crtc)));
13792                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13793                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13794                                 pipe_name(drm_crtc_index(crtc)));
13795         }
13796 }
13797
13798 static void
13799 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13800                           struct drm_atomic_state *state,
13801                           struct drm_crtc_state *old_state,
13802                           struct drm_crtc_state *new_state)
13803 {
13804         if (!needs_modeset(new_state) &&
13805             !to_intel_crtc_state(new_state)->update_pipe)
13806                 return;
13807
13808         verify_wm_state(crtc, new_state);
13809         verify_connector_state(crtc->dev, state, crtc);
13810         verify_crtc_state(crtc, old_state, new_state);
13811         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13812 }
13813
13814 static void
13815 verify_disabled_dpll_state(struct drm_device *dev)
13816 {
13817         struct drm_i915_private *dev_priv = to_i915(dev);
13818         int i;
13819
13820         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13821                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13822 }
13823
13824 static void
13825 intel_modeset_verify_disabled(struct drm_device *dev,
13826                               struct drm_atomic_state *state)
13827 {
13828         verify_encoder_state(dev);
13829         verify_connector_state(dev, state, NULL);
13830         verify_disabled_dpll_state(dev);
13831 }
13832
13833 static void update_scanline_offset(struct intel_crtc *crtc)
13834 {
13835         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13836
13837         /*
13838          * The scanline counter increments at the leading edge of hsync.
13839          *
13840          * On most platforms it starts counting from vtotal-1 on the
13841          * first active line. That means the scanline counter value is
13842          * always one less than what we would expect. Ie. just after
13843          * start of vblank, which also occurs at start of hsync (on the
13844          * last active line), the scanline counter will read vblank_start-1.
13845          *
13846          * On gen2 the scanline counter starts counting from 1 instead
13847          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13848          * to keep the value positive), instead of adding one.
13849          *
13850          * On HSW+ the behaviour of the scanline counter depends on the output
13851          * type. For DP ports it behaves like most other platforms, but on HDMI
13852          * there's an extra 1 line difference. So we need to add two instead of
13853          * one to the value.
13854          */
13855         if (IS_GEN2(dev_priv)) {
13856                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13857                 int vtotal;
13858
13859                 vtotal = adjusted_mode->crtc_vtotal;
13860                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13861                         vtotal /= 2;
13862
13863                 crtc->scanline_offset = vtotal - 1;
13864         } else if (HAS_DDI(dev_priv) &&
13865                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13866                 crtc->scanline_offset = 2;
13867         } else
13868                 crtc->scanline_offset = 1;
13869 }
13870
13871 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13872 {
13873         struct drm_device *dev = state->dev;
13874         struct drm_i915_private *dev_priv = to_i915(dev);
13875         struct drm_crtc *crtc;
13876         struct drm_crtc_state *crtc_state;
13877         int i;
13878
13879         if (!dev_priv->display.crtc_compute_clock)
13880                 return;
13881
13882         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13883                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13884                 struct intel_shared_dpll *old_dpll =
13885                         to_intel_crtc_state(crtc->state)->shared_dpll;
13886
13887                 if (!needs_modeset(crtc_state))
13888                         continue;
13889
13890                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13891
13892                 if (!old_dpll)
13893                         continue;
13894
13895                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
13896         }
13897 }
13898
13899 /*
13900  * This implements the workaround described in the "notes" section of the mode
13901  * set sequence documentation. When going from no pipes or single pipe to
13902  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13903  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13904  */
13905 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13906 {
13907         struct drm_crtc_state *crtc_state;
13908         struct intel_crtc *intel_crtc;
13909         struct drm_crtc *crtc;
13910         struct intel_crtc_state *first_crtc_state = NULL;
13911         struct intel_crtc_state *other_crtc_state = NULL;
13912         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13913         int i;
13914
13915         /* look at all crtc's that are going to be enabled in during modeset */
13916         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13917                 intel_crtc = to_intel_crtc(crtc);
13918
13919                 if (!crtc_state->active || !needs_modeset(crtc_state))
13920                         continue;
13921
13922                 if (first_crtc_state) {
13923                         other_crtc_state = to_intel_crtc_state(crtc_state);
13924                         break;
13925                 } else {
13926                         first_crtc_state = to_intel_crtc_state(crtc_state);
13927                         first_pipe = intel_crtc->pipe;
13928                 }
13929         }
13930
13931         /* No workaround needed? */
13932         if (!first_crtc_state)
13933                 return 0;
13934
13935         /* w/a possibly needed, check how many crtc's are already enabled. */
13936         for_each_intel_crtc(state->dev, intel_crtc) {
13937                 struct intel_crtc_state *pipe_config;
13938
13939                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13940                 if (IS_ERR(pipe_config))
13941                         return PTR_ERR(pipe_config);
13942
13943                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13944
13945                 if (!pipe_config->base.active ||
13946                     needs_modeset(&pipe_config->base))
13947                         continue;
13948
13949                 /* 2 or more enabled crtcs means no need for w/a */
13950                 if (enabled_pipe != INVALID_PIPE)
13951                         return 0;
13952
13953                 enabled_pipe = intel_crtc->pipe;
13954         }
13955
13956         if (enabled_pipe != INVALID_PIPE)
13957                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13958         else if (other_crtc_state)
13959                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13960
13961         return 0;
13962 }
13963
13964 static int intel_lock_all_pipes(struct drm_atomic_state *state)
13965 {
13966         struct drm_crtc *crtc;
13967
13968         /* Add all pipes to the state */
13969         for_each_crtc(state->dev, crtc) {
13970                 struct drm_crtc_state *crtc_state;
13971
13972                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13973                 if (IS_ERR(crtc_state))
13974                         return PTR_ERR(crtc_state);
13975         }
13976
13977         return 0;
13978 }
13979
13980 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13981 {
13982         struct drm_crtc *crtc;
13983
13984         /*
13985          * Add all pipes to the state, and force
13986          * a modeset on all the active ones.
13987          */
13988         for_each_crtc(state->dev, crtc) {
13989                 struct drm_crtc_state *crtc_state;
13990                 int ret;
13991
13992                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13993                 if (IS_ERR(crtc_state))
13994                         return PTR_ERR(crtc_state);
13995
13996                 if (!crtc_state->active || needs_modeset(crtc_state))
13997                         continue;
13998
13999                 crtc_state->mode_changed = true;
14000
14001                 ret = drm_atomic_add_affected_connectors(state, crtc);
14002                 if (ret)
14003                         return ret;
14004
14005                 ret = drm_atomic_add_affected_planes(state, crtc);
14006                 if (ret)
14007                         return ret;
14008         }
14009
14010         return 0;
14011 }
14012
14013 static int intel_modeset_checks(struct drm_atomic_state *state)
14014 {
14015         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14016         struct drm_i915_private *dev_priv = to_i915(state->dev);
14017         struct drm_crtc *crtc;
14018         struct drm_crtc_state *crtc_state;
14019         int ret = 0, i;
14020
14021         if (!check_digital_port_conflicts(state)) {
14022                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
14023                 return -EINVAL;
14024         }
14025
14026         intel_state->modeset = true;
14027         intel_state->active_crtcs = dev_priv->active_crtcs;
14028
14029         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14030                 if (crtc_state->active)
14031                         intel_state->active_crtcs |= 1 << i;
14032                 else
14033                         intel_state->active_crtcs &= ~(1 << i);
14034
14035                 if (crtc_state->active != crtc->state->active)
14036                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
14037         }
14038
14039         /*
14040          * See if the config requires any additional preparation, e.g.
14041          * to adjust global state with pipes off.  We need to do this
14042          * here so we can get the modeset_pipe updated config for the new
14043          * mode set on this crtc.  For other crtcs we need to use the
14044          * adjusted_mode bits in the crtc directly.
14045          */
14046         if (dev_priv->display.modeset_calc_cdclk) {
14047                 if (!intel_state->cdclk_pll_vco)
14048                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
14049                 if (!intel_state->cdclk_pll_vco)
14050                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
14051
14052                 ret = dev_priv->display.modeset_calc_cdclk(state);
14053                 if (ret < 0)
14054                         return ret;
14055
14056                 /*
14057                  * Writes to dev_priv->atomic_cdclk_freq must protected by
14058                  * holding all the crtc locks, even if we don't end up
14059                  * touching the hardware
14060                  */
14061                 if (intel_state->cdclk != dev_priv->atomic_cdclk_freq) {
14062                         ret = intel_lock_all_pipes(state);
14063                         if (ret < 0)
14064                                 return ret;
14065                 }
14066
14067                 /* All pipes must be switched off while we change the cdclk. */
14068                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14069                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) {
14070                         ret = intel_modeset_all_pipes(state);
14071                         if (ret < 0)
14072                                 return ret;
14073                 }
14074
14075                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
14076                               intel_state->cdclk, intel_state->dev_cdclk);
14077         } else {
14078                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
14079         }
14080
14081         intel_modeset_clear_plls(state);
14082
14083         if (IS_HASWELL(dev_priv))
14084                 return haswell_mode_set_planes_workaround(state);
14085
14086         return 0;
14087 }
14088
14089 /*
14090  * Handle calculation of various watermark data at the end of the atomic check
14091  * phase.  The code here should be run after the per-crtc and per-plane 'check'
14092  * handlers to ensure that all derived state has been updated.
14093  */
14094 static int calc_watermark_data(struct drm_atomic_state *state)
14095 {
14096         struct drm_device *dev = state->dev;
14097         struct drm_i915_private *dev_priv = to_i915(dev);
14098
14099         /* Is there platform-specific watermark information to calculate? */
14100         if (dev_priv->display.compute_global_watermarks)
14101                 return dev_priv->display.compute_global_watermarks(state);
14102
14103         return 0;
14104 }
14105
14106 /**
14107  * intel_atomic_check - validate state object
14108  * @dev: drm device
14109  * @state: state to validate
14110  */
14111 static int intel_atomic_check(struct drm_device *dev,
14112                               struct drm_atomic_state *state)
14113 {
14114         struct drm_i915_private *dev_priv = to_i915(dev);
14115         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14116         struct drm_crtc *crtc;
14117         struct drm_crtc_state *crtc_state;
14118         int ret, i;
14119         bool any_ms = false;
14120
14121         ret = drm_atomic_helper_check_modeset(dev, state);
14122         if (ret)
14123                 return ret;
14124
14125         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14126                 struct intel_crtc_state *pipe_config =
14127                         to_intel_crtc_state(crtc_state);
14128
14129                 /* Catch I915_MODE_FLAG_INHERITED */
14130                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14131                         crtc_state->mode_changed = true;
14132
14133                 if (!needs_modeset(crtc_state))
14134                         continue;
14135
14136                 if (!crtc_state->enable) {
14137                         any_ms = true;
14138                         continue;
14139                 }
14140
14141                 /* FIXME: For only active_changed we shouldn't need to do any
14142                  * state recomputation at all. */
14143
14144                 ret = drm_atomic_add_affected_connectors(state, crtc);
14145                 if (ret)
14146                         return ret;
14147
14148                 ret = intel_modeset_pipe_config(crtc, pipe_config);
14149                 if (ret) {
14150                         intel_dump_pipe_config(to_intel_crtc(crtc),
14151                                                pipe_config, "[failed]");
14152                         return ret;
14153                 }
14154
14155                 if (i915.fastboot &&
14156                     intel_pipe_config_compare(dev_priv,
14157                                         to_intel_crtc_state(crtc->state),
14158                                         pipe_config, true)) {
14159                         crtc_state->mode_changed = false;
14160                         to_intel_crtc_state(crtc_state)->update_pipe = true;
14161                 }
14162
14163                 if (needs_modeset(crtc_state))
14164                         any_ms = true;
14165
14166                 ret = drm_atomic_add_affected_planes(state, crtc);
14167                 if (ret)
14168                         return ret;
14169
14170                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14171                                        needs_modeset(crtc_state) ?
14172                                        "[modeset]" : "[fastset]");
14173         }
14174
14175         if (any_ms) {
14176                 ret = intel_modeset_checks(state);
14177
14178                 if (ret)
14179                         return ret;
14180         } else {
14181                 intel_state->cdclk = dev_priv->atomic_cdclk_freq;
14182         }
14183
14184         ret = drm_atomic_helper_check_planes(dev, state);
14185         if (ret)
14186                 return ret;
14187
14188         intel_fbc_choose_crtc(dev_priv, state);
14189         return calc_watermark_data(state);
14190 }
14191
14192 static int intel_atomic_prepare_commit(struct drm_device *dev,
14193                                        struct drm_atomic_state *state)
14194 {
14195         struct drm_i915_private *dev_priv = to_i915(dev);
14196         struct drm_crtc_state *crtc_state;
14197         struct drm_crtc *crtc;
14198         int i, ret;
14199
14200         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14201                 if (state->legacy_cursor_update)
14202                         continue;
14203
14204                 ret = intel_crtc_wait_for_pending_flips(crtc);
14205                 if (ret)
14206                         return ret;
14207
14208                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14209                         flush_workqueue(dev_priv->wq);
14210         }
14211
14212         ret = mutex_lock_interruptible(&dev->struct_mutex);
14213         if (ret)
14214                 return ret;
14215
14216         ret = drm_atomic_helper_prepare_planes(dev, state);
14217         mutex_unlock(&dev->struct_mutex);
14218
14219         return ret;
14220 }
14221
14222 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14223 {
14224         struct drm_device *dev = crtc->base.dev;
14225
14226         if (!dev->max_vblank_count)
14227                 return drm_accurate_vblank_count(&crtc->base);
14228
14229         return dev->driver->get_vblank_counter(dev, crtc->pipe);
14230 }
14231
14232 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14233                                           struct drm_i915_private *dev_priv,
14234                                           unsigned crtc_mask)
14235 {
14236         unsigned last_vblank_count[I915_MAX_PIPES];
14237         enum pipe pipe;
14238         int ret;
14239
14240         if (!crtc_mask)
14241                 return;
14242
14243         for_each_pipe(dev_priv, pipe) {
14244                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14245                                                                   pipe);
14246
14247                 if (!((1 << pipe) & crtc_mask))
14248                         continue;
14249
14250                 ret = drm_crtc_vblank_get(&crtc->base);
14251                 if (WARN_ON(ret != 0)) {
14252                         crtc_mask &= ~(1 << pipe);
14253                         continue;
14254                 }
14255
14256                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
14257         }
14258
14259         for_each_pipe(dev_priv, pipe) {
14260                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14261                                                                   pipe);
14262                 long lret;
14263
14264                 if (!((1 << pipe) & crtc_mask))
14265                         continue;
14266
14267                 lret = wait_event_timeout(dev->vblank[pipe].queue,
14268                                 last_vblank_count[pipe] !=
14269                                         drm_crtc_vblank_count(&crtc->base),
14270                                 msecs_to_jiffies(50));
14271
14272                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14273
14274                 drm_crtc_vblank_put(&crtc->base);
14275         }
14276 }
14277
14278 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14279 {
14280         /* fb updated, need to unpin old fb */
14281         if (crtc_state->fb_changed)
14282                 return true;
14283
14284         /* wm changes, need vblank before final wm's */
14285         if (crtc_state->update_wm_post)
14286                 return true;
14287
14288         /*
14289          * cxsr is re-enabled after vblank.
14290          * This is already handled by crtc_state->update_wm_post,
14291          * but added for clarity.
14292          */
14293         if (crtc_state->disable_cxsr)
14294                 return true;
14295
14296         return false;
14297 }
14298
14299 static void intel_update_crtc(struct drm_crtc *crtc,
14300                               struct drm_atomic_state *state,
14301                               struct drm_crtc_state *old_crtc_state,
14302                               unsigned int *crtc_vblank_mask)
14303 {
14304         struct drm_device *dev = crtc->dev;
14305         struct drm_i915_private *dev_priv = to_i915(dev);
14306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14307         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14308         bool modeset = needs_modeset(crtc->state);
14309
14310         if (modeset) {
14311                 update_scanline_offset(intel_crtc);
14312                 dev_priv->display.crtc_enable(pipe_config, state);
14313         } else {
14314                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14315         }
14316
14317         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14318                 intel_fbc_enable(
14319                     intel_crtc, pipe_config,
14320                     to_intel_plane_state(crtc->primary->state));
14321         }
14322
14323         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14324
14325         if (needs_vblank_wait(pipe_config))
14326                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14327 }
14328
14329 static void intel_update_crtcs(struct drm_atomic_state *state,
14330                                unsigned int *crtc_vblank_mask)
14331 {
14332         struct drm_crtc *crtc;
14333         struct drm_crtc_state *old_crtc_state;
14334         int i;
14335
14336         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14337                 if (!crtc->state->active)
14338                         continue;
14339
14340                 intel_update_crtc(crtc, state, old_crtc_state,
14341                                   crtc_vblank_mask);
14342         }
14343 }
14344
14345 static void skl_update_crtcs(struct drm_atomic_state *state,
14346                              unsigned int *crtc_vblank_mask)
14347 {
14348         struct drm_i915_private *dev_priv = to_i915(state->dev);
14349         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14350         struct drm_crtc *crtc;
14351         struct intel_crtc *intel_crtc;
14352         struct drm_crtc_state *old_crtc_state;
14353         struct intel_crtc_state *cstate;
14354         unsigned int updated = 0;
14355         bool progress;
14356         enum pipe pipe;
14357         int i;
14358
14359         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
14360
14361         for_each_crtc_in_state(state, crtc, old_crtc_state, i)
14362                 /* ignore allocations for crtc's that have been turned off. */
14363                 if (crtc->state->active)
14364                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
14365
14366         /*
14367          * Whenever the number of active pipes changes, we need to make sure we
14368          * update the pipes in the right order so that their ddb allocations
14369          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14370          * cause pipe underruns and other bad stuff.
14371          */
14372         do {
14373                 progress = false;
14374
14375                 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14376                         bool vbl_wait = false;
14377                         unsigned int cmask = drm_crtc_mask(crtc);
14378
14379                         intel_crtc = to_intel_crtc(crtc);
14380                         cstate = to_intel_crtc_state(crtc->state);
14381                         pipe = intel_crtc->pipe;
14382
14383                         if (updated & cmask || !cstate->base.active)
14384                                 continue;
14385
14386                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
14387                                 continue;
14388
14389                         updated |= cmask;
14390                         entries[i] = &cstate->wm.skl.ddb;
14391
14392                         /*
14393                          * If this is an already active pipe, it's DDB changed,
14394                          * and this isn't the last pipe that needs updating
14395                          * then we need to wait for a vblank to pass for the
14396                          * new ddb allocation to take effect.
14397                          */
14398                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
14399                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
14400                             !crtc->state->active_changed &&
14401                             intel_state->wm_results.dirty_pipes != updated)
14402                                 vbl_wait = true;
14403
14404                         intel_update_crtc(crtc, state, old_crtc_state,
14405                                           crtc_vblank_mask);
14406
14407                         if (vbl_wait)
14408                                 intel_wait_for_vblank(dev_priv, pipe);
14409
14410                         progress = true;
14411                 }
14412         } while (progress);
14413 }
14414
14415 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14416 {
14417         struct drm_device *dev = state->dev;
14418         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14419         struct drm_i915_private *dev_priv = to_i915(dev);
14420         struct drm_crtc_state *old_crtc_state;
14421         struct drm_crtc *crtc;
14422         struct intel_crtc_state *intel_cstate;
14423         bool hw_check = intel_state->modeset;
14424         unsigned long put_domains[I915_MAX_PIPES] = {};
14425         unsigned crtc_vblank_mask = 0;
14426         int i;
14427
14428         drm_atomic_helper_wait_for_dependencies(state);
14429
14430         if (intel_state->modeset)
14431                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14432
14433         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14434                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14435
14436                 if (needs_modeset(crtc->state) ||
14437                     to_intel_crtc_state(crtc->state)->update_pipe) {
14438                         hw_check = true;
14439
14440                         put_domains[to_intel_crtc(crtc)->pipe] =
14441                                 modeset_get_crtc_power_domains(crtc,
14442                                         to_intel_crtc_state(crtc->state));
14443                 }
14444
14445                 if (!needs_modeset(crtc->state))
14446                         continue;
14447
14448                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14449
14450                 if (old_crtc_state->active) {
14451                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14452                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14453                         intel_crtc->active = false;
14454                         intel_fbc_disable(intel_crtc);
14455                         intel_disable_shared_dpll(intel_crtc);
14456
14457                         /*
14458                          * Underruns don't always raise
14459                          * interrupts, so check manually.
14460                          */
14461                         intel_check_cpu_fifo_underruns(dev_priv);
14462                         intel_check_pch_fifo_underruns(dev_priv);
14463
14464                         if (!crtc->state->active) {
14465                                 /*
14466                                  * Make sure we don't call initial_watermarks
14467                                  * for ILK-style watermark updates.
14468                                  */
14469                                 if (dev_priv->display.atomic_update_watermarks)
14470                                         dev_priv->display.initial_watermarks(intel_state,
14471                                                                              to_intel_crtc_state(crtc->state));
14472                                 else
14473                                         intel_update_watermarks(intel_crtc);
14474                         }
14475                 }
14476         }
14477
14478         /* Only after disabling all output pipelines that will be changed can we
14479          * update the the output configuration. */
14480         intel_modeset_update_crtc_state(state);
14481
14482         if (intel_state->modeset) {
14483                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14484
14485                 if (dev_priv->display.modeset_commit_cdclk &&
14486                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14487                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14488                         dev_priv->display.modeset_commit_cdclk(state);
14489
14490                 /*
14491                  * SKL workaround: bspec recommends we disable the SAGV when we
14492                  * have more then one pipe enabled
14493                  */
14494                 if (!intel_can_enable_sagv(state))
14495                         intel_disable_sagv(dev_priv);
14496
14497                 intel_modeset_verify_disabled(dev, state);
14498         }
14499
14500         /* Complete the events for pipes that have now been disabled */
14501         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14502                 bool modeset = needs_modeset(crtc->state);
14503
14504                 /* Complete events for now disable pipes here. */
14505                 if (modeset && !crtc->state->active && crtc->state->event) {
14506                         spin_lock_irq(&dev->event_lock);
14507                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
14508                         spin_unlock_irq(&dev->event_lock);
14509
14510                         crtc->state->event = NULL;
14511                 }
14512         }
14513
14514         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14515         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14516
14517         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14518          * already, but still need the state for the delayed optimization. To
14519          * fix this:
14520          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14521          * - schedule that vblank worker _before_ calling hw_done
14522          * - at the start of commit_tail, cancel it _synchrously
14523          * - switch over to the vblank wait helper in the core after that since
14524          *   we don't need out special handling any more.
14525          */
14526         if (!state->legacy_cursor_update)
14527                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14528
14529         /*
14530          * Now that the vblank has passed, we can go ahead and program the
14531          * optimal watermarks on platforms that need two-step watermark
14532          * programming.
14533          *
14534          * TODO: Move this (and other cleanup) to an async worker eventually.
14535          */
14536         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14537                 intel_cstate = to_intel_crtc_state(crtc->state);
14538
14539                 if (dev_priv->display.optimize_watermarks)
14540                         dev_priv->display.optimize_watermarks(intel_state,
14541                                                               intel_cstate);
14542         }
14543
14544         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14545                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14546
14547                 if (put_domains[i])
14548                         modeset_put_power_domains(dev_priv, put_domains[i]);
14549
14550                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state);
14551         }
14552
14553         if (intel_state->modeset && intel_can_enable_sagv(state))
14554                 intel_enable_sagv(dev_priv);
14555
14556         drm_atomic_helper_commit_hw_done(state);
14557
14558         if (intel_state->modeset)
14559                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14560
14561         mutex_lock(&dev->struct_mutex);
14562         drm_atomic_helper_cleanup_planes(dev, state);
14563         mutex_unlock(&dev->struct_mutex);
14564
14565         drm_atomic_helper_commit_cleanup_done(state);
14566
14567         drm_atomic_state_put(state);
14568
14569         /* As one of the primary mmio accessors, KMS has a high likelihood
14570          * of triggering bugs in unclaimed access. After we finish
14571          * modesetting, see if an error has been flagged, and if so
14572          * enable debugging for the next modeset - and hope we catch
14573          * the culprit.
14574          *
14575          * XXX note that we assume display power is on at this point.
14576          * This might hold true now but we need to add pm helper to check
14577          * unclaimed only when the hardware is on, as atomic commits
14578          * can happen also when the device is completely off.
14579          */
14580         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14581 }
14582
14583 static void intel_atomic_commit_work(struct work_struct *work)
14584 {
14585         struct drm_atomic_state *state =
14586                 container_of(work, struct drm_atomic_state, commit_work);
14587
14588         intel_atomic_commit_tail(state);
14589 }
14590
14591 static int __i915_sw_fence_call
14592 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14593                           enum i915_sw_fence_notify notify)
14594 {
14595         struct intel_atomic_state *state =
14596                 container_of(fence, struct intel_atomic_state, commit_ready);
14597
14598         switch (notify) {
14599         case FENCE_COMPLETE:
14600                 if (state->base.commit_work.func)
14601                         queue_work(system_unbound_wq, &state->base.commit_work);
14602                 break;
14603
14604         case FENCE_FREE:
14605                 drm_atomic_state_put(&state->base);
14606                 break;
14607         }
14608
14609         return NOTIFY_DONE;
14610 }
14611
14612 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14613 {
14614         struct drm_plane_state *old_plane_state;
14615         struct drm_plane *plane;
14616         int i;
14617
14618         for_each_plane_in_state(state, plane, old_plane_state, i)
14619                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14620                                   intel_fb_obj(plane->state->fb),
14621                                   to_intel_plane(plane)->frontbuffer_bit);
14622 }
14623
14624 /**
14625  * intel_atomic_commit - commit validated state object
14626  * @dev: DRM device
14627  * @state: the top-level driver state object
14628  * @nonblock: nonblocking commit
14629  *
14630  * This function commits a top-level state object that has been validated
14631  * with drm_atomic_helper_check().
14632  *
14633  * RETURNS
14634  * Zero for success or -errno.
14635  */
14636 static int intel_atomic_commit(struct drm_device *dev,
14637                                struct drm_atomic_state *state,
14638                                bool nonblock)
14639 {
14640         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14641         struct drm_i915_private *dev_priv = to_i915(dev);
14642         int ret = 0;
14643
14644         ret = drm_atomic_helper_setup_commit(state, nonblock);
14645         if (ret)
14646                 return ret;
14647
14648         drm_atomic_state_get(state);
14649         i915_sw_fence_init(&intel_state->commit_ready,
14650                            intel_atomic_commit_ready);
14651
14652         ret = intel_atomic_prepare_commit(dev, state);
14653         if (ret) {
14654                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14655                 i915_sw_fence_commit(&intel_state->commit_ready);
14656                 return ret;
14657         }
14658
14659         drm_atomic_helper_swap_state(state, true);
14660         dev_priv->wm.distrust_bios_wm = false;
14661         intel_shared_dpll_swap_state(state);
14662         intel_atomic_track_fbs(state);
14663
14664         if (intel_state->modeset) {
14665                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14666                        sizeof(intel_state->min_pixclk));
14667                 dev_priv->active_crtcs = intel_state->active_crtcs;
14668                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14669         }
14670
14671         drm_atomic_state_get(state);
14672         INIT_WORK(&state->commit_work,
14673                   nonblock ? intel_atomic_commit_work : NULL);
14674
14675         i915_sw_fence_commit(&intel_state->commit_ready);
14676         if (!nonblock) {
14677                 i915_sw_fence_wait(&intel_state->commit_ready);
14678                 intel_atomic_commit_tail(state);
14679         }
14680
14681         return 0;
14682 }
14683
14684 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14685 {
14686         struct drm_device *dev = crtc->dev;
14687         struct drm_atomic_state *state;
14688         struct drm_crtc_state *crtc_state;
14689         int ret;
14690
14691         state = drm_atomic_state_alloc(dev);
14692         if (!state) {
14693                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14694                               crtc->base.id, crtc->name);
14695                 return;
14696         }
14697
14698         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14699
14700 retry:
14701         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14702         ret = PTR_ERR_OR_ZERO(crtc_state);
14703         if (!ret) {
14704                 if (!crtc_state->active)
14705                         goto out;
14706
14707                 crtc_state->mode_changed = true;
14708                 ret = drm_atomic_commit(state);
14709         }
14710
14711         if (ret == -EDEADLK) {
14712                 drm_atomic_state_clear(state);
14713                 drm_modeset_backoff(state->acquire_ctx);
14714                 goto retry;
14715         }
14716
14717 out:
14718         drm_atomic_state_put(state);
14719 }
14720
14721 /*
14722  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14723  *        drm_atomic_helper_legacy_gamma_set() directly.
14724  */
14725 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14726                                          u16 *red, u16 *green, u16 *blue,
14727                                          uint32_t size)
14728 {
14729         struct drm_device *dev = crtc->dev;
14730         struct drm_mode_config *config = &dev->mode_config;
14731         struct drm_crtc_state *state;
14732         int ret;
14733
14734         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14735         if (ret)
14736                 return ret;
14737
14738         /*
14739          * Make sure we update the legacy properties so this works when
14740          * atomic is not enabled.
14741          */
14742
14743         state = crtc->state;
14744
14745         drm_object_property_set_value(&crtc->base,
14746                                       config->degamma_lut_property,
14747                                       (state->degamma_lut) ?
14748                                       state->degamma_lut->base.id : 0);
14749
14750         drm_object_property_set_value(&crtc->base,
14751                                       config->ctm_property,
14752                                       (state->ctm) ?
14753                                       state->ctm->base.id : 0);
14754
14755         drm_object_property_set_value(&crtc->base,
14756                                       config->gamma_lut_property,
14757                                       (state->gamma_lut) ?
14758                                       state->gamma_lut->base.id : 0);
14759
14760         return 0;
14761 }
14762
14763 static const struct drm_crtc_funcs intel_crtc_funcs = {
14764         .gamma_set = intel_atomic_legacy_gamma_set,
14765         .set_config = drm_atomic_helper_set_config,
14766         .set_property = drm_atomic_helper_crtc_set_property,
14767         .destroy = intel_crtc_destroy,
14768         .page_flip = intel_crtc_page_flip,
14769         .atomic_duplicate_state = intel_crtc_duplicate_state,
14770         .atomic_destroy_state = intel_crtc_destroy_state,
14771 };
14772
14773 /**
14774  * intel_prepare_plane_fb - Prepare fb for usage on plane
14775  * @plane: drm plane to prepare for
14776  * @fb: framebuffer to prepare for presentation
14777  *
14778  * Prepares a framebuffer for usage on a display plane.  Generally this
14779  * involves pinning the underlying object and updating the frontbuffer tracking
14780  * bits.  Some older platforms need special physical address handling for
14781  * cursor planes.
14782  *
14783  * Must be called with struct_mutex held.
14784  *
14785  * Returns 0 on success, negative error code on failure.
14786  */
14787 int
14788 intel_prepare_plane_fb(struct drm_plane *plane,
14789                        struct drm_plane_state *new_state)
14790 {
14791         struct intel_atomic_state *intel_state =
14792                 to_intel_atomic_state(new_state->state);
14793         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14794         struct drm_framebuffer *fb = new_state->fb;
14795         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14796         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14797         int ret;
14798
14799         if (!obj && !old_obj)
14800                 return 0;
14801
14802         if (old_obj) {
14803                 struct drm_crtc_state *crtc_state =
14804                         drm_atomic_get_existing_crtc_state(new_state->state,
14805                                                            plane->state->crtc);
14806
14807                 /* Big Hammer, we also need to ensure that any pending
14808                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14809                  * current scanout is retired before unpinning the old
14810                  * framebuffer. Note that we rely on userspace rendering
14811                  * into the buffer attached to the pipe they are waiting
14812                  * on. If not, userspace generates a GPU hang with IPEHR
14813                  * point to the MI_WAIT_FOR_EVENT.
14814                  *
14815                  * This should only fail upon a hung GPU, in which case we
14816                  * can safely continue.
14817                  */
14818                 if (needs_modeset(crtc_state)) {
14819                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14820                                                               old_obj->resv, NULL,
14821                                                               false, 0,
14822                                                               GFP_KERNEL);
14823                         if (ret < 0)
14824                                 return ret;
14825                 }
14826         }
14827
14828         if (new_state->fence) { /* explicit fencing */
14829                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
14830                                                     new_state->fence,
14831                                                     I915_FENCE_TIMEOUT,
14832                                                     GFP_KERNEL);
14833                 if (ret < 0)
14834                         return ret;
14835         }
14836
14837         if (!obj)
14838                 return 0;
14839
14840         if (!new_state->fence) { /* implicit fencing */
14841                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14842                                                       obj->resv, NULL,
14843                                                       false, I915_FENCE_TIMEOUT,
14844                                                       GFP_KERNEL);
14845                 if (ret < 0)
14846                         return ret;
14847
14848                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
14849         }
14850
14851         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14852             INTEL_INFO(dev_priv)->cursor_needs_physical) {
14853                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
14854                 ret = i915_gem_object_attach_phys(obj, align);
14855                 if (ret) {
14856                         DRM_DEBUG_KMS("failed to attach phys object\n");
14857                         return ret;
14858                 }
14859         } else {
14860                 struct i915_vma *vma;
14861
14862                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14863                 if (IS_ERR(vma)) {
14864                         DRM_DEBUG_KMS("failed to pin object\n");
14865                         return PTR_ERR(vma);
14866                 }
14867         }
14868
14869         return 0;
14870 }
14871
14872 /**
14873  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14874  * @plane: drm plane to clean up for
14875  * @fb: old framebuffer that was on plane
14876  *
14877  * Cleans up a framebuffer that has just been removed from a plane.
14878  *
14879  * Must be called with struct_mutex held.
14880  */
14881 void
14882 intel_cleanup_plane_fb(struct drm_plane *plane,
14883                        struct drm_plane_state *old_state)
14884 {
14885         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14886         struct intel_plane_state *old_intel_state;
14887         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14888         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14889
14890         old_intel_state = to_intel_plane_state(old_state);
14891
14892         if (!obj && !old_obj)
14893                 return;
14894
14895         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14896             !INTEL_INFO(dev_priv)->cursor_needs_physical))
14897                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14898 }
14899
14900 int
14901 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14902 {
14903         int max_scale;
14904         int crtc_clock, cdclk;
14905
14906         if (!intel_crtc || !crtc_state->base.enable)
14907                 return DRM_PLANE_HELPER_NO_SCALING;
14908
14909         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14910         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14911
14912         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14913                 return DRM_PLANE_HELPER_NO_SCALING;
14914
14915         /*
14916          * skl max scale is lower of:
14917          *    close to 3 but not 3, -1 is for that purpose
14918          *            or
14919          *    cdclk/crtc_clock
14920          */
14921         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14922
14923         return max_scale;
14924 }
14925
14926 static int
14927 intel_check_primary_plane(struct drm_plane *plane,
14928                           struct intel_crtc_state *crtc_state,
14929                           struct intel_plane_state *state)
14930 {
14931         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14932         struct drm_crtc *crtc = state->base.crtc;
14933         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14934         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14935         bool can_position = false;
14936         int ret;
14937
14938         if (INTEL_GEN(dev_priv) >= 9) {
14939                 /* use scaler when colorkey is not required */
14940                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14941                         min_scale = 1;
14942                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14943                 }
14944                 can_position = true;
14945         }
14946
14947         ret = drm_plane_helper_check_state(&state->base,
14948                                            &state->clip,
14949                                            min_scale, max_scale,
14950                                            can_position, true);
14951         if (ret)
14952                 return ret;
14953
14954         if (!state->base.fb)
14955                 return 0;
14956
14957         if (INTEL_GEN(dev_priv) >= 9) {
14958                 ret = skl_check_plane_surface(state);
14959                 if (ret)
14960                         return ret;
14961         }
14962
14963         return 0;
14964 }
14965
14966 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14967                                     struct drm_crtc_state *old_crtc_state)
14968 {
14969         struct drm_device *dev = crtc->dev;
14970         struct drm_i915_private *dev_priv = to_i915(dev);
14971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14972         struct intel_crtc_state *intel_cstate =
14973                 to_intel_crtc_state(crtc->state);
14974         struct intel_crtc_state *old_intel_cstate =
14975                 to_intel_crtc_state(old_crtc_state);
14976         struct intel_atomic_state *old_intel_state =
14977                 to_intel_atomic_state(old_crtc_state->state);
14978         bool modeset = needs_modeset(crtc->state);
14979
14980         /* Perform vblank evasion around commit operation */
14981         intel_pipe_update_start(intel_crtc);
14982
14983         if (modeset)
14984                 goto out;
14985
14986         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14987                 intel_color_set_csc(crtc->state);
14988                 intel_color_load_luts(crtc->state);
14989         }
14990
14991         if (intel_cstate->update_pipe)
14992                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
14993         else if (INTEL_GEN(dev_priv) >= 9)
14994                 skl_detach_scalers(intel_crtc);
14995
14996 out:
14997         if (dev_priv->display.atomic_update_watermarks)
14998                 dev_priv->display.atomic_update_watermarks(old_intel_state,
14999                                                            intel_cstate);
15000 }
15001
15002 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
15003                                      struct drm_crtc_state *old_crtc_state)
15004 {
15005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15006
15007         intel_pipe_update_end(intel_crtc, NULL);
15008 }
15009
15010 /**
15011  * intel_plane_destroy - destroy a plane
15012  * @plane: plane to destroy
15013  *
15014  * Common destruction function for all types of planes (primary, cursor,
15015  * sprite).
15016  */
15017 void intel_plane_destroy(struct drm_plane *plane)
15018 {
15019         drm_plane_cleanup(plane);
15020         kfree(to_intel_plane(plane));
15021 }
15022
15023 const struct drm_plane_funcs intel_plane_funcs = {
15024         .update_plane = drm_atomic_helper_update_plane,
15025         .disable_plane = drm_atomic_helper_disable_plane,
15026         .destroy = intel_plane_destroy,
15027         .set_property = drm_atomic_helper_plane_set_property,
15028         .atomic_get_property = intel_plane_atomic_get_property,
15029         .atomic_set_property = intel_plane_atomic_set_property,
15030         .atomic_duplicate_state = intel_plane_duplicate_state,
15031         .atomic_destroy_state = intel_plane_destroy_state,
15032 };
15033
15034 static struct intel_plane *
15035 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15036 {
15037         struct intel_plane *primary = NULL;
15038         struct intel_plane_state *state = NULL;
15039         const uint32_t *intel_primary_formats;
15040         unsigned int supported_rotations;
15041         unsigned int num_formats;
15042         int ret;
15043
15044         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
15045         if (!primary) {
15046                 ret = -ENOMEM;
15047                 goto fail;
15048         }
15049
15050         state = intel_create_plane_state(&primary->base);
15051         if (!state) {
15052                 ret = -ENOMEM;
15053                 goto fail;
15054         }
15055
15056         primary->base.state = &state->base;
15057
15058         primary->can_scale = false;
15059         primary->max_downscale = 1;
15060         if (INTEL_GEN(dev_priv) >= 9) {
15061                 primary->can_scale = true;
15062                 state->scaler_id = -1;
15063         }
15064         primary->pipe = pipe;
15065         /*
15066          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15067          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15068          */
15069         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15070                 primary->plane = (enum plane) !pipe;
15071         else
15072                 primary->plane = (enum plane) pipe;
15073         primary->id = PLANE_PRIMARY;
15074         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
15075         primary->check_plane = intel_check_primary_plane;
15076
15077         if (INTEL_GEN(dev_priv) >= 9) {
15078                 intel_primary_formats = skl_primary_formats;
15079                 num_formats = ARRAY_SIZE(skl_primary_formats);
15080
15081                 primary->update_plane = skylake_update_primary_plane;
15082                 primary->disable_plane = skylake_disable_primary_plane;
15083         } else if (HAS_PCH_SPLIT(dev_priv)) {
15084                 intel_primary_formats = i965_primary_formats;
15085                 num_formats = ARRAY_SIZE(i965_primary_formats);
15086
15087                 primary->update_plane = ironlake_update_primary_plane;
15088                 primary->disable_plane = i9xx_disable_primary_plane;
15089         } else if (INTEL_GEN(dev_priv) >= 4) {
15090                 intel_primary_formats = i965_primary_formats;
15091                 num_formats = ARRAY_SIZE(i965_primary_formats);
15092
15093                 primary->update_plane = i9xx_update_primary_plane;
15094                 primary->disable_plane = i9xx_disable_primary_plane;
15095         } else {
15096                 intel_primary_formats = i8xx_primary_formats;
15097                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15098
15099                 primary->update_plane = i9xx_update_primary_plane;
15100                 primary->disable_plane = i9xx_disable_primary_plane;
15101         }
15102
15103         if (INTEL_GEN(dev_priv) >= 9)
15104                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15105                                                0, &intel_plane_funcs,
15106                                                intel_primary_formats, num_formats,
15107                                                DRM_PLANE_TYPE_PRIMARY,
15108                                                "plane 1%c", pipe_name(pipe));
15109         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15110                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15111                                                0, &intel_plane_funcs,
15112                                                intel_primary_formats, num_formats,
15113                                                DRM_PLANE_TYPE_PRIMARY,
15114                                                "primary %c", pipe_name(pipe));
15115         else
15116                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15117                                                0, &intel_plane_funcs,
15118                                                intel_primary_formats, num_formats,
15119                                                DRM_PLANE_TYPE_PRIMARY,
15120                                                "plane %c", plane_name(primary->plane));
15121         if (ret)
15122                 goto fail;
15123
15124         if (INTEL_GEN(dev_priv) >= 9) {
15125                 supported_rotations =
15126                         DRM_ROTATE_0 | DRM_ROTATE_90 |
15127                         DRM_ROTATE_180 | DRM_ROTATE_270;
15128         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15129                 supported_rotations =
15130                         DRM_ROTATE_0 | DRM_ROTATE_180 |
15131                         DRM_REFLECT_X;
15132         } else if (INTEL_GEN(dev_priv) >= 4) {
15133                 supported_rotations =
15134                         DRM_ROTATE_0 | DRM_ROTATE_180;
15135         } else {
15136                 supported_rotations = DRM_ROTATE_0;
15137         }
15138
15139         if (INTEL_GEN(dev_priv) >= 4)
15140                 drm_plane_create_rotation_property(&primary->base,
15141                                                    DRM_ROTATE_0,
15142                                                    supported_rotations);
15143
15144         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
15145
15146         return primary;
15147
15148 fail:
15149         kfree(state);
15150         kfree(primary);
15151
15152         return ERR_PTR(ret);
15153 }
15154
15155 static int
15156 intel_check_cursor_plane(struct drm_plane *plane,
15157                          struct intel_crtc_state *crtc_state,
15158                          struct intel_plane_state *state)
15159 {
15160         struct drm_framebuffer *fb = state->base.fb;
15161         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15162         enum pipe pipe = to_intel_plane(plane)->pipe;
15163         unsigned stride;
15164         int ret;
15165
15166         ret = drm_plane_helper_check_state(&state->base,
15167                                            &state->clip,
15168                                            DRM_PLANE_HELPER_NO_SCALING,
15169                                            DRM_PLANE_HELPER_NO_SCALING,
15170                                            true, true);
15171         if (ret)
15172                 return ret;
15173
15174         /* if we want to turn off the cursor ignore width and height */
15175         if (!obj)
15176                 return 0;
15177
15178         /* Check for which cursor types we support */
15179         if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
15180                             state->base.crtc_h)) {
15181                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15182                           state->base.crtc_w, state->base.crtc_h);
15183                 return -EINVAL;
15184         }
15185
15186         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15187         if (obj->base.size < stride * state->base.crtc_h) {
15188                 DRM_DEBUG_KMS("buffer is too small\n");
15189                 return -ENOMEM;
15190         }
15191
15192         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
15193                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15194                 return -EINVAL;
15195         }
15196
15197         /*
15198          * There's something wrong with the cursor on CHV pipe C.
15199          * If it straddles the left edge of the screen then
15200          * moving it away from the edge or disabling it often
15201          * results in a pipe underrun, and often that can lead to
15202          * dead pipe (constant underrun reported, and it scans
15203          * out just a solid color). To recover from that, the
15204          * display power well must be turned off and on again.
15205          * Refuse the put the cursor into that compromised position.
15206          */
15207         if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
15208             state->base.visible && state->base.crtc_x < 0) {
15209                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15210                 return -EINVAL;
15211         }
15212
15213         return 0;
15214 }
15215
15216 static void
15217 intel_disable_cursor_plane(struct drm_plane *plane,
15218                            struct drm_crtc *crtc)
15219 {
15220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15221
15222         intel_crtc->cursor_addr = 0;
15223         intel_crtc_update_cursor(crtc, NULL);
15224 }
15225
15226 static void
15227 intel_update_cursor_plane(struct drm_plane *plane,
15228                           const struct intel_crtc_state *crtc_state,
15229                           const struct intel_plane_state *state)
15230 {
15231         struct drm_crtc *crtc = crtc_state->base.crtc;
15232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15233         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15234         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15235         uint32_t addr;
15236
15237         if (!obj)
15238                 addr = 0;
15239         else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
15240                 addr = i915_gem_object_ggtt_offset(obj, NULL);
15241         else
15242                 addr = obj->phys_handle->busaddr;
15243
15244         intel_crtc->cursor_addr = addr;
15245         intel_crtc_update_cursor(crtc, state);
15246 }
15247
15248 static struct intel_plane *
15249 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15250 {
15251         struct intel_plane *cursor = NULL;
15252         struct intel_plane_state *state = NULL;
15253         int ret;
15254
15255         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15256         if (!cursor) {
15257                 ret = -ENOMEM;
15258                 goto fail;
15259         }
15260
15261         state = intel_create_plane_state(&cursor->base);
15262         if (!state) {
15263                 ret = -ENOMEM;
15264                 goto fail;
15265         }
15266
15267         cursor->base.state = &state->base;
15268
15269         cursor->can_scale = false;
15270         cursor->max_downscale = 1;
15271         cursor->pipe = pipe;
15272         cursor->plane = pipe;
15273         cursor->id = PLANE_CURSOR;
15274         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15275         cursor->check_plane = intel_check_cursor_plane;
15276         cursor->update_plane = intel_update_cursor_plane;
15277         cursor->disable_plane = intel_disable_cursor_plane;
15278
15279         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15280                                        0, &intel_plane_funcs,
15281                                        intel_cursor_formats,
15282                                        ARRAY_SIZE(intel_cursor_formats),
15283                                        DRM_PLANE_TYPE_CURSOR,
15284                                        "cursor %c", pipe_name(pipe));
15285         if (ret)
15286                 goto fail;
15287
15288         if (INTEL_GEN(dev_priv) >= 4)
15289                 drm_plane_create_rotation_property(&cursor->base,
15290                                                    DRM_ROTATE_0,
15291                                                    DRM_ROTATE_0 |
15292                                                    DRM_ROTATE_180);
15293
15294         if (INTEL_GEN(dev_priv) >= 9)
15295                 state->scaler_id = -1;
15296
15297         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15298
15299         return cursor;
15300
15301 fail:
15302         kfree(state);
15303         kfree(cursor);
15304
15305         return ERR_PTR(ret);
15306 }
15307
15308 static void skl_init_scalers(struct drm_i915_private *dev_priv,
15309                              struct intel_crtc *crtc,
15310                              struct intel_crtc_state *crtc_state)
15311 {
15312         struct intel_crtc_scaler_state *scaler_state =
15313                 &crtc_state->scaler_state;
15314         int i;
15315
15316         for (i = 0; i < crtc->num_scalers; i++) {
15317                 struct intel_scaler *scaler = &scaler_state->scalers[i];
15318
15319                 scaler->in_use = 0;
15320                 scaler->mode = PS_SCALER_MODE_DYN;
15321         }
15322
15323         scaler_state->scaler_id = -1;
15324 }
15325
15326 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15327 {
15328         struct intel_crtc *intel_crtc;
15329         struct intel_crtc_state *crtc_state = NULL;
15330         struct intel_plane *primary = NULL;
15331         struct intel_plane *cursor = NULL;
15332         int sprite, ret;
15333
15334         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15335         if (!intel_crtc)
15336                 return -ENOMEM;
15337
15338         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15339         if (!crtc_state) {
15340                 ret = -ENOMEM;
15341                 goto fail;
15342         }
15343         intel_crtc->config = crtc_state;
15344         intel_crtc->base.state = &crtc_state->base;
15345         crtc_state->base.crtc = &intel_crtc->base;
15346
15347         /* initialize shared scalers */
15348         if (INTEL_GEN(dev_priv) >= 9) {
15349                 if (pipe == PIPE_C)
15350                         intel_crtc->num_scalers = 1;
15351                 else
15352                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
15353
15354                 skl_init_scalers(dev_priv, intel_crtc, crtc_state);
15355         }
15356
15357         primary = intel_primary_plane_create(dev_priv, pipe);
15358         if (IS_ERR(primary)) {
15359                 ret = PTR_ERR(primary);
15360                 goto fail;
15361         }
15362         intel_crtc->plane_ids_mask |= BIT(primary->id);
15363
15364         for_each_sprite(dev_priv, pipe, sprite) {
15365                 struct intel_plane *plane;
15366
15367                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15368                 if (IS_ERR(plane)) {
15369                         ret = PTR_ERR(plane);
15370                         goto fail;
15371                 }
15372                 intel_crtc->plane_ids_mask |= BIT(plane->id);
15373         }
15374
15375         cursor = intel_cursor_plane_create(dev_priv, pipe);
15376         if (IS_ERR(cursor)) {
15377                 ret = PTR_ERR(cursor);
15378                 goto fail;
15379         }
15380         intel_crtc->plane_ids_mask |= BIT(cursor->id);
15381
15382         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15383                                         &primary->base, &cursor->base,
15384                                         &intel_crtc_funcs,
15385                                         "pipe %c", pipe_name(pipe));
15386         if (ret)
15387                 goto fail;
15388
15389         intel_crtc->pipe = pipe;
15390         intel_crtc->plane = primary->plane;
15391
15392         intel_crtc->cursor_base = ~0;
15393         intel_crtc->cursor_cntl = ~0;
15394         intel_crtc->cursor_size = ~0;
15395
15396         intel_crtc->wm.cxsr_allowed = true;
15397
15398         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15399                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15400         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
15401         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
15402
15403         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15404
15405         intel_color_init(&intel_crtc->base);
15406
15407         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15408
15409         return 0;
15410
15411 fail:
15412         /*
15413          * drm_mode_config_cleanup() will free up any
15414          * crtcs/planes already initialized.
15415          */
15416         kfree(crtc_state);
15417         kfree(intel_crtc);
15418
15419         return ret;
15420 }
15421
15422 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15423 {
15424         struct drm_encoder *encoder = connector->base.encoder;
15425         struct drm_device *dev = connector->base.dev;
15426
15427         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15428
15429         if (!encoder || WARN_ON(!encoder->crtc))
15430                 return INVALID_PIPE;
15431
15432         return to_intel_crtc(encoder->crtc)->pipe;
15433 }
15434
15435 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15436                                 struct drm_file *file)
15437 {
15438         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15439         struct drm_crtc *drmmode_crtc;
15440         struct intel_crtc *crtc;
15441
15442         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15443         if (!drmmode_crtc)
15444                 return -ENOENT;
15445
15446         crtc = to_intel_crtc(drmmode_crtc);
15447         pipe_from_crtc_id->pipe = crtc->pipe;
15448
15449         return 0;
15450 }
15451
15452 static int intel_encoder_clones(struct intel_encoder *encoder)
15453 {
15454         struct drm_device *dev = encoder->base.dev;
15455         struct intel_encoder *source_encoder;
15456         int index_mask = 0;
15457         int entry = 0;
15458
15459         for_each_intel_encoder(dev, source_encoder) {
15460                 if (encoders_cloneable(encoder, source_encoder))
15461                         index_mask |= (1 << entry);
15462
15463                 entry++;
15464         }
15465
15466         return index_mask;
15467 }
15468
15469 static bool has_edp_a(struct drm_i915_private *dev_priv)
15470 {
15471         if (!IS_MOBILE(dev_priv))
15472                 return false;
15473
15474         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15475                 return false;
15476
15477         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15478                 return false;
15479
15480         return true;
15481 }
15482
15483 static bool intel_crt_present(struct drm_i915_private *dev_priv)
15484 {
15485         if (INTEL_GEN(dev_priv) >= 9)
15486                 return false;
15487
15488         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15489                 return false;
15490
15491         if (IS_CHERRYVIEW(dev_priv))
15492                 return false;
15493
15494         if (HAS_PCH_LPT_H(dev_priv) &&
15495             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15496                 return false;
15497
15498         /* DDI E can't be used if DDI A requires 4 lanes */
15499         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15500                 return false;
15501
15502         if (!dev_priv->vbt.int_crt_support)
15503                 return false;
15504
15505         return true;
15506 }
15507
15508 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15509 {
15510         int pps_num;
15511         int pps_idx;
15512
15513         if (HAS_DDI(dev_priv))
15514                 return;
15515         /*
15516          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15517          * everywhere where registers can be write protected.
15518          */
15519         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15520                 pps_num = 2;
15521         else
15522                 pps_num = 1;
15523
15524         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15525                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15526
15527                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15528                 I915_WRITE(PP_CONTROL(pps_idx), val);
15529         }
15530 }
15531
15532 static void intel_pps_init(struct drm_i915_private *dev_priv)
15533 {
15534         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
15535                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15536         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15537                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15538         else
15539                 dev_priv->pps_mmio_base = PPS_BASE;
15540
15541         intel_pps_unlock_regs_wa(dev_priv);
15542 }
15543
15544 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
15545 {
15546         struct intel_encoder *encoder;
15547         bool dpd_is_edp = false;
15548
15549         intel_pps_init(dev_priv);
15550
15551         /*
15552          * intel_edp_init_connector() depends on this completing first, to
15553          * prevent the registeration of both eDP and LVDS and the incorrect
15554          * sharing of the PPS.
15555          */
15556         intel_lvds_init(dev_priv);
15557
15558         if (intel_crt_present(dev_priv))
15559                 intel_crt_init(dev_priv);
15560
15561         if (IS_GEN9_LP(dev_priv)) {
15562                 /*
15563                  * FIXME: Broxton doesn't support port detection via the
15564                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15565                  * detect the ports.
15566                  */
15567                 intel_ddi_init(dev_priv, PORT_A);
15568                 intel_ddi_init(dev_priv, PORT_B);
15569                 intel_ddi_init(dev_priv, PORT_C);
15570
15571                 intel_dsi_init(dev_priv);
15572         } else if (HAS_DDI(dev_priv)) {
15573                 int found;
15574
15575                 /*
15576                  * Haswell uses DDI functions to detect digital outputs.
15577                  * On SKL pre-D0 the strap isn't connected, so we assume
15578                  * it's there.
15579                  */
15580                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15581                 /* WaIgnoreDDIAStrap: skl */
15582                 if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15583                         intel_ddi_init(dev_priv, PORT_A);
15584
15585                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15586                  * register */
15587                 found = I915_READ(SFUSE_STRAP);
15588
15589                 if (found & SFUSE_STRAP_DDIB_DETECTED)
15590                         intel_ddi_init(dev_priv, PORT_B);
15591                 if (found & SFUSE_STRAP_DDIC_DETECTED)
15592                         intel_ddi_init(dev_priv, PORT_C);
15593                 if (found & SFUSE_STRAP_DDID_DETECTED)
15594                         intel_ddi_init(dev_priv, PORT_D);
15595                 /*
15596                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15597                  */
15598                 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
15599                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15600                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15601                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15602                         intel_ddi_init(dev_priv, PORT_E);
15603
15604         } else if (HAS_PCH_SPLIT(dev_priv)) {
15605                 int found;
15606                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
15607
15608                 if (has_edp_a(dev_priv))
15609                         intel_dp_init(dev_priv, DP_A, PORT_A);
15610
15611                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15612                         /* PCH SDVOB multiplex with HDMIB */
15613                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
15614                         if (!found)
15615                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
15616                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15617                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
15618                 }
15619
15620                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15621                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
15622
15623                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15624                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
15625
15626                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15627                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
15628
15629                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15630                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
15631         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15632                 bool has_edp, has_port;
15633
15634                 /*
15635                  * The DP_DETECTED bit is the latched state of the DDC
15636                  * SDA pin at boot. However since eDP doesn't require DDC
15637                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
15638                  * eDP ports may have been muxed to an alternate function.
15639                  * Thus we can't rely on the DP_DETECTED bit alone to detect
15640                  * eDP ports. Consult the VBT as well as DP_DETECTED to
15641                  * detect eDP ports.
15642                  *
15643                  * Sadly the straps seem to be missing sometimes even for HDMI
15644                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15645                  * and VBT for the presence of the port. Additionally we can't
15646                  * trust the port type the VBT declares as we've seen at least
15647                  * HDMI ports that the VBT claim are DP or eDP.
15648                  */
15649                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
15650                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15651                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15652                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
15653                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15654                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
15655
15656                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
15657                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15658                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15659                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
15660                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15661                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
15662
15663                 if (IS_CHERRYVIEW(dev_priv)) {
15664                         /*
15665                          * eDP not supported on port D,
15666                          * so no need to worry about it
15667                          */
15668                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15669                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15670                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
15671                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15672                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
15673                 }
15674
15675                 intel_dsi_init(dev_priv);
15676         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
15677                 bool found = false;
15678
15679                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15680                         DRM_DEBUG_KMS("probing SDVOB\n");
15681                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
15682                         if (!found && IS_G4X(dev_priv)) {
15683                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15684                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
15685                         }
15686
15687                         if (!found && IS_G4X(dev_priv))
15688                                 intel_dp_init(dev_priv, DP_B, PORT_B);
15689                 }
15690
15691                 /* Before G4X SDVOC doesn't have its own detect register */
15692
15693                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15694                         DRM_DEBUG_KMS("probing SDVOC\n");
15695                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
15696                 }
15697
15698                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15699
15700                         if (IS_G4X(dev_priv)) {
15701                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15702                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
15703                         }
15704                         if (IS_G4X(dev_priv))
15705                                 intel_dp_init(dev_priv, DP_C, PORT_C);
15706                 }
15707
15708                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
15709                         intel_dp_init(dev_priv, DP_D, PORT_D);
15710         } else if (IS_GEN2(dev_priv))
15711                 intel_dvo_init(dev_priv);
15712
15713         if (SUPPORTS_TV(dev_priv))
15714                 intel_tv_init(dev_priv);
15715
15716         intel_psr_init(dev_priv);
15717
15718         for_each_intel_encoder(&dev_priv->drm, encoder) {
15719                 encoder->base.possible_crtcs = encoder->crtc_mask;
15720                 encoder->base.possible_clones =
15721                         intel_encoder_clones(encoder);
15722         }
15723
15724         intel_init_pch_refclk(dev_priv);
15725
15726         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
15727 }
15728
15729 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15730 {
15731         struct drm_device *dev = fb->dev;
15732         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15733
15734         drm_framebuffer_cleanup(fb);
15735         mutex_lock(&dev->struct_mutex);
15736         WARN_ON(!intel_fb->obj->framebuffer_references--);
15737         i915_gem_object_put(intel_fb->obj);
15738         mutex_unlock(&dev->struct_mutex);
15739         kfree(intel_fb);
15740 }
15741
15742 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15743                                                 struct drm_file *file,
15744                                                 unsigned int *handle)
15745 {
15746         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15747         struct drm_i915_gem_object *obj = intel_fb->obj;
15748
15749         if (obj->userptr.mm) {
15750                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15751                 return -EINVAL;
15752         }
15753
15754         return drm_gem_handle_create(file, &obj->base, handle);
15755 }
15756
15757 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15758                                         struct drm_file *file,
15759                                         unsigned flags, unsigned color,
15760                                         struct drm_clip_rect *clips,
15761                                         unsigned num_clips)
15762 {
15763         struct drm_device *dev = fb->dev;
15764         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15765         struct drm_i915_gem_object *obj = intel_fb->obj;
15766
15767         mutex_lock(&dev->struct_mutex);
15768         if (obj->pin_display && obj->cache_dirty)
15769                 i915_gem_clflush_object(obj, true);
15770         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15771         mutex_unlock(&dev->struct_mutex);
15772
15773         return 0;
15774 }
15775
15776 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15777         .destroy = intel_user_framebuffer_destroy,
15778         .create_handle = intel_user_framebuffer_create_handle,
15779         .dirty = intel_user_framebuffer_dirty,
15780 };
15781
15782 static
15783 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
15784                          uint64_t fb_modifier, uint32_t pixel_format)
15785 {
15786         u32 gen = INTEL_INFO(dev_priv)->gen;
15787
15788         if (gen >= 9) {
15789                 int cpp = drm_format_plane_cpp(pixel_format, 0);
15790
15791                 /* "The stride in bytes must not exceed the of the size of 8K
15792                  *  pixels and 32K bytes."
15793                  */
15794                 return min(8192 * cpp, 32768);
15795         } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
15796                    !IS_CHERRYVIEW(dev_priv)) {
15797                 return 32*1024;
15798         } else if (gen >= 4) {
15799                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15800                         return 16*1024;
15801                 else
15802                         return 32*1024;
15803         } else if (gen >= 3) {
15804                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15805                         return 8*1024;
15806                 else
15807                         return 16*1024;
15808         } else {
15809                 /* XXX DSPC is limited to 4k tiled */
15810                 return 8*1024;
15811         }
15812 }
15813
15814 static int intel_framebuffer_init(struct drm_device *dev,
15815                                   struct intel_framebuffer *intel_fb,
15816                                   struct drm_mode_fb_cmd2 *mode_cmd,
15817                                   struct drm_i915_gem_object *obj)
15818 {
15819         struct drm_i915_private *dev_priv = to_i915(dev);
15820         unsigned int tiling = i915_gem_object_get_tiling(obj);
15821         int ret;
15822         u32 pitch_limit, stride_alignment;
15823         struct drm_format_name_buf format_name;
15824
15825         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15826
15827         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15828                 /*
15829                  * If there's a fence, enforce that
15830                  * the fb modifier and tiling mode match.
15831                  */
15832                 if (tiling != I915_TILING_NONE &&
15833                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15834                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15835                         return -EINVAL;
15836                 }
15837         } else {
15838                 if (tiling == I915_TILING_X) {
15839                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15840                 } else if (tiling == I915_TILING_Y) {
15841                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15842                         return -EINVAL;
15843                 }
15844         }
15845
15846         /* Passed in modifier sanity checking. */
15847         switch (mode_cmd->modifier[0]) {
15848         case I915_FORMAT_MOD_Y_TILED:
15849         case I915_FORMAT_MOD_Yf_TILED:
15850                 if (INTEL_GEN(dev_priv) < 9) {
15851                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15852                                   mode_cmd->modifier[0]);
15853                         return -EINVAL;
15854                 }
15855         case DRM_FORMAT_MOD_NONE:
15856         case I915_FORMAT_MOD_X_TILED:
15857                 break;
15858         default:
15859                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15860                           mode_cmd->modifier[0]);
15861                 return -EINVAL;
15862         }
15863
15864         /*
15865          * gen2/3 display engine uses the fence if present,
15866          * so the tiling mode must match the fb modifier exactly.
15867          */
15868         if (INTEL_INFO(dev_priv)->gen < 4 &&
15869             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15870                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15871                 return -EINVAL;
15872         }
15873
15874         stride_alignment = intel_fb_stride_alignment(dev_priv,
15875                                                      mode_cmd->modifier[0],
15876                                                      mode_cmd->pixel_format);
15877         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15878                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15879                           mode_cmd->pitches[0], stride_alignment);
15880                 return -EINVAL;
15881         }
15882
15883         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
15884                                            mode_cmd->pixel_format);
15885         if (mode_cmd->pitches[0] > pitch_limit) {
15886                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15887                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15888                           "tiled" : "linear",
15889                           mode_cmd->pitches[0], pitch_limit);
15890                 return -EINVAL;
15891         }
15892
15893         /*
15894          * If there's a fence, enforce that
15895          * the fb pitch and fence stride match.
15896          */
15897         if (tiling != I915_TILING_NONE &&
15898             mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15899                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15900                           mode_cmd->pitches[0],
15901                           i915_gem_object_get_stride(obj));
15902                 return -EINVAL;
15903         }
15904
15905         /* Reject formats not supported by any plane early. */
15906         switch (mode_cmd->pixel_format) {
15907         case DRM_FORMAT_C8:
15908         case DRM_FORMAT_RGB565:
15909         case DRM_FORMAT_XRGB8888:
15910         case DRM_FORMAT_ARGB8888:
15911                 break;
15912         case DRM_FORMAT_XRGB1555:
15913                 if (INTEL_GEN(dev_priv) > 3) {
15914                         DRM_DEBUG("unsupported pixel format: %s\n",
15915                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15916                         return -EINVAL;
15917                 }
15918                 break;
15919         case DRM_FORMAT_ABGR8888:
15920                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
15921                     INTEL_GEN(dev_priv) < 9) {
15922                         DRM_DEBUG("unsupported pixel format: %s\n",
15923                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15924                         return -EINVAL;
15925                 }
15926                 break;
15927         case DRM_FORMAT_XBGR8888:
15928         case DRM_FORMAT_XRGB2101010:
15929         case DRM_FORMAT_XBGR2101010:
15930                 if (INTEL_GEN(dev_priv) < 4) {
15931                         DRM_DEBUG("unsupported pixel format: %s\n",
15932                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15933                         return -EINVAL;
15934                 }
15935                 break;
15936         case DRM_FORMAT_ABGR2101010:
15937                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
15938                         DRM_DEBUG("unsupported pixel format: %s\n",
15939                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15940                         return -EINVAL;
15941                 }
15942                 break;
15943         case DRM_FORMAT_YUYV:
15944         case DRM_FORMAT_UYVY:
15945         case DRM_FORMAT_YVYU:
15946         case DRM_FORMAT_VYUY:
15947                 if (INTEL_GEN(dev_priv) < 5) {
15948                         DRM_DEBUG("unsupported pixel format: %s\n",
15949                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15950                         return -EINVAL;
15951                 }
15952                 break;
15953         default:
15954                 DRM_DEBUG("unsupported pixel format: %s\n",
15955                           drm_get_format_name(mode_cmd->pixel_format, &format_name));
15956                 return -EINVAL;
15957         }
15958
15959         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15960         if (mode_cmd->offsets[0] != 0)
15961                 return -EINVAL;
15962
15963         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15964         intel_fb->obj = obj;
15965
15966         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15967         if (ret)
15968                 return ret;
15969
15970         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15971         if (ret) {
15972                 DRM_ERROR("framebuffer init failed %d\n", ret);
15973                 return ret;
15974         }
15975
15976         intel_fb->obj->framebuffer_references++;
15977
15978         return 0;
15979 }
15980
15981 static struct drm_framebuffer *
15982 intel_user_framebuffer_create(struct drm_device *dev,
15983                               struct drm_file *filp,
15984                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15985 {
15986         struct drm_framebuffer *fb;
15987         struct drm_i915_gem_object *obj;
15988         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15989
15990         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15991         if (!obj)
15992                 return ERR_PTR(-ENOENT);
15993
15994         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15995         if (IS_ERR(fb))
15996                 i915_gem_object_put(obj);
15997
15998         return fb;
15999 }
16000
16001 static void intel_atomic_state_free(struct drm_atomic_state *state)
16002 {
16003         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
16004
16005         drm_atomic_state_default_release(state);
16006
16007         i915_sw_fence_fini(&intel_state->commit_ready);
16008
16009         kfree(state);
16010 }
16011
16012 static const struct drm_mode_config_funcs intel_mode_funcs = {
16013         .fb_create = intel_user_framebuffer_create,
16014         .output_poll_changed = intel_fbdev_output_poll_changed,
16015         .atomic_check = intel_atomic_check,
16016         .atomic_commit = intel_atomic_commit,
16017         .atomic_state_alloc = intel_atomic_state_alloc,
16018         .atomic_state_clear = intel_atomic_state_clear,
16019         .atomic_state_free = intel_atomic_state_free,
16020 };
16021
16022 /**
16023  * intel_init_display_hooks - initialize the display modesetting hooks
16024  * @dev_priv: device private
16025  */
16026 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
16027 {
16028         if (INTEL_INFO(dev_priv)->gen >= 9) {
16029                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16030                 dev_priv->display.get_initial_plane_config =
16031                         skylake_get_initial_plane_config;
16032                 dev_priv->display.crtc_compute_clock =
16033                         haswell_crtc_compute_clock;
16034                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16035                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16036         } else if (HAS_DDI(dev_priv)) {
16037                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16038                 dev_priv->display.get_initial_plane_config =
16039                         ironlake_get_initial_plane_config;
16040                 dev_priv->display.crtc_compute_clock =
16041                         haswell_crtc_compute_clock;
16042                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16043                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16044         } else if (HAS_PCH_SPLIT(dev_priv)) {
16045                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
16046                 dev_priv->display.get_initial_plane_config =
16047                         ironlake_get_initial_plane_config;
16048                 dev_priv->display.crtc_compute_clock =
16049                         ironlake_crtc_compute_clock;
16050                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
16051                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
16052         } else if (IS_CHERRYVIEW(dev_priv)) {
16053                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16054                 dev_priv->display.get_initial_plane_config =
16055                         i9xx_get_initial_plane_config;
16056                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
16057                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16058                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16059         } else if (IS_VALLEYVIEW(dev_priv)) {
16060                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16061                 dev_priv->display.get_initial_plane_config =
16062                         i9xx_get_initial_plane_config;
16063                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
16064                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16065                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16066         } else if (IS_G4X(dev_priv)) {
16067                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16068                 dev_priv->display.get_initial_plane_config =
16069                         i9xx_get_initial_plane_config;
16070                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
16071                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16072                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16073         } else if (IS_PINEVIEW(dev_priv)) {
16074                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16075                 dev_priv->display.get_initial_plane_config =
16076                         i9xx_get_initial_plane_config;
16077                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
16078                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16079                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16080         } else if (!IS_GEN2(dev_priv)) {
16081                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16082                 dev_priv->display.get_initial_plane_config =
16083                         i9xx_get_initial_plane_config;
16084                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
16085                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16086                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16087         } else {
16088                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16089                 dev_priv->display.get_initial_plane_config =
16090                         i9xx_get_initial_plane_config;
16091                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16092                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16093                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16094         }
16095
16096         /* Returns the core display clock speed */
16097         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
16098                 dev_priv->display.get_display_clock_speed =
16099                         skylake_get_display_clock_speed;
16100         else if (IS_GEN9_LP(dev_priv))
16101                 dev_priv->display.get_display_clock_speed =
16102                         broxton_get_display_clock_speed;
16103         else if (IS_BROADWELL(dev_priv))
16104                 dev_priv->display.get_display_clock_speed =
16105                         broadwell_get_display_clock_speed;
16106         else if (IS_HASWELL(dev_priv))
16107                 dev_priv->display.get_display_clock_speed =
16108                         haswell_get_display_clock_speed;
16109         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16110                 dev_priv->display.get_display_clock_speed =
16111                         valleyview_get_display_clock_speed;
16112         else if (IS_GEN5(dev_priv))
16113                 dev_priv->display.get_display_clock_speed =
16114                         ilk_get_display_clock_speed;
16115         else if (IS_I945G(dev_priv) || IS_I965G(dev_priv) ||
16116                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
16117                 dev_priv->display.get_display_clock_speed =
16118                         i945_get_display_clock_speed;
16119         else if (IS_GM45(dev_priv))
16120                 dev_priv->display.get_display_clock_speed =
16121                         gm45_get_display_clock_speed;
16122         else if (IS_I965GM(dev_priv))
16123                 dev_priv->display.get_display_clock_speed =
16124                         i965gm_get_display_clock_speed;
16125         else if (IS_PINEVIEW(dev_priv))
16126                 dev_priv->display.get_display_clock_speed =
16127                         pnv_get_display_clock_speed;
16128         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
16129                 dev_priv->display.get_display_clock_speed =
16130                         g33_get_display_clock_speed;
16131         else if (IS_I915G(dev_priv))
16132                 dev_priv->display.get_display_clock_speed =
16133                         i915_get_display_clock_speed;
16134         else if (IS_I945GM(dev_priv) || IS_I845G(dev_priv))
16135                 dev_priv->display.get_display_clock_speed =
16136                         i9xx_misc_get_display_clock_speed;
16137         else if (IS_I915GM(dev_priv))
16138                 dev_priv->display.get_display_clock_speed =
16139                         i915gm_get_display_clock_speed;
16140         else if (IS_I865G(dev_priv))
16141                 dev_priv->display.get_display_clock_speed =
16142                         i865_get_display_clock_speed;
16143         else if (IS_I85X(dev_priv))
16144                 dev_priv->display.get_display_clock_speed =
16145                         i85x_get_display_clock_speed;
16146         else { /* 830 */
16147                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
16148                 dev_priv->display.get_display_clock_speed =
16149                         i830_get_display_clock_speed;
16150         }
16151
16152         if (IS_GEN5(dev_priv)) {
16153                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16154         } else if (IS_GEN6(dev_priv)) {
16155                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16156         } else if (IS_IVYBRIDGE(dev_priv)) {
16157                 /* FIXME: detect B0+ stepping and use auto training */
16158                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16159         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16160                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16161         }
16162
16163         if (IS_BROADWELL(dev_priv)) {
16164                 dev_priv->display.modeset_commit_cdclk =
16165                         broadwell_modeset_commit_cdclk;
16166                 dev_priv->display.modeset_calc_cdclk =
16167                         broadwell_modeset_calc_cdclk;
16168         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16169                 dev_priv->display.modeset_commit_cdclk =
16170                         valleyview_modeset_commit_cdclk;
16171                 dev_priv->display.modeset_calc_cdclk =
16172                         valleyview_modeset_calc_cdclk;
16173         } else if (IS_GEN9_LP(dev_priv)) {
16174                 dev_priv->display.modeset_commit_cdclk =
16175                         bxt_modeset_commit_cdclk;
16176                 dev_priv->display.modeset_calc_cdclk =
16177                         bxt_modeset_calc_cdclk;
16178         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16179                 dev_priv->display.modeset_commit_cdclk =
16180                         skl_modeset_commit_cdclk;
16181                 dev_priv->display.modeset_calc_cdclk =
16182                         skl_modeset_calc_cdclk;
16183         }
16184
16185         if (dev_priv->info.gen >= 9)
16186                 dev_priv->display.update_crtcs = skl_update_crtcs;
16187         else
16188                 dev_priv->display.update_crtcs = intel_update_crtcs;
16189
16190         switch (INTEL_INFO(dev_priv)->gen) {
16191         case 2:
16192                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16193                 break;
16194
16195         case 3:
16196                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16197                 break;
16198
16199         case 4:
16200         case 5:
16201                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16202                 break;
16203
16204         case 6:
16205                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16206                 break;
16207         case 7:
16208         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16209                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16210                 break;
16211         case 9:
16212                 /* Drop through - unsupported since execlist only. */
16213         default:
16214                 /* Default just returns -ENODEV to indicate unsupported */
16215                 dev_priv->display.queue_flip = intel_default_queue_flip;
16216         }
16217 }
16218
16219 /*
16220  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16221  * resume, or other times.  This quirk makes sure that's the case for
16222  * affected systems.
16223  */
16224 static void quirk_pipea_force(struct drm_device *dev)
16225 {
16226         struct drm_i915_private *dev_priv = to_i915(dev);
16227
16228         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16229         DRM_INFO("applying pipe a force quirk\n");
16230 }
16231
16232 static void quirk_pipeb_force(struct drm_device *dev)
16233 {
16234         struct drm_i915_private *dev_priv = to_i915(dev);
16235
16236         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16237         DRM_INFO("applying pipe b force quirk\n");
16238 }
16239
16240 /*
16241  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16242  */
16243 static void quirk_ssc_force_disable(struct drm_device *dev)
16244 {
16245         struct drm_i915_private *dev_priv = to_i915(dev);
16246         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16247         DRM_INFO("applying lvds SSC disable quirk\n");
16248 }
16249
16250 /*
16251  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16252  * brightness value
16253  */
16254 static void quirk_invert_brightness(struct drm_device *dev)
16255 {
16256         struct drm_i915_private *dev_priv = to_i915(dev);
16257         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16258         DRM_INFO("applying inverted panel brightness quirk\n");
16259 }
16260
16261 /* Some VBT's incorrectly indicate no backlight is present */
16262 static void quirk_backlight_present(struct drm_device *dev)
16263 {
16264         struct drm_i915_private *dev_priv = to_i915(dev);
16265         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16266         DRM_INFO("applying backlight present quirk\n");
16267 }
16268
16269 struct intel_quirk {
16270         int device;
16271         int subsystem_vendor;
16272         int subsystem_device;
16273         void (*hook)(struct drm_device *dev);
16274 };
16275
16276 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16277 struct intel_dmi_quirk {
16278         void (*hook)(struct drm_device *dev);
16279         const struct dmi_system_id (*dmi_id_list)[];
16280 };
16281
16282 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16283 {
16284         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16285         return 1;
16286 }
16287
16288 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16289         {
16290                 .dmi_id_list = &(const struct dmi_system_id[]) {
16291                         {
16292                                 .callback = intel_dmi_reverse_brightness,
16293                                 .ident = "NCR Corporation",
16294                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16295                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
16296                                 },
16297                         },
16298                         { }  /* terminating entry */
16299                 },
16300                 .hook = quirk_invert_brightness,
16301         },
16302 };
16303
16304 static struct intel_quirk intel_quirks[] = {
16305         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16306         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16307
16308         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16309         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16310
16311         /* 830 needs to leave pipe A & dpll A up */
16312         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16313
16314         /* 830 needs to leave pipe B & dpll B up */
16315         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16316
16317         /* Lenovo U160 cannot use SSC on LVDS */
16318         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16319
16320         /* Sony Vaio Y cannot use SSC on LVDS */
16321         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16322
16323         /* Acer Aspire 5734Z must invert backlight brightness */
16324         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16325
16326         /* Acer/eMachines G725 */
16327         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16328
16329         /* Acer/eMachines e725 */
16330         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16331
16332         /* Acer/Packard Bell NCL20 */
16333         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16334
16335         /* Acer Aspire 4736Z */
16336         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16337
16338         /* Acer Aspire 5336 */
16339         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16340
16341         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16342         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16343
16344         /* Acer C720 Chromebook (Core i3 4005U) */
16345         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16346
16347         /* Apple Macbook 2,1 (Core 2 T7400) */
16348         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16349
16350         /* Apple Macbook 4,1 */
16351         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16352
16353         /* Toshiba CB35 Chromebook (Celeron 2955U) */
16354         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16355
16356         /* HP Chromebook 14 (Celeron 2955U) */
16357         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16358
16359         /* Dell Chromebook 11 */
16360         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16361
16362         /* Dell Chromebook 11 (2015 version) */
16363         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16364 };
16365
16366 static void intel_init_quirks(struct drm_device *dev)
16367 {
16368         struct pci_dev *d = dev->pdev;
16369         int i;
16370
16371         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16372                 struct intel_quirk *q = &intel_quirks[i];
16373
16374                 if (d->device == q->device &&
16375                     (d->subsystem_vendor == q->subsystem_vendor ||
16376                      q->subsystem_vendor == PCI_ANY_ID) &&
16377                     (d->subsystem_device == q->subsystem_device ||
16378                      q->subsystem_device == PCI_ANY_ID))
16379                         q->hook(dev);
16380         }
16381         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16382                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16383                         intel_dmi_quirks[i].hook(dev);
16384         }
16385 }
16386
16387 /* Disable the VGA plane that we never use */
16388 static void i915_disable_vga(struct drm_i915_private *dev_priv)
16389 {
16390         struct pci_dev *pdev = dev_priv->drm.pdev;
16391         u8 sr1;
16392         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16393
16394         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16395         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16396         outb(SR01, VGA_SR_INDEX);
16397         sr1 = inb(VGA_SR_DATA);
16398         outb(sr1 | 1<<5, VGA_SR_DATA);
16399         vga_put(pdev, VGA_RSRC_LEGACY_IO);
16400         udelay(300);
16401
16402         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16403         POSTING_READ(vga_reg);
16404 }
16405
16406 void intel_modeset_init_hw(struct drm_device *dev)
16407 {
16408         struct drm_i915_private *dev_priv = to_i915(dev);
16409
16410         intel_update_cdclk(dev_priv);
16411
16412         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16413
16414         intel_init_clock_gating(dev_priv);
16415 }
16416
16417 /*
16418  * Calculate what we think the watermarks should be for the state we've read
16419  * out of the hardware and then immediately program those watermarks so that
16420  * we ensure the hardware settings match our internal state.
16421  *
16422  * We can calculate what we think WM's should be by creating a duplicate of the
16423  * current state (which was constructed during hardware readout) and running it
16424  * through the atomic check code to calculate new watermark values in the
16425  * state object.
16426  */
16427 static void sanitize_watermarks(struct drm_device *dev)
16428 {
16429         struct drm_i915_private *dev_priv = to_i915(dev);
16430         struct drm_atomic_state *state;
16431         struct intel_atomic_state *intel_state;
16432         struct drm_crtc *crtc;
16433         struct drm_crtc_state *cstate;
16434         struct drm_modeset_acquire_ctx ctx;
16435         int ret;
16436         int i;
16437
16438         /* Only supported on platforms that use atomic watermark design */
16439         if (!dev_priv->display.optimize_watermarks)
16440                 return;
16441
16442         /*
16443          * We need to hold connection_mutex before calling duplicate_state so
16444          * that the connector loop is protected.
16445          */
16446         drm_modeset_acquire_init(&ctx, 0);
16447 retry:
16448         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16449         if (ret == -EDEADLK) {
16450                 drm_modeset_backoff(&ctx);
16451                 goto retry;
16452         } else if (WARN_ON(ret)) {
16453                 goto fail;
16454         }
16455
16456         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16457         if (WARN_ON(IS_ERR(state)))
16458                 goto fail;
16459
16460         intel_state = to_intel_atomic_state(state);
16461
16462         /*
16463          * Hardware readout is the only time we don't want to calculate
16464          * intermediate watermarks (since we don't trust the current
16465          * watermarks).
16466          */
16467         intel_state->skip_intermediate_wm = true;
16468
16469         ret = intel_atomic_check(dev, state);
16470         if (ret) {
16471                 /*
16472                  * If we fail here, it means that the hardware appears to be
16473                  * programmed in a way that shouldn't be possible, given our
16474                  * understanding of watermark requirements.  This might mean a
16475                  * mistake in the hardware readout code or a mistake in the
16476                  * watermark calculations for a given platform.  Raise a WARN
16477                  * so that this is noticeable.
16478                  *
16479                  * If this actually happens, we'll have to just leave the
16480                  * BIOS-programmed watermarks untouched and hope for the best.
16481                  */
16482                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16483                 goto put_state;
16484         }
16485
16486         /* Write calculated watermark values back */
16487         for_each_crtc_in_state(state, crtc, cstate, i) {
16488                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16489
16490                 cs->wm.need_postvbl_update = true;
16491                 dev_priv->display.optimize_watermarks(intel_state, cs);
16492         }
16493
16494 put_state:
16495         drm_atomic_state_put(state);
16496 fail:
16497         drm_modeset_drop_locks(&ctx);
16498         drm_modeset_acquire_fini(&ctx);
16499 }
16500
16501 int intel_modeset_init(struct drm_device *dev)
16502 {
16503         struct drm_i915_private *dev_priv = to_i915(dev);
16504         struct i915_ggtt *ggtt = &dev_priv->ggtt;
16505         enum pipe pipe;
16506         struct intel_crtc *crtc;
16507
16508         drm_mode_config_init(dev);
16509
16510         dev->mode_config.min_width = 0;
16511         dev->mode_config.min_height = 0;
16512
16513         dev->mode_config.preferred_depth = 24;
16514         dev->mode_config.prefer_shadow = 1;
16515
16516         dev->mode_config.allow_fb_modifiers = true;
16517
16518         dev->mode_config.funcs = &intel_mode_funcs;
16519
16520         intel_init_quirks(dev);
16521
16522         intel_init_pm(dev_priv);
16523
16524         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16525                 return 0;
16526
16527         /*
16528          * There may be no VBT; and if the BIOS enabled SSC we can
16529          * just keep using it to avoid unnecessary flicker.  Whereas if the
16530          * BIOS isn't using it, don't assume it will work even if the VBT
16531          * indicates as much.
16532          */
16533         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
16534                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16535                                             DREF_SSC1_ENABLE);
16536
16537                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16538                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16539                                      bios_lvds_use_ssc ? "en" : "dis",
16540                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16541                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16542                 }
16543         }
16544
16545         if (IS_GEN2(dev_priv)) {
16546                 dev->mode_config.max_width = 2048;
16547                 dev->mode_config.max_height = 2048;
16548         } else if (IS_GEN3(dev_priv)) {
16549                 dev->mode_config.max_width = 4096;
16550                 dev->mode_config.max_height = 4096;
16551         } else {
16552                 dev->mode_config.max_width = 8192;
16553                 dev->mode_config.max_height = 8192;
16554         }
16555
16556         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16557                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
16558                 dev->mode_config.cursor_height = 1023;
16559         } else if (IS_GEN2(dev_priv)) {
16560                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16561                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16562         } else {
16563                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16564                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16565         }
16566
16567         dev->mode_config.fb_base = ggtt->mappable_base;
16568
16569         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16570                       INTEL_INFO(dev_priv)->num_pipes,
16571                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
16572
16573         for_each_pipe(dev_priv, pipe) {
16574                 int ret;
16575
16576                 ret = intel_crtc_init(dev_priv, pipe);
16577                 if (ret) {
16578                         drm_mode_config_cleanup(dev);
16579                         return ret;
16580                 }
16581         }
16582
16583         intel_update_czclk(dev_priv);
16584         intel_update_cdclk(dev_priv);
16585         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16586
16587         intel_shared_dpll_init(dev);
16588
16589         if (dev_priv->max_cdclk_freq == 0)
16590                 intel_update_max_cdclk(dev_priv);
16591
16592         /* Just disable it once at startup */
16593         i915_disable_vga(dev_priv);
16594         intel_setup_outputs(dev_priv);
16595
16596         drm_modeset_lock_all(dev);
16597         intel_modeset_setup_hw_state(dev);
16598         drm_modeset_unlock_all(dev);
16599
16600         for_each_intel_crtc(dev, crtc) {
16601                 struct intel_initial_plane_config plane_config = {};
16602
16603                 if (!crtc->active)
16604                         continue;
16605
16606                 /*
16607                  * Note that reserving the BIOS fb up front prevents us
16608                  * from stuffing other stolen allocations like the ring
16609                  * on top.  This prevents some ugliness at boot time, and
16610                  * can even allow for smooth boot transitions if the BIOS
16611                  * fb is large enough for the active pipe configuration.
16612                  */
16613                 dev_priv->display.get_initial_plane_config(crtc,
16614                                                            &plane_config);
16615
16616                 /*
16617                  * If the fb is shared between multiple heads, we'll
16618                  * just get the first one.
16619                  */
16620                 intel_find_initial_plane_obj(crtc, &plane_config);
16621         }
16622
16623         /*
16624          * Make sure hardware watermarks really match the state we read out.
16625          * Note that we need to do this after reconstructing the BIOS fb's
16626          * since the watermark calculation done here will use pstate->fb.
16627          */
16628         sanitize_watermarks(dev);
16629
16630         return 0;
16631 }
16632
16633 static void intel_enable_pipe_a(struct drm_device *dev)
16634 {
16635         struct intel_connector *connector;
16636         struct drm_connector *crt = NULL;
16637         struct intel_load_detect_pipe load_detect_temp;
16638         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16639
16640         /* We can't just switch on the pipe A, we need to set things up with a
16641          * proper mode and output configuration. As a gross hack, enable pipe A
16642          * by enabling the load detect pipe once. */
16643         for_each_intel_connector(dev, connector) {
16644                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16645                         crt = &connector->base;
16646                         break;
16647                 }
16648         }
16649
16650         if (!crt)
16651                 return;
16652
16653         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16654                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16655 }
16656
16657 static bool
16658 intel_check_plane_mapping(struct intel_crtc *crtc)
16659 {
16660         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
16661         u32 val;
16662
16663         if (INTEL_INFO(dev_priv)->num_pipes == 1)
16664                 return true;
16665
16666         val = I915_READ(DSPCNTR(!crtc->plane));
16667
16668         if ((val & DISPLAY_PLANE_ENABLE) &&
16669             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16670                 return false;
16671
16672         return true;
16673 }
16674
16675 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16676 {
16677         struct drm_device *dev = crtc->base.dev;
16678         struct intel_encoder *encoder;
16679
16680         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16681                 return true;
16682
16683         return false;
16684 }
16685
16686 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16687 {
16688         struct drm_device *dev = encoder->base.dev;
16689         struct intel_connector *connector;
16690
16691         for_each_connector_on_encoder(dev, &encoder->base, connector)
16692                 return connector;
16693
16694         return NULL;
16695 }
16696
16697 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16698                               enum transcoder pch_transcoder)
16699 {
16700         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16701                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16702 }
16703
16704 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16705 {
16706         struct drm_device *dev = crtc->base.dev;
16707         struct drm_i915_private *dev_priv = to_i915(dev);
16708         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16709
16710         /* Clear any frame start delays used for debugging left by the BIOS */
16711         if (!transcoder_is_dsi(cpu_transcoder)) {
16712                 i915_reg_t reg = PIPECONF(cpu_transcoder);
16713
16714                 I915_WRITE(reg,
16715                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16716         }
16717
16718         /* restore vblank interrupts to correct state */
16719         drm_crtc_vblank_reset(&crtc->base);
16720         if (crtc->active) {
16721                 struct intel_plane *plane;
16722
16723                 drm_crtc_vblank_on(&crtc->base);
16724
16725                 /* Disable everything but the primary plane */
16726                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16727                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16728                                 continue;
16729
16730                         plane->disable_plane(&plane->base, &crtc->base);
16731                 }
16732         }
16733
16734         /* We need to sanitize the plane -> pipe mapping first because this will
16735          * disable the crtc (and hence change the state) if it is wrong. Note
16736          * that gen4+ has a fixed plane -> pipe mapping.  */
16737         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
16738                 bool plane;
16739
16740                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16741                               crtc->base.base.id, crtc->base.name);
16742
16743                 /* Pipe has the wrong plane attached and the plane is active.
16744                  * Temporarily change the plane mapping and disable everything
16745                  * ...  */
16746                 plane = crtc->plane;
16747                 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16748                 crtc->plane = !plane;
16749                 intel_crtc_disable_noatomic(&crtc->base);
16750                 crtc->plane = plane;
16751         }
16752
16753         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16754             crtc->pipe == PIPE_A && !crtc->active) {
16755                 /* BIOS forgot to enable pipe A, this mostly happens after
16756                  * resume. Force-enable the pipe to fix this, the update_dpms
16757                  * call below we restore the pipe to the right state, but leave
16758                  * the required bits on. */
16759                 intel_enable_pipe_a(dev);
16760         }
16761
16762         /* Adjust the state of the output pipe according to whether we
16763          * have active connectors/encoders. */
16764         if (crtc->active && !intel_crtc_has_encoders(crtc))
16765                 intel_crtc_disable_noatomic(&crtc->base);
16766
16767         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
16768                 /*
16769                  * We start out with underrun reporting disabled to avoid races.
16770                  * For correct bookkeeping mark this on active crtcs.
16771                  *
16772                  * Also on gmch platforms we dont have any hardware bits to
16773                  * disable the underrun reporting. Which means we need to start
16774                  * out with underrun reporting disabled also on inactive pipes,
16775                  * since otherwise we'll complain about the garbage we read when
16776                  * e.g. coming up after runtime pm.
16777                  *
16778                  * No protection against concurrent access is required - at
16779                  * worst a fifo underrun happens which also sets this to false.
16780                  */
16781                 crtc->cpu_fifo_underrun_disabled = true;
16782                 /*
16783                  * We track the PCH trancoder underrun reporting state
16784                  * within the crtc. With crtc for pipe A housing the underrun
16785                  * reporting state for PCH transcoder A, crtc for pipe B housing
16786                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16787                  * and marking underrun reporting as disabled for the non-existing
16788                  * PCH transcoders B and C would prevent enabling the south
16789                  * error interrupt (see cpt_can_enable_serr_int()).
16790                  */
16791                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16792                         crtc->pch_fifo_underrun_disabled = true;
16793         }
16794 }
16795
16796 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16797 {
16798         struct intel_connector *connector;
16799
16800         /* We need to check both for a crtc link (meaning that the
16801          * encoder is active and trying to read from a pipe) and the
16802          * pipe itself being active. */
16803         bool has_active_crtc = encoder->base.crtc &&
16804                 to_intel_crtc(encoder->base.crtc)->active;
16805
16806         connector = intel_encoder_find_connector(encoder);
16807         if (connector && !has_active_crtc) {
16808                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16809                               encoder->base.base.id,
16810                               encoder->base.name);
16811
16812                 /* Connector is active, but has no active pipe. This is
16813                  * fallout from our resume register restoring. Disable
16814                  * the encoder manually again. */
16815                 if (encoder->base.crtc) {
16816                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16817
16818                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16819                                       encoder->base.base.id,
16820                                       encoder->base.name);
16821                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16822                         if (encoder->post_disable)
16823                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16824                 }
16825                 encoder->base.crtc = NULL;
16826
16827                 /* Inconsistent output/port/pipe state happens presumably due to
16828                  * a bug in one of the get_hw_state functions. Or someplace else
16829                  * in our code, like the register restore mess on resume. Clamp
16830                  * things to off as a safer default. */
16831
16832                 connector->base.dpms = DRM_MODE_DPMS_OFF;
16833                 connector->base.encoder = NULL;
16834         }
16835         /* Enabled encoders without active connectors will be fixed in
16836          * the crtc fixup. */
16837 }
16838
16839 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
16840 {
16841         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16842
16843         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16844                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16845                 i915_disable_vga(dev_priv);
16846         }
16847 }
16848
16849 void i915_redisable_vga(struct drm_i915_private *dev_priv)
16850 {
16851         /* This function can be called both from intel_modeset_setup_hw_state or
16852          * at a very early point in our resume sequence, where the power well
16853          * structures are not yet restored. Since this function is at a very
16854          * paranoid "someone might have enabled VGA while we were not looking"
16855          * level, just check if the power well is enabled instead of trying to
16856          * follow the "don't touch the power well if we don't need it" policy
16857          * the rest of the driver uses. */
16858         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16859                 return;
16860
16861         i915_redisable_vga_power_on(dev_priv);
16862
16863         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16864 }
16865
16866 static bool primary_get_hw_state(struct intel_plane *plane)
16867 {
16868         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16869
16870         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16871 }
16872
16873 /* FIXME read out full plane state for all planes */
16874 static void readout_plane_state(struct intel_crtc *crtc)
16875 {
16876         struct drm_plane *primary = crtc->base.primary;
16877         struct intel_plane_state *plane_state =
16878                 to_intel_plane_state(primary->state);
16879
16880         plane_state->base.visible = crtc->active &&
16881                 primary_get_hw_state(to_intel_plane(primary));
16882
16883         if (plane_state->base.visible)
16884                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16885 }
16886
16887 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16888 {
16889         struct drm_i915_private *dev_priv = to_i915(dev);
16890         enum pipe pipe;
16891         struct intel_crtc *crtc;
16892         struct intel_encoder *encoder;
16893         struct intel_connector *connector;
16894         int i;
16895
16896         dev_priv->active_crtcs = 0;
16897
16898         for_each_intel_crtc(dev, crtc) {
16899                 struct intel_crtc_state *crtc_state = crtc->config;
16900
16901                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16902                 memset(crtc_state, 0, sizeof(*crtc_state));
16903                 crtc_state->base.crtc = &crtc->base;
16904
16905                 crtc_state->base.active = crtc_state->base.enable =
16906                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16907
16908                 crtc->base.enabled = crtc_state->base.enable;
16909                 crtc->active = crtc_state->base.active;
16910
16911                 if (crtc_state->base.active)
16912                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16913
16914                 readout_plane_state(crtc);
16915
16916                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16917                               crtc->base.base.id, crtc->base.name,
16918                               enableddisabled(crtc->active));
16919         }
16920
16921         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16922                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16923
16924                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16925                                                   &pll->config.hw_state);
16926                 pll->config.crtc_mask = 0;
16927                 for_each_intel_crtc(dev, crtc) {
16928                         if (crtc->active && crtc->config->shared_dpll == pll)
16929                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16930                 }
16931                 pll->active_mask = pll->config.crtc_mask;
16932
16933                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16934                               pll->name, pll->config.crtc_mask, pll->on);
16935         }
16936
16937         for_each_intel_encoder(dev, encoder) {
16938                 pipe = 0;
16939
16940                 if (encoder->get_hw_state(encoder, &pipe)) {
16941                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16942
16943                         encoder->base.crtc = &crtc->base;
16944                         crtc->config->output_types |= 1 << encoder->type;
16945                         encoder->get_config(encoder, crtc->config);
16946                 } else {
16947                         encoder->base.crtc = NULL;
16948                 }
16949
16950                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16951                               encoder->base.base.id, encoder->base.name,
16952                               enableddisabled(encoder->base.crtc),
16953                               pipe_name(pipe));
16954         }
16955
16956         for_each_intel_connector(dev, connector) {
16957                 if (connector->get_hw_state(connector)) {
16958                         connector->base.dpms = DRM_MODE_DPMS_ON;
16959
16960                         encoder = connector->encoder;
16961                         connector->base.encoder = &encoder->base;
16962
16963                         if (encoder->base.crtc &&
16964                             encoder->base.crtc->state->active) {
16965                                 /*
16966                                  * This has to be done during hardware readout
16967                                  * because anything calling .crtc_disable may
16968                                  * rely on the connector_mask being accurate.
16969                                  */
16970                                 encoder->base.crtc->state->connector_mask |=
16971                                         1 << drm_connector_index(&connector->base);
16972                                 encoder->base.crtc->state->encoder_mask |=
16973                                         1 << drm_encoder_index(&encoder->base);
16974                         }
16975
16976                 } else {
16977                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16978                         connector->base.encoder = NULL;
16979                 }
16980                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16981                               connector->base.base.id, connector->base.name,
16982                               enableddisabled(connector->base.encoder));
16983         }
16984
16985         for_each_intel_crtc(dev, crtc) {
16986                 int pixclk = 0;
16987
16988                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16989
16990                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16991                 if (crtc->base.state->active) {
16992                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16993                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16994                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16995
16996                         /*
16997                          * The initial mode needs to be set in order to keep
16998                          * the atomic core happy. It wants a valid mode if the
16999                          * crtc's enabled, so we do the above call.
17000                          *
17001                          * At this point some state updated by the connectors
17002                          * in their ->detect() callback has not run yet, so
17003                          * no recalculation can be done yet.
17004                          *
17005                          * Even if we could do a recalculation and modeset
17006                          * right now it would cause a double modeset if
17007                          * fbdev or userspace chooses a different initial mode.
17008                          *
17009                          * If that happens, someone indicated they wanted a
17010                          * mode change, which means it's safe to do a full
17011                          * recalculation.
17012                          */
17013                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
17014
17015                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
17016                                 pixclk = ilk_pipe_pixel_rate(crtc->config);
17017                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17018                                 pixclk = crtc->config->base.adjusted_mode.crtc_clock;
17019                         else
17020                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
17021
17022                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
17023                         if (IS_BROADWELL(dev_priv) && crtc->config->ips_enabled)
17024                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
17025
17026                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
17027                         update_scanline_offset(crtc);
17028                 }
17029
17030                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
17031
17032                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
17033         }
17034 }
17035
17036 /* Scan out the current hw modeset state,
17037  * and sanitizes it to the current state
17038  */
17039 static void
17040 intel_modeset_setup_hw_state(struct drm_device *dev)
17041 {
17042         struct drm_i915_private *dev_priv = to_i915(dev);
17043         enum pipe pipe;
17044         struct intel_crtc *crtc;
17045         struct intel_encoder *encoder;
17046         int i;
17047
17048         intel_modeset_readout_hw_state(dev);
17049
17050         /* HW state is read out, now we need to sanitize this mess. */
17051         for_each_intel_encoder(dev, encoder) {
17052                 intel_sanitize_encoder(encoder);
17053         }
17054
17055         for_each_pipe(dev_priv, pipe) {
17056                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17057
17058                 intel_sanitize_crtc(crtc);
17059                 intel_dump_pipe_config(crtc, crtc->config,
17060                                        "[setup_hw_state]");
17061         }
17062
17063         intel_modeset_update_connector_atomic_state(dev);
17064
17065         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17066                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17067
17068                 if (!pll->on || pll->active_mask)
17069                         continue;
17070
17071                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
17072
17073                 pll->funcs.disable(dev_priv, pll);
17074                 pll->on = false;
17075         }
17076
17077         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17078                 vlv_wm_get_hw_state(dev);
17079         else if (IS_GEN9(dev_priv))
17080                 skl_wm_get_hw_state(dev);
17081         else if (HAS_PCH_SPLIT(dev_priv))
17082                 ilk_wm_get_hw_state(dev);
17083
17084         for_each_intel_crtc(dev, crtc) {
17085                 unsigned long put_domains;
17086
17087                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
17088                 if (WARN_ON(put_domains))
17089                         modeset_put_power_domains(dev_priv, put_domains);
17090         }
17091         intel_display_set_init_power(dev_priv, false);
17092
17093         intel_fbc_init_pipe_state(dev_priv);
17094 }
17095
17096 void intel_display_resume(struct drm_device *dev)
17097 {
17098         struct drm_i915_private *dev_priv = to_i915(dev);
17099         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17100         struct drm_modeset_acquire_ctx ctx;
17101         int ret;
17102
17103         dev_priv->modeset_restore_state = NULL;
17104         if (state)
17105                 state->acquire_ctx = &ctx;
17106
17107         /*
17108          * This is a cludge because with real atomic modeset mode_config.mutex
17109          * won't be taken. Unfortunately some probed state like
17110          * audio_codec_enable is still protected by mode_config.mutex, so lock
17111          * it here for now.
17112          */
17113         mutex_lock(&dev->mode_config.mutex);
17114         drm_modeset_acquire_init(&ctx, 0);
17115
17116         while (1) {
17117                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17118                 if (ret != -EDEADLK)
17119                         break;
17120
17121                 drm_modeset_backoff(&ctx);
17122         }
17123
17124         if (!ret)
17125                 ret = __intel_display_resume(dev, state);
17126
17127         drm_modeset_drop_locks(&ctx);
17128         drm_modeset_acquire_fini(&ctx);
17129         mutex_unlock(&dev->mode_config.mutex);
17130
17131         if (ret)
17132                 DRM_ERROR("Restoring old state failed with %i\n", ret);
17133         drm_atomic_state_put(state);
17134 }
17135
17136 void intel_modeset_gem_init(struct drm_device *dev)
17137 {
17138         struct drm_i915_private *dev_priv = to_i915(dev);
17139         struct drm_crtc *c;
17140         struct drm_i915_gem_object *obj;
17141
17142         intel_init_gt_powersave(dev_priv);
17143
17144         intel_modeset_init_hw(dev);
17145
17146         intel_setup_overlay(dev_priv);
17147
17148         /*
17149          * Make sure any fbs we allocated at startup are properly
17150          * pinned & fenced.  When we do the allocation it's too early
17151          * for this.
17152          */
17153         for_each_crtc(dev, c) {
17154                 struct i915_vma *vma;
17155
17156                 obj = intel_fb_obj(c->primary->fb);
17157                 if (obj == NULL)
17158                         continue;
17159
17160                 mutex_lock(&dev->struct_mutex);
17161                 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
17162                                                  c->primary->state->rotation);
17163                 mutex_unlock(&dev->struct_mutex);
17164                 if (IS_ERR(vma)) {
17165                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
17166                                   to_intel_crtc(c)->pipe);
17167                         drm_framebuffer_unreference(c->primary->fb);
17168                         c->primary->fb = NULL;
17169                         c->primary->crtc = c->primary->state->crtc = NULL;
17170                         update_state_fb(c->primary);
17171                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
17172                 }
17173         }
17174 }
17175
17176 int intel_connector_register(struct drm_connector *connector)
17177 {
17178         struct intel_connector *intel_connector = to_intel_connector(connector);
17179         int ret;
17180
17181         ret = intel_backlight_device_register(intel_connector);
17182         if (ret)
17183                 goto err;
17184
17185         return 0;
17186
17187 err:
17188         return ret;
17189 }
17190
17191 void intel_connector_unregister(struct drm_connector *connector)
17192 {
17193         struct intel_connector *intel_connector = to_intel_connector(connector);
17194
17195         intel_backlight_device_unregister(intel_connector);
17196         intel_panel_destroy_backlight(connector);
17197 }
17198
17199 void intel_modeset_cleanup(struct drm_device *dev)
17200 {
17201         struct drm_i915_private *dev_priv = to_i915(dev);
17202
17203         intel_disable_gt_powersave(dev_priv);
17204
17205         /*
17206          * Interrupts and polling as the first thing to avoid creating havoc.
17207          * Too much stuff here (turning of connectors, ...) would
17208          * experience fancy races otherwise.
17209          */
17210         intel_irq_uninstall(dev_priv);
17211
17212         /*
17213          * Due to the hpd irq storm handling the hotplug work can re-arm the
17214          * poll handlers. Hence disable polling after hpd handling is shut down.
17215          */
17216         drm_kms_helper_poll_fini(dev);
17217
17218         intel_unregister_dsm_handler();
17219
17220         intel_fbc_global_disable(dev_priv);
17221
17222         /* flush any delayed tasks or pending work */
17223         flush_scheduled_work();
17224
17225         drm_mode_config_cleanup(dev);
17226
17227         intel_cleanup_overlay(dev_priv);
17228
17229         intel_cleanup_gt_powersave(dev_priv);
17230
17231         intel_teardown_gmbus(dev_priv);
17232 }
17233
17234 void intel_connector_attach_encoder(struct intel_connector *connector,
17235                                     struct intel_encoder *encoder)
17236 {
17237         connector->encoder = encoder;
17238         drm_mode_connector_attach_encoder(&connector->base,
17239                                           &encoder->base);
17240 }
17241
17242 /*
17243  * set vga decode state - true == enable VGA decode
17244  */
17245 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
17246 {
17247         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17248         u16 gmch_ctrl;
17249
17250         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17251                 DRM_ERROR("failed to read control word\n");
17252                 return -EIO;
17253         }
17254
17255         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17256                 return 0;
17257
17258         if (state)
17259                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17260         else
17261                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17262
17263         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17264                 DRM_ERROR("failed to write control word\n");
17265                 return -EIO;
17266         }
17267
17268         return 0;
17269 }
17270
17271 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17272
17273 struct intel_display_error_state {
17274
17275         u32 power_well_driver;
17276
17277         int num_transcoders;
17278
17279         struct intel_cursor_error_state {
17280                 u32 control;
17281                 u32 position;
17282                 u32 base;
17283                 u32 size;
17284         } cursor[I915_MAX_PIPES];
17285
17286         struct intel_pipe_error_state {
17287                 bool power_domain_on;
17288                 u32 source;
17289                 u32 stat;
17290         } pipe[I915_MAX_PIPES];
17291
17292         struct intel_plane_error_state {
17293                 u32 control;
17294                 u32 stride;
17295                 u32 size;
17296                 u32 pos;
17297                 u32 addr;
17298                 u32 surface;
17299                 u32 tile_offset;
17300         } plane[I915_MAX_PIPES];
17301
17302         struct intel_transcoder_error_state {
17303                 bool power_domain_on;
17304                 enum transcoder cpu_transcoder;
17305
17306                 u32 conf;
17307
17308                 u32 htotal;
17309                 u32 hblank;
17310                 u32 hsync;
17311                 u32 vtotal;
17312                 u32 vblank;
17313                 u32 vsync;
17314         } transcoder[4];
17315 };
17316
17317 struct intel_display_error_state *
17318 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17319 {
17320         struct intel_display_error_state *error;
17321         int transcoders[] = {
17322                 TRANSCODER_A,
17323                 TRANSCODER_B,
17324                 TRANSCODER_C,
17325                 TRANSCODER_EDP,
17326         };
17327         int i;
17328
17329         if (INTEL_INFO(dev_priv)->num_pipes == 0)
17330                 return NULL;
17331
17332         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17333         if (error == NULL)
17334                 return NULL;
17335
17336         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17337                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17338
17339         for_each_pipe(dev_priv, i) {
17340                 error->pipe[i].power_domain_on =
17341                         __intel_display_power_is_enabled(dev_priv,
17342                                                          POWER_DOMAIN_PIPE(i));
17343                 if (!error->pipe[i].power_domain_on)
17344                         continue;
17345
17346                 error->cursor[i].control = I915_READ(CURCNTR(i));
17347                 error->cursor[i].position = I915_READ(CURPOS(i));
17348                 error->cursor[i].base = I915_READ(CURBASE(i));
17349
17350                 error->plane[i].control = I915_READ(DSPCNTR(i));
17351                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17352                 if (INTEL_GEN(dev_priv) <= 3) {
17353                         error->plane[i].size = I915_READ(DSPSIZE(i));
17354                         error->plane[i].pos = I915_READ(DSPPOS(i));
17355                 }
17356                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17357                         error->plane[i].addr = I915_READ(DSPADDR(i));
17358                 if (INTEL_GEN(dev_priv) >= 4) {
17359                         error->plane[i].surface = I915_READ(DSPSURF(i));
17360                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17361                 }
17362
17363                 error->pipe[i].source = I915_READ(PIPESRC(i));
17364
17365                 if (HAS_GMCH_DISPLAY(dev_priv))
17366                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17367         }
17368
17369         /* Note: this does not include DSI transcoders. */
17370         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17371         if (HAS_DDI(dev_priv))
17372                 error->num_transcoders++; /* Account for eDP. */
17373
17374         for (i = 0; i < error->num_transcoders; i++) {
17375                 enum transcoder cpu_transcoder = transcoders[i];
17376
17377                 error->transcoder[i].power_domain_on =
17378                         __intel_display_power_is_enabled(dev_priv,
17379                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17380                 if (!error->transcoder[i].power_domain_on)
17381                         continue;
17382
17383                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17384
17385                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17386                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17387                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17388                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17389                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17390                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17391                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17392         }
17393
17394         return error;
17395 }
17396
17397 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17398
17399 void
17400 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17401                                 struct drm_i915_private *dev_priv,
17402                                 struct intel_display_error_state *error)
17403 {
17404         int i;
17405
17406         if (!error)
17407                 return;
17408
17409         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
17410         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17411                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17412                            error->power_well_driver);
17413         for_each_pipe(dev_priv, i) {
17414                 err_printf(m, "Pipe [%d]:\n", i);
17415                 err_printf(m, "  Power: %s\n",
17416                            onoff(error->pipe[i].power_domain_on));
17417                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17418                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17419
17420                 err_printf(m, "Plane [%d]:\n", i);
17421                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17422                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17423                 if (INTEL_GEN(dev_priv) <= 3) {
17424                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17425                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17426                 }
17427                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17428                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17429                 if (INTEL_GEN(dev_priv) >= 4) {
17430                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17431                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17432                 }
17433
17434                 err_printf(m, "Cursor [%d]:\n", i);
17435                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17436                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17437                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17438         }
17439
17440         for (i = 0; i < error->num_transcoders; i++) {
17441                 err_printf(m, "CPU transcoder: %s\n",
17442                            transcoder_name(error->transcoder[i].cpu_transcoder));
17443                 err_printf(m, "  Power: %s\n",
17444                            onoff(error->transcoder[i].power_domain_on));
17445                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17446                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17447                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17448                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17449                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17450                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17451                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17452         }
17453 }
17454
17455 #endif