drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "intel_dsi.h"
  41 #include "i915_trace.h"
  42 #include <drm/drm_atomic.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_dp_helper.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_plane_helper.h>
  47 #include <drm/drm_rect.h>
  48 #include <linux/dma_remapping.h>
  49 #include <linux/reservation.h>
  50
  51 static bool is_mmio_work(struct intel_flip_work *work)
  52 {
  53         return work->mmio_work.func;
  54 }
  55
  56 /* Primary plane formats for gen <= 3 */
  57 static const uint32_t i8xx_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB1555,
  61         DRM_FORMAT_XRGB8888,
  62 };
  63
  64 /* Primary plane formats for gen >= 4 */
  65 static const uint32_t i965_primary_formats[] = {
  66         DRM_FORMAT_C8,
  67         DRM_FORMAT_RGB565,
  68         DRM_FORMAT_XRGB8888,
  69         DRM_FORMAT_XBGR8888,
  70         DRM_FORMAT_XRGB2101010,
  71         DRM_FORMAT_XBGR2101010,
  72 };
  73
  74 static const uint32_t skl_primary_formats[] = {
  75         DRM_FORMAT_C8,
  76         DRM_FORMAT_RGB565,
  77         DRM_FORMAT_XRGB8888,
  78         DRM_FORMAT_XBGR8888,
  79         DRM_FORMAT_ARGB8888,
  80         DRM_FORMAT_ABGR8888,
  81         DRM_FORMAT_XRGB2101010,
  82         DRM_FORMAT_XBGR2101010,
  83         DRM_FORMAT_YUYV,
  84         DRM_FORMAT_YVYU,
  85         DRM_FORMAT_UYVY,
  86         DRM_FORMAT_VYUY,
  87 };
  88
  89 /* Cursor formats */
  90 static const uint32_t intel_cursor_formats[] = {
  91         DRM_FORMAT_ARGB8888,
  92 };
  93
  94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  95                                 struct intel_crtc_state *pipe_config);
  96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  97                                    struct intel_crtc_state *pipe_config);
  98
  99 static int intel_framebuffer_init(struct drm_device *dev,
 100                                   struct intel_framebuffer *ifb,
 101                                   struct drm_mode_fb_cmd2 *mode_cmd,
 102                                   struct drm_i915_gem_object *obj);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 119                                     struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 126 static int glk_calc_cdclk(int max_pixclk);
 127 static int bxt_calc_cdclk(int max_pixclk);
 128
 129 struct intel_limit {
 130         struct {
 131                 int min, max;
 132         } dot, vco, n, m, m1, m2, p, p1;
 133
 134         struct {
 135                 int dot_limit;
 136                 int p2_slow, p2_fast;
 137         } p2;
 138 };
 139
 140 /* returns HPLL frequency in kHz */
 141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 142 {
 143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 144
 145         /* Obtain SKU information */
 146         mutex_lock(&dev_priv->sb_lock);
 147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 148                 CCK_FUSE_HPLL_FREQ_MASK;
 149         mutex_unlock(&dev_priv->sb_lock);
 150
 151         return vco_freq[hpll_freq] * 1000;
 152 }
 153
 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 155                       const char *name, u32 reg, int ref_freq)
 156 {
 157         u32 val;
 158         int divider;
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 171 }
 172
 173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 174                                   const char *name, u32 reg)
 175 {
 176         if (dev_priv->hpll_freq == 0)
 177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 178
 179         return vlv_get_cck_clock(dev_priv, name, reg,
 180                                  dev_priv->hpll_freq);
 181 }
 182
 183 static int
 184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 185 {
 186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 187 }
 188
 189 static int
 190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 191 {
 192         /* RAWCLK_FREQ_VLV register updated from power well code */
 193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 195 }
 196
 197 static int
 198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 199 {
 200         uint32_t clkcfg;
 201
 202         /* hrawclock is 1/4 the FSB frequency */
 203         clkcfg = I915_READ(CLKCFG);
 204         switch (clkcfg & CLKCFG_FSB_MASK) {
 205         case CLKCFG_FSB_400:
 206                 return 100000;
 207         case CLKCFG_FSB_533:
 208                 return 133333;
 209         case CLKCFG_FSB_667:
 210                 return 166667;
 211         case CLKCFG_FSB_800:
 212                 return 200000;
 213         case CLKCFG_FSB_1067:
 214                 return 266667;
 215         case CLKCFG_FSB_1333:
 216                 return 333333;
 217         /* these two are just a guess; one of them might be right */
 218         case CLKCFG_FSB_1600:
 219         case CLKCFG_FSB_1600_ALT:
 220                 return 400000;
 221         default:
 222                 return 133333;
 223         }
 224 }
 225
 226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 227 {
 228         if (HAS_PCH_SPLIT(dev_priv))
 229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 234         else
 235                 return; /* no rawclk on other platforms, or no need to know it */
 236
 237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 238 }
 239
 240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 241 {
 242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 243                 return;
 244
 245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 246                                                       CCK_CZ_CLOCK_CONTROL);
 247
 248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 249 }
 250
 251 static inline u32 /* units of 100MHz */
 252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 253                     const struct intel_crtc_state *pipe_config)
 254 {
 255         if (HAS_DDI(dev_priv))
 256                 return pipe_config->port_clock; /* SPLL */
 257         else if (IS_GEN5(dev_priv))
 258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 259         else
 260                 return 270000;
 261 }
 262
 263 static const struct intel_limit intel_limits_i8xx_dac = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 2, .max = 33 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 4, .p2_fast = 2 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i8xx_dvo = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 908000, .max = 1512000 },
 279         .n = { .min = 2, .max = 16 },
 280         .m = { .min = 96, .max = 140 },
 281         .m1 = { .min = 18, .max = 26 },
 282         .m2 = { .min = 6, .max = 16 },
 283         .p = { .min = 4, .max = 128 },
 284         .p1 = { .min = 2, .max = 33 },
 285         .p2 = { .dot_limit = 165000,
 286                 .p2_slow = 4, .p2_fast = 4 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i8xx_lvds = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 908000, .max = 1512000 },
 292         .n = { .min = 2, .max = 16 },
 293         .m = { .min = 96, .max = 140 },
 294         .m1 = { .min = 18, .max = 26 },
 295         .m2 = { .min = 6, .max = 16 },
 296         .p = { .min = 4, .max = 128 },
 297         .p1 = { .min = 1, .max = 6 },
 298         .p2 = { .dot_limit = 165000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302 static const struct intel_limit intel_limits_i9xx_sdvo = {
 303         .dot = { .min = 20000, .max = 400000 },
 304         .vco = { .min = 1400000, .max = 2800000 },
 305         .n = { .min = 1, .max = 6 },
 306         .m = { .min = 70, .max = 120 },
 307         .m1 = { .min = 8, .max = 18 },
 308         .m2 = { .min = 3, .max = 7 },
 309         .p = { .min = 5, .max = 80 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 200000,
 312                 .p2_slow = 10, .p2_fast = 5 },
 313 };
 314
 315 static const struct intel_limit intel_limits_i9xx_lvds = {
 316         .dot = { .min = 20000, .max = 400000 },
 317         .vco = { .min = 1400000, .max = 2800000 },
 318         .n = { .min = 1, .max = 6 },
 319         .m = { .min = 70, .max = 120 },
 320         .m1 = { .min = 8, .max = 18 },
 321         .m2 = { .min = 3, .max = 7 },
 322         .p = { .min = 7, .max = 98 },
 323         .p1 = { .min = 1, .max = 8 },
 324         .p2 = { .dot_limit = 112000,
 325                 .p2_slow = 14, .p2_fast = 7 },
 326 };
 327
 328
 329 static const struct intel_limit intel_limits_g4x_sdvo = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 1750000, .max = 3500000},
 332         .n = { .min = 1, .max = 4 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 1, .max = 3},
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 10,
 340                 .p2_fast = 10
 341         },
 342 };
 343
 344 static const struct intel_limit intel_limits_g4x_hdmi = {
 345         .dot = { .min = 22000, .max = 400000 },
 346         .vco = { .min = 1750000, .max = 3500000},
 347         .n = { .min = 1, .max = 4 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 16, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 5, .max = 80 },
 352         .p1 = { .min = 1, .max = 8},
 353         .p2 = { .dot_limit = 165000,
 354                 .p2_slow = 10, .p2_fast = 5 },
 355 };
 356
 357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 358         .dot = { .min = 20000, .max = 115000 },
 359         .vco = { .min = 1750000, .max = 3500000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 104, .max = 138 },
 362         .m1 = { .min = 17, .max = 23 },
 363         .m2 = { .min = 5, .max = 11 },
 364         .p = { .min = 28, .max = 112 },
 365         .p1 = { .min = 2, .max = 8 },
 366         .p2 = { .dot_limit = 0,
 367                 .p2_slow = 14, .p2_fast = 14
 368         },
 369 };
 370
 371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 372         .dot = { .min = 80000, .max = 224000 },
 373         .vco = { .min = 1750000, .max = 3500000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 104, .max = 138 },
 376         .m1 = { .min = 17, .max = 23 },
 377         .m2 = { .min = 5, .max = 11 },
 378         .p = { .min = 14, .max = 42 },
 379         .p1 = { .min = 2, .max = 6 },
 380         .p2 = { .dot_limit = 0,
 381                 .p2_slow = 7, .p2_fast = 7
 382         },
 383 };
 384
 385 static const struct intel_limit intel_limits_pineview_sdvo = {
 386         .dot = { .min = 20000, .max = 400000},
 387         .vco = { .min = 1700000, .max = 3500000 },
 388         /* Pineview's Ncounter is a ring counter */
 389         .n = { .min = 3, .max = 6 },
 390         .m = { .min = 2, .max = 256 },
 391         /* Pineview only has one combined m divider, which we treat as m2. */
 392         .m1 = { .min = 0, .max = 0 },
 393         .m2 = { .min = 0, .max = 254 },
 394         .p = { .min = 5, .max = 80 },
 395         .p1 = { .min = 1, .max = 8 },
 396         .p2 = { .dot_limit = 200000,
 397                 .p2_slow = 10, .p2_fast = 5 },
 398 };
 399
 400 static const struct intel_limit intel_limits_pineview_lvds = {
 401         .dot = { .min = 20000, .max = 400000 },
 402         .vco = { .min = 1700000, .max = 3500000 },
 403         .n = { .min = 3, .max = 6 },
 404         .m = { .min = 2, .max = 256 },
 405         .m1 = { .min = 0, .max = 0 },
 406         .m2 = { .min = 0, .max = 254 },
 407         .p = { .min = 7, .max = 112 },
 408         .p1 = { .min = 1, .max = 8 },
 409         .p2 = { .dot_limit = 112000,
 410                 .p2_slow = 14, .p2_fast = 14 },
 411 };
 412
 413 /* Ironlake / Sandybridge
 414  *
 415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 416  * the range value for them is (actual_value - 2).
 417  */
 418 static const struct intel_limit intel_limits_ironlake_dac = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 5 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 5, .max = 80 },
 426         .p1 = { .min = 1, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 10, .p2_fast = 5 },
 429 };
 430
 431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 3 },
 435         .m = { .min = 79, .max = 118 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 127 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 56 },
 452         .p1 = { .min = 2, .max = 8 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 /* LVDS 100mhz refclk limits. */
 458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 459         .dot = { .min = 25000, .max = 350000 },
 460         .vco = { .min = 1760000, .max = 3510000 },
 461         .n = { .min = 1, .max = 2 },
 462         .m = { .min = 79, .max = 126 },
 463         .m1 = { .min = 12, .max = 22 },
 464         .m2 = { .min = 5, .max = 9 },
 465         .p = { .min = 28, .max = 112 },
 466         .p1 = { .min = 2, .max = 8 },
 467         .p2 = { .dot_limit = 225000,
 468                 .p2_slow = 14, .p2_fast = 14 },
 469 };
 470
 471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 472         .dot = { .min = 25000, .max = 350000 },
 473         .vco = { .min = 1760000, .max = 3510000 },
 474         .n = { .min = 1, .max = 3 },
 475         .m = { .min = 79, .max = 126 },
 476         .m1 = { .min = 12, .max = 22 },
 477         .m2 = { .min = 5, .max = 9 },
 478         .p = { .min = 14, .max = 42 },
 479         .p1 = { .min = 2, .max = 6 },
 480         .p2 = { .dot_limit = 225000,
 481                 .p2_slow = 7, .p2_fast = 7 },
 482 };
 483
 484 static const struct intel_limit intel_limits_vlv = {
 485          /*
 486           * These are the data rate limits (measured in fast clocks)
 487           * since those are the strictest limits we have. The fast
 488           * clock and actual rate limits are more relaxed, so checking
 489           * them would make no difference.
 490           */
 491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 492         .vco = { .min = 4000000, .max = 6000000 },
 493         .n = { .min = 1, .max = 7 },
 494         .m1 = { .min = 2, .max = 3 },
 495         .m2 = { .min = 11, .max = 156 },
 496         .p1 = { .min = 2, .max = 3 },
 497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 498 };
 499
 500 static const struct intel_limit intel_limits_chv = {
 501         /*
 502          * These are the data rate limits (measured in fast clocks)
 503          * since those are the strictest limits we have.  The fast
 504          * clock and actual rate limits are more relaxed, so checking
 505          * them would make no difference.
 506          */
 507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 508         .vco = { .min = 4800000, .max = 6480000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 514 };
 515
 516 static const struct intel_limit intel_limits_bxt = {
 517         /* FIXME: find real dot limits */
 518         .dot = { .min = 0, .max = INT_MAX },
 519         .vco = { .min = 4800000, .max = 6700000 },
 520         .n = { .min = 1, .max = 1 },
 521         .m1 = { .min = 2, .max = 2 },
 522         /* FIXME: find real m2 limits */
 523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 524         .p1 = { .min = 2, .max = 4 },
 525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 526 };
 527
 528 static bool
 529 needs_modeset(struct drm_crtc_state *state)
 530 {
 531         return drm_atomic_crtc_needs_modeset(state);
 532 }
 533
 534 /*
 535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 538  * The helpers' return value is the rate of the clock that is fed to the
 539  * display engine's pipe which can be the above fast dot clock rate or a
 540  * divided-down version of it.
 541  */
 542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 544 {
 545         clock->m = clock->m2 + 2;
 546         clock->p = clock->p1 * clock->p2;
 547         if (WARN_ON(clock->n == 0 || clock->p == 0))
 548                 return 0;
 549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 551
 552         return clock->dot;
 553 }
 554
 555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 556 {
 557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 558 }
 559
 560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 561 {
 562         clock->m = i9xx_dpll_compute_m(clock);
 563         clock->p = clock->p1 * clock->p2;
 564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 565                 return 0;
 566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 568
 569         return clock->dot;
 570 }
 571
 572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 573 {
 574         clock->m = clock->m1 * clock->m2;
 575         clock->p = clock->p1 * clock->p2;
 576         if (WARN_ON(clock->n == 0 || clock->p == 0))
 577                 return 0;
 578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 580
 581         return clock->dot / 5;
 582 }
 583
 584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 585 {
 586         clock->m = clock->m1 * clock->m2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 591                         clock->n << 22);
 592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 593
 594         return clock->dot / 5;
 595 }
 596
 597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 598 /**
 599  * Returns whether the given set of divisors are valid for a given refclk with
 600  * the given connectors.
 601  */
 602
 603 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 604                                const struct intel_limit *limit,
 605                                const struct dpll *clock)
 606 {
 607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 608                 INTELPllInvalid("n out of range\n");
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 612                 INTELPllInvalid("m2 out of range\n");
 613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 614                 INTELPllInvalid("m1 out of range\n");
 615
 616         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 617             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 618                 if (clock->m1 <= clock->m2)
 619                         INTELPllInvalid("m1 <= m2\n");
 620
 621         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 622             !IS_GEN9_LP(dev_priv)) {
 623                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 624                         INTELPllInvalid("p out of range\n");
 625                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 626                         INTELPllInvalid("m out of range\n");
 627         }
 628
 629         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 630                 INTELPllInvalid("vco out of range\n");
 631         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 632          * connector, etc., rather than just a single range.
 633          */
 634         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 635                 INTELPllInvalid("dot out of range\n");
 636
 637         return true;
 638 }
 639
 640 static int
 641 i9xx_select_p2_div(const struct intel_limit *limit,
 642                    const struct intel_crtc_state *crtc_state,
 643                    int target)
 644 {
 645         struct drm_device *dev = crtc_state->base.crtc->dev;
 646
 647         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 648                 /*
 649                  * For LVDS just rely on its current settings for dual-channel.
 650                  * We haven't figured out how to reliably set up different
 651                  * single/dual channel state, if we even can.
 652                  */
 653                 if (intel_is_dual_link_lvds(dev))
 654                         return limit->p2.p2_fast;
 655                 else
 656                         return limit->p2.p2_slow;
 657         } else {
 658                 if (target < limit->p2.dot_limit)
 659                         return limit->p2.p2_slow;
 660                 else
 661                         return limit->p2.p2_fast;
 662         }
 663 }
 664
 665 /*
 666  * Returns a set of divisors for the desired target clock with the given
 667  * refclk, or FALSE.  The returned values represent the clock equation:
 668  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 669  *
 670  * Target and reference clocks are specified in kHz.
 671  *
 672  * If match_clock is provided, then best_clock P divider must match the P
 673  * divider from @match_clock used for LVDS downclocking.
 674  */
 675 static bool
 676 i9xx_find_best_dpll(const struct intel_limit *limit,
 677                     struct intel_crtc_state *crtc_state,
 678                     int target, int refclk, struct dpll *match_clock,
 679                     struct dpll *best_clock)
 680 {
 681         struct drm_device *dev = crtc_state->base.crtc->dev;
 682         struct dpll clock;
 683         int err = target;
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 688
 689         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 690              clock.m1++) {
 691                 for (clock.m2 = limit->m2.min;
 692                      clock.m2 <= limit->m2.max; clock.m2++) {
 693                         if (clock.m2 >= clock.m1)
 694                                 break;
 695                         for (clock.n = limit->n.min;
 696                              clock.n <= limit->n.max; clock.n++) {
 697                                 for (clock.p1 = limit->p1.min;
 698                                         clock.p1 <= limit->p1.max; clock.p1++) {
 699                                         int this_err;
 700
 701                                         i9xx_calc_dpll_params(refclk, &clock);
 702                                         if (!intel_PLL_is_valid(to_i915(dev),
 703                                                                 limit,
 704                                                                 &clock))
 705                                                 continue;
 706                                         if (match_clock &&
 707                                             clock.p != match_clock->p)
 708                                                 continue;
 709
 710                                         this_err = abs(clock.dot - target);
 711                                         if (this_err < err) {
 712                                                 *best_clock = clock;
 713                                                 err = this_err;
 714                                         }
 715                                 }
 716                         }
 717                 }
 718         }
 719
 720         return (err != target);
 721 }
 722
 723 /*
 724  * Returns a set of divisors for the desired target clock with the given
 725  * refclk, or FALSE.  The returned values represent the clock equation:
 726  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 727  *
 728  * Target and reference clocks are specified in kHz.
 729  *
 730  * If match_clock is provided, then best_clock P divider must match the P
 731  * divider from @match_clock used for LVDS downclocking.
 732  */
 733 static bool
 734 pnv_find_best_dpll(const struct intel_limit *limit,
 735                    struct intel_crtc_state *crtc_state,
 736                    int target, int refclk, struct dpll *match_clock,
 737                    struct dpll *best_clock)
 738 {
 739         struct drm_device *dev = crtc_state->base.crtc->dev;
 740         struct dpll clock;
 741         int err = target;
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744
 745         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 746
 747         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 748              clock.m1++) {
 749                 for (clock.m2 = limit->m2.min;
 750                      clock.m2 <= limit->m2.max; clock.m2++) {
 751                         for (clock.n = limit->n.min;
 752                              clock.n <= limit->n.max; clock.n++) {
 753                                 for (clock.p1 = limit->p1.min;
 754                                         clock.p1 <= limit->p1.max; clock.p1++) {
 755                                         int this_err;
 756
 757                                         pnv_calc_dpll_params(refclk, &clock);
 758                                         if (!intel_PLL_is_valid(to_i915(dev),
 759                                                                 limit,
 760                                                                 &clock))
 761                                                 continue;
 762                                         if (match_clock &&
 763                                             clock.p != match_clock->p)
 764                                                 continue;
 765
 766                                         this_err = abs(clock.dot - target);
 767                                         if (this_err < err) {
 768                                                 *best_clock = clock;
 769                                                 err = this_err;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return (err != target);
 777 }
 778
 779 /*
 780  * Returns a set of divisors for the desired target clock with the given
 781  * refclk, or FALSE.  The returned values represent the clock equation:
 782  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 783  *
 784  * Target and reference clocks are specified in kHz.
 785  *
 786  * If match_clock is provided, then best_clock P divider must match the P
 787  * divider from @match_clock used for LVDS downclocking.
 788  */
 789 static bool
 790 g4x_find_best_dpll(const struct intel_limit *limit,
 791                    struct intel_crtc_state *crtc_state,
 792                    int target, int refclk, struct dpll *match_clock,
 793                    struct dpll *best_clock)
 794 {
 795         struct drm_device *dev = crtc_state->base.crtc->dev;
 796         struct dpll clock;
 797         int max_n;
 798         bool found = false;
 799         /* approximately equals target * 0.00585 */
 800         int err_most = (target >> 8) + (target >> 9);
 801
 802         memset(best_clock, 0, sizeof(*best_clock));
 803
 804         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 805
 806         max_n = limit->n.max;
 807         /* based on hardware requirement, prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirement, prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         i9xx_calc_dpll_params(refclk, &clock);
 819                                         if (!intel_PLL_is_valid(to_i915(dev),
 820                                                                 limit,
 821                                                                 &clock))
 822                                                 continue;
 823
 824                                         this_err = abs(clock.dot - target);
 825                                         if (this_err < err_most) {
 826                                                 *best_clock = clock;
 827                                                 err_most = this_err;
 828                                                 max_n = clock.n;
 829                                                 found = true;
 830                                         }
 831                                 }
 832                         }
 833                 }
 834         }
 835         return found;
 836 }
 837
 838 /*
 839  * Check if the calculated PLL configuration is more optimal compared to the
 840  * best configuration and error found so far. Return the calculated error.
 841  */
 842 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 843                                const struct dpll *calculated_clock,
 844                                const struct dpll *best_clock,
 845                                unsigned int best_error_ppm,
 846                                unsigned int *error_ppm)
 847 {
 848         /*
 849          * For CHV ignore the error and consider only the P value.
 850          * Prefer a bigger P value based on HW requirements.
 851          */
 852         if (IS_CHERRYVIEW(to_i915(dev))) {
 853                 *error_ppm = 0;
 854
 855                 return calculated_clock->p > best_clock->p;
 856         }
 857
 858         if (WARN_ON_ONCE(!target_freq))
 859                 return false;
 860
 861         *error_ppm = div_u64(1000000ULL *
 862                                 abs(target_freq - calculated_clock->dot),
 863                              target_freq);
 864         /*
 865          * Prefer a better P value over a better (smaller) error if the error
 866          * is small. Ensure this preference for future configurations too by
 867          * setting the error to 0.
 868          */
 869         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 870                 *error_ppm = 0;
 871
 872                 return true;
 873         }
 874
 875         return *error_ppm + 10 < best_error_ppm;
 876 }
 877
 878 /*
 879  * Returns a set of divisors for the desired target clock with the given
 880  * refclk, or FALSE.  The returned values represent the clock equation:
 881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 882  */
 883 static bool
 884 vlv_find_best_dpll(const struct intel_limit *limit,
 885                    struct intel_crtc_state *crtc_state,
 886                    int target, int refclk, struct dpll *match_clock,
 887                    struct dpll *best_clock)
 888 {
 889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 890         struct drm_device *dev = crtc->base.dev;
 891         struct dpll clock;
 892         unsigned int bestppm = 1000000;
 893         /* min update 19.2 MHz */
 894         int max_n = min(limit->n.max, refclk / 19200);
 895         bool found = false;
 896
 897         target *= 5; /* fast clock */
 898
 899         memset(best_clock, 0, sizeof(*best_clock));
 900
 901         /* based on hardware requirement, prefer smaller n to precision */
 902         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 903                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 904                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 905                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 906                                 clock.p = clock.p1 * clock.p2;
 907                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 908                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 909                                         unsigned int ppm;
 910
 911                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 912                                                                      refclk * clock.m1);
 913
 914                                         vlv_calc_dpll_params(refclk, &clock);
 915
 916                                         if (!intel_PLL_is_valid(to_i915(dev),
 917                                                                 limit,
 918                                                                 &clock))
 919                                                 continue;
 920
 921                                         if (!vlv_PLL_is_optimal(dev, target,
 922                                                                 &clock,
 923                                                                 best_clock,
 924                                                                 bestppm, &ppm))
 925                                                 continue;
 926
 927                                         *best_clock = clock;
 928                                         bestppm = ppm;
 929                                         found = true;
 930                                 }
 931                         }
 932                 }
 933         }
 934
 935         return found;
 936 }
 937
 938 /*
 939  * Returns a set of divisors for the desired target clock with the given
 940  * refclk, or FALSE.  The returned values represent the clock equation:
 941  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 942  */
 943 static bool
 944 chv_find_best_dpll(const struct intel_limit *limit,
 945                    struct intel_crtc_state *crtc_state,
 946                    int target, int refclk, struct dpll *match_clock,
 947                    struct dpll *best_clock)
 948 {
 949         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 950         struct drm_device *dev = crtc->base.dev;
 951         unsigned int best_error_ppm;
 952         struct dpll clock;
 953         uint64_t m2;
 954         int found = false;
 955
 956         memset(best_clock, 0, sizeof(*best_clock));
 957         best_error_ppm = 1000000;
 958
 959         /*
 960          * Based on hardware doc, the n always set to 1, and m1 always
 961          * set to 2.  If requires to support 200Mhz refclk, we need to
 962          * revisit this because n may not 1 anymore.
 963          */
 964         clock.n = 1, clock.m1 = 2;
 965         target *= 5;    /* fast clock */
 966
 967         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 968                 for (clock.p2 = limit->p2.p2_fast;
 969                                 clock.p2 >= limit->p2.p2_slow;
 970                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 971                         unsigned int error_ppm;
 972
 973                         clock.p = clock.p1 * clock.p2;
 974
 975                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 976                                         clock.n) << 22, refclk * clock.m1);
 977
 978                         if (m2 > INT_MAX/clock.m1)
 979                                 continue;
 980
 981                         clock.m2 = m2;
 982
 983                         chv_calc_dpll_params(refclk, &clock);
 984
 985                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 986                                 continue;
 987
 988                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 989                                                 best_error_ppm, &error_ppm))
 990                                 continue;
 991
 992                         *best_clock = clock;
 993                         best_error_ppm = error_ppm;
 994                         found = true;
 995                 }
 996         }
 997
 998         return found;
 999 }
1000
1001 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1002                         struct dpll *best_clock)
1003 {
1004         int refclk = 100000;
1005         const struct intel_limit *limit = &intel_limits_bxt;
1006
1007         return chv_find_best_dpll(limit, crtc_state,
1008                                   target_clock, refclk, NULL, best_clock);
1009 }
1010
1011 bool intel_crtc_active(struct intel_crtc *crtc)
1012 {
1013         /* Be paranoid as we can arrive here with only partial
1014          * state retrieved from the hardware during setup.
1015          *
1016          * We can ditch the adjusted_mode.crtc_clock check as soon
1017          * as Haswell has gained clock readout/fastboot support.
1018          *
1019          * We can ditch the crtc->primary->fb check as soon as we can
1020          * properly reconstruct framebuffers.
1021          *
1022          * FIXME: The intel_crtc->active here should be switched to
1023          * crtc->state->active once we have proper CRTC states wired up
1024          * for atomic.
1025          */
1026         return crtc->active && crtc->base.primary->state->fb &&
1027                 crtc->config->base.adjusted_mode.crtc_clock;
1028 }
1029
1030 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1031                                              enum pipe pipe)
1032 {
1033         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1034
1035         return crtc->config->cpu_transcoder;
1036 }
1037
1038 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1039 {
1040         i915_reg_t reg = PIPEDSL(pipe);
1041         u32 line1, line2;
1042         u32 line_mask;
1043
1044         if (IS_GEN2(dev_priv))
1045                 line_mask = DSL_LINEMASK_GEN2;
1046         else
1047                 line_mask = DSL_LINEMASK_GEN3;
1048
1049         line1 = I915_READ(reg) & line_mask;
1050         msleep(5);
1051         line2 = I915_READ(reg) & line_mask;
1052
1053         return line1 == line2;
1054 }
1055
1056 /*
1057  * intel_wait_for_pipe_off - wait for pipe to turn off
1058  * @crtc: crtc whose pipe to wait for
1059  *
1060  * After disabling a pipe, we can't wait for vblank in the usual way,
1061  * spinning on the vblank interrupt status bit, since we won't actually
1062  * see an interrupt when the pipe is disabled.
1063  *
1064  * On Gen4 and above:
1065  *   wait for the pipe register state bit to turn off
1066  *
1067  * Otherwise:
1068  *   wait for the display line value to settle (it usually
1069  *   ends up stopping at the start of the next frame).
1070  *
1071  */
1072 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1073 {
1074         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076         enum pipe pipe = crtc->pipe;
1077
1078         if (INTEL_GEN(dev_priv) >= 4) {
1079                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081                 /* Wait for the Pipe State to go off */
1082                 if (intel_wait_for_register(dev_priv,
1083                                             reg, I965_PIPECONF_ACTIVE, 0,
1084                                             100))
1085                         WARN(1, "pipe_off wait timed out\n");
1086         } else {
1087                 /* Wait for the display line to settle */
1088                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1089                         WARN(1, "pipe_off wait timed out\n");
1090         }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state)
1096 {
1097         u32 val;
1098         bool cur_state;
1099
1100         val = I915_READ(DPLL(pipe));
1101         cur_state = !!(val & DPLL_VCO_ENABLE);
1102         I915_STATE_WARN(cur_state != state,
1103              "PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112
1113         mutex_lock(&dev_priv->sb_lock);
1114         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115         mutex_unlock(&dev_priv->sb_lock);
1116
1117         cur_state = val & DSI_PLL_VCO_EN;
1118         I915_STATE_WARN(cur_state != state,
1119              "DSI PLL state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124                           enum pipe pipe, bool state)
1125 {
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (HAS_DDI(dev_priv)) {
1131                 /* DDI does not have a specific FDI_TX register */
1132                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134         } else {
1135                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         I915_STATE_WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150
1151         val = I915_READ(FDI_RX_CTL(pipe));
1152         cur_state = !!(val & FDI_RX_ENABLE);
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI RX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161                                       enum pipe pipe)
1162 {
1163         u32 val;
1164
1165         /* ILK FDI PLL is always enabled */
1166         if (IS_GEN5(dev_priv))
1167                 return;
1168
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv))
1171                 return;
1172
1173         val = I915_READ(FDI_TX_CTL(pipe));
1174         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         u32 val;
1181         bool cur_state;
1182
1183         val = I915_READ(FDI_RX_CTL(pipe));
1184         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185         I915_STATE_WARN(cur_state != state,
1186              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187                         onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1191 {
1192         i915_reg_t pp_reg;
1193         u32 val;
1194         enum pipe panel_pipe = PIPE_A;
1195         bool locked = true;
1196
1197         if (WARN_ON(HAS_DDI(dev_priv)))
1198                 return;
1199
1200         if (HAS_PCH_SPLIT(dev_priv)) {
1201                 u32 port_sel;
1202
1203                 pp_reg = PP_CONTROL(0);
1204                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1205
1206                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1207                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1208                         panel_pipe = PIPE_B;
1209                 /* XXX: else fix for eDP */
1210         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1211                 /* presumably write lock depends on pipe, not port select */
1212                 pp_reg = PP_CONTROL(pipe);
1213                 panel_pipe = pipe;
1214         } else {
1215                 pp_reg = PP_CONTROL(0);
1216                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1217                         panel_pipe = PIPE_B;
1218         }
1219
1220         val = I915_READ(pp_reg);
1221         if (!(val & PANEL_POWER_ON) ||
1222             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1223                 locked = false;
1224
1225         I915_STATE_WARN(panel_pipe == pipe && locked,
1226              "panel assertion failure, pipe %c regs locked\n",
1227              pipe_name(pipe));
1228 }
1229
1230 static void assert_cursor(struct drm_i915_private *dev_priv,
1231                           enum pipe pipe, bool state)
1232 {
1233         bool cur_state;
1234
1235         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1236                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1237         else
1238                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1239
1240         I915_STATE_WARN(cur_state != state,
1241              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1242                         pipe_name(pipe), onoff(state), onoff(cur_state));
1243 }
1244 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1245 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1246
1247 void assert_pipe(struct drm_i915_private *dev_priv,
1248                  enum pipe pipe, bool state)
1249 {
1250         bool cur_state;
1251         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1252                                                                       pipe);
1253         enum intel_display_power_domain power_domain;
1254
1255         /* if we need the pipe quirk it must be always on */
1256         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1257             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1258                 state = true;
1259
1260         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1261         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1262                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1263                 cur_state = !!(val & PIPECONF_ENABLE);
1264
1265                 intel_display_power_put(dev_priv, power_domain);
1266         } else {
1267                 cur_state = false;
1268         }
1269
1270         I915_STATE_WARN(cur_state != state,
1271              "pipe %c assertion failure (expected %s, current %s)\n",
1272                         pipe_name(pipe), onoff(state), onoff(cur_state));
1273 }
1274
1275 static void assert_plane(struct drm_i915_private *dev_priv,
1276                          enum plane plane, bool state)
1277 {
1278         u32 val;
1279         bool cur_state;
1280
1281         val = I915_READ(DSPCNTR(plane));
1282         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1283         I915_STATE_WARN(cur_state != state,
1284              "plane %c assertion failure (expected %s, current %s)\n",
1285                         plane_name(plane), onoff(state), onoff(cur_state));
1286 }
1287
1288 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1289 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1290
1291 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1292                                    enum pipe pipe)
1293 {
1294         int i;
1295
1296         /* Primary planes are fixed to pipes on gen4+ */
1297         if (INTEL_GEN(dev_priv) >= 4) {
1298                 u32 val = I915_READ(DSPCNTR(pipe));
1299                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1300                      "plane %c assertion failure, should be disabled but not\n",
1301                      plane_name(pipe));
1302                 return;
1303         }
1304
1305         /* Need to check both planes against the pipe */
1306         for_each_pipe(dev_priv, i) {
1307                 u32 val = I915_READ(DSPCNTR(i));
1308                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1309                         DISPPLANE_SEL_PIPE_SHIFT;
1310                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1311                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1312                      plane_name(i), pipe_name(pipe));
1313         }
1314 }
1315
1316 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1317                                     enum pipe pipe)
1318 {
1319         int sprite;
1320
1321         if (INTEL_GEN(dev_priv) >= 9) {
1322                 for_each_sprite(dev_priv, pipe, sprite) {
1323                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1324                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1325                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1326                              sprite, pipe_name(pipe));
1327                 }
1328         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1329                 for_each_sprite(dev_priv, pipe, sprite) {
1330                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1331                         I915_STATE_WARN(val & SP_ENABLE,
1332                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1333                              sprite_name(pipe, sprite), pipe_name(pipe));
1334                 }
1335         } else if (INTEL_GEN(dev_priv) >= 7) {
1336                 u32 val = I915_READ(SPRCTL(pipe));
1337                 I915_STATE_WARN(val & SPRITE_ENABLE,
1338                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1339                      plane_name(pipe), pipe_name(pipe));
1340         } else if (INTEL_GEN(dev_priv) >= 5) {
1341                 u32 val = I915_READ(DVSCNTR(pipe));
1342                 I915_STATE_WARN(val & DVS_ENABLE,
1343                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                      plane_name(pipe), pipe_name(pipe));
1345         }
1346 }
1347
1348 static void assert_vblank_disabled(struct drm_crtc *crtc)
1349 {
1350         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1351                 drm_crtc_vblank_put(crtc);
1352 }
1353
1354 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355                                     enum pipe pipe)
1356 {
1357         u32 val;
1358         bool enabled;
1359
1360         val = I915_READ(PCH_TRANSCONF(pipe));
1361         enabled = !!(val & TRANS_ENABLE);
1362         I915_STATE_WARN(enabled,
1363              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1364              pipe_name(pipe));
1365 }
1366
1367 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1368                             enum pipe pipe, u32 port_sel, u32 val)
1369 {
1370         if ((val & DP_PORT_EN) == 0)
1371                 return false;
1372
1373         if (HAS_PCH_CPT(dev_priv)) {
1374                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1375                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376                         return false;
1377         } else if (IS_CHERRYVIEW(dev_priv)) {
1378                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379                         return false;
1380         } else {
1381                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382                         return false;
1383         }
1384         return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388                               enum pipe pipe, u32 val)
1389 {
1390         if ((val & SDVO_ENABLE) == 0)
1391                 return false;
1392
1393         if (HAS_PCH_CPT(dev_priv)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395                         return false;
1396         } else if (IS_CHERRYVIEW(dev_priv)) {
1397                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398                         return false;
1399         } else {
1400                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401                         return false;
1402         }
1403         return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407                               enum pipe pipe, u32 val)
1408 {
1409         if ((val & LVDS_PORT_EN) == 0)
1410                 return false;
1411
1412         if (HAS_PCH_CPT(dev_priv)) {
1413                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414                         return false;
1415         } else {
1416                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417                         return false;
1418         }
1419         return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423                               enum pipe pipe, u32 val)
1424 {
1425         if ((val & ADPA_DAC_ENABLE) == 0)
1426                 return false;
1427         if (HAS_PCH_CPT(dev_priv)) {
1428                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429                         return false;
1430         } else {
1431                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432                         return false;
1433         }
1434         return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438                                    enum pipe pipe, i915_reg_t reg,
1439                                    u32 port_sel)
1440 {
1441         u32 val = I915_READ(reg);
1442         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1443              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1444              i915_mmio_reg_offset(reg), pipe_name(pipe));
1445
1446         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1447              && (val & DP_PIPEB_SELECT),
1448              "IBX PCH dp port still using transcoder B\n");
1449 }
1450
1451 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1452                                      enum pipe pipe, i915_reg_t reg)
1453 {
1454         u32 val = I915_READ(reg);
1455         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1456              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1457              i915_mmio_reg_offset(reg), pipe_name(pipe));
1458
1459         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1460              && (val & SDVO_PIPE_B_SELECT),
1461              "IBX PCH hdmi port still using transcoder B\n");
1462 }
1463
1464 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1465                                       enum pipe pipe)
1466 {
1467         u32 val;
1468
1469         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473         val = I915_READ(PCH_ADPA);
1474         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1475              "PCH VGA enabled on transcoder %c, should be disabled\n",
1476              pipe_name(pipe));
1477
1478         val = I915_READ(PCH_LVDS);
1479         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1480              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1485         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1486 }
1487
1488 static void _vlv_enable_pll(struct intel_crtc *crtc,
1489                             const struct intel_crtc_state *pipe_config)
1490 {
1491         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1492         enum pipe pipe = crtc->pipe;
1493
1494         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1495         POSTING_READ(DPLL(pipe));
1496         udelay(150);
1497
1498         if (intel_wait_for_register(dev_priv,
1499                                     DPLL(pipe),
1500                                     DPLL_LOCK_VLV,
1501                                     DPLL_LOCK_VLV,
1502                                     1))
1503                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1504 }
1505
1506 static void vlv_enable_pll(struct intel_crtc *crtc,
1507                            const struct intel_crtc_state *pipe_config)
1508 {
1509         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1510         enum pipe pipe = crtc->pipe;
1511
1512         assert_pipe_disabled(dev_priv, pipe);
1513
1514         /* PLL is protected by panel, make sure we can write it */
1515         assert_panel_unlocked(dev_priv, pipe);
1516
1517         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1518                 _vlv_enable_pll(crtc, pipe_config);
1519
1520         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1521         POSTING_READ(DPLL_MD(pipe));
1522 }
1523
1524
1525 static void _chv_enable_pll(struct intel_crtc *crtc,
1526                             const struct intel_crtc_state *pipe_config)
1527 {
1528         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1529         enum pipe pipe = crtc->pipe;
1530         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1531         u32 tmp;
1532
1533         mutex_lock(&dev_priv->sb_lock);
1534
1535         /* Enable back the 10bit clock to display controller */
1536         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1537         tmp |= DPIO_DCLKP_EN;
1538         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1539
1540         mutex_unlock(&dev_priv->sb_lock);
1541
1542         /*
1543          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1544          */
1545         udelay(1);
1546
1547         /* Enable PLL */
1548         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1549
1550         /* Check PLL is locked */
1551         if (intel_wait_for_register(dev_priv,
1552                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1553                                     1))
1554                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1555 }
1556
1557 static void chv_enable_pll(struct intel_crtc *crtc,
1558                            const struct intel_crtc_state *pipe_config)
1559 {
1560         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561         enum pipe pipe = crtc->pipe;
1562
1563         assert_pipe_disabled(dev_priv, pipe);
1564
1565         /* PLL is protected by panel, make sure we can write it */
1566         assert_panel_unlocked(dev_priv, pipe);
1567
1568         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1569                 _chv_enable_pll(crtc, pipe_config);
1570
1571         if (pipe != PIPE_A) {
1572                 /*
1573                  * WaPixelRepeatModeFixForC0:chv
1574                  *
1575                  * DPLLCMD is AWOL. Use chicken bits to propagate
1576                  * the value from DPLLBMD to either pipe B or C.
1577                  */
1578                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1579                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1580                 I915_WRITE(CBR4_VLV, 0);
1581                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1582
1583                 /*
1584                  * DPLLB VGA mode also seems to cause problems.
1585                  * We should always have it disabled.
1586                  */
1587                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1588         } else {
1589                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1590                 POSTING_READ(DPLL_MD(pipe));
1591         }
1592 }
1593
1594 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1595 {
1596         struct intel_crtc *crtc;
1597         int count = 0;
1598
1599         for_each_intel_crtc(&dev_priv->drm, crtc) {
1600                 count += crtc->base.state->active &&
1601                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1602         }
1603
1604         return count;
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1610         i915_reg_t reg = DPLL(crtc->pipe);
1611         u32 dpll = crtc->config->dpll_hw_state.dpll;
1612
1613         assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615         /* PLL is protected by panel, make sure we can write it */
1616         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1617                 assert_panel_unlocked(dev_priv, crtc->pipe);
1618
1619         /* Enable DVO 2x clock on both PLLs if necessary */
1620         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1621                 /*
1622                  * It appears to be important that we don't enable this
1623                  * for the current pipe before otherwise configuring the
1624                  * PLL. No idea how this should be handled if multiple
1625                  * DVO outputs are enabled simultaneosly.
1626                  */
1627                 dpll |= DPLL_DVO_2X_MODE;
1628                 I915_WRITE(DPLL(!crtc->pipe),
1629                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1630         }
1631
1632         /*
1633          * Apparently we need to have VGA mode enabled prior to changing
1634          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1635          * dividers, even though the register value does change.
1636          */
1637         I915_WRITE(reg, 0);
1638
1639         I915_WRITE(reg, dpll);
1640
1641         /* Wait for the clocks to stabilize. */
1642         POSTING_READ(reg);
1643         udelay(150);
1644
1645         if (INTEL_GEN(dev_priv) >= 4) {
1646                 I915_WRITE(DPLL_MD(crtc->pipe),
1647                            crtc->config->dpll_hw_state.dpll_md);
1648         } else {
1649                 /* The pixel multiplier can only be updated once the
1650                  * DPLL is enabled and the clocks are stable.
1651                  *
1652                  * So write it again.
1653                  */
1654                 I915_WRITE(reg, dpll);
1655         }
1656
1657         /* We do this three times for luck */
1658         I915_WRITE(reg, dpll);
1659         POSTING_READ(reg);
1660         udelay(150); /* wait for warmup */
1661         I915_WRITE(reg, dpll);
1662         POSTING_READ(reg);
1663         udelay(150); /* wait for warmup */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667 }
1668
1669 /**
1670  * i9xx_disable_pll - disable a PLL
1671  * @dev_priv: i915 private structure
1672  * @pipe: pipe PLL to disable
1673  *
1674  * Disable the PLL for @pipe, making sure the pipe is off first.
1675  *
1676  * Note!  This is for pre-ILK only.
1677  */
1678 static void i9xx_disable_pll(struct intel_crtc *crtc)
1679 {
1680         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1681         enum pipe pipe = crtc->pipe;
1682
1683         /* Disable DVO 2x clock on both PLLs if necessary */
1684         if (IS_I830(dev_priv) &&
1685             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1686             !intel_num_dvo_pipes(dev_priv)) {
1687                 I915_WRITE(DPLL(PIPE_B),
1688                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1689                 I915_WRITE(DPLL(PIPE_A),
1690                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1691         }
1692
1693         /* Don't disable pipe or pipe PLLs if needed */
1694         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1695             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1696                 return;
1697
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700
1701         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1702         POSTING_READ(DPLL(pipe));
1703 }
1704
1705 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1706 {
1707         u32 val;
1708
1709         /* Make sure the pipe isn't still relying on us */
1710         assert_pipe_disabled(dev_priv, pipe);
1711
1712         val = DPLL_INTEGRATED_REF_CLK_VLV |
1713                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1714         if (pipe != PIPE_A)
1715                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1716
1717         I915_WRITE(DPLL(pipe), val);
1718         POSTING_READ(DPLL(pipe));
1719 }
1720
1721 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1722 {
1723         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1724         u32 val;
1725
1726         /* Make sure the pipe isn't still relying on us */
1727         assert_pipe_disabled(dev_priv, pipe);
1728
1729         val = DPLL_SSC_REF_CLK_CHV |
1730                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1731         if (pipe != PIPE_A)
1732                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1733
1734         I915_WRITE(DPLL(pipe), val);
1735         POSTING_READ(DPLL(pipe));
1736
1737         mutex_lock(&dev_priv->sb_lock);
1738
1739         /* Disable 10bit clock to display controller */
1740         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1741         val &= ~DPIO_DCLKP_EN;
1742         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1743
1744         mutex_unlock(&dev_priv->sb_lock);
1745 }
1746
1747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1748                          struct intel_digital_port *dport,
1749                          unsigned int expected_mask)
1750 {
1751         u32 port_mask;
1752         i915_reg_t dpll_reg;
1753
1754         switch (dport->port) {
1755         case PORT_B:
1756                 port_mask = DPLL_PORTB_READY_MASK;
1757                 dpll_reg = DPLL(0);
1758                 break;
1759         case PORT_C:
1760                 port_mask = DPLL_PORTC_READY_MASK;
1761                 dpll_reg = DPLL(0);
1762                 expected_mask <<= 4;
1763                 break;
1764         case PORT_D:
1765                 port_mask = DPLL_PORTD_READY_MASK;
1766                 dpll_reg = DPIO_PHY_STATUS;
1767                 break;
1768         default:
1769                 BUG();
1770         }
1771
1772         if (intel_wait_for_register(dev_priv,
1773                                     dpll_reg, port_mask, expected_mask,
1774                                     1000))
1775                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1776                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1777 }
1778
1779 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1780                                            enum pipe pipe)
1781 {
1782         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1783                                                                 pipe);
1784         i915_reg_t reg;
1785         uint32_t val, pipeconf_val;
1786
1787         /* Make sure PCH DPLL is enabled */
1788         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1789
1790         /* FDI must be feeding us bits for PCH ports */
1791         assert_fdi_tx_enabled(dev_priv, pipe);
1792         assert_fdi_rx_enabled(dev_priv, pipe);
1793
1794         if (HAS_PCH_CPT(dev_priv)) {
1795                 /* Workaround: Set the timing override bit before enabling the
1796                  * pch transcoder. */
1797                 reg = TRANS_CHICKEN2(pipe);
1798                 val = I915_READ(reg);
1799                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1800                 I915_WRITE(reg, val);
1801         }
1802
1803         reg = PCH_TRANSCONF(pipe);
1804         val = I915_READ(reg);
1805         pipeconf_val = I915_READ(PIPECONF(pipe));
1806
1807         if (HAS_PCH_IBX(dev_priv)) {
1808                 /*
1809                  * Make the BPC in transcoder be consistent with
1810                  * that in pipeconf reg. For HDMI we must use 8bpc
1811                  * here for both 8bpc and 12bpc.
1812                  */
1813                 val &= ~PIPECONF_BPC_MASK;
1814                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1815                         val |= PIPECONF_8BPC;
1816                 else
1817                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1818         }
1819
1820         val &= ~TRANS_INTERLACE_MASK;
1821         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1822                 if (HAS_PCH_IBX(dev_priv) &&
1823                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1824                         val |= TRANS_LEGACY_INTERLACED_ILK;
1825                 else
1826                         val |= TRANS_INTERLACED;
1827         else
1828                 val |= TRANS_PROGRESSIVE;
1829
1830         I915_WRITE(reg, val | TRANS_ENABLE);
1831         if (intel_wait_for_register(dev_priv,
1832                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1833                                     100))
1834                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1835 }
1836
1837 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1838                                       enum transcoder cpu_transcoder)
1839 {
1840         u32 val, pipeconf_val;
1841
1842         /* FDI must be feeding us bits for PCH ports */
1843         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1844         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1845
1846         /* Workaround: set timing override bit. */
1847         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1848         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1849         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1850
1851         val = TRANS_ENABLE;
1852         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1853
1854         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1855             PIPECONF_INTERLACED_ILK)
1856                 val |= TRANS_INTERLACED;
1857         else
1858                 val |= TRANS_PROGRESSIVE;
1859
1860         I915_WRITE(LPT_TRANSCONF, val);
1861         if (intel_wait_for_register(dev_priv,
1862                                     LPT_TRANSCONF,
1863                                     TRANS_STATE_ENABLE,
1864                                     TRANS_STATE_ENABLE,
1865                                     100))
1866                 DRM_ERROR("Failed to enable PCH transcoder\n");
1867 }
1868
1869 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1870                                             enum pipe pipe)
1871 {
1872         i915_reg_t reg;
1873         uint32_t val;
1874
1875         /* FDI relies on the transcoder */
1876         assert_fdi_tx_disabled(dev_priv, pipe);
1877         assert_fdi_rx_disabled(dev_priv, pipe);
1878
1879         /* Ports must be off as well */
1880         assert_pch_ports_disabled(dev_priv, pipe);
1881
1882         reg = PCH_TRANSCONF(pipe);
1883         val = I915_READ(reg);
1884         val &= ~TRANS_ENABLE;
1885         I915_WRITE(reg, val);
1886         /* wait for PCH transcoder off, transcoder state */
1887         if (intel_wait_for_register(dev_priv,
1888                                     reg, TRANS_STATE_ENABLE, 0,
1889                                     50))
1890                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1891
1892         if (HAS_PCH_CPT(dev_priv)) {
1893                 /* Workaround: Clear the timing override chicken bit again. */
1894                 reg = TRANS_CHICKEN2(pipe);
1895                 val = I915_READ(reg);
1896                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1897                 I915_WRITE(reg, val);
1898         }
1899 }
1900
1901 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1902 {
1903         u32 val;
1904
1905         val = I915_READ(LPT_TRANSCONF);
1906         val &= ~TRANS_ENABLE;
1907         I915_WRITE(LPT_TRANSCONF, val);
1908         /* wait for PCH transcoder off, transcoder state */
1909         if (intel_wait_for_register(dev_priv,
1910                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1911                                     50))
1912                 DRM_ERROR("Failed to disable PCH transcoder\n");
1913
1914         /* Workaround: clear timing override bit. */
1915         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1916         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1918 }
1919
1920 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1921 {
1922         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1923
1924         WARN_ON(!crtc->config->has_pch_encoder);
1925
1926         if (HAS_PCH_LPT(dev_priv))
1927                 return TRANSCODER_A;
1928         else
1929                 return (enum transcoder) crtc->pipe;
1930 }
1931
1932 /**
1933  * intel_enable_pipe - enable a pipe, asserting requirements
1934  * @crtc: crtc responsible for the pipe
1935  *
1936  * Enable @crtc's pipe, making sure that various hardware specific requirements
1937  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1938  */
1939 static void intel_enable_pipe(struct intel_crtc *crtc)
1940 {
1941         struct drm_device *dev = crtc->base.dev;
1942         struct drm_i915_private *dev_priv = to_i915(dev);
1943         enum pipe pipe = crtc->pipe;
1944         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1945         i915_reg_t reg;
1946         u32 val;
1947
1948         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1949
1950         assert_planes_disabled(dev_priv, pipe);
1951         assert_cursor_disabled(dev_priv, pipe);
1952         assert_sprites_disabled(dev_priv, pipe);
1953
1954         /*
1955          * A pipe without a PLL won't actually be able to drive bits from
1956          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1957          * need the check.
1958          */
1959         if (HAS_GMCH_DISPLAY(dev_priv)) {
1960                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1961                         assert_dsi_pll_enabled(dev_priv);
1962                 else
1963                         assert_pll_enabled(dev_priv, pipe);
1964         } else {
1965                 if (crtc->config->has_pch_encoder) {
1966                         /* if driving the PCH, we need FDI enabled */
1967                         assert_fdi_rx_pll_enabled(dev_priv,
1968                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1969                         assert_fdi_tx_pll_enabled(dev_priv,
1970                                                   (enum pipe) cpu_transcoder);
1971                 }
1972                 /* FIXME: assert CPU port conditions for SNB+ */
1973         }
1974
1975         reg = PIPECONF(cpu_transcoder);
1976         val = I915_READ(reg);
1977         if (val & PIPECONF_ENABLE) {
1978                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1979                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1980                 return;
1981         }
1982
1983         I915_WRITE(reg, val | PIPECONF_ENABLE);
1984         POSTING_READ(reg);
1985
1986         /*
1987          * Until the pipe starts DSL will read as 0, which would cause
1988          * an apparent vblank timestamp jump, which messes up also the
1989          * frame count when it's derived from the timestamps. So let's
1990          * wait for the pipe to start properly before we call
1991          * drm_crtc_vblank_on()
1992          */
1993         if (dev->max_vblank_count == 0 &&
1994             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1995                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1996 }
1997
1998 /**
1999  * intel_disable_pipe - disable a pipe, asserting requirements
2000  * @crtc: crtc whose pipes is to be disabled
2001  *
2002  * Disable the pipe of @crtc, making sure that various hardware
2003  * specific requirements are met, if applicable, e.g. plane
2004  * disabled, panel fitter off, etc.
2005  *
2006  * Will wait until the pipe has shut down before returning.
2007  */
2008 static void intel_disable_pipe(struct intel_crtc *crtc)
2009 {
2010         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2011         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2012         enum pipe pipe = crtc->pipe;
2013         i915_reg_t reg;
2014         u32 val;
2015
2016         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2017
2018         /*
2019          * Make sure planes won't keep trying to pump pixels to us,
2020          * or we might hang the display.
2021          */
2022         assert_planes_disabled(dev_priv, pipe);
2023         assert_cursor_disabled(dev_priv, pipe);
2024         assert_sprites_disabled(dev_priv, pipe);
2025
2026         reg = PIPECONF(cpu_transcoder);
2027         val = I915_READ(reg);
2028         if ((val & PIPECONF_ENABLE) == 0)
2029                 return;
2030
2031         /*
2032          * Double wide has implications for planes
2033          * so best keep it disabled when not needed.
2034          */
2035         if (crtc->config->double_wide)
2036                 val &= ~PIPECONF_DOUBLE_WIDE;
2037
2038         /* Don't disable pipe or pipe PLLs if needed */
2039         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2040             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2041                 val &= ~PIPECONF_ENABLE;
2042
2043         I915_WRITE(reg, val);
2044         if ((val & PIPECONF_ENABLE) == 0)
2045                 intel_wait_for_pipe_off(crtc);
2046 }
2047
2048 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2049 {
2050         return IS_GEN2(dev_priv) ? 2048 : 4096;
2051 }
2052
2053 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2054                                            uint64_t fb_modifier, unsigned int cpp)
2055 {
2056         switch (fb_modifier) {
2057         case DRM_FORMAT_MOD_NONE:
2058                 return cpp;
2059         case I915_FORMAT_MOD_X_TILED:
2060                 if (IS_GEN2(dev_priv))
2061                         return 128;
2062                 else
2063                         return 512;
2064         case I915_FORMAT_MOD_Y_TILED:
2065                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2066                         return 128;
2067                 else
2068                         return 512;
2069         case I915_FORMAT_MOD_Yf_TILED:
2070                 switch (cpp) {
2071                 case 1:
2072                         return 64;
2073                 case 2:
2074                 case 4:
2075                         return 128;
2076                 case 8:
2077                 case 16:
2078                         return 256;
2079                 default:
2080                         MISSING_CASE(cpp);
2081                         return cpp;
2082                 }
2083                 break;
2084         default:
2085                 MISSING_CASE(fb_modifier);
2086                 return cpp;
2087         }
2088 }
2089
2090 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2091                                uint64_t fb_modifier, unsigned int cpp)
2092 {
2093         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2094                 return 1;
2095         else
2096                 return intel_tile_size(dev_priv) /
2097                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2098 }
2099
2100 /* Return the tile dimensions in pixel units */
2101 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2102                             unsigned int *tile_width,
2103                             unsigned int *tile_height,
2104                             uint64_t fb_modifier,
2105                             unsigned int cpp)
2106 {
2107         unsigned int tile_width_bytes =
2108                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2109
2110         *tile_width = tile_width_bytes / cpp;
2111         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2112 }
2113
2114 unsigned int
2115 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2116                       uint32_t pixel_format, uint64_t fb_modifier)
2117 {
2118         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2119         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2120
2121         return ALIGN(height, tile_height);
2122 }
2123
2124 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2125 {
2126         unsigned int size = 0;
2127         int i;
2128
2129         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2130                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2131
2132         return size;
2133 }
2134
2135 static void
2136 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2137                         const struct drm_framebuffer *fb,
2138                         unsigned int rotation)
2139 {
2140         if (drm_rotation_90_or_270(rotation)) {
2141                 *view = i915_ggtt_view_rotated;
2142                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2143         } else {
2144                 *view = i915_ggtt_view_normal;
2145         }
2146 }
2147
2148 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2149 {
2150         if (INTEL_INFO(dev_priv)->gen >= 9)
2151                 return 256 * 1024;
2152         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2153                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2154                 return 128 * 1024;
2155         else if (INTEL_INFO(dev_priv)->gen >= 4)
2156                 return 4 * 1024;
2157         else
2158                 return 0;
2159 }
2160
2161 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2162                                          uint64_t fb_modifier)
2163 {
2164         switch (fb_modifier) {
2165         case DRM_FORMAT_MOD_NONE:
2166                 return intel_linear_alignment(dev_priv);
2167         case I915_FORMAT_MOD_X_TILED:
2168                 if (INTEL_INFO(dev_priv)->gen >= 9)
2169                         return 256 * 1024;
2170                 return 0;
2171         case I915_FORMAT_MOD_Y_TILED:
2172         case I915_FORMAT_MOD_Yf_TILED:
2173                 return 1 * 1024 * 1024;
2174         default:
2175                 MISSING_CASE(fb_modifier);
2176                 return 0;
2177         }
2178 }
2179
2180 struct i915_vma *
2181 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2182 {
2183         struct drm_device *dev = fb->dev;
2184         struct drm_i915_private *dev_priv = to_i915(dev);
2185         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2186         struct i915_ggtt_view view;
2187         struct i915_vma *vma;
2188         u32 alignment;
2189
2190         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2191
2192         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2193
2194         intel_fill_fb_ggtt_view(&view, fb, rotation);
2195
2196         /* Note that the w/a also requires 64 PTE of padding following the
2197          * bo. We currently fill all unused PTE with the shadow page and so
2198          * we should always have valid PTE following the scanout preventing
2199          * the VT-d warning.
2200          */
2201         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2202                 alignment = 256 * 1024;
2203
2204         /*
2205          * Global gtt pte registers are special registers which actually forward
2206          * writes to a chunk of system memory. Which means that there is no risk
2207          * that the register values disappear as soon as we call
2208          * intel_runtime_pm_put(), so it is correct to wrap only the
2209          * pin/unpin/fence and not more.
2210          */
2211         intel_runtime_pm_get(dev_priv);
2212
2213         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2214         if (IS_ERR(vma))
2215                 goto err;
2216
2217         if (i915_vma_is_map_and_fenceable(vma)) {
2218                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2219                  * fence, whereas 965+ only requires a fence if using
2220                  * framebuffer compression.  For simplicity, we always, when
2221                  * possible, install a fence as the cost is not that onerous.
2222                  *
2223                  * If we fail to fence the tiled scanout, then either the
2224                  * modeset will reject the change (which is highly unlikely as
2225                  * the affected systems, all but one, do not have unmappable
2226                  * space) or we will not be able to enable full powersaving
2227                  * techniques (also likely not to apply due to various limits
2228                  * FBC and the like impose on the size of the buffer, which
2229                  * presumably we violated anyway with this unmappable buffer).
2230                  * Anyway, it is presumably better to stumble onwards with
2231                  * something and try to run the system in a "less than optimal"
2232                  * mode that matches the user configuration.
2233                  */
2234                 if (i915_vma_get_fence(vma) == 0)
2235                         i915_vma_pin_fence(vma);
2236         }
2237
2238 err:
2239         intel_runtime_pm_put(dev_priv);
2240         return vma;
2241 }
2242
2243 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2244 {
2245         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2246         struct i915_ggtt_view view;
2247         struct i915_vma *vma;
2248
2249         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2250
2251         intel_fill_fb_ggtt_view(&view, fb, rotation);
2252         vma = i915_gem_object_to_ggtt(obj, &view);
2253
2254         i915_vma_unpin_fence(vma);
2255         i915_gem_object_unpin_from_display_plane(vma);
2256 }
2257
2258 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2259                           unsigned int rotation)
2260 {
2261         if (drm_rotation_90_or_270(rotation))
2262                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2263         else
2264                 return fb->pitches[plane];
2265 }
2266
2267 /*
2268  * Convert the x/y offsets into a linear offset.
2269  * Only valid with 0/180 degree rotation, which is fine since linear
2270  * offset is only used with linear buffers on pre-hsw and tiled buffers
2271  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2272  */
2273 u32 intel_fb_xy_to_linear(int x, int y,
2274                           const struct intel_plane_state *state,
2275                           int plane)
2276 {
2277         const struct drm_framebuffer *fb = state->base.fb;
2278         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2279         unsigned int pitch = fb->pitches[plane];
2280
2281         return y * pitch + x * cpp;
2282 }
2283
2284 /*
2285  * Add the x/y offsets derived from fb->offsets[] to the user
2286  * specified plane src x/y offsets. The resulting x/y offsets
2287  * specify the start of scanout from the beginning of the gtt mapping.
2288  */
2289 void intel_add_fb_offsets(int *x, int *y,
2290                           const struct intel_plane_state *state,
2291                           int plane)
2292
2293 {
2294         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2295         unsigned int rotation = state->base.rotation;
2296
2297         if (drm_rotation_90_or_270(rotation)) {
2298                 *x += intel_fb->rotated[plane].x;
2299                 *y += intel_fb->rotated[plane].y;
2300         } else {
2301                 *x += intel_fb->normal[plane].x;
2302                 *y += intel_fb->normal[plane].y;
2303         }
2304 }
2305
2306 /*
2307  * Input tile dimensions and pitch must already be
2308  * rotated to match x and y, and in pixel units.
2309  */
2310 static u32 _intel_adjust_tile_offset(int *x, int *y,
2311                                      unsigned int tile_width,
2312                                      unsigned int tile_height,
2313                                      unsigned int tile_size,
2314                                      unsigned int pitch_tiles,
2315                                      u32 old_offset,
2316                                      u32 new_offset)
2317 {
2318         unsigned int pitch_pixels = pitch_tiles * tile_width;
2319         unsigned int tiles;
2320
2321         WARN_ON(old_offset & (tile_size - 1));
2322         WARN_ON(new_offset & (tile_size - 1));
2323         WARN_ON(new_offset > old_offset);
2324
2325         tiles = (old_offset - new_offset) / tile_size;
2326
2327         *y += tiles / pitch_tiles * tile_height;
2328         *x += tiles % pitch_tiles * tile_width;
2329
2330         /* minimize x in case it got needlessly big */
2331         *y += *x / pitch_pixels * tile_height;
2332         *x %= pitch_pixels;
2333
2334         return new_offset;
2335 }
2336
2337 /*
2338  * Adjust the tile offset by moving the difference into
2339  * the x/y offsets.
2340  */
2341 static u32 intel_adjust_tile_offset(int *x, int *y,
2342                                     const struct intel_plane_state *state, int plane,
2343                                     u32 old_offset, u32 new_offset)
2344 {
2345         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2346         const struct drm_framebuffer *fb = state->base.fb;
2347         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2348         unsigned int rotation = state->base.rotation;
2349         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2350
2351         WARN_ON(new_offset > old_offset);
2352
2353         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2354                 unsigned int tile_size, tile_width, tile_height;
2355                 unsigned int pitch_tiles;
2356
2357                 tile_size = intel_tile_size(dev_priv);
2358                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2359                                 fb->modifier, cpp);
2360
2361                 if (drm_rotation_90_or_270(rotation)) {
2362                         pitch_tiles = pitch / tile_height;
2363                         swap(tile_width, tile_height);
2364                 } else {
2365                         pitch_tiles = pitch / (tile_width * cpp);
2366                 }
2367
2368                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2369                                           tile_size, pitch_tiles,
2370                                           old_offset, new_offset);
2371         } else {
2372                 old_offset += *y * pitch + *x * cpp;
2373
2374                 *y = (old_offset - new_offset) / pitch;
2375                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2376         }
2377
2378         return new_offset;
2379 }
2380
2381 /*
2382  * Computes the linear offset to the base tile and adjusts
2383  * x, y. bytes per pixel is assumed to be a power-of-two.
2384  *
2385  * In the 90/270 rotated case, x and y are assumed
2386  * to be already rotated to match the rotated GTT view, and
2387  * pitch is the tile_height aligned framebuffer height.
2388  *
2389  * This function is used when computing the derived information
2390  * under intel_framebuffer, so using any of that information
2391  * here is not allowed. Anything under drm_framebuffer can be
2392  * used. This is why the user has to pass in the pitch since it
2393  * is specified in the rotated orientation.
2394  */
2395 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2396                                       int *x, int *y,
2397                                       const struct drm_framebuffer *fb, int plane,
2398                                       unsigned int pitch,
2399                                       unsigned int rotation,
2400                                       u32 alignment)
2401 {
2402         uint64_t fb_modifier = fb->modifier;
2403         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2404         u32 offset, offset_aligned;
2405
2406         if (alignment)
2407                 alignment--;
2408
2409         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2410                 unsigned int tile_size, tile_width, tile_height;
2411                 unsigned int tile_rows, tiles, pitch_tiles;
2412
2413                 tile_size = intel_tile_size(dev_priv);
2414                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2415                                 fb_modifier, cpp);
2416
2417                 if (drm_rotation_90_or_270(rotation)) {
2418                         pitch_tiles = pitch / tile_height;
2419                         swap(tile_width, tile_height);
2420                 } else {
2421                         pitch_tiles = pitch / (tile_width * cpp);
2422                 }
2423
2424                 tile_rows = *y / tile_height;
2425                 *y %= tile_height;
2426
2427                 tiles = *x / tile_width;
2428                 *x %= tile_width;
2429
2430                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2431                 offset_aligned = offset & ~alignment;
2432
2433                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2434                                           tile_size, pitch_tiles,
2435                                           offset, offset_aligned);
2436         } else {
2437                 offset = *y * pitch + *x * cpp;
2438                 offset_aligned = offset & ~alignment;
2439
2440                 *y = (offset & alignment) / pitch;
2441                 *x = ((offset & alignment) - *y * pitch) / cpp;
2442         }
2443
2444         return offset_aligned;
2445 }
2446
2447 u32 intel_compute_tile_offset(int *x, int *y,
2448                               const struct intel_plane_state *state,
2449                               int plane)
2450 {
2451         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2452         const struct drm_framebuffer *fb = state->base.fb;
2453         unsigned int rotation = state->base.rotation;
2454         int pitch = intel_fb_pitch(fb, plane, rotation);
2455         u32 alignment;
2456
2457         /* AUX_DIST needs only 4K alignment */
2458         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2459                 alignment = 4096;
2460         else
2461                 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2462
2463         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2464                                           rotation, alignment);
2465 }
2466
2467 /* Convert the fb->offset[] linear offset into x/y offsets */
2468 static void intel_fb_offset_to_xy(int *x, int *y,
2469                                   const struct drm_framebuffer *fb, int plane)
2470 {
2471         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2472         unsigned int pitch = fb->pitches[plane];
2473         u32 linear_offset = fb->offsets[plane];
2474
2475         *y = linear_offset / pitch;
2476         *x = linear_offset % pitch / cpp;
2477 }
2478
2479 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2480 {
2481         switch (fb_modifier) {
2482         case I915_FORMAT_MOD_X_TILED:
2483                 return I915_TILING_X;
2484         case I915_FORMAT_MOD_Y_TILED:
2485                 return I915_TILING_Y;
2486         default:
2487                 return I915_TILING_NONE;
2488         }
2489 }
2490
2491 static int
2492 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2493                    struct drm_framebuffer *fb)
2494 {
2495         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2496         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2497         u32 gtt_offset_rotated = 0;
2498         unsigned int max_size = 0;
2499         uint32_t format = fb->pixel_format;
2500         int i, num_planes = drm_format_num_planes(format);
2501         unsigned int tile_size = intel_tile_size(dev_priv);
2502
2503         for (i = 0; i < num_planes; i++) {
2504                 unsigned int width, height;
2505                 unsigned int cpp, size;
2506                 u32 offset;
2507                 int x, y;
2508
2509                 cpp = drm_format_plane_cpp(format, i);
2510                 width = drm_format_plane_width(fb->width, format, i);
2511                 height = drm_format_plane_height(fb->height, format, i);
2512
2513                 intel_fb_offset_to_xy(&x, &y, fb, i);
2514
2515                 /*
2516                  * The fence (if used) is aligned to the start of the object
2517                  * so having the framebuffer wrap around across the edge of the
2518                  * fenced region doesn't really work. We have no API to configure
2519                  * the fence start offset within the object (nor could we probably
2520                  * on gen2/3). So it's just easier if we just require that the
2521                  * fb layout agrees with the fence layout. We already check that the
2522                  * fb stride matches the fence stride elsewhere.
2523                  */
2524                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2525                     (x + width) * cpp > fb->pitches[i]) {
2526                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2527                                   i, fb->offsets[i]);
2528                         return -EINVAL;
2529                 }
2530
2531                 /*
2532                  * First pixel of the framebuffer from
2533                  * the start of the normal gtt mapping.
2534                  */
2535                 intel_fb->normal[i].x = x;
2536                 intel_fb->normal[i].y = y;
2537
2538                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2539                                                     fb, 0, fb->pitches[i],
2540                                                     DRM_ROTATE_0, tile_size);
2541                 offset /= tile_size;
2542
2543                 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2544                         unsigned int tile_width, tile_height;
2545                         unsigned int pitch_tiles;
2546                         struct drm_rect r;
2547
2548                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2549                                         fb->modifier, cpp);
2550
2551                         rot_info->plane[i].offset = offset;
2552                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2553                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2554                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2555
2556                         intel_fb->rotated[i].pitch =
2557                                 rot_info->plane[i].height * tile_height;
2558
2559                         /* how many tiles does this plane need */
2560                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2561                         /*
2562                          * If the plane isn't horizontally tile aligned,
2563                          * we need one more tile.
2564                          */
2565                         if (x != 0)
2566                                 size++;
2567
2568                         /* rotate the x/y offsets to match the GTT view */
2569                         r.x1 = x;
2570                         r.y1 = y;
2571                         r.x2 = x + width;
2572                         r.y2 = y + height;
2573                         drm_rect_rotate(&r,
2574                                         rot_info->plane[i].width * tile_width,
2575                                         rot_info->plane[i].height * tile_height,
2576                                         DRM_ROTATE_270);
2577                         x = r.x1;
2578                         y = r.y1;
2579
2580                         /* rotate the tile dimensions to match the GTT view */
2581                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2582                         swap(tile_width, tile_height);
2583
2584                         /*
2585                          * We only keep the x/y offsets, so push all of the
2586                          * gtt offset into the x/y offsets.
2587                          */
2588                         _intel_adjust_tile_offset(&x, &y, tile_size,
2589                                                   tile_width, tile_height, pitch_tiles,
2590                                                   gtt_offset_rotated * tile_size, 0);
2591
2592                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2593
2594                         /*
2595                          * First pixel of the framebuffer from
2596                          * the start of the rotated gtt mapping.
2597                          */
2598                         intel_fb->rotated[i].x = x;
2599                         intel_fb->rotated[i].y = y;
2600                 } else {
2601                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2602                                             x * cpp, tile_size);
2603                 }
2604
2605                 /* how many tiles in total needed in the bo */
2606                 max_size = max(max_size, offset + size);
2607         }
2608
2609         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2610                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2611                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2612                 return -EINVAL;
2613         }
2614
2615         return 0;
2616 }
2617
2618 static int i9xx_format_to_fourcc(int format)
2619 {
2620         switch (format) {
2621         case DISPPLANE_8BPP:
2622                 return DRM_FORMAT_C8;
2623         case DISPPLANE_BGRX555:
2624                 return DRM_FORMAT_XRGB1555;
2625         case DISPPLANE_BGRX565:
2626                 return DRM_FORMAT_RGB565;
2627         default:
2628         case DISPPLANE_BGRX888:
2629                 return DRM_FORMAT_XRGB8888;
2630         case DISPPLANE_RGBX888:
2631                 return DRM_FORMAT_XBGR8888;
2632         case DISPPLANE_BGRX101010:
2633                 return DRM_FORMAT_XRGB2101010;
2634         case DISPPLANE_RGBX101010:
2635                 return DRM_FORMAT_XBGR2101010;
2636         }
2637 }
2638
2639 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2640 {
2641         switch (format) {
2642         case PLANE_CTL_FORMAT_RGB_565:
2643                 return DRM_FORMAT_RGB565;
2644         default:
2645         case PLANE_CTL_FORMAT_XRGB_8888:
2646                 if (rgb_order) {
2647                         if (alpha)
2648                                 return DRM_FORMAT_ABGR8888;
2649                         else
2650                                 return DRM_FORMAT_XBGR8888;
2651                 } else {
2652                         if (alpha)
2653                                 return DRM_FORMAT_ARGB8888;
2654                         else
2655                                 return DRM_FORMAT_XRGB8888;
2656                 }
2657         case PLANE_CTL_FORMAT_XRGB_2101010:
2658                 if (rgb_order)
2659                         return DRM_FORMAT_XBGR2101010;
2660                 else
2661                         return DRM_FORMAT_XRGB2101010;
2662         }
2663 }
2664
2665 static bool
2666 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2667                               struct intel_initial_plane_config *plane_config)
2668 {
2669         struct drm_device *dev = crtc->base.dev;
2670         struct drm_i915_private *dev_priv = to_i915(dev);
2671         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2672         struct drm_i915_gem_object *obj = NULL;
2673         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2674         struct drm_framebuffer *fb = &plane_config->fb->base;
2675         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2676         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2677                                     PAGE_SIZE);
2678
2679         size_aligned -= base_aligned;
2680
2681         if (plane_config->size == 0)
2682                 return false;
2683
2684         /* If the FB is too big, just don't use it since fbdev is not very
2685          * important and we should probably use that space with FBC or other
2686          * features. */
2687         if (size_aligned * 2 > ggtt->stolen_usable_size)
2688                 return false;
2689
2690         mutex_lock(&dev->struct_mutex);
2691
2692         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2693                                                              base_aligned,
2694                                                              base_aligned,
2695                                                              size_aligned);
2696         if (!obj) {
2697                 mutex_unlock(&dev->struct_mutex);
2698                 return false;
2699         }
2700
2701         if (plane_config->tiling == I915_TILING_X)
2702                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2703
2704         mode_cmd.pixel_format = fb->pixel_format;
2705         mode_cmd.width = fb->width;
2706         mode_cmd.height = fb->height;
2707         mode_cmd.pitches[0] = fb->pitches[0];
2708         mode_cmd.modifier[0] = fb->modifier;
2709         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2710
2711         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2712                                    &mode_cmd, obj)) {
2713                 DRM_DEBUG_KMS("intel fb init failed\n");
2714                 goto out_unref_obj;
2715         }
2716
2717         mutex_unlock(&dev->struct_mutex);
2718
2719         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2720         return true;
2721
2722 out_unref_obj:
2723         i915_gem_object_put(obj);
2724         mutex_unlock(&dev->struct_mutex);
2725         return false;
2726 }
2727
2728 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2729 static void
2730 update_state_fb(struct drm_plane *plane)
2731 {
2732         if (plane->fb == plane->state->fb)
2733                 return;
2734
2735         if (plane->state->fb)
2736                 drm_framebuffer_unreference(plane->state->fb);
2737         plane->state->fb = plane->fb;
2738         if (plane->state->fb)
2739                 drm_framebuffer_reference(plane->state->fb);
2740 }
2741
2742 static void
2743 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2744                              struct intel_initial_plane_config *plane_config)
2745 {
2746         struct drm_device *dev = intel_crtc->base.dev;
2747         struct drm_i915_private *dev_priv = to_i915(dev);
2748         struct drm_crtc *c;
2749         struct intel_crtc *i;
2750         struct drm_i915_gem_object *obj;
2751         struct drm_plane *primary = intel_crtc->base.primary;
2752         struct drm_plane_state *plane_state = primary->state;
2753         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2754         struct intel_plane *intel_plane = to_intel_plane(primary);
2755         struct intel_plane_state *intel_state =
2756                 to_intel_plane_state(plane_state);
2757         struct drm_framebuffer *fb;
2758
2759         if (!plane_config->fb)
2760                 return;
2761
2762         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2763                 fb = &plane_config->fb->base;
2764                 goto valid_fb;
2765         }
2766
2767         kfree(plane_config->fb);
2768
2769         /*
2770          * Failed to alloc the obj, check to see if we should share
2771          * an fb with another CRTC instead
2772          */
2773         for_each_crtc(dev, c) {
2774                 i = to_intel_crtc(c);
2775
2776                 if (c == &intel_crtc->base)
2777                         continue;
2778
2779                 if (!i->active)
2780                         continue;
2781
2782                 fb = c->primary->fb;
2783                 if (!fb)
2784                         continue;
2785
2786                 obj = intel_fb_obj(fb);
2787                 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2788                         drm_framebuffer_reference(fb);
2789                         goto valid_fb;
2790                 }
2791         }
2792
2793         /*
2794          * We've failed to reconstruct the BIOS FB.  Current display state
2795          * indicates that the primary plane is visible, but has a NULL FB,
2796          * which will lead to problems later if we don't fix it up.  The
2797          * simplest solution is to just disable the primary plane now and
2798          * pretend the BIOS never had it enabled.
2799          */
2800         to_intel_plane_state(plane_state)->base.visible = false;
2801         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2802         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2803         intel_plane->disable_plane(primary, &intel_crtc->base);
2804
2805         return;
2806
2807 valid_fb:
2808         plane_state->src_x = 0;
2809         plane_state->src_y = 0;
2810         plane_state->src_w = fb->width << 16;
2811         plane_state->src_h = fb->height << 16;
2812
2813         plane_state->crtc_x = 0;
2814         plane_state->crtc_y = 0;
2815         plane_state->crtc_w = fb->width;
2816         plane_state->crtc_h = fb->height;
2817
2818         intel_state->base.src = drm_plane_state_src(plane_state);
2819         intel_state->base.dst = drm_plane_state_dest(plane_state);
2820
2821         obj = intel_fb_obj(fb);
2822         if (i915_gem_object_is_tiled(obj))
2823                 dev_priv->preserve_bios_swizzle = true;
2824
2825         drm_framebuffer_reference(fb);
2826         primary->fb = primary->state->fb = fb;
2827         primary->crtc = primary->state->crtc = &intel_crtc->base;
2828         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2829         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2830                   &obj->frontbuffer_bits);
2831 }
2832
2833 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2834                                unsigned int rotation)
2835 {
2836         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2837
2838         switch (fb->modifier) {
2839         case DRM_FORMAT_MOD_NONE:
2840         case I915_FORMAT_MOD_X_TILED:
2841                 switch (cpp) {
2842                 case 8:
2843                         return 4096;
2844                 case 4:
2845                 case 2:
2846                 case 1:
2847                         return 8192;
2848                 default:
2849                         MISSING_CASE(cpp);
2850                         break;
2851                 }
2852                 break;
2853         case I915_FORMAT_MOD_Y_TILED:
2854         case I915_FORMAT_MOD_Yf_TILED:
2855                 switch (cpp) {
2856                 case 8:
2857                         return 2048;
2858                 case 4:
2859                         return 4096;
2860                 case 2:
2861                 case 1:
2862                         return 8192;
2863                 default:
2864                         MISSING_CASE(cpp);
2865                         break;
2866                 }
2867                 break;
2868         default:
2869                 MISSING_CASE(fb->modifier);
2870         }
2871
2872         return 2048;
2873 }
2874
2875 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2876 {
2877         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2878         const struct drm_framebuffer *fb = plane_state->base.fb;
2879         unsigned int rotation = plane_state->base.rotation;
2880         int x = plane_state->base.src.x1 >> 16;
2881         int y = plane_state->base.src.y1 >> 16;
2882         int w = drm_rect_width(&plane_state->base.src) >> 16;
2883         int h = drm_rect_height(&plane_state->base.src) >> 16;
2884         int max_width = skl_max_plane_width(fb, 0, rotation);
2885         int max_height = 4096;
2886         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2887
2888         if (w > max_width || h > max_height) {
2889                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2890                               w, h, max_width, max_height);
2891                 return -EINVAL;
2892         }
2893
2894         intel_add_fb_offsets(&x, &y, plane_state, 0);
2895         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2896
2897         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2898
2899         /*
2900          * AUX surface offset is specified as the distance from the
2901          * main surface offset, and it must be non-negative. Make
2902          * sure that is what we will get.
2903          */
2904         if (offset > aux_offset)
2905                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2906                                                   offset, aux_offset & ~(alignment - 1));
2907
2908         /*
2909          * When using an X-tiled surface, the plane blows up
2910          * if the x offset + width exceed the stride.
2911          *
2912          * TODO: linear and Y-tiled seem fine, Yf untested,
2913          */
2914         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2915                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2916
2917                 while ((x + w) * cpp > fb->pitches[0]) {
2918                         if (offset == 0) {
2919                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2920                                 return -EINVAL;
2921                         }
2922
2923                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2924                                                           offset, offset - alignment);
2925                 }
2926         }
2927
2928         plane_state->main.offset = offset;
2929         plane_state->main.x = x;
2930         plane_state->main.y = y;
2931
2932         return 0;
2933 }
2934
2935 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2936 {
2937         const struct drm_framebuffer *fb = plane_state->base.fb;
2938         unsigned int rotation = plane_state->base.rotation;
2939         int max_width = skl_max_plane_width(fb, 1, rotation);
2940         int max_height = 4096;
2941         int x = plane_state->base.src.x1 >> 17;
2942         int y = plane_state->base.src.y1 >> 17;
2943         int w = drm_rect_width(&plane_state->base.src) >> 17;
2944         int h = drm_rect_height(&plane_state->base.src) >> 17;
2945         u32 offset;
2946
2947         intel_add_fb_offsets(&x, &y, plane_state, 1);
2948         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2949
2950         /* FIXME not quite sure how/if these apply to the chroma plane */
2951         if (w > max_width || h > max_height) {
2952                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2953                               w, h, max_width, max_height);
2954                 return -EINVAL;
2955         }
2956
2957         plane_state->aux.offset = offset;
2958         plane_state->aux.x = x;
2959         plane_state->aux.y = y;
2960
2961         return 0;
2962 }
2963
2964 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2965 {
2966         const struct drm_framebuffer *fb = plane_state->base.fb;
2967         unsigned int rotation = plane_state->base.rotation;
2968         int ret;
2969
2970         /* Rotate src coordinates to match rotated GTT view */
2971         if (drm_rotation_90_or_270(rotation))
2972                 drm_rect_rotate(&plane_state->base.src,
2973                                 fb->width << 16, fb->height << 16,
2974                                 DRM_ROTATE_270);
2975
2976         /*
2977          * Handle the AUX surface first since
2978          * the main surface setup depends on it.
2979          */
2980         if (fb->pixel_format == DRM_FORMAT_NV12) {
2981                 ret = skl_check_nv12_aux_surface(plane_state);
2982                 if (ret)
2983                         return ret;
2984         } else {
2985                 plane_state->aux.offset = ~0xfff;
2986                 plane_state->aux.x = 0;
2987                 plane_state->aux.y = 0;
2988         }
2989
2990         ret = skl_check_main_surface(plane_state);
2991         if (ret)
2992                 return ret;
2993
2994         return 0;
2995 }
2996
2997 static void i9xx_update_primary_plane(struct drm_plane *primary,
2998                                       const struct intel_crtc_state *crtc_state,
2999                                       const struct intel_plane_state *plane_state)
3000 {
3001         struct drm_i915_private *dev_priv = to_i915(primary->dev);
3002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3003         struct drm_framebuffer *fb = plane_state->base.fb;
3004         int plane = intel_crtc->plane;
3005         u32 linear_offset;
3006         u32 dspcntr;
3007         i915_reg_t reg = DSPCNTR(plane);
3008         unsigned int rotation = plane_state->base.rotation;
3009         int x = plane_state->base.src.x1 >> 16;
3010         int y = plane_state->base.src.y1 >> 16;
3011
3012         dspcntr = DISPPLANE_GAMMA_ENABLE;
3013
3014         dspcntr |= DISPLAY_PLANE_ENABLE;
3015
3016         if (INTEL_GEN(dev_priv) < 4) {
3017                 if (intel_crtc->pipe == PIPE_B)
3018                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3019
3020                 /* pipesrc and dspsize control the size that is scaled from,
3021                  * which should always be the user's requested size.
3022                  */
3023                 I915_WRITE(DSPSIZE(plane),
3024                            ((crtc_state->pipe_src_h - 1) << 16) |
3025                            (crtc_state->pipe_src_w - 1));
3026                 I915_WRITE(DSPPOS(plane), 0);
3027         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3028                 I915_WRITE(PRIMSIZE(plane),
3029                            ((crtc_state->pipe_src_h - 1) << 16) |
3030                            (crtc_state->pipe_src_w - 1));
3031                 I915_WRITE(PRIMPOS(plane), 0);
3032                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3033         }
3034
3035         switch (fb->pixel_format) {
3036         case DRM_FORMAT_C8:
3037                 dspcntr |= DISPPLANE_8BPP;
3038                 break;
3039         case DRM_FORMAT_XRGB1555:
3040                 dspcntr |= DISPPLANE_BGRX555;
3041                 break;
3042         case DRM_FORMAT_RGB565:
3043                 dspcntr |= DISPPLANE_BGRX565;
3044                 break;
3045         case DRM_FORMAT_XRGB8888:
3046                 dspcntr |= DISPPLANE_BGRX888;
3047                 break;
3048         case DRM_FORMAT_XBGR8888:
3049                 dspcntr |= DISPPLANE_RGBX888;
3050                 break;
3051         case DRM_FORMAT_XRGB2101010:
3052                 dspcntr |= DISPPLANE_BGRX101010;
3053                 break;
3054         case DRM_FORMAT_XBGR2101010:
3055                 dspcntr |= DISPPLANE_RGBX101010;
3056                 break;
3057         default:
3058                 BUG();
3059         }
3060
3061         if (INTEL_GEN(dev_priv) >= 4 &&
3062             fb->modifier == I915_FORMAT_MOD_X_TILED)
3063                 dspcntr |= DISPPLANE_TILED;
3064
3065         if (rotation & DRM_ROTATE_180)
3066                 dspcntr |= DISPPLANE_ROTATE_180;
3067
3068         if (rotation & DRM_REFLECT_X)
3069                 dspcntr |= DISPPLANE_MIRROR;
3070
3071         if (IS_G4X(dev_priv))
3072                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3073
3074         intel_add_fb_offsets(&x, &y, plane_state, 0);
3075
3076         if (INTEL_GEN(dev_priv) >= 4)
3077                 intel_crtc->dspaddr_offset =
3078                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3079
3080         if (rotation & DRM_ROTATE_180) {
3081                 x += crtc_state->pipe_src_w - 1;
3082                 y += crtc_state->pipe_src_h - 1;
3083         } else if (rotation & DRM_REFLECT_X) {
3084                 x += crtc_state->pipe_src_w - 1;
3085         }
3086
3087         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3088
3089         if (INTEL_GEN(dev_priv) < 4)
3090                 intel_crtc->dspaddr_offset = linear_offset;
3091
3092         intel_crtc->adjusted_x = x;
3093         intel_crtc->adjusted_y = y;
3094
3095         I915_WRITE(reg, dspcntr);
3096
3097         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3098         if (INTEL_GEN(dev_priv) >= 4) {
3099                 I915_WRITE(DSPSURF(plane),
3100                            intel_fb_gtt_offset(fb, rotation) +
3101                            intel_crtc->dspaddr_offset);
3102                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3103                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3104         } else {
3105                 I915_WRITE(DSPADDR(plane),
3106                            intel_fb_gtt_offset(fb, rotation) +
3107                            intel_crtc->dspaddr_offset);
3108         }
3109         POSTING_READ(reg);
3110 }
3111
3112 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3113                                        struct drm_crtc *crtc)
3114 {
3115         struct drm_device *dev = crtc->dev;
3116         struct drm_i915_private *dev_priv = to_i915(dev);
3117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3118         int plane = intel_crtc->plane;
3119
3120         I915_WRITE(DSPCNTR(plane), 0);
3121         if (INTEL_INFO(dev_priv)->gen >= 4)
3122                 I915_WRITE(DSPSURF(plane), 0);
3123         else
3124                 I915_WRITE(DSPADDR(plane), 0);
3125         POSTING_READ(DSPCNTR(plane));
3126 }
3127
3128 static void ironlake_update_primary_plane(struct drm_plane *primary,
3129                                           const struct intel_crtc_state *crtc_state,
3130                                           const struct intel_plane_state *plane_state)
3131 {
3132         struct drm_device *dev = primary->dev;
3133         struct drm_i915_private *dev_priv = to_i915(dev);
3134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3135         struct drm_framebuffer *fb = plane_state->base.fb;
3136         int plane = intel_crtc->plane;
3137         u32 linear_offset;
3138         u32 dspcntr;
3139         i915_reg_t reg = DSPCNTR(plane);
3140         unsigned int rotation = plane_state->base.rotation;
3141         int x = plane_state->base.src.x1 >> 16;
3142         int y = plane_state->base.src.y1 >> 16;
3143
3144         dspcntr = DISPPLANE_GAMMA_ENABLE;
3145         dspcntr |= DISPLAY_PLANE_ENABLE;
3146
3147         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3148                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3149
3150         switch (fb->pixel_format) {
3151         case DRM_FORMAT_C8:
3152                 dspcntr |= DISPPLANE_8BPP;
3153                 break;
3154         case DRM_FORMAT_RGB565:
3155                 dspcntr |= DISPPLANE_BGRX565;
3156                 break;
3157         case DRM_FORMAT_XRGB8888:
3158                 dspcntr |= DISPPLANE_BGRX888;
3159                 break;
3160         case DRM_FORMAT_XBGR8888:
3161                 dspcntr |= DISPPLANE_RGBX888;
3162                 break;
3163         case DRM_FORMAT_XRGB2101010:
3164                 dspcntr |= DISPPLANE_BGRX101010;
3165                 break;
3166         case DRM_FORMAT_XBGR2101010:
3167                 dspcntr |= DISPPLANE_RGBX101010;
3168                 break;
3169         default:
3170                 BUG();
3171         }
3172
3173         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3174                 dspcntr |= DISPPLANE_TILED;
3175
3176         if (rotation & DRM_ROTATE_180)
3177                 dspcntr |= DISPPLANE_ROTATE_180;
3178
3179         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3180                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3181
3182         intel_add_fb_offsets(&x, &y, plane_state, 0);
3183
3184         intel_crtc->dspaddr_offset =
3185                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3186
3187         /* HSW+ does this automagically in hardware */
3188         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3189             rotation & DRM_ROTATE_180) {
3190                 x += crtc_state->pipe_src_w - 1;
3191                 y += crtc_state->pipe_src_h - 1;
3192         }
3193
3194         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3195
3196         intel_crtc->adjusted_x = x;
3197         intel_crtc->adjusted_y = y;
3198
3199         I915_WRITE(reg, dspcntr);
3200
3201         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3202         I915_WRITE(DSPSURF(plane),
3203                    intel_fb_gtt_offset(fb, rotation) +
3204                    intel_crtc->dspaddr_offset);
3205         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3206                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3207         } else {
3208                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3209                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3210         }
3211         POSTING_READ(reg);
3212 }
3213
3214 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3215                               uint64_t fb_modifier, uint32_t pixel_format)
3216 {
3217         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3218                 return 64;
3219         } else {
3220                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3221
3222                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3223         }
3224 }
3225
3226 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3227                         unsigned int rotation)
3228 {
3229         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3230         struct i915_ggtt_view view;
3231         struct i915_vma *vma;
3232
3233         intel_fill_fb_ggtt_view(&view, fb, rotation);
3234
3235         vma = i915_gem_object_to_ggtt(obj, &view);
3236         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3237                  view.type))
3238                 return -1;
3239
3240         return i915_ggtt_offset(vma);
3241 }
3242
3243 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3244 {
3245         struct drm_device *dev = intel_crtc->base.dev;
3246         struct drm_i915_private *dev_priv = to_i915(dev);
3247
3248         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3249         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3250         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3251 }
3252
3253 /*
3254  * This function detaches (aka. unbinds) unused scalers in hardware
3255  */
3256 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3257 {
3258         struct intel_crtc_scaler_state *scaler_state;
3259         int i;
3260
3261         scaler_state = &intel_crtc->config->scaler_state;
3262
3263         /* loop through and disable scalers that aren't in use */
3264         for (i = 0; i < intel_crtc->num_scalers; i++) {
3265                 if (!scaler_state->scalers[i].in_use)
3266                         skl_detach_scaler(intel_crtc, i);
3267         }
3268 }
3269
3270 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3271                      unsigned int rotation)
3272 {
3273         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3274         u32 stride = intel_fb_pitch(fb, plane, rotation);
3275
3276         /*
3277          * The stride is either expressed as a multiple of 64 bytes chunks for
3278          * linear buffers or in number of tiles for tiled buffers.
3279          */
3280         if (drm_rotation_90_or_270(rotation)) {
3281                 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3282
3283                 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
3284         } else {
3285                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
3286                                                     fb->pixel_format);
3287         }
3288
3289         return stride;
3290 }
3291
3292 u32 skl_plane_ctl_format(uint32_t pixel_format)
3293 {
3294         switch (pixel_format) {
3295         case DRM_FORMAT_C8:
3296                 return PLANE_CTL_FORMAT_INDEXED;
3297         case DRM_FORMAT_RGB565:
3298                 return PLANE_CTL_FORMAT_RGB_565;
3299         case DRM_FORMAT_XBGR8888:
3300                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3301         case DRM_FORMAT_XRGB8888:
3302                 return PLANE_CTL_FORMAT_XRGB_8888;
3303         /*
3304          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3305          * to be already pre-multiplied. We need to add a knob (or a different
3306          * DRM_FORMAT) for user-space to configure that.
3307          */
3308         case DRM_FORMAT_ABGR8888:
3309                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3310                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3311         case DRM_FORMAT_ARGB8888:
3312                 return PLANE_CTL_FORMAT_XRGB_8888 |
3313                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3314         case DRM_FORMAT_XRGB2101010:
3315                 return PLANE_CTL_FORMAT_XRGB_2101010;
3316         case DRM_FORMAT_XBGR2101010:
3317                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3318         case DRM_FORMAT_YUYV:
3319                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3320         case DRM_FORMAT_YVYU:
3321                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3322         case DRM_FORMAT_UYVY:
3323                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3324         case DRM_FORMAT_VYUY:
3325                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3326         default:
3327                 MISSING_CASE(pixel_format);
3328         }
3329
3330         return 0;
3331 }
3332
3333 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3334 {
3335         switch (fb_modifier) {
3336         case DRM_FORMAT_MOD_NONE:
3337                 break;
3338         case I915_FORMAT_MOD_X_TILED:
3339                 return PLANE_CTL_TILED_X;
3340         case I915_FORMAT_MOD_Y_TILED:
3341                 return PLANE_CTL_TILED_Y;
3342         case I915_FORMAT_MOD_Yf_TILED:
3343                 return PLANE_CTL_TILED_YF;
3344         default:
3345                 MISSING_CASE(fb_modifier);
3346         }
3347
3348         return 0;
3349 }
3350
3351 u32 skl_plane_ctl_rotation(unsigned int rotation)
3352 {
3353         switch (rotation) {
3354         case DRM_ROTATE_0:
3355                 break;
3356         /*
3357          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3358          * while i915 HW rotation is clockwise, thats why this swapping.
3359          */
3360         case DRM_ROTATE_90:
3361                 return PLANE_CTL_ROTATE_270;
3362         case DRM_ROTATE_180:
3363                 return PLANE_CTL_ROTATE_180;
3364         case DRM_ROTATE_270:
3365                 return PLANE_CTL_ROTATE_90;
3366         default:
3367                 MISSING_CASE(rotation);
3368         }
3369
3370         return 0;
3371 }
3372
3373 static void skylake_update_primary_plane(struct drm_plane *plane,
3374                                          const struct intel_crtc_state *crtc_state,
3375                                          const struct intel_plane_state *plane_state)
3376 {
3377         struct drm_device *dev = plane->dev;
3378         struct drm_i915_private *dev_priv = to_i915(dev);
3379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3380         struct drm_framebuffer *fb = plane_state->base.fb;
3381         enum plane_id plane_id = to_intel_plane(plane)->id;
3382         enum pipe pipe = to_intel_plane(plane)->pipe;
3383         u32 plane_ctl;
3384         unsigned int rotation = plane_state->base.rotation;
3385         u32 stride = skl_plane_stride(fb, 0, rotation);
3386         u32 surf_addr = plane_state->main.offset;
3387         int scaler_id = plane_state->scaler_id;
3388         int src_x = plane_state->main.x;
3389         int src_y = plane_state->main.y;
3390         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3391         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3392         int dst_x = plane_state->base.dst.x1;
3393         int dst_y = plane_state->base.dst.y1;
3394         int dst_w = drm_rect_width(&plane_state->base.dst);
3395         int dst_h = drm_rect_height(&plane_state->base.dst);
3396
3397         plane_ctl = PLANE_CTL_ENABLE |
3398                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3399                     PLANE_CTL_PIPE_CSC_ENABLE;
3400
3401         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3402         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3403         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3404         plane_ctl |= skl_plane_ctl_rotation(rotation);
3405
3406         /* Sizes are 0 based */
3407         src_w--;
3408         src_h--;
3409         dst_w--;
3410         dst_h--;
3411
3412         intel_crtc->dspaddr_offset = surf_addr;
3413
3414         intel_crtc->adjusted_x = src_x;
3415         intel_crtc->adjusted_y = src_y;
3416
3417         I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
3418         I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3419         I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
3420         I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3421
3422         if (scaler_id >= 0) {
3423                 uint32_t ps_ctrl = 0;
3424
3425                 WARN_ON(!dst_w || !dst_h);
3426                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3427                         crtc_state->scaler_state.scalers[scaler_id].mode;
3428                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3429                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3430                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3431                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3432                 I915_WRITE(PLANE_POS(pipe, plane_id), 0);
3433         } else {
3434                 I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3435         }
3436
3437         I915_WRITE(PLANE_SURF(pipe, plane_id),
3438                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
3439
3440         POSTING_READ(PLANE_SURF(pipe, plane_id));
3441 }
3442
3443 static void skylake_disable_primary_plane(struct drm_plane *primary,
3444                                           struct drm_crtc *crtc)
3445 {
3446         struct drm_device *dev = crtc->dev;
3447         struct drm_i915_private *dev_priv = to_i915(dev);
3448         enum plane_id plane_id = to_intel_plane(primary)->id;
3449         enum pipe pipe = to_intel_plane(primary)->pipe;
3450
3451         I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
3452         I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
3453         POSTING_READ(PLANE_SURF(pipe, plane_id));
3454 }
3455
3456 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3457 static int
3458 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3459                            int x, int y, enum mode_set_atomic state)
3460 {
3461         /* Support for kgdboc is disabled, this needs a major rework. */
3462         DRM_ERROR("legacy panic handler not supported any more.\n");
3463
3464         return -ENODEV;
3465 }
3466
3467 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3468 {
3469         struct intel_crtc *crtc;
3470
3471         for_each_intel_crtc(&dev_priv->drm, crtc)
3472                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3473 }
3474
3475 static void intel_update_primary_planes(struct drm_device *dev)
3476 {
3477         struct drm_crtc *crtc;
3478
3479         for_each_crtc(dev, crtc) {
3480                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3481                 struct intel_plane_state *plane_state =
3482                         to_intel_plane_state(plane->base.state);
3483
3484                 if (plane_state->base.visible)
3485                         plane->update_plane(&plane->base,
3486                                             to_intel_crtc_state(crtc->state),
3487                                             plane_state);
3488         }
3489 }
3490
3491 static int
3492 __intel_display_resume(struct drm_device *dev,
3493                        struct drm_atomic_state *state)
3494 {
3495         struct drm_crtc_state *crtc_state;
3496         struct drm_crtc *crtc;
3497         int i, ret;
3498
3499         intel_modeset_setup_hw_state(dev);
3500         i915_redisable_vga(to_i915(dev));
3501
3502         if (!state)
3503                 return 0;
3504
3505         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3506                 /*
3507                  * Force recalculation even if we restore
3508                  * current state. With fast modeset this may not result
3509                  * in a modeset when the state is compatible.
3510                  */
3511                 crtc_state->mode_changed = true;
3512         }
3513
3514         /* ignore any reset values/BIOS leftovers in the WM registers */
3515         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3516
3517         ret = drm_atomic_commit(state);
3518
3519         WARN_ON(ret == -EDEADLK);
3520         return ret;
3521 }
3522
3523 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3524 {
3525         return intel_has_gpu_reset(dev_priv) &&
3526                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3527 }
3528
3529 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3530 {
3531         struct drm_device *dev = &dev_priv->drm;
3532         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3533         struct drm_atomic_state *state;
3534         int ret;
3535
3536         /*
3537          * Need mode_config.mutex so that we don't
3538          * trample ongoing ->detect() and whatnot.
3539          */
3540         mutex_lock(&dev->mode_config.mutex);
3541         drm_modeset_acquire_init(ctx, 0);
3542         while (1) {
3543                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3544                 if (ret != -EDEADLK)
3545                         break;
3546
3547                 drm_modeset_backoff(ctx);
3548         }
3549
3550         /* reset doesn't touch the display, but flips might get nuked anyway, */
3551         if (!i915.force_reset_modeset_test &&
3552             !gpu_reset_clobbers_display(dev_priv))
3553                 return;
3554
3555         /*
3556          * Disabling the crtcs gracefully seems nicer. Also the
3557          * g33 docs say we should at least disable all the planes.
3558          */
3559         state = drm_atomic_helper_duplicate_state(dev, ctx);
3560         if (IS_ERR(state)) {
3561                 ret = PTR_ERR(state);
3562                 state = NULL;
3563                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3564                 goto err;
3565         }
3566
3567         ret = drm_atomic_helper_disable_all(dev, ctx);
3568         if (ret) {
3569                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3570                 goto err;
3571         }
3572
3573         dev_priv->modeset_restore_state = state;
3574         state->acquire_ctx = ctx;
3575         return;
3576
3577 err:
3578         drm_atomic_state_put(state);
3579 }
3580
3581 void intel_finish_reset(struct drm_i915_private *dev_priv)
3582 {
3583         struct drm_device *dev = &dev_priv->drm;
3584         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3585         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3586         int ret;
3587
3588         /*
3589          * Flips in the rings will be nuked by the reset,
3590          * so complete all pending flips so that user space
3591          * will get its events and not get stuck.
3592          */
3593         intel_complete_page_flips(dev_priv);
3594
3595         dev_priv->modeset_restore_state = NULL;
3596
3597         /* reset doesn't touch the display */
3598         if (!gpu_reset_clobbers_display(dev_priv)) {
3599                 if (!state) {
3600                         /*
3601                          * Flips in the rings have been nuked by the reset,
3602                          * so update the base address of all primary
3603                          * planes to the the last fb to make sure we're
3604                          * showing the correct fb after a reset.
3605                          *
3606                          * FIXME: Atomic will make this obsolete since we won't schedule
3607                          * CS-based flips (which might get lost in gpu resets) any more.
3608                          */
3609                         intel_update_primary_planes(dev);
3610                 } else {
3611                         ret = __intel_display_resume(dev, state);
3612                         if (ret)
3613                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3614                 }
3615         } else {
3616                 /*
3617                  * The display has been reset as well,
3618                  * so need a full re-initialization.
3619                  */
3620                 intel_runtime_pm_disable_interrupts(dev_priv);
3621                 intel_runtime_pm_enable_interrupts(dev_priv);
3622
3623                 intel_pps_unlock_regs_wa(dev_priv);
3624                 intel_modeset_init_hw(dev);
3625
3626                 spin_lock_irq(&dev_priv->irq_lock);
3627                 if (dev_priv->display.hpd_irq_setup)
3628                         dev_priv->display.hpd_irq_setup(dev_priv);
3629                 spin_unlock_irq(&dev_priv->irq_lock);
3630
3631                 ret = __intel_display_resume(dev, state);
3632                 if (ret)
3633                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3634
3635                 intel_hpd_init(dev_priv);
3636         }
3637
3638         if (state)
3639                 drm_atomic_state_put(state);
3640         drm_modeset_drop_locks(ctx);
3641         drm_modeset_acquire_fini(ctx);
3642         mutex_unlock(&dev->mode_config.mutex);
3643 }
3644
3645 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3646 {
3647         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3648
3649         if (i915_reset_in_progress(error))
3650                 return true;
3651
3652         if (crtc->reset_count != i915_reset_count(error))
3653                 return true;
3654
3655         return false;
3656 }
3657
3658 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3659 {
3660         struct drm_device *dev = crtc->dev;
3661         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3662         bool pending;
3663
3664         if (abort_flip_on_reset(intel_crtc))
3665                 return false;
3666
3667         spin_lock_irq(&dev->event_lock);
3668         pending = to_intel_crtc(crtc)->flip_work != NULL;
3669         spin_unlock_irq(&dev->event_lock);
3670
3671         return pending;
3672 }
3673
3674 static void intel_update_pipe_config(struct intel_crtc *crtc,
3675                                      struct intel_crtc_state *old_crtc_state)
3676 {
3677         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3678         struct intel_crtc_state *pipe_config =
3679                 to_intel_crtc_state(crtc->base.state);
3680
3681         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3682         crtc->base.mode = crtc->base.state->mode;
3683
3684         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3685                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3686                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3687
3688         /*
3689          * Update pipe size and adjust fitter if needed: the reason for this is
3690          * that in compute_mode_changes we check the native mode (not the pfit
3691          * mode) to see if we can flip rather than do a full mode set. In the
3692          * fastboot case, we'll flip, but if we don't update the pipesrc and
3693          * pfit state, we'll end up with a big fb scanned out into the wrong
3694          * sized surface.
3695          */
3696
3697         I915_WRITE(PIPESRC(crtc->pipe),
3698                    ((pipe_config->pipe_src_w - 1) << 16) |
3699                    (pipe_config->pipe_src_h - 1));
3700
3701         /* on skylake this is done by detaching scalers */
3702         if (INTEL_GEN(dev_priv) >= 9) {
3703                 skl_detach_scalers(crtc);
3704
3705                 if (pipe_config->pch_pfit.enabled)
3706                         skylake_pfit_enable(crtc);
3707         } else if (HAS_PCH_SPLIT(dev_priv)) {
3708                 if (pipe_config->pch_pfit.enabled)
3709                         ironlake_pfit_enable(crtc);
3710                 else if (old_crtc_state->pch_pfit.enabled)
3711                         ironlake_pfit_disable(crtc, true);
3712         }
3713 }
3714
3715 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3716 {
3717         struct drm_device *dev = crtc->dev;
3718         struct drm_i915_private *dev_priv = to_i915(dev);
3719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3720         int pipe = intel_crtc->pipe;
3721         i915_reg_t reg;
3722         u32 temp;
3723
3724         /* enable normal train */
3725         reg = FDI_TX_CTL(pipe);
3726         temp = I915_READ(reg);
3727         if (IS_IVYBRIDGE(dev_priv)) {
3728                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3729                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3730         } else {
3731                 temp &= ~FDI_LINK_TRAIN_NONE;
3732                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3733         }
3734         I915_WRITE(reg, temp);
3735
3736         reg = FDI_RX_CTL(pipe);
3737         temp = I915_READ(reg);
3738         if (HAS_PCH_CPT(dev_priv)) {
3739                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3740                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3741         } else {
3742                 temp &= ~FDI_LINK_TRAIN_NONE;
3743                 temp |= FDI_LINK_TRAIN_NONE;
3744         }
3745         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3746
3747         /* wait one idle pattern time */
3748         POSTING_READ(reg);
3749         udelay(1000);
3750
3751         /* IVB wants error correction enabled */
3752         if (IS_IVYBRIDGE(dev_priv))
3753                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3754                            FDI_FE_ERRC_ENABLE);
3755 }
3756
3757 /* The FDI link training functions for ILK/Ibexpeak. */
3758 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3759 {
3760         struct drm_device *dev = crtc->dev;
3761         struct drm_i915_private *dev_priv = to_i915(dev);
3762         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3763         int pipe = intel_crtc->pipe;
3764         i915_reg_t reg;
3765         u32 temp, tries;
3766
3767         /* FDI needs bits from pipe first */
3768         assert_pipe_enabled(dev_priv, pipe);
3769
3770         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3771            for train result */
3772         reg = FDI_RX_IMR(pipe);
3773         temp = I915_READ(reg);
3774         temp &= ~FDI_RX_SYMBOL_LOCK;
3775         temp &= ~FDI_RX_BIT_LOCK;
3776         I915_WRITE(reg, temp);
3777         I915_READ(reg);
3778         udelay(150);
3779
3780         /* enable CPU FDI TX and PCH FDI RX */
3781         reg = FDI_TX_CTL(pipe);
3782         temp = I915_READ(reg);
3783         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3784         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3785         temp &= ~FDI_LINK_TRAIN_NONE;
3786         temp |= FDI_LINK_TRAIN_PATTERN_1;
3787         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3788
3789         reg = FDI_RX_CTL(pipe);
3790         temp = I915_READ(reg);
3791         temp &= ~FDI_LINK_TRAIN_NONE;
3792         temp |= FDI_LINK_TRAIN_PATTERN_1;
3793         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3794
3795         POSTING_READ(reg);
3796         udelay(150);
3797
3798         /* Ironlake workaround, enable clock pointer after FDI enable*/
3799         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3800         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3801                    FDI_RX_PHASE_SYNC_POINTER_EN);
3802
3803         reg = FDI_RX_IIR(pipe);
3804         for (tries = 0; tries < 5; tries++) {
3805                 temp = I915_READ(reg);
3806                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3807
3808                 if ((temp & FDI_RX_BIT_LOCK)) {
3809                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3810                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3811                         break;
3812                 }
3813         }
3814         if (tries == 5)
3815                 DRM_ERROR("FDI train 1 fail!\n");
3816
3817         /* Train 2 */
3818         reg = FDI_TX_CTL(pipe);
3819         temp = I915_READ(reg);
3820         temp &= ~FDI_LINK_TRAIN_NONE;
3821         temp |= FDI_LINK_TRAIN_PATTERN_2;
3822         I915_WRITE(reg, temp);
3823
3824         reg = FDI_RX_CTL(pipe);
3825         temp = I915_READ(reg);
3826         temp &= ~FDI_LINK_TRAIN_NONE;
3827         temp |= FDI_LINK_TRAIN_PATTERN_2;
3828         I915_WRITE(reg, temp);
3829
3830         POSTING_READ(reg);
3831         udelay(150);
3832
3833         reg = FDI_RX_IIR(pipe);
3834         for (tries = 0; tries < 5; tries++) {
3835                 temp = I915_READ(reg);
3836                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3837
3838                 if (temp & FDI_RX_SYMBOL_LOCK) {
3839                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3840                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3841                         break;
3842                 }
3843         }
3844         if (tries == 5)
3845                 DRM_ERROR("FDI train 2 fail!\n");
3846
3847         DRM_DEBUG_KMS("FDI train done\n");
3848
3849 }
3850
3851 static const int snb_b_fdi_train_param[] = {
3852         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3853         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3854         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3855         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3856 };
3857
3858 /* The FDI link training functions for SNB/Cougarpoint. */
3859 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3860 {
3861         struct drm_device *dev = crtc->dev;
3862         struct drm_i915_private *dev_priv = to_i915(dev);
3863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3864         int pipe = intel_crtc->pipe;
3865         i915_reg_t reg;
3866         u32 temp, i, retry;
3867
3868         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3869            for train result */
3870         reg = FDI_RX_IMR(pipe);
3871         temp = I915_READ(reg);
3872         temp &= ~FDI_RX_SYMBOL_LOCK;
3873         temp &= ~FDI_RX_BIT_LOCK;
3874         I915_WRITE(reg, temp);
3875
3876         POSTING_READ(reg);
3877         udelay(150);
3878
3879         /* enable CPU FDI TX and PCH FDI RX */
3880         reg = FDI_TX_CTL(pipe);
3881         temp = I915_READ(reg);
3882         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3883         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3884         temp &= ~FDI_LINK_TRAIN_NONE;
3885         temp |= FDI_LINK_TRAIN_PATTERN_1;
3886         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3887         /* SNB-B */
3888         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3889         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3890
3891         I915_WRITE(FDI_RX_MISC(pipe),
3892                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3893
3894         reg = FDI_RX_CTL(pipe);
3895         temp = I915_READ(reg);
3896         if (HAS_PCH_CPT(dev_priv)) {
3897                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3898                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3899         } else {
3900                 temp &= ~FDI_LINK_TRAIN_NONE;
3901                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3902         }
3903         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3904
3905         POSTING_READ(reg);
3906         udelay(150);
3907
3908         for (i = 0; i < 4; i++) {
3909                 reg = FDI_TX_CTL(pipe);
3910                 temp = I915_READ(reg);
3911                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3912                 temp |= snb_b_fdi_train_param[i];
3913                 I915_WRITE(reg, temp);
3914
3915                 POSTING_READ(reg);
3916                 udelay(500);
3917
3918                 for (retry = 0; retry < 5; retry++) {
3919                         reg = FDI_RX_IIR(pipe);
3920                         temp = I915_READ(reg);
3921                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3922                         if (temp & FDI_RX_BIT_LOCK) {
3923                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3924                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3925                                 break;
3926                         }
3927                         udelay(50);
3928                 }
3929                 if (retry < 5)
3930                         break;
3931         }
3932         if (i == 4)
3933                 DRM_ERROR("FDI train 1 fail!\n");
3934
3935         /* Train 2 */
3936         reg = FDI_TX_CTL(pipe);
3937         temp = I915_READ(reg);
3938         temp &= ~FDI_LINK_TRAIN_NONE;
3939         temp |= FDI_LINK_TRAIN_PATTERN_2;
3940         if (IS_GEN6(dev_priv)) {
3941                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3942                 /* SNB-B */
3943                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3944         }
3945         I915_WRITE(reg, temp);
3946
3947         reg = FDI_RX_CTL(pipe);
3948         temp = I915_READ(reg);
3949         if (HAS_PCH_CPT(dev_priv)) {
3950                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3951                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3952         } else {
3953                 temp &= ~FDI_LINK_TRAIN_NONE;
3954                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3955         }
3956         I915_WRITE(reg, temp);
3957
3958         POSTING_READ(reg);
3959         udelay(150);
3960
3961         for (i = 0; i < 4; i++) {
3962                 reg = FDI_TX_CTL(pipe);
3963                 temp = I915_READ(reg);
3964                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3965                 temp |= snb_b_fdi_train_param[i];
3966                 I915_WRITE(reg, temp);
3967
3968                 POSTING_READ(reg);
3969                 udelay(500);
3970
3971                 for (retry = 0; retry < 5; retry++) {
3972                         reg = FDI_RX_IIR(pipe);
3973                         temp = I915_READ(reg);
3974                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3975                         if (temp & FDI_RX_SYMBOL_LOCK) {
3976                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3977                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3978                                 break;
3979                         }
3980                         udelay(50);
3981                 }
3982                 if (retry < 5)
3983                         break;
3984         }
3985         if (i == 4)
3986                 DRM_ERROR("FDI train 2 fail!\n");
3987
3988         DRM_DEBUG_KMS("FDI train done.\n");
3989 }
3990
3991 /* Manual link training for Ivy Bridge A0 parts */
3992 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3993 {
3994         struct drm_device *dev = crtc->dev;
3995         struct drm_i915_private *dev_priv = to_i915(dev);
3996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3997         int pipe = intel_crtc->pipe;
3998         i915_reg_t reg;
3999         u32 temp, i, j;
4000
4001         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4002            for train result */
4003         reg = FDI_RX_IMR(pipe);
4004         temp = I915_READ(reg);
4005         temp &= ~FDI_RX_SYMBOL_LOCK;
4006         temp &= ~FDI_RX_BIT_LOCK;
4007         I915_WRITE(reg, temp);
4008
4009         POSTING_READ(reg);
4010         udelay(150);
4011
4012         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4013                       I915_READ(FDI_RX_IIR(pipe)));
4014
4015         /* Try each vswing and preemphasis setting twice before moving on */
4016         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4017                 /* disable first in case we need to retry */
4018                 reg = FDI_TX_CTL(pipe);
4019                 temp = I915_READ(reg);
4020                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4021                 temp &= ~FDI_TX_ENABLE;
4022                 I915_WRITE(reg, temp);
4023
4024                 reg = FDI_RX_CTL(pipe);
4025                 temp = I915_READ(reg);
4026                 temp &= ~FDI_LINK_TRAIN_AUTO;
4027                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4028                 temp &= ~FDI_RX_ENABLE;
4029                 I915_WRITE(reg, temp);
4030
4031                 /* enable CPU FDI TX and PCH FDI RX */
4032                 reg = FDI_TX_CTL(pipe);
4033                 temp = I915_READ(reg);
4034                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4035                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4036                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4037                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4038                 temp |= snb_b_fdi_train_param[j/2];
4039                 temp |= FDI_COMPOSITE_SYNC;
4040                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4041
4042                 I915_WRITE(FDI_RX_MISC(pipe),
4043                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4044
4045                 reg = FDI_RX_CTL(pipe);
4046                 temp = I915_READ(reg);
4047                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4048                 temp |= FDI_COMPOSITE_SYNC;
4049                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4050
4051                 POSTING_READ(reg);
4052                 udelay(1); /* should be 0.5us */
4053
4054                 for (i = 0; i < 4; i++) {
4055                         reg = FDI_RX_IIR(pipe);
4056                         temp = I915_READ(reg);
4057                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4058
4059                         if (temp & FDI_RX_BIT_LOCK ||
4060                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4061                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4062                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4063                                               i);
4064                                 break;
4065                         }
4066                         udelay(1); /* should be 0.5us */
4067                 }
4068                 if (i == 4) {
4069                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4070                         continue;
4071                 }
4072
4073                 /* Train 2 */
4074                 reg = FDI_TX_CTL(pipe);
4075                 temp = I915_READ(reg);
4076                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4077                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4078                 I915_WRITE(reg, temp);
4079
4080                 reg = FDI_RX_CTL(pipe);
4081                 temp = I915_READ(reg);
4082                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4083                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4084                 I915_WRITE(reg, temp);
4085
4086                 POSTING_READ(reg);
4087                 udelay(2); /* should be 1.5us */
4088
4089                 for (i = 0; i < 4; i++) {
4090                         reg = FDI_RX_IIR(pipe);
4091                         temp = I915_READ(reg);
4092                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4093
4094                         if (temp & FDI_RX_SYMBOL_LOCK ||
4095                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4096                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4097                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4098                                               i);
4099                                 goto train_done;
4100                         }
4101                         udelay(2); /* should be 1.5us */
4102                 }
4103                 if (i == 4)
4104                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4105         }
4106
4107 train_done:
4108         DRM_DEBUG_KMS("FDI train done.\n");
4109 }
4110
4111 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4112 {
4113         struct drm_device *dev = intel_crtc->base.dev;
4114         struct drm_i915_private *dev_priv = to_i915(dev);
4115         int pipe = intel_crtc->pipe;
4116         i915_reg_t reg;
4117         u32 temp;
4118
4119         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4120         reg = FDI_RX_CTL(pipe);
4121         temp = I915_READ(reg);
4122         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4123         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4124         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4125         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4126
4127         POSTING_READ(reg);
4128         udelay(200);
4129
4130         /* Switch from Rawclk to PCDclk */
4131         temp = I915_READ(reg);
4132         I915_WRITE(reg, temp | FDI_PCDCLK);
4133
4134         POSTING_READ(reg);
4135         udelay(200);
4136
4137         /* Enable CPU FDI TX PLL, always on for Ironlake */
4138         reg = FDI_TX_CTL(pipe);
4139         temp = I915_READ(reg);
4140         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4141                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4142
4143                 POSTING_READ(reg);
4144                 udelay(100);
4145         }
4146 }
4147
4148 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4149 {
4150         struct drm_device *dev = intel_crtc->base.dev;
4151         struct drm_i915_private *dev_priv = to_i915(dev);
4152         int pipe = intel_crtc->pipe;
4153         i915_reg_t reg;
4154         u32 temp;
4155
4156         /* Switch from PCDclk to Rawclk */
4157         reg = FDI_RX_CTL(pipe);
4158         temp = I915_READ(reg);
4159         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4160
4161         /* Disable CPU FDI TX PLL */
4162         reg = FDI_TX_CTL(pipe);
4163         temp = I915_READ(reg);
4164         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4165
4166         POSTING_READ(reg);
4167         udelay(100);
4168
4169         reg = FDI_RX_CTL(pipe);
4170         temp = I915_READ(reg);
4171         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4172
4173         /* Wait for the clocks to turn off. */
4174         POSTING_READ(reg);
4175         udelay(100);
4176 }
4177
4178 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4179 {
4180         struct drm_device *dev = crtc->dev;
4181         struct drm_i915_private *dev_priv = to_i915(dev);
4182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4183         int pipe = intel_crtc->pipe;
4184         i915_reg_t reg;
4185         u32 temp;
4186
4187         /* disable CPU FDI tx and PCH FDI rx */
4188         reg = FDI_TX_CTL(pipe);
4189         temp = I915_READ(reg);
4190         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4191         POSTING_READ(reg);
4192
4193         reg = FDI_RX_CTL(pipe);
4194         temp = I915_READ(reg);
4195         temp &= ~(0x7 << 16);
4196         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4197         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4198
4199         POSTING_READ(reg);
4200         udelay(100);
4201
4202         /* Ironlake workaround, disable clock pointer after downing FDI */
4203         if (HAS_PCH_IBX(dev_priv))
4204                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4205
4206         /* still set train pattern 1 */
4207         reg = FDI_TX_CTL(pipe);
4208         temp = I915_READ(reg);
4209         temp &= ~FDI_LINK_TRAIN_NONE;
4210         temp |= FDI_LINK_TRAIN_PATTERN_1;
4211         I915_WRITE(reg, temp);
4212
4213         reg = FDI_RX_CTL(pipe);
4214         temp = I915_READ(reg);
4215         if (HAS_PCH_CPT(dev_priv)) {
4216                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4217                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4218         } else {
4219                 temp &= ~FDI_LINK_TRAIN_NONE;
4220                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4221         }
4222         /* BPC in FDI rx is consistent with that in PIPECONF */
4223         temp &= ~(0x07 << 16);
4224         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4225         I915_WRITE(reg, temp);
4226
4227         POSTING_READ(reg);
4228         udelay(100);
4229 }
4230
4231 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4232 {
4233         struct intel_crtc *crtc;
4234
4235         /* Note that we don't need to be called with mode_config.lock here
4236          * as our list of CRTC objects is static for the lifetime of the
4237          * device and so cannot disappear as we iterate. Similarly, we can
4238          * happily treat the predicates as racy, atomic checks as userspace
4239          * cannot claim and pin a new fb without at least acquring the
4240          * struct_mutex and so serialising with us.
4241          */
4242         for_each_intel_crtc(&dev_priv->drm, crtc) {
4243                 if (atomic_read(&crtc->unpin_work_count) == 0)
4244                         continue;
4245
4246                 if (crtc->flip_work)
4247                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4248
4249                 return true;
4250         }
4251
4252         return false;
4253 }
4254
4255 static void page_flip_completed(struct intel_crtc *intel_crtc)
4256 {
4257         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4258         struct intel_flip_work *work = intel_crtc->flip_work;
4259
4260         intel_crtc->flip_work = NULL;
4261
4262         if (work->event)
4263                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4264
4265         drm_crtc_vblank_put(&intel_crtc->base);
4266
4267         wake_up_all(&dev_priv->pending_flip_queue);
4268         queue_work(dev_priv->wq, &work->unpin_work);
4269
4270         trace_i915_flip_complete(intel_crtc->plane,
4271                                  work->pending_flip_obj);
4272 }
4273
4274 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4275 {
4276         struct drm_device *dev = crtc->dev;
4277         struct drm_i915_private *dev_priv = to_i915(dev);
4278         long ret;
4279
4280         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4281
4282         ret = wait_event_interruptible_timeout(
4283                                         dev_priv->pending_flip_queue,
4284                                         !intel_crtc_has_pending_flip(crtc),
4285                                         60*HZ);
4286
4287         if (ret < 0)
4288                 return ret;
4289
4290         if (ret == 0) {
4291                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4292                 struct intel_flip_work *work;
4293
4294                 spin_lock_irq(&dev->event_lock);
4295                 work = intel_crtc->flip_work;
4296                 if (work && !is_mmio_work(work)) {
4297                         WARN_ONCE(1, "Removing stuck page flip\n");
4298                         page_flip_completed(intel_crtc);
4299                 }
4300                 spin_unlock_irq(&dev->event_lock);
4301         }
4302
4303         return 0;
4304 }
4305
4306 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4307 {
4308         u32 temp;
4309
4310         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4311
4312         mutex_lock(&dev_priv->sb_lock);
4313
4314         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4315         temp |= SBI_SSCCTL_DISABLE;
4316         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4317
4318         mutex_unlock(&dev_priv->sb_lock);
4319 }
4320
4321 /* Program iCLKIP clock to the desired frequency */
4322 static void lpt_program_iclkip(struct drm_crtc *crtc)
4323 {
4324         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4325         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4326         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4327         u32 temp;
4328
4329         lpt_disable_iclkip(dev_priv);
4330
4331         /* The iCLK virtual clock root frequency is in MHz,
4332          * but the adjusted_mode->crtc_clock in in KHz. To get the
4333          * divisors, it is necessary to divide one by another, so we
4334          * convert the virtual clock precision to KHz here for higher
4335          * precision.
4336          */
4337         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4338                 u32 iclk_virtual_root_freq = 172800 * 1000;
4339                 u32 iclk_pi_range = 64;
4340                 u32 desired_divisor;
4341
4342                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4343                                                     clock << auxdiv);
4344                 divsel = (desired_divisor / iclk_pi_range) - 2;
4345                 phaseinc = desired_divisor % iclk_pi_range;
4346
4347                 /*
4348                  * Near 20MHz is a corner case which is
4349                  * out of range for the 7-bit divisor
4350                  */
4351                 if (divsel <= 0x7f)
4352                         break;
4353         }
4354
4355         /* This should not happen with any sane values */
4356         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4357                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4358         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4359                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4360
4361         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4362                         clock,
4363                         auxdiv,
4364                         divsel,
4365                         phasedir,
4366                         phaseinc);
4367
4368         mutex_lock(&dev_priv->sb_lock);
4369
4370         /* Program SSCDIVINTPHASE6 */
4371         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4372         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4373         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4374         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4375         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4376         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4377         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4378         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4379
4380         /* Program SSCAUXDIV */
4381         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4382         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4383         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4384         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4385
4386         /* Enable modulator and associated divider */
4387         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4388         temp &= ~SBI_SSCCTL_DISABLE;
4389         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4390
4391         mutex_unlock(&dev_priv->sb_lock);
4392
4393         /* Wait for initialization time */
4394         udelay(24);
4395
4396         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4397 }
4398
4399 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4400 {
4401         u32 divsel, phaseinc, auxdiv;
4402         u32 iclk_virtual_root_freq = 172800 * 1000;
4403         u32 iclk_pi_range = 64;
4404         u32 desired_divisor;
4405         u32 temp;
4406
4407         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4408                 return 0;
4409
4410         mutex_lock(&dev_priv->sb_lock);
4411
4412         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4413         if (temp & SBI_SSCCTL_DISABLE) {
4414                 mutex_unlock(&dev_priv->sb_lock);
4415                 return 0;
4416         }
4417
4418         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4419         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4420                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4421         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4422                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4423
4424         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4425         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4426                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4427
4428         mutex_unlock(&dev_priv->sb_lock);
4429
4430         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4431
4432         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4433                                  desired_divisor << auxdiv);
4434 }
4435
4436 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4437                                                 enum pipe pch_transcoder)
4438 {
4439         struct drm_device *dev = crtc->base.dev;
4440         struct drm_i915_private *dev_priv = to_i915(dev);
4441         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4442
4443         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4444                    I915_READ(HTOTAL(cpu_transcoder)));
4445         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4446                    I915_READ(HBLANK(cpu_transcoder)));
4447         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4448                    I915_READ(HSYNC(cpu_transcoder)));
4449
4450         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4451                    I915_READ(VTOTAL(cpu_transcoder)));
4452         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4453                    I915_READ(VBLANK(cpu_transcoder)));
4454         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4455                    I915_READ(VSYNC(cpu_transcoder)));
4456         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4457                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4458 }
4459
4460 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4461 {
4462         struct drm_i915_private *dev_priv = to_i915(dev);
4463         uint32_t temp;
4464
4465         temp = I915_READ(SOUTH_CHICKEN1);
4466         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4467                 return;
4468
4469         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4470         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4471
4472         temp &= ~FDI_BC_BIFURCATION_SELECT;
4473         if (enable)
4474                 temp |= FDI_BC_BIFURCATION_SELECT;
4475
4476         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4477         I915_WRITE(SOUTH_CHICKEN1, temp);
4478         POSTING_READ(SOUTH_CHICKEN1);
4479 }
4480
4481 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4482 {
4483         struct drm_device *dev = intel_crtc->base.dev;
4484
4485         switch (intel_crtc->pipe) {
4486         case PIPE_A:
4487                 break;
4488         case PIPE_B:
4489                 if (intel_crtc->config->fdi_lanes > 2)
4490                         cpt_set_fdi_bc_bifurcation(dev, false);
4491                 else
4492                         cpt_set_fdi_bc_bifurcation(dev, true);
4493
4494                 break;
4495         case PIPE_C:
4496                 cpt_set_fdi_bc_bifurcation(dev, true);
4497
4498                 break;
4499         default:
4500                 BUG();
4501         }
4502 }
4503
4504 /* Return which DP Port should be selected for Transcoder DP control */
4505 static enum port
4506 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4507 {
4508         struct drm_device *dev = crtc->dev;
4509         struct intel_encoder *encoder;
4510
4511         for_each_encoder_on_crtc(dev, crtc, encoder) {
4512                 if (encoder->type == INTEL_OUTPUT_DP ||
4513                     encoder->type == INTEL_OUTPUT_EDP)
4514                         return enc_to_dig_port(&encoder->base)->port;
4515         }
4516
4517         return -1;
4518 }
4519
4520 /*
4521  * Enable PCH resources required for PCH ports:
4522  *   - PCH PLLs
4523  *   - FDI training & RX/TX
4524  *   - update transcoder timings
4525  *   - DP transcoding bits
4526  *   - transcoder
4527  */
4528 static void ironlake_pch_enable(struct drm_crtc *crtc)
4529 {
4530         struct drm_device *dev = crtc->dev;
4531         struct drm_i915_private *dev_priv = to_i915(dev);
4532         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4533         int pipe = intel_crtc->pipe;
4534         u32 temp;
4535
4536         assert_pch_transcoder_disabled(dev_priv, pipe);
4537
4538         if (IS_IVYBRIDGE(dev_priv))
4539                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4540
4541         /* Write the TU size bits before fdi link training, so that error
4542          * detection works. */
4543         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4544                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4545
4546         /* For PCH output, training FDI link */
4547         dev_priv->display.fdi_link_train(crtc);
4548
4549         /* We need to program the right clock selection before writing the pixel
4550          * mutliplier into the DPLL. */
4551         if (HAS_PCH_CPT(dev_priv)) {
4552                 u32 sel;
4553
4554                 temp = I915_READ(PCH_DPLL_SEL);
4555                 temp |= TRANS_DPLL_ENABLE(pipe);
4556                 sel = TRANS_DPLLB_SEL(pipe);
4557                 if (intel_crtc->config->shared_dpll ==
4558                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4559                         temp |= sel;
4560                 else
4561                         temp &= ~sel;
4562                 I915_WRITE(PCH_DPLL_SEL, temp);
4563         }
4564
4565         /* XXX: pch pll's can be enabled any time before we enable the PCH
4566          * transcoder, and we actually should do this to not upset any PCH
4567          * transcoder that already use the clock when we share it.
4568          *
4569          * Note that enable_shared_dpll tries to do the right thing, but
4570          * get_shared_dpll unconditionally resets the pll - we need that to have
4571          * the right LVDS enable sequence. */
4572         intel_enable_shared_dpll(intel_crtc);
4573
4574         /* set transcoder timing, panel must allow it */
4575         assert_panel_unlocked(dev_priv, pipe);
4576         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4577
4578         intel_fdi_normal_train(crtc);
4579
4580         /* For PCH DP, enable TRANS_DP_CTL */
4581         if (HAS_PCH_CPT(dev_priv) &&
4582             intel_crtc_has_dp_encoder(intel_crtc->config)) {
4583                 const struct drm_display_mode *adjusted_mode =
4584                         &intel_crtc->config->base.adjusted_mode;
4585                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4586                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4587                 temp = I915_READ(reg);
4588                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4589                           TRANS_DP_SYNC_MASK |
4590                           TRANS_DP_BPC_MASK);
4591                 temp |= TRANS_DP_OUTPUT_ENABLE;
4592                 temp |= bpc << 9; /* same format but at 11:9 */
4593
4594                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4595                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4596                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4597                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4598
4599                 switch (intel_trans_dp_port_sel(crtc)) {
4600                 case PORT_B:
4601                         temp |= TRANS_DP_PORT_SEL_B;
4602                         break;
4603                 case PORT_C:
4604                         temp |= TRANS_DP_PORT_SEL_C;
4605                         break;
4606                 case PORT_D:
4607                         temp |= TRANS_DP_PORT_SEL_D;
4608                         break;
4609                 default:
4610                         BUG();
4611                 }
4612
4613                 I915_WRITE(reg, temp);
4614         }
4615
4616         ironlake_enable_pch_transcoder(dev_priv, pipe);
4617 }
4618
4619 static void lpt_pch_enable(struct drm_crtc *crtc)
4620 {
4621         struct drm_device *dev = crtc->dev;
4622         struct drm_i915_private *dev_priv = to_i915(dev);
4623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4624         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4625
4626         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4627
4628         lpt_program_iclkip(crtc);
4629
4630         /* Set transcoder timing. */
4631         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4632
4633         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4634 }
4635
4636 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4637 {
4638         struct drm_i915_private *dev_priv = to_i915(dev);
4639         i915_reg_t dslreg = PIPEDSL(pipe);
4640         u32 temp;
4641
4642         temp = I915_READ(dslreg);
4643         udelay(500);
4644         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4645                 if (wait_for(I915_READ(dslreg) != temp, 5))
4646                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4647         }
4648 }
4649
4650 static int
4651 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4652                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4653                   int src_w, int src_h, int dst_w, int dst_h)
4654 {
4655         struct intel_crtc_scaler_state *scaler_state =
4656                 &crtc_state->scaler_state;
4657         struct intel_crtc *intel_crtc =
4658                 to_intel_crtc(crtc_state->base.crtc);
4659         int need_scaling;
4660
4661         need_scaling = drm_rotation_90_or_270(rotation) ?
4662                 (src_h != dst_w || src_w != dst_h):
4663                 (src_w != dst_w || src_h != dst_h);
4664
4665         /*
4666          * if plane is being disabled or scaler is no more required or force detach
4667          *  - free scaler binded to this plane/crtc
4668          *  - in order to do this, update crtc->scaler_usage
4669          *
4670          * Here scaler state in crtc_state is set free so that
4671          * scaler can be assigned to other user. Actual register
4672          * update to free the scaler is done in plane/panel-fit programming.
4673          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4674          */
4675         if (force_detach || !need_scaling) {
4676                 if (*scaler_id >= 0) {
4677                         scaler_state->scaler_users &= ~(1 << scaler_user);
4678                         scaler_state->scalers[*scaler_id].in_use = 0;
4679
4680                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4681                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4682                                 intel_crtc->pipe, scaler_user, *scaler_id,
4683                                 scaler_state->scaler_users);
4684                         *scaler_id = -1;
4685                 }
4686                 return 0;
4687         }
4688
4689         /* range checks */
4690         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4691                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4692
4693                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4694                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4695                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4696                         "size is out of scaler range\n",
4697                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4698                 return -EINVAL;
4699         }
4700
4701         /* mark this plane as a scaler user in crtc_state */
4702         scaler_state->scaler_users |= (1 << scaler_user);
4703         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4704                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4705                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4706                 scaler_state->scaler_users);
4707
4708         return 0;
4709 }
4710
4711 /**
4712  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4713  *
4714  * @state: crtc's scaler state
4715  *
4716  * Return
4717  *     0 - scaler_usage updated successfully
4718  *    error - requested scaling cannot be supported or other error condition
4719  */
4720 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4721 {
4722         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4723
4724         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4725                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4726                 state->pipe_src_w, state->pipe_src_h,
4727                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4728 }
4729
4730 /**
4731  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4732  *
4733  * @state: crtc's scaler state
4734  * @plane_state: atomic plane state to update
4735  *
4736  * Return
4737  *     0 - scaler_usage updated successfully
4738  *    error - requested scaling cannot be supported or other error condition
4739  */
4740 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4741                                    struct intel_plane_state *plane_state)
4742 {
4743
4744         struct intel_plane *intel_plane =
4745                 to_intel_plane(plane_state->base.plane);
4746         struct drm_framebuffer *fb = plane_state->base.fb;
4747         int ret;
4748
4749         bool force_detach = !fb || !plane_state->base.visible;
4750
4751         ret = skl_update_scaler(crtc_state, force_detach,
4752                                 drm_plane_index(&intel_plane->base),
4753                                 &plane_state->scaler_id,
4754                                 plane_state->base.rotation,
4755                                 drm_rect_width(&plane_state->base.src) >> 16,
4756                                 drm_rect_height(&plane_state->base.src) >> 16,
4757                                 drm_rect_width(&plane_state->base.dst),
4758                                 drm_rect_height(&plane_state->base.dst));
4759
4760         if (ret || plane_state->scaler_id < 0)
4761                 return ret;
4762
4763         /* check colorkey */
4764         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4765                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4766                               intel_plane->base.base.id,
4767                               intel_plane->base.name);
4768                 return -EINVAL;
4769         }
4770
4771         /* Check src format */
4772         switch (fb->pixel_format) {
4773         case DRM_FORMAT_RGB565:
4774         case DRM_FORMAT_XBGR8888:
4775         case DRM_FORMAT_XRGB8888:
4776         case DRM_FORMAT_ABGR8888:
4777         case DRM_FORMAT_ARGB8888:
4778         case DRM_FORMAT_XRGB2101010:
4779         case DRM_FORMAT_XBGR2101010:
4780         case DRM_FORMAT_YUYV:
4781         case DRM_FORMAT_YVYU:
4782         case DRM_FORMAT_UYVY:
4783         case DRM_FORMAT_VYUY:
4784                 break;
4785         default:
4786                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4787                               intel_plane->base.base.id, intel_plane->base.name,
4788                               fb->base.id, fb->pixel_format);
4789                 return -EINVAL;
4790         }
4791
4792         return 0;
4793 }
4794
4795 static void skylake_scaler_disable(struct intel_crtc *crtc)
4796 {
4797         int i;
4798
4799         for (i = 0; i < crtc->num_scalers; i++)
4800                 skl_detach_scaler(crtc, i);
4801 }
4802
4803 static void skylake_pfit_enable(struct intel_crtc *crtc)
4804 {
4805         struct drm_device *dev = crtc->base.dev;
4806         struct drm_i915_private *dev_priv = to_i915(dev);
4807         int pipe = crtc->pipe;
4808         struct intel_crtc_scaler_state *scaler_state =
4809                 &crtc->config->scaler_state;
4810
4811         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4812
4813         if (crtc->config->pch_pfit.enabled) {
4814                 int id;
4815
4816                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4817                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4818                         return;
4819                 }
4820
4821                 id = scaler_state->scaler_id;
4822                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4823                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4824                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4825                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4826
4827                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4828         }
4829 }
4830
4831 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4832 {
4833         struct drm_device *dev = crtc->base.dev;
4834         struct drm_i915_private *dev_priv = to_i915(dev);
4835         int pipe = crtc->pipe;
4836
4837         if (crtc->config->pch_pfit.enabled) {
4838                 /* Force use of hard-coded filter coefficients
4839                  * as some pre-programmed values are broken,
4840                  * e.g. x201.
4841                  */
4842                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4843                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4844                                                  PF_PIPE_SEL_IVB(pipe));
4845                 else
4846                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4847                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4848                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4849         }
4850 }
4851
4852 void hsw_enable_ips(struct intel_crtc *crtc)
4853 {
4854         struct drm_device *dev = crtc->base.dev;
4855         struct drm_i915_private *dev_priv = to_i915(dev);
4856
4857         if (!crtc->config->ips_enabled)
4858                 return;
4859
4860         /*
4861          * We can only enable IPS after we enable a plane and wait for a vblank
4862          * This function is called from post_plane_update, which is run after
4863          * a vblank wait.
4864          */
4865
4866         assert_plane_enabled(dev_priv, crtc->plane);
4867         if (IS_BROADWELL(dev_priv)) {
4868                 mutex_lock(&dev_priv->rps.hw_lock);
4869                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4870                 mutex_unlock(&dev_priv->rps.hw_lock);
4871                 /* Quoting Art Runyan: "its not safe to expect any particular
4872                  * value in IPS_CTL bit 31 after enabling IPS through the
4873                  * mailbox." Moreover, the mailbox may return a bogus state,
4874                  * so we need to just enable it and continue on.
4875                  */
4876         } else {
4877                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4878                 /* The bit only becomes 1 in the next vblank, so this wait here
4879                  * is essentially intel_wait_for_vblank. If we don't have this
4880                  * and don't wait for vblanks until the end of crtc_enable, then
4881                  * the HW state readout code will complain that the expected
4882                  * IPS_CTL value is not the one we read. */
4883                 if (intel_wait_for_register(dev_priv,
4884                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4885                                             50))
4886                         DRM_ERROR("Timed out waiting for IPS enable\n");
4887         }
4888 }
4889
4890 void hsw_disable_ips(struct intel_crtc *crtc)
4891 {
4892         struct drm_device *dev = crtc->base.dev;
4893         struct drm_i915_private *dev_priv = to_i915(dev);
4894
4895         if (!crtc->config->ips_enabled)
4896                 return;
4897
4898         assert_plane_enabled(dev_priv, crtc->plane);
4899         if (IS_BROADWELL(dev_priv)) {
4900                 mutex_lock(&dev_priv->rps.hw_lock);
4901                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4902                 mutex_unlock(&dev_priv->rps.hw_lock);
4903                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4904                 if (intel_wait_for_register(dev_priv,
4905                                             IPS_CTL, IPS_ENABLE, 0,
4906                                             42))
4907                         DRM_ERROR("Timed out waiting for IPS disable\n");
4908         } else {
4909                 I915_WRITE(IPS_CTL, 0);
4910                 POSTING_READ(IPS_CTL);
4911         }
4912
4913         /* We need to wait for a vblank before we can disable the plane. */
4914         intel_wait_for_vblank(dev_priv, crtc->pipe);
4915 }
4916
4917 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4918 {
4919         if (intel_crtc->overlay) {
4920                 struct drm_device *dev = intel_crtc->base.dev;
4921                 struct drm_i915_private *dev_priv = to_i915(dev);
4922
4923                 mutex_lock(&dev->struct_mutex);
4924                 dev_priv->mm.interruptible = false;
4925                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4926                 dev_priv->mm.interruptible = true;
4927                 mutex_unlock(&dev->struct_mutex);
4928         }
4929
4930         /* Let userspace switch the overlay on again. In most cases userspace
4931          * has to recompute where to put it anyway.
4932          */
4933 }
4934
4935 /**
4936  * intel_post_enable_primary - Perform operations after enabling primary plane
4937  * @crtc: the CRTC whose primary plane was just enabled
4938  *
4939  * Performs potentially sleeping operations that must be done after the primary
4940  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4941  * called due to an explicit primary plane update, or due to an implicit
4942  * re-enable that is caused when a sprite plane is updated to no longer
4943  * completely hide the primary plane.
4944  */
4945 static void
4946 intel_post_enable_primary(struct drm_crtc *crtc)
4947 {
4948         struct drm_device *dev = crtc->dev;
4949         struct drm_i915_private *dev_priv = to_i915(dev);
4950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4951         int pipe = intel_crtc->pipe;
4952
4953         /*
4954          * FIXME IPS should be fine as long as one plane is
4955          * enabled, but in practice it seems to have problems
4956          * when going from primary only to sprite only and vice
4957          * versa.
4958          */
4959         hsw_enable_ips(intel_crtc);
4960
4961         /*
4962          * Gen2 reports pipe underruns whenever all planes are disabled.
4963          * So don't enable underrun reporting before at least some planes
4964          * are enabled.
4965          * FIXME: Need to fix the logic to work when we turn off all planes
4966          * but leave the pipe running.
4967          */
4968         if (IS_GEN2(dev_priv))
4969                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4970
4971         /* Underruns don't always raise interrupts, so check manually. */
4972         intel_check_cpu_fifo_underruns(dev_priv);
4973         intel_check_pch_fifo_underruns(dev_priv);
4974 }
4975
4976 /* FIXME move all this to pre_plane_update() with proper state tracking */
4977 static void
4978 intel_pre_disable_primary(struct drm_crtc *crtc)
4979 {
4980         struct drm_device *dev = crtc->dev;
4981         struct drm_i915_private *dev_priv = to_i915(dev);
4982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4983         int pipe = intel_crtc->pipe;
4984
4985         /*
4986          * Gen2 reports pipe underruns whenever all planes are disabled.
4987          * So diasble underrun reporting before all the planes get disabled.
4988          * FIXME: Need to fix the logic to work when we turn off all planes
4989          * but leave the pipe running.
4990          */
4991         if (IS_GEN2(dev_priv))
4992                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4993
4994         /*
4995          * FIXME IPS should be fine as long as one plane is
4996          * enabled, but in practice it seems to have problems
4997          * when going from primary only to sprite only and vice
4998          * versa.
4999          */
5000         hsw_disable_ips(intel_crtc);
5001 }
5002
5003 /* FIXME get rid of this and use pre_plane_update */
5004 static void
5005 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5006 {
5007         struct drm_device *dev = crtc->dev;
5008         struct drm_i915_private *dev_priv = to_i915(dev);
5009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5010         int pipe = intel_crtc->pipe;
5011
5012         intel_pre_disable_primary(crtc);
5013
5014         /*
5015          * Vblank time updates from the shadow to live plane control register
5016          * are blocked if the memory self-refresh mode is active at that
5017          * moment. So to make sure the plane gets truly disabled, disable
5018          * first the self-refresh mode. The self-refresh enable bit in turn
5019          * will be checked/applied by the HW only at the next frame start
5020          * event which is after the vblank start event, so we need to have a
5021          * wait-for-vblank between disabling the plane and the pipe.
5022          */
5023         if (HAS_GMCH_DISPLAY(dev_priv) &&
5024             intel_set_memory_cxsr(dev_priv, false))
5025                 intel_wait_for_vblank(dev_priv, pipe);
5026 }
5027
5028 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5029 {
5030         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5031         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5032         struct intel_crtc_state *pipe_config =
5033                 to_intel_crtc_state(crtc->base.state);
5034         struct drm_plane *primary = crtc->base.primary;
5035         struct drm_plane_state *old_pri_state =
5036                 drm_atomic_get_existing_plane_state(old_state, primary);
5037
5038         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5039
5040         crtc->wm.cxsr_allowed = true;
5041
5042         if (pipe_config->update_wm_post && pipe_config->base.active)
5043                 intel_update_watermarks(crtc);
5044
5045         if (old_pri_state) {
5046                 struct intel_plane_state *primary_state =
5047                         to_intel_plane_state(primary->state);
5048                 struct intel_plane_state *old_primary_state =
5049                         to_intel_plane_state(old_pri_state);
5050
5051                 intel_fbc_post_update(crtc);
5052
5053                 if (primary_state->base.visible &&
5054                     (needs_modeset(&pipe_config->base) ||
5055                      !old_primary_state->base.visible))
5056                         intel_post_enable_primary(&crtc->base);
5057         }
5058 }
5059
5060 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5061 {
5062         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5063         struct drm_device *dev = crtc->base.dev;
5064         struct drm_i915_private *dev_priv = to_i915(dev);
5065         struct intel_crtc_state *pipe_config =
5066                 to_intel_crtc_state(crtc->base.state);
5067         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5068         struct drm_plane *primary = crtc->base.primary;
5069         struct drm_plane_state *old_pri_state =
5070                 drm_atomic_get_existing_plane_state(old_state, primary);
5071         bool modeset = needs_modeset(&pipe_config->base);
5072         struct intel_atomic_state *old_intel_state =
5073                 to_intel_atomic_state(old_state);
5074
5075         if (old_pri_state) {
5076                 struct intel_plane_state *primary_state =
5077                         to_intel_plane_state(primary->state);
5078                 struct intel_plane_state *old_primary_state =
5079                         to_intel_plane_state(old_pri_state);
5080
5081                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5082
5083                 if (old_primary_state->base.visible &&
5084                     (modeset || !primary_state->base.visible))
5085                         intel_pre_disable_primary(&crtc->base);
5086         }
5087
5088         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5089                 crtc->wm.cxsr_allowed = false;
5090
5091                 /*
5092                  * Vblank time updates from the shadow to live plane control register
5093                  * are blocked if the memory self-refresh mode is active at that
5094                  * moment. So to make sure the plane gets truly disabled, disable
5095                  * first the self-refresh mode. The self-refresh enable bit in turn
5096                  * will be checked/applied by the HW only at the next frame start
5097                  * event which is after the vblank start event, so we need to have a
5098                  * wait-for-vblank between disabling the plane and the pipe.
5099                  */
5100                 if (old_crtc_state->base.active &&
5101                     intel_set_memory_cxsr(dev_priv, false))
5102                         intel_wait_for_vblank(dev_priv, crtc->pipe);
5103         }
5104
5105         /*
5106          * IVB workaround: must disable low power watermarks for at least
5107          * one frame before enabling scaling.  LP watermarks can be re-enabled
5108          * when scaling is disabled.
5109          *
5110          * WaCxSRDisabledForSpriteScaling:ivb
5111          */
5112         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5113                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5114
5115         /*
5116          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5117          * watermark programming here.
5118          */
5119         if (needs_modeset(&pipe_config->base))
5120                 return;
5121
5122         /*
5123          * For platforms that support atomic watermarks, program the
5124          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5125          * will be the intermediate values that are safe for both pre- and
5126          * post- vblank; when vblank happens, the 'active' values will be set
5127          * to the final 'target' values and we'll do this again to get the
5128          * optimal watermarks.  For gen9+ platforms, the values we program here
5129          * will be the final target values which will get automatically latched
5130          * at vblank time; no further programming will be necessary.
5131          *
5132          * If a platform hasn't been transitioned to atomic watermarks yet,
5133          * we'll continue to update watermarks the old way, if flags tell
5134          * us to.
5135          */
5136         if (dev_priv->display.initial_watermarks != NULL)
5137                 dev_priv->display.initial_watermarks(old_intel_state,
5138                                                      pipe_config);
5139         else if (pipe_config->update_wm_pre)
5140                 intel_update_watermarks(crtc);
5141 }
5142
5143 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5144 {
5145         struct drm_device *dev = crtc->dev;
5146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5147         struct drm_plane *p;
5148         int pipe = intel_crtc->pipe;
5149
5150         intel_crtc_dpms_overlay_disable(intel_crtc);
5151
5152         drm_for_each_plane_mask(p, dev, plane_mask)
5153                 to_intel_plane(p)->disable_plane(p, crtc);
5154
5155         /*
5156          * FIXME: Once we grow proper nuclear flip support out of this we need
5157          * to compute the mask of flip planes precisely. For the time being
5158          * consider this a flip to a NULL plane.
5159          */
5160         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5161 }
5162
5163 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5164                                           struct intel_crtc_state *crtc_state,
5165                                           struct drm_atomic_state *old_state)
5166 {
5167         struct drm_connector_state *old_conn_state;
5168         struct drm_connector *conn;
5169         int i;
5170
5171         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5172                 struct drm_connector_state *conn_state = conn->state;
5173                 struct intel_encoder *encoder =
5174                         to_intel_encoder(conn_state->best_encoder);
5175
5176                 if (conn_state->crtc != crtc)
5177                         continue;
5178
5179                 if (encoder->pre_pll_enable)
5180                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5181         }
5182 }
5183
5184 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5185                                       struct intel_crtc_state *crtc_state,
5186                                       struct drm_atomic_state *old_state)
5187 {
5188         struct drm_connector_state *old_conn_state;
5189         struct drm_connector *conn;
5190         int i;
5191
5192         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5193                 struct drm_connector_state *conn_state = conn->state;
5194                 struct intel_encoder *encoder =
5195                         to_intel_encoder(conn_state->best_encoder);
5196
5197                 if (conn_state->crtc != crtc)
5198                         continue;
5199
5200                 if (encoder->pre_enable)
5201                         encoder->pre_enable(encoder, crtc_state, conn_state);
5202         }
5203 }
5204
5205 static void intel_encoders_enable(struct drm_crtc *crtc,
5206                                   struct intel_crtc_state *crtc_state,
5207                                   struct drm_atomic_state *old_state)
5208 {
5209         struct drm_connector_state *old_conn_state;
5210         struct drm_connector *conn;
5211         int i;
5212
5213         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5214                 struct drm_connector_state *conn_state = conn->state;
5215                 struct intel_encoder *encoder =
5216                         to_intel_encoder(conn_state->best_encoder);
5217
5218                 if (conn_state->crtc != crtc)
5219                         continue;
5220
5221                 encoder->enable(encoder, crtc_state, conn_state);
5222                 intel_opregion_notify_encoder(encoder, true);
5223         }
5224 }
5225
5226 static void intel_encoders_disable(struct drm_crtc *crtc,
5227                                    struct intel_crtc_state *old_crtc_state,
5228                                    struct drm_atomic_state *old_state)
5229 {
5230         struct drm_connector_state *old_conn_state;
5231         struct drm_connector *conn;
5232         int i;
5233
5234         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5235                 struct intel_encoder *encoder =
5236                         to_intel_encoder(old_conn_state->best_encoder);
5237
5238                 if (old_conn_state->crtc != crtc)
5239                         continue;
5240
5241                 intel_opregion_notify_encoder(encoder, false);
5242                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5243         }
5244 }
5245
5246 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5247                                         struct intel_crtc_state *old_crtc_state,
5248                                         struct drm_atomic_state *old_state)
5249 {
5250         struct drm_connector_state *old_conn_state;
5251         struct drm_connector *conn;
5252         int i;
5253
5254         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5255                 struct intel_encoder *encoder =
5256                         to_intel_encoder(old_conn_state->best_encoder);
5257
5258                 if (old_conn_state->crtc != crtc)
5259                         continue;
5260
5261                 if (encoder->post_disable)
5262                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5263         }
5264 }
5265
5266 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5267                                             struct intel_crtc_state *old_crtc_state,
5268                                             struct drm_atomic_state *old_state)
5269 {
5270         struct drm_connector_state *old_conn_state;
5271         struct drm_connector *conn;
5272         int i;
5273
5274         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5275                 struct intel_encoder *encoder =
5276                         to_intel_encoder(old_conn_state->best_encoder);
5277
5278                 if (old_conn_state->crtc != crtc)
5279                         continue;
5280
5281                 if (encoder->post_pll_disable)
5282                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5283         }
5284 }
5285
5286 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5287                                  struct drm_atomic_state *old_state)
5288 {
5289         struct drm_crtc *crtc = pipe_config->base.crtc;
5290         struct drm_device *dev = crtc->dev;
5291         struct drm_i915_private *dev_priv = to_i915(dev);
5292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5293         int pipe = intel_crtc->pipe;
5294         struct intel_atomic_state *old_intel_state =
5295                 to_intel_atomic_state(old_state);
5296
5297         if (WARN_ON(intel_crtc->active))
5298                 return;
5299
5300         /*
5301          * Sometimes spurious CPU pipe underruns happen during FDI
5302          * training, at least with VGA+HDMI cloning. Suppress them.
5303          *
5304          * On ILK we get an occasional spurious CPU pipe underruns
5305          * between eDP port A enable and vdd enable. Also PCH port
5306          * enable seems to result in the occasional CPU pipe underrun.
5307          *
5308          * Spurious PCH underruns also occur during PCH enabling.
5309          */
5310         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5311                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5312         if (intel_crtc->config->has_pch_encoder)
5313                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5314
5315         if (intel_crtc->config->has_pch_encoder)
5316                 intel_prepare_shared_dpll(intel_crtc);
5317
5318         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5319                 intel_dp_set_m_n(intel_crtc, M1_N1);
5320
5321         intel_set_pipe_timings(intel_crtc);
5322         intel_set_pipe_src_size(intel_crtc);
5323
5324         if (intel_crtc->config->has_pch_encoder) {
5325                 intel_cpu_transcoder_set_m_n(intel_crtc,
5326                                      &intel_crtc->config->fdi_m_n, NULL);
5327         }
5328
5329         ironlake_set_pipeconf(crtc);
5330
5331         intel_crtc->active = true;
5332
5333         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5334
5335         if (intel_crtc->config->has_pch_encoder) {
5336                 /* Note: FDI PLL enabling _must_ be done before we enable the
5337                  * cpu pipes, hence this is separate from all the other fdi/pch
5338                  * enabling. */
5339                 ironlake_fdi_pll_enable(intel_crtc);
5340         } else {
5341                 assert_fdi_tx_disabled(dev_priv, pipe);
5342                 assert_fdi_rx_disabled(dev_priv, pipe);
5343         }
5344
5345         ironlake_pfit_enable(intel_crtc);
5346
5347         /*
5348          * On ILK+ LUT must be loaded before the pipe is running but with
5349          * clocks enabled
5350          */
5351         intel_color_load_luts(&pipe_config->base);
5352
5353         if (dev_priv->display.initial_watermarks != NULL)
5354                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5355         intel_enable_pipe(intel_crtc);
5356
5357         if (intel_crtc->config->has_pch_encoder)
5358                 ironlake_pch_enable(crtc);
5359
5360         assert_vblank_disabled(crtc);
5361         drm_crtc_vblank_on(crtc);
5362
5363         intel_encoders_enable(crtc, pipe_config, old_state);
5364
5365         if (HAS_PCH_CPT(dev_priv))
5366                 cpt_verify_modeset(dev, intel_crtc->pipe);
5367
5368         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5369         if (intel_crtc->config->has_pch_encoder)
5370                 intel_wait_for_vblank(dev_priv, pipe);
5371         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5372         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5373 }
5374
5375 /* IPS only exists on ULT machines and is tied to pipe A. */
5376 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5377 {
5378         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5379 }
5380
5381 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5382                                 struct drm_atomic_state *old_state)
5383 {
5384         struct drm_crtc *crtc = pipe_config->base.crtc;
5385         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5386         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5387         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5388         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5389         struct intel_atomic_state *old_intel_state =
5390                 to_intel_atomic_state(old_state);
5391
5392         if (WARN_ON(intel_crtc->active))
5393                 return;
5394
5395         if (intel_crtc->config->has_pch_encoder)
5396                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5397                                                       false);
5398
5399         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5400
5401         if (intel_crtc->config->shared_dpll)
5402                 intel_enable_shared_dpll(intel_crtc);
5403
5404         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5405                 intel_dp_set_m_n(intel_crtc, M1_N1);
5406
5407         if (!transcoder_is_dsi(cpu_transcoder))
5408                 intel_set_pipe_timings(intel_crtc);
5409
5410         intel_set_pipe_src_size(intel_crtc);
5411
5412         if (cpu_transcoder != TRANSCODER_EDP &&
5413             !transcoder_is_dsi(cpu_transcoder)) {
5414                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5415                            intel_crtc->config->pixel_multiplier - 1);
5416         }
5417
5418         if (intel_crtc->config->has_pch_encoder) {
5419                 intel_cpu_transcoder_set_m_n(intel_crtc,
5420                                      &intel_crtc->config->fdi_m_n, NULL);
5421         }
5422
5423         if (!transcoder_is_dsi(cpu_transcoder))
5424                 haswell_set_pipeconf(crtc);
5425
5426         haswell_set_pipemisc(crtc);
5427
5428         intel_color_set_csc(&pipe_config->base);
5429
5430         intel_crtc->active = true;
5431
5432         if (intel_crtc->config->has_pch_encoder)
5433                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5434         else
5435                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5436
5437         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5438
5439         if (intel_crtc->config->has_pch_encoder)
5440                 dev_priv->display.fdi_link_train(crtc);
5441
5442         if (!transcoder_is_dsi(cpu_transcoder))
5443                 intel_ddi_enable_pipe_clock(intel_crtc);
5444
5445         if (INTEL_GEN(dev_priv) >= 9)
5446                 skylake_pfit_enable(intel_crtc);
5447         else
5448                 ironlake_pfit_enable(intel_crtc);
5449
5450         /*
5451          * On ILK+ LUT must be loaded before the pipe is running but with
5452          * clocks enabled
5453          */
5454         intel_color_load_luts(&pipe_config->base);
5455
5456         intel_ddi_set_pipe_settings(crtc);
5457         if (!transcoder_is_dsi(cpu_transcoder))
5458                 intel_ddi_enable_transcoder_func(crtc);
5459
5460         if (dev_priv->display.initial_watermarks != NULL)
5461                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5462
5463         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5464         if (!transcoder_is_dsi(cpu_transcoder))
5465                 intel_enable_pipe(intel_crtc);
5466
5467         if (intel_crtc->config->has_pch_encoder)
5468                 lpt_pch_enable(crtc);
5469
5470         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5471                 intel_ddi_set_vc_payload_alloc(crtc, true);
5472
5473         assert_vblank_disabled(crtc);
5474         drm_crtc_vblank_on(crtc);
5475
5476         intel_encoders_enable(crtc, pipe_config, old_state);
5477
5478         if (intel_crtc->config->has_pch_encoder) {
5479                 intel_wait_for_vblank(dev_priv, pipe);
5480                 intel_wait_for_vblank(dev_priv, pipe);
5481                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5482                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5483                                                       true);
5484         }
5485
5486         /* If we change the relative order between pipe/planes enabling, we need
5487          * to change the workaround. */
5488         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5489         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5490                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5491                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5492         }
5493 }
5494
5495 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5496 {
5497         struct drm_device *dev = crtc->base.dev;
5498         struct drm_i915_private *dev_priv = to_i915(dev);
5499         int pipe = crtc->pipe;
5500
5501         /* To avoid upsetting the power well on haswell only disable the pfit if
5502          * it's in use. The hw state code will make sure we get this right. */
5503         if (force || crtc->config->pch_pfit.enabled) {
5504                 I915_WRITE(PF_CTL(pipe), 0);
5505                 I915_WRITE(PF_WIN_POS(pipe), 0);
5506                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5507         }
5508 }
5509
5510 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5511                                   struct drm_atomic_state *old_state)
5512 {
5513         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5514         struct drm_device *dev = crtc->dev;
5515         struct drm_i915_private *dev_priv = to_i915(dev);
5516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5517         int pipe = intel_crtc->pipe;
5518
5519         /*
5520          * Sometimes spurious CPU pipe underruns happen when the
5521          * pipe is already disabled, but FDI RX/TX is still enabled.
5522          * Happens at least with VGA+HDMI cloning. Suppress them.
5523          */
5524         if (intel_crtc->config->has_pch_encoder) {
5525                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5526                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5527         }
5528
5529         intel_encoders_disable(crtc, old_crtc_state, old_state);
5530
5531         drm_crtc_vblank_off(crtc);
5532         assert_vblank_disabled(crtc);
5533
5534         intel_disable_pipe(intel_crtc);
5535
5536         ironlake_pfit_disable(intel_crtc, false);
5537
5538         if (intel_crtc->config->has_pch_encoder)
5539                 ironlake_fdi_disable(crtc);
5540
5541         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5542
5543         if (intel_crtc->config->has_pch_encoder) {
5544                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5545
5546                 if (HAS_PCH_CPT(dev_priv)) {
5547                         i915_reg_t reg;
5548                         u32 temp;
5549
5550                         /* disable TRANS_DP_CTL */
5551                         reg = TRANS_DP_CTL(pipe);
5552                         temp = I915_READ(reg);
5553                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5554                                   TRANS_DP_PORT_SEL_MASK);
5555                         temp |= TRANS_DP_PORT_SEL_NONE;
5556                         I915_WRITE(reg, temp);
5557
5558                         /* disable DPLL_SEL */
5559                         temp = I915_READ(PCH_DPLL_SEL);
5560                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5561                         I915_WRITE(PCH_DPLL_SEL, temp);
5562                 }
5563
5564                 ironlake_fdi_pll_disable(intel_crtc);
5565         }
5566
5567         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5568         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5569 }
5570
5571 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5572                                  struct drm_atomic_state *old_state)
5573 {
5574         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5575         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5577         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5578
5579         if (intel_crtc->config->has_pch_encoder)
5580                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5581                                                       false);
5582
5583         intel_encoders_disable(crtc, old_crtc_state, old_state);
5584
5585         drm_crtc_vblank_off(crtc);
5586         assert_vblank_disabled(crtc);
5587
5588         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5589         if (!transcoder_is_dsi(cpu_transcoder))
5590                 intel_disable_pipe(intel_crtc);
5591
5592         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5593                 intel_ddi_set_vc_payload_alloc(crtc, false);
5594
5595         if (!transcoder_is_dsi(cpu_transcoder))
5596                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5597
5598         if (INTEL_GEN(dev_priv) >= 9)
5599                 skylake_scaler_disable(intel_crtc);
5600         else
5601                 ironlake_pfit_disable(intel_crtc, false);
5602
5603         if (!transcoder_is_dsi(cpu_transcoder))
5604                 intel_ddi_disable_pipe_clock(intel_crtc);
5605
5606         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5607
5608         if (old_crtc_state->has_pch_encoder)
5609                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5610                                                       true);
5611 }
5612
5613 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5614 {
5615         struct drm_device *dev = crtc->base.dev;
5616         struct drm_i915_private *dev_priv = to_i915(dev);
5617         struct intel_crtc_state *pipe_config = crtc->config;
5618
5619         if (!pipe_config->gmch_pfit.control)
5620                 return;
5621
5622         /*
5623          * The panel fitter should only be adjusted whilst the pipe is disabled,
5624          * according to register description and PRM.
5625          */
5626         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5627         assert_pipe_disabled(dev_priv, crtc->pipe);
5628
5629         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5630         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5631
5632         /* Border color in case we don't scale up to the full screen. Black by
5633          * default, change to something else for debugging. */
5634         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5635 }
5636
5637 static enum intel_display_power_domain port_to_power_domain(enum port port)
5638 {
5639         switch (port) {
5640         case PORT_A:
5641                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5642         case PORT_B:
5643                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5644         case PORT_C:
5645                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5646         case PORT_D:
5647                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5648         case PORT_E:
5649                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5650         default:
5651                 MISSING_CASE(port);
5652                 return POWER_DOMAIN_PORT_OTHER;
5653         }
5654 }
5655
5656 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5657 {
5658         switch (port) {
5659         case PORT_A:
5660                 return POWER_DOMAIN_AUX_A;
5661         case PORT_B:
5662                 return POWER_DOMAIN_AUX_B;
5663         case PORT_C:
5664                 return POWER_DOMAIN_AUX_C;
5665         case PORT_D:
5666                 return POWER_DOMAIN_AUX_D;
5667         case PORT_E:
5668                 /* FIXME: Check VBT for actual wiring of PORT E */
5669                 return POWER_DOMAIN_AUX_D;
5670         default:
5671                 MISSING_CASE(port);
5672                 return POWER_DOMAIN_AUX_A;
5673         }
5674 }
5675
5676 enum intel_display_power_domain
5677 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5678 {
5679         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5680         struct intel_digital_port *intel_dig_port;
5681
5682         switch (intel_encoder->type) {
5683         case INTEL_OUTPUT_UNKNOWN:
5684                 /* Only DDI platforms should ever use this output type */
5685                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5686         case INTEL_OUTPUT_DP:
5687         case INTEL_OUTPUT_HDMI:
5688         case INTEL_OUTPUT_EDP:
5689                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5690                 return port_to_power_domain(intel_dig_port->port);
5691         case INTEL_OUTPUT_DP_MST:
5692                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5693                 return port_to_power_domain(intel_dig_port->port);
5694         case INTEL_OUTPUT_ANALOG:
5695                 return POWER_DOMAIN_PORT_CRT;
5696         case INTEL_OUTPUT_DSI:
5697                 return POWER_DOMAIN_PORT_DSI;
5698         default:
5699                 return POWER_DOMAIN_PORT_OTHER;
5700         }
5701 }
5702
5703 enum intel_display_power_domain
5704 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5705 {
5706         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5707         struct intel_digital_port *intel_dig_port;
5708
5709         switch (intel_encoder->type) {
5710         case INTEL_OUTPUT_UNKNOWN:
5711         case INTEL_OUTPUT_HDMI:
5712                 /*
5713                  * Only DDI platforms should ever use these output types.
5714                  * We can get here after the HDMI detect code has already set
5715                  * the type of the shared encoder. Since we can't be sure
5716                  * what's the status of the given connectors, play safe and
5717                  * run the DP detection too.
5718                  */
5719                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5720         case INTEL_OUTPUT_DP:
5721         case INTEL_OUTPUT_EDP:
5722                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5723                 return port_to_aux_power_domain(intel_dig_port->port);
5724         case INTEL_OUTPUT_DP_MST:
5725                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5726                 return port_to_aux_power_domain(intel_dig_port->port);
5727         default:
5728                 MISSING_CASE(intel_encoder->type);
5729                 return POWER_DOMAIN_AUX_A;
5730         }
5731 }
5732
5733 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5734                                             struct intel_crtc_state *crtc_state)
5735 {
5736         struct drm_device *dev = crtc->dev;
5737         struct drm_encoder *encoder;
5738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5739         enum pipe pipe = intel_crtc->pipe;
5740         unsigned long mask;
5741         enum transcoder transcoder = crtc_state->cpu_transcoder;
5742
5743         if (!crtc_state->base.active)
5744                 return 0;
5745
5746         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5747         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5748         if (crtc_state->pch_pfit.enabled ||
5749             crtc_state->pch_pfit.force_thru)
5750                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5751
5752         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5753                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5754
5755                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5756         }
5757
5758         if (crtc_state->shared_dpll)
5759                 mask |= BIT(POWER_DOMAIN_PLLS);
5760
5761         return mask;
5762 }
5763
5764 static unsigned long
5765 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5766                                struct intel_crtc_state *crtc_state)
5767 {
5768         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5770         enum intel_display_power_domain domain;
5771         unsigned long domains, new_domains, old_domains;
5772
5773         old_domains = intel_crtc->enabled_power_domains;
5774         intel_crtc->enabled_power_domains = new_domains =
5775                 get_crtc_power_domains(crtc, crtc_state);
5776
5777         domains = new_domains & ~old_domains;
5778
5779         for_each_power_domain(domain, domains)
5780                 intel_display_power_get(dev_priv, domain);
5781
5782         return old_domains & ~new_domains;
5783 }
5784
5785 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5786                                       unsigned long domains)
5787 {
5788         enum intel_display_power_domain domain;
5789
5790         for_each_power_domain(domain, domains)
5791                 intel_display_power_put(dev_priv, domain);
5792 }
5793
5794 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5795 {
5796         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5797
5798         if (IS_GEMINILAKE(dev_priv))
5799                 return 2 * max_cdclk_freq;
5800         else if (INTEL_INFO(dev_priv)->gen >= 9 ||
5801                  IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5802                 return max_cdclk_freq;
5803         else if (IS_CHERRYVIEW(dev_priv))
5804                 return max_cdclk_freq*95/100;
5805         else if (INTEL_INFO(dev_priv)->gen < 4)
5806                 return 2*max_cdclk_freq*90/100;
5807         else
5808                 return max_cdclk_freq*90/100;
5809 }
5810
5811 static int skl_calc_cdclk(int max_pixclk, int vco);
5812
5813 static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
5814 {
5815         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5816                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5817                 int max_cdclk, vco;
5818
5819                 vco = dev_priv->skl_preferred_vco_freq;
5820                 WARN_ON(vco != 8100000 && vco != 8640000);
5821
5822                 /*
5823                  * Use the lower (vco 8640) cdclk values as a
5824                  * first guess. skl_calc_cdclk() will correct it
5825                  * if the preferred vco is 8100 instead.
5826                  */
5827                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5828                         max_cdclk = 617143;
5829                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5830                         max_cdclk = 540000;
5831                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5832                         max_cdclk = 432000;
5833                 else
5834                         max_cdclk = 308571;
5835
5836                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5837         } else if (IS_GEMINILAKE(dev_priv)) {
5838                 dev_priv->max_cdclk_freq = 316800;
5839         } else if (IS_BROXTON(dev_priv)) {
5840                 dev_priv->max_cdclk_freq = 624000;
5841         } else if (IS_BROADWELL(dev_priv))  {
5842                 /*
5843                  * FIXME with extra cooling we can allow
5844                  * 540 MHz for ULX and 675 Mhz for ULT.
5845                  * How can we know if extra cooling is
5846                  * available? PCI ID, VTB, something else?
5847                  */
5848                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5849                         dev_priv->max_cdclk_freq = 450000;
5850                 else if (IS_BDW_ULX(dev_priv))
5851                         dev_priv->max_cdclk_freq = 450000;
5852                 else if (IS_BDW_ULT(dev_priv))
5853                         dev_priv->max_cdclk_freq = 540000;
5854                 else
5855                         dev_priv->max_cdclk_freq = 675000;
5856         } else if (IS_CHERRYVIEW(dev_priv)) {
5857                 dev_priv->max_cdclk_freq = 320000;
5858         } else if (IS_VALLEYVIEW(dev_priv)) {
5859                 dev_priv->max_cdclk_freq = 400000;
5860         } else {
5861                 /* otherwise assume cdclk is fixed */
5862                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5863         }
5864
5865         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5866
5867         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5868                          dev_priv->max_cdclk_freq);
5869
5870         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5871                          dev_priv->max_dotclk_freq);
5872 }
5873
5874 static void intel_update_cdclk(struct drm_i915_private *dev_priv)
5875 {
5876         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv);
5877
5878         if (INTEL_GEN(dev_priv) >= 9)
5879                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5880                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5881                                  dev_priv->cdclk_pll.ref);
5882         else
5883                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5884                                  dev_priv->cdclk_freq);
5885
5886         /*
5887          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5888          * Programmng [sic] note: bit[9:2] should be programmed to the number
5889          * of cdclk that generates 4MHz reference clock freq which is used to
5890          * generate GMBus clock. This will vary with the cdclk freq.
5891          */
5892         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5893                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5894 }
5895
5896 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5897 static int skl_cdclk_decimal(int cdclk)
5898 {
5899         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5900 }
5901
5902 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5903 {
5904         int ratio;
5905
5906         if (cdclk == dev_priv->cdclk_pll.ref)
5907                 return 0;
5908
5909         switch (cdclk) {
5910         default:
5911                 MISSING_CASE(cdclk);
5912         case 144000:
5913         case 288000:
5914         case 384000:
5915         case 576000:
5916                 ratio = 60;
5917                 break;
5918         case 624000:
5919                 ratio = 65;
5920                 break;
5921         }
5922
5923         return dev_priv->cdclk_pll.ref * ratio;
5924 }
5925
5926 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5927 {
5928         int ratio;
5929
5930         if (cdclk == dev_priv->cdclk_pll.ref)
5931                 return 0;
5932
5933         switch (cdclk) {
5934         default:
5935                 MISSING_CASE(cdclk);
5936         case  79200:
5937         case 158400:
5938         case 316800:
5939                 ratio = 33;
5940                 break;
5941         }
5942
5943         return dev_priv->cdclk_pll.ref * ratio;
5944 }
5945
5946 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5947 {
5948         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5949
5950         /* Timeout 200us */
5951         if (intel_wait_for_register(dev_priv,
5952                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5953                                     1))
5954                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5955
5956         dev_priv->cdclk_pll.vco = 0;
5957 }
5958
5959 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5960 {
5961         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5962         u32 val;
5963
5964         val = I915_READ(BXT_DE_PLL_CTL);
5965         val &= ~BXT_DE_PLL_RATIO_MASK;
5966         val |= BXT_DE_PLL_RATIO(ratio);
5967         I915_WRITE(BXT_DE_PLL_CTL, val);
5968
5969         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5970
5971         /* Timeout 200us */
5972         if (intel_wait_for_register(dev_priv,
5973                                     BXT_DE_PLL_ENABLE,
5974                                     BXT_DE_PLL_LOCK,
5975                                     BXT_DE_PLL_LOCK,
5976                                     1))
5977                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5978
5979         dev_priv->cdclk_pll.vco = vco;
5980 }
5981
5982 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5983 {
5984         u32 val, divider;
5985         int vco, ret;
5986
5987         if (IS_GEMINILAKE(dev_priv))
5988                 vco = glk_de_pll_vco(dev_priv, cdclk);
5989         else
5990                 vco = bxt_de_pll_vco(dev_priv, cdclk);
5991
5992         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5993
5994         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5995         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5996         case 8:
5997                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5998                 break;
5999         case 4:
6000                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
6001                 break;
6002         case 3:
6003                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
6004                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
6005                 break;
6006         case 2:
6007                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6008                 break;
6009         default:
6010                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6011                 WARN_ON(vco != 0);
6012
6013                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6014                 break;
6015         }
6016
6017         /* Inform power controller of upcoming frequency change */
6018         mutex_lock(&dev_priv->rps.hw_lock);
6019         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6020                                       0x80000000);
6021         mutex_unlock(&dev_priv->rps.hw_lock);
6022
6023         if (ret) {
6024                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6025                           ret, cdclk);
6026                 return;
6027         }
6028
6029         if (dev_priv->cdclk_pll.vco != 0 &&
6030             dev_priv->cdclk_pll.vco != vco)
6031                 bxt_de_pll_disable(dev_priv);
6032
6033         if (dev_priv->cdclk_pll.vco != vco)
6034                 bxt_de_pll_enable(dev_priv, vco);
6035
6036         val = divider | skl_cdclk_decimal(cdclk);
6037         /*
6038          * FIXME if only the cd2x divider needs changing, it could be done
6039          * without shutting off the pipe (if only one pipe is active).
6040          */
6041         val |= BXT_CDCLK_CD2X_PIPE_NONE;
6042         /*
6043          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6044          * enable otherwise.
6045          */
6046         if (cdclk >= 500000)
6047                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6048         I915_WRITE(CDCLK_CTL, val);
6049
6050         mutex_lock(&dev_priv->rps.hw_lock);
6051         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6052                                       DIV_ROUND_UP(cdclk, 25000));
6053         mutex_unlock(&dev_priv->rps.hw_lock);
6054
6055         if (ret) {
6056                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6057                           ret, cdclk);
6058                 return;
6059         }
6060
6061         intel_update_cdclk(dev_priv);
6062 }
6063
6064 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6065 {
6066         u32 cdctl, expected;
6067
6068         intel_update_cdclk(dev_priv);
6069
6070         if (dev_priv->cdclk_pll.vco == 0 ||
6071             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6072                 goto sanitize;
6073
6074         /* DPLL okay; verify the cdclock
6075          *
6076          * Some BIOS versions leave an incorrect decimal frequency value and
6077          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6078          * so sanitize this register.
6079          */
6080         cdctl = I915_READ(CDCLK_CTL);
6081         /*
6082          * Let's ignore the pipe field, since BIOS could have configured the
6083          * dividers both synching to an active pipe, or asynchronously
6084          * (PIPE_NONE).
6085          */
6086         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6087
6088         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6089                    skl_cdclk_decimal(dev_priv->cdclk_freq);
6090         /*
6091          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6092          * enable otherwise.
6093          */
6094         if (dev_priv->cdclk_freq >= 500000)
6095                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6096
6097         if (cdctl == expected)
6098                 /* All well; nothing to sanitize */
6099                 return;
6100
6101 sanitize:
6102         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6103
6104         /* force cdclk programming */
6105         dev_priv->cdclk_freq = 0;
6106
6107         /* force full PLL disable + enable */
6108         dev_priv->cdclk_pll.vco = -1;
6109 }
6110
6111 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6112 {
6113         int cdclk;
6114
6115         bxt_sanitize_cdclk(dev_priv);
6116
6117         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6118                 return;
6119
6120         /*
6121          * FIXME:
6122          * - The initial CDCLK needs to be read from VBT.
6123          *   Need to make this change after VBT has changes for BXT.
6124          */
6125         if (IS_GEMINILAKE(dev_priv))
6126                 cdclk = glk_calc_cdclk(0);
6127         else
6128                 cdclk = bxt_calc_cdclk(0);
6129
6130         bxt_set_cdclk(dev_priv, cdclk);
6131 }
6132
6133 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6134 {
6135         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6136 }
6137
6138 static int skl_calc_cdclk(int max_pixclk, int vco)
6139 {
6140         if (vco == 8640000) {
6141                 if (max_pixclk > 540000)
6142                         return 617143;
6143                 else if (max_pixclk > 432000)
6144                         return 540000;
6145                 else if (max_pixclk > 308571)
6146                         return 432000;
6147                 else
6148                         return 308571;
6149         } else {
6150                 if (max_pixclk > 540000)
6151                         return 675000;
6152                 else if (max_pixclk > 450000)
6153                         return 540000;
6154                 else if (max_pixclk > 337500)
6155                         return 450000;
6156                 else
6157                         return 337500;
6158         }
6159 }
6160
6161 static void
6162 skl_dpll0_update(struct drm_i915_private *dev_priv)
6163 {
6164         u32 val;
6165
6166         dev_priv->cdclk_pll.ref = 24000;
6167         dev_priv->cdclk_pll.vco = 0;
6168
6169         val = I915_READ(LCPLL1_CTL);
6170         if ((val & LCPLL_PLL_ENABLE) == 0)
6171                 return;
6172
6173         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6174                 return;
6175
6176         val = I915_READ(DPLL_CTRL1);
6177
6178         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6179                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6180                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6181                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6182                 return;
6183
6184         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6185         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6186         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6187         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6188         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6189                 dev_priv->cdclk_pll.vco = 8100000;
6190                 break;
6191         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6192         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6193                 dev_priv->cdclk_pll.vco = 8640000;
6194                 break;
6195         default:
6196                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6197                 break;
6198         }
6199 }
6200
6201 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6202 {
6203         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6204
6205         dev_priv->skl_preferred_vco_freq = vco;
6206
6207         if (changed)
6208                 intel_update_max_cdclk(dev_priv);
6209 }
6210
6211 static void
6212 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6213 {
6214         int min_cdclk = skl_calc_cdclk(0, vco);
6215         u32 val;
6216
6217         WARN_ON(vco != 8100000 && vco != 8640000);
6218
6219         /* select the minimum CDCLK before enabling DPLL 0 */
6220         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6221         I915_WRITE(CDCLK_CTL, val);
6222         POSTING_READ(CDCLK_CTL);
6223
6224         /*
6225          * We always enable DPLL0 with the lowest link rate possible, but still
6226          * taking into account the VCO required to operate the eDP panel at the
6227          * desired frequency. The usual DP link rates operate with a VCO of
6228          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6229          * The modeset code is responsible for the selection of the exact link
6230          * rate later on, with the constraint of choosing a frequency that
6231          * works with vco.
6232          */
6233         val = I915_READ(DPLL_CTRL1);
6234
6235         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6236                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6237         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6238         if (vco == 8640000)
6239                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6240                                             SKL_DPLL0);
6241         else
6242                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6243                                             SKL_DPLL0);
6244
6245         I915_WRITE(DPLL_CTRL1, val);
6246         POSTING_READ(DPLL_CTRL1);
6247
6248         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6249
6250         if (intel_wait_for_register(dev_priv,
6251                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6252                                     5))
6253                 DRM_ERROR("DPLL0 not locked\n");
6254
6255         dev_priv->cdclk_pll.vco = vco;
6256
6257         /* We'll want to keep using the current vco from now on. */
6258         skl_set_preferred_cdclk_vco(dev_priv, vco);
6259 }
6260
6261 static void
6262 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6263 {
6264         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6265         if (intel_wait_for_register(dev_priv,
6266                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6267                                    1))
6268                 DRM_ERROR("Couldn't disable DPLL0\n");
6269
6270         dev_priv->cdclk_pll.vco = 0;
6271 }
6272
6273 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6274 {
6275         u32 freq_select, pcu_ack;
6276         int ret;
6277
6278         WARN_ON((cdclk == 24000) != (vco == 0));
6279
6280         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6281
6282         mutex_lock(&dev_priv->rps.hw_lock);
6283         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
6284                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
6285                                 SKL_CDCLK_READY_FOR_CHANGE,
6286                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
6287         mutex_unlock(&dev_priv->rps.hw_lock);
6288         if (ret) {
6289                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
6290                           ret);
6291                 return;
6292         }
6293
6294         /* set CDCLK_CTL */
6295         switch (cdclk) {
6296         case 450000:
6297         case 432000:
6298                 freq_select = CDCLK_FREQ_450_432;
6299                 pcu_ack = 1;
6300                 break;
6301         case 540000:
6302                 freq_select = CDCLK_FREQ_540;
6303                 pcu_ack = 2;
6304                 break;
6305         case 308571:
6306         case 337500:
6307         default:
6308                 freq_select = CDCLK_FREQ_337_308;
6309                 pcu_ack = 0;
6310                 break;
6311         case 617143:
6312         case 675000:
6313                 freq_select = CDCLK_FREQ_675_617;
6314                 pcu_ack = 3;
6315                 break;
6316         }
6317
6318         if (dev_priv->cdclk_pll.vco != 0 &&
6319             dev_priv->cdclk_pll.vco != vco)
6320                 skl_dpll0_disable(dev_priv);
6321
6322         if (dev_priv->cdclk_pll.vco != vco)
6323                 skl_dpll0_enable(dev_priv, vco);
6324
6325         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6326         POSTING_READ(CDCLK_CTL);
6327
6328         /* inform PCU of the change */
6329         mutex_lock(&dev_priv->rps.hw_lock);
6330         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6331         mutex_unlock(&dev_priv->rps.hw_lock);
6332
6333         intel_update_cdclk(dev_priv);
6334 }
6335
6336 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6337
6338 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6339 {
6340         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6341 }
6342
6343 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6344 {
6345         int cdclk, vco;
6346
6347         skl_sanitize_cdclk(dev_priv);
6348
6349         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6350                 /*
6351                  * Use the current vco as our initial
6352                  * guess as to what the preferred vco is.
6353                  */
6354                 if (dev_priv->skl_preferred_vco_freq == 0)
6355                         skl_set_preferred_cdclk_vco(dev_priv,
6356                                                     dev_priv->cdclk_pll.vco);
6357                 return;
6358         }
6359
6360         vco = dev_priv->skl_preferred_vco_freq;
6361         if (vco == 0)
6362                 vco = 8100000;
6363         cdclk = skl_calc_cdclk(0, vco);
6364
6365         skl_set_cdclk(dev_priv, cdclk, vco);
6366 }
6367
6368 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6369 {
6370         uint32_t cdctl, expected;
6371
6372         /*
6373          * check if the pre-os intialized the display
6374          * There is SWF18 scratchpad register defined which is set by the
6375          * pre-os which can be used by the OS drivers to check the status
6376          */
6377         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6378                 goto sanitize;
6379
6380         intel_update_cdclk(dev_priv);
6381         /* Is PLL enabled and locked ? */
6382         if (dev_priv->cdclk_pll.vco == 0 ||
6383             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6384                 goto sanitize;
6385
6386         /* DPLL okay; verify the cdclock
6387          *
6388          * Noticed in some instances that the freq selection is correct but
6389          * decimal part is programmed wrong from BIOS where pre-os does not
6390          * enable display. Verify the same as well.
6391          */
6392         cdctl = I915_READ(CDCLK_CTL);
6393         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6394                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6395         if (cdctl == expected)
6396                 /* All well; nothing to sanitize */
6397                 return;
6398
6399 sanitize:
6400         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6401
6402         /* force cdclk programming */
6403         dev_priv->cdclk_freq = 0;
6404         /* force full PLL disable + enable */
6405         dev_priv->cdclk_pll.vco = -1;
6406 }
6407
6408 /* Adjust CDclk dividers to allow high res or save power if possible */
6409 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6410 {
6411         struct drm_i915_private *dev_priv = to_i915(dev);
6412         u32 val, cmd;
6413
6414         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6415                                         != dev_priv->cdclk_freq);
6416
6417         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6418                 cmd = 2;
6419         else if (cdclk == 266667)
6420                 cmd = 1;
6421         else
6422                 cmd = 0;
6423
6424         mutex_lock(&dev_priv->rps.hw_lock);
6425         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6426         val &= ~DSPFREQGUAR_MASK;
6427         val |= (cmd << DSPFREQGUAR_SHIFT);
6428         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6429         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6430                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6431                      50)) {
6432                 DRM_ERROR("timed out waiting for CDclk change\n");
6433         }
6434         mutex_unlock(&dev_priv->rps.hw_lock);
6435
6436         mutex_lock(&dev_priv->sb_lock);
6437
6438         if (cdclk == 400000) {
6439                 u32 divider;
6440
6441                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6442
6443                 /* adjust cdclk divider */
6444                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6445                 val &= ~CCK_FREQUENCY_VALUES;
6446                 val |= divider;
6447                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6448
6449                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6450                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6451                              50))
6452                         DRM_ERROR("timed out waiting for CDclk change\n");
6453         }
6454
6455         /* adjust self-refresh exit latency value */
6456         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6457         val &= ~0x7f;
6458
6459         /*
6460          * For high bandwidth configs, we set a higher latency in the bunit
6461          * so that the core display fetch happens in time to avoid underruns.
6462          */
6463         if (cdclk == 400000)
6464                 val |= 4500 / 250; /* 4.5 usec */
6465         else
6466                 val |= 3000 / 250; /* 3.0 usec */
6467         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6468
6469         mutex_unlock(&dev_priv->sb_lock);
6470
6471         intel_update_cdclk(dev_priv);
6472 }
6473
6474 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6475 {
6476         struct drm_i915_private *dev_priv = to_i915(dev);
6477         u32 val, cmd;
6478
6479         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6480                                                 != dev_priv->cdclk_freq);
6481
6482         switch (cdclk) {
6483         case 333333:
6484         case 320000:
6485         case 266667:
6486         case 200000:
6487                 break;
6488         default:
6489                 MISSING_CASE(cdclk);
6490                 return;
6491         }
6492
6493         /*
6494          * Specs are full of misinformation, but testing on actual
6495          * hardware has shown that we just need to write the desired
6496          * CCK divider into the Punit register.
6497          */
6498         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6499
6500         mutex_lock(&dev_priv->rps.hw_lock);
6501         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6502         val &= ~DSPFREQGUAR_MASK_CHV;
6503         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6504         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6505         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6506                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6507                      50)) {
6508                 DRM_ERROR("timed out waiting for CDclk change\n");
6509         }
6510         mutex_unlock(&dev_priv->rps.hw_lock);
6511
6512         intel_update_cdclk(dev_priv);
6513 }
6514
6515 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6516                                  int max_pixclk)
6517 {
6518         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6519         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6520
6521         /*
6522          * Really only a few cases to deal with, as only 4 CDclks are supported:
6523          *   200MHz
6524          *   267MHz
6525          *   320/333MHz (depends on HPLL freq)
6526          *   400MHz (VLV only)
6527          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6528          * of the lower bin and adjust if needed.
6529          *
6530          * We seem to get an unstable or solid color picture at 200MHz.
6531          * Not sure what's wrong. For now use 200MHz only when all pipes
6532          * are off.
6533          */
6534         if (!IS_CHERRYVIEW(dev_priv) &&
6535             max_pixclk > freq_320*limit/100)
6536                 return 400000;
6537         else if (max_pixclk > 266667*limit/100)
6538                 return freq_320;
6539         else if (max_pixclk > 0)
6540                 return 266667;
6541         else
6542                 return 200000;
6543 }
6544
6545 static int glk_calc_cdclk(int max_pixclk)
6546 {
6547         if (max_pixclk > 2 * 158400)
6548                 return 316800;
6549         else if (max_pixclk > 2 * 79200)
6550                 return 158400;
6551         else
6552                 return 79200;
6553 }
6554
6555 static int bxt_calc_cdclk(int max_pixclk)
6556 {
6557         if (max_pixclk > 576000)
6558                 return 624000;
6559         else if (max_pixclk > 384000)
6560                 return 576000;
6561         else if (max_pixclk > 288000)
6562                 return 384000;
6563         else if (max_pixclk > 144000)
6564                 return 288000;
6565         else
6566                 return 144000;
6567 }
6568
6569 /* Compute the max pixel clock for new configuration. */
6570 static int intel_mode_max_pixclk(struct drm_device *dev,
6571                                  struct drm_atomic_state *state)
6572 {
6573         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6574         struct drm_i915_private *dev_priv = to_i915(dev);
6575         struct drm_crtc *crtc;
6576         struct drm_crtc_state *crtc_state;
6577         unsigned max_pixclk = 0, i;
6578         enum pipe pipe;
6579
6580         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6581                sizeof(intel_state->min_pixclk));
6582
6583         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6584                 int pixclk = 0;
6585
6586                 if (crtc_state->enable)
6587                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6588
6589                 intel_state->min_pixclk[i] = pixclk;
6590         }
6591
6592         for_each_pipe(dev_priv, pipe)
6593                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6594
6595         return max_pixclk;
6596 }
6597
6598 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6599 {
6600         struct drm_device *dev = state->dev;
6601         struct drm_i915_private *dev_priv = to_i915(dev);
6602         int max_pixclk = intel_mode_max_pixclk(dev, state);
6603         struct intel_atomic_state *intel_state =
6604                 to_intel_atomic_state(state);
6605
6606         intel_state->cdclk = intel_state->dev_cdclk =
6607                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6608
6609         if (!intel_state->active_crtcs)
6610                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6611
6612         return 0;
6613 }
6614
6615 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6616 {
6617         struct drm_i915_private *dev_priv = to_i915(state->dev);
6618         int max_pixclk = ilk_max_pixel_rate(state);
6619         struct intel_atomic_state *intel_state =
6620                 to_intel_atomic_state(state);
6621         int cdclk;
6622
6623         if (IS_GEMINILAKE(dev_priv))
6624                 cdclk = glk_calc_cdclk(max_pixclk);
6625         else
6626                 cdclk = bxt_calc_cdclk(max_pixclk);
6627
6628         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
6629
6630         if (!intel_state->active_crtcs) {
6631                 if (IS_GEMINILAKE(dev_priv))
6632                         cdclk = glk_calc_cdclk(0);
6633                 else
6634                         cdclk = bxt_calc_cdclk(0);
6635
6636                 intel_state->dev_cdclk = cdclk;
6637         }
6638
6639         return 0;
6640 }
6641
6642 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6643 {
6644         unsigned int credits, default_credits;
6645
6646         if (IS_CHERRYVIEW(dev_priv))
6647                 default_credits = PFI_CREDIT(12);
6648         else
6649                 default_credits = PFI_CREDIT(8);
6650
6651         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6652                 /* CHV suggested value is 31 or 63 */
6653                 if (IS_CHERRYVIEW(dev_priv))
6654                         credits = PFI_CREDIT_63;
6655                 else
6656                         credits = PFI_CREDIT(15);
6657         } else {
6658                 credits = default_credits;
6659         }
6660
6661         /*
6662          * WA - write default credits before re-programming
6663          * FIXME: should we also set the resend bit here?
6664          */
6665         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6666                    default_credits);
6667
6668         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6669                    credits | PFI_CREDIT_RESEND);
6670
6671         /*
6672          * FIXME is this guaranteed to clear
6673          * immediately or should we poll for it?
6674          */
6675         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6676 }
6677
6678 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6679 {
6680         struct drm_device *dev = old_state->dev;
6681         struct drm_i915_private *dev_priv = to_i915(dev);
6682         struct intel_atomic_state *old_intel_state =
6683                 to_intel_atomic_state(old_state);
6684         unsigned req_cdclk = old_intel_state->dev_cdclk;
6685
6686         /*
6687          * FIXME: We can end up here with all power domains off, yet
6688          * with a CDCLK frequency other than the minimum. To account
6689          * for this take the PIPE-A power domain, which covers the HW
6690          * blocks needed for the following programming. This can be
6691          * removed once it's guaranteed that we get here either with
6692          * the minimum CDCLK set, or the required power domains
6693          * enabled.
6694          */
6695         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6696
6697         if (IS_CHERRYVIEW(dev_priv))
6698                 cherryview_set_cdclk(dev, req_cdclk);
6699         else
6700                 valleyview_set_cdclk(dev, req_cdclk);
6701
6702         vlv_program_pfi_credits(dev_priv);
6703
6704         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6705 }
6706
6707 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6708                                    struct drm_atomic_state *old_state)
6709 {
6710         struct drm_crtc *crtc = pipe_config->base.crtc;
6711         struct drm_device *dev = crtc->dev;
6712         struct drm_i915_private *dev_priv = to_i915(dev);
6713         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6714         int pipe = intel_crtc->pipe;
6715
6716         if (WARN_ON(intel_crtc->active))
6717                 return;
6718
6719         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6720                 intel_dp_set_m_n(intel_crtc, M1_N1);
6721
6722         intel_set_pipe_timings(intel_crtc);
6723         intel_set_pipe_src_size(intel_crtc);
6724
6725         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6726                 struct drm_i915_private *dev_priv = to_i915(dev);
6727
6728                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6729                 I915_WRITE(CHV_CANVAS(pipe), 0);
6730         }
6731
6732         i9xx_set_pipeconf(intel_crtc);
6733
6734         intel_crtc->active = true;
6735
6736         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6737
6738         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6739
6740         if (IS_CHERRYVIEW(dev_priv)) {
6741                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6742                 chv_enable_pll(intel_crtc, intel_crtc->config);
6743         } else {
6744                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6745                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6746         }
6747
6748         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6749
6750         i9xx_pfit_enable(intel_crtc);
6751
6752         intel_color_load_luts(&pipe_config->base);
6753
6754         intel_update_watermarks(intel_crtc);
6755         intel_enable_pipe(intel_crtc);
6756
6757         assert_vblank_disabled(crtc);
6758         drm_crtc_vblank_on(crtc);
6759
6760         intel_encoders_enable(crtc, pipe_config, old_state);
6761 }
6762
6763 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6764 {
6765         struct drm_device *dev = crtc->base.dev;
6766         struct drm_i915_private *dev_priv = to_i915(dev);
6767
6768         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6769         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6770 }
6771
6772 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6773                              struct drm_atomic_state *old_state)
6774 {
6775         struct drm_crtc *crtc = pipe_config->base.crtc;
6776         struct drm_device *dev = crtc->dev;
6777         struct drm_i915_private *dev_priv = to_i915(dev);
6778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6779         enum pipe pipe = intel_crtc->pipe;
6780
6781         if (WARN_ON(intel_crtc->active))
6782                 return;
6783
6784         i9xx_set_pll_dividers(intel_crtc);
6785
6786         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6787                 intel_dp_set_m_n(intel_crtc, M1_N1);
6788
6789         intel_set_pipe_timings(intel_crtc);
6790         intel_set_pipe_src_size(intel_crtc);
6791
6792         i9xx_set_pipeconf(intel_crtc);
6793
6794         intel_crtc->active = true;
6795
6796         if (!IS_GEN2(dev_priv))
6797                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6798
6799         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6800
6801         i9xx_enable_pll(intel_crtc);
6802
6803         i9xx_pfit_enable(intel_crtc);
6804
6805         intel_color_load_luts(&pipe_config->base);
6806
6807         intel_update_watermarks(intel_crtc);
6808         intel_enable_pipe(intel_crtc);
6809
6810         assert_vblank_disabled(crtc);
6811         drm_crtc_vblank_on(crtc);
6812
6813         intel_encoders_enable(crtc, pipe_config, old_state);
6814 }
6815
6816 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6817 {
6818         struct drm_device *dev = crtc->base.dev;
6819         struct drm_i915_private *dev_priv = to_i915(dev);
6820
6821         if (!crtc->config->gmch_pfit.control)
6822                 return;
6823
6824         assert_pipe_disabled(dev_priv, crtc->pipe);
6825
6826         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6827                          I915_READ(PFIT_CONTROL));
6828         I915_WRITE(PFIT_CONTROL, 0);
6829 }
6830
6831 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6832                               struct drm_atomic_state *old_state)
6833 {
6834         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6835         struct drm_device *dev = crtc->dev;
6836         struct drm_i915_private *dev_priv = to_i915(dev);
6837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6838         int pipe = intel_crtc->pipe;
6839
6840         /*
6841          * On gen2 planes are double buffered but the pipe isn't, so we must
6842          * wait for planes to fully turn off before disabling the pipe.
6843          */
6844         if (IS_GEN2(dev_priv))
6845                 intel_wait_for_vblank(dev_priv, pipe);
6846
6847         intel_encoders_disable(crtc, old_crtc_state, old_state);
6848
6849         drm_crtc_vblank_off(crtc);
6850         assert_vblank_disabled(crtc);
6851
6852         intel_disable_pipe(intel_crtc);
6853
6854         i9xx_pfit_disable(intel_crtc);
6855
6856         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6857
6858         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6859                 if (IS_CHERRYVIEW(dev_priv))
6860                         chv_disable_pll(dev_priv, pipe);
6861                 else if (IS_VALLEYVIEW(dev_priv))
6862                         vlv_disable_pll(dev_priv, pipe);
6863                 else
6864                         i9xx_disable_pll(intel_crtc);
6865         }
6866
6867         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6868
6869         if (!IS_GEN2(dev_priv))
6870                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6871 }
6872
6873 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6874 {
6875         struct intel_encoder *encoder;
6876         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6877         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6878         enum intel_display_power_domain domain;
6879         unsigned long domains;
6880         struct drm_atomic_state *state;
6881         struct intel_crtc_state *crtc_state;
6882         int ret;
6883
6884         if (!intel_crtc->active)
6885                 return;
6886
6887         if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6888                 WARN_ON(intel_crtc->flip_work);
6889
6890                 intel_pre_disable_primary_noatomic(crtc);
6891
6892                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6893                 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6894         }
6895
6896         state = drm_atomic_state_alloc(crtc->dev);
6897         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6898
6899         /* Everything's already locked, -EDEADLK can't happen. */
6900         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6901         ret = drm_atomic_add_affected_connectors(state, crtc);
6902
6903         WARN_ON(IS_ERR(crtc_state) || ret);
6904
6905         dev_priv->display.crtc_disable(crtc_state, state);
6906
6907         drm_atomic_state_put(state);
6908
6909         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6910                       crtc->base.id, crtc->name);
6911
6912         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6913         crtc->state->active = false;
6914         intel_crtc->active = false;
6915         crtc->enabled = false;
6916         crtc->state->connector_mask = 0;
6917         crtc->state->encoder_mask = 0;
6918
6919         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6920                 encoder->base.crtc = NULL;
6921
6922         intel_fbc_disable(intel_crtc);
6923         intel_update_watermarks(intel_crtc);
6924         intel_disable_shared_dpll(intel_crtc);
6925
6926         domains = intel_crtc->enabled_power_domains;
6927         for_each_power_domain(domain, domains)
6928                 intel_display_power_put(dev_priv, domain);
6929         intel_crtc->enabled_power_domains = 0;
6930
6931         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6932         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6933 }
6934
6935 /*
6936  * turn all crtc's off, but do not adjust state
6937  * This has to be paired with a call to intel_modeset_setup_hw_state.
6938  */
6939 int intel_display_suspend(struct drm_device *dev)
6940 {
6941         struct drm_i915_private *dev_priv = to_i915(dev);
6942         struct drm_atomic_state *state;
6943         int ret;
6944
6945         state = drm_atomic_helper_suspend(dev);
6946         ret = PTR_ERR_OR_ZERO(state);
6947         if (ret)
6948                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6949         else
6950                 dev_priv->modeset_restore_state = state;
6951         return ret;
6952 }
6953
6954 void intel_encoder_destroy(struct drm_encoder *encoder)
6955 {
6956         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6957
6958         drm_encoder_cleanup(encoder);
6959         kfree(intel_encoder);
6960 }
6961
6962 /* Cross check the actual hw state with our own modeset state tracking (and it's
6963  * internal consistency). */
6964 static void intel_connector_verify_state(struct intel_connector *connector)
6965 {
6966         struct drm_crtc *crtc = connector->base.state->crtc;
6967
6968         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6969                       connector->base.base.id,
6970                       connector->base.name);
6971
6972         if (connector->get_hw_state(connector)) {
6973                 struct intel_encoder *encoder = connector->encoder;
6974                 struct drm_connector_state *conn_state = connector->base.state;
6975
6976                 I915_STATE_WARN(!crtc,
6977                          "connector enabled without attached crtc\n");
6978
6979                 if (!crtc)
6980                         return;
6981
6982                 I915_STATE_WARN(!crtc->state->active,
6983                       "connector is active, but attached crtc isn't\n");
6984
6985                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6986                         return;
6987
6988                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6989                         "atomic encoder doesn't match attached encoder\n");
6990
6991                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6992                         "attached encoder crtc differs from connector crtc\n");
6993         } else {
6994                 I915_STATE_WARN(crtc && crtc->state->active,
6995                         "attached crtc is active, but connector isn't\n");
6996                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6997                         "best encoder set without crtc!\n");
6998         }
6999 }
7000
7001 int intel_connector_init(struct intel_connector *connector)
7002 {
7003         drm_atomic_helper_connector_reset(&connector->base);
7004
7005         if (!connector->base.state)
7006                 return -ENOMEM;
7007
7008         return 0;
7009 }
7010
7011 struct intel_connector *intel_connector_alloc(void)
7012 {
7013         struct intel_connector *connector;
7014
7015         connector = kzalloc(sizeof *connector, GFP_KERNEL);
7016         if (!connector)
7017                 return NULL;
7018
7019         if (intel_connector_init(connector) < 0) {
7020                 kfree(connector);
7021                 return NULL;
7022         }
7023
7024         return connector;
7025 }
7026
7027 /* Simple connector->get_hw_state implementation for encoders that support only
7028  * one connector and no cloning and hence the encoder state determines the state
7029  * of the connector. */
7030 bool intel_connector_get_hw_state(struct intel_connector *connector)
7031 {
7032         enum pipe pipe = 0;
7033         struct intel_encoder *encoder = connector->encoder;
7034
7035         return encoder->get_hw_state(encoder, &pipe);
7036 }
7037
7038 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7039 {
7040         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7041                 return crtc_state->fdi_lanes;
7042
7043         return 0;
7044 }
7045
7046 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7047                                      struct intel_crtc_state *pipe_config)
7048 {
7049         struct drm_i915_private *dev_priv = to_i915(dev);
7050         struct drm_atomic_state *state = pipe_config->base.state;
7051         struct intel_crtc *other_crtc;
7052         struct intel_crtc_state *other_crtc_state;
7053
7054         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7055                       pipe_name(pipe), pipe_config->fdi_lanes);
7056         if (pipe_config->fdi_lanes > 4) {
7057                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7058                               pipe_name(pipe), pipe_config->fdi_lanes);
7059                 return -EINVAL;
7060         }
7061
7062         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7063                 if (pipe_config->fdi_lanes > 2) {
7064                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7065                                       pipe_config->fdi_lanes);
7066                         return -EINVAL;
7067                 } else {
7068                         return 0;
7069                 }
7070         }
7071
7072         if (INTEL_INFO(dev_priv)->num_pipes == 2)
7073                 return 0;
7074
7075         /* Ivybridge 3 pipe is really complicated */
7076         switch (pipe) {
7077         case PIPE_A:
7078                 return 0;
7079         case PIPE_B:
7080                 if (pipe_config->fdi_lanes <= 2)
7081                         return 0;
7082
7083                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7084                 other_crtc_state =
7085                         intel_atomic_get_crtc_state(state, other_crtc);
7086                 if (IS_ERR(other_crtc_state))
7087                         return PTR_ERR(other_crtc_state);
7088
7089                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7090                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7091                                       pipe_name(pipe), pipe_config->fdi_lanes);
7092                         return -EINVAL;
7093                 }
7094                 return 0;
7095         case PIPE_C:
7096                 if (pipe_config->fdi_lanes > 2) {
7097                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7098                                       pipe_name(pipe), pipe_config->fdi_lanes);
7099                         return -EINVAL;
7100                 }
7101
7102                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7103                 other_crtc_state =
7104                         intel_atomic_get_crtc_state(state, other_crtc);
7105                 if (IS_ERR(other_crtc_state))
7106                         return PTR_ERR(other_crtc_state);
7107
7108                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7109                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7110                         return -EINVAL;
7111                 }
7112                 return 0;
7113         default:
7114                 BUG();
7115         }
7116 }
7117
7118 #define RETRY 1
7119 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7120                                        struct intel_crtc_state *pipe_config)
7121 {
7122         struct drm_device *dev = intel_crtc->base.dev;
7123         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7124         int lane, link_bw, fdi_dotclock, ret;
7125         bool needs_recompute = false;
7126
7127 retry:
7128         /* FDI is a binary signal running at ~2.7GHz, encoding
7129          * each output octet as 10 bits. The actual frequency
7130          * is stored as a divider into a 100MHz clock, and the
7131          * mode pixel clock is stored in units of 1KHz.
7132          * Hence the bw of each lane in terms of the mode signal
7133          * is:
7134          */
7135         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7136
7137         fdi_dotclock = adjusted_mode->crtc_clock;
7138
7139         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7140                                            pipe_config->pipe_bpp);
7141
7142         pipe_config->fdi_lanes = lane;
7143
7144         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7145                                link_bw, &pipe_config->fdi_m_n);
7146
7147         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7148         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7149                 pipe_config->pipe_bpp -= 2*3;
7150                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7151                               pipe_config->pipe_bpp);
7152                 needs_recompute = true;
7153                 pipe_config->bw_constrained = true;
7154
7155                 goto retry;
7156         }
7157
7158         if (needs_recompute)
7159                 return RETRY;
7160
7161         return ret;
7162 }
7163
7164 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7165                                      struct intel_crtc_state *pipe_config)
7166 {
7167         if (pipe_config->pipe_bpp > 24)
7168                 return false;
7169
7170         /* HSW can handle pixel rate up to cdclk? */
7171         if (IS_HASWELL(dev_priv))
7172                 return true;
7173
7174         /*
7175          * We compare against max which means we must take
7176          * the increased cdclk requirement into account when
7177          * calculating the new cdclk.
7178          *
7179          * Should measure whether using a lower cdclk w/o IPS
7180          */
7181         return ilk_pipe_pixel_rate(pipe_config) <=
7182                 dev_priv->max_cdclk_freq * 95 / 100;
7183 }
7184
7185 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7186                                    struct intel_crtc_state *pipe_config)
7187 {
7188         struct drm_device *dev = crtc->base.dev;
7189         struct drm_i915_private *dev_priv = to_i915(dev);
7190
7191         pipe_config->ips_enabled = i915.enable_ips &&
7192                 hsw_crtc_supports_ips(crtc) &&
7193                 pipe_config_supports_ips(dev_priv, pipe_config);
7194 }
7195
7196 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7197 {
7198         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7199
7200         /* GDG double wide on either pipe, otherwise pipe A only */
7201         return INTEL_INFO(dev_priv)->gen < 4 &&
7202                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7203 }
7204
7205 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7206                                      struct intel_crtc_state *pipe_config)
7207 {
7208         struct drm_device *dev = crtc->base.dev;
7209         struct drm_i915_private *dev_priv = to_i915(dev);
7210         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7211         int clock_limit = dev_priv->max_dotclk_freq;
7212
7213         if (INTEL_GEN(dev_priv) < 4) {
7214                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7215
7216                 /*
7217                  * Enable double wide mode when the dot clock
7218                  * is > 90% of the (display) core speed.
7219                  */
7220                 if (intel_crtc_supports_double_wide(crtc) &&
7221                     adjusted_mode->crtc_clock > clock_limit) {
7222                         clock_limit = dev_priv->max_dotclk_freq;
7223                         pipe_config->double_wide = true;
7224                 }
7225         }
7226
7227         if (adjusted_mode->crtc_clock > clock_limit) {
7228                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7229                               adjusted_mode->crtc_clock, clock_limit,
7230                               yesno(pipe_config->double_wide));
7231                 return -EINVAL;
7232         }
7233
7234         /*
7235          * Pipe horizontal size must be even in:
7236          * - DVO ganged mode
7237          * - LVDS dual channel mode
7238          * - Double wide pipe
7239          */
7240         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7241              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7242                 pipe_config->pipe_src_w &= ~1;
7243
7244         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7245          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7246          */
7247         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7248                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7249                 return -EINVAL;
7250
7251         if (HAS_IPS(dev_priv))
7252                 hsw_compute_ips_config(crtc, pipe_config);
7253
7254         if (pipe_config->has_pch_encoder)
7255                 return ironlake_fdi_compute_config(crtc, pipe_config);
7256
7257         return 0;
7258 }
7259
7260 static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv)
7261 {
7262         u32 cdctl;
7263
7264         skl_dpll0_update(dev_priv);
7265
7266         if (dev_priv->cdclk_pll.vco == 0)
7267                 return dev_priv->cdclk_pll.ref;
7268
7269         cdctl = I915_READ(CDCLK_CTL);
7270
7271         if (dev_priv->cdclk_pll.vco == 8640000) {
7272                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7273                 case CDCLK_FREQ_450_432:
7274                         return 432000;
7275                 case CDCLK_FREQ_337_308:
7276                         return 308571;
7277                 case CDCLK_FREQ_540:
7278                         return 540000;
7279                 case CDCLK_FREQ_675_617:
7280                         return 617143;
7281                 default:
7282                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7283                 }
7284         } else {
7285                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7286                 case CDCLK_FREQ_450_432:
7287                         return 450000;
7288                 case CDCLK_FREQ_337_308:
7289                         return 337500;
7290                 case CDCLK_FREQ_540:
7291                         return 540000;
7292                 case CDCLK_FREQ_675_617:
7293                         return 675000;
7294                 default:
7295                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7296                 }
7297         }
7298
7299         return dev_priv->cdclk_pll.ref;
7300 }
7301
7302 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7303 {
7304         u32 val;
7305
7306         dev_priv->cdclk_pll.ref = 19200;
7307         dev_priv->cdclk_pll.vco = 0;
7308
7309         val = I915_READ(BXT_DE_PLL_ENABLE);
7310         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7311                 return;
7312
7313         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7314                 return;
7315
7316         val = I915_READ(BXT_DE_PLL_CTL);
7317         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7318                 dev_priv->cdclk_pll.ref;
7319 }
7320
7321 static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
7322 {
7323         u32 divider;
7324         int div, vco;
7325
7326         bxt_de_pll_update(dev_priv);
7327
7328         vco = dev_priv->cdclk_pll.vco;
7329         if (vco == 0)
7330                 return dev_priv->cdclk_pll.ref;
7331
7332         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7333
7334         switch (divider) {
7335         case BXT_CDCLK_CD2X_DIV_SEL_1:
7336                 div = 2;
7337                 break;
7338         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7339                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
7340                 div = 3;
7341                 break;
7342         case BXT_CDCLK_CD2X_DIV_SEL_2:
7343                 div = 4;
7344                 break;
7345         case BXT_CDCLK_CD2X_DIV_SEL_4:
7346                 div = 8;
7347                 break;
7348         default:
7349                 MISSING_CASE(divider);
7350                 return dev_priv->cdclk_pll.ref;
7351         }
7352
7353         return DIV_ROUND_CLOSEST(vco, div);
7354 }
7355
7356 static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7357 {
7358         uint32_t lcpll = I915_READ(LCPLL_CTL);
7359         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7360
7361         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7362                 return 800000;
7363         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7364                 return 450000;
7365         else if (freq == LCPLL_CLK_FREQ_450)
7366                 return 450000;
7367         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7368                 return 540000;
7369         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7370                 return 337500;
7371         else
7372                 return 675000;
7373 }
7374
7375 static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7376 {
7377         uint32_t lcpll = I915_READ(LCPLL_CTL);
7378         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7379
7380         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7381                 return 800000;
7382         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7383                 return 450000;
7384         else if (freq == LCPLL_CLK_FREQ_450)
7385                 return 450000;
7386         else if (IS_HSW_ULT(dev_priv))
7387                 return 337500;
7388         else
7389                 return 540000;
7390 }
7391
7392 static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv)
7393 {
7394         return vlv_get_cck_clock_hpll(dev_priv, "cdclk",
7395                                       CCK_DISPLAY_CLOCK_CONTROL);
7396 }
7397
7398 static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv)
7399 {
7400         return 450000;
7401 }
7402
7403 static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv)
7404 {
7405         return 400000;
7406 }
7407
7408 static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv)
7409 {
7410         return 333333;
7411 }
7412
7413 static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv)
7414 {
7415         return 200000;
7416 }
7417
7418 static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv)
7419 {
7420         struct pci_dev *pdev = dev_priv->drm.pdev;
7421         u16 gcfgc = 0;
7422
7423         pci_read_config_word(pdev, GCFGC, &gcfgc);
7424
7425         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7426         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7427                 return 266667;
7428         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7429                 return 333333;
7430         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7431                 return 444444;
7432         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7433                 return 200000;
7434         default:
7435                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7436         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7437                 return 133333;
7438         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7439                 return 166667;
7440         }
7441 }
7442
7443 static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7444 {
7445         struct pci_dev *pdev = dev_priv->drm.pdev;
7446         u16 gcfgc = 0;
7447
7448         pci_read_config_word(pdev, GCFGC, &gcfgc);
7449
7450         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7451                 return 133333;
7452         else {
7453                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7454                 case GC_DISPLAY_CLOCK_333_MHZ:
7455                         return 333333;
7456                 default:
7457                 case GC_DISPLAY_CLOCK_190_200_MHZ:
7458                         return 190000;
7459                 }
7460         }
7461 }
7462
7463 static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv)
7464 {
7465         return 266667;
7466 }
7467
7468 static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv)
7469 {
7470         struct pci_dev *pdev = dev_priv->drm.pdev;
7471         u16 hpllcc = 0;
7472
7473         /*
7474          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7475          * encoding is different :(
7476          * FIXME is this the right way to detect 852GM/852GMV?
7477          */
7478         if (pdev->revision == 0x1)
7479                 return 133333;
7480
7481         pci_bus_read_config_word(pdev->bus,
7482                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7483
7484         /* Assume that the hardware is in the high speed state.  This
7485          * should be the default.
7486          */
7487         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7488         case GC_CLOCK_133_200:
7489         case GC_CLOCK_133_200_2:
7490         case GC_CLOCK_100_200:
7491                 return 200000;
7492         case GC_CLOCK_166_250:
7493                 return 250000;
7494         case GC_CLOCK_100_133:
7495                 return 133333;
7496         case GC_CLOCK_133_266:
7497         case GC_CLOCK_133_266_2:
7498         case GC_CLOCK_166_266:
7499                 return 266667;
7500         }
7501
7502         /* Shouldn't happen */
7503         return 0;
7504 }
7505
7506 static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv)
7507 {
7508         return 133333;
7509 }
7510
7511 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
7512 {
7513         static const unsigned int blb_vco[8] = {
7514                 [0] = 3200000,
7515                 [1] = 4000000,
7516                 [2] = 5333333,
7517                 [3] = 4800000,
7518                 [4] = 6400000,
7519         };
7520         static const unsigned int pnv_vco[8] = {
7521                 [0] = 3200000,
7522                 [1] = 4000000,
7523                 [2] = 5333333,
7524                 [3] = 4800000,
7525                 [4] = 2666667,
7526         };
7527         static const unsigned int cl_vco[8] = {
7528                 [0] = 3200000,
7529                 [1] = 4000000,
7530                 [2] = 5333333,
7531                 [3] = 6400000,
7532                 [4] = 3333333,
7533                 [5] = 3566667,
7534                 [6] = 4266667,
7535         };
7536         static const unsigned int elk_vco[8] = {
7537                 [0] = 3200000,
7538                 [1] = 4000000,
7539                 [2] = 5333333,
7540                 [3] = 4800000,
7541         };
7542         static const unsigned int ctg_vco[8] = {
7543                 [0] = 3200000,
7544                 [1] = 4000000,
7545                 [2] = 5333333,
7546                 [3] = 6400000,
7547                 [4] = 2666667,
7548                 [5] = 4266667,
7549         };
7550         const unsigned int *vco_table;
7551         unsigned int vco;
7552         uint8_t tmp = 0;
7553
7554         /* FIXME other chipsets? */
7555         if (IS_GM45(dev_priv))
7556                 vco_table = ctg_vco;
7557         else if (IS_G4X(dev_priv))
7558                 vco_table = elk_vco;
7559         else if (IS_I965GM(dev_priv))
7560                 vco_table = cl_vco;
7561         else if (IS_PINEVIEW(dev_priv))
7562                 vco_table = pnv_vco;
7563         else if (IS_G33(dev_priv))
7564                 vco_table = blb_vco;
7565         else
7566                 return 0;
7567
7568         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
7569
7570         vco = vco_table[tmp & 0x7];
7571         if (vco == 0)
7572                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7573         else
7574                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7575
7576         return vco;
7577 }
7578
7579 static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv)
7580 {
7581         struct pci_dev *pdev = dev_priv->drm.pdev;
7582         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7583         uint16_t tmp = 0;
7584
7585         pci_read_config_word(pdev, GCFGC, &tmp);
7586
7587         cdclk_sel = (tmp >> 12) & 0x1;
7588
7589         switch (vco) {
7590         case 2666667:
7591         case 4000000:
7592         case 5333333:
7593                 return cdclk_sel ? 333333 : 222222;
7594         case 3200000:
7595                 return cdclk_sel ? 320000 : 228571;
7596         default:
7597                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7598                 return 222222;
7599         }
7600 }
7601
7602 static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7603 {
7604         struct pci_dev *pdev = dev_priv->drm.pdev;
7605         static const uint8_t div_3200[] = { 16, 10,  8 };
7606         static const uint8_t div_4000[] = { 20, 12, 10 };
7607         static const uint8_t div_5333[] = { 24, 16, 14 };
7608         const uint8_t *div_table;
7609         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7610         uint16_t tmp = 0;
7611
7612         pci_read_config_word(pdev, GCFGC, &tmp);
7613
7614         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7615
7616         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7617                 goto fail;
7618
7619         switch (vco) {
7620         case 3200000:
7621                 div_table = div_3200;
7622                 break;
7623         case 4000000:
7624                 div_table = div_4000;
7625                 break;
7626         case 5333333:
7627                 div_table = div_5333;
7628                 break;
7629         default:
7630                 goto fail;
7631         }
7632
7633         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7634
7635 fail:
7636         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7637         return 200000;
7638 }
7639
7640 static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv)
7641 {
7642         struct pci_dev *pdev = dev_priv->drm.pdev;
7643         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7644         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7645         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7646         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7647         const uint8_t *div_table;
7648         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7649         uint16_t tmp = 0;
7650
7651         pci_read_config_word(pdev, GCFGC, &tmp);
7652
7653         cdclk_sel = (tmp >> 4) & 0x7;
7654
7655         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7656                 goto fail;
7657
7658         switch (vco) {
7659         case 3200000:
7660                 div_table = div_3200;
7661                 break;
7662         case 4000000:
7663                 div_table = div_4000;
7664                 break;
7665         case 4800000:
7666                 div_table = div_4800;
7667                 break;
7668         case 5333333:
7669                 div_table = div_5333;
7670                 break;
7671         default:
7672                 goto fail;
7673         }
7674
7675         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7676
7677 fail:
7678         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7679         return 190476;
7680 }
7681
7682 static void
7683 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7684 {
7685         while (*num > DATA_LINK_M_N_MASK ||
7686                *den > DATA_LINK_M_N_MASK) {
7687                 *num >>= 1;
7688                 *den >>= 1;
7689         }
7690 }
7691
7692 static void compute_m_n(unsigned int m, unsigned int n,
7693                         uint32_t *ret_m, uint32_t *ret_n)
7694 {
7695         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7696         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7697         intel_reduce_m_n_ratio(ret_m, ret_n);
7698 }
7699
7700 void
7701 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7702                        int pixel_clock, int link_clock,
7703                        struct intel_link_m_n *m_n)
7704 {
7705         m_n->tu = 64;
7706
7707         compute_m_n(bits_per_pixel * pixel_clock,
7708                     link_clock * nlanes * 8,
7709                     &m_n->gmch_m, &m_n->gmch_n);
7710
7711         compute_m_n(pixel_clock, link_clock,
7712                     &m_n->link_m, &m_n->link_n);
7713 }
7714
7715 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7716 {
7717         if (i915.panel_use_ssc >= 0)
7718                 return i915.panel_use_ssc != 0;
7719         return dev_priv->vbt.lvds_use_ssc
7720                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7721 }
7722
7723 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7724 {
7725         return (1 << dpll->n) << 16 | dpll->m2;
7726 }
7727
7728 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7729 {
7730         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7731 }
7732
7733 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7734                                      struct intel_crtc_state *crtc_state,
7735                                      struct dpll *reduced_clock)
7736 {
7737         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7738         u32 fp, fp2 = 0;
7739
7740         if (IS_PINEVIEW(dev_priv)) {
7741                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7742                 if (reduced_clock)
7743                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7744         } else {
7745                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7746                 if (reduced_clock)
7747                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7748         }
7749
7750         crtc_state->dpll_hw_state.fp0 = fp;
7751
7752         crtc->lowfreq_avail = false;
7753         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7754             reduced_clock) {
7755                 crtc_state->dpll_hw_state.fp1 = fp2;
7756                 crtc->lowfreq_avail = true;
7757         } else {
7758                 crtc_state->dpll_hw_state.fp1 = fp;
7759         }
7760 }
7761
7762 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7763                 pipe)
7764 {
7765         u32 reg_val;
7766
7767         /*
7768          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7769          * and set it to a reasonable value instead.
7770          */
7771         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7772         reg_val &= 0xffffff00;
7773         reg_val |= 0x00000030;
7774         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7775
7776         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7777         reg_val &= 0x8cffffff;
7778         reg_val = 0x8c000000;
7779         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7780
7781         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7782         reg_val &= 0xffffff00;
7783         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7784
7785         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7786         reg_val &= 0x00ffffff;
7787         reg_val |= 0xb0000000;
7788         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7789 }
7790
7791 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7792                                          struct intel_link_m_n *m_n)
7793 {
7794         struct drm_device *dev = crtc->base.dev;
7795         struct drm_i915_private *dev_priv = to_i915(dev);
7796         int pipe = crtc->pipe;
7797
7798         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7799         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7800         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7801         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7802 }
7803
7804 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7805                                          struct intel_link_m_n *m_n,
7806                                          struct intel_link_m_n *m2_n2)
7807 {
7808         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7809         int pipe = crtc->pipe;
7810         enum transcoder transcoder = crtc->config->cpu_transcoder;
7811
7812         if (INTEL_GEN(dev_priv) >= 5) {
7813                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7814                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7815                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7816                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7817                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7818                  * for gen < 8) and if DRRS is supported (to make sure the
7819                  * registers are not unnecessarily accessed).
7820                  */
7821                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
7822                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
7823                         I915_WRITE(PIPE_DATA_M2(transcoder),
7824                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7825                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7826                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7827                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7828                 }
7829         } else {
7830                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7831                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7832                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7833                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7834         }
7835 }
7836
7837 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7838 {
7839         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7840
7841         if (m_n == M1_N1) {
7842                 dp_m_n = &crtc->config->dp_m_n;
7843                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7844         } else if (m_n == M2_N2) {
7845
7846                 /*
7847                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7848                  * needs to be programmed into M1_N1.
7849                  */
7850                 dp_m_n = &crtc->config->dp_m2_n2;
7851         } else {
7852                 DRM_ERROR("Unsupported divider value\n");
7853                 return;
7854         }
7855
7856         if (crtc->config->has_pch_encoder)
7857                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7858         else
7859                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7860 }
7861
7862 static void vlv_compute_dpll(struct intel_crtc *crtc,
7863                              struct intel_crtc_state *pipe_config)
7864 {
7865         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7866                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7867         if (crtc->pipe != PIPE_A)
7868                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7869
7870         /* DPLL not used with DSI, but still need the rest set up */
7871         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7872                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7873                         DPLL_EXT_BUFFER_ENABLE_VLV;
7874
7875         pipe_config->dpll_hw_state.dpll_md =
7876                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7877 }
7878
7879 static void chv_compute_dpll(struct intel_crtc *crtc,
7880                              struct intel_crtc_state *pipe_config)
7881 {
7882         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7883                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7884         if (crtc->pipe != PIPE_A)
7885                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7886
7887         /* DPLL not used with DSI, but still need the rest set up */
7888         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7889                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7890
7891         pipe_config->dpll_hw_state.dpll_md =
7892                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7893 }
7894
7895 static void vlv_prepare_pll(struct intel_crtc *crtc,
7896                             const struct intel_crtc_state *pipe_config)
7897 {
7898         struct drm_device *dev = crtc->base.dev;
7899         struct drm_i915_private *dev_priv = to_i915(dev);
7900         enum pipe pipe = crtc->pipe;
7901         u32 mdiv;
7902         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7903         u32 coreclk, reg_val;
7904
7905         /* Enable Refclk */
7906         I915_WRITE(DPLL(pipe),
7907                    pipe_config->dpll_hw_state.dpll &
7908                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7909
7910         /* No need to actually set up the DPLL with DSI */
7911         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7912                 return;
7913
7914         mutex_lock(&dev_priv->sb_lock);
7915
7916         bestn = pipe_config->dpll.n;
7917         bestm1 = pipe_config->dpll.m1;
7918         bestm2 = pipe_config->dpll.m2;
7919         bestp1 = pipe_config->dpll.p1;
7920         bestp2 = pipe_config->dpll.p2;
7921
7922         /* See eDP HDMI DPIO driver vbios notes doc */
7923
7924         /* PLL B needs special handling */
7925         if (pipe == PIPE_B)
7926                 vlv_pllb_recal_opamp(dev_priv, pipe);
7927
7928         /* Set up Tx target for periodic Rcomp update */
7929         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7930
7931         /* Disable target IRef on PLL */
7932         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7933         reg_val &= 0x00ffffff;
7934         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7935
7936         /* Disable fast lock */
7937         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7938
7939         /* Set idtafcrecal before PLL is enabled */
7940         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7941         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7942         mdiv |= ((bestn << DPIO_N_SHIFT));
7943         mdiv |= (1 << DPIO_K_SHIFT);
7944
7945         /*
7946          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7947          * but we don't support that).
7948          * Note: don't use the DAC post divider as it seems unstable.
7949          */
7950         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7951         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7952
7953         mdiv |= DPIO_ENABLE_CALIBRATION;
7954         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7955
7956         /* Set HBR and RBR LPF coefficients */
7957         if (pipe_config->port_clock == 162000 ||
7958             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7959             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7960                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7961                                  0x009f0003);
7962         else
7963                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7964                                  0x00d0000f);
7965
7966         if (intel_crtc_has_dp_encoder(pipe_config)) {
7967                 /* Use SSC source */
7968                 if (pipe == PIPE_A)
7969                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7970                                          0x0df40000);
7971                 else
7972                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7973                                          0x0df70000);
7974         } else { /* HDMI or VGA */
7975                 /* Use bend source */
7976                 if (pipe == PIPE_A)
7977                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7978                                          0x0df70000);
7979                 else
7980                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7981                                          0x0df40000);
7982         }
7983
7984         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7985         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7986         if (intel_crtc_has_dp_encoder(crtc->config))
7987                 coreclk |= 0x01000000;
7988         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7989
7990         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7991         mutex_unlock(&dev_priv->sb_lock);
7992 }
7993
7994 static void chv_prepare_pll(struct intel_crtc *crtc,
7995                             const struct intel_crtc_state *pipe_config)
7996 {
7997         struct drm_device *dev = crtc->base.dev;
7998         struct drm_i915_private *dev_priv = to_i915(dev);
7999         enum pipe pipe = crtc->pipe;
8000         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8001         u32 loopfilter, tribuf_calcntr;
8002         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8003         u32 dpio_val;
8004         int vco;
8005
8006         /* Enable Refclk and SSC */
8007         I915_WRITE(DPLL(pipe),
8008                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8009
8010         /* No need to actually set up the DPLL with DSI */
8011         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8012                 return;
8013
8014         bestn = pipe_config->dpll.n;
8015         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8016         bestm1 = pipe_config->dpll.m1;
8017         bestm2 = pipe_config->dpll.m2 >> 22;
8018         bestp1 = pipe_config->dpll.p1;
8019         bestp2 = pipe_config->dpll.p2;
8020         vco = pipe_config->dpll.vco;
8021         dpio_val = 0;
8022         loopfilter = 0;
8023
8024         mutex_lock(&dev_priv->sb_lock);
8025
8026         /* p1 and p2 divider */
8027         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8028                         5 << DPIO_CHV_S1_DIV_SHIFT |
8029                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8030                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8031                         1 << DPIO_CHV_K_DIV_SHIFT);
8032
8033         /* Feedback post-divider - m2 */
8034         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8035
8036         /* Feedback refclk divider - n and m1 */
8037         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8038                         DPIO_CHV_M1_DIV_BY_2 |
8039                         1 << DPIO_CHV_N_DIV_SHIFT);
8040
8041         /* M2 fraction division */
8042         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8043
8044         /* M2 fraction division enable */
8045         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8046         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8047         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8048         if (bestm2_frac)
8049                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8050         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8051
8052         /* Program digital lock detect threshold */
8053         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8054         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8055                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8056         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8057         if (!bestm2_frac)
8058                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8059         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8060
8061         /* Loop filter */
8062         if (vco == 5400000) {
8063                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8064                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8065                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8066                 tribuf_calcntr = 0x9;
8067         } else if (vco <= 6200000) {
8068                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8069                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8070                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8071                 tribuf_calcntr = 0x9;
8072         } else if (vco <= 6480000) {
8073                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8074                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8075                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8076                 tribuf_calcntr = 0x8;
8077         } else {
8078                 /* Not supported. Apply the same limits as in the max case */
8079                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8080                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8081                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8082                 tribuf_calcntr = 0;
8083         }
8084         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8085
8086         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8087         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8088         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8089         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8090
8091         /* AFC Recal */
8092         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8093                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8094                         DPIO_AFC_RECAL);
8095
8096         mutex_unlock(&dev_priv->sb_lock);
8097 }
8098
8099 /**
8100  * vlv_force_pll_on - forcibly enable just the PLL
8101  * @dev_priv: i915 private structure
8102  * @pipe: pipe PLL to enable
8103  * @dpll: PLL configuration
8104  *
8105  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8106  * in cases where we need the PLL enabled even when @pipe is not going to
8107  * be enabled.
8108  */
8109 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8110                      const struct dpll *dpll)
8111 {
8112         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8113         struct intel_crtc_state *pipe_config;
8114
8115         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8116         if (!pipe_config)
8117                 return -ENOMEM;
8118
8119         pipe_config->base.crtc = &crtc->base;
8120         pipe_config->pixel_multiplier = 1;
8121         pipe_config->dpll = *dpll;
8122
8123         if (IS_CHERRYVIEW(dev_priv)) {
8124                 chv_compute_dpll(crtc, pipe_config);
8125                 chv_prepare_pll(crtc, pipe_config);
8126                 chv_enable_pll(crtc, pipe_config);
8127         } else {
8128                 vlv_compute_dpll(crtc, pipe_config);
8129                 vlv_prepare_pll(crtc, pipe_config);
8130                 vlv_enable_pll(crtc, pipe_config);
8131         }
8132
8133         kfree(pipe_config);
8134
8135         return 0;
8136 }
8137
8138 /**
8139  * vlv_force_pll_off - forcibly disable just the PLL
8140  * @dev_priv: i915 private structure
8141  * @pipe: pipe PLL to disable
8142  *
8143  * Disable the PLL for @pipe. To be used in cases where we need
8144  * the PLL enabled even when @pipe is not going to be enabled.
8145  */
8146 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8147 {
8148         if (IS_CHERRYVIEW(dev_priv))
8149                 chv_disable_pll(dev_priv, pipe);
8150         else
8151                 vlv_disable_pll(dev_priv, pipe);
8152 }
8153
8154 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8155                               struct intel_crtc_state *crtc_state,
8156                               struct dpll *reduced_clock)
8157 {
8158         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8159         u32 dpll;
8160         struct dpll *clock = &crtc_state->dpll;
8161
8162         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8163
8164         dpll = DPLL_VGA_MODE_DIS;
8165
8166         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8167                 dpll |= DPLLB_MODE_LVDS;
8168         else
8169                 dpll |= DPLLB_MODE_DAC_SERIAL;
8170
8171         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8172             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8173                 dpll |= (crtc_state->pixel_multiplier - 1)
8174                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8175         }
8176
8177         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8178             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8179                 dpll |= DPLL_SDVO_HIGH_SPEED;
8180
8181         if (intel_crtc_has_dp_encoder(crtc_state))
8182                 dpll |= DPLL_SDVO_HIGH_SPEED;
8183
8184         /* compute bitmask from p1 value */
8185         if (IS_PINEVIEW(dev_priv))
8186                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8187         else {
8188                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8189                 if (IS_G4X(dev_priv) && reduced_clock)
8190                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8191         }
8192         switch (clock->p2) {
8193         case 5:
8194                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8195                 break;
8196         case 7:
8197                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8198                 break;
8199         case 10:
8200                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8201                 break;
8202         case 14:
8203                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8204                 break;
8205         }
8206         if (INTEL_GEN(dev_priv) >= 4)
8207                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8208
8209         if (crtc_state->sdvo_tv_clock)
8210                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8211         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8212                  intel_panel_use_ssc(dev_priv))
8213                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8214         else
8215                 dpll |= PLL_REF_INPUT_DREFCLK;
8216
8217         dpll |= DPLL_VCO_ENABLE;
8218         crtc_state->dpll_hw_state.dpll = dpll;
8219
8220         if (INTEL_GEN(dev_priv) >= 4) {
8221                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8222                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8223                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8224         }
8225 }
8226
8227 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8228                               struct intel_crtc_state *crtc_state,
8229                               struct dpll *reduced_clock)
8230 {
8231         struct drm_device *dev = crtc->base.dev;
8232         struct drm_i915_private *dev_priv = to_i915(dev);
8233         u32 dpll;
8234         struct dpll *clock = &crtc_state->dpll;
8235
8236         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8237
8238         dpll = DPLL_VGA_MODE_DIS;
8239
8240         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8241                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8242         } else {
8243                 if (clock->p1 == 2)
8244                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8245                 else
8246                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8247                 if (clock->p2 == 4)
8248                         dpll |= PLL_P2_DIVIDE_BY_4;
8249         }
8250
8251         if (!IS_I830(dev_priv) &&
8252             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8253                 dpll |= DPLL_DVO_2X_MODE;
8254
8255         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8256             intel_panel_use_ssc(dev_priv))
8257                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8258         else
8259                 dpll |= PLL_REF_INPUT_DREFCLK;
8260
8261         dpll |= DPLL_VCO_ENABLE;
8262         crtc_state->dpll_hw_state.dpll = dpll;
8263 }
8264
8265 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8266 {
8267         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8268         enum pipe pipe = intel_crtc->pipe;
8269         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8270         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8271         uint32_t crtc_vtotal, crtc_vblank_end;
8272         int vsyncshift = 0;
8273
8274         /* We need to be careful not to changed the adjusted mode, for otherwise
8275          * the hw state checker will get angry at the mismatch. */
8276         crtc_vtotal = adjusted_mode->crtc_vtotal;
8277         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8278
8279         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8280                 /* the chip adds 2 halflines automatically */
8281                 crtc_vtotal -= 1;
8282                 crtc_vblank_end -= 1;
8283
8284                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8285                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8286                 else
8287                         vsyncshift = adjusted_mode->crtc_hsync_start -
8288                                 adjusted_mode->crtc_htotal / 2;
8289                 if (vsyncshift < 0)
8290                         vsyncshift += adjusted_mode->crtc_htotal;
8291         }
8292
8293         if (INTEL_GEN(dev_priv) > 3)
8294                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8295
8296         I915_WRITE(HTOTAL(cpu_transcoder),
8297                    (adjusted_mode->crtc_hdisplay - 1) |
8298                    ((adjusted_mode->crtc_htotal - 1) << 16));
8299         I915_WRITE(HBLANK(cpu_transcoder),
8300                    (adjusted_mode->crtc_hblank_start - 1) |
8301                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8302         I915_WRITE(HSYNC(cpu_transcoder),
8303                    (adjusted_mode->crtc_hsync_start - 1) |
8304                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8305
8306         I915_WRITE(VTOTAL(cpu_transcoder),
8307                    (adjusted_mode->crtc_vdisplay - 1) |
8308                    ((crtc_vtotal - 1) << 16));
8309         I915_WRITE(VBLANK(cpu_transcoder),
8310                    (adjusted_mode->crtc_vblank_start - 1) |
8311                    ((crtc_vblank_end - 1) << 16));
8312         I915_WRITE(VSYNC(cpu_transcoder),
8313                    (adjusted_mode->crtc_vsync_start - 1) |
8314                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8315
8316         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8317          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8318          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8319          * bits. */
8320         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8321             (pipe == PIPE_B || pipe == PIPE_C))
8322                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8323
8324 }
8325
8326 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8327 {
8328         struct drm_device *dev = intel_crtc->base.dev;
8329         struct drm_i915_private *dev_priv = to_i915(dev);
8330         enum pipe pipe = intel_crtc->pipe;
8331
8332         /* pipesrc controls the size that is scaled from, which should
8333          * always be the user's requested size.
8334          */
8335         I915_WRITE(PIPESRC(pipe),
8336                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
8337                    (intel_crtc->config->pipe_src_h - 1));
8338 }
8339
8340 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8341                                    struct intel_crtc_state *pipe_config)
8342 {
8343         struct drm_device *dev = crtc->base.dev;
8344         struct drm_i915_private *dev_priv = to_i915(dev);
8345         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8346         uint32_t tmp;
8347
8348         tmp = I915_READ(HTOTAL(cpu_transcoder));
8349         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8350         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8351         tmp = I915_READ(HBLANK(cpu_transcoder));
8352         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8353         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8354         tmp = I915_READ(HSYNC(cpu_transcoder));
8355         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8356         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8357
8358         tmp = I915_READ(VTOTAL(cpu_transcoder));
8359         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8360         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8361         tmp = I915_READ(VBLANK(cpu_transcoder));
8362         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8363         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8364         tmp = I915_READ(VSYNC(cpu_transcoder));
8365         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8366         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8367
8368         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8369                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8370                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8371                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8372         }
8373 }
8374
8375 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8376                                     struct intel_crtc_state *pipe_config)
8377 {
8378         struct drm_device *dev = crtc->base.dev;
8379         struct drm_i915_private *dev_priv = to_i915(dev);
8380         u32 tmp;
8381
8382         tmp = I915_READ(PIPESRC(crtc->pipe));
8383         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8384         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8385
8386         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8387         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8388 }
8389
8390 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8391                                  struct intel_crtc_state *pipe_config)
8392 {
8393         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8394         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8395         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8396         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8397
8398         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8399         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8400         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8401         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8402
8403         mode->flags = pipe_config->base.adjusted_mode.flags;
8404         mode->type = DRM_MODE_TYPE_DRIVER;
8405
8406         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8407         mode->flags |= pipe_config->base.adjusted_mode.flags;
8408
8409         mode->hsync = drm_mode_hsync(mode);
8410         mode->vrefresh = drm_mode_vrefresh(mode);
8411         drm_mode_set_name(mode);
8412 }
8413
8414 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8415 {
8416         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8417         uint32_t pipeconf;
8418
8419         pipeconf = 0;
8420
8421         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8422             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8423                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8424
8425         if (intel_crtc->config->double_wide)
8426                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8427
8428         /* only g4x and later have fancy bpc/dither controls */
8429         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8430             IS_CHERRYVIEW(dev_priv)) {
8431                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8432                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8433                         pipeconf |= PIPECONF_DITHER_EN |
8434                                     PIPECONF_DITHER_TYPE_SP;
8435
8436                 switch (intel_crtc->config->pipe_bpp) {
8437                 case 18:
8438                         pipeconf |= PIPECONF_6BPC;
8439                         break;
8440                 case 24:
8441                         pipeconf |= PIPECONF_8BPC;
8442                         break;
8443                 case 30:
8444                         pipeconf |= PIPECONF_10BPC;
8445                         break;
8446                 default:
8447                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8448                         BUG();
8449                 }
8450         }
8451
8452         if (HAS_PIPE_CXSR(dev_priv)) {
8453                 if (intel_crtc->lowfreq_avail) {
8454                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8455                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8456                 } else {
8457                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8458                 }
8459         }
8460
8461         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8462                 if (INTEL_GEN(dev_priv) < 4 ||
8463                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8464                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8465                 else
8466                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8467         } else
8468                 pipeconf |= PIPECONF_PROGRESSIVE;
8469
8470         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8471              intel_crtc->config->limited_color_range)
8472                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8473
8474         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8475         POSTING_READ(PIPECONF(intel_crtc->pipe));
8476 }
8477
8478 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8479                                    struct intel_crtc_state *crtc_state)
8480 {
8481         struct drm_device *dev = crtc->base.dev;
8482         struct drm_i915_private *dev_priv = to_i915(dev);
8483         const struct intel_limit *limit;
8484         int refclk = 48000;
8485
8486         memset(&crtc_state->dpll_hw_state, 0,
8487                sizeof(crtc_state->dpll_hw_state));
8488
8489         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8490                 if (intel_panel_use_ssc(dev_priv)) {
8491                         refclk = dev_priv->vbt.lvds_ssc_freq;
8492                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8493                 }
8494
8495                 limit = &intel_limits_i8xx_lvds;
8496         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8497                 limit = &intel_limits_i8xx_dvo;
8498         } else {
8499                 limit = &intel_limits_i8xx_dac;
8500         }
8501
8502         if (!crtc_state->clock_set &&
8503             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8504                                  refclk, NULL, &crtc_state->dpll)) {
8505                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8506                 return -EINVAL;
8507         }
8508
8509         i8xx_compute_dpll(crtc, crtc_state, NULL);
8510
8511         return 0;
8512 }
8513
8514 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8515                                   struct intel_crtc_state *crtc_state)
8516 {
8517         struct drm_device *dev = crtc->base.dev;
8518         struct drm_i915_private *dev_priv = to_i915(dev);
8519         const struct intel_limit *limit;
8520         int refclk = 96000;
8521
8522         memset(&crtc_state->dpll_hw_state, 0,
8523                sizeof(crtc_state->dpll_hw_state));
8524
8525         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8526                 if (intel_panel_use_ssc(dev_priv)) {
8527                         refclk = dev_priv->vbt.lvds_ssc_freq;
8528                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8529                 }
8530
8531                 if (intel_is_dual_link_lvds(dev))
8532                         limit = &intel_limits_g4x_dual_channel_lvds;
8533                 else
8534                         limit = &intel_limits_g4x_single_channel_lvds;
8535         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8536                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8537                 limit = &intel_limits_g4x_hdmi;
8538         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8539                 limit = &intel_limits_g4x_sdvo;
8540         } else {
8541                 /* The option is for other outputs */
8542                 limit = &intel_limits_i9xx_sdvo;
8543         }
8544
8545         if (!crtc_state->clock_set &&
8546             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8547                                 refclk, NULL, &crtc_state->dpll)) {
8548                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8549                 return -EINVAL;
8550         }
8551
8552         i9xx_compute_dpll(crtc, crtc_state, NULL);
8553
8554         return 0;
8555 }
8556
8557 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8558                                   struct intel_crtc_state *crtc_state)
8559 {
8560         struct drm_device *dev = crtc->base.dev;
8561         struct drm_i915_private *dev_priv = to_i915(dev);
8562         const struct intel_limit *limit;
8563         int refclk = 96000;
8564
8565         memset(&crtc_state->dpll_hw_state, 0,
8566                sizeof(crtc_state->dpll_hw_state));
8567
8568         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8569                 if (intel_panel_use_ssc(dev_priv)) {
8570                         refclk = dev_priv->vbt.lvds_ssc_freq;
8571                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8572                 }
8573
8574                 limit = &intel_limits_pineview_lvds;
8575         } else {
8576                 limit = &intel_limits_pineview_sdvo;
8577         }
8578
8579         if (!crtc_state->clock_set &&
8580             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8581                                 refclk, NULL, &crtc_state->dpll)) {
8582                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8583                 return -EINVAL;
8584         }
8585
8586         i9xx_compute_dpll(crtc, crtc_state, NULL);
8587
8588         return 0;
8589 }
8590
8591 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8592                                    struct intel_crtc_state *crtc_state)
8593 {
8594         struct drm_device *dev = crtc->base.dev;
8595         struct drm_i915_private *dev_priv = to_i915(dev);
8596         const struct intel_limit *limit;
8597         int refclk = 96000;
8598
8599         memset(&crtc_state->dpll_hw_state, 0,
8600                sizeof(crtc_state->dpll_hw_state));
8601
8602         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8603                 if (intel_panel_use_ssc(dev_priv)) {
8604                         refclk = dev_priv->vbt.lvds_ssc_freq;
8605                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8606                 }
8607
8608                 limit = &intel_limits_i9xx_lvds;
8609         } else {
8610                 limit = &intel_limits_i9xx_sdvo;
8611         }
8612
8613         if (!crtc_state->clock_set &&
8614             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8615                                  refclk, NULL, &crtc_state->dpll)) {
8616                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8617                 return -EINVAL;
8618         }
8619
8620         i9xx_compute_dpll(crtc, crtc_state, NULL);
8621
8622         return 0;
8623 }
8624
8625 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8626                                   struct intel_crtc_state *crtc_state)
8627 {
8628         int refclk = 100000;
8629         const struct intel_limit *limit = &intel_limits_chv;
8630
8631         memset(&crtc_state->dpll_hw_state, 0,
8632                sizeof(crtc_state->dpll_hw_state));
8633
8634         if (!crtc_state->clock_set &&
8635             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8636                                 refclk, NULL, &crtc_state->dpll)) {
8637                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8638                 return -EINVAL;
8639         }
8640
8641         chv_compute_dpll(crtc, crtc_state);
8642
8643         return 0;
8644 }
8645
8646 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8647                                   struct intel_crtc_state *crtc_state)
8648 {
8649         int refclk = 100000;
8650         const struct intel_limit *limit = &intel_limits_vlv;
8651
8652         memset(&crtc_state->dpll_hw_state, 0,
8653                sizeof(crtc_state->dpll_hw_state));
8654
8655         if (!crtc_state->clock_set &&
8656             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8657                                 refclk, NULL, &crtc_state->dpll)) {
8658                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8659                 return -EINVAL;
8660         }
8661
8662         vlv_compute_dpll(crtc, crtc_state);
8663
8664         return 0;
8665 }
8666
8667 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8668                                  struct intel_crtc_state *pipe_config)
8669 {
8670         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8671         uint32_t tmp;
8672
8673         if (INTEL_GEN(dev_priv) <= 3 &&
8674             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
8675                 return;
8676
8677         tmp = I915_READ(PFIT_CONTROL);
8678         if (!(tmp & PFIT_ENABLE))
8679                 return;
8680
8681         /* Check whether the pfit is attached to our pipe. */
8682         if (INTEL_GEN(dev_priv) < 4) {
8683                 if (crtc->pipe != PIPE_B)
8684                         return;
8685         } else {
8686                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8687                         return;
8688         }
8689
8690         pipe_config->gmch_pfit.control = tmp;
8691         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8692 }
8693
8694 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8695                                struct intel_crtc_state *pipe_config)
8696 {
8697         struct drm_device *dev = crtc->base.dev;
8698         struct drm_i915_private *dev_priv = to_i915(dev);
8699         int pipe = pipe_config->cpu_transcoder;
8700         struct dpll clock;
8701         u32 mdiv;
8702         int refclk = 100000;
8703
8704         /* In case of DSI, DPLL will not be used */
8705         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8706                 return;
8707
8708         mutex_lock(&dev_priv->sb_lock);
8709         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8710         mutex_unlock(&dev_priv->sb_lock);
8711
8712         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8713         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8714         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8715         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8716         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8717
8718         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8719 }
8720
8721 static void
8722 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8723                               struct intel_initial_plane_config *plane_config)
8724 {
8725         struct drm_device *dev = crtc->base.dev;
8726         struct drm_i915_private *dev_priv = to_i915(dev);
8727         u32 val, base, offset;
8728         int pipe = crtc->pipe, plane = crtc->plane;
8729         int fourcc, pixel_format;
8730         unsigned int aligned_height;
8731         struct drm_framebuffer *fb;
8732         struct intel_framebuffer *intel_fb;
8733
8734         val = I915_READ(DSPCNTR(plane));
8735         if (!(val & DISPLAY_PLANE_ENABLE))
8736                 return;
8737
8738         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8739         if (!intel_fb) {
8740                 DRM_DEBUG_KMS("failed to alloc fb\n");
8741                 return;
8742         }
8743
8744         fb = &intel_fb->base;
8745
8746         if (INTEL_GEN(dev_priv) >= 4) {
8747                 if (val & DISPPLANE_TILED) {
8748                         plane_config->tiling = I915_TILING_X;
8749                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8750                 }
8751         }
8752
8753         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8754         fourcc = i9xx_format_to_fourcc(pixel_format);
8755         fb->pixel_format = fourcc;
8756         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8757
8758         if (INTEL_GEN(dev_priv) >= 4) {
8759                 if (plane_config->tiling)
8760                         offset = I915_READ(DSPTILEOFF(plane));
8761                 else
8762                         offset = I915_READ(DSPLINOFF(plane));
8763                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8764         } else {
8765                 base = I915_READ(DSPADDR(plane));
8766         }
8767         plane_config->base = base;
8768
8769         val = I915_READ(PIPESRC(pipe));
8770         fb->width = ((val >> 16) & 0xfff) + 1;
8771         fb->height = ((val >> 0) & 0xfff) + 1;
8772
8773         val = I915_READ(DSPSTRIDE(pipe));
8774         fb->pitches[0] = val & 0xffffffc0;
8775
8776         aligned_height = intel_fb_align_height(dev, fb->height,
8777                                                fb->pixel_format,
8778                                                fb->modifier);
8779
8780         plane_config->size = fb->pitches[0] * aligned_height;
8781
8782         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8783                       pipe_name(pipe), plane, fb->width, fb->height,
8784                       fb->bits_per_pixel, base, fb->pitches[0],
8785                       plane_config->size);
8786
8787         plane_config->fb = intel_fb;
8788 }
8789
8790 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8791                                struct intel_crtc_state *pipe_config)
8792 {
8793         struct drm_device *dev = crtc->base.dev;
8794         struct drm_i915_private *dev_priv = to_i915(dev);
8795         int pipe = pipe_config->cpu_transcoder;
8796         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8797         struct dpll clock;
8798         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8799         int refclk = 100000;
8800
8801         /* In case of DSI, DPLL will not be used */
8802         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8803                 return;
8804
8805         mutex_lock(&dev_priv->sb_lock);
8806         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8807         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8808         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8809         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8810         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8811         mutex_unlock(&dev_priv->sb_lock);
8812
8813         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8814         clock.m2 = (pll_dw0 & 0xff) << 22;
8815         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8816                 clock.m2 |= pll_dw2 & 0x3fffff;
8817         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8818         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8819         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8820
8821         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8822 }
8823
8824 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8825                                  struct intel_crtc_state *pipe_config)
8826 {
8827         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8828         enum intel_display_power_domain power_domain;
8829         uint32_t tmp;
8830         bool ret;
8831
8832         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8833         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8834                 return false;
8835
8836         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8837         pipe_config->shared_dpll = NULL;
8838
8839         ret = false;
8840
8841         tmp = I915_READ(PIPECONF(crtc->pipe));
8842         if (!(tmp & PIPECONF_ENABLE))
8843                 goto out;
8844
8845         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8846             IS_CHERRYVIEW(dev_priv)) {
8847                 switch (tmp & PIPECONF_BPC_MASK) {
8848                 case PIPECONF_6BPC:
8849                         pipe_config->pipe_bpp = 18;
8850                         break;
8851                 case PIPECONF_8BPC:
8852                         pipe_config->pipe_bpp = 24;
8853                         break;
8854                 case PIPECONF_10BPC:
8855                         pipe_config->pipe_bpp = 30;
8856                         break;
8857                 default:
8858                         break;
8859                 }
8860         }
8861
8862         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8863             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8864                 pipe_config->limited_color_range = true;
8865
8866         if (INTEL_GEN(dev_priv) < 4)
8867                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8868
8869         intel_get_pipe_timings(crtc, pipe_config);
8870         intel_get_pipe_src_size(crtc, pipe_config);
8871
8872         i9xx_get_pfit_config(crtc, pipe_config);
8873
8874         if (INTEL_GEN(dev_priv) >= 4) {
8875                 /* No way to read it out on pipes B and C */
8876                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8877                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8878                 else
8879                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8880                 pipe_config->pixel_multiplier =
8881                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8882                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8883                 pipe_config->dpll_hw_state.dpll_md = tmp;
8884         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8885                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8886                 tmp = I915_READ(DPLL(crtc->pipe));
8887                 pipe_config->pixel_multiplier =
8888                         ((tmp & SDVO_MULTIPLIER_MASK)
8889                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8890         } else {
8891                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8892                  * port and will be fixed up in the encoder->get_config
8893                  * function. */
8894                 pipe_config->pixel_multiplier = 1;
8895         }
8896         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8897         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8898                 /*
8899                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8900                  * on 830. Filter it out here so that we don't
8901                  * report errors due to that.
8902                  */
8903                 if (IS_I830(dev_priv))
8904                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8905
8906                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8907                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8908         } else {
8909                 /* Mask out read-only status bits. */
8910                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8911                                                      DPLL_PORTC_READY_MASK |
8912                                                      DPLL_PORTB_READY_MASK);
8913         }
8914
8915         if (IS_CHERRYVIEW(dev_priv))
8916                 chv_crtc_clock_get(crtc, pipe_config);
8917         else if (IS_VALLEYVIEW(dev_priv))
8918                 vlv_crtc_clock_get(crtc, pipe_config);
8919         else
8920                 i9xx_crtc_clock_get(crtc, pipe_config);
8921
8922         /*
8923          * Normally the dotclock is filled in by the encoder .get_config()
8924          * but in case the pipe is enabled w/o any ports we need a sane
8925          * default.
8926          */
8927         pipe_config->base.adjusted_mode.crtc_clock =
8928                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8929
8930         ret = true;
8931
8932 out:
8933         intel_display_power_put(dev_priv, power_domain);
8934
8935         return ret;
8936 }
8937
8938 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
8939 {
8940         struct intel_encoder *encoder;
8941         int i;
8942         u32 val, final;
8943         bool has_lvds = false;
8944         bool has_cpu_edp = false;
8945         bool has_panel = false;
8946         bool has_ck505 = false;
8947         bool can_ssc = false;
8948         bool using_ssc_source = false;
8949
8950         /* We need to take the global config into account */
8951         for_each_intel_encoder(&dev_priv->drm, encoder) {
8952                 switch (encoder->type) {
8953                 case INTEL_OUTPUT_LVDS:
8954                         has_panel = true;
8955                         has_lvds = true;
8956                         break;
8957                 case INTEL_OUTPUT_EDP:
8958                         has_panel = true;
8959                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8960                                 has_cpu_edp = true;
8961                         break;
8962                 default:
8963                         break;
8964                 }
8965         }
8966
8967         if (HAS_PCH_IBX(dev_priv)) {
8968                 has_ck505 = dev_priv->vbt.display_clock_mode;
8969                 can_ssc = has_ck505;
8970         } else {
8971                 has_ck505 = false;
8972                 can_ssc = true;
8973         }
8974
8975         /* Check if any DPLLs are using the SSC source */
8976         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8977                 u32 temp = I915_READ(PCH_DPLL(i));
8978
8979                 if (!(temp & DPLL_VCO_ENABLE))
8980                         continue;
8981
8982                 if ((temp & PLL_REF_INPUT_MASK) ==
8983                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8984                         using_ssc_source = true;
8985                         break;
8986                 }
8987         }
8988
8989         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8990                       has_panel, has_lvds, has_ck505, using_ssc_source);
8991
8992         /* Ironlake: try to setup display ref clock before DPLL
8993          * enabling. This is only under driver's control after
8994          * PCH B stepping, previous chipset stepping should be
8995          * ignoring this setting.
8996          */
8997         val = I915_READ(PCH_DREF_CONTROL);
8998
8999         /* As we must carefully and slowly disable/enable each source in turn,
9000          * compute the final state we want first and check if we need to
9001          * make any changes at all.
9002          */
9003         final = val;
9004         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9005         if (has_ck505)
9006                 final |= DREF_NONSPREAD_CK505_ENABLE;
9007         else
9008                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9009
9010         final &= ~DREF_SSC_SOURCE_MASK;
9011         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9012         final &= ~DREF_SSC1_ENABLE;
9013
9014         if (has_panel) {
9015                 final |= DREF_SSC_SOURCE_ENABLE;
9016
9017                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9018                         final |= DREF_SSC1_ENABLE;
9019
9020                 if (has_cpu_edp) {
9021                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9022                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9023                         else
9024                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9025                 } else
9026                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9027         } else if (using_ssc_source) {
9028                 final |= DREF_SSC_SOURCE_ENABLE;
9029                 final |= DREF_SSC1_ENABLE;
9030         }
9031
9032         if (final == val)
9033                 return;
9034
9035         /* Always enable nonspread source */
9036         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9037
9038         if (has_ck505)
9039                 val |= DREF_NONSPREAD_CK505_ENABLE;
9040         else
9041                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9042
9043         if (has_panel) {
9044                 val &= ~DREF_SSC_SOURCE_MASK;
9045                 val |= DREF_SSC_SOURCE_ENABLE;
9046
9047                 /* SSC must be turned on before enabling the CPU output  */
9048                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9049                         DRM_DEBUG_KMS("Using SSC on panel\n");
9050                         val |= DREF_SSC1_ENABLE;
9051                 } else
9052                         val &= ~DREF_SSC1_ENABLE;
9053
9054                 /* Get SSC going before enabling the outputs */
9055                 I915_WRITE(PCH_DREF_CONTROL, val);
9056                 POSTING_READ(PCH_DREF_CONTROL);
9057                 udelay(200);
9058
9059                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9060
9061                 /* Enable CPU source on CPU attached eDP */
9062                 if (has_cpu_edp) {
9063                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9064                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9065                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9066                         } else
9067                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9068                 } else
9069                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9070
9071                 I915_WRITE(PCH_DREF_CONTROL, val);
9072                 POSTING_READ(PCH_DREF_CONTROL);
9073                 udelay(200);
9074         } else {
9075                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9076
9077                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9078
9079                 /* Turn off CPU output */
9080                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9081
9082                 I915_WRITE(PCH_DREF_CONTROL, val);
9083                 POSTING_READ(PCH_DREF_CONTROL);
9084                 udelay(200);
9085
9086                 if (!using_ssc_source) {
9087                         DRM_DEBUG_KMS("Disabling SSC source\n");
9088
9089                         /* Turn off the SSC source */
9090                         val &= ~DREF_SSC_SOURCE_MASK;
9091                         val |= DREF_SSC_SOURCE_DISABLE;
9092
9093                         /* Turn off SSC1 */
9094                         val &= ~DREF_SSC1_ENABLE;
9095
9096                         I915_WRITE(PCH_DREF_CONTROL, val);
9097                         POSTING_READ(PCH_DREF_CONTROL);
9098                         udelay(200);
9099                 }
9100         }
9101
9102         BUG_ON(val != final);
9103 }
9104
9105 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9106 {
9107         uint32_t tmp;
9108
9109         tmp = I915_READ(SOUTH_CHICKEN2);
9110         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9111         I915_WRITE(SOUTH_CHICKEN2, tmp);
9112
9113         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9114                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9115                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9116
9117         tmp = I915_READ(SOUTH_CHICKEN2);
9118         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9119         I915_WRITE(SOUTH_CHICKEN2, tmp);
9120
9121         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9122                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9123                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9124 }
9125
9126 /* WaMPhyProgramming:hsw */
9127 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9128 {
9129         uint32_t tmp;
9130
9131         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9132         tmp &= ~(0xFF << 24);
9133         tmp |= (0x12 << 24);
9134         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9135
9136         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9137         tmp |= (1 << 11);
9138         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9139
9140         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9141         tmp |= (1 << 11);
9142         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9143
9144         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9145         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9146         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9147
9148         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9149         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9150         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9151
9152         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9153         tmp &= ~(7 << 13);
9154         tmp |= (5 << 13);
9155         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9156
9157         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9158         tmp &= ~(7 << 13);
9159         tmp |= (5 << 13);
9160         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9161
9162         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9163         tmp &= ~0xFF;
9164         tmp |= 0x1C;
9165         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9166
9167         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9168         tmp &= ~0xFF;
9169         tmp |= 0x1C;
9170         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9171
9172         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9173         tmp &= ~(0xFF << 16);
9174         tmp |= (0x1C << 16);
9175         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9176
9177         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9178         tmp &= ~(0xFF << 16);
9179         tmp |= (0x1C << 16);
9180         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9181
9182         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9183         tmp |= (1 << 27);
9184         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9185
9186         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9187         tmp |= (1 << 27);
9188         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9189
9190         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9191         tmp &= ~(0xF << 28);
9192         tmp |= (4 << 28);
9193         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9194
9195         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9196         tmp &= ~(0xF << 28);
9197         tmp |= (4 << 28);
9198         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9199 }
9200
9201 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9202  * Programming" based on the parameters passed:
9203  * - Sequence to enable CLKOUT_DP
9204  * - Sequence to enable CLKOUT_DP without spread
9205  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9206  */
9207 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9208                                  bool with_spread, bool with_fdi)
9209 {
9210         uint32_t reg, tmp;
9211
9212         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9213                 with_spread = true;
9214         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9215             with_fdi, "LP PCH doesn't have FDI\n"))
9216                 with_fdi = false;
9217
9218         mutex_lock(&dev_priv->sb_lock);
9219
9220         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9221         tmp &= ~SBI_SSCCTL_DISABLE;
9222         tmp |= SBI_SSCCTL_PATHALT;
9223         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9224
9225         udelay(24);
9226
9227         if (with_spread) {
9228                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9229                 tmp &= ~SBI_SSCCTL_PATHALT;
9230                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9231
9232                 if (with_fdi) {
9233                         lpt_reset_fdi_mphy(dev_priv);
9234                         lpt_program_fdi_mphy(dev_priv);
9235                 }
9236         }
9237
9238         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9239         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9240         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9241         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9242
9243         mutex_unlock(&dev_priv->sb_lock);
9244 }
9245
9246 /* Sequence to disable CLKOUT_DP */
9247 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9248 {
9249         uint32_t reg, tmp;
9250
9251         mutex_lock(&dev_priv->sb_lock);
9252
9253         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9254         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9255         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9256         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9257
9258         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9259         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9260                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9261                         tmp |= SBI_SSCCTL_PATHALT;
9262                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9263                         udelay(32);
9264                 }
9265                 tmp |= SBI_SSCCTL_DISABLE;
9266                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9267         }
9268
9269         mutex_unlock(&dev_priv->sb_lock);
9270 }
9271
9272 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9273
9274 static const uint16_t sscdivintphase[] = {
9275         [BEND_IDX( 50)] = 0x3B23,
9276         [BEND_IDX( 45)] = 0x3B23,
9277         [BEND_IDX( 40)] = 0x3C23,
9278         [BEND_IDX( 35)] = 0x3C23,
9279         [BEND_IDX( 30)] = 0x3D23,
9280         [BEND_IDX( 25)] = 0x3D23,
9281         [BEND_IDX( 20)] = 0x3E23,
9282         [BEND_IDX( 15)] = 0x3E23,
9283         [BEND_IDX( 10)] = 0x3F23,
9284         [BEND_IDX(  5)] = 0x3F23,
9285         [BEND_IDX(  0)] = 0x0025,
9286         [BEND_IDX( -5)] = 0x0025,
9287         [BEND_IDX(-10)] = 0x0125,
9288         [BEND_IDX(-15)] = 0x0125,
9289         [BEND_IDX(-20)] = 0x0225,
9290         [BEND_IDX(-25)] = 0x0225,
9291         [BEND_IDX(-30)] = 0x0325,
9292         [BEND_IDX(-35)] = 0x0325,
9293         [BEND_IDX(-40)] = 0x0425,
9294         [BEND_IDX(-45)] = 0x0425,
9295         [BEND_IDX(-50)] = 0x0525,
9296 };
9297
9298 /*
9299  * Bend CLKOUT_DP
9300  * steps -50 to 50 inclusive, in steps of 5
9301  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9302  * change in clock period = -(steps / 10) * 5.787 ps
9303  */
9304 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9305 {
9306         uint32_t tmp;
9307         int idx = BEND_IDX(steps);
9308
9309         if (WARN_ON(steps % 5 != 0))
9310                 return;
9311
9312         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9313                 return;
9314
9315         mutex_lock(&dev_priv->sb_lock);
9316
9317         if (steps % 10 != 0)
9318                 tmp = 0xAAAAAAAB;
9319         else
9320                 tmp = 0x00000000;
9321         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9322
9323         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9324         tmp &= 0xffff0000;
9325         tmp |= sscdivintphase[idx];
9326         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9327
9328         mutex_unlock(&dev_priv->sb_lock);
9329 }
9330
9331 #undef BEND_IDX
9332
9333 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9334 {
9335         struct intel_encoder *encoder;
9336         bool has_vga = false;
9337
9338         for_each_intel_encoder(&dev_priv->drm, encoder) {
9339                 switch (encoder->type) {
9340                 case INTEL_OUTPUT_ANALOG:
9341                         has_vga = true;
9342                         break;
9343                 default:
9344                         break;
9345                 }
9346         }
9347
9348         if (has_vga) {
9349                 lpt_bend_clkout_dp(dev_priv, 0);
9350                 lpt_enable_clkout_dp(dev_priv, true, true);
9351         } else {
9352                 lpt_disable_clkout_dp(dev_priv);
9353         }
9354 }
9355
9356 /*
9357  * Initialize reference clocks when the driver loads
9358  */
9359 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9360 {
9361         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9362                 ironlake_init_pch_refclk(dev_priv);
9363         else if (HAS_PCH_LPT(dev_priv))
9364                 lpt_init_pch_refclk(dev_priv);
9365 }
9366
9367 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9368 {
9369         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9371         int pipe = intel_crtc->pipe;
9372         uint32_t val;
9373
9374         val = 0;
9375
9376         switch (intel_crtc->config->pipe_bpp) {
9377         case 18:
9378                 val |= PIPECONF_6BPC;
9379                 break;
9380         case 24:
9381                 val |= PIPECONF_8BPC;
9382                 break;
9383         case 30:
9384                 val |= PIPECONF_10BPC;
9385                 break;
9386         case 36:
9387                 val |= PIPECONF_12BPC;
9388                 break;
9389         default:
9390                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9391                 BUG();
9392         }
9393
9394         if (intel_crtc->config->dither)
9395                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9396
9397         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9398                 val |= PIPECONF_INTERLACED_ILK;
9399         else
9400                 val |= PIPECONF_PROGRESSIVE;
9401
9402         if (intel_crtc->config->limited_color_range)
9403                 val |= PIPECONF_COLOR_RANGE_SELECT;
9404
9405         I915_WRITE(PIPECONF(pipe), val);
9406         POSTING_READ(PIPECONF(pipe));
9407 }
9408
9409 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9410 {
9411         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9412         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9413         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9414         u32 val = 0;
9415
9416         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9417                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9418
9419         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9420                 val |= PIPECONF_INTERLACED_ILK;
9421         else
9422                 val |= PIPECONF_PROGRESSIVE;
9423
9424         I915_WRITE(PIPECONF(cpu_transcoder), val);
9425         POSTING_READ(PIPECONF(cpu_transcoder));
9426 }
9427
9428 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9429 {
9430         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9432
9433         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9434                 u32 val = 0;
9435
9436                 switch (intel_crtc->config->pipe_bpp) {
9437                 case 18:
9438                         val |= PIPEMISC_DITHER_6_BPC;
9439                         break;
9440                 case 24:
9441                         val |= PIPEMISC_DITHER_8_BPC;
9442                         break;
9443                 case 30:
9444                         val |= PIPEMISC_DITHER_10_BPC;
9445                         break;
9446                 case 36:
9447                         val |= PIPEMISC_DITHER_12_BPC;
9448                         break;
9449                 default:
9450                         /* Case prevented by pipe_config_set_bpp. */
9451                         BUG();
9452                 }
9453
9454                 if (intel_crtc->config->dither)
9455                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9456
9457                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9458         }
9459 }
9460
9461 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9462 {
9463         /*
9464          * Account for spread spectrum to avoid
9465          * oversubscribing the link. Max center spread
9466          * is 2.5%; use 5% for safety's sake.
9467          */
9468         u32 bps = target_clock * bpp * 21 / 20;
9469         return DIV_ROUND_UP(bps, link_bw * 8);
9470 }
9471
9472 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9473 {
9474         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9475 }
9476
9477 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9478                                   struct intel_crtc_state *crtc_state,
9479                                   struct dpll *reduced_clock)
9480 {
9481         struct drm_crtc *crtc = &intel_crtc->base;
9482         struct drm_device *dev = crtc->dev;
9483         struct drm_i915_private *dev_priv = to_i915(dev);
9484         u32 dpll, fp, fp2;
9485         int factor;
9486
9487         /* Enable autotuning of the PLL clock (if permissible) */
9488         factor = 21;
9489         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9490                 if ((intel_panel_use_ssc(dev_priv) &&
9491                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9492                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
9493                         factor = 25;
9494         } else if (crtc_state->sdvo_tv_clock)
9495                 factor = 20;
9496
9497         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9498
9499         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9500                 fp |= FP_CB_TUNE;
9501
9502         if (reduced_clock) {
9503                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9504
9505                 if (reduced_clock->m < factor * reduced_clock->n)
9506                         fp2 |= FP_CB_TUNE;
9507         } else {
9508                 fp2 = fp;
9509         }
9510
9511         dpll = 0;
9512
9513         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9514                 dpll |= DPLLB_MODE_LVDS;
9515         else
9516                 dpll |= DPLLB_MODE_DAC_SERIAL;
9517
9518         dpll |= (crtc_state->pixel_multiplier - 1)
9519                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9520
9521         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9522             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9523                 dpll |= DPLL_SDVO_HIGH_SPEED;
9524
9525         if (intel_crtc_has_dp_encoder(crtc_state))
9526                 dpll |= DPLL_SDVO_HIGH_SPEED;
9527
9528         /*
9529          * The high speed IO clock is only really required for
9530          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9531          * possible to share the DPLL between CRT and HDMI. Enabling
9532          * the clock needlessly does no real harm, except use up a
9533          * bit of power potentially.
9534          *
9535          * We'll limit this to IVB with 3 pipes, since it has only two
9536          * DPLLs and so DPLL sharing is the only way to get three pipes
9537          * driving PCH ports at the same time. On SNB we could do this,
9538          * and potentially avoid enabling the second DPLL, but it's not
9539          * clear if it''s a win or loss power wise. No point in doing
9540          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9541          */
9542         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9543             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9544                 dpll |= DPLL_SDVO_HIGH_SPEED;
9545
9546         /* compute bitmask from p1 value */
9547         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9548         /* also FPA1 */
9549         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9550
9551         switch (crtc_state->dpll.p2) {
9552         case 5:
9553                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9554                 break;
9555         case 7:
9556                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9557                 break;
9558         case 10:
9559                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9560                 break;
9561         case 14:
9562                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9563                 break;
9564         }
9565
9566         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9567             intel_panel_use_ssc(dev_priv))
9568                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9569         else
9570                 dpll |= PLL_REF_INPUT_DREFCLK;
9571
9572         dpll |= DPLL_VCO_ENABLE;
9573
9574         crtc_state->dpll_hw_state.dpll = dpll;
9575         crtc_state->dpll_hw_state.fp0 = fp;
9576         crtc_state->dpll_hw_state.fp1 = fp2;
9577 }
9578
9579 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9580                                        struct intel_crtc_state *crtc_state)
9581 {
9582         struct drm_device *dev = crtc->base.dev;
9583         struct drm_i915_private *dev_priv = to_i915(dev);
9584         struct dpll reduced_clock;
9585         bool has_reduced_clock = false;
9586         struct intel_shared_dpll *pll;
9587         const struct intel_limit *limit;
9588         int refclk = 120000;
9589
9590         memset(&crtc_state->dpll_hw_state, 0,
9591                sizeof(crtc_state->dpll_hw_state));
9592
9593         crtc->lowfreq_avail = false;
9594
9595         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9596         if (!crtc_state->has_pch_encoder)
9597                 return 0;
9598
9599         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9600                 if (intel_panel_use_ssc(dev_priv)) {
9601                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9602                                       dev_priv->vbt.lvds_ssc_freq);
9603                         refclk = dev_priv->vbt.lvds_ssc_freq;
9604                 }
9605
9606                 if (intel_is_dual_link_lvds(dev)) {
9607                         if (refclk == 100000)
9608                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9609                         else
9610                                 limit = &intel_limits_ironlake_dual_lvds;
9611                 } else {
9612                         if (refclk == 100000)
9613                                 limit = &intel_limits_ironlake_single_lvds_100m;
9614                         else
9615                                 limit = &intel_limits_ironlake_single_lvds;
9616                 }
9617         } else {
9618                 limit = &intel_limits_ironlake_dac;
9619         }
9620
9621         if (!crtc_state->clock_set &&
9622             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9623                                 refclk, NULL, &crtc_state->dpll)) {
9624                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9625                 return -EINVAL;
9626         }
9627
9628         ironlake_compute_dpll(crtc, crtc_state,
9629                               has_reduced_clock ? &reduced_clock : NULL);
9630
9631         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9632         if (pll == NULL) {
9633                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9634                                  pipe_name(crtc->pipe));
9635                 return -EINVAL;
9636         }
9637
9638         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9639             has_reduced_clock)
9640                 crtc->lowfreq_avail = true;
9641
9642         return 0;
9643 }
9644
9645 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9646                                          struct intel_link_m_n *m_n)
9647 {
9648         struct drm_device *dev = crtc->base.dev;
9649         struct drm_i915_private *dev_priv = to_i915(dev);
9650         enum pipe pipe = crtc->pipe;
9651
9652         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9653         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9654         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9655                 & ~TU_SIZE_MASK;
9656         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9657         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9658                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9659 }
9660
9661 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9662                                          enum transcoder transcoder,
9663                                          struct intel_link_m_n *m_n,
9664                                          struct intel_link_m_n *m2_n2)
9665 {
9666         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9667         enum pipe pipe = crtc->pipe;
9668
9669         if (INTEL_GEN(dev_priv) >= 5) {
9670                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9671                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9672                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9673                         & ~TU_SIZE_MASK;
9674                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9675                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9676                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9677                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9678                  * gen < 8) and if DRRS is supported (to make sure the
9679                  * registers are not unnecessarily read).
9680                  */
9681                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
9682                         crtc->config->has_drrs) {
9683                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9684                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9685                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9686                                         & ~TU_SIZE_MASK;
9687                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9688                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9689                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9690                 }
9691         } else {
9692                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9693                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9694                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9695                         & ~TU_SIZE_MASK;
9696                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9697                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9698                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9699         }
9700 }
9701
9702 void intel_dp_get_m_n(struct intel_crtc *crtc,
9703                       struct intel_crtc_state *pipe_config)
9704 {
9705         if (pipe_config->has_pch_encoder)
9706                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9707         else
9708                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9709                                              &pipe_config->dp_m_n,
9710                                              &pipe_config->dp_m2_n2);
9711 }
9712
9713 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9714                                         struct intel_crtc_state *pipe_config)
9715 {
9716         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9717                                      &pipe_config->fdi_m_n, NULL);
9718 }
9719
9720 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9721                                     struct intel_crtc_state *pipe_config)
9722 {
9723         struct drm_device *dev = crtc->base.dev;
9724         struct drm_i915_private *dev_priv = to_i915(dev);
9725         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9726         uint32_t ps_ctrl = 0;
9727         int id = -1;
9728         int i;
9729
9730         /* find scaler attached to this pipe */
9731         for (i = 0; i < crtc->num_scalers; i++) {
9732                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9733                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9734                         id = i;
9735                         pipe_config->pch_pfit.enabled = true;
9736                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9737                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9738                         break;
9739                 }
9740         }
9741
9742         scaler_state->scaler_id = id;
9743         if (id >= 0) {
9744                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9745         } else {
9746                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9747         }
9748 }
9749
9750 static void
9751 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9752                                  struct intel_initial_plane_config *plane_config)
9753 {
9754         struct drm_device *dev = crtc->base.dev;
9755         struct drm_i915_private *dev_priv = to_i915(dev);
9756         u32 val, base, offset, stride_mult, tiling;
9757         int pipe = crtc->pipe;
9758         int fourcc, pixel_format;
9759         unsigned int aligned_height;
9760         struct drm_framebuffer *fb;
9761         struct intel_framebuffer *intel_fb;
9762
9763         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9764         if (!intel_fb) {
9765                 DRM_DEBUG_KMS("failed to alloc fb\n");
9766                 return;
9767         }
9768
9769         fb = &intel_fb->base;
9770
9771         val = I915_READ(PLANE_CTL(pipe, 0));
9772         if (!(val & PLANE_CTL_ENABLE))
9773                 goto error;
9774
9775         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9776         fourcc = skl_format_to_fourcc(pixel_format,
9777                                       val & PLANE_CTL_ORDER_RGBX,
9778                                       val & PLANE_CTL_ALPHA_MASK);
9779         fb->pixel_format = fourcc;
9780         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9781
9782         tiling = val & PLANE_CTL_TILED_MASK;
9783         switch (tiling) {
9784         case PLANE_CTL_TILED_LINEAR:
9785                 fb->modifier = DRM_FORMAT_MOD_NONE;
9786                 break;
9787         case PLANE_CTL_TILED_X:
9788                 plane_config->tiling = I915_TILING_X;
9789                 fb->modifier = I915_FORMAT_MOD_X_TILED;
9790                 break;
9791         case PLANE_CTL_TILED_Y:
9792                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
9793                 break;
9794         case PLANE_CTL_TILED_YF:
9795                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9796                 break;
9797         default:
9798                 MISSING_CASE(tiling);
9799                 goto error;
9800         }
9801
9802         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9803         plane_config->base = base;
9804
9805         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9806
9807         val = I915_READ(PLANE_SIZE(pipe, 0));
9808         fb->height = ((val >> 16) & 0xfff) + 1;
9809         fb->width = ((val >> 0) & 0x1fff) + 1;
9810
9811         val = I915_READ(PLANE_STRIDE(pipe, 0));
9812         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier,
9813                                                 fb->pixel_format);
9814         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9815
9816         aligned_height = intel_fb_align_height(dev, fb->height,
9817                                                fb->pixel_format,
9818                                                fb->modifier);
9819
9820         plane_config->size = fb->pitches[0] * aligned_height;
9821
9822         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9823                       pipe_name(pipe), fb->width, fb->height,
9824                       fb->bits_per_pixel, base, fb->pitches[0],
9825                       plane_config->size);
9826
9827         plane_config->fb = intel_fb;
9828         return;
9829
9830 error:
9831         kfree(intel_fb);
9832 }
9833
9834 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9835                                      struct intel_crtc_state *pipe_config)
9836 {
9837         struct drm_device *dev = crtc->base.dev;
9838         struct drm_i915_private *dev_priv = to_i915(dev);
9839         uint32_t tmp;
9840
9841         tmp = I915_READ(PF_CTL(crtc->pipe));
9842
9843         if (tmp & PF_ENABLE) {
9844                 pipe_config->pch_pfit.enabled = true;
9845                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9846                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9847
9848                 /* We currently do not free assignements of panel fitters on
9849                  * ivb/hsw (since we don't use the higher upscaling modes which
9850                  * differentiates them) so just WARN about this case for now. */
9851                 if (IS_GEN7(dev_priv)) {
9852                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9853                                 PF_PIPE_SEL_IVB(crtc->pipe));
9854                 }
9855         }
9856 }
9857
9858 static void
9859 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9860                                   struct intel_initial_plane_config *plane_config)
9861 {
9862         struct drm_device *dev = crtc->base.dev;
9863         struct drm_i915_private *dev_priv = to_i915(dev);
9864         u32 val, base, offset;
9865         int pipe = crtc->pipe;
9866         int fourcc, pixel_format;
9867         unsigned int aligned_height;
9868         struct drm_framebuffer *fb;
9869         struct intel_framebuffer *intel_fb;
9870
9871         val = I915_READ(DSPCNTR(pipe));
9872         if (!(val & DISPLAY_PLANE_ENABLE))
9873                 return;
9874
9875         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9876         if (!intel_fb) {
9877                 DRM_DEBUG_KMS("failed to alloc fb\n");
9878                 return;
9879         }
9880
9881         fb = &intel_fb->base;
9882
9883         if (INTEL_GEN(dev_priv) >= 4) {
9884                 if (val & DISPPLANE_TILED) {
9885                         plane_config->tiling = I915_TILING_X;
9886                         fb->modifier = I915_FORMAT_MOD_X_TILED;
9887                 }
9888         }
9889
9890         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9891         fourcc = i9xx_format_to_fourcc(pixel_format);
9892         fb->pixel_format = fourcc;
9893         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9894
9895         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9896         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9897                 offset = I915_READ(DSPOFFSET(pipe));
9898         } else {
9899                 if (plane_config->tiling)
9900                         offset = I915_READ(DSPTILEOFF(pipe));
9901                 else
9902                         offset = I915_READ(DSPLINOFF(pipe));
9903         }
9904         plane_config->base = base;
9905
9906         val = I915_READ(PIPESRC(pipe));
9907         fb->width = ((val >> 16) & 0xfff) + 1;
9908         fb->height = ((val >> 0) & 0xfff) + 1;
9909
9910         val = I915_READ(DSPSTRIDE(pipe));
9911         fb->pitches[0] = val & 0xffffffc0;
9912
9913         aligned_height = intel_fb_align_height(dev, fb->height,
9914                                                fb->pixel_format,
9915                                                fb->modifier);
9916
9917         plane_config->size = fb->pitches[0] * aligned_height;
9918
9919         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9920                       pipe_name(pipe), fb->width, fb->height,
9921                       fb->bits_per_pixel, base, fb->pitches[0],
9922                       plane_config->size);
9923
9924         plane_config->fb = intel_fb;
9925 }
9926
9927 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9928                                      struct intel_crtc_state *pipe_config)
9929 {
9930         struct drm_device *dev = crtc->base.dev;
9931         struct drm_i915_private *dev_priv = to_i915(dev);
9932         enum intel_display_power_domain power_domain;
9933         uint32_t tmp;
9934         bool ret;
9935
9936         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9937         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9938                 return false;
9939
9940         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9941         pipe_config->shared_dpll = NULL;
9942
9943         ret = false;
9944         tmp = I915_READ(PIPECONF(crtc->pipe));
9945         if (!(tmp & PIPECONF_ENABLE))
9946                 goto out;
9947
9948         switch (tmp & PIPECONF_BPC_MASK) {
9949         case PIPECONF_6BPC:
9950                 pipe_config->pipe_bpp = 18;
9951                 break;
9952         case PIPECONF_8BPC:
9953                 pipe_config->pipe_bpp = 24;
9954                 break;
9955         case PIPECONF_10BPC:
9956                 pipe_config->pipe_bpp = 30;
9957                 break;
9958         case PIPECONF_12BPC:
9959                 pipe_config->pipe_bpp = 36;
9960                 break;
9961         default:
9962                 break;
9963         }
9964
9965         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9966                 pipe_config->limited_color_range = true;
9967
9968         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9969                 struct intel_shared_dpll *pll;
9970                 enum intel_dpll_id pll_id;
9971
9972                 pipe_config->has_pch_encoder = true;
9973
9974                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9975                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9976                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9977
9978                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9979
9980                 if (HAS_PCH_IBX(dev_priv)) {
9981                         /*
9982                          * The pipe->pch transcoder and pch transcoder->pll
9983                          * mapping is fixed.
9984                          */
9985                         pll_id = (enum intel_dpll_id) crtc->pipe;
9986                 } else {
9987                         tmp = I915_READ(PCH_DPLL_SEL);
9988                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9989                                 pll_id = DPLL_ID_PCH_PLL_B;
9990                         else
9991                                 pll_id= DPLL_ID_PCH_PLL_A;
9992                 }
9993
9994                 pipe_config->shared_dpll =
9995                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9996                 pll = pipe_config->shared_dpll;
9997
9998                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9999                                                  &pipe_config->dpll_hw_state));
10000
10001                 tmp = pipe_config->dpll_hw_state.dpll;
10002                 pipe_config->pixel_multiplier =
10003                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10004                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10005
10006                 ironlake_pch_clock_get(crtc, pipe_config);
10007         } else {
10008                 pipe_config->pixel_multiplier = 1;
10009         }
10010
10011         intel_get_pipe_timings(crtc, pipe_config);
10012         intel_get_pipe_src_size(crtc, pipe_config);
10013
10014         ironlake_get_pfit_config(crtc, pipe_config);
10015
10016         ret = true;
10017
10018 out:
10019         intel_display_power_put(dev_priv, power_domain);
10020
10021         return ret;
10022 }
10023
10024 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
10025 {
10026         struct drm_device *dev = &dev_priv->drm;
10027         struct intel_crtc *crtc;
10028
10029         for_each_intel_crtc(dev, crtc)
10030                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
10031                      pipe_name(crtc->pipe));
10032
10033         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10034         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10035         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10036         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10037         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10038         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10039              "CPU PWM1 enabled\n");
10040         if (IS_HASWELL(dev_priv))
10041                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10042                      "CPU PWM2 enabled\n");
10043         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10044              "PCH PWM1 enabled\n");
10045         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10046              "Utility pin enabled\n");
10047         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10048
10049         /*
10050          * In theory we can still leave IRQs enabled, as long as only the HPD
10051          * interrupts remain enabled. We used to check for that, but since it's
10052          * gen-specific and since we only disable LCPLL after we fully disable
10053          * the interrupts, the check below should be enough.
10054          */
10055         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10056 }
10057
10058 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10059 {
10060         if (IS_HASWELL(dev_priv))
10061                 return I915_READ(D_COMP_HSW);
10062         else
10063                 return I915_READ(D_COMP_BDW);
10064 }
10065
10066 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10067 {
10068         if (IS_HASWELL(dev_priv)) {
10069                 mutex_lock(&dev_priv->rps.hw_lock);
10070                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10071                                             val))
10072                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10073                 mutex_unlock(&dev_priv->rps.hw_lock);
10074         } else {
10075                 I915_WRITE(D_COMP_BDW, val);
10076                 POSTING_READ(D_COMP_BDW);
10077         }
10078 }
10079
10080 /*
10081  * This function implements pieces of two sequences from BSpec:
10082  * - Sequence for display software to disable LCPLL
10083  * - Sequence for display software to allow package C8+
10084  * The steps implemented here are just the steps that actually touch the LCPLL
10085  * register. Callers should take care of disabling all the display engine
10086  * functions, doing the mode unset, fixing interrupts, etc.
10087  */
10088 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10089                               bool switch_to_fclk, bool allow_power_down)
10090 {
10091         uint32_t val;
10092
10093         assert_can_disable_lcpll(dev_priv);
10094
10095         val = I915_READ(LCPLL_CTL);
10096
10097         if (switch_to_fclk) {
10098                 val |= LCPLL_CD_SOURCE_FCLK;
10099                 I915_WRITE(LCPLL_CTL, val);
10100
10101                 if (wait_for_us(I915_READ(LCPLL_CTL) &
10102                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10103                         DRM_ERROR("Switching to FCLK failed\n");
10104
10105                 val = I915_READ(LCPLL_CTL);
10106         }
10107
10108         val |= LCPLL_PLL_DISABLE;
10109         I915_WRITE(LCPLL_CTL, val);
10110         POSTING_READ(LCPLL_CTL);
10111
10112         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10113                 DRM_ERROR("LCPLL still locked\n");
10114
10115         val = hsw_read_dcomp(dev_priv);
10116         val |= D_COMP_COMP_DISABLE;
10117         hsw_write_dcomp(dev_priv, val);
10118         ndelay(100);
10119
10120         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10121                      1))
10122                 DRM_ERROR("D_COMP RCOMP still in progress\n");
10123
10124         if (allow_power_down) {
10125                 val = I915_READ(LCPLL_CTL);
10126                 val |= LCPLL_POWER_DOWN_ALLOW;
10127                 I915_WRITE(LCPLL_CTL, val);
10128                 POSTING_READ(LCPLL_CTL);
10129         }
10130 }
10131
10132 /*
10133  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10134  * source.
10135  */
10136 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10137 {
10138         uint32_t val;
10139
10140         val = I915_READ(LCPLL_CTL);
10141
10142         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10143                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10144                 return;
10145
10146         /*
10147          * Make sure we're not on PC8 state before disabling PC8, otherwise
10148          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10149          */
10150         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10151
10152         if (val & LCPLL_POWER_DOWN_ALLOW) {
10153                 val &= ~LCPLL_POWER_DOWN_ALLOW;
10154                 I915_WRITE(LCPLL_CTL, val);
10155                 POSTING_READ(LCPLL_CTL);
10156         }
10157
10158         val = hsw_read_dcomp(dev_priv);
10159         val |= D_COMP_COMP_FORCE;
10160         val &= ~D_COMP_COMP_DISABLE;
10161         hsw_write_dcomp(dev_priv, val);
10162
10163         val = I915_READ(LCPLL_CTL);
10164         val &= ~LCPLL_PLL_DISABLE;
10165         I915_WRITE(LCPLL_CTL, val);
10166
10167         if (intel_wait_for_register(dev_priv,
10168                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10169                                     5))
10170                 DRM_ERROR("LCPLL not locked yet\n");
10171
10172         if (val & LCPLL_CD_SOURCE_FCLK) {
10173                 val = I915_READ(LCPLL_CTL);
10174                 val &= ~LCPLL_CD_SOURCE_FCLK;
10175                 I915_WRITE(LCPLL_CTL, val);
10176
10177                 if (wait_for_us((I915_READ(LCPLL_CTL) &
10178                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10179                         DRM_ERROR("Switching back to LCPLL failed\n");
10180         }
10181
10182         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10183         intel_update_cdclk(dev_priv);
10184 }
10185
10186 /*
10187  * Package states C8 and deeper are really deep PC states that can only be
10188  * reached when all the devices on the system allow it, so even if the graphics
10189  * device allows PC8+, it doesn't mean the system will actually get to these
10190  * states. Our driver only allows PC8+ when going into runtime PM.
10191  *
10192  * The requirements for PC8+ are that all the outputs are disabled, the power
10193  * well is disabled and most interrupts are disabled, and these are also
10194  * requirements for runtime PM. When these conditions are met, we manually do
10195  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10196  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10197  * hang the machine.
10198  *
10199  * When we really reach PC8 or deeper states (not just when we allow it) we lose
10200  * the state of some registers, so when we come back from PC8+ we need to
10201  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10202  * need to take care of the registers kept by RC6. Notice that this happens even
10203  * if we don't put the device in PCI D3 state (which is what currently happens
10204  * because of the runtime PM support).
10205  *
10206  * For more, read "Display Sequences for Package C8" on the hardware
10207  * documentation.
10208  */
10209 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10210 {
10211         uint32_t val;
10212
10213         DRM_DEBUG_KMS("Enabling package C8+\n");
10214
10215         if (HAS_PCH_LPT_LP(dev_priv)) {
10216                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10217                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10218                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10219         }
10220
10221         lpt_disable_clkout_dp(dev_priv);
10222         hsw_disable_lcpll(dev_priv, true, true);
10223 }
10224
10225 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10226 {
10227         uint32_t val;
10228
10229         DRM_DEBUG_KMS("Disabling package C8+\n");
10230
10231         hsw_restore_lcpll(dev_priv);
10232         lpt_init_pch_refclk(dev_priv);
10233
10234         if (HAS_PCH_LPT_LP(dev_priv)) {
10235                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10236                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10237                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10238         }
10239 }
10240
10241 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10242 {
10243         struct drm_device *dev = old_state->dev;
10244         struct intel_atomic_state *old_intel_state =
10245                 to_intel_atomic_state(old_state);
10246         unsigned int req_cdclk = old_intel_state->dev_cdclk;
10247
10248         bxt_set_cdclk(to_i915(dev), req_cdclk);
10249 }
10250
10251 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
10252                                           int pixel_rate)
10253 {
10254         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
10255
10256         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10257         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10258                 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10259
10260         /* BSpec says "Do not use DisplayPort with CDCLK less than
10261          * 432 MHz, audio enabled, port width x4, and link rate
10262          * HBR2 (5.4 GHz), or else there may be audio corruption or
10263          * screen corruption."
10264          */
10265         if (intel_crtc_has_dp_encoder(crtc_state) &&
10266             crtc_state->has_audio &&
10267             crtc_state->port_clock >= 540000 &&
10268             crtc_state->lane_count == 4)
10269                 pixel_rate = max(432000, pixel_rate);
10270
10271         return pixel_rate;
10272 }
10273
10274 /* compute the max rate for new configuration */
10275 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10276 {
10277         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10278         struct drm_i915_private *dev_priv = to_i915(state->dev);
10279         struct drm_crtc *crtc;
10280         struct drm_crtc_state *cstate;
10281         struct intel_crtc_state *crtc_state;
10282         unsigned max_pixel_rate = 0, i;
10283         enum pipe pipe;
10284
10285         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10286                sizeof(intel_state->min_pixclk));
10287
10288         for_each_crtc_in_state(state, crtc, cstate, i) {
10289                 int pixel_rate;
10290
10291                 crtc_state = to_intel_crtc_state(cstate);
10292                 if (!crtc_state->base.enable) {
10293                         intel_state->min_pixclk[i] = 0;
10294                         continue;
10295                 }
10296
10297                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10298
10299                 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
10300                         pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
10301                                                                     pixel_rate);
10302
10303                 intel_state->min_pixclk[i] = pixel_rate;
10304         }
10305
10306         for_each_pipe(dev_priv, pipe)
10307                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10308
10309         return max_pixel_rate;
10310 }
10311
10312 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10313 {
10314         struct drm_i915_private *dev_priv = to_i915(dev);
10315         uint32_t val, data;
10316         int ret;
10317
10318         if (WARN((I915_READ(LCPLL_CTL) &
10319                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10320                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10321                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10322                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10323                  "trying to change cdclk frequency with cdclk not enabled\n"))
10324                 return;
10325
10326         mutex_lock(&dev_priv->rps.hw_lock);
10327         ret = sandybridge_pcode_write(dev_priv,
10328                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10329         mutex_unlock(&dev_priv->rps.hw_lock);
10330         if (ret) {
10331                 DRM_ERROR("failed to inform pcode about cdclk change\n");
10332                 return;
10333         }
10334
10335         val = I915_READ(LCPLL_CTL);
10336         val |= LCPLL_CD_SOURCE_FCLK;
10337         I915_WRITE(LCPLL_CTL, val);
10338
10339         if (wait_for_us(I915_READ(LCPLL_CTL) &
10340                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
10341                 DRM_ERROR("Switching to FCLK failed\n");
10342
10343         val = I915_READ(LCPLL_CTL);
10344         val &= ~LCPLL_CLK_FREQ_MASK;
10345
10346         switch (cdclk) {
10347         case 450000:
10348                 val |= LCPLL_CLK_FREQ_450;
10349                 data = 0;
10350                 break;
10351         case 540000:
10352                 val |= LCPLL_CLK_FREQ_54O_BDW;
10353                 data = 1;
10354                 break;
10355         case 337500:
10356                 val |= LCPLL_CLK_FREQ_337_5_BDW;
10357                 data = 2;
10358                 break;
10359         case 675000:
10360                 val |= LCPLL_CLK_FREQ_675_BDW;
10361                 data = 3;
10362                 break;
10363         default:
10364                 WARN(1, "invalid cdclk frequency\n");
10365                 return;
10366         }
10367
10368         I915_WRITE(LCPLL_CTL, val);
10369
10370         val = I915_READ(LCPLL_CTL);
10371         val &= ~LCPLL_CD_SOURCE_FCLK;
10372         I915_WRITE(LCPLL_CTL, val);
10373
10374         if (wait_for_us((I915_READ(LCPLL_CTL) &
10375                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10376                 DRM_ERROR("Switching back to LCPLL failed\n");
10377
10378         mutex_lock(&dev_priv->rps.hw_lock);
10379         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10380         mutex_unlock(&dev_priv->rps.hw_lock);
10381
10382         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10383
10384         intel_update_cdclk(dev_priv);
10385
10386         WARN(cdclk != dev_priv->cdclk_freq,
10387              "cdclk requested %d kHz but got %d kHz\n",
10388              cdclk, dev_priv->cdclk_freq);
10389 }
10390
10391 static int broadwell_calc_cdclk(int max_pixclk)
10392 {
10393         if (max_pixclk > 540000)
10394                 return 675000;
10395         else if (max_pixclk > 450000)
10396                 return 540000;
10397         else if (max_pixclk > 337500)
10398                 return 450000;
10399         else
10400                 return 337500;
10401 }
10402
10403 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10404 {
10405         struct drm_i915_private *dev_priv = to_i915(state->dev);
10406         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10407         int max_pixclk = ilk_max_pixel_rate(state);
10408         int cdclk;
10409
10410         /*
10411          * FIXME should also account for plane ratio
10412          * once 64bpp pixel formats are supported.
10413          */
10414         cdclk = broadwell_calc_cdclk(max_pixclk);
10415
10416         if (cdclk > dev_priv->max_cdclk_freq) {
10417                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10418                               cdclk, dev_priv->max_cdclk_freq);
10419                 return -EINVAL;
10420         }
10421
10422         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10423         if (!intel_state->active_crtcs)
10424                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10425
10426         return 0;
10427 }
10428
10429 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10430 {
10431         struct drm_device *dev = old_state->dev;
10432         struct intel_atomic_state *old_intel_state =
10433                 to_intel_atomic_state(old_state);
10434         unsigned req_cdclk = old_intel_state->dev_cdclk;
10435
10436         broadwell_set_cdclk(dev, req_cdclk);
10437 }
10438
10439 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10440 {
10441         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10442         struct drm_i915_private *dev_priv = to_i915(state->dev);
10443         const int max_pixclk = ilk_max_pixel_rate(state);
10444         int vco = intel_state->cdclk_pll_vco;
10445         int cdclk;
10446
10447         /*
10448          * FIXME should also account for plane ratio
10449          * once 64bpp pixel formats are supported.
10450          */
10451         cdclk = skl_calc_cdclk(max_pixclk, vco);
10452
10453         /*
10454          * FIXME move the cdclk caclulation to
10455          * compute_config() so we can fail gracegully.
10456          */
10457         if (cdclk > dev_priv->max_cdclk_freq) {
10458                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10459                           cdclk, dev_priv->max_cdclk_freq);
10460                 cdclk = dev_priv->max_cdclk_freq;
10461         }
10462
10463         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10464         if (!intel_state->active_crtcs)
10465                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10466
10467         return 0;
10468 }
10469
10470 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10471 {
10472         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10473         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10474         unsigned int req_cdclk = intel_state->dev_cdclk;
10475         unsigned int req_vco = intel_state->cdclk_pll_vco;
10476
10477         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10478 }
10479
10480 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10481                                       struct intel_crtc_state *crtc_state)
10482 {
10483         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10484                 if (!intel_ddi_pll_select(crtc, crtc_state))
10485                         return -EINVAL;
10486         }
10487
10488         crtc->lowfreq_avail = false;
10489
10490         return 0;
10491 }
10492
10493 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10494                                 enum port port,
10495                                 struct intel_crtc_state *pipe_config)
10496 {
10497         enum intel_dpll_id id;
10498
10499         switch (port) {
10500         case PORT_A:
10501                 id = DPLL_ID_SKL_DPLL0;
10502                 break;
10503         case PORT_B:
10504                 id = DPLL_ID_SKL_DPLL1;
10505                 break;
10506         case PORT_C:
10507                 id = DPLL_ID_SKL_DPLL2;
10508                 break;
10509         default:
10510                 DRM_ERROR("Incorrect port type\n");
10511                 return;
10512         }
10513
10514         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10515 }
10516
10517 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10518                                 enum port port,
10519                                 struct intel_crtc_state *pipe_config)
10520 {
10521         enum intel_dpll_id id;
10522         u32 temp;
10523
10524         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10525         id = temp >> (port * 3 + 1);
10526
10527         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10528                 return;
10529
10530         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10531 }
10532
10533 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10534                                 enum port port,
10535                                 struct intel_crtc_state *pipe_config)
10536 {
10537         enum intel_dpll_id id;
10538         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10539
10540         switch (ddi_pll_sel) {
10541         case PORT_CLK_SEL_WRPLL1:
10542                 id = DPLL_ID_WRPLL1;
10543                 break;
10544         case PORT_CLK_SEL_WRPLL2:
10545                 id = DPLL_ID_WRPLL2;
10546                 break;
10547         case PORT_CLK_SEL_SPLL:
10548                 id = DPLL_ID_SPLL;
10549                 break;
10550         case PORT_CLK_SEL_LCPLL_810:
10551                 id = DPLL_ID_LCPLL_810;
10552                 break;
10553         case PORT_CLK_SEL_LCPLL_1350:
10554                 id = DPLL_ID_LCPLL_1350;
10555                 break;
10556         case PORT_CLK_SEL_LCPLL_2700:
10557                 id = DPLL_ID_LCPLL_2700;
10558                 break;
10559         default:
10560                 MISSING_CASE(ddi_pll_sel);
10561                 /* fall through */
10562         case PORT_CLK_SEL_NONE:
10563                 return;
10564         }
10565
10566         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10567 }
10568
10569 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10570                                      struct intel_crtc_state *pipe_config,
10571                                      unsigned long *power_domain_mask)
10572 {
10573         struct drm_device *dev = crtc->base.dev;
10574         struct drm_i915_private *dev_priv = to_i915(dev);
10575         enum intel_display_power_domain power_domain;
10576         u32 tmp;
10577
10578         /*
10579          * The pipe->transcoder mapping is fixed with the exception of the eDP
10580          * transcoder handled below.
10581          */
10582         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10583
10584         /*
10585          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10586          * consistency and less surprising code; it's in always on power).
10587          */
10588         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10589         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10590                 enum pipe trans_edp_pipe;
10591                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10592                 default:
10593                         WARN(1, "unknown pipe linked to edp transcoder\n");
10594                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10595                 case TRANS_DDI_EDP_INPUT_A_ON:
10596                         trans_edp_pipe = PIPE_A;
10597                         break;
10598                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10599                         trans_edp_pipe = PIPE_B;
10600                         break;
10601                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10602                         trans_edp_pipe = PIPE_C;
10603                         break;
10604                 }
10605
10606                 if (trans_edp_pipe == crtc->pipe)
10607                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10608         }
10609
10610         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10611         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10612                 return false;
10613         *power_domain_mask |= BIT(power_domain);
10614
10615         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10616
10617         return tmp & PIPECONF_ENABLE;
10618 }
10619
10620 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10621                                          struct intel_crtc_state *pipe_config,
10622                                          unsigned long *power_domain_mask)
10623 {
10624         struct drm_device *dev = crtc->base.dev;
10625         struct drm_i915_private *dev_priv = to_i915(dev);
10626         enum intel_display_power_domain power_domain;
10627         enum port port;
10628         enum transcoder cpu_transcoder;
10629         u32 tmp;
10630
10631         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10632                 if (port == PORT_A)
10633                         cpu_transcoder = TRANSCODER_DSI_A;
10634                 else
10635                         cpu_transcoder = TRANSCODER_DSI_C;
10636
10637                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10638                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10639                         continue;
10640                 *power_domain_mask |= BIT(power_domain);
10641
10642                 /*
10643                  * The PLL needs to be enabled with a valid divider
10644                  * configuration, otherwise accessing DSI registers will hang
10645                  * the machine. See BSpec North Display Engine
10646                  * registers/MIPI[BXT]. We can break out here early, since we
10647                  * need the same DSI PLL to be enabled for both DSI ports.
10648                  */
10649                 if (!intel_dsi_pll_is_enabled(dev_priv))
10650                         break;
10651
10652                 /* XXX: this works for video mode only */
10653                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10654                 if (!(tmp & DPI_ENABLE))
10655                         continue;
10656
10657                 tmp = I915_READ(MIPI_CTRL(port));
10658                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10659                         continue;
10660
10661                 pipe_config->cpu_transcoder = cpu_transcoder;
10662                 break;
10663         }
10664
10665         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10666 }
10667
10668 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10669                                        struct intel_crtc_state *pipe_config)
10670 {
10671         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10672         struct intel_shared_dpll *pll;
10673         enum port port;
10674         uint32_t tmp;
10675
10676         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10677
10678         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10679
10680         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
10681                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10682         else if (IS_GEN9_LP(dev_priv))
10683                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10684         else
10685                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10686
10687         pll = pipe_config->shared_dpll;
10688         if (pll) {
10689                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10690                                                  &pipe_config->dpll_hw_state));
10691         }
10692
10693         /*
10694          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10695          * DDI E. So just check whether this pipe is wired to DDI E and whether
10696          * the PCH transcoder is on.
10697          */
10698         if (INTEL_GEN(dev_priv) < 9 &&
10699             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10700                 pipe_config->has_pch_encoder = true;
10701
10702                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10703                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10704                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10705
10706                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10707         }
10708 }
10709
10710 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10711                                     struct intel_crtc_state *pipe_config)
10712 {
10713         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10714         enum intel_display_power_domain power_domain;
10715         unsigned long power_domain_mask;
10716         bool active;
10717
10718         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10719         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10720                 return false;
10721         power_domain_mask = BIT(power_domain);
10722
10723         pipe_config->shared_dpll = NULL;
10724
10725         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10726
10727         if (IS_GEN9_LP(dev_priv) &&
10728             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10729                 WARN_ON(active);
10730                 active = true;
10731         }
10732
10733         if (!active)
10734                 goto out;
10735
10736         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10737                 haswell_get_ddi_port_state(crtc, pipe_config);
10738                 intel_get_pipe_timings(crtc, pipe_config);
10739         }
10740
10741         intel_get_pipe_src_size(crtc, pipe_config);
10742
10743         pipe_config->gamma_mode =
10744                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10745
10746         if (INTEL_GEN(dev_priv) >= 9) {
10747                 intel_crtc_init_scalers(crtc, pipe_config);
10748
10749                 pipe_config->scaler_state.scaler_id = -1;
10750                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10751         }
10752
10753         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10754         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10755                 power_domain_mask |= BIT(power_domain);
10756                 if (INTEL_GEN(dev_priv) >= 9)
10757                         skylake_get_pfit_config(crtc, pipe_config);
10758                 else
10759                         ironlake_get_pfit_config(crtc, pipe_config);
10760         }
10761
10762         if (IS_HASWELL(dev_priv))
10763                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10764                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10765
10766         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10767             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10768                 pipe_config->pixel_multiplier =
10769                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10770         } else {
10771                 pipe_config->pixel_multiplier = 1;
10772         }
10773
10774 out:
10775         for_each_power_domain(power_domain, power_domain_mask)
10776                 intel_display_power_put(dev_priv, power_domain);
10777
10778         return active;
10779 }
10780
10781 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10782                                const struct intel_plane_state *plane_state)
10783 {
10784         struct drm_device *dev = crtc->dev;
10785         struct drm_i915_private *dev_priv = to_i915(dev);
10786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10787         uint32_t cntl = 0, size = 0;
10788
10789         if (plane_state && plane_state->base.visible) {
10790                 unsigned int width = plane_state->base.crtc_w;
10791                 unsigned int height = plane_state->base.crtc_h;
10792                 unsigned int stride = roundup_pow_of_two(width) * 4;
10793
10794                 switch (stride) {
10795                 default:
10796                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10797                                   width, stride);
10798                         stride = 256;
10799                         /* fallthrough */
10800                 case 256:
10801                 case 512:
10802                 case 1024:
10803                 case 2048:
10804                         break;
10805                 }
10806
10807                 cntl |= CURSOR_ENABLE |
10808                         CURSOR_GAMMA_ENABLE |
10809                         CURSOR_FORMAT_ARGB |
10810                         CURSOR_STRIDE(stride);
10811
10812                 size = (height << 12) | width;
10813         }
10814
10815         if (intel_crtc->cursor_cntl != 0 &&
10816             (intel_crtc->cursor_base != base ||
10817              intel_crtc->cursor_size != size ||
10818              intel_crtc->cursor_cntl != cntl)) {
10819                 /* On these chipsets we can only modify the base/size/stride
10820                  * whilst the cursor is disabled.
10821                  */
10822                 I915_WRITE(CURCNTR(PIPE_A), 0);
10823                 POSTING_READ(CURCNTR(PIPE_A));
10824                 intel_crtc->cursor_cntl = 0;
10825         }
10826
10827         if (intel_crtc->cursor_base != base) {
10828                 I915_WRITE(CURBASE(PIPE_A), base);
10829                 intel_crtc->cursor_base = base;
10830         }
10831
10832         if (intel_crtc->cursor_size != size) {
10833                 I915_WRITE(CURSIZE, size);
10834                 intel_crtc->cursor_size = size;
10835         }
10836
10837         if (intel_crtc->cursor_cntl != cntl) {
10838                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10839                 POSTING_READ(CURCNTR(PIPE_A));
10840                 intel_crtc->cursor_cntl = cntl;
10841         }
10842 }
10843
10844 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10845                                const struct intel_plane_state *plane_state)
10846 {
10847         struct drm_device *dev = crtc->dev;
10848         struct drm_i915_private *dev_priv = to_i915(dev);
10849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10850         int pipe = intel_crtc->pipe;
10851         uint32_t cntl = 0;
10852
10853         if (plane_state && plane_state->base.visible) {
10854                 cntl = MCURSOR_GAMMA_ENABLE;
10855                 switch (plane_state->base.crtc_w) {
10856                         case 64:
10857                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10858                                 break;
10859                         case 128:
10860                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10861                                 break;
10862                         case 256:
10863                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10864                                 break;
10865                         default:
10866                                 MISSING_CASE(plane_state->base.crtc_w);
10867                                 return;
10868                 }
10869                 cntl |= pipe << 28; /* Connect to correct pipe */
10870
10871                 if (HAS_DDI(dev_priv))
10872                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10873
10874                 if (plane_state->base.rotation & DRM_ROTATE_180)
10875                         cntl |= CURSOR_ROTATE_180;
10876         }
10877
10878         if (intel_crtc->cursor_cntl != cntl) {
10879                 I915_WRITE(CURCNTR(pipe), cntl);
10880                 POSTING_READ(CURCNTR(pipe));
10881                 intel_crtc->cursor_cntl = cntl;
10882         }
10883
10884         /* and commit changes on next vblank */
10885         I915_WRITE(CURBASE(pipe), base);
10886         POSTING_READ(CURBASE(pipe));
10887
10888         intel_crtc->cursor_base = base;
10889 }
10890
10891 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10892 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10893                                      const struct intel_plane_state *plane_state)
10894 {
10895         struct drm_device *dev = crtc->dev;
10896         struct drm_i915_private *dev_priv = to_i915(dev);
10897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10898         int pipe = intel_crtc->pipe;
10899         u32 base = intel_crtc->cursor_addr;
10900         u32 pos = 0;
10901
10902         if (plane_state) {
10903                 int x = plane_state->base.crtc_x;
10904                 int y = plane_state->base.crtc_y;
10905
10906                 if (x < 0) {
10907                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10908                         x = -x;
10909                 }
10910                 pos |= x << CURSOR_X_SHIFT;
10911
10912                 if (y < 0) {
10913                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10914                         y = -y;
10915                 }
10916                 pos |= y << CURSOR_Y_SHIFT;
10917
10918                 /* ILK+ do this automagically */
10919                 if (HAS_GMCH_DISPLAY(dev_priv) &&
10920                     plane_state->base.rotation & DRM_ROTATE_180) {
10921                         base += (plane_state->base.crtc_h *
10922                                  plane_state->base.crtc_w - 1) * 4;
10923                 }
10924         }
10925
10926         I915_WRITE(CURPOS(pipe), pos);
10927
10928         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
10929                 i845_update_cursor(crtc, base, plane_state);
10930         else
10931                 i9xx_update_cursor(crtc, base, plane_state);
10932 }
10933
10934 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
10935                            uint32_t width, uint32_t height)
10936 {
10937         if (width == 0 || height == 0)
10938                 return false;
10939
10940         /*
10941          * 845g/865g are special in that they are only limited by
10942          * the width of their cursors, the height is arbitrary up to
10943          * the precision of the register. Everything else requires
10944          * square cursors, limited to a few power-of-two sizes.
10945          */
10946         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
10947                 if ((width & 63) != 0)
10948                         return false;
10949
10950                 if (width > (IS_I845G(dev_priv) ? 64 : 512))
10951                         return false;
10952
10953                 if (height > 1023)
10954                         return false;
10955         } else {
10956                 switch (width | height) {
10957                 case 256:
10958                 case 128:
10959                         if (IS_GEN2(dev_priv))
10960                                 return false;
10961                 case 64:
10962                         break;
10963                 default:
10964                         return false;
10965                 }
10966         }
10967
10968         return true;
10969 }
10970
10971 /* VESA 640x480x72Hz mode to set on the pipe */
10972 static struct drm_display_mode load_detect_mode = {
10973         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10974                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10975 };
10976
10977 struct drm_framebuffer *
10978 __intel_framebuffer_create(struct drm_device *dev,
10979                            struct drm_mode_fb_cmd2 *mode_cmd,
10980                            struct drm_i915_gem_object *obj)
10981 {
10982         struct intel_framebuffer *intel_fb;
10983         int ret;
10984
10985         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10986         if (!intel_fb)
10987                 return ERR_PTR(-ENOMEM);
10988
10989         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10990         if (ret)
10991                 goto err;
10992
10993         return &intel_fb->base;
10994
10995 err:
10996         kfree(intel_fb);
10997         return ERR_PTR(ret);
10998 }
10999
11000 static struct drm_framebuffer *
11001 intel_framebuffer_create(struct drm_device *dev,
11002                          struct drm_mode_fb_cmd2 *mode_cmd,
11003                          struct drm_i915_gem_object *obj)
11004 {
11005         struct drm_framebuffer *fb;
11006         int ret;
11007
11008         ret = i915_mutex_lock_interruptible(dev);
11009         if (ret)
11010                 return ERR_PTR(ret);
11011         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
11012         mutex_unlock(&dev->struct_mutex);
11013
11014         return fb;
11015 }
11016
11017 static u32
11018 intel_framebuffer_pitch_for_width(int width, int bpp)
11019 {
11020         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
11021         return ALIGN(pitch, 64);
11022 }
11023
11024 static u32
11025 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
11026 {
11027         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
11028         return PAGE_ALIGN(pitch * mode->vdisplay);
11029 }
11030
11031 static struct drm_framebuffer *
11032 intel_framebuffer_create_for_mode(struct drm_device *dev,
11033                                   struct drm_display_mode *mode,
11034                                   int depth, int bpp)
11035 {
11036         struct drm_framebuffer *fb;
11037         struct drm_i915_gem_object *obj;
11038         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
11039
11040         obj = i915_gem_object_create(to_i915(dev),
11041                                     intel_framebuffer_size_for_mode(mode, bpp));
11042         if (IS_ERR(obj))
11043                 return ERR_CAST(obj);
11044
11045         mode_cmd.width = mode->hdisplay;
11046         mode_cmd.height = mode->vdisplay;
11047         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11048                                                                 bpp);
11049         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11050
11051         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11052         if (IS_ERR(fb))
11053                 i915_gem_object_put(obj);
11054
11055         return fb;
11056 }
11057
11058 static struct drm_framebuffer *
11059 mode_fits_in_fbdev(struct drm_device *dev,
11060                    struct drm_display_mode *mode)
11061 {
11062 #ifdef CONFIG_DRM_FBDEV_EMULATION
11063         struct drm_i915_private *dev_priv = to_i915(dev);
11064         struct drm_i915_gem_object *obj;
11065         struct drm_framebuffer *fb;
11066
11067         if (!dev_priv->fbdev)
11068                 return NULL;
11069
11070         if (!dev_priv->fbdev->fb)
11071                 return NULL;
11072
11073         obj = dev_priv->fbdev->fb->obj;
11074         BUG_ON(!obj);
11075
11076         fb = &dev_priv->fbdev->fb->base;
11077         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11078                                                                fb->bits_per_pixel))
11079                 return NULL;
11080
11081         if (obj->base.size < mode->vdisplay * fb->pitches[0])
11082                 return NULL;
11083
11084         drm_framebuffer_reference(fb);
11085         return fb;
11086 #else
11087         return NULL;
11088 #endif
11089 }
11090
11091 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11092                                            struct drm_crtc *crtc,
11093                                            struct drm_display_mode *mode,
11094                                            struct drm_framebuffer *fb,
11095                                            int x, int y)
11096 {
11097         struct drm_plane_state *plane_state;
11098         int hdisplay, vdisplay;
11099         int ret;
11100
11101         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11102         if (IS_ERR(plane_state))
11103                 return PTR_ERR(plane_state);
11104
11105         if (mode)
11106                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11107         else
11108                 hdisplay = vdisplay = 0;
11109
11110         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11111         if (ret)
11112                 return ret;
11113         drm_atomic_set_fb_for_plane(plane_state, fb);
11114         plane_state->crtc_x = 0;
11115         plane_state->crtc_y = 0;
11116         plane_state->crtc_w = hdisplay;
11117         plane_state->crtc_h = vdisplay;
11118         plane_state->src_x = x << 16;
11119         plane_state->src_y = y << 16;
11120         plane_state->src_w = hdisplay << 16;
11121         plane_state->src_h = vdisplay << 16;
11122
11123         return 0;
11124 }
11125
11126 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11127                                 struct drm_display_mode *mode,
11128                                 struct intel_load_detect_pipe *old,
11129                                 struct drm_modeset_acquire_ctx *ctx)
11130 {
11131         struct intel_crtc *intel_crtc;
11132         struct intel_encoder *intel_encoder =
11133                 intel_attached_encoder(connector);
11134         struct drm_crtc *possible_crtc;
11135         struct drm_encoder *encoder = &intel_encoder->base;
11136         struct drm_crtc *crtc = NULL;
11137         struct drm_device *dev = encoder->dev;
11138         struct drm_i915_private *dev_priv = to_i915(dev);
11139         struct drm_framebuffer *fb;
11140         struct drm_mode_config *config = &dev->mode_config;
11141         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11142         struct drm_connector_state *connector_state;
11143         struct intel_crtc_state *crtc_state;
11144         int ret, i = -1;
11145
11146         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11147                       connector->base.id, connector->name,
11148                       encoder->base.id, encoder->name);
11149
11150         old->restore_state = NULL;
11151
11152 retry:
11153         ret = drm_modeset_lock(&config->connection_mutex, ctx);
11154         if (ret)
11155                 goto fail;
11156
11157         /*
11158          * Algorithm gets a little messy:
11159          *
11160          *   - if the connector already has an assigned crtc, use it (but make
11161          *     sure it's on first)
11162          *
11163          *   - try to find the first unused crtc that can drive this connector,
11164          *     and use that if we find one
11165          */
11166
11167         /* See if we already have a CRTC for this connector */
11168         if (connector->state->crtc) {
11169                 crtc = connector->state->crtc;
11170
11171                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11172                 if (ret)
11173                         goto fail;
11174
11175                 /* Make sure the crtc and connector are running */
11176                 goto found;
11177         }
11178
11179         /* Find an unused one (if possible) */
11180         for_each_crtc(dev, possible_crtc) {
11181                 i++;
11182                 if (!(encoder->possible_crtcs & (1 << i)))
11183                         continue;
11184
11185                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11186                 if (ret)
11187                         goto fail;
11188
11189                 if (possible_crtc->state->enable) {
11190                         drm_modeset_unlock(&possible_crtc->mutex);
11191                         continue;
11192                 }
11193
11194                 crtc = possible_crtc;
11195                 break;
11196         }
11197
11198         /*
11199          * If we didn't find an unused CRTC, don't use any.
11200          */
11201         if (!crtc) {
11202                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11203                 goto fail;
11204         }
11205
11206 found:
11207         intel_crtc = to_intel_crtc(crtc);
11208
11209         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11210         if (ret)
11211                 goto fail;
11212
11213         state = drm_atomic_state_alloc(dev);
11214         restore_state = drm_atomic_state_alloc(dev);
11215         if (!state || !restore_state) {
11216                 ret = -ENOMEM;
11217                 goto fail;
11218         }
11219
11220         state->acquire_ctx = ctx;
11221         restore_state->acquire_ctx = ctx;
11222
11223         connector_state = drm_atomic_get_connector_state(state, connector);
11224         if (IS_ERR(connector_state)) {
11225                 ret = PTR_ERR(connector_state);
11226                 goto fail;
11227         }
11228
11229         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11230         if (ret)
11231                 goto fail;
11232
11233         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11234         if (IS_ERR(crtc_state)) {
11235                 ret = PTR_ERR(crtc_state);
11236                 goto fail;
11237         }
11238
11239         crtc_state->base.active = crtc_state->base.enable = true;
11240
11241         if (!mode)
11242                 mode = &load_detect_mode;
11243
11244         /* We need a framebuffer large enough to accommodate all accesses
11245          * that the plane may generate whilst we perform load detection.
11246          * We can not rely on the fbcon either being present (we get called
11247          * during its initialisation to detect all boot displays, or it may
11248          * not even exist) or that it is large enough to satisfy the
11249          * requested mode.
11250          */
11251         fb = mode_fits_in_fbdev(dev, mode);
11252         if (fb == NULL) {
11253                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11254                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11255         } else
11256                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11257         if (IS_ERR(fb)) {
11258                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11259                 goto fail;
11260         }
11261
11262         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11263         if (ret)
11264                 goto fail;
11265
11266         drm_framebuffer_unreference(fb);
11267
11268         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11269         if (ret)
11270                 goto fail;
11271
11272         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11273         if (!ret)
11274                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11275         if (!ret)
11276                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11277         if (ret) {
11278                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11279                 goto fail;
11280         }
11281
11282         ret = drm_atomic_commit(state);
11283         if (ret) {
11284                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11285                 goto fail;
11286         }
11287
11288         old->restore_state = restore_state;
11289
11290         /* let the connector get through one full cycle before testing */
11291         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11292         return true;
11293
11294 fail:
11295         if (state) {
11296                 drm_atomic_state_put(state);
11297                 state = NULL;
11298         }
11299         if (restore_state) {
11300                 drm_atomic_state_put(restore_state);
11301                 restore_state = NULL;
11302         }
11303
11304         if (ret == -EDEADLK) {
11305                 drm_modeset_backoff(ctx);
11306                 goto retry;
11307         }
11308
11309         return false;
11310 }
11311
11312 void intel_release_load_detect_pipe(struct drm_connector *connector,
11313                                     struct intel_load_detect_pipe *old,
11314                                     struct drm_modeset_acquire_ctx *ctx)
11315 {
11316         struct intel_encoder *intel_encoder =
11317                 intel_attached_encoder(connector);
11318         struct drm_encoder *encoder = &intel_encoder->base;
11319         struct drm_atomic_state *state = old->restore_state;
11320         int ret;
11321
11322         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11323                       connector->base.id, connector->name,
11324                       encoder->base.id, encoder->name);
11325
11326         if (!state)
11327                 return;
11328
11329         ret = drm_atomic_commit(state);
11330         if (ret)
11331                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11332         drm_atomic_state_put(state);
11333 }
11334
11335 static int i9xx_pll_refclk(struct drm_device *dev,
11336                            const struct intel_crtc_state *pipe_config)
11337 {
11338         struct drm_i915_private *dev_priv = to_i915(dev);
11339         u32 dpll = pipe_config->dpll_hw_state.dpll;
11340
11341         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11342                 return dev_priv->vbt.lvds_ssc_freq;
11343         else if (HAS_PCH_SPLIT(dev_priv))
11344                 return 120000;
11345         else if (!IS_GEN2(dev_priv))
11346                 return 96000;
11347         else
11348                 return 48000;
11349 }
11350
11351 /* Returns the clock of the currently programmed mode of the given pipe. */
11352 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11353                                 struct intel_crtc_state *pipe_config)
11354 {
11355         struct drm_device *dev = crtc->base.dev;
11356         struct drm_i915_private *dev_priv = to_i915(dev);
11357         int pipe = pipe_config->cpu_transcoder;
11358         u32 dpll = pipe_config->dpll_hw_state.dpll;
11359         u32 fp;
11360         struct dpll clock;
11361         int port_clock;
11362         int refclk = i9xx_pll_refclk(dev, pipe_config);
11363
11364         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11365                 fp = pipe_config->dpll_hw_state.fp0;
11366         else
11367                 fp = pipe_config->dpll_hw_state.fp1;
11368
11369         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11370         if (IS_PINEVIEW(dev_priv)) {
11371                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11372                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11373         } else {
11374                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11375                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11376         }
11377
11378         if (!IS_GEN2(dev_priv)) {
11379                 if (IS_PINEVIEW(dev_priv))
11380                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11381                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11382                 else
11383                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11384                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11385
11386                 switch (dpll & DPLL_MODE_MASK) {
11387                 case DPLLB_MODE_DAC_SERIAL:
11388                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11389                                 5 : 10;
11390                         break;
11391                 case DPLLB_MODE_LVDS:
11392                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11393                                 7 : 14;
11394                         break;
11395                 default:
11396                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11397                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11398                         return;
11399                 }
11400
11401                 if (IS_PINEVIEW(dev_priv))
11402                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11403                 else
11404                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11405         } else {
11406                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11407                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11408
11409                 if (is_lvds) {
11410                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11411                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11412
11413                         if (lvds & LVDS_CLKB_POWER_UP)
11414                                 clock.p2 = 7;
11415                         else
11416                                 clock.p2 = 14;
11417                 } else {
11418                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11419                                 clock.p1 = 2;
11420                         else {
11421                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11422                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11423                         }
11424                         if (dpll & PLL_P2_DIVIDE_BY_4)
11425                                 clock.p2 = 4;
11426                         else
11427                                 clock.p2 = 2;
11428                 }
11429
11430                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11431         }
11432
11433         /*
11434          * This value includes pixel_multiplier. We will use
11435          * port_clock to compute adjusted_mode.crtc_clock in the
11436          * encoder's get_config() function.
11437          */
11438         pipe_config->port_clock = port_clock;
11439 }
11440
11441 int intel_dotclock_calculate(int link_freq,
11442                              const struct intel_link_m_n *m_n)
11443 {
11444         /*
11445          * The calculation for the data clock is:
11446          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11447          * But we want to avoid losing precison if possible, so:
11448          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11449          *
11450          * and the link clock is simpler:
11451          * link_clock = (m * link_clock) / n
11452          */
11453
11454         if (!m_n->link_n)
11455                 return 0;
11456
11457         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11458 }
11459
11460 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11461                                    struct intel_crtc_state *pipe_config)
11462 {
11463         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11464
11465         /* read out port_clock from the DPLL */
11466         i9xx_crtc_clock_get(crtc, pipe_config);
11467
11468         /*
11469          * In case there is an active pipe without active ports,
11470          * we may need some idea for the dotclock anyway.
11471          * Calculate one based on the FDI configuration.
11472          */
11473         pipe_config->base.adjusted_mode.crtc_clock =
11474                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11475                                          &pipe_config->fdi_m_n);
11476 }
11477
11478 /** Returns the currently programmed mode of the given pipe. */
11479 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11480                                              struct drm_crtc *crtc)
11481 {
11482         struct drm_i915_private *dev_priv = to_i915(dev);
11483         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11484         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11485         struct drm_display_mode *mode;
11486         struct intel_crtc_state *pipe_config;
11487         int htot = I915_READ(HTOTAL(cpu_transcoder));
11488         int hsync = I915_READ(HSYNC(cpu_transcoder));
11489         int vtot = I915_READ(VTOTAL(cpu_transcoder));
11490         int vsync = I915_READ(VSYNC(cpu_transcoder));
11491         enum pipe pipe = intel_crtc->pipe;
11492
11493         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11494         if (!mode)
11495                 return NULL;
11496
11497         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11498         if (!pipe_config) {
11499                 kfree(mode);
11500                 return NULL;
11501         }
11502
11503         /*
11504          * Construct a pipe_config sufficient for getting the clock info
11505          * back out of crtc_clock_get.
11506          *
11507          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11508          * to use a real value here instead.
11509          */
11510         pipe_config->cpu_transcoder = (enum transcoder) pipe;
11511         pipe_config->pixel_multiplier = 1;
11512         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11513         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11514         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11515         i9xx_crtc_clock_get(intel_crtc, pipe_config);
11516
11517         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11518         mode->hdisplay = (htot & 0xffff) + 1;
11519         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11520         mode->hsync_start = (hsync & 0xffff) + 1;
11521         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11522         mode->vdisplay = (vtot & 0xffff) + 1;
11523         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11524         mode->vsync_start = (vsync & 0xffff) + 1;
11525         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11526
11527         drm_mode_set_name(mode);
11528
11529         kfree(pipe_config);
11530
11531         return mode;
11532 }
11533
11534 static void intel_crtc_destroy(struct drm_crtc *crtc)
11535 {
11536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11537         struct drm_device *dev = crtc->dev;
11538         struct intel_flip_work *work;
11539
11540         spin_lock_irq(&dev->event_lock);
11541         work = intel_crtc->flip_work;
11542         intel_crtc->flip_work = NULL;
11543         spin_unlock_irq(&dev->event_lock);
11544
11545         if (work) {
11546                 cancel_work_sync(&work->mmio_work);
11547                 cancel_work_sync(&work->unpin_work);
11548                 kfree(work);
11549         }
11550
11551         drm_crtc_cleanup(crtc);
11552
11553         kfree(intel_crtc);
11554 }
11555
11556 static void intel_unpin_work_fn(struct work_struct *__work)
11557 {
11558         struct intel_flip_work *work =
11559                 container_of(__work, struct intel_flip_work, unpin_work);
11560         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11561         struct drm_device *dev = crtc->base.dev;
11562         struct drm_plane *primary = crtc->base.primary;
11563
11564         if (is_mmio_work(work))
11565                 flush_work(&work->mmio_work);
11566
11567         mutex_lock(&dev->struct_mutex);
11568         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11569         i915_gem_object_put(work->pending_flip_obj);
11570         mutex_unlock(&dev->struct_mutex);
11571
11572         i915_gem_request_put(work->flip_queued_req);
11573
11574         intel_frontbuffer_flip_complete(to_i915(dev),
11575                                         to_intel_plane(primary)->frontbuffer_bit);
11576         intel_fbc_post_update(crtc);
11577         drm_framebuffer_unreference(work->old_fb);
11578
11579         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11580         atomic_dec(&crtc->unpin_work_count);
11581
11582         kfree(work);
11583 }
11584
11585 /* Is 'a' after or equal to 'b'? */
11586 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11587 {
11588         return !((a - b) & 0x80000000);
11589 }
11590
11591 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11592                                    struct intel_flip_work *work)
11593 {
11594         struct drm_device *dev = crtc->base.dev;
11595         struct drm_i915_private *dev_priv = to_i915(dev);
11596
11597         if (abort_flip_on_reset(crtc))
11598                 return true;
11599
11600         /*
11601          * The relevant registers doen't exist on pre-ctg.
11602          * As the flip done interrupt doesn't trigger for mmio
11603          * flips on gmch platforms, a flip count check isn't
11604          * really needed there. But since ctg has the registers,
11605          * include it in the check anyway.
11606          */
11607         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11608                 return true;
11609
11610         /*
11611          * BDW signals flip done immediately if the plane
11612          * is disabled, even if the plane enable is already
11613          * armed to occur at the next vblank :(
11614          */
11615
11616         /*
11617          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11618          * used the same base address. In that case the mmio flip might
11619          * have completed, but the CS hasn't even executed the flip yet.
11620          *
11621          * A flip count check isn't enough as the CS might have updated
11622          * the base address just after start of vblank, but before we
11623          * managed to process the interrupt. This means we'd complete the
11624          * CS flip too soon.
11625          *
11626          * Combining both checks should get us a good enough result. It may
11627          * still happen that the CS flip has been executed, but has not
11628          * yet actually completed. But in case the base address is the same
11629          * anyway, we don't really care.
11630          */
11631         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11632                 crtc->flip_work->gtt_offset &&
11633                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11634                                     crtc->flip_work->flip_count);
11635 }
11636
11637 static bool
11638 __pageflip_finished_mmio(struct intel_crtc *crtc,
11639                                struct intel_flip_work *work)
11640 {
11641         /*
11642          * MMIO work completes when vblank is different from
11643          * flip_queued_vblank.
11644          *
11645          * Reset counter value doesn't matter, this is handled by
11646          * i915_wait_request finishing early, so no need to handle
11647          * reset here.
11648          */
11649         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11650 }
11651
11652
11653 static bool pageflip_finished(struct intel_crtc *crtc,
11654                               struct intel_flip_work *work)
11655 {
11656         if (!atomic_read(&work->pending))
11657                 return false;
11658
11659         smp_rmb();
11660
11661         if (is_mmio_work(work))
11662                 return __pageflip_finished_mmio(crtc, work);
11663         else
11664                 return __pageflip_finished_cs(crtc, work);
11665 }
11666
11667 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11668 {
11669         struct drm_device *dev = &dev_priv->drm;
11670         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11671         struct intel_flip_work *work;
11672         unsigned long flags;
11673
11674         /* Ignore early vblank irqs */
11675         if (!crtc)
11676                 return;
11677
11678         /*
11679          * This is called both by irq handlers and the reset code (to complete
11680          * lost pageflips) so needs the full irqsave spinlocks.
11681          */
11682         spin_lock_irqsave(&dev->event_lock, flags);
11683         work = crtc->flip_work;
11684
11685         if (work != NULL &&
11686             !is_mmio_work(work) &&
11687             pageflip_finished(crtc, work))
11688                 page_flip_completed(crtc);
11689
11690         spin_unlock_irqrestore(&dev->event_lock, flags);
11691 }
11692
11693 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11694 {
11695         struct drm_device *dev = &dev_priv->drm;
11696         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11697         struct intel_flip_work *work;
11698         unsigned long flags;
11699
11700         /* Ignore early vblank irqs */
11701         if (!crtc)
11702                 return;
11703
11704         /*
11705          * This is called both by irq handlers and the reset code (to complete
11706          * lost pageflips) so needs the full irqsave spinlocks.
11707          */
11708         spin_lock_irqsave(&dev->event_lock, flags);
11709         work = crtc->flip_work;
11710
11711         if (work != NULL &&
11712             is_mmio_work(work) &&
11713             pageflip_finished(crtc, work))
11714                 page_flip_completed(crtc);
11715
11716         spin_unlock_irqrestore(&dev->event_lock, flags);
11717 }
11718
11719 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11720                                                struct intel_flip_work *work)
11721 {
11722         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11723
11724         /* Ensure that the work item is consistent when activating it ... */
11725         smp_mb__before_atomic();
11726         atomic_set(&work->pending, 1);
11727 }
11728
11729 static int intel_gen2_queue_flip(struct drm_device *dev,
11730                                  struct drm_crtc *crtc,
11731                                  struct drm_framebuffer *fb,
11732                                  struct drm_i915_gem_object *obj,
11733                                  struct drm_i915_gem_request *req,
11734                                  uint32_t flags)
11735 {
11736         struct intel_ring *ring = req->ring;
11737         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11738         u32 flip_mask;
11739         int ret;
11740
11741         ret = intel_ring_begin(req, 6);
11742         if (ret)
11743                 return ret;
11744
11745         /* Can't queue multiple flips, so wait for the previous
11746          * one to finish before executing the next.
11747          */
11748         if (intel_crtc->plane)
11749                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11750         else
11751                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11752         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11753         intel_ring_emit(ring, MI_NOOP);
11754         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11755                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11756         intel_ring_emit(ring, fb->pitches[0]);
11757         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11758         intel_ring_emit(ring, 0); /* aux display base address, unused */
11759
11760         return 0;
11761 }
11762
11763 static int intel_gen3_queue_flip(struct drm_device *dev,
11764                                  struct drm_crtc *crtc,
11765                                  struct drm_framebuffer *fb,
11766                                  struct drm_i915_gem_object *obj,
11767                                  struct drm_i915_gem_request *req,
11768                                  uint32_t flags)
11769 {
11770         struct intel_ring *ring = req->ring;
11771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11772         u32 flip_mask;
11773         int ret;
11774
11775         ret = intel_ring_begin(req, 6);
11776         if (ret)
11777                 return ret;
11778
11779         if (intel_crtc->plane)
11780                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11781         else
11782                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11783         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11784         intel_ring_emit(ring, MI_NOOP);
11785         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11786                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11787         intel_ring_emit(ring, fb->pitches[0]);
11788         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11789         intel_ring_emit(ring, MI_NOOP);
11790
11791         return 0;
11792 }
11793
11794 static int intel_gen4_queue_flip(struct drm_device *dev,
11795                                  struct drm_crtc *crtc,
11796                                  struct drm_framebuffer *fb,
11797                                  struct drm_i915_gem_object *obj,
11798                                  struct drm_i915_gem_request *req,
11799                                  uint32_t flags)
11800 {
11801         struct intel_ring *ring = req->ring;
11802         struct drm_i915_private *dev_priv = to_i915(dev);
11803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11804         uint32_t pf, pipesrc;
11805         int ret;
11806
11807         ret = intel_ring_begin(req, 4);
11808         if (ret)
11809                 return ret;
11810
11811         /* i965+ uses the linear or tiled offsets from the
11812          * Display Registers (which do not change across a page-flip)
11813          * so we need only reprogram the base address.
11814          */
11815         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11816                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11817         intel_ring_emit(ring, fb->pitches[0]);
11818         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11819                         intel_fb_modifier_to_tiling(fb->modifier));
11820
11821         /* XXX Enabling the panel-fitter across page-flip is so far
11822          * untested on non-native modes, so ignore it for now.
11823          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11824          */
11825         pf = 0;
11826         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11827         intel_ring_emit(ring, pf | pipesrc);
11828
11829         return 0;
11830 }
11831
11832 static int intel_gen6_queue_flip(struct drm_device *dev,
11833                                  struct drm_crtc *crtc,
11834                                  struct drm_framebuffer *fb,
11835                                  struct drm_i915_gem_object *obj,
11836                                  struct drm_i915_gem_request *req,
11837                                  uint32_t flags)
11838 {
11839         struct intel_ring *ring = req->ring;
11840         struct drm_i915_private *dev_priv = to_i915(dev);
11841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11842         uint32_t pf, pipesrc;
11843         int ret;
11844
11845         ret = intel_ring_begin(req, 4);
11846         if (ret)
11847                 return ret;
11848
11849         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11850                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11851         intel_ring_emit(ring, fb->pitches[0] |
11852                         intel_fb_modifier_to_tiling(fb->modifier));
11853         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11854
11855         /* Contrary to the suggestions in the documentation,
11856          * "Enable Panel Fitter" does not seem to be required when page
11857          * flipping with a non-native mode, and worse causes a normal
11858          * modeset to fail.
11859          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11860          */
11861         pf = 0;
11862         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11863         intel_ring_emit(ring, pf | pipesrc);
11864
11865         return 0;
11866 }
11867
11868 static int intel_gen7_queue_flip(struct drm_device *dev,
11869                                  struct drm_crtc *crtc,
11870                                  struct drm_framebuffer *fb,
11871                                  struct drm_i915_gem_object *obj,
11872                                  struct drm_i915_gem_request *req,
11873                                  uint32_t flags)
11874 {
11875         struct drm_i915_private *dev_priv = to_i915(dev);
11876         struct intel_ring *ring = req->ring;
11877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11878         uint32_t plane_bit = 0;
11879         int len, ret;
11880
11881         switch (intel_crtc->plane) {
11882         case PLANE_A:
11883                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11884                 break;
11885         case PLANE_B:
11886                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11887                 break;
11888         case PLANE_C:
11889                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11890                 break;
11891         default:
11892                 WARN_ONCE(1, "unknown plane in flip command\n");
11893                 return -ENODEV;
11894         }
11895
11896         len = 4;
11897         if (req->engine->id == RCS) {
11898                 len += 6;
11899                 /*
11900                  * On Gen 8, SRM is now taking an extra dword to accommodate
11901                  * 48bits addresses, and we need a NOOP for the batch size to
11902                  * stay even.
11903                  */
11904                 if (IS_GEN8(dev_priv))
11905                         len += 2;
11906         }
11907
11908         /*
11909          * BSpec MI_DISPLAY_FLIP for IVB:
11910          * "The full packet must be contained within the same cache line."
11911          *
11912          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11913          * cacheline, if we ever start emitting more commands before
11914          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11915          * then do the cacheline alignment, and finally emit the
11916          * MI_DISPLAY_FLIP.
11917          */
11918         ret = intel_ring_cacheline_align(req);
11919         if (ret)
11920                 return ret;
11921
11922         ret = intel_ring_begin(req, len);
11923         if (ret)
11924                 return ret;
11925
11926         /* Unmask the flip-done completion message. Note that the bspec says that
11927          * we should do this for both the BCS and RCS, and that we must not unmask
11928          * more than one flip event at any time (or ensure that one flip message
11929          * can be sent by waiting for flip-done prior to queueing new flips).
11930          * Experimentation says that BCS works despite DERRMR masking all
11931          * flip-done completion events and that unmasking all planes at once
11932          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11933          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11934          */
11935         if (req->engine->id == RCS) {
11936                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11937                 intel_ring_emit_reg(ring, DERRMR);
11938                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11939                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11940                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11941                 if (IS_GEN8(dev_priv))
11942                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11943                                               MI_SRM_LRM_GLOBAL_GTT);
11944                 else
11945                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11946                                               MI_SRM_LRM_GLOBAL_GTT);
11947                 intel_ring_emit_reg(ring, DERRMR);
11948                 intel_ring_emit(ring,
11949                                 i915_ggtt_offset(req->engine->scratch) + 256);
11950                 if (IS_GEN8(dev_priv)) {
11951                         intel_ring_emit(ring, 0);
11952                         intel_ring_emit(ring, MI_NOOP);
11953                 }
11954         }
11955
11956         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11957         intel_ring_emit(ring, fb->pitches[0] |
11958                         intel_fb_modifier_to_tiling(fb->modifier));
11959         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11960         intel_ring_emit(ring, (MI_NOOP));
11961
11962         return 0;
11963 }
11964
11965 static bool use_mmio_flip(struct intel_engine_cs *engine,
11966                           struct drm_i915_gem_object *obj)
11967 {
11968         /*
11969          * This is not being used for older platforms, because
11970          * non-availability of flip done interrupt forces us to use
11971          * CS flips. Older platforms derive flip done using some clever
11972          * tricks involving the flip_pending status bits and vblank irqs.
11973          * So using MMIO flips there would disrupt this mechanism.
11974          */
11975
11976         if (engine == NULL)
11977                 return true;
11978
11979         if (INTEL_GEN(engine->i915) < 5)
11980                 return false;
11981
11982         if (i915.use_mmio_flip < 0)
11983                 return false;
11984         else if (i915.use_mmio_flip > 0)
11985                 return true;
11986         else if (i915.enable_execlists)
11987                 return true;
11988
11989         return engine != i915_gem_object_last_write_engine(obj);
11990 }
11991
11992 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11993                              unsigned int rotation,
11994                              struct intel_flip_work *work)
11995 {
11996         struct drm_device *dev = intel_crtc->base.dev;
11997         struct drm_i915_private *dev_priv = to_i915(dev);
11998         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11999         const enum pipe pipe = intel_crtc->pipe;
12000         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
12001
12002         ctl = I915_READ(PLANE_CTL(pipe, 0));
12003         ctl &= ~PLANE_CTL_TILED_MASK;
12004         switch (fb->modifier) {
12005         case DRM_FORMAT_MOD_NONE:
12006                 break;
12007         case I915_FORMAT_MOD_X_TILED:
12008                 ctl |= PLANE_CTL_TILED_X;
12009                 break;
12010         case I915_FORMAT_MOD_Y_TILED:
12011                 ctl |= PLANE_CTL_TILED_Y;
12012                 break;
12013         case I915_FORMAT_MOD_Yf_TILED:
12014                 ctl |= PLANE_CTL_TILED_YF;
12015                 break;
12016         default:
12017                 MISSING_CASE(fb->modifier);
12018         }
12019
12020         /*
12021          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
12022          * PLANE_SURF updates, the update is then guaranteed to be atomic.
12023          */
12024         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
12025         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
12026
12027         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
12028         POSTING_READ(PLANE_SURF(pipe, 0));
12029 }
12030
12031 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
12032                              struct intel_flip_work *work)
12033 {
12034         struct drm_device *dev = intel_crtc->base.dev;
12035         struct drm_i915_private *dev_priv = to_i915(dev);
12036         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12037         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12038         u32 dspcntr;
12039
12040         dspcntr = I915_READ(reg);
12041
12042         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
12043                 dspcntr |= DISPPLANE_TILED;
12044         else
12045                 dspcntr &= ~DISPPLANE_TILED;
12046
12047         I915_WRITE(reg, dspcntr);
12048
12049         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12050         POSTING_READ(DSPSURF(intel_crtc->plane));
12051 }
12052
12053 static void intel_mmio_flip_work_func(struct work_struct *w)
12054 {
12055         struct intel_flip_work *work =
12056                 container_of(w, struct intel_flip_work, mmio_work);
12057         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12058         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12059         struct intel_framebuffer *intel_fb =
12060                 to_intel_framebuffer(crtc->base.primary->fb);
12061         struct drm_i915_gem_object *obj = intel_fb->obj;
12062
12063         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
12064
12065         intel_pipe_update_start(crtc);
12066
12067         if (INTEL_GEN(dev_priv) >= 9)
12068                 skl_do_mmio_flip(crtc, work->rotation, work);
12069         else
12070                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12071                 ilk_do_mmio_flip(crtc, work);
12072
12073         intel_pipe_update_end(crtc, work);
12074 }
12075
12076 static int intel_default_queue_flip(struct drm_device *dev,
12077                                     struct drm_crtc *crtc,
12078                                     struct drm_framebuffer *fb,
12079                                     struct drm_i915_gem_object *obj,
12080                                     struct drm_i915_gem_request *req,
12081                                     uint32_t flags)
12082 {
12083         return -ENODEV;
12084 }
12085
12086 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12087                                       struct intel_crtc *intel_crtc,
12088                                       struct intel_flip_work *work)
12089 {
12090         u32 addr, vblank;
12091
12092         if (!atomic_read(&work->pending))
12093                 return false;
12094
12095         smp_rmb();
12096
12097         vblank = intel_crtc_get_vblank_counter(intel_crtc);
12098         if (work->flip_ready_vblank == 0) {
12099                 if (work->flip_queued_req &&
12100                     !i915_gem_request_completed(work->flip_queued_req))
12101                         return false;
12102
12103                 work->flip_ready_vblank = vblank;
12104         }
12105
12106         if (vblank - work->flip_ready_vblank < 3)
12107                 return false;
12108
12109         /* Potential stall - if we see that the flip has happened,
12110          * assume a missed interrupt. */
12111         if (INTEL_GEN(dev_priv) >= 4)
12112                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12113         else
12114                 addr = I915_READ(DSPADDR(intel_crtc->plane));
12115
12116         /* There is a potential issue here with a false positive after a flip
12117          * to the same address. We could address this by checking for a
12118          * non-incrementing frame counter.
12119          */
12120         return addr == work->gtt_offset;
12121 }
12122
12123 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12124 {
12125         struct drm_device *dev = &dev_priv->drm;
12126         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12127         struct intel_flip_work *work;
12128
12129         WARN_ON(!in_interrupt());
12130
12131         if (crtc == NULL)
12132                 return;
12133
12134         spin_lock(&dev->event_lock);
12135         work = crtc->flip_work;
12136
12137         if (work != NULL && !is_mmio_work(work) &&
12138             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
12139                 WARN_ONCE(1,
12140                           "Kicking stuck page flip: queued at %d, now %d\n",
12141                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
12142                 page_flip_completed(crtc);
12143                 work = NULL;
12144         }
12145
12146         if (work != NULL && !is_mmio_work(work) &&
12147             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
12148                 intel_queue_rps_boost_for_request(work->flip_queued_req);
12149         spin_unlock(&dev->event_lock);
12150 }
12151
12152 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12153                                 struct drm_framebuffer *fb,
12154                                 struct drm_pending_vblank_event *event,
12155                                 uint32_t page_flip_flags)
12156 {
12157         struct drm_device *dev = crtc->dev;
12158         struct drm_i915_private *dev_priv = to_i915(dev);
12159         struct drm_framebuffer *old_fb = crtc->primary->fb;
12160         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12162         struct drm_plane *primary = crtc->primary;
12163         enum pipe pipe = intel_crtc->pipe;
12164         struct intel_flip_work *work;
12165         struct intel_engine_cs *engine;
12166         bool mmio_flip;
12167         struct drm_i915_gem_request *request;
12168         struct i915_vma *vma;
12169         int ret;
12170
12171         /*
12172          * drm_mode_page_flip_ioctl() should already catch this, but double
12173          * check to be safe.  In the future we may enable pageflipping from
12174          * a disabled primary plane.
12175          */
12176         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12177                 return -EBUSY;
12178
12179         /* Can't change pixel format via MI display flips. */
12180         if (fb->pixel_format != crtc->primary->fb->pixel_format)
12181                 return -EINVAL;
12182
12183         /*
12184          * TILEOFF/LINOFF registers can't be changed via MI display flips.
12185          * Note that pitch changes could also affect these register.
12186          */
12187         if (INTEL_GEN(dev_priv) > 3 &&
12188             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12189              fb->pitches[0] != crtc->primary->fb->pitches[0]))
12190                 return -EINVAL;
12191
12192         if (i915_terminally_wedged(&dev_priv->gpu_error))
12193                 goto out_hang;
12194
12195         work = kzalloc(sizeof(*work), GFP_KERNEL);
12196         if (work == NULL)
12197                 return -ENOMEM;
12198
12199         work->event = event;
12200         work->crtc = crtc;
12201         work->old_fb = old_fb;
12202         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12203
12204         ret = drm_crtc_vblank_get(crtc);
12205         if (ret)
12206                 goto free_work;
12207
12208         /* We borrow the event spin lock for protecting flip_work */
12209         spin_lock_irq(&dev->event_lock);
12210         if (intel_crtc->flip_work) {
12211                 /* Before declaring the flip queue wedged, check if
12212                  * the hardware completed the operation behind our backs.
12213                  */
12214                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12215                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12216                         page_flip_completed(intel_crtc);
12217                 } else {
12218                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12219                         spin_unlock_irq(&dev->event_lock);
12220
12221                         drm_crtc_vblank_put(crtc);
12222                         kfree(work);
12223                         return -EBUSY;
12224                 }
12225         }
12226         intel_crtc->flip_work = work;
12227         spin_unlock_irq(&dev->event_lock);
12228
12229         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12230                 flush_workqueue(dev_priv->wq);
12231
12232         /* Reference the objects for the scheduled work. */
12233         drm_framebuffer_reference(work->old_fb);
12234
12235         crtc->primary->fb = fb;
12236         update_state_fb(crtc->primary);
12237
12238         work->pending_flip_obj = i915_gem_object_get(obj);
12239
12240         ret = i915_mutex_lock_interruptible(dev);
12241         if (ret)
12242                 goto cleanup;
12243
12244         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12245         if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12246                 ret = -EIO;
12247                 goto unlock;
12248         }
12249
12250         atomic_inc(&intel_crtc->unpin_work_count);
12251
12252         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12253                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12254
12255         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
12256                 engine = dev_priv->engine[BCS];
12257                 if (fb->modifier != old_fb->modifier)
12258                         /* vlv: DISPLAY_FLIP fails to change tiling */
12259                         engine = NULL;
12260         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
12261                 engine = dev_priv->engine[BCS];
12262         } else if (INTEL_GEN(dev_priv) >= 7) {
12263                 engine = i915_gem_object_last_write_engine(obj);
12264                 if (engine == NULL || engine->id != RCS)
12265                         engine = dev_priv->engine[BCS];
12266         } else {
12267                 engine = dev_priv->engine[RCS];
12268         }
12269
12270         mmio_flip = use_mmio_flip(engine, obj);
12271
12272         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12273         if (IS_ERR(vma)) {
12274                 ret = PTR_ERR(vma);
12275                 goto cleanup_pending;
12276         }
12277
12278         work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12279         work->gtt_offset += intel_crtc->dspaddr_offset;
12280         work->rotation = crtc->primary->state->rotation;
12281
12282         /*
12283          * There's the potential that the next frame will not be compatible with
12284          * FBC, so we want to call pre_update() before the actual page flip.
12285          * The problem is that pre_update() caches some information about the fb
12286          * object, so we want to do this only after the object is pinned. Let's
12287          * be on the safe side and do this immediately before scheduling the
12288          * flip.
12289          */
12290         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12291                              to_intel_plane_state(primary->state));
12292
12293         if (mmio_flip) {
12294                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12295                 queue_work(system_unbound_wq, &work->mmio_work);
12296         } else {
12297                 request = i915_gem_request_alloc(engine,
12298                                                  dev_priv->kernel_context);
12299                 if (IS_ERR(request)) {
12300                         ret = PTR_ERR(request);
12301                         goto cleanup_unpin;
12302                 }
12303
12304                 ret = i915_gem_request_await_object(request, obj, false);
12305                 if (ret)
12306                         goto cleanup_request;
12307
12308                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12309                                                    page_flip_flags);
12310                 if (ret)
12311                         goto cleanup_request;
12312
12313                 intel_mark_page_flip_active(intel_crtc, work);
12314
12315                 work->flip_queued_req = i915_gem_request_get(request);
12316                 i915_add_request_no_flush(request);
12317         }
12318
12319         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12320         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12321                           to_intel_plane(primary)->frontbuffer_bit);
12322         mutex_unlock(&dev->struct_mutex);
12323
12324         intel_frontbuffer_flip_prepare(to_i915(dev),
12325                                        to_intel_plane(primary)->frontbuffer_bit);
12326
12327         trace_i915_flip_request(intel_crtc->plane, obj);
12328
12329         return 0;
12330
12331 cleanup_request:
12332         i915_add_request_no_flush(request);
12333 cleanup_unpin:
12334         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12335 cleanup_pending:
12336         atomic_dec(&intel_crtc->unpin_work_count);
12337 unlock:
12338         mutex_unlock(&dev->struct_mutex);
12339 cleanup:
12340         crtc->primary->fb = old_fb;
12341         update_state_fb(crtc->primary);
12342
12343         i915_gem_object_put(obj);
12344         drm_framebuffer_unreference(work->old_fb);
12345
12346         spin_lock_irq(&dev->event_lock);
12347         intel_crtc->flip_work = NULL;
12348         spin_unlock_irq(&dev->event_lock);
12349
12350         drm_crtc_vblank_put(crtc);
12351 free_work:
12352         kfree(work);
12353
12354         if (ret == -EIO) {
12355                 struct drm_atomic_state *state;
12356                 struct drm_plane_state *plane_state;
12357
12358 out_hang:
12359                 state = drm_atomic_state_alloc(dev);
12360                 if (!state)
12361                         return -ENOMEM;
12362                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12363
12364 retry:
12365                 plane_state = drm_atomic_get_plane_state(state, primary);
12366                 ret = PTR_ERR_OR_ZERO(plane_state);
12367                 if (!ret) {
12368                         drm_atomic_set_fb_for_plane(plane_state, fb);
12369
12370                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12371                         if (!ret)
12372                                 ret = drm_atomic_commit(state);
12373                 }
12374
12375                 if (ret == -EDEADLK) {
12376                         drm_modeset_backoff(state->acquire_ctx);
12377                         drm_atomic_state_clear(state);
12378                         goto retry;
12379                 }
12380
12381                 drm_atomic_state_put(state);
12382
12383                 if (ret == 0 && event) {
12384                         spin_lock_irq(&dev->event_lock);
12385                         drm_crtc_send_vblank_event(crtc, event);
12386                         spin_unlock_irq(&dev->event_lock);
12387                 }
12388         }
12389         return ret;
12390 }
12391
12392
12393 /**
12394  * intel_wm_need_update - Check whether watermarks need updating
12395  * @plane: drm plane
12396  * @state: new plane state
12397  *
12398  * Check current plane state versus the new one to determine whether
12399  * watermarks need to be recalculated.
12400  *
12401  * Returns true or false.
12402  */
12403 static bool intel_wm_need_update(struct drm_plane *plane,
12404                                  struct drm_plane_state *state)
12405 {
12406         struct intel_plane_state *new = to_intel_plane_state(state);
12407         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12408
12409         /* Update watermarks on tiling or size changes. */
12410         if (new->base.visible != cur->base.visible)
12411                 return true;
12412
12413         if (!cur->base.fb || !new->base.fb)
12414                 return false;
12415
12416         if (cur->base.fb->modifier != new->base.fb->modifier ||
12417             cur->base.rotation != new->base.rotation ||
12418             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12419             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12420             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12421             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12422                 return true;
12423
12424         return false;
12425 }
12426
12427 static bool needs_scaling(struct intel_plane_state *state)
12428 {
12429         int src_w = drm_rect_width(&state->base.src) >> 16;
12430         int src_h = drm_rect_height(&state->base.src) >> 16;
12431         int dst_w = drm_rect_width(&state->base.dst);
12432         int dst_h = drm_rect_height(&state->base.dst);
12433
12434         return (src_w != dst_w || src_h != dst_h);
12435 }
12436
12437 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12438                                     struct drm_plane_state *plane_state)
12439 {
12440         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12441         struct drm_crtc *crtc = crtc_state->crtc;
12442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12443         struct drm_plane *plane = plane_state->plane;
12444         struct drm_device *dev = crtc->dev;
12445         struct drm_i915_private *dev_priv = to_i915(dev);
12446         struct intel_plane_state *old_plane_state =
12447                 to_intel_plane_state(plane->state);
12448         bool mode_changed = needs_modeset(crtc_state);
12449         bool was_crtc_enabled = crtc->state->active;
12450         bool is_crtc_enabled = crtc_state->active;
12451         bool turn_off, turn_on, visible, was_visible;
12452         struct drm_framebuffer *fb = plane_state->fb;
12453         int ret;
12454
12455         if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12456                 ret = skl_update_scaler_plane(
12457                         to_intel_crtc_state(crtc_state),
12458                         to_intel_plane_state(plane_state));
12459                 if (ret)
12460                         return ret;
12461         }
12462
12463         was_visible = old_plane_state->base.visible;
12464         visible = to_intel_plane_state(plane_state)->base.visible;
12465
12466         if (!was_crtc_enabled && WARN_ON(was_visible))
12467                 was_visible = false;
12468
12469         /*
12470          * Visibility is calculated as if the crtc was on, but
12471          * after scaler setup everything depends on it being off
12472          * when the crtc isn't active.
12473          *
12474          * FIXME this is wrong for watermarks. Watermarks should also
12475          * be computed as if the pipe would be active. Perhaps move
12476          * per-plane wm computation to the .check_plane() hook, and
12477          * only combine the results from all planes in the current place?
12478          */
12479         if (!is_crtc_enabled)
12480                 to_intel_plane_state(plane_state)->base.visible = visible = false;
12481
12482         if (!was_visible && !visible)
12483                 return 0;
12484
12485         if (fb != old_plane_state->base.fb)
12486                 pipe_config->fb_changed = true;
12487
12488         turn_off = was_visible && (!visible || mode_changed);
12489         turn_on = visible && (!was_visible || mode_changed);
12490
12491         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12492                          intel_crtc->base.base.id,
12493                          intel_crtc->base.name,
12494                          plane->base.id, plane->name,
12495                          fb ? fb->base.id : -1);
12496
12497         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12498                          plane->base.id, plane->name,
12499                          was_visible, visible,
12500                          turn_off, turn_on, mode_changed);
12501
12502         if (turn_on) {
12503                 pipe_config->update_wm_pre = true;
12504
12505                 /* must disable cxsr around plane enable/disable */
12506                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12507                         pipe_config->disable_cxsr = true;
12508         } else if (turn_off) {
12509                 pipe_config->update_wm_post = true;
12510
12511                 /* must disable cxsr around plane enable/disable */
12512                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12513                         pipe_config->disable_cxsr = true;
12514         } else if (intel_wm_need_update(plane, plane_state)) {
12515                 /* FIXME bollocks */
12516                 pipe_config->update_wm_pre = true;
12517                 pipe_config->update_wm_post = true;
12518         }
12519
12520         /* Pre-gen9 platforms need two-step watermark updates */
12521         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12522             INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks)
12523                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12524
12525         if (visible || was_visible)
12526                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12527
12528         /*
12529          * WaCxSRDisabledForSpriteScaling:ivb
12530          *
12531          * cstate->update_wm was already set above, so this flag will
12532          * take effect when we commit and program watermarks.
12533          */
12534         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
12535             needs_scaling(to_intel_plane_state(plane_state)) &&
12536             !needs_scaling(old_plane_state))
12537                 pipe_config->disable_lp_wm = true;
12538
12539         return 0;
12540 }
12541
12542 static bool encoders_cloneable(const struct intel_encoder *a,
12543                                const struct intel_encoder *b)
12544 {
12545         /* masks could be asymmetric, so check both ways */
12546         return a == b || (a->cloneable & (1 << b->type) &&
12547                           b->cloneable & (1 << a->type));
12548 }
12549
12550 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12551                                          struct intel_crtc *crtc,
12552                                          struct intel_encoder *encoder)
12553 {
12554         struct intel_encoder *source_encoder;
12555         struct drm_connector *connector;
12556         struct drm_connector_state *connector_state;
12557         int i;
12558
12559         for_each_connector_in_state(state, connector, connector_state, i) {
12560                 if (connector_state->crtc != &crtc->base)
12561                         continue;
12562
12563                 source_encoder =
12564                         to_intel_encoder(connector_state->best_encoder);
12565                 if (!encoders_cloneable(encoder, source_encoder))
12566                         return false;
12567         }
12568
12569         return true;
12570 }
12571
12572 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12573                                    struct drm_crtc_state *crtc_state)
12574 {
12575         struct drm_device *dev = crtc->dev;
12576         struct drm_i915_private *dev_priv = to_i915(dev);
12577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12578         struct intel_crtc_state *pipe_config =
12579                 to_intel_crtc_state(crtc_state);
12580         struct drm_atomic_state *state = crtc_state->state;
12581         int ret;
12582         bool mode_changed = needs_modeset(crtc_state);
12583
12584         if (mode_changed && !crtc_state->active)
12585                 pipe_config->update_wm_post = true;
12586
12587         if (mode_changed && crtc_state->enable &&
12588             dev_priv->display.crtc_compute_clock &&
12589             !WARN_ON(pipe_config->shared_dpll)) {
12590                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12591                                                            pipe_config);
12592                 if (ret)
12593                         return ret;
12594         }
12595
12596         if (crtc_state->color_mgmt_changed) {
12597                 ret = intel_color_check(crtc, crtc_state);
12598                 if (ret)
12599                         return ret;
12600
12601                 /*
12602                  * Changing color management on Intel hardware is
12603                  * handled as part of planes update.
12604                  */
12605                 crtc_state->planes_changed = true;
12606         }
12607
12608         ret = 0;
12609         if (dev_priv->display.compute_pipe_wm) {
12610                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12611                 if (ret) {
12612                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12613                         return ret;
12614                 }
12615         }
12616
12617         if (dev_priv->display.compute_intermediate_wm &&
12618             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12619                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12620                         return 0;
12621
12622                 /*
12623                  * Calculate 'intermediate' watermarks that satisfy both the
12624                  * old state and the new state.  We can program these
12625                  * immediately.
12626                  */
12627                 ret = dev_priv->display.compute_intermediate_wm(dev,
12628                                                                 intel_crtc,
12629                                                                 pipe_config);
12630                 if (ret) {
12631                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12632                         return ret;
12633                 }
12634         } else if (dev_priv->display.compute_intermediate_wm) {
12635                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12636                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12637         }
12638
12639         if (INTEL_GEN(dev_priv) >= 9) {
12640                 if (mode_changed)
12641                         ret = skl_update_scaler_crtc(pipe_config);
12642
12643                 if (!ret)
12644                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12645                                                          pipe_config);
12646         }
12647
12648         return ret;
12649 }
12650
12651 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12652         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12653         .atomic_begin = intel_begin_crtc_commit,
12654         .atomic_flush = intel_finish_crtc_commit,
12655         .atomic_check = intel_crtc_atomic_check,
12656 };
12657
12658 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12659 {
12660         struct intel_connector *connector;
12661
12662         for_each_intel_connector(dev, connector) {
12663                 if (connector->base.state->crtc)
12664                         drm_connector_unreference(&connector->base);
12665
12666                 if (connector->base.encoder) {
12667                         connector->base.state->best_encoder =
12668                                 connector->base.encoder;
12669                         connector->base.state->crtc =
12670                                 connector->base.encoder->crtc;
12671
12672                         drm_connector_reference(&connector->base);
12673                 } else {
12674                         connector->base.state->best_encoder = NULL;
12675                         connector->base.state->crtc = NULL;
12676                 }
12677         }
12678 }
12679
12680 static void
12681 connected_sink_compute_bpp(struct intel_connector *connector,
12682                            struct intel_crtc_state *pipe_config)
12683 {
12684         const struct drm_display_info *info = &connector->base.display_info;
12685         int bpp = pipe_config->pipe_bpp;
12686
12687         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12688                       connector->base.base.id,
12689                       connector->base.name);
12690
12691         /* Don't use an invalid EDID bpc value */
12692         if (info->bpc != 0 && info->bpc * 3 < bpp) {
12693                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12694                               bpp, info->bpc * 3);
12695                 pipe_config->pipe_bpp = info->bpc * 3;
12696         }
12697
12698         /* Clamp bpp to 8 on screens without EDID 1.4 */
12699         if (info->bpc == 0 && bpp > 24) {
12700                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12701                               bpp);
12702                 pipe_config->pipe_bpp = 24;
12703         }
12704 }
12705
12706 static int
12707 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12708                           struct intel_crtc_state *pipe_config)
12709 {
12710         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12711         struct drm_atomic_state *state;
12712         struct drm_connector *connector;
12713         struct drm_connector_state *connector_state;
12714         int bpp, i;
12715
12716         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12717             IS_CHERRYVIEW(dev_priv)))
12718                 bpp = 10*3;
12719         else if (INTEL_GEN(dev_priv) >= 5)
12720                 bpp = 12*3;
12721         else
12722                 bpp = 8*3;
12723
12724
12725         pipe_config->pipe_bpp = bpp;
12726
12727         state = pipe_config->base.state;
12728
12729         /* Clamp display bpp to EDID value */
12730         for_each_connector_in_state(state, connector, connector_state, i) {
12731                 if (connector_state->crtc != &crtc->base)
12732                         continue;
12733
12734                 connected_sink_compute_bpp(to_intel_connector(connector),
12735                                            pipe_config);
12736         }
12737
12738         return bpp;
12739 }
12740
12741 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12742 {
12743         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12744                         "type: 0x%x flags: 0x%x\n",
12745                 mode->crtc_clock,
12746                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12747                 mode->crtc_hsync_end, mode->crtc_htotal,
12748                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12749                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12750 }
12751
12752 static inline void
12753 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
12754                       unsigned int lane_count, struct intel_link_m_n *m_n)
12755 {
12756         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12757                       id, lane_count,
12758                       m_n->gmch_m, m_n->gmch_n,
12759                       m_n->link_m, m_n->link_n, m_n->tu);
12760 }
12761
12762 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12763                                    struct intel_crtc_state *pipe_config,
12764                                    const char *context)
12765 {
12766         struct drm_device *dev = crtc->base.dev;
12767         struct drm_i915_private *dev_priv = to_i915(dev);
12768         struct drm_plane *plane;
12769         struct intel_plane *intel_plane;
12770         struct intel_plane_state *state;
12771         struct drm_framebuffer *fb;
12772
12773         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
12774                       crtc->base.base.id, crtc->base.name, context);
12775
12776         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12777                       transcoder_name(pipe_config->cpu_transcoder),
12778                       pipe_config->pipe_bpp, pipe_config->dither);
12779
12780         if (pipe_config->has_pch_encoder)
12781                 intel_dump_m_n_config(pipe_config, "fdi",
12782                                       pipe_config->fdi_lanes,
12783                                       &pipe_config->fdi_m_n);
12784
12785         if (intel_crtc_has_dp_encoder(pipe_config)) {
12786                 intel_dump_m_n_config(pipe_config, "dp m_n",
12787                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12788                 if (pipe_config->has_drrs)
12789                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12790                                               pipe_config->lane_count,
12791                                               &pipe_config->dp_m2_n2);
12792         }
12793
12794         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12795                       pipe_config->has_audio, pipe_config->has_infoframe);
12796
12797         DRM_DEBUG_KMS("requested mode:\n");
12798         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12799         DRM_DEBUG_KMS("adjusted mode:\n");
12800         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12801         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12802         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n",
12803                       pipe_config->port_clock,
12804                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12805
12806         if (INTEL_GEN(dev_priv) >= 9)
12807                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12808                               crtc->num_scalers,
12809                               pipe_config->scaler_state.scaler_users,
12810                               pipe_config->scaler_state.scaler_id);
12811
12812         if (HAS_GMCH_DISPLAY(dev_priv))
12813                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12814                               pipe_config->gmch_pfit.control,
12815                               pipe_config->gmch_pfit.pgm_ratios,
12816                               pipe_config->gmch_pfit.lvds_border_bits);
12817         else
12818                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12819                               pipe_config->pch_pfit.pos,
12820                               pipe_config->pch_pfit.size,
12821                               enableddisabled(pipe_config->pch_pfit.enabled));
12822
12823         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12824                       pipe_config->ips_enabled, pipe_config->double_wide);
12825
12826         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
12827
12828         DRM_DEBUG_KMS("planes on this crtc\n");
12829         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12830                 struct drm_format_name_buf format_name;
12831                 intel_plane = to_intel_plane(plane);
12832                 if (intel_plane->pipe != crtc->pipe)
12833                         continue;
12834
12835                 state = to_intel_plane_state(plane->state);
12836                 fb = state->base.fb;
12837                 if (!fb) {
12838                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12839                                       plane->base.id, plane->name, state->scaler_id);
12840                         continue;
12841                 }
12842
12843                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
12844                               plane->base.id, plane->name,
12845                               fb->base.id, fb->width, fb->height,
12846                               drm_get_format_name(fb->pixel_format, &format_name));
12847                 if (INTEL_GEN(dev_priv) >= 9)
12848                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12849                                       state->scaler_id,
12850                                       state->base.src.x1 >> 16,
12851                                       state->base.src.y1 >> 16,
12852                                       drm_rect_width(&state->base.src) >> 16,
12853                                       drm_rect_height(&state->base.src) >> 16,
12854                                       state->base.dst.x1, state->base.dst.y1,
12855                                       drm_rect_width(&state->base.dst),
12856                                       drm_rect_height(&state->base.dst));
12857         }
12858 }
12859
12860 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12861 {
12862         struct drm_device *dev = state->dev;
12863         struct drm_connector *connector;
12864         unsigned int used_ports = 0;
12865         unsigned int used_mst_ports = 0;
12866
12867         /*
12868          * Walk the connector list instead of the encoder
12869          * list to detect the problem on ddi platforms
12870          * where there's just one encoder per digital port.
12871          */
12872         drm_for_each_connector(connector, dev) {
12873                 struct drm_connector_state *connector_state;
12874                 struct intel_encoder *encoder;
12875
12876                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12877                 if (!connector_state)
12878                         connector_state = connector->state;
12879
12880                 if (!connector_state->best_encoder)
12881                         continue;
12882
12883                 encoder = to_intel_encoder(connector_state->best_encoder);
12884
12885                 WARN_ON(!connector_state->crtc);
12886
12887                 switch (encoder->type) {
12888                         unsigned int port_mask;
12889                 case INTEL_OUTPUT_UNKNOWN:
12890                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12891                                 break;
12892                 case INTEL_OUTPUT_DP:
12893                 case INTEL_OUTPUT_HDMI:
12894                 case INTEL_OUTPUT_EDP:
12895                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12896
12897                         /* the same port mustn't appear more than once */
12898                         if (used_ports & port_mask)
12899                                 return false;
12900
12901                         used_ports |= port_mask;
12902                         break;
12903                 case INTEL_OUTPUT_DP_MST:
12904                         used_mst_ports |=
12905                                 1 << enc_to_mst(&encoder->base)->primary->port;
12906                         break;
12907                 default:
12908                         break;
12909                 }
12910         }
12911
12912         /* can't mix MST and SST/HDMI on the same port */
12913         if (used_ports & used_mst_ports)
12914                 return false;
12915
12916         return true;
12917 }
12918
12919 static void
12920 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12921 {
12922         struct drm_crtc_state tmp_state;
12923         struct intel_crtc_scaler_state scaler_state;
12924         struct intel_dpll_hw_state dpll_hw_state;
12925         struct intel_shared_dpll *shared_dpll;
12926         bool force_thru;
12927
12928         /* FIXME: before the switch to atomic started, a new pipe_config was
12929          * kzalloc'd. Code that depends on any field being zero should be
12930          * fixed, so that the crtc_state can be safely duplicated. For now,
12931          * only fields that are know to not cause problems are preserved. */
12932
12933         tmp_state = crtc_state->base;
12934         scaler_state = crtc_state->scaler_state;
12935         shared_dpll = crtc_state->shared_dpll;
12936         dpll_hw_state = crtc_state->dpll_hw_state;
12937         force_thru = crtc_state->pch_pfit.force_thru;
12938
12939         memset(crtc_state, 0, sizeof *crtc_state);
12940
12941         crtc_state->base = tmp_state;
12942         crtc_state->scaler_state = scaler_state;
12943         crtc_state->shared_dpll = shared_dpll;
12944         crtc_state->dpll_hw_state = dpll_hw_state;
12945         crtc_state->pch_pfit.force_thru = force_thru;
12946 }
12947
12948 static int
12949 intel_modeset_pipe_config(struct drm_crtc *crtc,
12950                           struct intel_crtc_state *pipe_config)
12951 {
12952         struct drm_atomic_state *state = pipe_config->base.state;
12953         struct intel_encoder *encoder;
12954         struct drm_connector *connector;
12955         struct drm_connector_state *connector_state;
12956         int base_bpp, ret = -EINVAL;
12957         int i;
12958         bool retry = true;
12959
12960         clear_intel_crtc_state(pipe_config);
12961
12962         pipe_config->cpu_transcoder =
12963                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12964
12965         /*
12966          * Sanitize sync polarity flags based on requested ones. If neither
12967          * positive or negative polarity is requested, treat this as meaning
12968          * negative polarity.
12969          */
12970         if (!(pipe_config->base.adjusted_mode.flags &
12971               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12972                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12973
12974         if (!(pipe_config->base.adjusted_mode.flags &
12975               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12976                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12977
12978         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12979                                              pipe_config);
12980         if (base_bpp < 0)
12981                 goto fail;
12982
12983         /*
12984          * Determine the real pipe dimensions. Note that stereo modes can
12985          * increase the actual pipe size due to the frame doubling and
12986          * insertion of additional space for blanks between the frame. This
12987          * is stored in the crtc timings. We use the requested mode to do this
12988          * computation to clearly distinguish it from the adjusted mode, which
12989          * can be changed by the connectors in the below retry loop.
12990          */
12991         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12992                                &pipe_config->pipe_src_w,
12993                                &pipe_config->pipe_src_h);
12994
12995         for_each_connector_in_state(state, connector, connector_state, i) {
12996                 if (connector_state->crtc != crtc)
12997                         continue;
12998
12999                 encoder = to_intel_encoder(connector_state->best_encoder);
13000
13001                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13002                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13003                         goto fail;
13004                 }
13005
13006                 /*
13007                  * Determine output_types before calling the .compute_config()
13008                  * hooks so that the hooks can use this information safely.
13009                  */
13010                 pipe_config->output_types |= 1 << encoder->type;
13011         }
13012
13013 encoder_retry:
13014         /* Ensure the port clock defaults are reset when retrying. */
13015         pipe_config->port_clock = 0;
13016         pipe_config->pixel_multiplier = 1;
13017
13018         /* Fill in default crtc timings, allow encoders to overwrite them. */
13019         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13020                               CRTC_STEREO_DOUBLE);
13021
13022         /* Pass our mode to the connectors and the CRTC to give them a chance to
13023          * adjust it according to limitations or connector properties, and also
13024          * a chance to reject the mode entirely.
13025          */
13026         for_each_connector_in_state(state, connector, connector_state, i) {
13027                 if (connector_state->crtc != crtc)
13028                         continue;
13029
13030                 encoder = to_intel_encoder(connector_state->best_encoder);
13031
13032                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13033                         DRM_DEBUG_KMS("Encoder config failure\n");
13034                         goto fail;
13035                 }
13036         }
13037
13038         /* Set default port clock if not overwritten by the encoder. Needs to be
13039          * done afterwards in case the encoder adjusts the mode. */
13040         if (!pipe_config->port_clock)
13041                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13042                         * pipe_config->pixel_multiplier;
13043
13044         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13045         if (ret < 0) {
13046                 DRM_DEBUG_KMS("CRTC fixup failed\n");
13047                 goto fail;
13048         }
13049
13050         if (ret == RETRY) {
13051                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13052                         ret = -EINVAL;
13053                         goto fail;
13054                 }
13055
13056                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13057                 retry = false;
13058                 goto encoder_retry;
13059         }
13060
13061         /* Dithering seems to not pass-through bits correctly when it should, so
13062          * only enable it on 6bpc panels. */
13063         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13064         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13065                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13066
13067 fail:
13068         return ret;
13069 }
13070
13071 static void
13072 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13073 {
13074         struct drm_crtc *crtc;
13075         struct drm_crtc_state *crtc_state;
13076         int i;
13077
13078         /* Double check state. */
13079         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13080                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13081
13082                 /* Update hwmode for vblank functions */
13083                 if (crtc->state->active)
13084                         crtc->hwmode = crtc->state->adjusted_mode;
13085                 else
13086                         crtc->hwmode.crtc_clock = 0;
13087
13088                 /*
13089                  * Update legacy state to satisfy fbc code. This can
13090                  * be removed when fbc uses the atomic state.
13091                  */
13092                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13093                         struct drm_plane_state *plane_state = crtc->primary->state;
13094
13095                         crtc->primary->fb = plane_state->fb;
13096                         crtc->x = plane_state->src_x >> 16;
13097                         crtc->y = plane_state->src_y >> 16;
13098                 }
13099         }
13100 }
13101
13102 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13103 {
13104         int diff;
13105
13106         if (clock1 == clock2)
13107                 return true;
13108
13109         if (!clock1 || !clock2)
13110                 return false;
13111
13112         diff = abs(clock1 - clock2);
13113
13114         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13115                 return true;
13116
13117         return false;
13118 }
13119
13120 static bool
13121 intel_compare_m_n(unsigned int m, unsigned int n,
13122                   unsigned int m2, unsigned int n2,
13123                   bool exact)
13124 {
13125         if (m == m2 && n == n2)
13126                 return true;
13127
13128         if (exact || !m || !n || !m2 || !n2)
13129                 return false;
13130
13131         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13132
13133         if (n > n2) {
13134                 while (n > n2) {
13135                         m2 <<= 1;
13136                         n2 <<= 1;
13137                 }
13138         } else if (n < n2) {
13139                 while (n < n2) {
13140                         m <<= 1;
13141                         n <<= 1;
13142                 }
13143         }
13144
13145         if (n != n2)
13146                 return false;
13147
13148         return intel_fuzzy_clock_check(m, m2);
13149 }
13150
13151 static bool
13152 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13153                        struct intel_link_m_n *m2_n2,
13154                        bool adjust)
13155 {
13156         if (m_n->tu == m2_n2->tu &&
13157             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13158                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13159             intel_compare_m_n(m_n->link_m, m_n->link_n,
13160                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
13161                 if (adjust)
13162                         *m2_n2 = *m_n;
13163
13164                 return true;
13165         }
13166
13167         return false;
13168 }
13169
13170 static void __printf(3, 4)
13171 pipe_config_err(bool adjust, const char *name, const char *format, ...)
13172 {
13173         char *level;
13174         unsigned int category;
13175         struct va_format vaf;
13176         va_list args;
13177
13178         if (adjust) {
13179                 level = KERN_DEBUG;
13180                 category = DRM_UT_KMS;
13181         } else {
13182                 level = KERN_ERR;
13183                 category = DRM_UT_NONE;
13184         }
13185
13186         va_start(args, format);
13187         vaf.fmt = format;
13188         vaf.va = &args;
13189
13190         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
13191
13192         va_end(args);
13193 }
13194
13195 static bool
13196 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
13197                           struct intel_crtc_state *current_config,
13198                           struct intel_crtc_state *pipe_config,
13199                           bool adjust)
13200 {
13201         bool ret = true;
13202
13203 #define PIPE_CONF_CHECK_X(name) \
13204         if (current_config->name != pipe_config->name) { \
13205                 pipe_config_err(adjust, __stringify(name), \
13206                           "(expected 0x%08x, found 0x%08x)\n", \
13207                           current_config->name, \
13208                           pipe_config->name); \
13209                 ret = false; \
13210         }
13211
13212 #define PIPE_CONF_CHECK_I(name) \
13213         if (current_config->name != pipe_config->name) { \
13214                 pipe_config_err(adjust, __stringify(name), \
13215                           "(expected %i, found %i)\n", \
13216                           current_config->name, \
13217                           pipe_config->name); \
13218                 ret = false; \
13219         }
13220
13221 #define PIPE_CONF_CHECK_P(name) \
13222         if (current_config->name != pipe_config->name) { \
13223                 pipe_config_err(adjust, __stringify(name), \
13224                           "(expected %p, found %p)\n", \
13225                           current_config->name, \
13226                           pipe_config->name); \
13227                 ret = false; \
13228         }
13229
13230 #define PIPE_CONF_CHECK_M_N(name) \
13231         if (!intel_compare_link_m_n(&current_config->name, \
13232                                     &pipe_config->name,\
13233                                     adjust)) { \
13234                 pipe_config_err(adjust, __stringify(name), \
13235                           "(expected tu %i gmch %i/%i link %i/%i, " \
13236                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13237                           current_config->name.tu, \
13238                           current_config->name.gmch_m, \
13239                           current_config->name.gmch_n, \
13240                           current_config->name.link_m, \
13241                           current_config->name.link_n, \
13242                           pipe_config->name.tu, \
13243                           pipe_config->name.gmch_m, \
13244                           pipe_config->name.gmch_n, \
13245                           pipe_config->name.link_m, \
13246                           pipe_config->name.link_n); \
13247                 ret = false; \
13248         }
13249
13250 /* This is required for BDW+ where there is only one set of registers for
13251  * switching between high and low RR.
13252  * This macro can be used whenever a comparison has to be made between one
13253  * hw state and multiple sw state variables.
13254  */
13255 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13256         if (!intel_compare_link_m_n(&current_config->name, \
13257                                     &pipe_config->name, adjust) && \
13258             !intel_compare_link_m_n(&current_config->alt_name, \
13259                                     &pipe_config->name, adjust)) { \
13260                 pipe_config_err(adjust, __stringify(name), \
13261                           "(expected tu %i gmch %i/%i link %i/%i, " \
13262                           "or tu %i gmch %i/%i link %i/%i, " \
13263                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13264                           current_config->name.tu, \
13265                           current_config->name.gmch_m, \
13266                           current_config->name.gmch_n, \
13267                           current_config->name.link_m, \
13268                           current_config->name.link_n, \
13269                           current_config->alt_name.tu, \
13270                           current_config->alt_name.gmch_m, \
13271                           current_config->alt_name.gmch_n, \
13272                           current_config->alt_name.link_m, \
13273                           current_config->alt_name.link_n, \
13274                           pipe_config->name.tu, \
13275                           pipe_config->name.gmch_m, \
13276                           pipe_config->name.gmch_n, \
13277                           pipe_config->name.link_m, \
13278                           pipe_config->name.link_n); \
13279                 ret = false; \
13280         }
13281
13282 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
13283         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13284                 pipe_config_err(adjust, __stringify(name), \
13285                           "(%x) (expected %i, found %i)\n", \
13286                           (mask), \
13287                           current_config->name & (mask), \
13288                           pipe_config->name & (mask)); \
13289                 ret = false; \
13290         }
13291
13292 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13293         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13294                 pipe_config_err(adjust, __stringify(name), \
13295                           "(expected %i, found %i)\n", \
13296                           current_config->name, \
13297                           pipe_config->name); \
13298                 ret = false; \
13299         }
13300
13301 #define PIPE_CONF_QUIRK(quirk)  \
13302         ((current_config->quirks | pipe_config->quirks) & (quirk))
13303
13304         PIPE_CONF_CHECK_I(cpu_transcoder);
13305
13306         PIPE_CONF_CHECK_I(has_pch_encoder);
13307         PIPE_CONF_CHECK_I(fdi_lanes);
13308         PIPE_CONF_CHECK_M_N(fdi_m_n);
13309
13310         PIPE_CONF_CHECK_I(lane_count);
13311         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13312
13313         if (INTEL_GEN(dev_priv) < 8) {
13314                 PIPE_CONF_CHECK_M_N(dp_m_n);
13315
13316                 if (current_config->has_drrs)
13317                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13318         } else
13319                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13320
13321         PIPE_CONF_CHECK_X(output_types);
13322
13323         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13324         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13325         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13326         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13327         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13328         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13329
13330         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13331         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13332         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13333         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13334         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13335         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13336
13337         PIPE_CONF_CHECK_I(pixel_multiplier);
13338         PIPE_CONF_CHECK_I(has_hdmi_sink);
13339         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13340             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13341                 PIPE_CONF_CHECK_I(limited_color_range);
13342         PIPE_CONF_CHECK_I(has_infoframe);
13343
13344         PIPE_CONF_CHECK_I(has_audio);
13345
13346         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13347                               DRM_MODE_FLAG_INTERLACE);
13348
13349         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13350                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13351                                       DRM_MODE_FLAG_PHSYNC);
13352                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13353                                       DRM_MODE_FLAG_NHSYNC);
13354                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13355                                       DRM_MODE_FLAG_PVSYNC);
13356                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13357                                       DRM_MODE_FLAG_NVSYNC);
13358         }
13359
13360         PIPE_CONF_CHECK_X(gmch_pfit.control);
13361         /* pfit ratios are autocomputed by the hw on gen4+ */
13362         if (INTEL_GEN(dev_priv) < 4)
13363                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13364         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13365
13366         if (!adjust) {
13367                 PIPE_CONF_CHECK_I(pipe_src_w);
13368                 PIPE_CONF_CHECK_I(pipe_src_h);
13369
13370                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13371                 if (current_config->pch_pfit.enabled) {
13372                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13373                         PIPE_CONF_CHECK_X(pch_pfit.size);
13374                 }
13375
13376                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13377         }
13378
13379         /* BDW+ don't expose a synchronous way to read the state */
13380         if (IS_HASWELL(dev_priv))
13381                 PIPE_CONF_CHECK_I(ips_enabled);
13382
13383         PIPE_CONF_CHECK_I(double_wide);
13384
13385         PIPE_CONF_CHECK_P(shared_dpll);
13386         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13387         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13388         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13389         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13390         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13391         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13392         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13393         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13394         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13395
13396         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13397         PIPE_CONF_CHECK_X(dsi_pll.div);
13398
13399         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13400                 PIPE_CONF_CHECK_I(pipe_bpp);
13401
13402         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13403         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13404
13405 #undef PIPE_CONF_CHECK_X
13406 #undef PIPE_CONF_CHECK_I
13407 #undef PIPE_CONF_CHECK_P
13408 #undef PIPE_CONF_CHECK_FLAGS
13409 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13410 #undef PIPE_CONF_QUIRK
13411
13412         return ret;
13413 }
13414
13415 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13416                                            const struct intel_crtc_state *pipe_config)
13417 {
13418         if (pipe_config->has_pch_encoder) {
13419                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13420                                                             &pipe_config->fdi_m_n);
13421                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13422
13423                 /*
13424                  * FDI already provided one idea for the dotclock.
13425                  * Yell if the encoder disagrees.
13426                  */
13427                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13428                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13429                      fdi_dotclock, dotclock);
13430         }
13431 }
13432
13433 static void verify_wm_state(struct drm_crtc *crtc,
13434                             struct drm_crtc_state *new_state)
13435 {
13436         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13437         struct skl_ddb_allocation hw_ddb, *sw_ddb;
13438         struct skl_pipe_wm hw_wm, *sw_wm;
13439         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13440         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13442         const enum pipe pipe = intel_crtc->pipe;
13443         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13444
13445         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
13446                 return;
13447
13448         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
13449         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
13450
13451         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13452         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13453
13454         /* planes */
13455         for_each_universal_plane(dev_priv, pipe, plane) {
13456                 hw_plane_wm = &hw_wm.planes[plane];
13457                 sw_plane_wm = &sw_wm->planes[plane];
13458
13459                 /* Watermarks */
13460                 for (level = 0; level <= max_level; level++) {
13461                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13462                                                 &sw_plane_wm->wm[level]))
13463                                 continue;
13464
13465                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13466                                   pipe_name(pipe), plane + 1, level,
13467                                   sw_plane_wm->wm[level].plane_en,
13468                                   sw_plane_wm->wm[level].plane_res_b,
13469                                   sw_plane_wm->wm[level].plane_res_l,
13470                                   hw_plane_wm->wm[level].plane_en,
13471                                   hw_plane_wm->wm[level].plane_res_b,
13472                                   hw_plane_wm->wm[level].plane_res_l);
13473                 }
13474
13475                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13476                                          &sw_plane_wm->trans_wm)) {
13477                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13478                                   pipe_name(pipe), plane + 1,
13479                                   sw_plane_wm->trans_wm.plane_en,
13480                                   sw_plane_wm->trans_wm.plane_res_b,
13481                                   sw_plane_wm->trans_wm.plane_res_l,
13482                                   hw_plane_wm->trans_wm.plane_en,
13483                                   hw_plane_wm->trans_wm.plane_res_b,
13484                                   hw_plane_wm->trans_wm.plane_res_l);
13485                 }
13486
13487                 /* DDB */
13488                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
13489                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
13490
13491                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13492                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13493                                   pipe_name(pipe), plane + 1,
13494                                   sw_ddb_entry->start, sw_ddb_entry->end,
13495                                   hw_ddb_entry->start, hw_ddb_entry->end);
13496                 }
13497         }
13498
13499         /*
13500          * cursor
13501          * If the cursor plane isn't active, we may not have updated it's ddb
13502          * allocation. In that case since the ddb allocation will be updated
13503          * once the plane becomes visible, we can skip this check
13504          */
13505         if (intel_crtc->cursor_addr) {
13506                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
13507                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13508
13509                 /* Watermarks */
13510                 for (level = 0; level <= max_level; level++) {
13511                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13512                                                 &sw_plane_wm->wm[level]))
13513                                 continue;
13514
13515                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13516                                   pipe_name(pipe), level,
13517                                   sw_plane_wm->wm[level].plane_en,
13518                                   sw_plane_wm->wm[level].plane_res_b,
13519                                   sw_plane_wm->wm[level].plane_res_l,
13520                                   hw_plane_wm->wm[level].plane_en,
13521                                   hw_plane_wm->wm[level].plane_res_b,
13522                                   hw_plane_wm->wm[level].plane_res_l);
13523                 }
13524
13525                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13526                                          &sw_plane_wm->trans_wm)) {
13527                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13528                                   pipe_name(pipe),
13529                                   sw_plane_wm->trans_wm.plane_en,
13530                                   sw_plane_wm->trans_wm.plane_res_b,
13531                                   sw_plane_wm->trans_wm.plane_res_l,
13532                                   hw_plane_wm->trans_wm.plane_en,
13533                                   hw_plane_wm->trans_wm.plane_res_b,
13534                                   hw_plane_wm->trans_wm.plane_res_l);
13535                 }
13536
13537                 /* DDB */
13538                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13539                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13540
13541                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13542                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13543                                   pipe_name(pipe),
13544                                   sw_ddb_entry->start, sw_ddb_entry->end,
13545                                   hw_ddb_entry->start, hw_ddb_entry->end);
13546                 }
13547         }
13548 }
13549
13550 static void
13551 verify_connector_state(struct drm_device *dev,
13552                        struct drm_atomic_state *state,
13553                        struct drm_crtc *crtc)
13554 {
13555         struct drm_connector *connector;
13556         struct drm_connector_state *old_conn_state;
13557         int i;
13558
13559         for_each_connector_in_state(state, connector, old_conn_state, i) {
13560                 struct drm_encoder *encoder = connector->encoder;
13561                 struct drm_connector_state *state = connector->state;
13562
13563                 if (state->crtc != crtc)
13564                         continue;
13565
13566                 intel_connector_verify_state(to_intel_connector(connector));
13567
13568                 I915_STATE_WARN(state->best_encoder != encoder,
13569                      "connector's atomic encoder doesn't match legacy encoder\n");
13570         }
13571 }
13572
13573 static void
13574 verify_encoder_state(struct drm_device *dev)
13575 {
13576         struct intel_encoder *encoder;
13577         struct intel_connector *connector;
13578
13579         for_each_intel_encoder(dev, encoder) {
13580                 bool enabled = false;
13581                 enum pipe pipe;
13582
13583                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13584                               encoder->base.base.id,
13585                               encoder->base.name);
13586
13587                 for_each_intel_connector(dev, connector) {
13588                         if (connector->base.state->best_encoder != &encoder->base)
13589                                 continue;
13590                         enabled = true;
13591
13592                         I915_STATE_WARN(connector->base.state->crtc !=
13593                                         encoder->base.crtc,
13594                              "connector's crtc doesn't match encoder crtc\n");
13595                 }
13596
13597                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13598                      "encoder's enabled state mismatch "
13599                      "(expected %i, found %i)\n",
13600                      !!encoder->base.crtc, enabled);
13601
13602                 if (!encoder->base.crtc) {
13603                         bool active;
13604
13605                         active = encoder->get_hw_state(encoder, &pipe);
13606                         I915_STATE_WARN(active,
13607                              "encoder detached but still enabled on pipe %c.\n",
13608                              pipe_name(pipe));
13609                 }
13610         }
13611 }
13612
13613 static void
13614 verify_crtc_state(struct drm_crtc *crtc,
13615                   struct drm_crtc_state *old_crtc_state,
13616                   struct drm_crtc_state *new_crtc_state)
13617 {
13618         struct drm_device *dev = crtc->dev;
13619         struct drm_i915_private *dev_priv = to_i915(dev);
13620         struct intel_encoder *encoder;
13621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13622         struct intel_crtc_state *pipe_config, *sw_config;
13623         struct drm_atomic_state *old_state;
13624         bool active;
13625
13626         old_state = old_crtc_state->state;
13627         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13628         pipe_config = to_intel_crtc_state(old_crtc_state);
13629         memset(pipe_config, 0, sizeof(*pipe_config));
13630         pipe_config->base.crtc = crtc;
13631         pipe_config->base.state = old_state;
13632
13633         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13634
13635         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13636
13637         /* hw state is inconsistent with the pipe quirk */
13638         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13639             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13640                 active = new_crtc_state->active;
13641
13642         I915_STATE_WARN(new_crtc_state->active != active,
13643              "crtc active state doesn't match with hw state "
13644              "(expected %i, found %i)\n", new_crtc_state->active, active);
13645
13646         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13647              "transitional active state does not match atomic hw state "
13648              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13649
13650         for_each_encoder_on_crtc(dev, crtc, encoder) {
13651                 enum pipe pipe;
13652
13653                 active = encoder->get_hw_state(encoder, &pipe);
13654                 I915_STATE_WARN(active != new_crtc_state->active,
13655                         "[ENCODER:%i] active %i with crtc active %i\n",
13656                         encoder->base.base.id, active, new_crtc_state->active);
13657
13658                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13659                                 "Encoder connected to wrong pipe %c\n",
13660                                 pipe_name(pipe));
13661
13662                 if (active) {
13663                         pipe_config->output_types |= 1 << encoder->type;
13664                         encoder->get_config(encoder, pipe_config);
13665                 }
13666         }
13667
13668         if (!new_crtc_state->active)
13669                 return;
13670
13671         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13672
13673         sw_config = to_intel_crtc_state(crtc->state);
13674         if (!intel_pipe_config_compare(dev_priv, sw_config,
13675                                        pipe_config, false)) {
13676                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13677                 intel_dump_pipe_config(intel_crtc, pipe_config,
13678                                        "[hw state]");
13679                 intel_dump_pipe_config(intel_crtc, sw_config,
13680                                        "[sw state]");
13681         }
13682 }
13683
13684 static void
13685 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13686                          struct intel_shared_dpll *pll,
13687                          struct drm_crtc *crtc,
13688                          struct drm_crtc_state *new_state)
13689 {
13690         struct intel_dpll_hw_state dpll_hw_state;
13691         unsigned crtc_mask;
13692         bool active;
13693
13694         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13695
13696         DRM_DEBUG_KMS("%s\n", pll->name);
13697
13698         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13699
13700         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13701                 I915_STATE_WARN(!pll->on && pll->active_mask,
13702                      "pll in active use but not on in sw tracking\n");
13703                 I915_STATE_WARN(pll->on && !pll->active_mask,
13704                      "pll is on but not used by any active crtc\n");
13705                 I915_STATE_WARN(pll->on != active,
13706                      "pll on state mismatch (expected %i, found %i)\n",
13707                      pll->on, active);
13708         }
13709
13710         if (!crtc) {
13711                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
13712                                 "more active pll users than references: %x vs %x\n",
13713                                 pll->active_mask, pll->state.crtc_mask);
13714
13715                 return;
13716         }
13717
13718         crtc_mask = 1 << drm_crtc_index(crtc);
13719
13720         if (new_state->active)
13721                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13722                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13723                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13724         else
13725                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13726                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13727                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13728
13729         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
13730                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13731                         crtc_mask, pll->state.crtc_mask);
13732
13733         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
13734                                           &dpll_hw_state,
13735                                           sizeof(dpll_hw_state)),
13736                         "pll hw state mismatch\n");
13737 }
13738
13739 static void
13740 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13741                          struct drm_crtc_state *old_crtc_state,
13742                          struct drm_crtc_state *new_crtc_state)
13743 {
13744         struct drm_i915_private *dev_priv = to_i915(dev);
13745         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13746         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13747
13748         if (new_state->shared_dpll)
13749                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13750
13751         if (old_state->shared_dpll &&
13752             old_state->shared_dpll != new_state->shared_dpll) {
13753                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13754                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13755
13756                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13757                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13758                                 pipe_name(drm_crtc_index(crtc)));
13759                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
13760                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13761                                 pipe_name(drm_crtc_index(crtc)));
13762         }
13763 }
13764
13765 static void
13766 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13767                           struct drm_atomic_state *state,
13768                           struct drm_crtc_state *old_state,
13769                           struct drm_crtc_state *new_state)
13770 {
13771         if (!needs_modeset(new_state) &&
13772             !to_intel_crtc_state(new_state)->update_pipe)
13773                 return;
13774
13775         verify_wm_state(crtc, new_state);
13776         verify_connector_state(crtc->dev, state, crtc);
13777         verify_crtc_state(crtc, old_state, new_state);
13778         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13779 }
13780
13781 static void
13782 verify_disabled_dpll_state(struct drm_device *dev)
13783 {
13784         struct drm_i915_private *dev_priv = to_i915(dev);
13785         int i;
13786
13787         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13788                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13789 }
13790
13791 static void
13792 intel_modeset_verify_disabled(struct drm_device *dev,
13793                               struct drm_atomic_state *state)
13794 {
13795         verify_encoder_state(dev);
13796         verify_connector_state(dev, state, NULL);
13797         verify_disabled_dpll_state(dev);
13798 }
13799
13800 static void update_scanline_offset(struct intel_crtc *crtc)
13801 {
13802         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13803
13804         /*
13805          * The scanline counter increments at the leading edge of hsync.
13806          *
13807          * On most platforms it starts counting from vtotal-1 on the
13808          * first active line. That means the scanline counter value is
13809          * always one less than what we would expect. Ie. just after
13810          * start of vblank, which also occurs at start of hsync (on the
13811          * last active line), the scanline counter will read vblank_start-1.
13812          *
13813          * On gen2 the scanline counter starts counting from 1 instead
13814          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13815          * to keep the value positive), instead of adding one.
13816          *
13817          * On HSW+ the behaviour of the scanline counter depends on the output
13818          * type. For DP ports it behaves like most other platforms, but on HDMI
13819          * there's an extra 1 line difference. So we need to add two instead of
13820          * one to the value.
13821          */
13822         if (IS_GEN2(dev_priv)) {
13823                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13824                 int vtotal;
13825
13826                 vtotal = adjusted_mode->crtc_vtotal;
13827                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13828                         vtotal /= 2;
13829
13830                 crtc->scanline_offset = vtotal - 1;
13831         } else if (HAS_DDI(dev_priv) &&
13832                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13833                 crtc->scanline_offset = 2;
13834         } else
13835                 crtc->scanline_offset = 1;
13836 }
13837
13838 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13839 {
13840         struct drm_device *dev = state->dev;
13841         struct drm_i915_private *dev_priv = to_i915(dev);
13842         struct drm_crtc *crtc;
13843         struct drm_crtc_state *crtc_state;
13844         int i;
13845
13846         if (!dev_priv->display.crtc_compute_clock)
13847                 return;
13848
13849         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13850                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13851                 struct intel_shared_dpll *old_dpll =
13852                         to_intel_crtc_state(crtc->state)->shared_dpll;
13853
13854                 if (!needs_modeset(crtc_state))
13855                         continue;
13856
13857                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13858
13859                 if (!old_dpll)
13860                         continue;
13861
13862                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
13863         }
13864 }
13865
13866 /*
13867  * This implements the workaround described in the "notes" section of the mode
13868  * set sequence documentation. When going from no pipes or single pipe to
13869  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13870  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13871  */
13872 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13873 {
13874         struct drm_crtc_state *crtc_state;
13875         struct intel_crtc *intel_crtc;
13876         struct drm_crtc *crtc;
13877         struct intel_crtc_state *first_crtc_state = NULL;
13878         struct intel_crtc_state *other_crtc_state = NULL;
13879         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13880         int i;
13881
13882         /* look at all crtc's that are going to be enabled in during modeset */
13883         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13884                 intel_crtc = to_intel_crtc(crtc);
13885
13886                 if (!crtc_state->active || !needs_modeset(crtc_state))
13887                         continue;
13888
13889                 if (first_crtc_state) {
13890                         other_crtc_state = to_intel_crtc_state(crtc_state);
13891                         break;
13892                 } else {
13893                         first_crtc_state = to_intel_crtc_state(crtc_state);
13894                         first_pipe = intel_crtc->pipe;
13895                 }
13896         }
13897
13898         /* No workaround needed? */
13899         if (!first_crtc_state)
13900                 return 0;
13901
13902         /* w/a possibly needed, check how many crtc's are already enabled. */
13903         for_each_intel_crtc(state->dev, intel_crtc) {
13904                 struct intel_crtc_state *pipe_config;
13905
13906                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13907                 if (IS_ERR(pipe_config))
13908                         return PTR_ERR(pipe_config);
13909
13910                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13911
13912                 if (!pipe_config->base.active ||
13913                     needs_modeset(&pipe_config->base))
13914                         continue;
13915
13916                 /* 2 or more enabled crtcs means no need for w/a */
13917                 if (enabled_pipe != INVALID_PIPE)
13918                         return 0;
13919
13920                 enabled_pipe = intel_crtc->pipe;
13921         }
13922
13923         if (enabled_pipe != INVALID_PIPE)
13924                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13925         else if (other_crtc_state)
13926                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13927
13928         return 0;
13929 }
13930
13931 static int intel_lock_all_pipes(struct drm_atomic_state *state)
13932 {
13933         struct drm_crtc *crtc;
13934
13935         /* Add all pipes to the state */
13936         for_each_crtc(state->dev, crtc) {
13937                 struct drm_crtc_state *crtc_state;
13938
13939                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13940                 if (IS_ERR(crtc_state))
13941                         return PTR_ERR(crtc_state);
13942         }
13943
13944         return 0;
13945 }
13946
13947 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13948 {
13949         struct drm_crtc *crtc;
13950
13951         /*
13952          * Add all pipes to the state, and force
13953          * a modeset on all the active ones.
13954          */
13955         for_each_crtc(state->dev, crtc) {
13956                 struct drm_crtc_state *crtc_state;
13957                 int ret;
13958
13959                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13960                 if (IS_ERR(crtc_state))
13961                         return PTR_ERR(crtc_state);
13962
13963                 if (!crtc_state->active || needs_modeset(crtc_state))
13964                         continue;
13965
13966                 crtc_state->mode_changed = true;
13967
13968                 ret = drm_atomic_add_affected_connectors(state, crtc);
13969                 if (ret)
13970                         return ret;
13971
13972                 ret = drm_atomic_add_affected_planes(state, crtc);
13973                 if (ret)
13974                         return ret;
13975         }
13976
13977         return 0;
13978 }
13979
13980 static int intel_modeset_checks(struct drm_atomic_state *state)
13981 {
13982         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13983         struct drm_i915_private *dev_priv = to_i915(state->dev);
13984         struct drm_crtc *crtc;
13985         struct drm_crtc_state *crtc_state;
13986         int ret = 0, i;
13987
13988         if (!check_digital_port_conflicts(state)) {
13989                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13990                 return -EINVAL;
13991         }
13992
13993         intel_state->modeset = true;
13994         intel_state->active_crtcs = dev_priv->active_crtcs;
13995
13996         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13997                 if (crtc_state->active)
13998                         intel_state->active_crtcs |= 1 << i;
13999                 else
14000                         intel_state->active_crtcs &= ~(1 << i);
14001
14002                 if (crtc_state->active != crtc->state->active)
14003                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
14004         }
14005
14006         /*
14007          * See if the config requires any additional preparation, e.g.
14008          * to adjust global state with pipes off.  We need to do this
14009          * here so we can get the modeset_pipe updated config for the new
14010          * mode set on this crtc.  For other crtcs we need to use the
14011          * adjusted_mode bits in the crtc directly.
14012          */
14013         if (dev_priv->display.modeset_calc_cdclk) {
14014                 if (!intel_state->cdclk_pll_vco)
14015                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
14016                 if (!intel_state->cdclk_pll_vco)
14017                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
14018
14019                 ret = dev_priv->display.modeset_calc_cdclk(state);
14020                 if (ret < 0)
14021                         return ret;
14022
14023                 /*
14024                  * Writes to dev_priv->atomic_cdclk_freq must protected by
14025                  * holding all the crtc locks, even if we don't end up
14026                  * touching the hardware
14027                  */
14028                 if (intel_state->cdclk != dev_priv->atomic_cdclk_freq) {
14029                         ret = intel_lock_all_pipes(state);
14030                         if (ret < 0)
14031                                 return ret;
14032                 }
14033
14034                 /* All pipes must be switched off while we change the cdclk. */
14035                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14036                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) {
14037                         ret = intel_modeset_all_pipes(state);
14038                         if (ret < 0)
14039                                 return ret;
14040                 }
14041
14042                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
14043                               intel_state->cdclk, intel_state->dev_cdclk);
14044         } else {
14045                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
14046         }
14047
14048         intel_modeset_clear_plls(state);
14049
14050         if (IS_HASWELL(dev_priv))
14051                 return haswell_mode_set_planes_workaround(state);
14052
14053         return 0;
14054 }
14055
14056 /*
14057  * Handle calculation of various watermark data at the end of the atomic check
14058  * phase.  The code here should be run after the per-crtc and per-plane 'check'
14059  * handlers to ensure that all derived state has been updated.
14060  */
14061 static int calc_watermark_data(struct drm_atomic_state *state)
14062 {
14063         struct drm_device *dev = state->dev;
14064         struct drm_i915_private *dev_priv = to_i915(dev);
14065
14066         /* Is there platform-specific watermark information to calculate? */
14067         if (dev_priv->display.compute_global_watermarks)
14068                 return dev_priv->display.compute_global_watermarks(state);
14069
14070         return 0;
14071 }
14072
14073 /**
14074  * intel_atomic_check - validate state object
14075  * @dev: drm device
14076  * @state: state to validate
14077  */
14078 static int intel_atomic_check(struct drm_device *dev,
14079                               struct drm_atomic_state *state)
14080 {
14081         struct drm_i915_private *dev_priv = to_i915(dev);
14082         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14083         struct drm_crtc *crtc;
14084         struct drm_crtc_state *crtc_state;
14085         int ret, i;
14086         bool any_ms = false;
14087
14088         ret = drm_atomic_helper_check_modeset(dev, state);
14089         if (ret)
14090                 return ret;
14091
14092         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14093                 struct intel_crtc_state *pipe_config =
14094                         to_intel_crtc_state(crtc_state);
14095
14096                 /* Catch I915_MODE_FLAG_INHERITED */
14097                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14098                         crtc_state->mode_changed = true;
14099
14100                 if (!needs_modeset(crtc_state))
14101                         continue;
14102
14103                 if (!crtc_state->enable) {
14104                         any_ms = true;
14105                         continue;
14106                 }
14107
14108                 /* FIXME: For only active_changed we shouldn't need to do any
14109                  * state recomputation at all. */
14110
14111                 ret = drm_atomic_add_affected_connectors(state, crtc);
14112                 if (ret)
14113                         return ret;
14114
14115                 ret = intel_modeset_pipe_config(crtc, pipe_config);
14116                 if (ret) {
14117                         intel_dump_pipe_config(to_intel_crtc(crtc),
14118                                                pipe_config, "[failed]");
14119                         return ret;
14120                 }
14121
14122                 if (i915.fastboot &&
14123                     intel_pipe_config_compare(dev_priv,
14124                                         to_intel_crtc_state(crtc->state),
14125                                         pipe_config, true)) {
14126                         crtc_state->mode_changed = false;
14127                         to_intel_crtc_state(crtc_state)->update_pipe = true;
14128                 }
14129
14130                 if (needs_modeset(crtc_state))
14131                         any_ms = true;
14132
14133                 ret = drm_atomic_add_affected_planes(state, crtc);
14134                 if (ret)
14135                         return ret;
14136
14137                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14138                                        needs_modeset(crtc_state) ?
14139                                        "[modeset]" : "[fastset]");
14140         }
14141
14142         if (any_ms) {
14143                 ret = intel_modeset_checks(state);
14144
14145                 if (ret)
14146                         return ret;
14147         } else {
14148                 intel_state->cdclk = dev_priv->atomic_cdclk_freq;
14149         }
14150
14151         ret = drm_atomic_helper_check_planes(dev, state);
14152         if (ret)
14153                 return ret;
14154
14155         intel_fbc_choose_crtc(dev_priv, state);
14156         return calc_watermark_data(state);
14157 }
14158
14159 static int intel_atomic_prepare_commit(struct drm_device *dev,
14160                                        struct drm_atomic_state *state)
14161 {
14162         struct drm_i915_private *dev_priv = to_i915(dev);
14163         struct drm_crtc_state *crtc_state;
14164         struct drm_crtc *crtc;
14165         int i, ret;
14166
14167         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14168                 if (state->legacy_cursor_update)
14169                         continue;
14170
14171                 ret = intel_crtc_wait_for_pending_flips(crtc);
14172                 if (ret)
14173                         return ret;
14174
14175                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14176                         flush_workqueue(dev_priv->wq);
14177         }
14178
14179         ret = mutex_lock_interruptible(&dev->struct_mutex);
14180         if (ret)
14181                 return ret;
14182
14183         ret = drm_atomic_helper_prepare_planes(dev, state);
14184         mutex_unlock(&dev->struct_mutex);
14185
14186         return ret;
14187 }
14188
14189 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14190 {
14191         struct drm_device *dev = crtc->base.dev;
14192
14193         if (!dev->max_vblank_count)
14194                 return drm_accurate_vblank_count(&crtc->base);
14195
14196         return dev->driver->get_vblank_counter(dev, crtc->pipe);
14197 }
14198
14199 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14200                                           struct drm_i915_private *dev_priv,
14201                                           unsigned crtc_mask)
14202 {
14203         unsigned last_vblank_count[I915_MAX_PIPES];
14204         enum pipe pipe;
14205         int ret;
14206
14207         if (!crtc_mask)
14208                 return;
14209
14210         for_each_pipe(dev_priv, pipe) {
14211                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14212                                                                   pipe);
14213
14214                 if (!((1 << pipe) & crtc_mask))
14215                         continue;
14216
14217                 ret = drm_crtc_vblank_get(&crtc->base);
14218                 if (WARN_ON(ret != 0)) {
14219                         crtc_mask &= ~(1 << pipe);
14220                         continue;
14221                 }
14222
14223                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
14224         }
14225
14226         for_each_pipe(dev_priv, pipe) {
14227                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14228                                                                   pipe);
14229                 long lret;
14230
14231                 if (!((1 << pipe) & crtc_mask))
14232                         continue;
14233
14234                 lret = wait_event_timeout(dev->vblank[pipe].queue,
14235                                 last_vblank_count[pipe] !=
14236                                         drm_crtc_vblank_count(&crtc->base),
14237                                 msecs_to_jiffies(50));
14238
14239                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14240
14241                 drm_crtc_vblank_put(&crtc->base);
14242         }
14243 }
14244
14245 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14246 {
14247         /* fb updated, need to unpin old fb */
14248         if (crtc_state->fb_changed)
14249                 return true;
14250
14251         /* wm changes, need vblank before final wm's */
14252         if (crtc_state->update_wm_post)
14253                 return true;
14254
14255         /*
14256          * cxsr is re-enabled after vblank.
14257          * This is already handled by crtc_state->update_wm_post,
14258          * but added for clarity.
14259          */
14260         if (crtc_state->disable_cxsr)
14261                 return true;
14262
14263         return false;
14264 }
14265
14266 static void intel_update_crtc(struct drm_crtc *crtc,
14267                               struct drm_atomic_state *state,
14268                               struct drm_crtc_state *old_crtc_state,
14269                               unsigned int *crtc_vblank_mask)
14270 {
14271         struct drm_device *dev = crtc->dev;
14272         struct drm_i915_private *dev_priv = to_i915(dev);
14273         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14274         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14275         bool modeset = needs_modeset(crtc->state);
14276
14277         if (modeset) {
14278                 update_scanline_offset(intel_crtc);
14279                 dev_priv->display.crtc_enable(pipe_config, state);
14280         } else {
14281                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14282         }
14283
14284         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14285                 intel_fbc_enable(
14286                     intel_crtc, pipe_config,
14287                     to_intel_plane_state(crtc->primary->state));
14288         }
14289
14290         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14291
14292         if (needs_vblank_wait(pipe_config))
14293                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14294 }
14295
14296 static void intel_update_crtcs(struct drm_atomic_state *state,
14297                                unsigned int *crtc_vblank_mask)
14298 {
14299         struct drm_crtc *crtc;
14300         struct drm_crtc_state *old_crtc_state;
14301         int i;
14302
14303         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14304                 if (!crtc->state->active)
14305                         continue;
14306
14307                 intel_update_crtc(crtc, state, old_crtc_state,
14308                                   crtc_vblank_mask);
14309         }
14310 }
14311
14312 static void skl_update_crtcs(struct drm_atomic_state *state,
14313                              unsigned int *crtc_vblank_mask)
14314 {
14315         struct drm_i915_private *dev_priv = to_i915(state->dev);
14316         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14317         struct drm_crtc *crtc;
14318         struct intel_crtc *intel_crtc;
14319         struct drm_crtc_state *old_crtc_state;
14320         struct intel_crtc_state *cstate;
14321         unsigned int updated = 0;
14322         bool progress;
14323         enum pipe pipe;
14324         int i;
14325
14326         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
14327
14328         for_each_crtc_in_state(state, crtc, old_crtc_state, i)
14329                 /* ignore allocations for crtc's that have been turned off. */
14330                 if (crtc->state->active)
14331                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
14332
14333         /*
14334          * Whenever the number of active pipes changes, we need to make sure we
14335          * update the pipes in the right order so that their ddb allocations
14336          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14337          * cause pipe underruns and other bad stuff.
14338          */
14339         do {
14340                 progress = false;
14341
14342                 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14343                         bool vbl_wait = false;
14344                         unsigned int cmask = drm_crtc_mask(crtc);
14345
14346                         intel_crtc = to_intel_crtc(crtc);
14347                         cstate = to_intel_crtc_state(crtc->state);
14348                         pipe = intel_crtc->pipe;
14349
14350                         if (updated & cmask || !cstate->base.active)
14351                                 continue;
14352
14353                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
14354                                 continue;
14355
14356                         updated |= cmask;
14357                         entries[i] = &cstate->wm.skl.ddb;
14358
14359                         /*
14360                          * If this is an already active pipe, it's DDB changed,
14361                          * and this isn't the last pipe that needs updating
14362                          * then we need to wait for a vblank to pass for the
14363                          * new ddb allocation to take effect.
14364                          */
14365                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
14366                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
14367                             !crtc->state->active_changed &&
14368                             intel_state->wm_results.dirty_pipes != updated)
14369                                 vbl_wait = true;
14370
14371                         intel_update_crtc(crtc, state, old_crtc_state,
14372                                           crtc_vblank_mask);
14373
14374                         if (vbl_wait)
14375                                 intel_wait_for_vblank(dev_priv, pipe);
14376
14377                         progress = true;
14378                 }
14379         } while (progress);
14380 }
14381
14382 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14383 {
14384         struct drm_device *dev = state->dev;
14385         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14386         struct drm_i915_private *dev_priv = to_i915(dev);
14387         struct drm_crtc_state *old_crtc_state;
14388         struct drm_crtc *crtc;
14389         struct intel_crtc_state *intel_cstate;
14390         bool hw_check = intel_state->modeset;
14391         unsigned long put_domains[I915_MAX_PIPES] = {};
14392         unsigned crtc_vblank_mask = 0;
14393         int i;
14394
14395         drm_atomic_helper_wait_for_dependencies(state);
14396
14397         if (intel_state->modeset)
14398                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14399
14400         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14401                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14402
14403                 if (needs_modeset(crtc->state) ||
14404                     to_intel_crtc_state(crtc->state)->update_pipe) {
14405                         hw_check = true;
14406
14407                         put_domains[to_intel_crtc(crtc)->pipe] =
14408                                 modeset_get_crtc_power_domains(crtc,
14409                                         to_intel_crtc_state(crtc->state));
14410                 }
14411
14412                 if (!needs_modeset(crtc->state))
14413                         continue;
14414
14415                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14416
14417                 if (old_crtc_state->active) {
14418                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14419                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14420                         intel_crtc->active = false;
14421                         intel_fbc_disable(intel_crtc);
14422                         intel_disable_shared_dpll(intel_crtc);
14423
14424                         /*
14425                          * Underruns don't always raise
14426                          * interrupts, so check manually.
14427                          */
14428                         intel_check_cpu_fifo_underruns(dev_priv);
14429                         intel_check_pch_fifo_underruns(dev_priv);
14430
14431                         if (!crtc->state->active) {
14432                                 /*
14433                                  * Make sure we don't call initial_watermarks
14434                                  * for ILK-style watermark updates.
14435                                  */
14436                                 if (dev_priv->display.atomic_update_watermarks)
14437                                         dev_priv->display.initial_watermarks(intel_state,
14438                                                                              to_intel_crtc_state(crtc->state));
14439                                 else
14440                                         intel_update_watermarks(intel_crtc);
14441                         }
14442                 }
14443         }
14444
14445         /* Only after disabling all output pipelines that will be changed can we
14446          * update the the output configuration. */
14447         intel_modeset_update_crtc_state(state);
14448
14449         if (intel_state->modeset) {
14450                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14451
14452                 if (dev_priv->display.modeset_commit_cdclk &&
14453                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14454                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14455                         dev_priv->display.modeset_commit_cdclk(state);
14456
14457                 /*
14458                  * SKL workaround: bspec recommends we disable the SAGV when we
14459                  * have more then one pipe enabled
14460                  */
14461                 if (!intel_can_enable_sagv(state))
14462                         intel_disable_sagv(dev_priv);
14463
14464                 intel_modeset_verify_disabled(dev, state);
14465         }
14466
14467         /* Complete the events for pipes that have now been disabled */
14468         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14469                 bool modeset = needs_modeset(crtc->state);
14470
14471                 /* Complete events for now disable pipes here. */
14472                 if (modeset && !crtc->state->active && crtc->state->event) {
14473                         spin_lock_irq(&dev->event_lock);
14474                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
14475                         spin_unlock_irq(&dev->event_lock);
14476
14477                         crtc->state->event = NULL;
14478                 }
14479         }
14480
14481         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14482         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14483
14484         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14485          * already, but still need the state for the delayed optimization. To
14486          * fix this:
14487          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14488          * - schedule that vblank worker _before_ calling hw_done
14489          * - at the start of commit_tail, cancel it _synchrously
14490          * - switch over to the vblank wait helper in the core after that since
14491          *   we don't need out special handling any more.
14492          */
14493         if (!state->legacy_cursor_update)
14494                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14495
14496         /*
14497          * Now that the vblank has passed, we can go ahead and program the
14498          * optimal watermarks on platforms that need two-step watermark
14499          * programming.
14500          *
14501          * TODO: Move this (and other cleanup) to an async worker eventually.
14502          */
14503         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14504                 intel_cstate = to_intel_crtc_state(crtc->state);
14505
14506                 if (dev_priv->display.optimize_watermarks)
14507                         dev_priv->display.optimize_watermarks(intel_state,
14508                                                               intel_cstate);
14509         }
14510
14511         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14512                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14513
14514                 if (put_domains[i])
14515                         modeset_put_power_domains(dev_priv, put_domains[i]);
14516
14517                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state);
14518         }
14519
14520         if (intel_state->modeset && intel_can_enable_sagv(state))
14521                 intel_enable_sagv(dev_priv);
14522
14523         drm_atomic_helper_commit_hw_done(state);
14524
14525         if (intel_state->modeset)
14526                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14527
14528         mutex_lock(&dev->struct_mutex);
14529         drm_atomic_helper_cleanup_planes(dev, state);
14530         mutex_unlock(&dev->struct_mutex);
14531
14532         drm_atomic_helper_commit_cleanup_done(state);
14533
14534         drm_atomic_state_put(state);
14535
14536         /* As one of the primary mmio accessors, KMS has a high likelihood
14537          * of triggering bugs in unclaimed access. After we finish
14538          * modesetting, see if an error has been flagged, and if so
14539          * enable debugging for the next modeset - and hope we catch
14540          * the culprit.
14541          *
14542          * XXX note that we assume display power is on at this point.
14543          * This might hold true now but we need to add pm helper to check
14544          * unclaimed only when the hardware is on, as atomic commits
14545          * can happen also when the device is completely off.
14546          */
14547         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14548 }
14549
14550 static void intel_atomic_commit_work(struct work_struct *work)
14551 {
14552         struct drm_atomic_state *state =
14553                 container_of(work, struct drm_atomic_state, commit_work);
14554
14555         intel_atomic_commit_tail(state);
14556 }
14557
14558 static int __i915_sw_fence_call
14559 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14560                           enum i915_sw_fence_notify notify)
14561 {
14562         struct intel_atomic_state *state =
14563                 container_of(fence, struct intel_atomic_state, commit_ready);
14564
14565         switch (notify) {
14566         case FENCE_COMPLETE:
14567                 if (state->base.commit_work.func)
14568                         queue_work(system_unbound_wq, &state->base.commit_work);
14569                 break;
14570
14571         case FENCE_FREE:
14572                 drm_atomic_state_put(&state->base);
14573                 break;
14574         }
14575
14576         return NOTIFY_DONE;
14577 }
14578
14579 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14580 {
14581         struct drm_plane_state *old_plane_state;
14582         struct drm_plane *plane;
14583         int i;
14584
14585         for_each_plane_in_state(state, plane, old_plane_state, i)
14586                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14587                                   intel_fb_obj(plane->state->fb),
14588                                   to_intel_plane(plane)->frontbuffer_bit);
14589 }
14590
14591 /**
14592  * intel_atomic_commit - commit validated state object
14593  * @dev: DRM device
14594  * @state: the top-level driver state object
14595  * @nonblock: nonblocking commit
14596  *
14597  * This function commits a top-level state object that has been validated
14598  * with drm_atomic_helper_check().
14599  *
14600  * RETURNS
14601  * Zero for success or -errno.
14602  */
14603 static int intel_atomic_commit(struct drm_device *dev,
14604                                struct drm_atomic_state *state,
14605                                bool nonblock)
14606 {
14607         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14608         struct drm_i915_private *dev_priv = to_i915(dev);
14609         int ret = 0;
14610
14611         ret = drm_atomic_helper_setup_commit(state, nonblock);
14612         if (ret)
14613                 return ret;
14614
14615         drm_atomic_state_get(state);
14616         i915_sw_fence_init(&intel_state->commit_ready,
14617                            intel_atomic_commit_ready);
14618
14619         ret = intel_atomic_prepare_commit(dev, state);
14620         if (ret) {
14621                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14622                 i915_sw_fence_commit(&intel_state->commit_ready);
14623                 return ret;
14624         }
14625
14626         drm_atomic_helper_swap_state(state, true);
14627         dev_priv->wm.distrust_bios_wm = false;
14628         intel_shared_dpll_swap_state(state);
14629         intel_atomic_track_fbs(state);
14630
14631         if (intel_state->modeset) {
14632                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14633                        sizeof(intel_state->min_pixclk));
14634                 dev_priv->active_crtcs = intel_state->active_crtcs;
14635                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14636         }
14637
14638         drm_atomic_state_get(state);
14639         INIT_WORK(&state->commit_work,
14640                   nonblock ? intel_atomic_commit_work : NULL);
14641
14642         i915_sw_fence_commit(&intel_state->commit_ready);
14643         if (!nonblock) {
14644                 i915_sw_fence_wait(&intel_state->commit_ready);
14645                 intel_atomic_commit_tail(state);
14646         }
14647
14648         return 0;
14649 }
14650
14651 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14652 {
14653         struct drm_device *dev = crtc->dev;
14654         struct drm_atomic_state *state;
14655         struct drm_crtc_state *crtc_state;
14656         int ret;
14657
14658         state = drm_atomic_state_alloc(dev);
14659         if (!state) {
14660                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14661                               crtc->base.id, crtc->name);
14662                 return;
14663         }
14664
14665         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14666
14667 retry:
14668         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14669         ret = PTR_ERR_OR_ZERO(crtc_state);
14670         if (!ret) {
14671                 if (!crtc_state->active)
14672                         goto out;
14673
14674                 crtc_state->mode_changed = true;
14675                 ret = drm_atomic_commit(state);
14676         }
14677
14678         if (ret == -EDEADLK) {
14679                 drm_atomic_state_clear(state);
14680                 drm_modeset_backoff(state->acquire_ctx);
14681                 goto retry;
14682         }
14683
14684 out:
14685         drm_atomic_state_put(state);
14686 }
14687
14688 /*
14689  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14690  *        drm_atomic_helper_legacy_gamma_set() directly.
14691  */
14692 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14693                                          u16 *red, u16 *green, u16 *blue,
14694                                          uint32_t size)
14695 {
14696         struct drm_device *dev = crtc->dev;
14697         struct drm_mode_config *config = &dev->mode_config;
14698         struct drm_crtc_state *state;
14699         int ret;
14700
14701         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14702         if (ret)
14703                 return ret;
14704
14705         /*
14706          * Make sure we update the legacy properties so this works when
14707          * atomic is not enabled.
14708          */
14709
14710         state = crtc->state;
14711
14712         drm_object_property_set_value(&crtc->base,
14713                                       config->degamma_lut_property,
14714                                       (state->degamma_lut) ?
14715                                       state->degamma_lut->base.id : 0);
14716
14717         drm_object_property_set_value(&crtc->base,
14718                                       config->ctm_property,
14719                                       (state->ctm) ?
14720                                       state->ctm->base.id : 0);
14721
14722         drm_object_property_set_value(&crtc->base,
14723                                       config->gamma_lut_property,
14724                                       (state->gamma_lut) ?
14725                                       state->gamma_lut->base.id : 0);
14726
14727         return 0;
14728 }
14729
14730 static const struct drm_crtc_funcs intel_crtc_funcs = {
14731         .gamma_set = intel_atomic_legacy_gamma_set,
14732         .set_config = drm_atomic_helper_set_config,
14733         .set_property = drm_atomic_helper_crtc_set_property,
14734         .destroy = intel_crtc_destroy,
14735         .page_flip = intel_crtc_page_flip,
14736         .atomic_duplicate_state = intel_crtc_duplicate_state,
14737         .atomic_destroy_state = intel_crtc_destroy_state,
14738 };
14739
14740 /**
14741  * intel_prepare_plane_fb - Prepare fb for usage on plane
14742  * @plane: drm plane to prepare for
14743  * @fb: framebuffer to prepare for presentation
14744  *
14745  * Prepares a framebuffer for usage on a display plane.  Generally this
14746  * involves pinning the underlying object and updating the frontbuffer tracking
14747  * bits.  Some older platforms need special physical address handling for
14748  * cursor planes.
14749  *
14750  * Must be called with struct_mutex held.
14751  *
14752  * Returns 0 on success, negative error code on failure.
14753  */
14754 int
14755 intel_prepare_plane_fb(struct drm_plane *plane,
14756                        struct drm_plane_state *new_state)
14757 {
14758         struct intel_atomic_state *intel_state =
14759                 to_intel_atomic_state(new_state->state);
14760         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14761         struct drm_framebuffer *fb = new_state->fb;
14762         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14763         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14764         int ret;
14765
14766         if (!obj && !old_obj)
14767                 return 0;
14768
14769         if (old_obj) {
14770                 struct drm_crtc_state *crtc_state =
14771                         drm_atomic_get_existing_crtc_state(new_state->state,
14772                                                            plane->state->crtc);
14773
14774                 /* Big Hammer, we also need to ensure that any pending
14775                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14776                  * current scanout is retired before unpinning the old
14777                  * framebuffer. Note that we rely on userspace rendering
14778                  * into the buffer attached to the pipe they are waiting
14779                  * on. If not, userspace generates a GPU hang with IPEHR
14780                  * point to the MI_WAIT_FOR_EVENT.
14781                  *
14782                  * This should only fail upon a hung GPU, in which case we
14783                  * can safely continue.
14784                  */
14785                 if (needs_modeset(crtc_state)) {
14786                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14787                                                               old_obj->resv, NULL,
14788                                                               false, 0,
14789                                                               GFP_KERNEL);
14790                         if (ret < 0)
14791                                 return ret;
14792                 }
14793         }
14794
14795         if (new_state->fence) { /* explicit fencing */
14796                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
14797                                                     new_state->fence,
14798                                                     I915_FENCE_TIMEOUT,
14799                                                     GFP_KERNEL);
14800                 if (ret < 0)
14801                         return ret;
14802         }
14803
14804         if (!obj)
14805                 return 0;
14806
14807         if (!new_state->fence) { /* implicit fencing */
14808                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14809                                                       obj->resv, NULL,
14810                                                       false, I915_FENCE_TIMEOUT,
14811                                                       GFP_KERNEL);
14812                 if (ret < 0)
14813                         return ret;
14814
14815                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
14816         }
14817
14818         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14819             INTEL_INFO(dev_priv)->cursor_needs_physical) {
14820                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
14821                 ret = i915_gem_object_attach_phys(obj, align);
14822                 if (ret) {
14823                         DRM_DEBUG_KMS("failed to attach phys object\n");
14824                         return ret;
14825                 }
14826         } else {
14827                 struct i915_vma *vma;
14828
14829                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14830                 if (IS_ERR(vma)) {
14831                         DRM_DEBUG_KMS("failed to pin object\n");
14832                         return PTR_ERR(vma);
14833                 }
14834         }
14835
14836         return 0;
14837 }
14838
14839 /**
14840  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14841  * @plane: drm plane to clean up for
14842  * @fb: old framebuffer that was on plane
14843  *
14844  * Cleans up a framebuffer that has just been removed from a plane.
14845  *
14846  * Must be called with struct_mutex held.
14847  */
14848 void
14849 intel_cleanup_plane_fb(struct drm_plane *plane,
14850                        struct drm_plane_state *old_state)
14851 {
14852         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14853         struct intel_plane_state *old_intel_state;
14854         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14855         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14856
14857         old_intel_state = to_intel_plane_state(old_state);
14858
14859         if (!obj && !old_obj)
14860                 return;
14861
14862         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14863             !INTEL_INFO(dev_priv)->cursor_needs_physical))
14864                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14865 }
14866
14867 int
14868 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14869 {
14870         int max_scale;
14871         int crtc_clock, cdclk;
14872
14873         if (!intel_crtc || !crtc_state->base.enable)
14874                 return DRM_PLANE_HELPER_NO_SCALING;
14875
14876         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14877         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14878
14879         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14880                 return DRM_PLANE_HELPER_NO_SCALING;
14881
14882         /*
14883          * skl max scale is lower of:
14884          *    close to 3 but not 3, -1 is for that purpose
14885          *            or
14886          *    cdclk/crtc_clock
14887          */
14888         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14889
14890         return max_scale;
14891 }
14892
14893 static int
14894 intel_check_primary_plane(struct drm_plane *plane,
14895                           struct intel_crtc_state *crtc_state,
14896                           struct intel_plane_state *state)
14897 {
14898         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14899         struct drm_crtc *crtc = state->base.crtc;
14900         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14901         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14902         bool can_position = false;
14903         int ret;
14904
14905         if (INTEL_GEN(dev_priv) >= 9) {
14906                 /* use scaler when colorkey is not required */
14907                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14908                         min_scale = 1;
14909                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14910                 }
14911                 can_position = true;
14912         }
14913
14914         ret = drm_plane_helper_check_state(&state->base,
14915                                            &state->clip,
14916                                            min_scale, max_scale,
14917                                            can_position, true);
14918         if (ret)
14919                 return ret;
14920
14921         if (!state->base.fb)
14922                 return 0;
14923
14924         if (INTEL_GEN(dev_priv) >= 9) {
14925                 ret = skl_check_plane_surface(state);
14926                 if (ret)
14927                         return ret;
14928         }
14929
14930         return 0;
14931 }
14932
14933 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14934                                     struct drm_crtc_state *old_crtc_state)
14935 {
14936         struct drm_device *dev = crtc->dev;
14937         struct drm_i915_private *dev_priv = to_i915(dev);
14938         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14939         struct intel_crtc_state *intel_cstate =
14940                 to_intel_crtc_state(crtc->state);
14941         struct intel_crtc_state *old_intel_cstate =
14942                 to_intel_crtc_state(old_crtc_state);
14943         struct intel_atomic_state *old_intel_state =
14944                 to_intel_atomic_state(old_crtc_state->state);
14945         bool modeset = needs_modeset(crtc->state);
14946
14947         /* Perform vblank evasion around commit operation */
14948         intel_pipe_update_start(intel_crtc);
14949
14950         if (modeset)
14951                 goto out;
14952
14953         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14954                 intel_color_set_csc(crtc->state);
14955                 intel_color_load_luts(crtc->state);
14956         }
14957
14958         if (intel_cstate->update_pipe)
14959                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
14960         else if (INTEL_GEN(dev_priv) >= 9)
14961                 skl_detach_scalers(intel_crtc);
14962
14963 out:
14964         if (dev_priv->display.atomic_update_watermarks)
14965                 dev_priv->display.atomic_update_watermarks(old_intel_state,
14966                                                            intel_cstate);
14967 }
14968
14969 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14970                                      struct drm_crtc_state *old_crtc_state)
14971 {
14972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14973
14974         intel_pipe_update_end(intel_crtc, NULL);
14975 }
14976
14977 /**
14978  * intel_plane_destroy - destroy a plane
14979  * @plane: plane to destroy
14980  *
14981  * Common destruction function for all types of planes (primary, cursor,
14982  * sprite).
14983  */
14984 void intel_plane_destroy(struct drm_plane *plane)
14985 {
14986         drm_plane_cleanup(plane);
14987         kfree(to_intel_plane(plane));
14988 }
14989
14990 const struct drm_plane_funcs intel_plane_funcs = {
14991         .update_plane = drm_atomic_helper_update_plane,
14992         .disable_plane = drm_atomic_helper_disable_plane,
14993         .destroy = intel_plane_destroy,
14994         .set_property = drm_atomic_helper_plane_set_property,
14995         .atomic_get_property = intel_plane_atomic_get_property,
14996         .atomic_set_property = intel_plane_atomic_set_property,
14997         .atomic_duplicate_state = intel_plane_duplicate_state,
14998         .atomic_destroy_state = intel_plane_destroy_state,
14999 };
15000
15001 static struct intel_plane *
15002 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15003 {
15004         struct intel_plane *primary = NULL;
15005         struct intel_plane_state *state = NULL;
15006         const uint32_t *intel_primary_formats;
15007         unsigned int supported_rotations;
15008         unsigned int num_formats;
15009         int ret;
15010
15011         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
15012         if (!primary) {
15013                 ret = -ENOMEM;
15014                 goto fail;
15015         }
15016
15017         state = intel_create_plane_state(&primary->base);
15018         if (!state) {
15019                 ret = -ENOMEM;
15020                 goto fail;
15021         }
15022
15023         primary->base.state = &state->base;
15024
15025         primary->can_scale = false;
15026         primary->max_downscale = 1;
15027         if (INTEL_GEN(dev_priv) >= 9) {
15028                 primary->can_scale = true;
15029                 state->scaler_id = -1;
15030         }
15031         primary->pipe = pipe;
15032         /*
15033          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15034          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15035          */
15036         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15037                 primary->plane = (enum plane) !pipe;
15038         else
15039                 primary->plane = (enum plane) pipe;
15040         primary->id = PLANE_PRIMARY;
15041         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
15042         primary->check_plane = intel_check_primary_plane;
15043
15044         if (INTEL_GEN(dev_priv) >= 9) {
15045                 intel_primary_formats = skl_primary_formats;
15046                 num_formats = ARRAY_SIZE(skl_primary_formats);
15047
15048                 primary->update_plane = skylake_update_primary_plane;
15049                 primary->disable_plane = skylake_disable_primary_plane;
15050         } else if (HAS_PCH_SPLIT(dev_priv)) {
15051                 intel_primary_formats = i965_primary_formats;
15052                 num_formats = ARRAY_SIZE(i965_primary_formats);
15053
15054                 primary->update_plane = ironlake_update_primary_plane;
15055                 primary->disable_plane = i9xx_disable_primary_plane;
15056         } else if (INTEL_GEN(dev_priv) >= 4) {
15057                 intel_primary_formats = i965_primary_formats;
15058                 num_formats = ARRAY_SIZE(i965_primary_formats);
15059
15060                 primary->update_plane = i9xx_update_primary_plane;
15061                 primary->disable_plane = i9xx_disable_primary_plane;
15062         } else {
15063                 intel_primary_formats = i8xx_primary_formats;
15064                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15065
15066                 primary->update_plane = i9xx_update_primary_plane;
15067                 primary->disable_plane = i9xx_disable_primary_plane;
15068         }
15069
15070         if (INTEL_GEN(dev_priv) >= 9)
15071                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15072                                                0, &intel_plane_funcs,
15073                                                intel_primary_formats, num_formats,
15074                                                DRM_PLANE_TYPE_PRIMARY,
15075                                                "plane 1%c", pipe_name(pipe));
15076         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15077                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15078                                                0, &intel_plane_funcs,
15079                                                intel_primary_formats, num_formats,
15080                                                DRM_PLANE_TYPE_PRIMARY,
15081                                                "primary %c", pipe_name(pipe));
15082         else
15083                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15084                                                0, &intel_plane_funcs,
15085                                                intel_primary_formats, num_formats,
15086                                                DRM_PLANE_TYPE_PRIMARY,
15087                                                "plane %c", plane_name(primary->plane));
15088         if (ret)
15089                 goto fail;
15090
15091         if (INTEL_GEN(dev_priv) >= 9) {
15092                 supported_rotations =
15093                         DRM_ROTATE_0 | DRM_ROTATE_90 |
15094                         DRM_ROTATE_180 | DRM_ROTATE_270;
15095         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15096                 supported_rotations =
15097                         DRM_ROTATE_0 | DRM_ROTATE_180 |
15098                         DRM_REFLECT_X;
15099         } else if (INTEL_GEN(dev_priv) >= 4) {
15100                 supported_rotations =
15101                         DRM_ROTATE_0 | DRM_ROTATE_180;
15102         } else {
15103                 supported_rotations = DRM_ROTATE_0;
15104         }
15105
15106         if (INTEL_GEN(dev_priv) >= 4)
15107                 drm_plane_create_rotation_property(&primary->base,
15108                                                    DRM_ROTATE_0,
15109                                                    supported_rotations);
15110
15111         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
15112
15113         return primary;
15114
15115 fail:
15116         kfree(state);
15117         kfree(primary);
15118
15119         return ERR_PTR(ret);
15120 }
15121
15122 static int
15123 intel_check_cursor_plane(struct drm_plane *plane,
15124                          struct intel_crtc_state *crtc_state,
15125                          struct intel_plane_state *state)
15126 {
15127         struct drm_framebuffer *fb = state->base.fb;
15128         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15129         enum pipe pipe = to_intel_plane(plane)->pipe;
15130         unsigned stride;
15131         int ret;
15132
15133         ret = drm_plane_helper_check_state(&state->base,
15134                                            &state->clip,
15135                                            DRM_PLANE_HELPER_NO_SCALING,
15136                                            DRM_PLANE_HELPER_NO_SCALING,
15137                                            true, true);
15138         if (ret)
15139                 return ret;
15140
15141         /* if we want to turn off the cursor ignore width and height */
15142         if (!obj)
15143                 return 0;
15144
15145         /* Check for which cursor types we support */
15146         if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
15147                             state->base.crtc_h)) {
15148                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15149                           state->base.crtc_w, state->base.crtc_h);
15150                 return -EINVAL;
15151         }
15152
15153         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15154         if (obj->base.size < stride * state->base.crtc_h) {
15155                 DRM_DEBUG_KMS("buffer is too small\n");
15156                 return -ENOMEM;
15157         }
15158
15159         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
15160                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15161                 return -EINVAL;
15162         }
15163
15164         /*
15165          * There's something wrong with the cursor on CHV pipe C.
15166          * If it straddles the left edge of the screen then
15167          * moving it away from the edge or disabling it often
15168          * results in a pipe underrun, and often that can lead to
15169          * dead pipe (constant underrun reported, and it scans
15170          * out just a solid color). To recover from that, the
15171          * display power well must be turned off and on again.
15172          * Refuse the put the cursor into that compromised position.
15173          */
15174         if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
15175             state->base.visible && state->base.crtc_x < 0) {
15176                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15177                 return -EINVAL;
15178         }
15179
15180         return 0;
15181 }
15182
15183 static void
15184 intel_disable_cursor_plane(struct drm_plane *plane,
15185                            struct drm_crtc *crtc)
15186 {
15187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15188
15189         intel_crtc->cursor_addr = 0;
15190         intel_crtc_update_cursor(crtc, NULL);
15191 }
15192
15193 static void
15194 intel_update_cursor_plane(struct drm_plane *plane,
15195                           const struct intel_crtc_state *crtc_state,
15196                           const struct intel_plane_state *state)
15197 {
15198         struct drm_crtc *crtc = crtc_state->base.crtc;
15199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15200         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15201         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15202         uint32_t addr;
15203
15204         if (!obj)
15205                 addr = 0;
15206         else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
15207                 addr = i915_gem_object_ggtt_offset(obj, NULL);
15208         else
15209                 addr = obj->phys_handle->busaddr;
15210
15211         intel_crtc->cursor_addr = addr;
15212         intel_crtc_update_cursor(crtc, state);
15213 }
15214
15215 static struct intel_plane *
15216 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15217 {
15218         struct intel_plane *cursor = NULL;
15219         struct intel_plane_state *state = NULL;
15220         int ret;
15221
15222         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15223         if (!cursor) {
15224                 ret = -ENOMEM;
15225                 goto fail;
15226         }
15227
15228         state = intel_create_plane_state(&cursor->base);
15229         if (!state) {
15230                 ret = -ENOMEM;
15231                 goto fail;
15232         }
15233
15234         cursor->base.state = &state->base;
15235
15236         cursor->can_scale = false;
15237         cursor->max_downscale = 1;
15238         cursor->pipe = pipe;
15239         cursor->plane = pipe;
15240         cursor->id = PLANE_CURSOR;
15241         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15242         cursor->check_plane = intel_check_cursor_plane;
15243         cursor->update_plane = intel_update_cursor_plane;
15244         cursor->disable_plane = intel_disable_cursor_plane;
15245
15246         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15247                                        0, &intel_plane_funcs,
15248                                        intel_cursor_formats,
15249                                        ARRAY_SIZE(intel_cursor_formats),
15250                                        DRM_PLANE_TYPE_CURSOR,
15251                                        "cursor %c", pipe_name(pipe));
15252         if (ret)
15253                 goto fail;
15254
15255         if (INTEL_GEN(dev_priv) >= 4)
15256                 drm_plane_create_rotation_property(&cursor->base,
15257                                                    DRM_ROTATE_0,
15258                                                    DRM_ROTATE_0 |
15259                                                    DRM_ROTATE_180);
15260
15261         if (INTEL_GEN(dev_priv) >= 9)
15262                 state->scaler_id = -1;
15263
15264         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15265
15266         return cursor;
15267
15268 fail:
15269         kfree(state);
15270         kfree(cursor);
15271
15272         return ERR_PTR(ret);
15273 }
15274
15275 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
15276                                     struct intel_crtc_state *crtc_state)
15277 {
15278         struct intel_crtc_scaler_state *scaler_state =
15279                 &crtc_state->scaler_state;
15280         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15281         int i;
15282
15283         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
15284         if (!crtc->num_scalers)
15285                 return;
15286
15287         for (i = 0; i < crtc->num_scalers; i++) {
15288                 struct intel_scaler *scaler = &scaler_state->scalers[i];
15289
15290                 scaler->in_use = 0;
15291                 scaler->mode = PS_SCALER_MODE_DYN;
15292         }
15293
15294         scaler_state->scaler_id = -1;
15295 }
15296
15297 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15298 {
15299         struct intel_crtc *intel_crtc;
15300         struct intel_crtc_state *crtc_state = NULL;
15301         struct intel_plane *primary = NULL;
15302         struct intel_plane *cursor = NULL;
15303         int sprite, ret;
15304
15305         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15306         if (!intel_crtc)
15307                 return -ENOMEM;
15308
15309         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15310         if (!crtc_state) {
15311                 ret = -ENOMEM;
15312                 goto fail;
15313         }
15314         intel_crtc->config = crtc_state;
15315         intel_crtc->base.state = &crtc_state->base;
15316         crtc_state->base.crtc = &intel_crtc->base;
15317
15318         primary = intel_primary_plane_create(dev_priv, pipe);
15319         if (IS_ERR(primary)) {
15320                 ret = PTR_ERR(primary);
15321                 goto fail;
15322         }
15323         intel_crtc->plane_ids_mask |= BIT(primary->id);
15324
15325         for_each_sprite(dev_priv, pipe, sprite) {
15326                 struct intel_plane *plane;
15327
15328                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15329                 if (IS_ERR(plane)) {
15330                         ret = PTR_ERR(plane);
15331                         goto fail;
15332                 }
15333                 intel_crtc->plane_ids_mask |= BIT(plane->id);
15334         }
15335
15336         cursor = intel_cursor_plane_create(dev_priv, pipe);
15337         if (IS_ERR(cursor)) {
15338                 ret = PTR_ERR(cursor);
15339                 goto fail;
15340         }
15341         intel_crtc->plane_ids_mask |= BIT(cursor->id);
15342
15343         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15344                                         &primary->base, &cursor->base,
15345                                         &intel_crtc_funcs,
15346                                         "pipe %c", pipe_name(pipe));
15347         if (ret)
15348                 goto fail;
15349
15350         intel_crtc->pipe = pipe;
15351         intel_crtc->plane = primary->plane;
15352
15353         intel_crtc->cursor_base = ~0;
15354         intel_crtc->cursor_cntl = ~0;
15355         intel_crtc->cursor_size = ~0;
15356
15357         intel_crtc->wm.cxsr_allowed = true;
15358
15359         /* initialize shared scalers */
15360         intel_crtc_init_scalers(intel_crtc, crtc_state);
15361
15362         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15363                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15364         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
15365         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
15366
15367         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15368
15369         intel_color_init(&intel_crtc->base);
15370
15371         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15372
15373         return 0;
15374
15375 fail:
15376         /*
15377          * drm_mode_config_cleanup() will free up any
15378          * crtcs/planes already initialized.
15379          */
15380         kfree(crtc_state);
15381         kfree(intel_crtc);
15382
15383         return ret;
15384 }
15385
15386 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15387 {
15388         struct drm_encoder *encoder = connector->base.encoder;
15389         struct drm_device *dev = connector->base.dev;
15390
15391         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15392
15393         if (!encoder || WARN_ON(!encoder->crtc))
15394                 return INVALID_PIPE;
15395
15396         return to_intel_crtc(encoder->crtc)->pipe;
15397 }
15398
15399 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15400                                 struct drm_file *file)
15401 {
15402         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15403         struct drm_crtc *drmmode_crtc;
15404         struct intel_crtc *crtc;
15405
15406         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15407         if (!drmmode_crtc)
15408                 return -ENOENT;
15409
15410         crtc = to_intel_crtc(drmmode_crtc);
15411         pipe_from_crtc_id->pipe = crtc->pipe;
15412
15413         return 0;
15414 }
15415
15416 static int intel_encoder_clones(struct intel_encoder *encoder)
15417 {
15418         struct drm_device *dev = encoder->base.dev;
15419         struct intel_encoder *source_encoder;
15420         int index_mask = 0;
15421         int entry = 0;
15422
15423         for_each_intel_encoder(dev, source_encoder) {
15424                 if (encoders_cloneable(encoder, source_encoder))
15425                         index_mask |= (1 << entry);
15426
15427                 entry++;
15428         }
15429
15430         return index_mask;
15431 }
15432
15433 static bool has_edp_a(struct drm_i915_private *dev_priv)
15434 {
15435         if (!IS_MOBILE(dev_priv))
15436                 return false;
15437
15438         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15439                 return false;
15440
15441         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15442                 return false;
15443
15444         return true;
15445 }
15446
15447 static bool intel_crt_present(struct drm_i915_private *dev_priv)
15448 {
15449         if (INTEL_GEN(dev_priv) >= 9)
15450                 return false;
15451
15452         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15453                 return false;
15454
15455         if (IS_CHERRYVIEW(dev_priv))
15456                 return false;
15457
15458         if (HAS_PCH_LPT_H(dev_priv) &&
15459             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15460                 return false;
15461
15462         /* DDI E can't be used if DDI A requires 4 lanes */
15463         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15464                 return false;
15465
15466         if (!dev_priv->vbt.int_crt_support)
15467                 return false;
15468
15469         return true;
15470 }
15471
15472 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15473 {
15474         int pps_num;
15475         int pps_idx;
15476
15477         if (HAS_DDI(dev_priv))
15478                 return;
15479         /*
15480          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15481          * everywhere where registers can be write protected.
15482          */
15483         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15484                 pps_num = 2;
15485         else
15486                 pps_num = 1;
15487
15488         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15489                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15490
15491                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15492                 I915_WRITE(PP_CONTROL(pps_idx), val);
15493         }
15494 }
15495
15496 static void intel_pps_init(struct drm_i915_private *dev_priv)
15497 {
15498         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
15499                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15500         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15501                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15502         else
15503                 dev_priv->pps_mmio_base = PPS_BASE;
15504
15505         intel_pps_unlock_regs_wa(dev_priv);
15506 }
15507
15508 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
15509 {
15510         struct intel_encoder *encoder;
15511         bool dpd_is_edp = false;
15512
15513         intel_pps_init(dev_priv);
15514
15515         /*
15516          * intel_edp_init_connector() depends on this completing first, to
15517          * prevent the registeration of both eDP and LVDS and the incorrect
15518          * sharing of the PPS.
15519          */
15520         intel_lvds_init(dev_priv);
15521
15522         if (intel_crt_present(dev_priv))
15523                 intel_crt_init(dev_priv);
15524
15525         if (IS_GEN9_LP(dev_priv)) {
15526                 /*
15527                  * FIXME: Broxton doesn't support port detection via the
15528                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15529                  * detect the ports.
15530                  */
15531                 intel_ddi_init(dev_priv, PORT_A);
15532                 intel_ddi_init(dev_priv, PORT_B);
15533                 intel_ddi_init(dev_priv, PORT_C);
15534
15535                 intel_dsi_init(dev_priv);
15536         } else if (HAS_DDI(dev_priv)) {
15537                 int found;
15538
15539                 /*
15540                  * Haswell uses DDI functions to detect digital outputs.
15541                  * On SKL pre-D0 the strap isn't connected, so we assume
15542                  * it's there.
15543                  */
15544                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15545                 /* WaIgnoreDDIAStrap: skl */
15546                 if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15547                         intel_ddi_init(dev_priv, PORT_A);
15548
15549                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15550                  * register */
15551                 found = I915_READ(SFUSE_STRAP);
15552
15553                 if (found & SFUSE_STRAP_DDIB_DETECTED)
15554                         intel_ddi_init(dev_priv, PORT_B);
15555                 if (found & SFUSE_STRAP_DDIC_DETECTED)
15556                         intel_ddi_init(dev_priv, PORT_C);
15557                 if (found & SFUSE_STRAP_DDID_DETECTED)
15558                         intel_ddi_init(dev_priv, PORT_D);
15559                 /*
15560                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15561                  */
15562                 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
15563                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15564                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15565                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15566                         intel_ddi_init(dev_priv, PORT_E);
15567
15568         } else if (HAS_PCH_SPLIT(dev_priv)) {
15569                 int found;
15570                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
15571
15572                 if (has_edp_a(dev_priv))
15573                         intel_dp_init(dev_priv, DP_A, PORT_A);
15574
15575                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15576                         /* PCH SDVOB multiplex with HDMIB */
15577                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
15578                         if (!found)
15579                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
15580                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15581                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
15582                 }
15583
15584                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15585                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
15586
15587                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15588                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
15589
15590                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15591                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
15592
15593                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15594                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
15595         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15596                 bool has_edp, has_port;
15597
15598                 /*
15599                  * The DP_DETECTED bit is the latched state of the DDC
15600                  * SDA pin at boot. However since eDP doesn't require DDC
15601                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
15602                  * eDP ports may have been muxed to an alternate function.
15603                  * Thus we can't rely on the DP_DETECTED bit alone to detect
15604                  * eDP ports. Consult the VBT as well as DP_DETECTED to
15605                  * detect eDP ports.
15606                  *
15607                  * Sadly the straps seem to be missing sometimes even for HDMI
15608                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15609                  * and VBT for the presence of the port. Additionally we can't
15610                  * trust the port type the VBT declares as we've seen at least
15611                  * HDMI ports that the VBT claim are DP or eDP.
15612                  */
15613                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
15614                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15615                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15616                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
15617                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15618                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
15619
15620                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
15621                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15622                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15623                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
15624                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15625                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
15626
15627                 if (IS_CHERRYVIEW(dev_priv)) {
15628                         /*
15629                          * eDP not supported on port D,
15630                          * so no need to worry about it
15631                          */
15632                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15633                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15634                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
15635                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15636                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
15637                 }
15638
15639                 intel_dsi_init(dev_priv);
15640         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
15641                 bool found = false;
15642
15643                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15644                         DRM_DEBUG_KMS("probing SDVOB\n");
15645                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
15646                         if (!found && IS_G4X(dev_priv)) {
15647                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15648                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
15649                         }
15650
15651                         if (!found && IS_G4X(dev_priv))
15652                                 intel_dp_init(dev_priv, DP_B, PORT_B);
15653                 }
15654
15655                 /* Before G4X SDVOC doesn't have its own detect register */
15656
15657                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15658                         DRM_DEBUG_KMS("probing SDVOC\n");
15659                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
15660                 }
15661
15662                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15663
15664                         if (IS_G4X(dev_priv)) {
15665                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15666                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
15667                         }
15668                         if (IS_G4X(dev_priv))
15669                                 intel_dp_init(dev_priv, DP_C, PORT_C);
15670                 }
15671
15672                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
15673                         intel_dp_init(dev_priv, DP_D, PORT_D);
15674         } else if (IS_GEN2(dev_priv))
15675                 intel_dvo_init(dev_priv);
15676
15677         if (SUPPORTS_TV(dev_priv))
15678                 intel_tv_init(dev_priv);
15679
15680         intel_psr_init(dev_priv);
15681
15682         for_each_intel_encoder(&dev_priv->drm, encoder) {
15683                 encoder->base.possible_crtcs = encoder->crtc_mask;
15684                 encoder->base.possible_clones =
15685                         intel_encoder_clones(encoder);
15686         }
15687
15688         intel_init_pch_refclk(dev_priv);
15689
15690         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
15691 }
15692
15693 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15694 {
15695         struct drm_device *dev = fb->dev;
15696         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15697
15698         drm_framebuffer_cleanup(fb);
15699         mutex_lock(&dev->struct_mutex);
15700         WARN_ON(!intel_fb->obj->framebuffer_references--);
15701         i915_gem_object_put(intel_fb->obj);
15702         mutex_unlock(&dev->struct_mutex);
15703         kfree(intel_fb);
15704 }
15705
15706 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15707                                                 struct drm_file *file,
15708                                                 unsigned int *handle)
15709 {
15710         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15711         struct drm_i915_gem_object *obj = intel_fb->obj;
15712
15713         if (obj->userptr.mm) {
15714                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15715                 return -EINVAL;
15716         }
15717
15718         return drm_gem_handle_create(file, &obj->base, handle);
15719 }
15720
15721 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15722                                         struct drm_file *file,
15723                                         unsigned flags, unsigned color,
15724                                         struct drm_clip_rect *clips,
15725                                         unsigned num_clips)
15726 {
15727         struct drm_device *dev = fb->dev;
15728         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15729         struct drm_i915_gem_object *obj = intel_fb->obj;
15730
15731         mutex_lock(&dev->struct_mutex);
15732         if (obj->pin_display && obj->cache_dirty)
15733                 i915_gem_clflush_object(obj, true);
15734         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15735         mutex_unlock(&dev->struct_mutex);
15736
15737         return 0;
15738 }
15739
15740 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15741         .destroy = intel_user_framebuffer_destroy,
15742         .create_handle = intel_user_framebuffer_create_handle,
15743         .dirty = intel_user_framebuffer_dirty,
15744 };
15745
15746 static
15747 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
15748                          uint64_t fb_modifier, uint32_t pixel_format)
15749 {
15750         u32 gen = INTEL_INFO(dev_priv)->gen;
15751
15752         if (gen >= 9) {
15753                 int cpp = drm_format_plane_cpp(pixel_format, 0);
15754
15755                 /* "The stride in bytes must not exceed the of the size of 8K
15756                  *  pixels and 32K bytes."
15757                  */
15758                 return min(8192 * cpp, 32768);
15759         } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
15760                    !IS_CHERRYVIEW(dev_priv)) {
15761                 return 32*1024;
15762         } else if (gen >= 4) {
15763                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15764                         return 16*1024;
15765                 else
15766                         return 32*1024;
15767         } else if (gen >= 3) {
15768                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15769                         return 8*1024;
15770                 else
15771                         return 16*1024;
15772         } else {
15773                 /* XXX DSPC is limited to 4k tiled */
15774                 return 8*1024;
15775         }
15776 }
15777
15778 static int intel_framebuffer_init(struct drm_device *dev,
15779                                   struct intel_framebuffer *intel_fb,
15780                                   struct drm_mode_fb_cmd2 *mode_cmd,
15781                                   struct drm_i915_gem_object *obj)
15782 {
15783         struct drm_i915_private *dev_priv = to_i915(dev);
15784         unsigned int tiling = i915_gem_object_get_tiling(obj);
15785         int ret;
15786         u32 pitch_limit, stride_alignment;
15787         struct drm_format_name_buf format_name;
15788
15789         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15790
15791         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15792                 /*
15793                  * If there's a fence, enforce that
15794                  * the fb modifier and tiling mode match.
15795                  */
15796                 if (tiling != I915_TILING_NONE &&
15797                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15798                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15799                         return -EINVAL;
15800                 }
15801         } else {
15802                 if (tiling == I915_TILING_X) {
15803                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15804                 } else if (tiling == I915_TILING_Y) {
15805                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15806                         return -EINVAL;
15807                 }
15808         }
15809
15810         /* Passed in modifier sanity checking. */
15811         switch (mode_cmd->modifier[0]) {
15812         case I915_FORMAT_MOD_Y_TILED:
15813         case I915_FORMAT_MOD_Yf_TILED:
15814                 if (INTEL_GEN(dev_priv) < 9) {
15815                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15816                                   mode_cmd->modifier[0]);
15817                         return -EINVAL;
15818                 }
15819         case DRM_FORMAT_MOD_NONE:
15820         case I915_FORMAT_MOD_X_TILED:
15821                 break;
15822         default:
15823                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15824                           mode_cmd->modifier[0]);
15825                 return -EINVAL;
15826         }
15827
15828         /*
15829          * gen2/3 display engine uses the fence if present,
15830          * so the tiling mode must match the fb modifier exactly.
15831          */
15832         if (INTEL_INFO(dev_priv)->gen < 4 &&
15833             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15834                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15835                 return -EINVAL;
15836         }
15837
15838         stride_alignment = intel_fb_stride_alignment(dev_priv,
15839                                                      mode_cmd->modifier[0],
15840                                                      mode_cmd->pixel_format);
15841         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15842                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15843                           mode_cmd->pitches[0], stride_alignment);
15844                 return -EINVAL;
15845         }
15846
15847         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
15848                                            mode_cmd->pixel_format);
15849         if (mode_cmd->pitches[0] > pitch_limit) {
15850                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15851                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15852                           "tiled" : "linear",
15853                           mode_cmd->pitches[0], pitch_limit);
15854                 return -EINVAL;
15855         }
15856
15857         /*
15858          * If there's a fence, enforce that
15859          * the fb pitch and fence stride match.
15860          */
15861         if (tiling != I915_TILING_NONE &&
15862             mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15863                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15864                           mode_cmd->pitches[0],
15865                           i915_gem_object_get_stride(obj));
15866                 return -EINVAL;
15867         }
15868
15869         /* Reject formats not supported by any plane early. */
15870         switch (mode_cmd->pixel_format) {
15871         case DRM_FORMAT_C8:
15872         case DRM_FORMAT_RGB565:
15873         case DRM_FORMAT_XRGB8888:
15874         case DRM_FORMAT_ARGB8888:
15875                 break;
15876         case DRM_FORMAT_XRGB1555:
15877                 if (INTEL_GEN(dev_priv) > 3) {
15878                         DRM_DEBUG("unsupported pixel format: %s\n",
15879                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15880                         return -EINVAL;
15881                 }
15882                 break;
15883         case DRM_FORMAT_ABGR8888:
15884                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
15885                     INTEL_GEN(dev_priv) < 9) {
15886                         DRM_DEBUG("unsupported pixel format: %s\n",
15887                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15888                         return -EINVAL;
15889                 }
15890                 break;
15891         case DRM_FORMAT_XBGR8888:
15892         case DRM_FORMAT_XRGB2101010:
15893         case DRM_FORMAT_XBGR2101010:
15894                 if (INTEL_GEN(dev_priv) < 4) {
15895                         DRM_DEBUG("unsupported pixel format: %s\n",
15896                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15897                         return -EINVAL;
15898                 }
15899                 break;
15900         case DRM_FORMAT_ABGR2101010:
15901                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
15902                         DRM_DEBUG("unsupported pixel format: %s\n",
15903                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15904                         return -EINVAL;
15905                 }
15906                 break;
15907         case DRM_FORMAT_YUYV:
15908         case DRM_FORMAT_UYVY:
15909         case DRM_FORMAT_YVYU:
15910         case DRM_FORMAT_VYUY:
15911                 if (INTEL_GEN(dev_priv) < 5) {
15912                         DRM_DEBUG("unsupported pixel format: %s\n",
15913                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15914                         return -EINVAL;
15915                 }
15916                 break;
15917         default:
15918                 DRM_DEBUG("unsupported pixel format: %s\n",
15919                           drm_get_format_name(mode_cmd->pixel_format, &format_name));
15920                 return -EINVAL;
15921         }
15922
15923         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15924         if (mode_cmd->offsets[0] != 0)
15925                 return -EINVAL;
15926
15927         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15928         intel_fb->obj = obj;
15929
15930         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15931         if (ret)
15932                 return ret;
15933
15934         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15935         if (ret) {
15936                 DRM_ERROR("framebuffer init failed %d\n", ret);
15937                 return ret;
15938         }
15939
15940         intel_fb->obj->framebuffer_references++;
15941
15942         return 0;
15943 }
15944
15945 static struct drm_framebuffer *
15946 intel_user_framebuffer_create(struct drm_device *dev,
15947                               struct drm_file *filp,
15948                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15949 {
15950         struct drm_framebuffer *fb;
15951         struct drm_i915_gem_object *obj;
15952         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15953
15954         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15955         if (!obj)
15956                 return ERR_PTR(-ENOENT);
15957
15958         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15959         if (IS_ERR(fb))
15960                 i915_gem_object_put(obj);
15961
15962         return fb;
15963 }
15964
15965 static void intel_atomic_state_free(struct drm_atomic_state *state)
15966 {
15967         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
15968
15969         drm_atomic_state_default_release(state);
15970
15971         i915_sw_fence_fini(&intel_state->commit_ready);
15972
15973         kfree(state);
15974 }
15975
15976 static const struct drm_mode_config_funcs intel_mode_funcs = {
15977         .fb_create = intel_user_framebuffer_create,
15978         .output_poll_changed = intel_fbdev_output_poll_changed,
15979         .atomic_check = intel_atomic_check,
15980         .atomic_commit = intel_atomic_commit,
15981         .atomic_state_alloc = intel_atomic_state_alloc,
15982         .atomic_state_clear = intel_atomic_state_clear,
15983         .atomic_state_free = intel_atomic_state_free,
15984 };
15985
15986 /**
15987  * intel_init_display_hooks - initialize the display modesetting hooks
15988  * @dev_priv: device private
15989  */
15990 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15991 {
15992         if (INTEL_INFO(dev_priv)->gen >= 9) {
15993                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15994                 dev_priv->display.get_initial_plane_config =
15995                         skylake_get_initial_plane_config;
15996                 dev_priv->display.crtc_compute_clock =
15997                         haswell_crtc_compute_clock;
15998                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15999                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16000         } else if (HAS_DDI(dev_priv)) {
16001                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16002                 dev_priv->display.get_initial_plane_config =
16003                         ironlake_get_initial_plane_config;
16004                 dev_priv->display.crtc_compute_clock =
16005                         haswell_crtc_compute_clock;
16006                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16007                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16008         } else if (HAS_PCH_SPLIT(dev_priv)) {
16009                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
16010                 dev_priv->display.get_initial_plane_config =
16011                         ironlake_get_initial_plane_config;
16012                 dev_priv->display.crtc_compute_clock =
16013                         ironlake_crtc_compute_clock;
16014                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
16015                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
16016         } else if (IS_CHERRYVIEW(dev_priv)) {
16017                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16018                 dev_priv->display.get_initial_plane_config =
16019                         i9xx_get_initial_plane_config;
16020                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
16021                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16022                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16023         } else if (IS_VALLEYVIEW(dev_priv)) {
16024                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16025                 dev_priv->display.get_initial_plane_config =
16026                         i9xx_get_initial_plane_config;
16027                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
16028                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16029                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16030         } else if (IS_G4X(dev_priv)) {
16031                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16032                 dev_priv->display.get_initial_plane_config =
16033                         i9xx_get_initial_plane_config;
16034                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
16035                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16036                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16037         } else if (IS_PINEVIEW(dev_priv)) {
16038                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16039                 dev_priv->display.get_initial_plane_config =
16040                         i9xx_get_initial_plane_config;
16041                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
16042                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16043                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16044         } else if (!IS_GEN2(dev_priv)) {
16045                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16046                 dev_priv->display.get_initial_plane_config =
16047                         i9xx_get_initial_plane_config;
16048                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
16049                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16050                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16051         } else {
16052                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16053                 dev_priv->display.get_initial_plane_config =
16054                         i9xx_get_initial_plane_config;
16055                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16056                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16057                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16058         }
16059
16060         /* Returns the core display clock speed */
16061         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
16062                 dev_priv->display.get_display_clock_speed =
16063                         skylake_get_display_clock_speed;
16064         else if (IS_GEN9_LP(dev_priv))
16065                 dev_priv->display.get_display_clock_speed =
16066                         broxton_get_display_clock_speed;
16067         else if (IS_BROADWELL(dev_priv))
16068                 dev_priv->display.get_display_clock_speed =
16069                         broadwell_get_display_clock_speed;
16070         else if (IS_HASWELL(dev_priv))
16071                 dev_priv->display.get_display_clock_speed =
16072                         haswell_get_display_clock_speed;
16073         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16074                 dev_priv->display.get_display_clock_speed =
16075                         valleyview_get_display_clock_speed;
16076         else if (IS_GEN5(dev_priv))
16077                 dev_priv->display.get_display_clock_speed =
16078                         ilk_get_display_clock_speed;
16079         else if (IS_I945G(dev_priv) || IS_I965G(dev_priv) ||
16080                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
16081                 dev_priv->display.get_display_clock_speed =
16082                         i945_get_display_clock_speed;
16083         else if (IS_GM45(dev_priv))
16084                 dev_priv->display.get_display_clock_speed =
16085                         gm45_get_display_clock_speed;
16086         else if (IS_I965GM(dev_priv))
16087                 dev_priv->display.get_display_clock_speed =
16088                         i965gm_get_display_clock_speed;
16089         else if (IS_PINEVIEW(dev_priv))
16090                 dev_priv->display.get_display_clock_speed =
16091                         pnv_get_display_clock_speed;
16092         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
16093                 dev_priv->display.get_display_clock_speed =
16094                         g33_get_display_clock_speed;
16095         else if (IS_I915G(dev_priv))
16096                 dev_priv->display.get_display_clock_speed =
16097                         i915_get_display_clock_speed;
16098         else if (IS_I945GM(dev_priv) || IS_I845G(dev_priv))
16099                 dev_priv->display.get_display_clock_speed =
16100                         i9xx_misc_get_display_clock_speed;
16101         else if (IS_I915GM(dev_priv))
16102                 dev_priv->display.get_display_clock_speed =
16103                         i915gm_get_display_clock_speed;
16104         else if (IS_I865G(dev_priv))
16105                 dev_priv->display.get_display_clock_speed =
16106                         i865_get_display_clock_speed;
16107         else if (IS_I85X(dev_priv))
16108                 dev_priv->display.get_display_clock_speed =
16109                         i85x_get_display_clock_speed;
16110         else { /* 830 */
16111                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
16112                 dev_priv->display.get_display_clock_speed =
16113                         i830_get_display_clock_speed;
16114         }
16115
16116         if (IS_GEN5(dev_priv)) {
16117                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16118         } else if (IS_GEN6(dev_priv)) {
16119                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16120         } else if (IS_IVYBRIDGE(dev_priv)) {
16121                 /* FIXME: detect B0+ stepping and use auto training */
16122                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16123         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16124                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16125         }
16126
16127         if (IS_BROADWELL(dev_priv)) {
16128                 dev_priv->display.modeset_commit_cdclk =
16129                         broadwell_modeset_commit_cdclk;
16130                 dev_priv->display.modeset_calc_cdclk =
16131                         broadwell_modeset_calc_cdclk;
16132         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16133                 dev_priv->display.modeset_commit_cdclk =
16134                         valleyview_modeset_commit_cdclk;
16135                 dev_priv->display.modeset_calc_cdclk =
16136                         valleyview_modeset_calc_cdclk;
16137         } else if (IS_GEN9_LP(dev_priv)) {
16138                 dev_priv->display.modeset_commit_cdclk =
16139                         bxt_modeset_commit_cdclk;
16140                 dev_priv->display.modeset_calc_cdclk =
16141                         bxt_modeset_calc_cdclk;
16142         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16143                 dev_priv->display.modeset_commit_cdclk =
16144                         skl_modeset_commit_cdclk;
16145                 dev_priv->display.modeset_calc_cdclk =
16146                         skl_modeset_calc_cdclk;
16147         }
16148
16149         if (dev_priv->info.gen >= 9)
16150                 dev_priv->display.update_crtcs = skl_update_crtcs;
16151         else
16152                 dev_priv->display.update_crtcs = intel_update_crtcs;
16153
16154         switch (INTEL_INFO(dev_priv)->gen) {
16155         case 2:
16156                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16157                 break;
16158
16159         case 3:
16160                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16161                 break;
16162
16163         case 4:
16164         case 5:
16165                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16166                 break;
16167
16168         case 6:
16169                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16170                 break;
16171         case 7:
16172         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16173                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16174                 break;
16175         case 9:
16176                 /* Drop through - unsupported since execlist only. */
16177         default:
16178                 /* Default just returns -ENODEV to indicate unsupported */
16179                 dev_priv->display.queue_flip = intel_default_queue_flip;
16180         }
16181 }
16182
16183 /*
16184  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16185  * resume, or other times.  This quirk makes sure that's the case for
16186  * affected systems.
16187  */
16188 static void quirk_pipea_force(struct drm_device *dev)
16189 {
16190         struct drm_i915_private *dev_priv = to_i915(dev);
16191
16192         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16193         DRM_INFO("applying pipe a force quirk\n");
16194 }
16195
16196 static void quirk_pipeb_force(struct drm_device *dev)
16197 {
16198         struct drm_i915_private *dev_priv = to_i915(dev);
16199
16200         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16201         DRM_INFO("applying pipe b force quirk\n");
16202 }
16203
16204 /*
16205  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16206  */
16207 static void quirk_ssc_force_disable(struct drm_device *dev)
16208 {
16209         struct drm_i915_private *dev_priv = to_i915(dev);
16210         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16211         DRM_INFO("applying lvds SSC disable quirk\n");
16212 }
16213
16214 /*
16215  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16216  * brightness value
16217  */
16218 static void quirk_invert_brightness(struct drm_device *dev)
16219 {
16220         struct drm_i915_private *dev_priv = to_i915(dev);
16221         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16222         DRM_INFO("applying inverted panel brightness quirk\n");
16223 }
16224
16225 /* Some VBT's incorrectly indicate no backlight is present */
16226 static void quirk_backlight_present(struct drm_device *dev)
16227 {
16228         struct drm_i915_private *dev_priv = to_i915(dev);
16229         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16230         DRM_INFO("applying backlight present quirk\n");
16231 }
16232
16233 struct intel_quirk {
16234         int device;
16235         int subsystem_vendor;
16236         int subsystem_device;
16237         void (*hook)(struct drm_device *dev);
16238 };
16239
16240 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16241 struct intel_dmi_quirk {
16242         void (*hook)(struct drm_device *dev);
16243         const struct dmi_system_id (*dmi_id_list)[];
16244 };
16245
16246 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16247 {
16248         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16249         return 1;
16250 }
16251
16252 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16253         {
16254                 .dmi_id_list = &(const struct dmi_system_id[]) {
16255                         {
16256                                 .callback = intel_dmi_reverse_brightness,
16257                                 .ident = "NCR Corporation",
16258                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16259                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
16260                                 },
16261                         },
16262                         { }  /* terminating entry */
16263                 },
16264                 .hook = quirk_invert_brightness,
16265         },
16266 };
16267
16268 static struct intel_quirk intel_quirks[] = {
16269         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16270         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16271
16272         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16273         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16274
16275         /* 830 needs to leave pipe A & dpll A up */
16276         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16277
16278         /* 830 needs to leave pipe B & dpll B up */
16279         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16280
16281         /* Lenovo U160 cannot use SSC on LVDS */
16282         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16283
16284         /* Sony Vaio Y cannot use SSC on LVDS */
16285         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16286
16287         /* Acer Aspire 5734Z must invert backlight brightness */
16288         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16289
16290         /* Acer/eMachines G725 */
16291         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16292
16293         /* Acer/eMachines e725 */
16294         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16295
16296         /* Acer/Packard Bell NCL20 */
16297         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16298
16299         /* Acer Aspire 4736Z */
16300         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16301
16302         /* Acer Aspire 5336 */
16303         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16304
16305         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16306         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16307
16308         /* Acer C720 Chromebook (Core i3 4005U) */
16309         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16310
16311         /* Apple Macbook 2,1 (Core 2 T7400) */
16312         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16313
16314         /* Apple Macbook 4,1 */
16315         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16316
16317         /* Toshiba CB35 Chromebook (Celeron 2955U) */
16318         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16319
16320         /* HP Chromebook 14 (Celeron 2955U) */
16321         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16322
16323         /* Dell Chromebook 11 */
16324         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16325
16326         /* Dell Chromebook 11 (2015 version) */
16327         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16328 };
16329
16330 static void intel_init_quirks(struct drm_device *dev)
16331 {
16332         struct pci_dev *d = dev->pdev;
16333         int i;
16334
16335         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16336                 struct intel_quirk *q = &intel_quirks[i];
16337
16338                 if (d->device == q->device &&
16339                     (d->subsystem_vendor == q->subsystem_vendor ||
16340                      q->subsystem_vendor == PCI_ANY_ID) &&
16341                     (d->subsystem_device == q->subsystem_device ||
16342                      q->subsystem_device == PCI_ANY_ID))
16343                         q->hook(dev);
16344         }
16345         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16346                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16347                         intel_dmi_quirks[i].hook(dev);
16348         }
16349 }
16350
16351 /* Disable the VGA plane that we never use */
16352 static void i915_disable_vga(struct drm_i915_private *dev_priv)
16353 {
16354         struct pci_dev *pdev = dev_priv->drm.pdev;
16355         u8 sr1;
16356         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16357
16358         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16359         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16360         outb(SR01, VGA_SR_INDEX);
16361         sr1 = inb(VGA_SR_DATA);
16362         outb(sr1 | 1<<5, VGA_SR_DATA);
16363         vga_put(pdev, VGA_RSRC_LEGACY_IO);
16364         udelay(300);
16365
16366         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16367         POSTING_READ(vga_reg);
16368 }
16369
16370 void intel_modeset_init_hw(struct drm_device *dev)
16371 {
16372         struct drm_i915_private *dev_priv = to_i915(dev);
16373
16374         intel_update_cdclk(dev_priv);
16375
16376         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16377
16378         intel_init_clock_gating(dev_priv);
16379 }
16380
16381 /*
16382  * Calculate what we think the watermarks should be for the state we've read
16383  * out of the hardware and then immediately program those watermarks so that
16384  * we ensure the hardware settings match our internal state.
16385  *
16386  * We can calculate what we think WM's should be by creating a duplicate of the
16387  * current state (which was constructed during hardware readout) and running it
16388  * through the atomic check code to calculate new watermark values in the
16389  * state object.
16390  */
16391 static void sanitize_watermarks(struct drm_device *dev)
16392 {
16393         struct drm_i915_private *dev_priv = to_i915(dev);
16394         struct drm_atomic_state *state;
16395         struct intel_atomic_state *intel_state;
16396         struct drm_crtc *crtc;
16397         struct drm_crtc_state *cstate;
16398         struct drm_modeset_acquire_ctx ctx;
16399         int ret;
16400         int i;
16401
16402         /* Only supported on platforms that use atomic watermark design */
16403         if (!dev_priv->display.optimize_watermarks)
16404                 return;
16405
16406         /*
16407          * We need to hold connection_mutex before calling duplicate_state so
16408          * that the connector loop is protected.
16409          */
16410         drm_modeset_acquire_init(&ctx, 0);
16411 retry:
16412         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16413         if (ret == -EDEADLK) {
16414                 drm_modeset_backoff(&ctx);
16415                 goto retry;
16416         } else if (WARN_ON(ret)) {
16417                 goto fail;
16418         }
16419
16420         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16421         if (WARN_ON(IS_ERR(state)))
16422                 goto fail;
16423
16424         intel_state = to_intel_atomic_state(state);
16425
16426         /*
16427          * Hardware readout is the only time we don't want to calculate
16428          * intermediate watermarks (since we don't trust the current
16429          * watermarks).
16430          */
16431         intel_state->skip_intermediate_wm = true;
16432
16433         ret = intel_atomic_check(dev, state);
16434         if (ret) {
16435                 /*
16436                  * If we fail here, it means that the hardware appears to be
16437                  * programmed in a way that shouldn't be possible, given our
16438                  * understanding of watermark requirements.  This might mean a
16439                  * mistake in the hardware readout code or a mistake in the
16440                  * watermark calculations for a given platform.  Raise a WARN
16441                  * so that this is noticeable.
16442                  *
16443                  * If this actually happens, we'll have to just leave the
16444                  * BIOS-programmed watermarks untouched and hope for the best.
16445                  */
16446                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16447                 goto put_state;
16448         }
16449
16450         /* Write calculated watermark values back */
16451         for_each_crtc_in_state(state, crtc, cstate, i) {
16452                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16453
16454                 cs->wm.need_postvbl_update = true;
16455                 dev_priv->display.optimize_watermarks(intel_state, cs);
16456         }
16457
16458 put_state:
16459         drm_atomic_state_put(state);
16460 fail:
16461         drm_modeset_drop_locks(&ctx);
16462         drm_modeset_acquire_fini(&ctx);
16463 }
16464
16465 int intel_modeset_init(struct drm_device *dev)
16466 {
16467         struct drm_i915_private *dev_priv = to_i915(dev);
16468         struct i915_ggtt *ggtt = &dev_priv->ggtt;
16469         enum pipe pipe;
16470         struct intel_crtc *crtc;
16471
16472         drm_mode_config_init(dev);
16473
16474         dev->mode_config.min_width = 0;
16475         dev->mode_config.min_height = 0;
16476
16477         dev->mode_config.preferred_depth = 24;
16478         dev->mode_config.prefer_shadow = 1;
16479
16480         dev->mode_config.allow_fb_modifiers = true;
16481
16482         dev->mode_config.funcs = &intel_mode_funcs;
16483
16484         intel_init_quirks(dev);
16485
16486         intel_init_pm(dev_priv);
16487
16488         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16489                 return 0;
16490
16491         /*
16492          * There may be no VBT; and if the BIOS enabled SSC we can
16493          * just keep using it to avoid unnecessary flicker.  Whereas if the
16494          * BIOS isn't using it, don't assume it will work even if the VBT
16495          * indicates as much.
16496          */
16497         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
16498                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16499                                             DREF_SSC1_ENABLE);
16500
16501                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16502                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16503                                      bios_lvds_use_ssc ? "en" : "dis",
16504                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16505                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16506                 }
16507         }
16508
16509         if (IS_GEN2(dev_priv)) {
16510                 dev->mode_config.max_width = 2048;
16511                 dev->mode_config.max_height = 2048;
16512         } else if (IS_GEN3(dev_priv)) {
16513                 dev->mode_config.max_width = 4096;
16514                 dev->mode_config.max_height = 4096;
16515         } else {
16516                 dev->mode_config.max_width = 8192;
16517                 dev->mode_config.max_height = 8192;
16518         }
16519
16520         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16521                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
16522                 dev->mode_config.cursor_height = 1023;
16523         } else if (IS_GEN2(dev_priv)) {
16524                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16525                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16526         } else {
16527                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16528                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16529         }
16530
16531         dev->mode_config.fb_base = ggtt->mappable_base;
16532
16533         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16534                       INTEL_INFO(dev_priv)->num_pipes,
16535                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
16536
16537         for_each_pipe(dev_priv, pipe) {
16538                 int ret;
16539
16540                 ret = intel_crtc_init(dev_priv, pipe);
16541                 if (ret) {
16542                         drm_mode_config_cleanup(dev);
16543                         return ret;
16544                 }
16545         }
16546
16547         intel_update_czclk(dev_priv);
16548         intel_update_cdclk(dev_priv);
16549         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16550
16551         intel_shared_dpll_init(dev);
16552
16553         if (dev_priv->max_cdclk_freq == 0)
16554                 intel_update_max_cdclk(dev_priv);
16555
16556         /* Just disable it once at startup */
16557         i915_disable_vga(dev_priv);
16558         intel_setup_outputs(dev_priv);
16559
16560         drm_modeset_lock_all(dev);
16561         intel_modeset_setup_hw_state(dev);
16562         drm_modeset_unlock_all(dev);
16563
16564         for_each_intel_crtc(dev, crtc) {
16565                 struct intel_initial_plane_config plane_config = {};
16566
16567                 if (!crtc->active)
16568                         continue;
16569
16570                 /*
16571                  * Note that reserving the BIOS fb up front prevents us
16572                  * from stuffing other stolen allocations like the ring
16573                  * on top.  This prevents some ugliness at boot time, and
16574                  * can even allow for smooth boot transitions if the BIOS
16575                  * fb is large enough for the active pipe configuration.
16576                  */
16577                 dev_priv->display.get_initial_plane_config(crtc,
16578                                                            &plane_config);
16579
16580                 /*
16581                  * If the fb is shared between multiple heads, we'll
16582                  * just get the first one.
16583                  */
16584                 intel_find_initial_plane_obj(crtc, &plane_config);
16585         }
16586
16587         /*
16588          * Make sure hardware watermarks really match the state we read out.
16589          * Note that we need to do this after reconstructing the BIOS fb's
16590          * since the watermark calculation done here will use pstate->fb.
16591          */
16592         sanitize_watermarks(dev);
16593
16594         return 0;
16595 }
16596
16597 static void intel_enable_pipe_a(struct drm_device *dev)
16598 {
16599         struct intel_connector *connector;
16600         struct drm_connector *crt = NULL;
16601         struct intel_load_detect_pipe load_detect_temp;
16602         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16603
16604         /* We can't just switch on the pipe A, we need to set things up with a
16605          * proper mode and output configuration. As a gross hack, enable pipe A
16606          * by enabling the load detect pipe once. */
16607         for_each_intel_connector(dev, connector) {
16608                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16609                         crt = &connector->base;
16610                         break;
16611                 }
16612         }
16613
16614         if (!crt)
16615                 return;
16616
16617         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16618                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16619 }
16620
16621 static bool
16622 intel_check_plane_mapping(struct intel_crtc *crtc)
16623 {
16624         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
16625         u32 val;
16626
16627         if (INTEL_INFO(dev_priv)->num_pipes == 1)
16628                 return true;
16629
16630         val = I915_READ(DSPCNTR(!crtc->plane));
16631
16632         if ((val & DISPLAY_PLANE_ENABLE) &&
16633             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16634                 return false;
16635
16636         return true;
16637 }
16638
16639 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16640 {
16641         struct drm_device *dev = crtc->base.dev;
16642         struct intel_encoder *encoder;
16643
16644         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16645                 return true;
16646
16647         return false;
16648 }
16649
16650 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16651 {
16652         struct drm_device *dev = encoder->base.dev;
16653         struct intel_connector *connector;
16654
16655         for_each_connector_on_encoder(dev, &encoder->base, connector)
16656                 return connector;
16657
16658         return NULL;
16659 }
16660
16661 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16662                               enum transcoder pch_transcoder)
16663 {
16664         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16665                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16666 }
16667
16668 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16669 {
16670         struct drm_device *dev = crtc->base.dev;
16671         struct drm_i915_private *dev_priv = to_i915(dev);
16672         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16673
16674         /* Clear any frame start delays used for debugging left by the BIOS */
16675         if (!transcoder_is_dsi(cpu_transcoder)) {
16676                 i915_reg_t reg = PIPECONF(cpu_transcoder);
16677
16678                 I915_WRITE(reg,
16679                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16680         }
16681
16682         /* restore vblank interrupts to correct state */
16683         drm_crtc_vblank_reset(&crtc->base);
16684         if (crtc->active) {
16685                 struct intel_plane *plane;
16686
16687                 drm_crtc_vblank_on(&crtc->base);
16688
16689                 /* Disable everything but the primary plane */
16690                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16691                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16692                                 continue;
16693
16694                         plane->disable_plane(&plane->base, &crtc->base);
16695                 }
16696         }
16697
16698         /* We need to sanitize the plane -> pipe mapping first because this will
16699          * disable the crtc (and hence change the state) if it is wrong. Note
16700          * that gen4+ has a fixed plane -> pipe mapping.  */
16701         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
16702                 bool plane;
16703
16704                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16705                               crtc->base.base.id, crtc->base.name);
16706
16707                 /* Pipe has the wrong plane attached and the plane is active.
16708                  * Temporarily change the plane mapping and disable everything
16709                  * ...  */
16710                 plane = crtc->plane;
16711                 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16712                 crtc->plane = !plane;
16713                 intel_crtc_disable_noatomic(&crtc->base);
16714                 crtc->plane = plane;
16715         }
16716
16717         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16718             crtc->pipe == PIPE_A && !crtc->active) {
16719                 /* BIOS forgot to enable pipe A, this mostly happens after
16720                  * resume. Force-enable the pipe to fix this, the update_dpms
16721                  * call below we restore the pipe to the right state, but leave
16722                  * the required bits on. */
16723                 intel_enable_pipe_a(dev);
16724         }
16725
16726         /* Adjust the state of the output pipe according to whether we
16727          * have active connectors/encoders. */
16728         if (crtc->active && !intel_crtc_has_encoders(crtc))
16729                 intel_crtc_disable_noatomic(&crtc->base);
16730
16731         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
16732                 /*
16733                  * We start out with underrun reporting disabled to avoid races.
16734                  * For correct bookkeeping mark this on active crtcs.
16735                  *
16736                  * Also on gmch platforms we dont have any hardware bits to
16737                  * disable the underrun reporting. Which means we need to start
16738                  * out with underrun reporting disabled also on inactive pipes,
16739                  * since otherwise we'll complain about the garbage we read when
16740                  * e.g. coming up after runtime pm.
16741                  *
16742                  * No protection against concurrent access is required - at
16743                  * worst a fifo underrun happens which also sets this to false.
16744                  */
16745                 crtc->cpu_fifo_underrun_disabled = true;
16746                 /*
16747                  * We track the PCH trancoder underrun reporting state
16748                  * within the crtc. With crtc for pipe A housing the underrun
16749                  * reporting state for PCH transcoder A, crtc for pipe B housing
16750                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16751                  * and marking underrun reporting as disabled for the non-existing
16752                  * PCH transcoders B and C would prevent enabling the south
16753                  * error interrupt (see cpt_can_enable_serr_int()).
16754                  */
16755                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16756                         crtc->pch_fifo_underrun_disabled = true;
16757         }
16758 }
16759
16760 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16761 {
16762         struct intel_connector *connector;
16763
16764         /* We need to check both for a crtc link (meaning that the
16765          * encoder is active and trying to read from a pipe) and the
16766          * pipe itself being active. */
16767         bool has_active_crtc = encoder->base.crtc &&
16768                 to_intel_crtc(encoder->base.crtc)->active;
16769
16770         connector = intel_encoder_find_connector(encoder);
16771         if (connector && !has_active_crtc) {
16772                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16773                               encoder->base.base.id,
16774                               encoder->base.name);
16775
16776                 /* Connector is active, but has no active pipe. This is
16777                  * fallout from our resume register restoring. Disable
16778                  * the encoder manually again. */
16779                 if (encoder->base.crtc) {
16780                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16781
16782                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16783                                       encoder->base.base.id,
16784                                       encoder->base.name);
16785                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16786                         if (encoder->post_disable)
16787                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16788                 }
16789                 encoder->base.crtc = NULL;
16790
16791                 /* Inconsistent output/port/pipe state happens presumably due to
16792                  * a bug in one of the get_hw_state functions. Or someplace else
16793                  * in our code, like the register restore mess on resume. Clamp
16794                  * things to off as a safer default. */
16795
16796                 connector->base.dpms = DRM_MODE_DPMS_OFF;
16797                 connector->base.encoder = NULL;
16798         }
16799         /* Enabled encoders without active connectors will be fixed in
16800          * the crtc fixup. */
16801 }
16802
16803 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
16804 {
16805         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16806
16807         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16808                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16809                 i915_disable_vga(dev_priv);
16810         }
16811 }
16812
16813 void i915_redisable_vga(struct drm_i915_private *dev_priv)
16814 {
16815         /* This function can be called both from intel_modeset_setup_hw_state or
16816          * at a very early point in our resume sequence, where the power well
16817          * structures are not yet restored. Since this function is at a very
16818          * paranoid "someone might have enabled VGA while we were not looking"
16819          * level, just check if the power well is enabled instead of trying to
16820          * follow the "don't touch the power well if we don't need it" policy
16821          * the rest of the driver uses. */
16822         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16823                 return;
16824
16825         i915_redisable_vga_power_on(dev_priv);
16826
16827         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16828 }
16829
16830 static bool primary_get_hw_state(struct intel_plane *plane)
16831 {
16832         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16833
16834         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16835 }
16836
16837 /* FIXME read out full plane state for all planes */
16838 static void readout_plane_state(struct intel_crtc *crtc)
16839 {
16840         struct drm_plane *primary = crtc->base.primary;
16841         struct intel_plane_state *plane_state =
16842                 to_intel_plane_state(primary->state);
16843
16844         plane_state->base.visible = crtc->active &&
16845                 primary_get_hw_state(to_intel_plane(primary));
16846
16847         if (plane_state->base.visible)
16848                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16849 }
16850
16851 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16852 {
16853         struct drm_i915_private *dev_priv = to_i915(dev);
16854         enum pipe pipe;
16855         struct intel_crtc *crtc;
16856         struct intel_encoder *encoder;
16857         struct intel_connector *connector;
16858         int i;
16859
16860         dev_priv->active_crtcs = 0;
16861
16862         for_each_intel_crtc(dev, crtc) {
16863                 struct intel_crtc_state *crtc_state = crtc->config;
16864
16865                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16866                 memset(crtc_state, 0, sizeof(*crtc_state));
16867                 crtc_state->base.crtc = &crtc->base;
16868
16869                 crtc_state->base.active = crtc_state->base.enable =
16870                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16871
16872                 crtc->base.enabled = crtc_state->base.enable;
16873                 crtc->active = crtc_state->base.active;
16874
16875                 if (crtc_state->base.active)
16876                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16877
16878                 readout_plane_state(crtc);
16879
16880                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16881                               crtc->base.base.id, crtc->base.name,
16882                               enableddisabled(crtc->active));
16883         }
16884
16885         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16886                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16887
16888                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16889                                                   &pll->state.hw_state);
16890                 pll->state.crtc_mask = 0;
16891                 for_each_intel_crtc(dev, crtc) {
16892                         if (crtc->active && crtc->config->shared_dpll == pll)
16893                                 pll->state.crtc_mask |= 1 << crtc->pipe;
16894                 }
16895                 pll->active_mask = pll->state.crtc_mask;
16896
16897                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16898                               pll->name, pll->state.crtc_mask, pll->on);
16899         }
16900
16901         for_each_intel_encoder(dev, encoder) {
16902                 pipe = 0;
16903
16904                 if (encoder->get_hw_state(encoder, &pipe)) {
16905                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16906
16907                         encoder->base.crtc = &crtc->base;
16908                         crtc->config->output_types |= 1 << encoder->type;
16909                         encoder->get_config(encoder, crtc->config);
16910                 } else {
16911                         encoder->base.crtc = NULL;
16912                 }
16913
16914                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16915                               encoder->base.base.id, encoder->base.name,
16916                               enableddisabled(encoder->base.crtc),
16917                               pipe_name(pipe));
16918         }
16919
16920         for_each_intel_connector(dev, connector) {
16921                 if (connector->get_hw_state(connector)) {
16922                         connector->base.dpms = DRM_MODE_DPMS_ON;
16923
16924                         encoder = connector->encoder;
16925                         connector->base.encoder = &encoder->base;
16926
16927                         if (encoder->base.crtc &&
16928                             encoder->base.crtc->state->active) {
16929                                 /*
16930                                  * This has to be done during hardware readout
16931                                  * because anything calling .crtc_disable may
16932                                  * rely on the connector_mask being accurate.
16933                                  */
16934                                 encoder->base.crtc->state->connector_mask |=
16935                                         1 << drm_connector_index(&connector->base);
16936                                 encoder->base.crtc->state->encoder_mask |=
16937                                         1 << drm_encoder_index(&encoder->base);
16938                         }
16939
16940                 } else {
16941                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16942                         connector->base.encoder = NULL;
16943                 }
16944                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16945                               connector->base.base.id, connector->base.name,
16946                               enableddisabled(connector->base.encoder));
16947         }
16948
16949         for_each_intel_crtc(dev, crtc) {
16950                 int pixclk = 0;
16951
16952                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16953
16954                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16955                 if (crtc->base.state->active) {
16956                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16957                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16958                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16959
16960                         /*
16961                          * The initial mode needs to be set in order to keep
16962                          * the atomic core happy. It wants a valid mode if the
16963                          * crtc's enabled, so we do the above call.
16964                          *
16965                          * At this point some state updated by the connectors
16966                          * in their ->detect() callback has not run yet, so
16967                          * no recalculation can be done yet.
16968                          *
16969                          * Even if we could do a recalculation and modeset
16970                          * right now it would cause a double modeset if
16971                          * fbdev or userspace chooses a different initial mode.
16972                          *
16973                          * If that happens, someone indicated they wanted a
16974                          * mode change, which means it's safe to do a full
16975                          * recalculation.
16976                          */
16977                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16978
16979                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16980                                 pixclk = ilk_pipe_pixel_rate(crtc->config);
16981                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16982                                 pixclk = crtc->config->base.adjusted_mode.crtc_clock;
16983                         else
16984                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16985
16986                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16987                         if (IS_BROADWELL(dev_priv) && crtc->config->ips_enabled)
16988                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16989
16990                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16991                         update_scanline_offset(crtc);
16992                 }
16993
16994                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16995
16996                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16997         }
16998 }
16999
17000 /* Scan out the current hw modeset state,
17001  * and sanitizes it to the current state
17002  */
17003 static void
17004 intel_modeset_setup_hw_state(struct drm_device *dev)
17005 {
17006         struct drm_i915_private *dev_priv = to_i915(dev);
17007         enum pipe pipe;
17008         struct intel_crtc *crtc;
17009         struct intel_encoder *encoder;
17010         int i;
17011
17012         intel_modeset_readout_hw_state(dev);
17013
17014         /* HW state is read out, now we need to sanitize this mess. */
17015         for_each_intel_encoder(dev, encoder) {
17016                 intel_sanitize_encoder(encoder);
17017         }
17018
17019         for_each_pipe(dev_priv, pipe) {
17020                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17021
17022                 intel_sanitize_crtc(crtc);
17023                 intel_dump_pipe_config(crtc, crtc->config,
17024                                        "[setup_hw_state]");
17025         }
17026
17027         intel_modeset_update_connector_atomic_state(dev);
17028
17029         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17030                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17031
17032                 if (!pll->on || pll->active_mask)
17033                         continue;
17034
17035                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
17036
17037                 pll->funcs.disable(dev_priv, pll);
17038                 pll->on = false;
17039         }
17040
17041         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17042                 vlv_wm_get_hw_state(dev);
17043         else if (IS_GEN9(dev_priv))
17044                 skl_wm_get_hw_state(dev);
17045         else if (HAS_PCH_SPLIT(dev_priv))
17046                 ilk_wm_get_hw_state(dev);
17047
17048         for_each_intel_crtc(dev, crtc) {
17049                 unsigned long put_domains;
17050
17051                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
17052                 if (WARN_ON(put_domains))
17053                         modeset_put_power_domains(dev_priv, put_domains);
17054         }
17055         intel_display_set_init_power(dev_priv, false);
17056
17057         intel_fbc_init_pipe_state(dev_priv);
17058 }
17059
17060 void intel_display_resume(struct drm_device *dev)
17061 {
17062         struct drm_i915_private *dev_priv = to_i915(dev);
17063         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17064         struct drm_modeset_acquire_ctx ctx;
17065         int ret;
17066
17067         dev_priv->modeset_restore_state = NULL;
17068         if (state)
17069                 state->acquire_ctx = &ctx;
17070
17071         /*
17072          * This is a cludge because with real atomic modeset mode_config.mutex
17073          * won't be taken. Unfortunately some probed state like
17074          * audio_codec_enable is still protected by mode_config.mutex, so lock
17075          * it here for now.
17076          */
17077         mutex_lock(&dev->mode_config.mutex);
17078         drm_modeset_acquire_init(&ctx, 0);
17079
17080         while (1) {
17081                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17082                 if (ret != -EDEADLK)
17083                         break;
17084
17085                 drm_modeset_backoff(&ctx);
17086         }
17087
17088         if (!ret)
17089                 ret = __intel_display_resume(dev, state);
17090
17091         drm_modeset_drop_locks(&ctx);
17092         drm_modeset_acquire_fini(&ctx);
17093         mutex_unlock(&dev->mode_config.mutex);
17094
17095         if (ret)
17096                 DRM_ERROR("Restoring old state failed with %i\n", ret);
17097         drm_atomic_state_put(state);
17098 }
17099
17100 void intel_modeset_gem_init(struct drm_device *dev)
17101 {
17102         struct drm_i915_private *dev_priv = to_i915(dev);
17103         struct drm_crtc *c;
17104         struct drm_i915_gem_object *obj;
17105
17106         intel_init_gt_powersave(dev_priv);
17107
17108         intel_modeset_init_hw(dev);
17109
17110         intel_setup_overlay(dev_priv);
17111
17112         /*
17113          * Make sure any fbs we allocated at startup are properly
17114          * pinned & fenced.  When we do the allocation it's too early
17115          * for this.
17116          */
17117         for_each_crtc(dev, c) {
17118                 struct i915_vma *vma;
17119
17120                 obj = intel_fb_obj(c->primary->fb);
17121                 if (obj == NULL)
17122                         continue;
17123
17124                 mutex_lock(&dev->struct_mutex);
17125                 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
17126                                                  c->primary->state->rotation);
17127                 mutex_unlock(&dev->struct_mutex);
17128                 if (IS_ERR(vma)) {
17129                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
17130                                   to_intel_crtc(c)->pipe);
17131                         drm_framebuffer_unreference(c->primary->fb);
17132                         c->primary->fb = NULL;
17133                         c->primary->crtc = c->primary->state->crtc = NULL;
17134                         update_state_fb(c->primary);
17135                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
17136                 }
17137         }
17138 }
17139
17140 int intel_connector_register(struct drm_connector *connector)
17141 {
17142         struct intel_connector *intel_connector = to_intel_connector(connector);
17143         int ret;
17144
17145         ret = intel_backlight_device_register(intel_connector);
17146         if (ret)
17147                 goto err;
17148
17149         return 0;
17150
17151 err:
17152         return ret;
17153 }
17154
17155 void intel_connector_unregister(struct drm_connector *connector)
17156 {
17157         struct intel_connector *intel_connector = to_intel_connector(connector);
17158
17159         intel_backlight_device_unregister(intel_connector);
17160         intel_panel_destroy_backlight(connector);
17161 }
17162
17163 void intel_modeset_cleanup(struct drm_device *dev)
17164 {
17165         struct drm_i915_private *dev_priv = to_i915(dev);
17166
17167         intel_disable_gt_powersave(dev_priv);
17168
17169         /*
17170          * Interrupts and polling as the first thing to avoid creating havoc.
17171          * Too much stuff here (turning of connectors, ...) would
17172          * experience fancy races otherwise.
17173          */
17174         intel_irq_uninstall(dev_priv);
17175
17176         /*
17177          * Due to the hpd irq storm handling the hotplug work can re-arm the
17178          * poll handlers. Hence disable polling after hpd handling is shut down.
17179          */
17180         drm_kms_helper_poll_fini(dev);
17181
17182         intel_unregister_dsm_handler();
17183
17184         intel_fbc_global_disable(dev_priv);
17185
17186         /* flush any delayed tasks or pending work */
17187         flush_scheduled_work();
17188
17189         drm_mode_config_cleanup(dev);
17190
17191         intel_cleanup_overlay(dev_priv);
17192
17193         intel_cleanup_gt_powersave(dev_priv);
17194
17195         intel_teardown_gmbus(dev_priv);
17196 }
17197
17198 void intel_connector_attach_encoder(struct intel_connector *connector,
17199                                     struct intel_encoder *encoder)
17200 {
17201         connector->encoder = encoder;
17202         drm_mode_connector_attach_encoder(&connector->base,
17203                                           &encoder->base);
17204 }
17205
17206 /*
17207  * set vga decode state - true == enable VGA decode
17208  */
17209 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
17210 {
17211         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17212         u16 gmch_ctrl;
17213
17214         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17215                 DRM_ERROR("failed to read control word\n");
17216                 return -EIO;
17217         }
17218
17219         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17220                 return 0;
17221
17222         if (state)
17223                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17224         else
17225                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17226
17227         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17228                 DRM_ERROR("failed to write control word\n");
17229                 return -EIO;
17230         }
17231
17232         return 0;
17233 }
17234
17235 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17236
17237 struct intel_display_error_state {
17238
17239         u32 power_well_driver;
17240
17241         int num_transcoders;
17242
17243         struct intel_cursor_error_state {
17244                 u32 control;
17245                 u32 position;
17246                 u32 base;
17247                 u32 size;
17248         } cursor[I915_MAX_PIPES];
17249
17250         struct intel_pipe_error_state {
17251                 bool power_domain_on;
17252                 u32 source;
17253                 u32 stat;
17254         } pipe[I915_MAX_PIPES];
17255
17256         struct intel_plane_error_state {
17257                 u32 control;
17258                 u32 stride;
17259                 u32 size;
17260                 u32 pos;
17261                 u32 addr;
17262                 u32 surface;
17263                 u32 tile_offset;
17264         } plane[I915_MAX_PIPES];
17265
17266         struct intel_transcoder_error_state {
17267                 bool power_domain_on;
17268                 enum transcoder cpu_transcoder;
17269
17270                 u32 conf;
17271
17272                 u32 htotal;
17273                 u32 hblank;
17274                 u32 hsync;
17275                 u32 vtotal;
17276                 u32 vblank;
17277                 u32 vsync;
17278         } transcoder[4];
17279 };
17280
17281 struct intel_display_error_state *
17282 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17283 {
17284         struct intel_display_error_state *error;
17285         int transcoders[] = {
17286                 TRANSCODER_A,
17287                 TRANSCODER_B,
17288                 TRANSCODER_C,
17289                 TRANSCODER_EDP,
17290         };
17291         int i;
17292
17293         if (INTEL_INFO(dev_priv)->num_pipes == 0)
17294                 return NULL;
17295
17296         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17297         if (error == NULL)
17298                 return NULL;
17299
17300         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17301                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17302
17303         for_each_pipe(dev_priv, i) {
17304                 error->pipe[i].power_domain_on =
17305                         __intel_display_power_is_enabled(dev_priv,
17306                                                          POWER_DOMAIN_PIPE(i));
17307                 if (!error->pipe[i].power_domain_on)
17308                         continue;
17309
17310                 error->cursor[i].control = I915_READ(CURCNTR(i));
17311                 error->cursor[i].position = I915_READ(CURPOS(i));
17312                 error->cursor[i].base = I915_READ(CURBASE(i));
17313
17314                 error->plane[i].control = I915_READ(DSPCNTR(i));
17315                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17316                 if (INTEL_GEN(dev_priv) <= 3) {
17317                         error->plane[i].size = I915_READ(DSPSIZE(i));
17318                         error->plane[i].pos = I915_READ(DSPPOS(i));
17319                 }
17320                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17321                         error->plane[i].addr = I915_READ(DSPADDR(i));
17322                 if (INTEL_GEN(dev_priv) >= 4) {
17323                         error->plane[i].surface = I915_READ(DSPSURF(i));
17324                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17325                 }
17326
17327                 error->pipe[i].source = I915_READ(PIPESRC(i));
17328
17329                 if (HAS_GMCH_DISPLAY(dev_priv))
17330                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17331         }
17332
17333         /* Note: this does not include DSI transcoders. */
17334         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17335         if (HAS_DDI(dev_priv))
17336                 error->num_transcoders++; /* Account for eDP. */
17337
17338         for (i = 0; i < error->num_transcoders; i++) {
17339                 enum transcoder cpu_transcoder = transcoders[i];
17340
17341                 error->transcoder[i].power_domain_on =
17342                         __intel_display_power_is_enabled(dev_priv,
17343                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17344                 if (!error->transcoder[i].power_domain_on)
17345                         continue;
17346
17347                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17348
17349                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17350                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17351                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17352                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17353                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17354                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17355                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17356         }
17357
17358         return error;
17359 }
17360
17361 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17362
17363 void
17364 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17365                                 struct drm_i915_private *dev_priv,
17366                                 struct intel_display_error_state *error)
17367 {
17368         int i;
17369
17370         if (!error)
17371                 return;
17372
17373         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
17374         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17375                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17376                            error->power_well_driver);
17377         for_each_pipe(dev_priv, i) {
17378                 err_printf(m, "Pipe [%d]:\n", i);
17379                 err_printf(m, "  Power: %s\n",
17380                            onoff(error->pipe[i].power_domain_on));
17381                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17382                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17383
17384                 err_printf(m, "Plane [%d]:\n", i);
17385                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17386                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17387                 if (INTEL_GEN(dev_priv) <= 3) {
17388                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17389                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17390                 }
17391                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17392                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17393                 if (INTEL_GEN(dev_priv) >= 4) {
17394                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17395                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17396                 }
17397
17398                 err_printf(m, "Cursor [%d]:\n", i);
17399                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17400                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17401                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17402         }
17403
17404         for (i = 0; i < error->num_transcoders; i++) {
17405                 err_printf(m, "CPU transcoder: %s\n",
17406                            transcoder_name(error->transcoder[i].cpu_transcoder));
17407                 err_printf(m, "  Power: %s\n",
17408                            onoff(error->transcoder[i].power_domain_on));
17409                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17410                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17411                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17412                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17413                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17414                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17415                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17416         }
17417 }
17418
17419 #endif