drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  45         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  46
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  51                                 struct intel_crtc_config *pipe_config);
  52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  53                                    struct intel_crtc_config *pipe_config);
  54
  55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  56                           int x, int y, struct drm_framebuffer *old_fb);
  57 static int intel_framebuffer_init(struct drm_device *dev,
  58                                   struct intel_framebuffer *ifb,
  59                                   struct drm_mode_fb_cmd2 *mode_cmd,
  60                                   struct drm_i915_gem_object *obj);
  61 static void intel_dp_set_m_n(struct intel_crtc *crtc);
  62 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  63 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  64 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  65                                          struct intel_link_m_n *m_n);
  66 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  67 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  68 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  69 static void vlv_prepare_pll(struct intel_crtc *crtc);
  70
  71 typedef struct {
  72         int     min, max;
  73 } intel_range_t;
  74
  75 typedef struct {
  76         int     dot_limit;
  77         int     p2_slow, p2_fast;
  78 } intel_p2_t;
  79
  80 typedef struct intel_limit intel_limit_t;
  81 struct intel_limit {
  82         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  83         intel_p2_t          p2;
  84 };
  85
  86 int
  87 intel_pch_rawclk(struct drm_device *dev)
  88 {
  89         struct drm_i915_private *dev_priv = dev->dev_private;
  90
  91         WARN_ON(!HAS_PCH_SPLIT(dev));
  92
  93         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  94 }
  95
  96 static inline u32 /* units of 100MHz */
  97 intel_fdi_link_freq(struct drm_device *dev)
  98 {
  99         if (IS_GEN5(dev)) {
 100                 struct drm_i915_private *dev_priv = dev->dev_private;
 101                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 102         } else
 103                 return 27;
 104 }
 105
 106 static const intel_limit_t intel_limits_i8xx_dac = {
 107         .dot = { .min = 25000, .max = 350000 },
 108         .vco = { .min = 908000, .max = 1512000 },
 109         .n = { .min = 2, .max = 16 },
 110         .m = { .min = 96, .max = 140 },
 111         .m1 = { .min = 18, .max = 26 },
 112         .m2 = { .min = 6, .max = 16 },
 113         .p = { .min = 4, .max = 128 },
 114         .p1 = { .min = 2, .max = 33 },
 115         .p2 = { .dot_limit = 165000,
 116                 .p2_slow = 4, .p2_fast = 2 },
 117 };
 118
 119 static const intel_limit_t intel_limits_i8xx_dvo = {
 120         .dot = { .min = 25000, .max = 350000 },
 121         .vco = { .min = 908000, .max = 1512000 },
 122         .n = { .min = 2, .max = 16 },
 123         .m = { .min = 96, .max = 140 },
 124         .m1 = { .min = 18, .max = 26 },
 125         .m2 = { .min = 6, .max = 16 },
 126         .p = { .min = 4, .max = 128 },
 127         .p1 = { .min = 2, .max = 33 },
 128         .p2 = { .dot_limit = 165000,
 129                 .p2_slow = 4, .p2_fast = 4 },
 130 };
 131
 132 static const intel_limit_t intel_limits_i8xx_lvds = {
 133         .dot = { .min = 25000, .max = 350000 },
 134         .vco = { .min = 908000, .max = 1512000 },
 135         .n = { .min = 2, .max = 16 },
 136         .m = { .min = 96, .max = 140 },
 137         .m1 = { .min = 18, .max = 26 },
 138         .m2 = { .min = 6, .max = 16 },
 139         .p = { .min = 4, .max = 128 },
 140         .p1 = { .min = 1, .max = 6 },
 141         .p2 = { .dot_limit = 165000,
 142                 .p2_slow = 14, .p2_fast = 7 },
 143 };
 144
 145 static const intel_limit_t intel_limits_i9xx_sdvo = {
 146         .dot = { .min = 20000, .max = 400000 },
 147         .vco = { .min = 1400000, .max = 2800000 },
 148         .n = { .min = 1, .max = 6 },
 149         .m = { .min = 70, .max = 120 },
 150         .m1 = { .min = 8, .max = 18 },
 151         .m2 = { .min = 3, .max = 7 },
 152         .p = { .min = 5, .max = 80 },
 153         .p1 = { .min = 1, .max = 8 },
 154         .p2 = { .dot_limit = 200000,
 155                 .p2_slow = 10, .p2_fast = 5 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 8, .max = 18 },
 164         .m2 = { .min = 3, .max = 7 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169 };
 170
 171
 172 static const intel_limit_t intel_limits_g4x_sdvo = {
 173         .dot = { .min = 25000, .max = 270000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 17, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 10, .max = 30 },
 180         .p1 = { .min = 1, .max = 3},
 181         .p2 = { .dot_limit = 270000,
 182                 .p2_slow = 10,
 183                 .p2_fast = 10
 184         },
 185 };
 186
 187 static const intel_limit_t intel_limits_g4x_hdmi = {
 188         .dot = { .min = 22000, .max = 400000 },
 189         .vco = { .min = 1750000, .max = 3500000},
 190         .n = { .min = 1, .max = 4 },
 191         .m = { .min = 104, .max = 138 },
 192         .m1 = { .min = 16, .max = 23 },
 193         .m2 = { .min = 5, .max = 11 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8},
 196         .p2 = { .dot_limit = 165000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 201         .dot = { .min = 20000, .max = 115000 },
 202         .vco = { .min = 1750000, .max = 3500000 },
 203         .n = { .min = 1, .max = 3 },
 204         .m = { .min = 104, .max = 138 },
 205         .m1 = { .min = 17, .max = 23 },
 206         .m2 = { .min = 5, .max = 11 },
 207         .p = { .min = 28, .max = 112 },
 208         .p1 = { .min = 2, .max = 8 },
 209         .p2 = { .dot_limit = 0,
 210                 .p2_slow = 14, .p2_fast = 14
 211         },
 212 };
 213
 214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 215         .dot = { .min = 80000, .max = 224000 },
 216         .vco = { .min = 1750000, .max = 3500000 },
 217         .n = { .min = 1, .max = 3 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 14, .max = 42 },
 222         .p1 = { .min = 2, .max = 6 },
 223         .p2 = { .dot_limit = 0,
 224                 .p2_slow = 7, .p2_fast = 7
 225         },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_sdvo = {
 229         .dot = { .min = 20000, .max = 400000},
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         /* Pineview's Ncounter is a ring counter */
 232         .n = { .min = 3, .max = 6 },
 233         .m = { .min = 2, .max = 256 },
 234         /* Pineview only has one combined m divider, which we treat as m2. */
 235         .m1 = { .min = 0, .max = 0 },
 236         .m2 = { .min = 0, .max = 254 },
 237         .p = { .min = 5, .max = 80 },
 238         .p1 = { .min = 1, .max = 8 },
 239         .p2 = { .dot_limit = 200000,
 240                 .p2_slow = 10, .p2_fast = 5 },
 241 };
 242
 243 static const intel_limit_t intel_limits_pineview_lvds = {
 244         .dot = { .min = 20000, .max = 400000 },
 245         .vco = { .min = 1700000, .max = 3500000 },
 246         .n = { .min = 3, .max = 6 },
 247         .m = { .min = 2, .max = 256 },
 248         .m1 = { .min = 0, .max = 0 },
 249         .m2 = { .min = 0, .max = 254 },
 250         .p = { .min = 7, .max = 112 },
 251         .p1 = { .min = 1, .max = 8 },
 252         .p2 = { .dot_limit = 112000,
 253                 .p2_slow = 14, .p2_fast = 14 },
 254 };
 255
 256 /* Ironlake / Sandybridge
 257  *
 258  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 259  * the range value for them is (actual_value - 2).
 260  */
 261 static const intel_limit_t intel_limits_ironlake_dac = {
 262         .dot = { .min = 25000, .max = 350000 },
 263         .vco = { .min = 1760000, .max = 3510000 },
 264         .n = { .min = 1, .max = 5 },
 265         .m = { .min = 79, .max = 127 },
 266         .m1 = { .min = 12, .max = 22 },
 267         .m2 = { .min = 5, .max = 9 },
 268         .p = { .min = 5, .max = 80 },
 269         .p1 = { .min = 1, .max = 8 },
 270         .p2 = { .dot_limit = 225000,
 271                 .p2_slow = 10, .p2_fast = 5 },
 272 };
 273
 274 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 275         .dot = { .min = 25000, .max = 350000 },
 276         .vco = { .min = 1760000, .max = 3510000 },
 277         .n = { .min = 1, .max = 3 },
 278         .m = { .min = 79, .max = 118 },
 279         .m1 = { .min = 12, .max = 22 },
 280         .m2 = { .min = 5, .max = 9 },
 281         .p = { .min = 28, .max = 112 },
 282         .p1 = { .min = 2, .max = 8 },
 283         .p2 = { .dot_limit = 225000,
 284                 .p2_slow = 14, .p2_fast = 14 },
 285 };
 286
 287 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 3 },
 291         .m = { .min = 79, .max = 127 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 14, .max = 56 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 7, .p2_fast = 7 },
 298 };
 299
 300 /* LVDS 100mhz refclk limits. */
 301 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 302         .dot = { .min = 25000, .max = 350000 },
 303         .vco = { .min = 1760000, .max = 3510000 },
 304         .n = { .min = 1, .max = 2 },
 305         .m = { .min = 79, .max = 126 },
 306         .m1 = { .min = 12, .max = 22 },
 307         .m2 = { .min = 5, .max = 9 },
 308         .p = { .min = 28, .max = 112 },
 309         .p1 = { .min = 2, .max = 8 },
 310         .p2 = { .dot_limit = 225000,
 311                 .p2_slow = 14, .p2_fast = 14 },
 312 };
 313
 314 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 315         .dot = { .min = 25000, .max = 350000 },
 316         .vco = { .min = 1760000, .max = 3510000 },
 317         .n = { .min = 1, .max = 3 },
 318         .m = { .min = 79, .max = 126 },
 319         .m1 = { .min = 12, .max = 22 },
 320         .m2 = { .min = 5, .max = 9 },
 321         .p = { .min = 14, .max = 42 },
 322         .p1 = { .min = 2, .max = 6 },
 323         .p2 = { .dot_limit = 225000,
 324                 .p2_slow = 7, .p2_fast = 7 },
 325 };
 326
 327 static const intel_limit_t intel_limits_vlv = {
 328          /*
 329           * These are the data rate limits (measured in fast clocks)
 330           * since those are the strictest limits we have. The fast
 331           * clock and actual rate limits are more relaxed, so checking
 332           * them would make no difference.
 333           */
 334         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 335         .vco = { .min = 4000000, .max = 6000000 },
 336         .n = { .min = 1, .max = 7 },
 337         .m1 = { .min = 2, .max = 3 },
 338         .m2 = { .min = 11, .max = 156 },
 339         .p1 = { .min = 2, .max = 3 },
 340         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 341 };
 342
 343 static const intel_limit_t intel_limits_chv = {
 344         /*
 345          * These are the data rate limits (measured in fast clocks)
 346          * since those are the strictest limits we have.  The fast
 347          * clock and actual rate limits are more relaxed, so checking
 348          * them would make no difference.
 349          */
 350         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 351         .vco = { .min = 4860000, .max = 6700000 },
 352         .n = { .min = 1, .max = 1 },
 353         .m1 = { .min = 2, .max = 2 },
 354         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 355         .p1 = { .min = 2, .max = 4 },
 356         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 357 };
 358
 359 static void vlv_clock(int refclk, intel_clock_t *clock)
 360 {
 361         clock->m = clock->m1 * clock->m2;
 362         clock->p = clock->p1 * clock->p2;
 363         if (WARN_ON(clock->n == 0 || clock->p == 0))
 364                 return;
 365         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 366         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 367 }
 368
 369 /**
 370  * Returns whether any output on the specified pipe is of the specified type
 371  */
 372 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 373 {
 374         struct drm_device *dev = crtc->dev;
 375         struct intel_encoder *encoder;
 376
 377         for_each_encoder_on_crtc(dev, crtc, encoder)
 378                 if (encoder->type == type)
 379                         return true;
 380
 381         return false;
 382 }
 383
 384 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 385                                                 int refclk)
 386 {
 387         struct drm_device *dev = crtc->dev;
 388         const intel_limit_t *limit;
 389
 390         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 391                 if (intel_is_dual_link_lvds(dev)) {
 392                         if (refclk == 100000)
 393                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 394                         else
 395                                 limit = &intel_limits_ironlake_dual_lvds;
 396                 } else {
 397                         if (refclk == 100000)
 398                                 limit = &intel_limits_ironlake_single_lvds_100m;
 399                         else
 400                                 limit = &intel_limits_ironlake_single_lvds;
 401                 }
 402         } else
 403                 limit = &intel_limits_ironlake_dac;
 404
 405         return limit;
 406 }
 407
 408 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 409 {
 410         struct drm_device *dev = crtc->dev;
 411         const intel_limit_t *limit;
 412
 413         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 414                 if (intel_is_dual_link_lvds(dev))
 415                         limit = &intel_limits_g4x_dual_channel_lvds;
 416                 else
 417                         limit = &intel_limits_g4x_single_channel_lvds;
 418         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 419                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 420                 limit = &intel_limits_g4x_hdmi;
 421         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 422                 limit = &intel_limits_g4x_sdvo;
 423         } else /* The option is for other outputs */
 424                 limit = &intel_limits_i9xx_sdvo;
 425
 426         return limit;
 427 }
 428
 429 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 430 {
 431         struct drm_device *dev = crtc->dev;
 432         const intel_limit_t *limit;
 433
 434         if (HAS_PCH_SPLIT(dev))
 435                 limit = intel_ironlake_limit(crtc, refclk);
 436         else if (IS_G4X(dev)) {
 437                 limit = intel_g4x_limit(crtc);
 438         } else if (IS_PINEVIEW(dev)) {
 439                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 440                         limit = &intel_limits_pineview_lvds;
 441                 else
 442                         limit = &intel_limits_pineview_sdvo;
 443         } else if (IS_CHERRYVIEW(dev)) {
 444                 limit = &intel_limits_chv;
 445         } else if (IS_VALLEYVIEW(dev)) {
 446                 limit = &intel_limits_vlv;
 447         } else if (!IS_GEN2(dev)) {
 448                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 449                         limit = &intel_limits_i9xx_lvds;
 450                 else
 451                         limit = &intel_limits_i9xx_sdvo;
 452         } else {
 453                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 454                         limit = &intel_limits_i8xx_lvds;
 455                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 456                         limit = &intel_limits_i8xx_dvo;
 457                 else
 458                         limit = &intel_limits_i8xx_dac;
 459         }
 460         return limit;
 461 }
 462
 463 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 464 static void pineview_clock(int refclk, intel_clock_t *clock)
 465 {
 466         clock->m = clock->m2 + 2;
 467         clock->p = clock->p1 * clock->p2;
 468         if (WARN_ON(clock->n == 0 || clock->p == 0))
 469                 return;
 470         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 471         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 472 }
 473
 474 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 475 {
 476         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 477 }
 478
 479 static void i9xx_clock(int refclk, intel_clock_t *clock)
 480 {
 481         clock->m = i9xx_dpll_compute_m(clock);
 482         clock->p = clock->p1 * clock->p2;
 483         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 484                 return;
 485         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 486         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 487 }
 488
 489 static void chv_clock(int refclk, intel_clock_t *clock)
 490 {
 491         clock->m = clock->m1 * clock->m2;
 492         clock->p = clock->p1 * clock->p2;
 493         if (WARN_ON(clock->n == 0 || clock->p == 0))
 494                 return;
 495         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 496                         clock->n << 22);
 497         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 498 }
 499
 500 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 501 /**
 502  * Returns whether the given set of divisors are valid for a given refclk with
 503  * the given connectors.
 504  */
 505
 506 static bool intel_PLL_is_valid(struct drm_device *dev,
 507                                const intel_limit_t *limit,
 508                                const intel_clock_t *clock)
 509 {
 510         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 511                 INTELPllInvalid("n out of range\n");
 512         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 513                 INTELPllInvalid("p1 out of range\n");
 514         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 515                 INTELPllInvalid("m2 out of range\n");
 516         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 517                 INTELPllInvalid("m1 out of range\n");
 518
 519         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 520                 if (clock->m1 <= clock->m2)
 521                         INTELPllInvalid("m1 <= m2\n");
 522
 523         if (!IS_VALLEYVIEW(dev)) {
 524                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 525                         INTELPllInvalid("p out of range\n");
 526                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 527                         INTELPllInvalid("m out of range\n");
 528         }
 529
 530         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 531                 INTELPllInvalid("vco out of range\n");
 532         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 533          * connector, etc., rather than just a single range.
 534          */
 535         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 536                 INTELPllInvalid("dot out of range\n");
 537
 538         return true;
 539 }
 540
 541 static bool
 542 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 543                     int target, int refclk, intel_clock_t *match_clock,
 544                     intel_clock_t *best_clock)
 545 {
 546         struct drm_device *dev = crtc->dev;
 547         intel_clock_t clock;
 548         int err = target;
 549
 550         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 551                 /*
 552                  * For LVDS just rely on its current settings for dual-channel.
 553                  * We haven't figured out how to reliably set up different
 554                  * single/dual channel state, if we even can.
 555                  */
 556                 if (intel_is_dual_link_lvds(dev))
 557                         clock.p2 = limit->p2.p2_fast;
 558                 else
 559                         clock.p2 = limit->p2.p2_slow;
 560         } else {
 561                 if (target < limit->p2.dot_limit)
 562                         clock.p2 = limit->p2.p2_slow;
 563                 else
 564                         clock.p2 = limit->p2.p2_fast;
 565         }
 566
 567         memset(best_clock, 0, sizeof(*best_clock));
 568
 569         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 570              clock.m1++) {
 571                 for (clock.m2 = limit->m2.min;
 572                      clock.m2 <= limit->m2.max; clock.m2++) {
 573                         if (clock.m2 >= clock.m1)
 574                                 break;
 575                         for (clock.n = limit->n.min;
 576                              clock.n <= limit->n.max; clock.n++) {
 577                                 for (clock.p1 = limit->p1.min;
 578                                         clock.p1 <= limit->p1.max; clock.p1++) {
 579                                         int this_err;
 580
 581                                         i9xx_clock(refclk, &clock);
 582                                         if (!intel_PLL_is_valid(dev, limit,
 583                                                                 &clock))
 584                                                 continue;
 585                                         if (match_clock &&
 586                                             clock.p != match_clock->p)
 587                                                 continue;
 588
 589                                         this_err = abs(clock.dot - target);
 590                                         if (this_err < err) {
 591                                                 *best_clock = clock;
 592                                                 err = this_err;
 593                                         }
 594                                 }
 595                         }
 596                 }
 597         }
 598
 599         return (err != target);
 600 }
 601
 602 static bool
 603 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 604                    int target, int refclk, intel_clock_t *match_clock,
 605                    intel_clock_t *best_clock)
 606 {
 607         struct drm_device *dev = crtc->dev;
 608         intel_clock_t clock;
 609         int err = target;
 610
 611         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 612                 /*
 613                  * For LVDS just rely on its current settings for dual-channel.
 614                  * We haven't figured out how to reliably set up different
 615                  * single/dual channel state, if we even can.
 616                  */
 617                 if (intel_is_dual_link_lvds(dev))
 618                         clock.p2 = limit->p2.p2_fast;
 619                 else
 620                         clock.p2 = limit->p2.p2_slow;
 621         } else {
 622                 if (target < limit->p2.dot_limit)
 623                         clock.p2 = limit->p2.p2_slow;
 624                 else
 625                         clock.p2 = limit->p2.p2_fast;
 626         }
 627
 628         memset(best_clock, 0, sizeof(*best_clock));
 629
 630         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 631              clock.m1++) {
 632                 for (clock.m2 = limit->m2.min;
 633                      clock.m2 <= limit->m2.max; clock.m2++) {
 634                         for (clock.n = limit->n.min;
 635                              clock.n <= limit->n.max; clock.n++) {
 636                                 for (clock.p1 = limit->p1.min;
 637                                         clock.p1 <= limit->p1.max; clock.p1++) {
 638                                         int this_err;
 639
 640                                         pineview_clock(refclk, &clock);
 641                                         if (!intel_PLL_is_valid(dev, limit,
 642                                                                 &clock))
 643                                                 continue;
 644                                         if (match_clock &&
 645                                             clock.p != match_clock->p)
 646                                                 continue;
 647
 648                                         this_err = abs(clock.dot - target);
 649                                         if (this_err < err) {
 650                                                 *best_clock = clock;
 651                                                 err = this_err;
 652                                         }
 653                                 }
 654                         }
 655                 }
 656         }
 657
 658         return (err != target);
 659 }
 660
 661 static bool
 662 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 663                    int target, int refclk, intel_clock_t *match_clock,
 664                    intel_clock_t *best_clock)
 665 {
 666         struct drm_device *dev = crtc->dev;
 667         intel_clock_t clock;
 668         int max_n;
 669         bool found;
 670         /* approximately equals target * 0.00585 */
 671         int err_most = (target >> 8) + (target >> 9);
 672         found = false;
 673
 674         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 675                 if (intel_is_dual_link_lvds(dev))
 676                         clock.p2 = limit->p2.p2_fast;
 677                 else
 678                         clock.p2 = limit->p2.p2_slow;
 679         } else {
 680                 if (target < limit->p2.dot_limit)
 681                         clock.p2 = limit->p2.p2_slow;
 682                 else
 683                         clock.p2 = limit->p2.p2_fast;
 684         }
 685
 686         memset(best_clock, 0, sizeof(*best_clock));
 687         max_n = limit->n.max;
 688         /* based on hardware requirement, prefer smaller n to precision */
 689         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 690                 /* based on hardware requirement, prefere larger m1,m2 */
 691                 for (clock.m1 = limit->m1.max;
 692                      clock.m1 >= limit->m1.min; clock.m1--) {
 693                         for (clock.m2 = limit->m2.max;
 694                              clock.m2 >= limit->m2.min; clock.m2--) {
 695                                 for (clock.p1 = limit->p1.max;
 696                                      clock.p1 >= limit->p1.min; clock.p1--) {
 697                                         int this_err;
 698
 699                                         i9xx_clock(refclk, &clock);
 700                                         if (!intel_PLL_is_valid(dev, limit,
 701                                                                 &clock))
 702                                                 continue;
 703
 704                                         this_err = abs(clock.dot - target);
 705                                         if (this_err < err_most) {
 706                                                 *best_clock = clock;
 707                                                 err_most = this_err;
 708                                                 max_n = clock.n;
 709                                                 found = true;
 710                                         }
 711                                 }
 712                         }
 713                 }
 714         }
 715         return found;
 716 }
 717
 718 static bool
 719 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->dev;
 724         intel_clock_t clock;
 725         unsigned int bestppm = 1000000;
 726         /* min update 19.2 MHz */
 727         int max_n = min(limit->n.max, refclk / 19200);
 728         bool found = false;
 729
 730         target *= 5; /* fast clock */
 731
 732         memset(best_clock, 0, sizeof(*best_clock));
 733
 734         /* based on hardware requirement, prefer smaller n to precision */
 735         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 736                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 737                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 738                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 739                                 clock.p = clock.p1 * clock.p2;
 740                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 741                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 742                                         unsigned int ppm, diff;
 743
 744                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 745                                                                      refclk * clock.m1);
 746
 747                                         vlv_clock(refclk, &clock);
 748
 749                                         if (!intel_PLL_is_valid(dev, limit,
 750                                                                 &clock))
 751                                                 continue;
 752
 753                                         diff = abs(clock.dot - target);
 754                                         ppm = div_u64(1000000ULL * diff, target);
 755
 756                                         if (ppm < 100 && clock.p > best_clock->p) {
 757                                                 bestppm = 0;
 758                                                 *best_clock = clock;
 759                                                 found = true;
 760                                         }
 761
 762                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 763                                                 bestppm = ppm;
 764                                                 *best_clock = clock;
 765                                                 found = true;
 766                                         }
 767                                 }
 768                         }
 769                 }
 770         }
 771
 772         return found;
 773 }
 774
 775 static bool
 776 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->dev;
 781         intel_clock_t clock;
 782         uint64_t m2;
 783         int found = false;
 784
 785         memset(best_clock, 0, sizeof(*best_clock));
 786
 787         /*
 788          * Based on hardware doc, the n always set to 1, and m1 always
 789          * set to 2.  If requires to support 200Mhz refclk, we need to
 790          * revisit this because n may not 1 anymore.
 791          */
 792         clock.n = 1, clock.m1 = 2;
 793         target *= 5;    /* fast clock */
 794
 795         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 796                 for (clock.p2 = limit->p2.p2_fast;
 797                                 clock.p2 >= limit->p2.p2_slow;
 798                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 799
 800                         clock.p = clock.p1 * clock.p2;
 801
 802                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 803                                         clock.n) << 22, refclk * clock.m1);
 804
 805                         if (m2 > INT_MAX/clock.m1)
 806                                 continue;
 807
 808                         clock.m2 = m2;
 809
 810                         chv_clock(refclk, &clock);
 811
 812                         if (!intel_PLL_is_valid(dev, limit, &clock))
 813                                 continue;
 814
 815                         /* based on hardware requirement, prefer bigger p
 816                          */
 817                         if (clock.p > best_clock->p) {
 818                                 *best_clock = clock;
 819                                 found = true;
 820                         }
 821                 }
 822         }
 823
 824         return found;
 825 }
 826
 827 bool intel_crtc_active(struct drm_crtc *crtc)
 828 {
 829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 830
 831         /* Be paranoid as we can arrive here with only partial
 832          * state retrieved from the hardware during setup.
 833          *
 834          * We can ditch the adjusted_mode.crtc_clock check as soon
 835          * as Haswell has gained clock readout/fastboot support.
 836          *
 837          * We can ditch the crtc->primary->fb check as soon as we can
 838          * properly reconstruct framebuffers.
 839          */
 840         return intel_crtc->active && crtc->primary->fb &&
 841                 intel_crtc->config.adjusted_mode.crtc_clock;
 842 }
 843
 844 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 845                                              enum pipe pipe)
 846 {
 847         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 849
 850         return intel_crtc->config.cpu_transcoder;
 851 }
 852
 853 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 854 {
 855         struct drm_i915_private *dev_priv = dev->dev_private;
 856         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 857
 858         frame = I915_READ(frame_reg);
 859
 860         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 861                 WARN(1, "vblank wait timed out\n");
 862 }
 863
 864 /**
 865  * intel_wait_for_vblank - wait for vblank on a given pipe
 866  * @dev: drm device
 867  * @pipe: pipe to wait for
 868  *
 869  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 870  * mode setting code.
 871  */
 872 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 873 {
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         int pipestat_reg = PIPESTAT(pipe);
 876
 877         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 878                 g4x_wait_for_vblank(dev, pipe);
 879                 return;
 880         }
 881
 882         /* Clear existing vblank status. Note this will clear any other
 883          * sticky status fields as well.
 884          *
 885          * This races with i915_driver_irq_handler() with the result
 886          * that either function could miss a vblank event.  Here it is not
 887          * fatal, as we will either wait upon the next vblank interrupt or
 888          * timeout.  Generally speaking intel_wait_for_vblank() is only
 889          * called during modeset at which time the GPU should be idle and
 890          * should *not* be performing page flips and thus not waiting on
 891          * vblanks...
 892          * Currently, the result of us stealing a vblank from the irq
 893          * handler is that a single frame will be skipped during swapbuffers.
 894          */
 895         I915_WRITE(pipestat_reg,
 896                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 897
 898         /* Wait for vblank interrupt bit to set */
 899         if (wait_for(I915_READ(pipestat_reg) &
 900                      PIPE_VBLANK_INTERRUPT_STATUS,
 901                      50))
 902                 DRM_DEBUG_KMS("vblank wait timed out\n");
 903 }
 904
 905 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 906 {
 907         struct drm_i915_private *dev_priv = dev->dev_private;
 908         u32 reg = PIPEDSL(pipe);
 909         u32 line1, line2;
 910         u32 line_mask;
 911
 912         if (IS_GEN2(dev))
 913                 line_mask = DSL_LINEMASK_GEN2;
 914         else
 915                 line_mask = DSL_LINEMASK_GEN3;
 916
 917         line1 = I915_READ(reg) & line_mask;
 918         mdelay(5);
 919         line2 = I915_READ(reg) & line_mask;
 920
 921         return line1 == line2;
 922 }
 923
 924 /*
 925  * intel_wait_for_pipe_off - wait for pipe to turn off
 926  * @dev: drm device
 927  * @pipe: pipe to wait for
 928  *
 929  * After disabling a pipe, we can't wait for vblank in the usual way,
 930  * spinning on the vblank interrupt status bit, since we won't actually
 931  * see an interrupt when the pipe is disabled.
 932  *
 933  * On Gen4 and above:
 934  *   wait for the pipe register state bit to turn off
 935  *
 936  * Otherwise:
 937  *   wait for the display line value to settle (it usually
 938  *   ends up stopping at the start of the next frame).
 939  *
 940  */
 941 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 942 {
 943         struct drm_i915_private *dev_priv = dev->dev_private;
 944         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 945                                                                       pipe);
 946
 947         if (INTEL_INFO(dev)->gen >= 4) {
 948                 int reg = PIPECONF(cpu_transcoder);
 949
 950                 /* Wait for the Pipe State to go off */
 951                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 952                              100))
 953                         WARN(1, "pipe_off wait timed out\n");
 954         } else {
 955                 /* Wait for the display line to settle */
 956                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 957                         WARN(1, "pipe_off wait timed out\n");
 958         }
 959 }
 960
 961 /*
 962  * ibx_digital_port_connected - is the specified port connected?
 963  * @dev_priv: i915 private structure
 964  * @port: the port to test
 965  *
 966  * Returns true if @port is connected, false otherwise.
 967  */
 968 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 969                                 struct intel_digital_port *port)
 970 {
 971         u32 bit;
 972
 973         if (HAS_PCH_IBX(dev_priv->dev)) {
 974                 switch (port->port) {
 975                 case PORT_B:
 976                         bit = SDE_PORTB_HOTPLUG;
 977                         break;
 978                 case PORT_C:
 979                         bit = SDE_PORTC_HOTPLUG;
 980                         break;
 981                 case PORT_D:
 982                         bit = SDE_PORTD_HOTPLUG;
 983                         break;
 984                 default:
 985                         return true;
 986                 }
 987         } else {
 988                 switch (port->port) {
 989                 case PORT_B:
 990                         bit = SDE_PORTB_HOTPLUG_CPT;
 991                         break;
 992                 case PORT_C:
 993                         bit = SDE_PORTC_HOTPLUG_CPT;
 994                         break;
 995                 case PORT_D:
 996                         bit = SDE_PORTD_HOTPLUG_CPT;
 997                         break;
 998                 default:
 999                         return true;
1000                 }
1001         }
1002
1003         return I915_READ(SDEISR) & bit;
1004 }
1005
1006 static const char *state_string(bool enabled)
1007 {
1008         return enabled ? "on" : "off";
1009 }
1010
1011 /* Only for pre-ILK configs */
1012 void assert_pll(struct drm_i915_private *dev_priv,
1013                 enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = DPLL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & DPLL_VCO_ENABLE);
1022         WARN(cur_state != state,
1023              "PLL state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026
1027 /* XXX: the dsi pll is shared between MIPI DSI ports */
1028 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1029 {
1030         u32 val;
1031         bool cur_state;
1032
1033         mutex_lock(&dev_priv->dpio_lock);
1034         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1035         mutex_unlock(&dev_priv->dpio_lock);
1036
1037         cur_state = val & DSI_PLL_VCO_EN;
1038         WARN(cur_state != state,
1039              "DSI PLL state assertion failure (expected %s, current %s)\n",
1040              state_string(state), state_string(cur_state));
1041 }
1042 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1043 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1044
1045 struct intel_shared_dpll *
1046 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1047 {
1048         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1049
1050         if (crtc->config.shared_dpll < 0)
1051                 return NULL;
1052
1053         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1054 }
1055
1056 /* For ILK+ */
1057 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1058                         struct intel_shared_dpll *pll,
1059                         bool state)
1060 {
1061         bool cur_state;
1062         struct intel_dpll_hw_state hw_state;
1063
1064         if (HAS_PCH_LPT(dev_priv->dev)) {
1065                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1066                 return;
1067         }
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                                   enum pipe pipe)
1158 {
1159         int pp_reg, lvds_reg;
1160         u32 val;
1161         enum pipe panel_pipe = PIPE_A;
1162         bool locked = true;
1163
1164         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1165                 pp_reg = PCH_PP_CONTROL;
1166                 lvds_reg = PCH_LVDS;
1167         } else {
1168                 pp_reg = PP_CONTROL;
1169                 lvds_reg = LVDS;
1170         }
1171
1172         val = I915_READ(pp_reg);
1173         if (!(val & PANEL_POWER_ON) ||
1174             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1175                 locked = false;
1176
1177         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1178                 panel_pipe = PIPE_B;
1179
1180         WARN(panel_pipe == pipe && locked,
1181              "panel assertion failure, pipe %c regs locked\n",
1182              pipe_name(pipe));
1183 }
1184
1185 static void assert_cursor(struct drm_i915_private *dev_priv,
1186                           enum pipe pipe, bool state)
1187 {
1188         struct drm_device *dev = dev_priv->dev;
1189         bool cur_state;
1190
1191         if (IS_845G(dev) || IS_I865G(dev))
1192                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1193         else
1194                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1195
1196         WARN(cur_state != state,
1197              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1198              pipe_name(pipe), state_string(state), state_string(cur_state));
1199 }
1200 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1201 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1202
1203 void assert_pipe(struct drm_i915_private *dev_priv,
1204                  enum pipe pipe, bool state)
1205 {
1206         int reg;
1207         u32 val;
1208         bool cur_state;
1209         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1210                                                                       pipe);
1211
1212         /* if we need the pipe A quirk it must be always on */
1213         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1214                 state = true;
1215
1216         if (!intel_display_power_enabled(dev_priv,
1217                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1218                 cur_state = false;
1219         } else {
1220                 reg = PIPECONF(cpu_transcoder);
1221                 val = I915_READ(reg);
1222                 cur_state = !!(val & PIPECONF_ENABLE);
1223         }
1224
1225         WARN(cur_state != state,
1226              "pipe %c assertion failure (expected %s, current %s)\n",
1227              pipe_name(pipe), state_string(state), state_string(cur_state));
1228 }
1229
1230 static void assert_plane(struct drm_i915_private *dev_priv,
1231                          enum plane plane, bool state)
1232 {
1233         int reg;
1234         u32 val;
1235         bool cur_state;
1236
1237         reg = DSPCNTR(plane);
1238         val = I915_READ(reg);
1239         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1240         WARN(cur_state != state,
1241              "plane %c assertion failure (expected %s, current %s)\n",
1242              plane_name(plane), state_string(state), state_string(cur_state));
1243 }
1244
1245 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1246 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1247
1248 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1249                                    enum pipe pipe)
1250 {
1251         struct drm_device *dev = dev_priv->dev;
1252         int reg, i;
1253         u32 val;
1254         int cur_pipe;
1255
1256         /* Primary planes are fixed to pipes on gen4+ */
1257         if (INTEL_INFO(dev)->gen >= 4) {
1258                 reg = DSPCNTR(pipe);
1259                 val = I915_READ(reg);
1260                 WARN(val & DISPLAY_PLANE_ENABLE,
1261                      "plane %c assertion failure, should be disabled but not\n",
1262                      plane_name(pipe));
1263                 return;
1264         }
1265
1266         /* Need to check both planes against the pipe */
1267         for_each_pipe(i) {
1268                 reg = DSPCNTR(i);
1269                 val = I915_READ(reg);
1270                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271                         DISPPLANE_SEL_PIPE_SHIFT;
1272                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274                      plane_name(i), pipe_name(pipe));
1275         }
1276 }
1277
1278 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279                                     enum pipe pipe)
1280 {
1281         struct drm_device *dev = dev_priv->dev;
1282         int reg, sprite;
1283         u32 val;
1284
1285         if (IS_VALLEYVIEW(dev)) {
1286                 for_each_sprite(pipe, sprite) {
1287                         reg = SPCNTR(pipe, sprite);
1288                         val = I915_READ(reg);
1289                         WARN(val & SP_ENABLE,
1290                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291                              sprite_name(pipe, sprite), pipe_name(pipe));
1292                 }
1293         } else if (INTEL_INFO(dev)->gen >= 7) {
1294                 reg = SPRCTL(pipe);
1295                 val = I915_READ(reg);
1296                 WARN(val & SPRITE_ENABLE,
1297                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1298                      plane_name(pipe), pipe_name(pipe));
1299         } else if (INTEL_INFO(dev)->gen >= 5) {
1300                 reg = DVSCNTR(pipe);
1301                 val = I915_READ(reg);
1302                 WARN(val & DVS_ENABLE,
1303                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1304                      plane_name(pipe), pipe_name(pipe));
1305         }
1306 }
1307
1308 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1309 {
1310         u32 val;
1311         bool enabled;
1312
1313         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1314
1315         val = I915_READ(PCH_DREF_CONTROL);
1316         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1317                             DREF_SUPERSPREAD_SOURCE_MASK));
1318         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1319 }
1320
1321 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1322                                            enum pipe pipe)
1323 {
1324         int reg;
1325         u32 val;
1326         bool enabled;
1327
1328         reg = PCH_TRANSCONF(pipe);
1329         val = I915_READ(reg);
1330         enabled = !!(val & TRANS_ENABLE);
1331         WARN(enabled,
1332              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1333              pipe_name(pipe));
1334 }
1335
1336 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1337                             enum pipe pipe, u32 port_sel, u32 val)
1338 {
1339         if ((val & DP_PORT_EN) == 0)
1340                 return false;
1341
1342         if (HAS_PCH_CPT(dev_priv->dev)) {
1343                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1344                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1345                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1346                         return false;
1347         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1348                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1349                         return false;
1350         } else {
1351                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1352                         return false;
1353         }
1354         return true;
1355 }
1356
1357 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1358                               enum pipe pipe, u32 val)
1359 {
1360         if ((val & SDVO_ENABLE) == 0)
1361                 return false;
1362
1363         if (HAS_PCH_CPT(dev_priv->dev)) {
1364                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1365                         return false;
1366         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1367                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1368                         return false;
1369         } else {
1370                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1371                         return false;
1372         }
1373         return true;
1374 }
1375
1376 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1377                               enum pipe pipe, u32 val)
1378 {
1379         if ((val & LVDS_PORT_EN) == 0)
1380                 return false;
1381
1382         if (HAS_PCH_CPT(dev_priv->dev)) {
1383                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1384                         return false;
1385         } else {
1386                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1387                         return false;
1388         }
1389         return true;
1390 }
1391
1392 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1393                               enum pipe pipe, u32 val)
1394 {
1395         if ((val & ADPA_DAC_ENABLE) == 0)
1396                 return false;
1397         if (HAS_PCH_CPT(dev_priv->dev)) {
1398                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1399                         return false;
1400         } else {
1401                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1402                         return false;
1403         }
1404         return true;
1405 }
1406
1407 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1408                                    enum pipe pipe, int reg, u32 port_sel)
1409 {
1410         u32 val = I915_READ(reg);
1411         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1412              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1413              reg, pipe_name(pipe));
1414
1415         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1416              && (val & DP_PIPEB_SELECT),
1417              "IBX PCH dp port still using transcoder B\n");
1418 }
1419
1420 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1421                                      enum pipe pipe, int reg)
1422 {
1423         u32 val = I915_READ(reg);
1424         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1425              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1426              reg, pipe_name(pipe));
1427
1428         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1429              && (val & SDVO_PIPE_B_SELECT),
1430              "IBX PCH hdmi port still using transcoder B\n");
1431 }
1432
1433 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1434                                       enum pipe pipe)
1435 {
1436         int reg;
1437         u32 val;
1438
1439         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1440         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1441         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1442
1443         reg = PCH_ADPA;
1444         val = I915_READ(reg);
1445         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1446              "PCH VGA enabled on transcoder %c, should be disabled\n",
1447              pipe_name(pipe));
1448
1449         reg = PCH_LVDS;
1450         val = I915_READ(reg);
1451         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1452              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1453              pipe_name(pipe));
1454
1455         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1456         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1457         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1458 }
1459
1460 static void intel_init_dpio(struct drm_device *dev)
1461 {
1462         struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464         if (!IS_VALLEYVIEW(dev))
1465                 return;
1466
1467         /*
1468          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1469          * CHV x1 PHY (DP/HDMI D)
1470          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1471          */
1472         if (IS_CHERRYVIEW(dev)) {
1473                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1474                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1475         } else {
1476                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1477         }
1478 }
1479
1480 static void intel_reset_dpio(struct drm_device *dev)
1481 {
1482         struct drm_i915_private *dev_priv = dev->dev_private;
1483
1484         if (!IS_VALLEYVIEW(dev))
1485                 return;
1486
1487         if (IS_CHERRYVIEW(dev)) {
1488                 enum dpio_phy phy;
1489                 u32 val;
1490
1491                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1492                         /* Poll for phypwrgood signal */
1493                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1494                                                 PHY_POWERGOOD(phy), 1))
1495                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1496
1497                         /*
1498                          * Deassert common lane reset for PHY.
1499                          *
1500                          * This should only be done on init and resume from S3
1501                          * with both PLLs disabled, or we risk losing DPIO and
1502                          * PLL synchronization.
1503                          */
1504                         val = I915_READ(DISPLAY_PHY_CONTROL);
1505                         I915_WRITE(DISPLAY_PHY_CONTROL,
1506                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1507                 }
1508
1509         } else {
1510                 /*
1511                  * If DPIO has already been reset, e.g. by BIOS, just skip all
1512                  * this.
1513                  */
1514                 if (I915_READ(DPIO_CTL) & DPIO_CMNRST)
1515                         return;
1516
1517                 /*
1518                  * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1519                  * Need to assert and de-assert PHY SB reset by gating the
1520                  * common lane power, then un-gating it.
1521                  * Simply ungating isn't enough to reset the PHY enough to get
1522                  * ports and lanes running.
1523                  */
1524                 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1525                                      false);
1526                 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1527                                      true);
1528         }
1529 }
1530
1531 static void vlv_enable_pll(struct intel_crtc *crtc)
1532 {
1533         struct drm_device *dev = crtc->base.dev;
1534         struct drm_i915_private *dev_priv = dev->dev_private;
1535         int reg = DPLL(crtc->pipe);
1536         u32 dpll = crtc->config.dpll_hw_state.dpll;
1537
1538         assert_pipe_disabled(dev_priv, crtc->pipe);
1539
1540         /* No really, not for ILK+ */
1541         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1542
1543         /* PLL is protected by panel, make sure we can write it */
1544         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1545                 assert_panel_unlocked(dev_priv, crtc->pipe);
1546
1547         I915_WRITE(reg, dpll);
1548         POSTING_READ(reg);
1549         udelay(150);
1550
1551         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1552                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1553
1554         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1555         POSTING_READ(DPLL_MD(crtc->pipe));
1556
1557         /* We do this three times for luck */
1558         I915_WRITE(reg, dpll);
1559         POSTING_READ(reg);
1560         udelay(150); /* wait for warmup */
1561         I915_WRITE(reg, dpll);
1562         POSTING_READ(reg);
1563         udelay(150); /* wait for warmup */
1564         I915_WRITE(reg, dpll);
1565         POSTING_READ(reg);
1566         udelay(150); /* wait for warmup */
1567 }
1568
1569 static void chv_enable_pll(struct intel_crtc *crtc)
1570 {
1571         struct drm_device *dev = crtc->base.dev;
1572         struct drm_i915_private *dev_priv = dev->dev_private;
1573         int pipe = crtc->pipe;
1574         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1575         u32 tmp;
1576
1577         assert_pipe_disabled(dev_priv, crtc->pipe);
1578
1579         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1580
1581         mutex_lock(&dev_priv->dpio_lock);
1582
1583         /* Enable back the 10bit clock to display controller */
1584         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1585         tmp |= DPIO_DCLKP_EN;
1586         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1587
1588         /*
1589          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1590          */
1591         udelay(1);
1592
1593         /* Enable PLL */
1594         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1595
1596         /* Check PLL is locked */
1597         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1598                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1599
1600         /* not sure when this should be written */
1601         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1602         POSTING_READ(DPLL_MD(pipe));
1603
1604         mutex_unlock(&dev_priv->dpio_lock);
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609         struct drm_device *dev = crtc->base.dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         int reg = DPLL(crtc->pipe);
1612         u32 dpll = crtc->config.dpll_hw_state.dpll;
1613
1614         assert_pipe_disabled(dev_priv, crtc->pipe);
1615
1616         /* No really, not for ILK+ */
1617         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1618
1619         /* PLL is protected by panel, make sure we can write it */
1620         if (IS_MOBILE(dev) && !IS_I830(dev))
1621                 assert_panel_unlocked(dev_priv, crtc->pipe);
1622
1623         I915_WRITE(reg, dpll);
1624
1625         /* Wait for the clocks to stabilize. */
1626         POSTING_READ(reg);
1627         udelay(150);
1628
1629         if (INTEL_INFO(dev)->gen >= 4) {
1630                 I915_WRITE(DPLL_MD(crtc->pipe),
1631                            crtc->config.dpll_hw_state.dpll_md);
1632         } else {
1633                 /* The pixel multiplier can only be updated once the
1634                  * DPLL is enabled and the clocks are stable.
1635                  *
1636                  * So write it again.
1637                  */
1638                 I915_WRITE(reg, dpll);
1639         }
1640
1641         /* We do this three times for luck */
1642         I915_WRITE(reg, dpll);
1643         POSTING_READ(reg);
1644         udelay(150); /* wait for warmup */
1645         I915_WRITE(reg, dpll);
1646         POSTING_READ(reg);
1647         udelay(150); /* wait for warmup */
1648         I915_WRITE(reg, dpll);
1649         POSTING_READ(reg);
1650         udelay(150); /* wait for warmup */
1651 }
1652
1653 /**
1654  * i9xx_disable_pll - disable a PLL
1655  * @dev_priv: i915 private structure
1656  * @pipe: pipe PLL to disable
1657  *
1658  * Disable the PLL for @pipe, making sure the pipe is off first.
1659  *
1660  * Note!  This is for pre-ILK only.
1661  */
1662 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1663 {
1664         /* Don't disable pipe A or pipe A PLLs if needed */
1665         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1666                 return;
1667
1668         /* Make sure the pipe isn't still relying on us */
1669         assert_pipe_disabled(dev_priv, pipe);
1670
1671         I915_WRITE(DPLL(pipe), 0);
1672         POSTING_READ(DPLL(pipe));
1673 }
1674
1675 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1676 {
1677         u32 val = 0;
1678
1679         /* Make sure the pipe isn't still relying on us */
1680         assert_pipe_disabled(dev_priv, pipe);
1681
1682         /*
1683          * Leave integrated clock source and reference clock enabled for pipe B.
1684          * The latter is needed for VGA hotplug / manual detection.
1685          */
1686         if (pipe == PIPE_B)
1687                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1688         I915_WRITE(DPLL(pipe), val);
1689         POSTING_READ(DPLL(pipe));
1690
1691 }
1692
1693 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1694 {
1695         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1696         u32 val;
1697
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700
1701         /* Set PLL en = 0 */
1702         val = DPLL_SSC_REF_CLOCK_CHV;
1703         if (pipe != PIPE_A)
1704                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1705         I915_WRITE(DPLL(pipe), val);
1706         POSTING_READ(DPLL(pipe));
1707
1708         mutex_lock(&dev_priv->dpio_lock);
1709
1710         /* Disable 10bit clock to display controller */
1711         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1712         val &= ~DPIO_DCLKP_EN;
1713         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1714
1715         mutex_unlock(&dev_priv->dpio_lock);
1716 }
1717
1718 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1719                 struct intel_digital_port *dport)
1720 {
1721         u32 port_mask;
1722         int dpll_reg;
1723
1724         switch (dport->port) {
1725         case PORT_B:
1726                 port_mask = DPLL_PORTB_READY_MASK;
1727                 dpll_reg = DPLL(0);
1728                 break;
1729         case PORT_C:
1730                 port_mask = DPLL_PORTC_READY_MASK;
1731                 dpll_reg = DPLL(0);
1732                 break;
1733         case PORT_D:
1734                 port_mask = DPLL_PORTD_READY_MASK;
1735                 dpll_reg = DPIO_PHY_STATUS;
1736                 break;
1737         default:
1738                 BUG();
1739         }
1740
1741         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1742                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1743                      port_name(dport->port), I915_READ(dpll_reg));
1744 }
1745
1746 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1747 {
1748         struct drm_device *dev = crtc->base.dev;
1749         struct drm_i915_private *dev_priv = dev->dev_private;
1750         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1751
1752         WARN_ON(!pll->refcount);
1753         if (pll->active == 0) {
1754                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1755                 WARN_ON(pll->on);
1756                 assert_shared_dpll_disabled(dev_priv, pll);
1757
1758                 pll->mode_set(dev_priv, pll);
1759         }
1760 }
1761
1762 /**
1763  * intel_enable_shared_dpll - enable PCH PLL
1764  * @dev_priv: i915 private structure
1765  * @pipe: pipe PLL to enable
1766  *
1767  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1768  * drives the transcoder clock.
1769  */
1770 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1771 {
1772         struct drm_device *dev = crtc->base.dev;
1773         struct drm_i915_private *dev_priv = dev->dev_private;
1774         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1775
1776         if (WARN_ON(pll == NULL))
1777                 return;
1778
1779         if (WARN_ON(pll->refcount == 0))
1780                 return;
1781
1782         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1783                       pll->name, pll->active, pll->on,
1784                       crtc->base.base.id);
1785
1786         if (pll->active++) {
1787                 WARN_ON(!pll->on);
1788                 assert_shared_dpll_enabled(dev_priv, pll);
1789                 return;
1790         }
1791         WARN_ON(pll->on);
1792
1793         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1794         pll->enable(dev_priv, pll);
1795         pll->on = true;
1796 }
1797
1798 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1799 {
1800         struct drm_device *dev = crtc->base.dev;
1801         struct drm_i915_private *dev_priv = dev->dev_private;
1802         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1803
1804         /* PCH only available on ILK+ */
1805         BUG_ON(INTEL_INFO(dev)->gen < 5);
1806         if (WARN_ON(pll == NULL))
1807                return;
1808
1809         if (WARN_ON(pll->refcount == 0))
1810                 return;
1811
1812         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815
1816         if (WARN_ON(pll->active == 0)) {
1817                 assert_shared_dpll_disabled(dev_priv, pll);
1818                 return;
1819         }
1820
1821         assert_shared_dpll_enabled(dev_priv, pll);
1822         WARN_ON(!pll->on);
1823         if (--pll->active)
1824                 return;
1825
1826         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1827         pll->disable(dev_priv, pll);
1828         pll->on = false;
1829 }
1830
1831 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1832                                            enum pipe pipe)
1833 {
1834         struct drm_device *dev = dev_priv->dev;
1835         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1836         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1837         uint32_t reg, val, pipeconf_val;
1838
1839         /* PCH only available on ILK+ */
1840         BUG_ON(INTEL_INFO(dev)->gen < 5);
1841
1842         /* Make sure PCH DPLL is enabled */
1843         assert_shared_dpll_enabled(dev_priv,
1844                                    intel_crtc_to_shared_dpll(intel_crtc));
1845
1846         /* FDI must be feeding us bits for PCH ports */
1847         assert_fdi_tx_enabled(dev_priv, pipe);
1848         assert_fdi_rx_enabled(dev_priv, pipe);
1849
1850         if (HAS_PCH_CPT(dev)) {
1851                 /* Workaround: Set the timing override bit before enabling the
1852                  * pch transcoder. */
1853                 reg = TRANS_CHICKEN2(pipe);
1854                 val = I915_READ(reg);
1855                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1856                 I915_WRITE(reg, val);
1857         }
1858
1859         reg = PCH_TRANSCONF(pipe);
1860         val = I915_READ(reg);
1861         pipeconf_val = I915_READ(PIPECONF(pipe));
1862
1863         if (HAS_PCH_IBX(dev_priv->dev)) {
1864                 /*
1865                  * make the BPC in transcoder be consistent with
1866                  * that in pipeconf reg.
1867                  */
1868                 val &= ~PIPECONF_BPC_MASK;
1869                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1870         }
1871
1872         val &= ~TRANS_INTERLACE_MASK;
1873         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1874                 if (HAS_PCH_IBX(dev_priv->dev) &&
1875                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1876                         val |= TRANS_LEGACY_INTERLACED_ILK;
1877                 else
1878                         val |= TRANS_INTERLACED;
1879         else
1880                 val |= TRANS_PROGRESSIVE;
1881
1882         I915_WRITE(reg, val | TRANS_ENABLE);
1883         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1884                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1885 }
1886
1887 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1888                                       enum transcoder cpu_transcoder)
1889 {
1890         u32 val, pipeconf_val;
1891
1892         /* PCH only available on ILK+ */
1893         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1894
1895         /* FDI must be feeding us bits for PCH ports */
1896         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1897         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1898
1899         /* Workaround: set timing override bit. */
1900         val = I915_READ(_TRANSA_CHICKEN2);
1901         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1902         I915_WRITE(_TRANSA_CHICKEN2, val);
1903
1904         val = TRANS_ENABLE;
1905         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1906
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1908             PIPECONF_INTERLACED_ILK)
1909                 val |= TRANS_INTERLACED;
1910         else
1911                 val |= TRANS_PROGRESSIVE;
1912
1913         I915_WRITE(LPT_TRANSCONF, val);
1914         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1915                 DRM_ERROR("Failed to enable PCH transcoder\n");
1916 }
1917
1918 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1919                                             enum pipe pipe)
1920 {
1921         struct drm_device *dev = dev_priv->dev;
1922         uint32_t reg, val;
1923
1924         /* FDI relies on the transcoder */
1925         assert_fdi_tx_disabled(dev_priv, pipe);
1926         assert_fdi_rx_disabled(dev_priv, pipe);
1927
1928         /* Ports must be off as well */
1929         assert_pch_ports_disabled(dev_priv, pipe);
1930
1931         reg = PCH_TRANSCONF(pipe);
1932         val = I915_READ(reg);
1933         val &= ~TRANS_ENABLE;
1934         I915_WRITE(reg, val);
1935         /* wait for PCH transcoder off, transcoder state */
1936         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1937                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1938
1939         if (!HAS_PCH_IBX(dev)) {
1940                 /* Workaround: Clear the timing override chicken bit again. */
1941                 reg = TRANS_CHICKEN2(pipe);
1942                 val = I915_READ(reg);
1943                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1944                 I915_WRITE(reg, val);
1945         }
1946 }
1947
1948 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1949 {
1950         u32 val;
1951
1952         val = I915_READ(LPT_TRANSCONF);
1953         val &= ~TRANS_ENABLE;
1954         I915_WRITE(LPT_TRANSCONF, val);
1955         /* wait for PCH transcoder off, transcoder state */
1956         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1957                 DRM_ERROR("Failed to disable PCH transcoder\n");
1958
1959         /* Workaround: clear timing override bit. */
1960         val = I915_READ(_TRANSA_CHICKEN2);
1961         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1962         I915_WRITE(_TRANSA_CHICKEN2, val);
1963 }
1964
1965 /**
1966  * intel_enable_pipe - enable a pipe, asserting requirements
1967  * @crtc: crtc responsible for the pipe
1968  *
1969  * Enable @crtc's pipe, making sure that various hardware specific requirements
1970  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1971  */
1972 static void intel_enable_pipe(struct intel_crtc *crtc)
1973 {
1974         struct drm_device *dev = crtc->base.dev;
1975         struct drm_i915_private *dev_priv = dev->dev_private;
1976         enum pipe pipe = crtc->pipe;
1977         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1978                                                                       pipe);
1979         enum pipe pch_transcoder;
1980         int reg;
1981         u32 val;
1982
1983         assert_planes_disabled(dev_priv, pipe);
1984         assert_cursor_disabled(dev_priv, pipe);
1985         assert_sprites_disabled(dev_priv, pipe);
1986
1987         if (HAS_PCH_LPT(dev_priv->dev))
1988                 pch_transcoder = TRANSCODER_A;
1989         else
1990                 pch_transcoder = pipe;
1991
1992         /*
1993          * A pipe without a PLL won't actually be able to drive bits from
1994          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1995          * need the check.
1996          */
1997         if (!HAS_PCH_SPLIT(dev_priv->dev))
1998                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1999                         assert_dsi_pll_enabled(dev_priv);
2000                 else
2001                         assert_pll_enabled(dev_priv, pipe);
2002         else {
2003                 if (crtc->config.has_pch_encoder) {
2004                         /* if driving the PCH, we need FDI enabled */
2005                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2006                         assert_fdi_tx_pll_enabled(dev_priv,
2007                                                   (enum pipe) cpu_transcoder);
2008                 }
2009                 /* FIXME: assert CPU port conditions for SNB+ */
2010         }
2011
2012         reg = PIPECONF(cpu_transcoder);
2013         val = I915_READ(reg);
2014         if (val & PIPECONF_ENABLE) {
2015                 WARN_ON(!(pipe == PIPE_A &&
2016                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
2017                 return;
2018         }
2019
2020         I915_WRITE(reg, val | PIPECONF_ENABLE);
2021         POSTING_READ(reg);
2022 }
2023
2024 /**
2025  * intel_disable_pipe - disable a pipe, asserting requirements
2026  * @dev_priv: i915 private structure
2027  * @pipe: pipe to disable
2028  *
2029  * Disable @pipe, making sure that various hardware specific requirements
2030  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2031  *
2032  * @pipe should be %PIPE_A or %PIPE_B.
2033  *
2034  * Will wait until the pipe has shut down before returning.
2035  */
2036 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2037                                enum pipe pipe)
2038 {
2039         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2040                                                                       pipe);
2041         int reg;
2042         u32 val;
2043
2044         /*
2045          * Make sure planes won't keep trying to pump pixels to us,
2046          * or we might hang the display.
2047          */
2048         assert_planes_disabled(dev_priv, pipe);
2049         assert_cursor_disabled(dev_priv, pipe);
2050         assert_sprites_disabled(dev_priv, pipe);
2051
2052         /* Don't disable pipe A or pipe A PLLs if needed */
2053         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2054                 return;
2055
2056         reg = PIPECONF(cpu_transcoder);
2057         val = I915_READ(reg);
2058         if ((val & PIPECONF_ENABLE) == 0)
2059                 return;
2060
2061         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2062         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2063 }
2064
2065 /*
2066  * Plane regs are double buffered, going from enabled->disabled needs a
2067  * trigger in order to latch.  The display address reg provides this.
2068  */
2069 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2070                                enum plane plane)
2071 {
2072         struct drm_device *dev = dev_priv->dev;
2073         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2074
2075         I915_WRITE(reg, I915_READ(reg));
2076         POSTING_READ(reg);
2077 }
2078
2079 /**
2080  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2081  * @dev_priv: i915 private structure
2082  * @plane: plane to enable
2083  * @pipe: pipe being fed
2084  *
2085  * Enable @plane on @pipe, making sure that @pipe is running first.
2086  */
2087 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2088                                           enum plane plane, enum pipe pipe)
2089 {
2090         struct drm_device *dev = dev_priv->dev;
2091         struct intel_crtc *intel_crtc =
2092                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2093         int reg;
2094         u32 val;
2095
2096         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2097         assert_pipe_enabled(dev_priv, pipe);
2098
2099         if (intel_crtc->primary_enabled)
2100                 return;
2101
2102         intel_crtc->primary_enabled = true;
2103
2104         reg = DSPCNTR(plane);
2105         val = I915_READ(reg);
2106         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2107
2108         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2109         intel_flush_primary_plane(dev_priv, plane);
2110
2111         /*
2112          * BDW signals flip done immediately if the plane
2113          * is disabled, even if the plane enable is already
2114          * armed to occur at the next vblank :(
2115          */
2116         if (IS_BROADWELL(dev))
2117                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2118 }
2119
2120 /**
2121  * intel_disable_primary_hw_plane - disable the primary hardware plane
2122  * @dev_priv: i915 private structure
2123  * @plane: plane to disable
2124  * @pipe: pipe consuming the data
2125  *
2126  * Disable @plane; should be an independent operation.
2127  */
2128 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2129                                            enum plane plane, enum pipe pipe)
2130 {
2131         struct intel_crtc *intel_crtc =
2132                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2133         int reg;
2134         u32 val;
2135
2136         if (!intel_crtc->primary_enabled)
2137                 return;
2138
2139         intel_crtc->primary_enabled = false;
2140
2141         reg = DSPCNTR(plane);
2142         val = I915_READ(reg);
2143         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2144
2145         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2146         intel_flush_primary_plane(dev_priv, plane);
2147 }
2148
2149 static bool need_vtd_wa(struct drm_device *dev)
2150 {
2151 #ifdef CONFIG_INTEL_IOMMU
2152         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2153                 return true;
2154 #endif
2155         return false;
2156 }
2157
2158 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2159 {
2160         int tile_height;
2161
2162         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2163         return ALIGN(height, tile_height);
2164 }
2165
2166 int
2167 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2168                            struct drm_i915_gem_object *obj,
2169                            struct intel_engine_cs *pipelined)
2170 {
2171         struct drm_i915_private *dev_priv = dev->dev_private;
2172         u32 alignment;
2173         int ret;
2174
2175         switch (obj->tiling_mode) {
2176         case I915_TILING_NONE:
2177                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2178                         alignment = 128 * 1024;
2179                 else if (INTEL_INFO(dev)->gen >= 4)
2180                         alignment = 4 * 1024;
2181                 else
2182                         alignment = 64 * 1024;
2183                 break;
2184         case I915_TILING_X:
2185                 /* pin() will align the object as required by fence */
2186                 alignment = 0;
2187                 break;
2188         case I915_TILING_Y:
2189                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2190                 return -EINVAL;
2191         default:
2192                 BUG();
2193         }
2194
2195         /* Note that the w/a also requires 64 PTE of padding following the
2196          * bo. We currently fill all unused PTE with the shadow page and so
2197          * we should always have valid PTE following the scanout preventing
2198          * the VT-d warning.
2199          */
2200         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2201                 alignment = 256 * 1024;
2202
2203         dev_priv->mm.interruptible = false;
2204         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2205         if (ret)
2206                 goto err_interruptible;
2207
2208         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2209          * fence, whereas 965+ only requires a fence if using
2210          * framebuffer compression.  For simplicity, we always install
2211          * a fence as the cost is not that onerous.
2212          */
2213         ret = i915_gem_object_get_fence(obj);
2214         if (ret)
2215                 goto err_unpin;
2216
2217         i915_gem_object_pin_fence(obj);
2218
2219         dev_priv->mm.interruptible = true;
2220         return 0;
2221
2222 err_unpin:
2223         i915_gem_object_unpin_from_display_plane(obj);
2224 err_interruptible:
2225         dev_priv->mm.interruptible = true;
2226         return ret;
2227 }
2228
2229 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2230 {
2231         i915_gem_object_unpin_fence(obj);
2232         i915_gem_object_unpin_from_display_plane(obj);
2233 }
2234
2235 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2236  * is assumed to be a power-of-two. */
2237 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2238                                              unsigned int tiling_mode,
2239                                              unsigned int cpp,
2240                                              unsigned int pitch)
2241 {
2242         if (tiling_mode != I915_TILING_NONE) {
2243                 unsigned int tile_rows, tiles;
2244
2245                 tile_rows = *y / 8;
2246                 *y %= 8;
2247
2248                 tiles = *x / (512/cpp);
2249                 *x %= 512/cpp;
2250
2251                 return tile_rows * pitch * 8 + tiles * 4096;
2252         } else {
2253                 unsigned int offset;
2254
2255                 offset = *y * pitch + *x * cpp;
2256                 *y = 0;
2257                 *x = (offset & 4095) / cpp;
2258                 return offset & -4096;
2259         }
2260 }
2261
2262 int intel_format_to_fourcc(int format)
2263 {
2264         switch (format) {
2265         case DISPPLANE_8BPP:
2266                 return DRM_FORMAT_C8;
2267         case DISPPLANE_BGRX555:
2268                 return DRM_FORMAT_XRGB1555;
2269         case DISPPLANE_BGRX565:
2270                 return DRM_FORMAT_RGB565;
2271         default:
2272         case DISPPLANE_BGRX888:
2273                 return DRM_FORMAT_XRGB8888;
2274         case DISPPLANE_RGBX888:
2275                 return DRM_FORMAT_XBGR8888;
2276         case DISPPLANE_BGRX101010:
2277                 return DRM_FORMAT_XRGB2101010;
2278         case DISPPLANE_RGBX101010:
2279                 return DRM_FORMAT_XBGR2101010;
2280         }
2281 }
2282
2283 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2284                                   struct intel_plane_config *plane_config)
2285 {
2286         struct drm_device *dev = crtc->base.dev;
2287         struct drm_i915_gem_object *obj = NULL;
2288         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2289         u32 base = plane_config->base;
2290
2291         if (plane_config->size == 0)
2292                 return false;
2293
2294         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2295                                                              plane_config->size);
2296         if (!obj)
2297                 return false;
2298
2299         if (plane_config->tiled) {
2300                 obj->tiling_mode = I915_TILING_X;
2301                 obj->stride = crtc->base.primary->fb->pitches[0];
2302         }
2303
2304         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2305         mode_cmd.width = crtc->base.primary->fb->width;
2306         mode_cmd.height = crtc->base.primary->fb->height;
2307         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2308
2309         mutex_lock(&dev->struct_mutex);
2310
2311         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2312                                    &mode_cmd, obj)) {
2313                 DRM_DEBUG_KMS("intel fb init failed\n");
2314                 goto out_unref_obj;
2315         }
2316
2317         mutex_unlock(&dev->struct_mutex);
2318
2319         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2320         return true;
2321
2322 out_unref_obj:
2323         drm_gem_object_unreference(&obj->base);
2324         mutex_unlock(&dev->struct_mutex);
2325         return false;
2326 }
2327
2328 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2329                                  struct intel_plane_config *plane_config)
2330 {
2331         struct drm_device *dev = intel_crtc->base.dev;
2332         struct drm_crtc *c;
2333         struct intel_crtc *i;
2334         struct intel_framebuffer *fb;
2335
2336         if (!intel_crtc->base.primary->fb)
2337                 return;
2338
2339         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2340                 return;
2341
2342         kfree(intel_crtc->base.primary->fb);
2343         intel_crtc->base.primary->fb = NULL;
2344
2345         /*
2346          * Failed to alloc the obj, check to see if we should share
2347          * an fb with another CRTC instead
2348          */
2349         for_each_crtc(dev, c) {
2350                 i = to_intel_crtc(c);
2351
2352                 if (c == &intel_crtc->base)
2353                         continue;
2354
2355                 if (!i->active || !c->primary->fb)
2356                         continue;
2357
2358                 fb = to_intel_framebuffer(c->primary->fb);
2359                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2360                         drm_framebuffer_reference(c->primary->fb);
2361                         intel_crtc->base.primary->fb = c->primary->fb;
2362                         break;
2363                 }
2364         }
2365 }
2366
2367 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2368                                       struct drm_framebuffer *fb,
2369                                       int x, int y)
2370 {
2371         struct drm_device *dev = crtc->dev;
2372         struct drm_i915_private *dev_priv = dev->dev_private;
2373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2374         struct intel_framebuffer *intel_fb;
2375         struct drm_i915_gem_object *obj;
2376         int plane = intel_crtc->plane;
2377         unsigned long linear_offset;
2378         u32 dspcntr;
2379         u32 reg;
2380
2381         intel_fb = to_intel_framebuffer(fb);
2382         obj = intel_fb->obj;
2383
2384         reg = DSPCNTR(plane);
2385         dspcntr = I915_READ(reg);
2386         /* Mask out pixel format bits in case we change it */
2387         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2388         switch (fb->pixel_format) {
2389         case DRM_FORMAT_C8:
2390                 dspcntr |= DISPPLANE_8BPP;
2391                 break;
2392         case DRM_FORMAT_XRGB1555:
2393         case DRM_FORMAT_ARGB1555:
2394                 dspcntr |= DISPPLANE_BGRX555;
2395                 break;
2396         case DRM_FORMAT_RGB565:
2397                 dspcntr |= DISPPLANE_BGRX565;
2398                 break;
2399         case DRM_FORMAT_XRGB8888:
2400         case DRM_FORMAT_ARGB8888:
2401                 dspcntr |= DISPPLANE_BGRX888;
2402                 break;
2403         case DRM_FORMAT_XBGR8888:
2404         case DRM_FORMAT_ABGR8888:
2405                 dspcntr |= DISPPLANE_RGBX888;
2406                 break;
2407         case DRM_FORMAT_XRGB2101010:
2408         case DRM_FORMAT_ARGB2101010:
2409                 dspcntr |= DISPPLANE_BGRX101010;
2410                 break;
2411         case DRM_FORMAT_XBGR2101010:
2412         case DRM_FORMAT_ABGR2101010:
2413                 dspcntr |= DISPPLANE_RGBX101010;
2414                 break;
2415         default:
2416                 BUG();
2417         }
2418
2419         if (INTEL_INFO(dev)->gen >= 4) {
2420                 if (obj->tiling_mode != I915_TILING_NONE)
2421                         dspcntr |= DISPPLANE_TILED;
2422                 else
2423                         dspcntr &= ~DISPPLANE_TILED;
2424         }
2425
2426         if (IS_G4X(dev))
2427                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2428
2429         I915_WRITE(reg, dspcntr);
2430
2431         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2432
2433         if (INTEL_INFO(dev)->gen >= 4) {
2434                 intel_crtc->dspaddr_offset =
2435                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2436                                                        fb->bits_per_pixel / 8,
2437                                                        fb->pitches[0]);
2438                 linear_offset -= intel_crtc->dspaddr_offset;
2439         } else {
2440                 intel_crtc->dspaddr_offset = linear_offset;
2441         }
2442
2443         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2444                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2445                       fb->pitches[0]);
2446         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2447         if (INTEL_INFO(dev)->gen >= 4) {
2448                 I915_WRITE(DSPSURF(plane),
2449                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2450                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2451                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2452         } else
2453                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2454         POSTING_READ(reg);
2455 }
2456
2457 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2458                                           struct drm_framebuffer *fb,
2459                                           int x, int y)
2460 {
2461         struct drm_device *dev = crtc->dev;
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2464         struct intel_framebuffer *intel_fb;
2465         struct drm_i915_gem_object *obj;
2466         int plane = intel_crtc->plane;
2467         unsigned long linear_offset;
2468         u32 dspcntr;
2469         u32 reg;
2470
2471         intel_fb = to_intel_framebuffer(fb);
2472         obj = intel_fb->obj;
2473
2474         reg = DSPCNTR(plane);
2475         dspcntr = I915_READ(reg);
2476         /* Mask out pixel format bits in case we change it */
2477         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2478         switch (fb->pixel_format) {
2479         case DRM_FORMAT_C8:
2480                 dspcntr |= DISPPLANE_8BPP;
2481                 break;
2482         case DRM_FORMAT_RGB565:
2483                 dspcntr |= DISPPLANE_BGRX565;
2484                 break;
2485         case DRM_FORMAT_XRGB8888:
2486         case DRM_FORMAT_ARGB8888:
2487                 dspcntr |= DISPPLANE_BGRX888;
2488                 break;
2489         case DRM_FORMAT_XBGR8888:
2490         case DRM_FORMAT_ABGR8888:
2491                 dspcntr |= DISPPLANE_RGBX888;
2492                 break;
2493         case DRM_FORMAT_XRGB2101010:
2494         case DRM_FORMAT_ARGB2101010:
2495                 dspcntr |= DISPPLANE_BGRX101010;
2496                 break;
2497         case DRM_FORMAT_XBGR2101010:
2498         case DRM_FORMAT_ABGR2101010:
2499                 dspcntr |= DISPPLANE_RGBX101010;
2500                 break;
2501         default:
2502                 BUG();
2503         }
2504
2505         if (obj->tiling_mode != I915_TILING_NONE)
2506                 dspcntr |= DISPPLANE_TILED;
2507         else
2508                 dspcntr &= ~DISPPLANE_TILED;
2509
2510         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2511                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2512         else
2513                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2514
2515         I915_WRITE(reg, dspcntr);
2516
2517         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2518         intel_crtc->dspaddr_offset =
2519                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2520                                                fb->bits_per_pixel / 8,
2521                                                fb->pitches[0]);
2522         linear_offset -= intel_crtc->dspaddr_offset;
2523
2524         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2525                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2526                       fb->pitches[0]);
2527         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2528         I915_WRITE(DSPSURF(plane),
2529                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2530         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2531                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2532         } else {
2533                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2534                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2535         }
2536         POSTING_READ(reg);
2537 }
2538
2539 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2540 static int
2541 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2542                            int x, int y, enum mode_set_atomic state)
2543 {
2544         struct drm_device *dev = crtc->dev;
2545         struct drm_i915_private *dev_priv = dev->dev_private;
2546
2547         if (dev_priv->display.disable_fbc)
2548                 dev_priv->display.disable_fbc(dev);
2549         intel_increase_pllclock(crtc);
2550
2551         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2552
2553         return 0;
2554 }
2555
2556 void intel_display_handle_reset(struct drm_device *dev)
2557 {
2558         struct drm_i915_private *dev_priv = dev->dev_private;
2559         struct drm_crtc *crtc;
2560
2561         /*
2562          * Flips in the rings have been nuked by the reset,
2563          * so complete all pending flips so that user space
2564          * will get its events and not get stuck.
2565          *
2566          * Also update the base address of all primary
2567          * planes to the the last fb to make sure we're
2568          * showing the correct fb after a reset.
2569          *
2570          * Need to make two loops over the crtcs so that we
2571          * don't try to grab a crtc mutex before the
2572          * pending_flip_queue really got woken up.
2573          */
2574
2575         for_each_crtc(dev, crtc) {
2576                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2577                 enum plane plane = intel_crtc->plane;
2578
2579                 intel_prepare_page_flip(dev, plane);
2580                 intel_finish_page_flip_plane(dev, plane);
2581         }
2582
2583         for_each_crtc(dev, crtc) {
2584                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2585
2586                 drm_modeset_lock(&crtc->mutex, NULL);
2587                 /*
2588                  * FIXME: Once we have proper support for primary planes (and
2589                  * disabling them without disabling the entire crtc) allow again
2590                  * a NULL crtc->primary->fb.
2591                  */
2592                 if (intel_crtc->active && crtc->primary->fb)
2593                         dev_priv->display.update_primary_plane(crtc,
2594                                                                crtc->primary->fb,
2595                                                                crtc->x,
2596                                                                crtc->y);
2597                 drm_modeset_unlock(&crtc->mutex);
2598         }
2599 }
2600
2601 static int
2602 intel_finish_fb(struct drm_framebuffer *old_fb)
2603 {
2604         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2605         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2606         bool was_interruptible = dev_priv->mm.interruptible;
2607         int ret;
2608
2609         /* Big Hammer, we also need to ensure that any pending
2610          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2611          * current scanout is retired before unpinning the old
2612          * framebuffer.
2613          *
2614          * This should only fail upon a hung GPU, in which case we
2615          * can safely continue.
2616          */
2617         dev_priv->mm.interruptible = false;
2618         ret = i915_gem_object_finish_gpu(obj);
2619         dev_priv->mm.interruptible = was_interruptible;
2620
2621         return ret;
2622 }
2623
2624 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2625 {
2626         struct drm_device *dev = crtc->dev;
2627         struct drm_i915_private *dev_priv = dev->dev_private;
2628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2629         unsigned long flags;
2630         bool pending;
2631
2632         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2633             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2634                 return false;
2635
2636         spin_lock_irqsave(&dev->event_lock, flags);
2637         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2638         spin_unlock_irqrestore(&dev->event_lock, flags);
2639
2640         return pending;
2641 }
2642
2643 static int
2644 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2645                     struct drm_framebuffer *fb)
2646 {
2647         struct drm_device *dev = crtc->dev;
2648         struct drm_i915_private *dev_priv = dev->dev_private;
2649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2650         struct drm_framebuffer *old_fb;
2651         int ret;
2652
2653         if (intel_crtc_has_pending_flip(crtc)) {
2654                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2655                 return -EBUSY;
2656         }
2657
2658         /* no fb bound */
2659         if (!fb) {
2660                 DRM_ERROR("No FB bound\n");
2661                 return 0;
2662         }
2663
2664         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2665                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2666                           plane_name(intel_crtc->plane),
2667                           INTEL_INFO(dev)->num_pipes);
2668                 return -EINVAL;
2669         }
2670
2671         mutex_lock(&dev->struct_mutex);
2672         ret = intel_pin_and_fence_fb_obj(dev,
2673                                          to_intel_framebuffer(fb)->obj,
2674                                          NULL);
2675         mutex_unlock(&dev->struct_mutex);
2676         if (ret != 0) {
2677                 DRM_ERROR("pin & fence failed\n");
2678                 return ret;
2679         }
2680
2681         /*
2682          * Update pipe size and adjust fitter if needed: the reason for this is
2683          * that in compute_mode_changes we check the native mode (not the pfit
2684          * mode) to see if we can flip rather than do a full mode set. In the
2685          * fastboot case, we'll flip, but if we don't update the pipesrc and
2686          * pfit state, we'll end up with a big fb scanned out into the wrong
2687          * sized surface.
2688          *
2689          * To fix this properly, we need to hoist the checks up into
2690          * compute_mode_changes (or above), check the actual pfit state and
2691          * whether the platform allows pfit disable with pipe active, and only
2692          * then update the pipesrc and pfit state, even on the flip path.
2693          */
2694         if (i915.fastboot) {
2695                 const struct drm_display_mode *adjusted_mode =
2696                         &intel_crtc->config.adjusted_mode;
2697
2698                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2699                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2700                            (adjusted_mode->crtc_vdisplay - 1));
2701                 if (!intel_crtc->config.pch_pfit.enabled &&
2702                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2703                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2704                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2705                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2706                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2707                 }
2708                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2709                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2710         }
2711
2712         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2713
2714         old_fb = crtc->primary->fb;
2715         crtc->primary->fb = fb;
2716         crtc->x = x;
2717         crtc->y = y;
2718
2719         if (old_fb) {
2720                 if (intel_crtc->active && old_fb != fb)
2721                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2722                 mutex_lock(&dev->struct_mutex);
2723                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2724                 mutex_unlock(&dev->struct_mutex);
2725         }
2726
2727         mutex_lock(&dev->struct_mutex);
2728         intel_update_fbc(dev);
2729         intel_edp_psr_update(dev);
2730         mutex_unlock(&dev->struct_mutex);
2731
2732         return 0;
2733 }
2734
2735 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2736 {
2737         struct drm_device *dev = crtc->dev;
2738         struct drm_i915_private *dev_priv = dev->dev_private;
2739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740         int pipe = intel_crtc->pipe;
2741         u32 reg, temp;
2742
2743         /* enable normal train */
2744         reg = FDI_TX_CTL(pipe);
2745         temp = I915_READ(reg);
2746         if (IS_IVYBRIDGE(dev)) {
2747                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2748                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2749         } else {
2750                 temp &= ~FDI_LINK_TRAIN_NONE;
2751                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2752         }
2753         I915_WRITE(reg, temp);
2754
2755         reg = FDI_RX_CTL(pipe);
2756         temp = I915_READ(reg);
2757         if (HAS_PCH_CPT(dev)) {
2758                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2759                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2760         } else {
2761                 temp &= ~FDI_LINK_TRAIN_NONE;
2762                 temp |= FDI_LINK_TRAIN_NONE;
2763         }
2764         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2765
2766         /* wait one idle pattern time */
2767         POSTING_READ(reg);
2768         udelay(1000);
2769
2770         /* IVB wants error correction enabled */
2771         if (IS_IVYBRIDGE(dev))
2772                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2773                            FDI_FE_ERRC_ENABLE);
2774 }
2775
2776 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2777 {
2778         return crtc->base.enabled && crtc->active &&
2779                 crtc->config.has_pch_encoder;
2780 }
2781
2782 static void ivb_modeset_global_resources(struct drm_device *dev)
2783 {
2784         struct drm_i915_private *dev_priv = dev->dev_private;
2785         struct intel_crtc *pipe_B_crtc =
2786                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2787         struct intel_crtc *pipe_C_crtc =
2788                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2789         uint32_t temp;
2790
2791         /*
2792          * When everything is off disable fdi C so that we could enable fdi B
2793          * with all lanes. Note that we don't care about enabled pipes without
2794          * an enabled pch encoder.
2795          */
2796         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2797             !pipe_has_enabled_pch(pipe_C_crtc)) {
2798                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2799                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2800
2801                 temp = I915_READ(SOUTH_CHICKEN1);
2802                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2803                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2804                 I915_WRITE(SOUTH_CHICKEN1, temp);
2805         }
2806 }
2807
2808 /* The FDI link training functions for ILK/Ibexpeak. */
2809 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2810 {
2811         struct drm_device *dev = crtc->dev;
2812         struct drm_i915_private *dev_priv = dev->dev_private;
2813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2814         int pipe = intel_crtc->pipe;
2815         u32 reg, temp, tries;
2816
2817         /* FDI needs bits from pipe first */
2818         assert_pipe_enabled(dev_priv, pipe);
2819
2820         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2821            for train result */
2822         reg = FDI_RX_IMR(pipe);
2823         temp = I915_READ(reg);
2824         temp &= ~FDI_RX_SYMBOL_LOCK;
2825         temp &= ~FDI_RX_BIT_LOCK;
2826         I915_WRITE(reg, temp);
2827         I915_READ(reg);
2828         udelay(150);
2829
2830         /* enable CPU FDI TX and PCH FDI RX */
2831         reg = FDI_TX_CTL(pipe);
2832         temp = I915_READ(reg);
2833         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2834         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2835         temp &= ~FDI_LINK_TRAIN_NONE;
2836         temp |= FDI_LINK_TRAIN_PATTERN_1;
2837         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2838
2839         reg = FDI_RX_CTL(pipe);
2840         temp = I915_READ(reg);
2841         temp &= ~FDI_LINK_TRAIN_NONE;
2842         temp |= FDI_LINK_TRAIN_PATTERN_1;
2843         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2844
2845         POSTING_READ(reg);
2846         udelay(150);
2847
2848         /* Ironlake workaround, enable clock pointer after FDI enable*/
2849         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2850         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2851                    FDI_RX_PHASE_SYNC_POINTER_EN);
2852
2853         reg = FDI_RX_IIR(pipe);
2854         for (tries = 0; tries < 5; tries++) {
2855                 temp = I915_READ(reg);
2856                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2857
2858                 if ((temp & FDI_RX_BIT_LOCK)) {
2859                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2860                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2861                         break;
2862                 }
2863         }
2864         if (tries == 5)
2865                 DRM_ERROR("FDI train 1 fail!\n");
2866
2867         /* Train 2 */
2868         reg = FDI_TX_CTL(pipe);
2869         temp = I915_READ(reg);
2870         temp &= ~FDI_LINK_TRAIN_NONE;
2871         temp |= FDI_LINK_TRAIN_PATTERN_2;
2872         I915_WRITE(reg, temp);
2873
2874         reg = FDI_RX_CTL(pipe);
2875         temp = I915_READ(reg);
2876         temp &= ~FDI_LINK_TRAIN_NONE;
2877         temp |= FDI_LINK_TRAIN_PATTERN_2;
2878         I915_WRITE(reg, temp);
2879
2880         POSTING_READ(reg);
2881         udelay(150);
2882
2883         reg = FDI_RX_IIR(pipe);
2884         for (tries = 0; tries < 5; tries++) {
2885                 temp = I915_READ(reg);
2886                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2887
2888                 if (temp & FDI_RX_SYMBOL_LOCK) {
2889                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2890                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2891                         break;
2892                 }
2893         }
2894         if (tries == 5)
2895                 DRM_ERROR("FDI train 2 fail!\n");
2896
2897         DRM_DEBUG_KMS("FDI train done\n");
2898
2899 }
2900
2901 static const int snb_b_fdi_train_param[] = {
2902         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2903         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2904         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2905         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2906 };
2907
2908 /* The FDI link training functions for SNB/Cougarpoint. */
2909 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2910 {
2911         struct drm_device *dev = crtc->dev;
2912         struct drm_i915_private *dev_priv = dev->dev_private;
2913         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2914         int pipe = intel_crtc->pipe;
2915         u32 reg, temp, i, retry;
2916
2917         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2918            for train result */
2919         reg = FDI_RX_IMR(pipe);
2920         temp = I915_READ(reg);
2921         temp &= ~FDI_RX_SYMBOL_LOCK;
2922         temp &= ~FDI_RX_BIT_LOCK;
2923         I915_WRITE(reg, temp);
2924
2925         POSTING_READ(reg);
2926         udelay(150);
2927
2928         /* enable CPU FDI TX and PCH FDI RX */
2929         reg = FDI_TX_CTL(pipe);
2930         temp = I915_READ(reg);
2931         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2932         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2933         temp &= ~FDI_LINK_TRAIN_NONE;
2934         temp |= FDI_LINK_TRAIN_PATTERN_1;
2935         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2936         /* SNB-B */
2937         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2938         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2939
2940         I915_WRITE(FDI_RX_MISC(pipe),
2941                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2942
2943         reg = FDI_RX_CTL(pipe);
2944         temp = I915_READ(reg);
2945         if (HAS_PCH_CPT(dev)) {
2946                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2947                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2948         } else {
2949                 temp &= ~FDI_LINK_TRAIN_NONE;
2950                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2951         }
2952         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2953
2954         POSTING_READ(reg);
2955         udelay(150);
2956
2957         for (i = 0; i < 4; i++) {
2958                 reg = FDI_TX_CTL(pipe);
2959                 temp = I915_READ(reg);
2960                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2961                 temp |= snb_b_fdi_train_param[i];
2962                 I915_WRITE(reg, temp);
2963
2964                 POSTING_READ(reg);
2965                 udelay(500);
2966
2967                 for (retry = 0; retry < 5; retry++) {
2968                         reg = FDI_RX_IIR(pipe);
2969                         temp = I915_READ(reg);
2970                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2971                         if (temp & FDI_RX_BIT_LOCK) {
2972                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2973                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2974                                 break;
2975                         }
2976                         udelay(50);
2977                 }
2978                 if (retry < 5)
2979                         break;
2980         }
2981         if (i == 4)
2982                 DRM_ERROR("FDI train 1 fail!\n");
2983
2984         /* Train 2 */
2985         reg = FDI_TX_CTL(pipe);
2986         temp = I915_READ(reg);
2987         temp &= ~FDI_LINK_TRAIN_NONE;
2988         temp |= FDI_LINK_TRAIN_PATTERN_2;
2989         if (IS_GEN6(dev)) {
2990                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2991                 /* SNB-B */
2992                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2993         }
2994         I915_WRITE(reg, temp);
2995
2996         reg = FDI_RX_CTL(pipe);
2997         temp = I915_READ(reg);
2998         if (HAS_PCH_CPT(dev)) {
2999                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3000                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3001         } else {
3002                 temp &= ~FDI_LINK_TRAIN_NONE;
3003                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3004         }
3005         I915_WRITE(reg, temp);
3006
3007         POSTING_READ(reg);
3008         udelay(150);
3009
3010         for (i = 0; i < 4; i++) {
3011                 reg = FDI_TX_CTL(pipe);
3012                 temp = I915_READ(reg);
3013                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3014                 temp |= snb_b_fdi_train_param[i];
3015                 I915_WRITE(reg, temp);
3016
3017                 POSTING_READ(reg);
3018                 udelay(500);
3019
3020                 for (retry = 0; retry < 5; retry++) {
3021                         reg = FDI_RX_IIR(pipe);
3022                         temp = I915_READ(reg);
3023                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3024                         if (temp & FDI_RX_SYMBOL_LOCK) {
3025                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3026                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3027                                 break;
3028                         }
3029                         udelay(50);
3030                 }
3031                 if (retry < 5)
3032                         break;
3033         }
3034         if (i == 4)
3035                 DRM_ERROR("FDI train 2 fail!\n");
3036
3037         DRM_DEBUG_KMS("FDI train done.\n");
3038 }
3039
3040 /* Manual link training for Ivy Bridge A0 parts */
3041 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3042 {
3043         struct drm_device *dev = crtc->dev;
3044         struct drm_i915_private *dev_priv = dev->dev_private;
3045         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3046         int pipe = intel_crtc->pipe;
3047         u32 reg, temp, i, j;
3048
3049         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3050            for train result */
3051         reg = FDI_RX_IMR(pipe);
3052         temp = I915_READ(reg);
3053         temp &= ~FDI_RX_SYMBOL_LOCK;
3054         temp &= ~FDI_RX_BIT_LOCK;
3055         I915_WRITE(reg, temp);
3056
3057         POSTING_READ(reg);
3058         udelay(150);
3059
3060         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3061                       I915_READ(FDI_RX_IIR(pipe)));
3062
3063         /* Try each vswing and preemphasis setting twice before moving on */
3064         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3065                 /* disable first in case we need to retry */
3066                 reg = FDI_TX_CTL(pipe);
3067                 temp = I915_READ(reg);
3068                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3069                 temp &= ~FDI_TX_ENABLE;
3070                 I915_WRITE(reg, temp);
3071
3072                 reg = FDI_RX_CTL(pipe);
3073                 temp = I915_READ(reg);
3074                 temp &= ~FDI_LINK_TRAIN_AUTO;
3075                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3076                 temp &= ~FDI_RX_ENABLE;
3077                 I915_WRITE(reg, temp);
3078
3079                 /* enable CPU FDI TX and PCH FDI RX */
3080                 reg = FDI_TX_CTL(pipe);
3081                 temp = I915_READ(reg);
3082                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3083                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3084                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3085                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3086                 temp |= snb_b_fdi_train_param[j/2];
3087                 temp |= FDI_COMPOSITE_SYNC;
3088                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3089
3090                 I915_WRITE(FDI_RX_MISC(pipe),
3091                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3092
3093                 reg = FDI_RX_CTL(pipe);
3094                 temp = I915_READ(reg);
3095                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3096                 temp |= FDI_COMPOSITE_SYNC;
3097                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3098
3099                 POSTING_READ(reg);
3100                 udelay(1); /* should be 0.5us */
3101
3102                 for (i = 0; i < 4; i++) {
3103                         reg = FDI_RX_IIR(pipe);
3104                         temp = I915_READ(reg);
3105                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3106
3107                         if (temp & FDI_RX_BIT_LOCK ||
3108                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3109                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3110                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3111                                               i);
3112                                 break;
3113                         }
3114                         udelay(1); /* should be 0.5us */
3115                 }
3116                 if (i == 4) {
3117                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3118                         continue;
3119                 }
3120
3121                 /* Train 2 */
3122                 reg = FDI_TX_CTL(pipe);
3123                 temp = I915_READ(reg);
3124                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3125                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3126                 I915_WRITE(reg, temp);
3127
3128                 reg = FDI_RX_CTL(pipe);
3129                 temp = I915_READ(reg);
3130                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3131                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3132                 I915_WRITE(reg, temp);
3133
3134                 POSTING_READ(reg);
3135                 udelay(2); /* should be 1.5us */
3136
3137                 for (i = 0; i < 4; i++) {
3138                         reg = FDI_RX_IIR(pipe);
3139                         temp = I915_READ(reg);
3140                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3141
3142                         if (temp & FDI_RX_SYMBOL_LOCK ||
3143                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3144                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3145                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3146                                               i);
3147                                 goto train_done;
3148                         }
3149                         udelay(2); /* should be 1.5us */
3150                 }
3151                 if (i == 4)
3152                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3153         }
3154
3155 train_done:
3156         DRM_DEBUG_KMS("FDI train done.\n");
3157 }
3158
3159 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3160 {
3161         struct drm_device *dev = intel_crtc->base.dev;
3162         struct drm_i915_private *dev_priv = dev->dev_private;
3163         int pipe = intel_crtc->pipe;
3164         u32 reg, temp;
3165
3166
3167         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3168         reg = FDI_RX_CTL(pipe);
3169         temp = I915_READ(reg);
3170         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3171         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3172         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3173         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3174
3175         POSTING_READ(reg);
3176         udelay(200);
3177
3178         /* Switch from Rawclk to PCDclk */
3179         temp = I915_READ(reg);
3180         I915_WRITE(reg, temp | FDI_PCDCLK);
3181
3182         POSTING_READ(reg);
3183         udelay(200);
3184
3185         /* Enable CPU FDI TX PLL, always on for Ironlake */
3186         reg = FDI_TX_CTL(pipe);
3187         temp = I915_READ(reg);
3188         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3189                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3190
3191                 POSTING_READ(reg);
3192                 udelay(100);
3193         }
3194 }
3195
3196 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3197 {
3198         struct drm_device *dev = intel_crtc->base.dev;
3199         struct drm_i915_private *dev_priv = dev->dev_private;
3200         int pipe = intel_crtc->pipe;
3201         u32 reg, temp;
3202
3203         /* Switch from PCDclk to Rawclk */
3204         reg = FDI_RX_CTL(pipe);
3205         temp = I915_READ(reg);
3206         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3207
3208         /* Disable CPU FDI TX PLL */
3209         reg = FDI_TX_CTL(pipe);
3210         temp = I915_READ(reg);
3211         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3212
3213         POSTING_READ(reg);
3214         udelay(100);
3215
3216         reg = FDI_RX_CTL(pipe);
3217         temp = I915_READ(reg);
3218         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3219
3220         /* Wait for the clocks to turn off. */
3221         POSTING_READ(reg);
3222         udelay(100);
3223 }
3224
3225 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3226 {
3227         struct drm_device *dev = crtc->dev;
3228         struct drm_i915_private *dev_priv = dev->dev_private;
3229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3230         int pipe = intel_crtc->pipe;
3231         u32 reg, temp;
3232
3233         /* disable CPU FDI tx and PCH FDI rx */
3234         reg = FDI_TX_CTL(pipe);
3235         temp = I915_READ(reg);
3236         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3237         POSTING_READ(reg);
3238
3239         reg = FDI_RX_CTL(pipe);
3240         temp = I915_READ(reg);
3241         temp &= ~(0x7 << 16);
3242         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3243         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3244
3245         POSTING_READ(reg);
3246         udelay(100);
3247
3248         /* Ironlake workaround, disable clock pointer after downing FDI */
3249         if (HAS_PCH_IBX(dev))
3250                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3251
3252         /* still set train pattern 1 */
3253         reg = FDI_TX_CTL(pipe);
3254         temp = I915_READ(reg);
3255         temp &= ~FDI_LINK_TRAIN_NONE;
3256         temp |= FDI_LINK_TRAIN_PATTERN_1;
3257         I915_WRITE(reg, temp);
3258
3259         reg = FDI_RX_CTL(pipe);
3260         temp = I915_READ(reg);
3261         if (HAS_PCH_CPT(dev)) {
3262                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3263                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3264         } else {
3265                 temp &= ~FDI_LINK_TRAIN_NONE;
3266                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3267         }
3268         /* BPC in FDI rx is consistent with that in PIPECONF */
3269         temp &= ~(0x07 << 16);
3270         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3271         I915_WRITE(reg, temp);
3272
3273         POSTING_READ(reg);
3274         udelay(100);
3275 }
3276
3277 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3278 {
3279         struct intel_crtc *crtc;
3280
3281         /* Note that we don't need to be called with mode_config.lock here
3282          * as our list of CRTC objects is static for the lifetime of the
3283          * device and so cannot disappear as we iterate. Similarly, we can
3284          * happily treat the predicates as racy, atomic checks as userspace
3285          * cannot claim and pin a new fb without at least acquring the
3286          * struct_mutex and so serialising with us.
3287          */
3288         for_each_intel_crtc(dev, crtc) {
3289                 if (atomic_read(&crtc->unpin_work_count) == 0)
3290                         continue;
3291
3292                 if (crtc->unpin_work)
3293                         intel_wait_for_vblank(dev, crtc->pipe);
3294
3295                 return true;
3296         }
3297
3298         return false;
3299 }
3300
3301 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3302 {
3303         struct drm_device *dev = crtc->dev;
3304         struct drm_i915_private *dev_priv = dev->dev_private;
3305
3306         if (crtc->primary->fb == NULL)
3307                 return;
3308
3309         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3310
3311         WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3312                                    !intel_crtc_has_pending_flip(crtc),
3313                                    60*HZ) == 0);
3314
3315         mutex_lock(&dev->struct_mutex);
3316         intel_finish_fb(crtc->primary->fb);
3317         mutex_unlock(&dev->struct_mutex);
3318 }
3319
3320 /* Program iCLKIP clock to the desired frequency */
3321 static void lpt_program_iclkip(struct drm_crtc *crtc)
3322 {
3323         struct drm_device *dev = crtc->dev;
3324         struct drm_i915_private *dev_priv = dev->dev_private;
3325         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3326         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3327         u32 temp;
3328
3329         mutex_lock(&dev_priv->dpio_lock);
3330
3331         /* It is necessary to ungate the pixclk gate prior to programming
3332          * the divisors, and gate it back when it is done.
3333          */
3334         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3335
3336         /* Disable SSCCTL */
3337         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3338                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3339                                 SBI_SSCCTL_DISABLE,
3340                         SBI_ICLK);
3341
3342         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3343         if (clock == 20000) {
3344                 auxdiv = 1;
3345                 divsel = 0x41;
3346                 phaseinc = 0x20;
3347         } else {
3348                 /* The iCLK virtual clock root frequency is in MHz,
3349                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3350                  * divisors, it is necessary to divide one by another, so we
3351                  * convert the virtual clock precision to KHz here for higher
3352                  * precision.
3353                  */
3354                 u32 iclk_virtual_root_freq = 172800 * 1000;
3355                 u32 iclk_pi_range = 64;
3356                 u32 desired_divisor, msb_divisor_value, pi_value;
3357
3358                 desired_divisor = (iclk_virtual_root_freq / clock);
3359                 msb_divisor_value = desired_divisor / iclk_pi_range;
3360                 pi_value = desired_divisor % iclk_pi_range;
3361
3362                 auxdiv = 0;
3363                 divsel = msb_divisor_value - 2;
3364                 phaseinc = pi_value;
3365         }
3366
3367         /* This should not happen with any sane values */
3368         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3369                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3370         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3371                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3372
3373         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3374                         clock,
3375                         auxdiv,
3376                         divsel,
3377                         phasedir,
3378                         phaseinc);
3379
3380         /* Program SSCDIVINTPHASE6 */
3381         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3382         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3383         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3384         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3385         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3386         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3387         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3388         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3389
3390         /* Program SSCAUXDIV */
3391         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3392         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3393         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3394         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3395
3396         /* Enable modulator and associated divider */
3397         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3398         temp &= ~SBI_SSCCTL_DISABLE;
3399         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3400
3401         /* Wait for initialization time */
3402         udelay(24);
3403
3404         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3405
3406         mutex_unlock(&dev_priv->dpio_lock);
3407 }
3408
3409 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3410                                                 enum pipe pch_transcoder)
3411 {
3412         struct drm_device *dev = crtc->base.dev;
3413         struct drm_i915_private *dev_priv = dev->dev_private;
3414         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3415
3416         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3417                    I915_READ(HTOTAL(cpu_transcoder)));
3418         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3419                    I915_READ(HBLANK(cpu_transcoder)));
3420         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3421                    I915_READ(HSYNC(cpu_transcoder)));
3422
3423         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3424                    I915_READ(VTOTAL(cpu_transcoder)));
3425         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3426                    I915_READ(VBLANK(cpu_transcoder)));
3427         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3428                    I915_READ(VSYNC(cpu_transcoder)));
3429         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3430                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3431 }
3432
3433 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3434 {
3435         struct drm_i915_private *dev_priv = dev->dev_private;
3436         uint32_t temp;
3437
3438         temp = I915_READ(SOUTH_CHICKEN1);
3439         if (temp & FDI_BC_BIFURCATION_SELECT)
3440                 return;
3441
3442         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3443         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3444
3445         temp |= FDI_BC_BIFURCATION_SELECT;
3446         DRM_DEBUG_KMS("enabling fdi C rx\n");
3447         I915_WRITE(SOUTH_CHICKEN1, temp);
3448         POSTING_READ(SOUTH_CHICKEN1);
3449 }
3450
3451 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3452 {
3453         struct drm_device *dev = intel_crtc->base.dev;
3454         struct drm_i915_private *dev_priv = dev->dev_private;
3455
3456         switch (intel_crtc->pipe) {
3457         case PIPE_A:
3458                 break;
3459         case PIPE_B:
3460                 if (intel_crtc->config.fdi_lanes > 2)
3461                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3462                 else
3463                         cpt_enable_fdi_bc_bifurcation(dev);
3464
3465                 break;
3466         case PIPE_C:
3467                 cpt_enable_fdi_bc_bifurcation(dev);
3468
3469                 break;
3470         default:
3471                 BUG();
3472         }
3473 }
3474
3475 /*
3476  * Enable PCH resources required for PCH ports:
3477  *   - PCH PLLs
3478  *   - FDI training & RX/TX
3479  *   - update transcoder timings
3480  *   - DP transcoding bits
3481  *   - transcoder
3482  */
3483 static void ironlake_pch_enable(struct drm_crtc *crtc)
3484 {
3485         struct drm_device *dev = crtc->dev;
3486         struct drm_i915_private *dev_priv = dev->dev_private;
3487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3488         int pipe = intel_crtc->pipe;
3489         u32 reg, temp;
3490
3491         assert_pch_transcoder_disabled(dev_priv, pipe);
3492
3493         if (IS_IVYBRIDGE(dev))
3494                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3495
3496         /* Write the TU size bits before fdi link training, so that error
3497          * detection works. */
3498         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3499                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3500
3501         /* For PCH output, training FDI link */
3502         dev_priv->display.fdi_link_train(crtc);
3503
3504         /* We need to program the right clock selection before writing the pixel
3505          * mutliplier into the DPLL. */
3506         if (HAS_PCH_CPT(dev)) {
3507                 u32 sel;
3508
3509                 temp = I915_READ(PCH_DPLL_SEL);
3510                 temp |= TRANS_DPLL_ENABLE(pipe);
3511                 sel = TRANS_DPLLB_SEL(pipe);
3512                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3513                         temp |= sel;
3514                 else
3515                         temp &= ~sel;
3516                 I915_WRITE(PCH_DPLL_SEL, temp);
3517         }
3518
3519         /* XXX: pch pll's can be enabled any time before we enable the PCH
3520          * transcoder, and we actually should do this to not upset any PCH
3521          * transcoder that already use the clock when we share it.
3522          *
3523          * Note that enable_shared_dpll tries to do the right thing, but
3524          * get_shared_dpll unconditionally resets the pll - we need that to have
3525          * the right LVDS enable sequence. */
3526         intel_enable_shared_dpll(intel_crtc);
3527
3528         /* set transcoder timing, panel must allow it */
3529         assert_panel_unlocked(dev_priv, pipe);
3530         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3531
3532         intel_fdi_normal_train(crtc);
3533
3534         /* For PCH DP, enable TRANS_DP_CTL */
3535         if (HAS_PCH_CPT(dev) &&
3536             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3537              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3538                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3539                 reg = TRANS_DP_CTL(pipe);
3540                 temp = I915_READ(reg);
3541                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3542                           TRANS_DP_SYNC_MASK |
3543                           TRANS_DP_BPC_MASK);
3544                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3545                          TRANS_DP_ENH_FRAMING);
3546                 temp |= bpc << 9; /* same format but at 11:9 */
3547
3548                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3549                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3550                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3551                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3552
3553                 switch (intel_trans_dp_port_sel(crtc)) {
3554                 case PCH_DP_B:
3555                         temp |= TRANS_DP_PORT_SEL_B;
3556                         break;
3557                 case PCH_DP_C:
3558                         temp |= TRANS_DP_PORT_SEL_C;
3559                         break;
3560                 case PCH_DP_D:
3561                         temp |= TRANS_DP_PORT_SEL_D;
3562                         break;
3563                 default:
3564                         BUG();
3565                 }
3566
3567                 I915_WRITE(reg, temp);
3568         }
3569
3570         ironlake_enable_pch_transcoder(dev_priv, pipe);
3571 }
3572
3573 static void lpt_pch_enable(struct drm_crtc *crtc)
3574 {
3575         struct drm_device *dev = crtc->dev;
3576         struct drm_i915_private *dev_priv = dev->dev_private;
3577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3578         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3579
3580         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3581
3582         lpt_program_iclkip(crtc);
3583
3584         /* Set transcoder timing. */
3585         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3586
3587         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3588 }
3589
3590 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3591 {
3592         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3593
3594         if (pll == NULL)
3595                 return;
3596
3597         if (pll->refcount == 0) {
3598                 WARN(1, "bad %s refcount\n", pll->name);
3599                 return;
3600         }
3601
3602         if (--pll->refcount == 0) {
3603                 WARN_ON(pll->on);
3604                 WARN_ON(pll->active);
3605         }
3606
3607         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3608 }
3609
3610 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3611 {
3612         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3613         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3614         enum intel_dpll_id i;
3615
3616         if (pll) {
3617                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3618                               crtc->base.base.id, pll->name);
3619                 intel_put_shared_dpll(crtc);
3620         }
3621
3622         if (HAS_PCH_IBX(dev_priv->dev)) {
3623                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3624                 i = (enum intel_dpll_id) crtc->pipe;
3625                 pll = &dev_priv->shared_dplls[i];
3626
3627                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3628                               crtc->base.base.id, pll->name);
3629
3630                 WARN_ON(pll->refcount);
3631
3632                 goto found;
3633         }
3634
3635         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3636                 pll = &dev_priv->shared_dplls[i];
3637
3638                 /* Only want to check enabled timings first */
3639                 if (pll->refcount == 0)
3640                         continue;
3641
3642                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3643                            sizeof(pll->hw_state)) == 0) {
3644                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3645                                       crtc->base.base.id,
3646                                       pll->name, pll->refcount, pll->active);
3647
3648                         goto found;
3649                 }
3650         }
3651
3652         /* Ok no matching timings, maybe there's a free one? */
3653         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3654                 pll = &dev_priv->shared_dplls[i];
3655                 if (pll->refcount == 0) {
3656                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3657                                       crtc->base.base.id, pll->name);
3658                         goto found;
3659                 }
3660         }
3661
3662         return NULL;
3663
3664 found:
3665         if (pll->refcount == 0)
3666                 pll->hw_state = crtc->config.dpll_hw_state;
3667
3668         crtc->config.shared_dpll = i;
3669         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3670                          pipe_name(crtc->pipe));
3671
3672         pll->refcount++;
3673
3674         return pll;
3675 }
3676
3677 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3678 {
3679         struct drm_i915_private *dev_priv = dev->dev_private;
3680         int dslreg = PIPEDSL(pipe);
3681         u32 temp;
3682
3683         temp = I915_READ(dslreg);
3684         udelay(500);
3685         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3686                 if (wait_for(I915_READ(dslreg) != temp, 5))
3687                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3688         }
3689 }
3690
3691 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3692 {
3693         struct drm_device *dev = crtc->base.dev;
3694         struct drm_i915_private *dev_priv = dev->dev_private;
3695         int pipe = crtc->pipe;
3696
3697         if (crtc->config.pch_pfit.enabled) {
3698                 /* Force use of hard-coded filter coefficients
3699                  * as some pre-programmed values are broken,
3700                  * e.g. x201.
3701                  */
3702                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3703                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3704                                                  PF_PIPE_SEL_IVB(pipe));
3705                 else
3706                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3707                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3708                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3709         }
3710 }
3711
3712 static void intel_enable_planes(struct drm_crtc *crtc)
3713 {
3714         struct drm_device *dev = crtc->dev;
3715         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3716         struct drm_plane *plane;
3717         struct intel_plane *intel_plane;
3718
3719         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3720                 intel_plane = to_intel_plane(plane);
3721                 if (intel_plane->pipe == pipe)
3722                         intel_plane_restore(&intel_plane->base);
3723         }
3724 }
3725
3726 static void intel_disable_planes(struct drm_crtc *crtc)
3727 {
3728         struct drm_device *dev = crtc->dev;
3729         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3730         struct drm_plane *plane;
3731         struct intel_plane *intel_plane;
3732
3733         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3734                 intel_plane = to_intel_plane(plane);
3735                 if (intel_plane->pipe == pipe)
3736                         intel_plane_disable(&intel_plane->base);
3737         }
3738 }
3739
3740 void hsw_enable_ips(struct intel_crtc *crtc)
3741 {
3742         struct drm_device *dev = crtc->base.dev;
3743         struct drm_i915_private *dev_priv = dev->dev_private;
3744
3745         if (!crtc->config.ips_enabled)
3746                 return;
3747
3748         /* We can only enable IPS after we enable a plane and wait for a vblank */
3749         intel_wait_for_vblank(dev, crtc->pipe);
3750
3751         assert_plane_enabled(dev_priv, crtc->plane);
3752         if (IS_BROADWELL(dev)) {
3753                 mutex_lock(&dev_priv->rps.hw_lock);
3754                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3755                 mutex_unlock(&dev_priv->rps.hw_lock);
3756                 /* Quoting Art Runyan: "its not safe to expect any particular
3757                  * value in IPS_CTL bit 31 after enabling IPS through the
3758                  * mailbox." Moreover, the mailbox may return a bogus state,
3759                  * so we need to just enable it and continue on.
3760                  */
3761         } else {
3762                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3763                 /* The bit only becomes 1 in the next vblank, so this wait here
3764                  * is essentially intel_wait_for_vblank. If we don't have this
3765                  * and don't wait for vblanks until the end of crtc_enable, then
3766                  * the HW state readout code will complain that the expected
3767                  * IPS_CTL value is not the one we read. */
3768                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3769                         DRM_ERROR("Timed out waiting for IPS enable\n");
3770         }
3771 }
3772
3773 void hsw_disable_ips(struct intel_crtc *crtc)
3774 {
3775         struct drm_device *dev = crtc->base.dev;
3776         struct drm_i915_private *dev_priv = dev->dev_private;
3777
3778         if (!crtc->config.ips_enabled)
3779                 return;
3780
3781         assert_plane_enabled(dev_priv, crtc->plane);
3782         if (IS_BROADWELL(dev)) {
3783                 mutex_lock(&dev_priv->rps.hw_lock);
3784                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3785                 mutex_unlock(&dev_priv->rps.hw_lock);
3786                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3787                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3788                         DRM_ERROR("Timed out waiting for IPS disable\n");
3789         } else {
3790                 I915_WRITE(IPS_CTL, 0);
3791                 POSTING_READ(IPS_CTL);
3792         }
3793
3794         /* We need to wait for a vblank before we can disable the plane. */
3795         intel_wait_for_vblank(dev, crtc->pipe);
3796 }
3797
3798 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3799 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3800 {
3801         struct drm_device *dev = crtc->dev;
3802         struct drm_i915_private *dev_priv = dev->dev_private;
3803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3804         enum pipe pipe = intel_crtc->pipe;
3805         int palreg = PALETTE(pipe);
3806         int i;
3807         bool reenable_ips = false;
3808
3809         /* The clocks have to be on to load the palette. */
3810         if (!crtc->enabled || !intel_crtc->active)
3811                 return;
3812
3813         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3814                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3815                         assert_dsi_pll_enabled(dev_priv);
3816                 else
3817                         assert_pll_enabled(dev_priv, pipe);
3818         }
3819
3820         /* use legacy palette for Ironlake */
3821         if (HAS_PCH_SPLIT(dev))
3822                 palreg = LGC_PALETTE(pipe);
3823
3824         /* Workaround : Do not read or write the pipe palette/gamma data while
3825          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3826          */
3827         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3828             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3829              GAMMA_MODE_MODE_SPLIT)) {
3830                 hsw_disable_ips(intel_crtc);
3831                 reenable_ips = true;
3832         }
3833
3834         for (i = 0; i < 256; i++) {
3835                 I915_WRITE(palreg + 4 * i,
3836                            (intel_crtc->lut_r[i] << 16) |
3837                            (intel_crtc->lut_g[i] << 8) |
3838                            intel_crtc->lut_b[i]);
3839         }
3840
3841         if (reenable_ips)
3842                 hsw_enable_ips(intel_crtc);
3843 }
3844
3845 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3846 {
3847         if (!enable && intel_crtc->overlay) {
3848                 struct drm_device *dev = intel_crtc->base.dev;
3849                 struct drm_i915_private *dev_priv = dev->dev_private;
3850
3851                 mutex_lock(&dev->struct_mutex);
3852                 dev_priv->mm.interruptible = false;
3853                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3854                 dev_priv->mm.interruptible = true;
3855                 mutex_unlock(&dev->struct_mutex);
3856         }
3857
3858         /* Let userspace switch the overlay on again. In most cases userspace
3859          * has to recompute where to put it anyway.
3860          */
3861 }
3862
3863 /**
3864  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3865  * cursor plane briefly if not already running after enabling the display
3866  * plane.
3867  * This workaround avoids occasional blank screens when self refresh is
3868  * enabled.
3869  */
3870 static void
3871 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3872 {
3873         u32 cntl = I915_READ(CURCNTR(pipe));
3874
3875         if ((cntl & CURSOR_MODE) == 0) {
3876                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3877
3878                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3879                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3880                 intel_wait_for_vblank(dev_priv->dev, pipe);
3881                 I915_WRITE(CURCNTR(pipe), cntl);
3882                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3883                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3884         }
3885 }
3886
3887 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3888 {
3889         struct drm_device *dev = crtc->dev;
3890         struct drm_i915_private *dev_priv = dev->dev_private;
3891         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3892         int pipe = intel_crtc->pipe;
3893         int plane = intel_crtc->plane;
3894
3895         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3896         intel_enable_planes(crtc);
3897         /* The fixup needs to happen before cursor is enabled */
3898         if (IS_G4X(dev))
3899                 g4x_fixup_plane(dev_priv, pipe);
3900         intel_crtc_update_cursor(crtc, true);
3901         intel_crtc_dpms_overlay(intel_crtc, true);
3902
3903         hsw_enable_ips(intel_crtc);
3904
3905         mutex_lock(&dev->struct_mutex);
3906         intel_update_fbc(dev);
3907         intel_edp_psr_update(dev);
3908         mutex_unlock(&dev->struct_mutex);
3909 }
3910
3911 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3912 {
3913         struct drm_device *dev = crtc->dev;
3914         struct drm_i915_private *dev_priv = dev->dev_private;
3915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3916         int pipe = intel_crtc->pipe;
3917         int plane = intel_crtc->plane;
3918
3919         intel_crtc_wait_for_pending_flips(crtc);
3920         drm_crtc_vblank_off(crtc);
3921
3922         if (dev_priv->fbc.plane == plane)
3923                 intel_disable_fbc(dev);
3924
3925         hsw_disable_ips(intel_crtc);
3926
3927         intel_crtc_dpms_overlay(intel_crtc, false);
3928         intel_crtc_update_cursor(crtc, false);
3929         intel_disable_planes(crtc);
3930         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3931 }
3932
3933 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3934 {
3935         struct drm_device *dev = crtc->dev;
3936         struct drm_i915_private *dev_priv = dev->dev_private;
3937         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3938         struct intel_encoder *encoder;
3939         int pipe = intel_crtc->pipe;
3940         enum plane plane = intel_crtc->plane;
3941
3942         WARN_ON(!crtc->enabled);
3943
3944         if (intel_crtc->active)
3945                 return;
3946
3947         if (intel_crtc->config.has_pch_encoder)
3948                 intel_prepare_shared_dpll(intel_crtc);
3949
3950         if (intel_crtc->config.has_dp_encoder)
3951                 intel_dp_set_m_n(intel_crtc);
3952
3953         intel_set_pipe_timings(intel_crtc);
3954
3955         if (intel_crtc->config.has_pch_encoder) {
3956                 intel_cpu_transcoder_set_m_n(intel_crtc,
3957                                              &intel_crtc->config.fdi_m_n);
3958         }
3959
3960         ironlake_set_pipeconf(crtc);
3961
3962         /* Set up the display plane register */
3963         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3964         POSTING_READ(DSPCNTR(plane));
3965
3966         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3967                                                crtc->x, crtc->y);
3968
3969         intel_crtc->active = true;
3970
3971         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3972         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3973
3974         for_each_encoder_on_crtc(dev, crtc, encoder)
3975                 if (encoder->pre_enable)
3976                         encoder->pre_enable(encoder);
3977
3978         if (intel_crtc->config.has_pch_encoder) {
3979                 /* Note: FDI PLL enabling _must_ be done before we enable the
3980                  * cpu pipes, hence this is separate from all the other fdi/pch
3981                  * enabling. */
3982                 ironlake_fdi_pll_enable(intel_crtc);
3983         } else {
3984                 assert_fdi_tx_disabled(dev_priv, pipe);
3985                 assert_fdi_rx_disabled(dev_priv, pipe);
3986         }
3987
3988         ironlake_pfit_enable(intel_crtc);
3989
3990         /*
3991          * On ILK+ LUT must be loaded before the pipe is running but with
3992          * clocks enabled
3993          */
3994         intel_crtc_load_lut(crtc);
3995
3996         intel_update_watermarks(crtc);
3997         intel_enable_pipe(intel_crtc);
3998
3999         if (intel_crtc->config.has_pch_encoder)
4000                 ironlake_pch_enable(crtc);
4001
4002         for_each_encoder_on_crtc(dev, crtc, encoder)
4003                 encoder->enable(encoder);
4004
4005         if (HAS_PCH_CPT(dev))
4006                 cpt_verify_modeset(dev, intel_crtc->pipe);
4007
4008         intel_crtc_enable_planes(crtc);
4009
4010         drm_crtc_vblank_on(crtc);
4011 }
4012
4013 /* IPS only exists on ULT machines and is tied to pipe A. */
4014 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4015 {
4016         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4017 }
4018
4019 /*
4020  * This implements the workaround described in the "notes" section of the mode
4021  * set sequence documentation. When going from no pipes or single pipe to
4022  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4023  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4024  */
4025 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4026 {
4027         struct drm_device *dev = crtc->base.dev;
4028         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4029
4030         /* We want to get the other_active_crtc only if there's only 1 other
4031          * active crtc. */
4032         for_each_intel_crtc(dev, crtc_it) {
4033                 if (!crtc_it->active || crtc_it == crtc)
4034                         continue;
4035
4036                 if (other_active_crtc)
4037                         return;
4038
4039                 other_active_crtc = crtc_it;
4040         }
4041         if (!other_active_crtc)
4042                 return;
4043
4044         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4045         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4046 }
4047
4048 static void haswell_crtc_enable(struct drm_crtc *crtc)
4049 {
4050         struct drm_device *dev = crtc->dev;
4051         struct drm_i915_private *dev_priv = dev->dev_private;
4052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4053         struct intel_encoder *encoder;
4054         int pipe = intel_crtc->pipe;
4055         enum plane plane = intel_crtc->plane;
4056
4057         WARN_ON(!crtc->enabled);
4058
4059         if (intel_crtc->active)
4060                 return;
4061
4062         if (intel_crtc->config.has_dp_encoder)
4063                 intel_dp_set_m_n(intel_crtc);
4064
4065         intel_set_pipe_timings(intel_crtc);
4066
4067         if (intel_crtc->config.has_pch_encoder) {
4068                 intel_cpu_transcoder_set_m_n(intel_crtc,
4069                                              &intel_crtc->config.fdi_m_n);
4070         }
4071
4072         haswell_set_pipeconf(crtc);
4073
4074         intel_set_pipe_csc(crtc);
4075
4076         /* Set up the display plane register */
4077         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4078         POSTING_READ(DSPCNTR(plane));
4079
4080         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4081                                                crtc->x, crtc->y);
4082
4083         intel_crtc->active = true;
4084
4085         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4086         if (intel_crtc->config.has_pch_encoder)
4087                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4088
4089         if (intel_crtc->config.has_pch_encoder)
4090                 dev_priv->display.fdi_link_train(crtc);
4091
4092         for_each_encoder_on_crtc(dev, crtc, encoder)
4093                 if (encoder->pre_enable)
4094                         encoder->pre_enable(encoder);
4095
4096         intel_ddi_enable_pipe_clock(intel_crtc);
4097
4098         ironlake_pfit_enable(intel_crtc);
4099
4100         /*
4101          * On ILK+ LUT must be loaded before the pipe is running but with
4102          * clocks enabled
4103          */
4104         intel_crtc_load_lut(crtc);
4105
4106         intel_ddi_set_pipe_settings(crtc);
4107         intel_ddi_enable_transcoder_func(crtc);
4108
4109         intel_update_watermarks(crtc);
4110         intel_enable_pipe(intel_crtc);
4111
4112         if (intel_crtc->config.has_pch_encoder)
4113                 lpt_pch_enable(crtc);
4114
4115         for_each_encoder_on_crtc(dev, crtc, encoder) {
4116                 encoder->enable(encoder);
4117                 intel_opregion_notify_encoder(encoder, true);
4118         }
4119
4120         /* If we change the relative order between pipe/planes enabling, we need
4121          * to change the workaround. */
4122         haswell_mode_set_planes_workaround(intel_crtc);
4123         intel_crtc_enable_planes(crtc);
4124
4125         drm_crtc_vblank_on(crtc);
4126 }
4127
4128 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4129 {
4130         struct drm_device *dev = crtc->base.dev;
4131         struct drm_i915_private *dev_priv = dev->dev_private;
4132         int pipe = crtc->pipe;
4133
4134         /* To avoid upsetting the power well on haswell only disable the pfit if
4135          * it's in use. The hw state code will make sure we get this right. */
4136         if (crtc->config.pch_pfit.enabled) {
4137                 I915_WRITE(PF_CTL(pipe), 0);
4138                 I915_WRITE(PF_WIN_POS(pipe), 0);
4139                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4140         }
4141 }
4142
4143 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4144 {
4145         struct drm_device *dev = crtc->dev;
4146         struct drm_i915_private *dev_priv = dev->dev_private;
4147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4148         struct intel_encoder *encoder;
4149         int pipe = intel_crtc->pipe;
4150         u32 reg, temp;
4151
4152         if (!intel_crtc->active)
4153                 return;
4154
4155         intel_crtc_disable_planes(crtc);
4156
4157         for_each_encoder_on_crtc(dev, crtc, encoder)
4158                 encoder->disable(encoder);
4159
4160         if (intel_crtc->config.has_pch_encoder)
4161                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4162
4163         intel_disable_pipe(dev_priv, pipe);
4164
4165         ironlake_pfit_disable(intel_crtc);
4166
4167         for_each_encoder_on_crtc(dev, crtc, encoder)
4168                 if (encoder->post_disable)
4169                         encoder->post_disable(encoder);
4170
4171         if (intel_crtc->config.has_pch_encoder) {
4172                 ironlake_fdi_disable(crtc);
4173
4174                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4175                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4176
4177                 if (HAS_PCH_CPT(dev)) {
4178                         /* disable TRANS_DP_CTL */
4179                         reg = TRANS_DP_CTL(pipe);
4180                         temp = I915_READ(reg);
4181                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4182                                   TRANS_DP_PORT_SEL_MASK);
4183                         temp |= TRANS_DP_PORT_SEL_NONE;
4184                         I915_WRITE(reg, temp);
4185
4186                         /* disable DPLL_SEL */
4187                         temp = I915_READ(PCH_DPLL_SEL);
4188                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4189                         I915_WRITE(PCH_DPLL_SEL, temp);
4190                 }
4191
4192                 /* disable PCH DPLL */
4193                 intel_disable_shared_dpll(intel_crtc);
4194
4195                 ironlake_fdi_pll_disable(intel_crtc);
4196         }
4197
4198         intel_crtc->active = false;
4199         intel_update_watermarks(crtc);
4200
4201         mutex_lock(&dev->struct_mutex);
4202         intel_update_fbc(dev);
4203         intel_edp_psr_update(dev);
4204         mutex_unlock(&dev->struct_mutex);
4205 }
4206
4207 static void haswell_crtc_disable(struct drm_crtc *crtc)
4208 {
4209         struct drm_device *dev = crtc->dev;
4210         struct drm_i915_private *dev_priv = dev->dev_private;
4211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4212         struct intel_encoder *encoder;
4213         int pipe = intel_crtc->pipe;
4214         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4215
4216         if (!intel_crtc->active)
4217                 return;
4218
4219         intel_crtc_disable_planes(crtc);
4220
4221         for_each_encoder_on_crtc(dev, crtc, encoder) {
4222                 intel_opregion_notify_encoder(encoder, false);
4223                 encoder->disable(encoder);
4224         }
4225
4226         if (intel_crtc->config.has_pch_encoder)
4227                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4228         intel_disable_pipe(dev_priv, pipe);
4229
4230         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4231
4232         ironlake_pfit_disable(intel_crtc);
4233
4234         intel_ddi_disable_pipe_clock(intel_crtc);
4235
4236         for_each_encoder_on_crtc(dev, crtc, encoder)
4237                 if (encoder->post_disable)
4238                         encoder->post_disable(encoder);
4239
4240         if (intel_crtc->config.has_pch_encoder) {
4241                 lpt_disable_pch_transcoder(dev_priv);
4242                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4243                 intel_ddi_fdi_disable(crtc);
4244         }
4245
4246         intel_crtc->active = false;
4247         intel_update_watermarks(crtc);
4248
4249         mutex_lock(&dev->struct_mutex);
4250         intel_update_fbc(dev);
4251         intel_edp_psr_update(dev);
4252         mutex_unlock(&dev->struct_mutex);
4253 }
4254
4255 static void ironlake_crtc_off(struct drm_crtc *crtc)
4256 {
4257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4258         intel_put_shared_dpll(intel_crtc);
4259 }
4260
4261 static void haswell_crtc_off(struct drm_crtc *crtc)
4262 {
4263         intel_ddi_put_crtc_pll(crtc);
4264 }
4265
4266 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4267 {
4268         struct drm_device *dev = crtc->base.dev;
4269         struct drm_i915_private *dev_priv = dev->dev_private;
4270         struct intel_crtc_config *pipe_config = &crtc->config;
4271
4272         if (!crtc->config.gmch_pfit.control)
4273                 return;
4274
4275         /*
4276          * The panel fitter should only be adjusted whilst the pipe is disabled,
4277          * according to register description and PRM.
4278          */
4279         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4280         assert_pipe_disabled(dev_priv, crtc->pipe);
4281
4282         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4283         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4284
4285         /* Border color in case we don't scale up to the full screen. Black by
4286          * default, change to something else for debugging. */
4287         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4288 }
4289
4290 #define for_each_power_domain(domain, mask)                             \
4291         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4292                 if ((1 << (domain)) & (mask))
4293
4294 enum intel_display_power_domain
4295 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4296 {
4297         struct drm_device *dev = intel_encoder->base.dev;
4298         struct intel_digital_port *intel_dig_port;
4299
4300         switch (intel_encoder->type) {
4301         case INTEL_OUTPUT_UNKNOWN:
4302                 /* Only DDI platforms should ever use this output type */
4303                 WARN_ON_ONCE(!HAS_DDI(dev));
4304         case INTEL_OUTPUT_DISPLAYPORT:
4305         case INTEL_OUTPUT_HDMI:
4306         case INTEL_OUTPUT_EDP:
4307                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4308                 switch (intel_dig_port->port) {
4309                 case PORT_A:
4310                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4311                 case PORT_B:
4312                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4313                 case PORT_C:
4314                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4315                 case PORT_D:
4316                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4317                 default:
4318                         WARN_ON_ONCE(1);
4319                         return POWER_DOMAIN_PORT_OTHER;
4320                 }
4321         case INTEL_OUTPUT_ANALOG:
4322                 return POWER_DOMAIN_PORT_CRT;
4323         case INTEL_OUTPUT_DSI:
4324                 return POWER_DOMAIN_PORT_DSI;
4325         default:
4326                 return POWER_DOMAIN_PORT_OTHER;
4327         }
4328 }
4329
4330 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4331 {
4332         struct drm_device *dev = crtc->dev;
4333         struct intel_encoder *intel_encoder;
4334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4335         enum pipe pipe = intel_crtc->pipe;
4336         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4337         unsigned long mask;
4338         enum transcoder transcoder;
4339
4340         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4341
4342         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4343         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4344         if (pfit_enabled)
4345                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4346
4347         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4348                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4349
4350         return mask;
4351 }
4352
4353 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4354                                   bool enable)
4355 {
4356         if (dev_priv->power_domains.init_power_on == enable)
4357                 return;
4358
4359         if (enable)
4360                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4361         else
4362                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4363
4364         dev_priv->power_domains.init_power_on = enable;
4365 }
4366
4367 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4368 {
4369         struct drm_i915_private *dev_priv = dev->dev_private;
4370         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4371         struct intel_crtc *crtc;
4372
4373         /*
4374          * First get all needed power domains, then put all unneeded, to avoid
4375          * any unnecessary toggling of the power wells.
4376          */
4377         for_each_intel_crtc(dev, crtc) {
4378                 enum intel_display_power_domain domain;
4379
4380                 if (!crtc->base.enabled)
4381                         continue;
4382
4383                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4384
4385                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4386                         intel_display_power_get(dev_priv, domain);
4387         }
4388
4389         for_each_intel_crtc(dev, crtc) {
4390                 enum intel_display_power_domain domain;
4391
4392                 for_each_power_domain(domain, crtc->enabled_power_domains)
4393                         intel_display_power_put(dev_priv, domain);
4394
4395                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4396         }
4397
4398         intel_display_set_init_power(dev_priv, false);
4399 }
4400
4401 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4402 {
4403         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4404
4405         /* Obtain SKU information */
4406         mutex_lock(&dev_priv->dpio_lock);
4407         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4408                 CCK_FUSE_HPLL_FREQ_MASK;
4409         mutex_unlock(&dev_priv->dpio_lock);
4410
4411         return vco_freq[hpll_freq];
4412 }
4413
4414 /* Adjust CDclk dividers to allow high res or save power if possible */
4415 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4416 {
4417         struct drm_i915_private *dev_priv = dev->dev_private;
4418         u32 val, cmd;
4419
4420         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4421         dev_priv->vlv_cdclk_freq = cdclk;
4422
4423         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4424                 cmd = 2;
4425         else if (cdclk == 266)
4426                 cmd = 1;
4427         else
4428                 cmd = 0;
4429
4430         mutex_lock(&dev_priv->rps.hw_lock);
4431         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4432         val &= ~DSPFREQGUAR_MASK;
4433         val |= (cmd << DSPFREQGUAR_SHIFT);
4434         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4435         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4436                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4437                      50)) {
4438                 DRM_ERROR("timed out waiting for CDclk change\n");
4439         }
4440         mutex_unlock(&dev_priv->rps.hw_lock);
4441
4442         if (cdclk == 400) {
4443                 u32 divider, vco;
4444
4445                 vco = valleyview_get_vco(dev_priv);
4446                 divider = ((vco << 1) / cdclk) - 1;
4447
4448                 mutex_lock(&dev_priv->dpio_lock);
4449                 /* adjust cdclk divider */
4450                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4451                 val &= ~0xf;
4452                 val |= divider;
4453                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4454                 mutex_unlock(&dev_priv->dpio_lock);
4455         }
4456
4457         mutex_lock(&dev_priv->dpio_lock);
4458         /* adjust self-refresh exit latency value */
4459         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4460         val &= ~0x7f;
4461
4462         /*
4463          * For high bandwidth configs, we set a higher latency in the bunit
4464          * so that the core display fetch happens in time to avoid underruns.
4465          */
4466         if (cdclk == 400)
4467                 val |= 4500 / 250; /* 4.5 usec */
4468         else
4469                 val |= 3000 / 250; /* 3.0 usec */
4470         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4471         mutex_unlock(&dev_priv->dpio_lock);
4472
4473         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4474         intel_i2c_reset(dev);
4475 }
4476
4477 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4478 {
4479         int cur_cdclk, vco;
4480         int divider;
4481
4482         vco = valleyview_get_vco(dev_priv);
4483
4484         mutex_lock(&dev_priv->dpio_lock);
4485         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4486         mutex_unlock(&dev_priv->dpio_lock);
4487
4488         divider &= 0xf;
4489
4490         cur_cdclk = (vco << 1) / (divider + 1);
4491
4492         return cur_cdclk;
4493 }
4494
4495 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4496                                  int max_pixclk)
4497 {
4498         /*
4499          * Really only a few cases to deal with, as only 4 CDclks are supported:
4500          *   200MHz
4501          *   267MHz
4502          *   320MHz
4503          *   400MHz
4504          * So we check to see whether we're above 90% of the lower bin and
4505          * adjust if needed.
4506          */
4507         if (max_pixclk > 288000) {
4508                 return 400;
4509         } else if (max_pixclk > 240000) {
4510                 return 320;
4511         } else
4512                 return 266;
4513         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4514 }
4515
4516 /* compute the max pixel clock for new configuration */
4517 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4518 {
4519         struct drm_device *dev = dev_priv->dev;
4520         struct intel_crtc *intel_crtc;
4521         int max_pixclk = 0;
4522
4523         for_each_intel_crtc(dev, intel_crtc) {
4524                 if (intel_crtc->new_enabled)
4525                         max_pixclk = max(max_pixclk,
4526                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4527         }
4528
4529         return max_pixclk;
4530 }
4531
4532 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4533                                             unsigned *prepare_pipes)
4534 {
4535         struct drm_i915_private *dev_priv = dev->dev_private;
4536         struct intel_crtc *intel_crtc;
4537         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4538
4539         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4540             dev_priv->vlv_cdclk_freq)
4541                 return;
4542
4543         /* disable/enable all currently active pipes while we change cdclk */
4544         for_each_intel_crtc(dev, intel_crtc)
4545                 if (intel_crtc->base.enabled)
4546                         *prepare_pipes |= (1 << intel_crtc->pipe);
4547 }
4548
4549 static void valleyview_modeset_global_resources(struct drm_device *dev)
4550 {
4551         struct drm_i915_private *dev_priv = dev->dev_private;
4552         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4553         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4554
4555         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4556                 valleyview_set_cdclk(dev, req_cdclk);
4557         modeset_update_crtc_power_domains(dev);
4558 }
4559
4560 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4561 {
4562         struct drm_device *dev = crtc->dev;
4563         struct drm_i915_private *dev_priv = dev->dev_private;
4564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4565         struct intel_encoder *encoder;
4566         int pipe = intel_crtc->pipe;
4567         int plane = intel_crtc->plane;
4568         bool is_dsi;
4569         u32 dspcntr;
4570
4571         WARN_ON(!crtc->enabled);
4572
4573         if (intel_crtc->active)
4574                 return;
4575
4576         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4577
4578         if (!is_dsi && !IS_CHERRYVIEW(dev))
4579                 vlv_prepare_pll(intel_crtc);
4580
4581         /* Set up the display plane register */
4582         dspcntr = DISPPLANE_GAMMA_ENABLE;
4583
4584         if (intel_crtc->config.has_dp_encoder)
4585                 intel_dp_set_m_n(intel_crtc);
4586
4587         intel_set_pipe_timings(intel_crtc);
4588
4589         /* pipesrc and dspsize control the size that is scaled from,
4590          * which should always be the user's requested size.
4591          */
4592         I915_WRITE(DSPSIZE(plane),
4593                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4594                    (intel_crtc->config.pipe_src_w - 1));
4595         I915_WRITE(DSPPOS(plane), 0);
4596
4597         i9xx_set_pipeconf(intel_crtc);
4598
4599         I915_WRITE(DSPCNTR(plane), dspcntr);
4600         POSTING_READ(DSPCNTR(plane));
4601
4602         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4603                                                crtc->x, crtc->y);
4604
4605         intel_crtc->active = true;
4606
4607         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4608
4609         for_each_encoder_on_crtc(dev, crtc, encoder)
4610                 if (encoder->pre_pll_enable)
4611                         encoder->pre_pll_enable(encoder);
4612
4613         if (!is_dsi) {
4614                 if (IS_CHERRYVIEW(dev))
4615                         chv_enable_pll(intel_crtc);
4616                 else
4617                         vlv_enable_pll(intel_crtc);
4618         }
4619
4620         for_each_encoder_on_crtc(dev, crtc, encoder)
4621                 if (encoder->pre_enable)
4622                         encoder->pre_enable(encoder);
4623
4624         i9xx_pfit_enable(intel_crtc);
4625
4626         intel_crtc_load_lut(crtc);
4627
4628         intel_update_watermarks(crtc);
4629         intel_enable_pipe(intel_crtc);
4630
4631         for_each_encoder_on_crtc(dev, crtc, encoder)
4632                 encoder->enable(encoder);
4633
4634         intel_crtc_enable_planes(crtc);
4635
4636         drm_crtc_vblank_on(crtc);
4637
4638         /* Underruns don't raise interrupts, so check manually. */
4639         i9xx_check_fifo_underruns(dev);
4640 }
4641
4642 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4643 {
4644         struct drm_device *dev = crtc->base.dev;
4645         struct drm_i915_private *dev_priv = dev->dev_private;
4646
4647         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4648         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4649 }
4650
4651 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4652 {
4653         struct drm_device *dev = crtc->dev;
4654         struct drm_i915_private *dev_priv = dev->dev_private;
4655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4656         struct intel_encoder *encoder;
4657         int pipe = intel_crtc->pipe;
4658         int plane = intel_crtc->plane;
4659         u32 dspcntr;
4660
4661         WARN_ON(!crtc->enabled);
4662
4663         if (intel_crtc->active)
4664                 return;
4665
4666         i9xx_set_pll_dividers(intel_crtc);
4667
4668         /* Set up the display plane register */
4669         dspcntr = DISPPLANE_GAMMA_ENABLE;
4670
4671         if (pipe == 0)
4672                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4673         else
4674                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4675
4676         if (intel_crtc->config.has_dp_encoder)
4677                 intel_dp_set_m_n(intel_crtc);
4678
4679         intel_set_pipe_timings(intel_crtc);
4680
4681         /* pipesrc and dspsize control the size that is scaled from,
4682          * which should always be the user's requested size.
4683          */
4684         I915_WRITE(DSPSIZE(plane),
4685                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4686                    (intel_crtc->config.pipe_src_w - 1));
4687         I915_WRITE(DSPPOS(plane), 0);
4688
4689         i9xx_set_pipeconf(intel_crtc);
4690
4691         I915_WRITE(DSPCNTR(plane), dspcntr);
4692         POSTING_READ(DSPCNTR(plane));
4693
4694         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4695                                                crtc->x, crtc->y);
4696
4697         intel_crtc->active = true;
4698
4699         if (!IS_GEN2(dev))
4700                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4701
4702         for_each_encoder_on_crtc(dev, crtc, encoder)
4703                 if (encoder->pre_enable)
4704                         encoder->pre_enable(encoder);
4705
4706         i9xx_enable_pll(intel_crtc);
4707
4708         i9xx_pfit_enable(intel_crtc);
4709
4710         intel_crtc_load_lut(crtc);
4711
4712         intel_update_watermarks(crtc);
4713         intel_enable_pipe(intel_crtc);
4714
4715         for_each_encoder_on_crtc(dev, crtc, encoder)
4716                 encoder->enable(encoder);
4717
4718         intel_crtc_enable_planes(crtc);
4719
4720         /*
4721          * Gen2 reports pipe underruns whenever all planes are disabled.
4722          * So don't enable underrun reporting before at least some planes
4723          * are enabled.
4724          * FIXME: Need to fix the logic to work when we turn off all planes
4725          * but leave the pipe running.
4726          */
4727         if (IS_GEN2(dev))
4728                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4729
4730         drm_crtc_vblank_on(crtc);
4731
4732         /* Underruns don't raise interrupts, so check manually. */
4733         i9xx_check_fifo_underruns(dev);
4734 }
4735
4736 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4737 {
4738         struct drm_device *dev = crtc->base.dev;
4739         struct drm_i915_private *dev_priv = dev->dev_private;
4740
4741         if (!crtc->config.gmch_pfit.control)
4742                 return;
4743
4744         assert_pipe_disabled(dev_priv, crtc->pipe);
4745
4746         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4747                          I915_READ(PFIT_CONTROL));
4748         I915_WRITE(PFIT_CONTROL, 0);
4749 }
4750
4751 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4752 {
4753         struct drm_device *dev = crtc->dev;
4754         struct drm_i915_private *dev_priv = dev->dev_private;
4755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4756         struct intel_encoder *encoder;
4757         int pipe = intel_crtc->pipe;
4758
4759         if (!intel_crtc->active)
4760                 return;
4761
4762         /*
4763          * Gen2 reports pipe underruns whenever all planes are disabled.
4764          * So diasble underrun reporting before all the planes get disabled.
4765          * FIXME: Need to fix the logic to work when we turn off all planes
4766          * but leave the pipe running.
4767          */
4768         if (IS_GEN2(dev))
4769                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4770
4771         intel_crtc_disable_planes(crtc);
4772
4773         for_each_encoder_on_crtc(dev, crtc, encoder)
4774                 encoder->disable(encoder);
4775
4776         /*
4777          * On gen2 planes are double buffered but the pipe isn't, so we must
4778          * wait for planes to fully turn off before disabling the pipe.
4779          */
4780         if (IS_GEN2(dev))
4781                 intel_wait_for_vblank(dev, pipe);
4782
4783         intel_disable_pipe(dev_priv, pipe);
4784
4785         i9xx_pfit_disable(intel_crtc);
4786
4787         for_each_encoder_on_crtc(dev, crtc, encoder)
4788                 if (encoder->post_disable)
4789                         encoder->post_disable(encoder);
4790
4791         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4792                 if (IS_CHERRYVIEW(dev))
4793                         chv_disable_pll(dev_priv, pipe);
4794                 else if (IS_VALLEYVIEW(dev))
4795                         vlv_disable_pll(dev_priv, pipe);
4796                 else
4797                         i9xx_disable_pll(dev_priv, pipe);
4798         }
4799
4800         if (!IS_GEN2(dev))
4801                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4802
4803         intel_crtc->active = false;
4804         intel_update_watermarks(crtc);
4805
4806         mutex_lock(&dev->struct_mutex);
4807         intel_update_fbc(dev);
4808         intel_edp_psr_update(dev);
4809         mutex_unlock(&dev->struct_mutex);
4810 }
4811
4812 static void i9xx_crtc_off(struct drm_crtc *crtc)
4813 {
4814 }
4815
4816 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4817                                     bool enabled)
4818 {
4819         struct drm_device *dev = crtc->dev;
4820         struct drm_i915_master_private *master_priv;
4821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4822         int pipe = intel_crtc->pipe;
4823
4824         if (!dev->primary->master)
4825                 return;
4826
4827         master_priv = dev->primary->master->driver_priv;
4828         if (!master_priv->sarea_priv)
4829                 return;
4830
4831         switch (pipe) {
4832         case 0:
4833                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4834                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4835                 break;
4836         case 1:
4837                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4838                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4839                 break;
4840         default:
4841                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4842                 break;
4843         }
4844 }
4845
4846 /**
4847  * Sets the power management mode of the pipe and plane.
4848  */
4849 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4850 {
4851         struct drm_device *dev = crtc->dev;
4852         struct drm_i915_private *dev_priv = dev->dev_private;
4853         struct intel_encoder *intel_encoder;
4854         bool enable = false;
4855
4856         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4857                 enable |= intel_encoder->connectors_active;
4858
4859         if (enable)
4860                 dev_priv->display.crtc_enable(crtc);
4861         else
4862                 dev_priv->display.crtc_disable(crtc);
4863
4864         intel_crtc_update_sarea(crtc, enable);
4865 }
4866
4867 static void intel_crtc_disable(struct drm_crtc *crtc)
4868 {
4869         struct drm_device *dev = crtc->dev;
4870         struct drm_connector *connector;
4871         struct drm_i915_private *dev_priv = dev->dev_private;
4872
4873         /* crtc should still be enabled when we disable it. */
4874         WARN_ON(!crtc->enabled);
4875
4876         dev_priv->display.crtc_disable(crtc);
4877         intel_crtc_update_sarea(crtc, false);
4878         dev_priv->display.off(crtc);
4879
4880         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4881         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4882         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4883
4884         if (crtc->primary->fb) {
4885                 mutex_lock(&dev->struct_mutex);
4886                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4887                 mutex_unlock(&dev->struct_mutex);
4888                 crtc->primary->fb = NULL;
4889         }
4890
4891         /* Update computed state. */
4892         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4893                 if (!connector->encoder || !connector->encoder->crtc)
4894                         continue;
4895
4896                 if (connector->encoder->crtc != crtc)
4897                         continue;
4898
4899                 connector->dpms = DRM_MODE_DPMS_OFF;
4900                 to_intel_encoder(connector->encoder)->connectors_active = false;
4901         }
4902 }
4903
4904 void intel_encoder_destroy(struct drm_encoder *encoder)
4905 {
4906         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4907
4908         drm_encoder_cleanup(encoder);
4909         kfree(intel_encoder);
4910 }
4911
4912 /* Simple dpms helper for encoders with just one connector, no cloning and only
4913  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4914  * state of the entire output pipe. */
4915 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4916 {
4917         if (mode == DRM_MODE_DPMS_ON) {
4918                 encoder->connectors_active = true;
4919
4920                 intel_crtc_update_dpms(encoder->base.crtc);
4921         } else {
4922                 encoder->connectors_active = false;
4923
4924                 intel_crtc_update_dpms(encoder->base.crtc);
4925         }
4926 }
4927
4928 /* Cross check the actual hw state with our own modeset state tracking (and it's
4929  * internal consistency). */
4930 static void intel_connector_check_state(struct intel_connector *connector)
4931 {
4932         if (connector->get_hw_state(connector)) {
4933                 struct intel_encoder *encoder = connector->encoder;
4934                 struct drm_crtc *crtc;
4935                 bool encoder_enabled;
4936                 enum pipe pipe;
4937
4938                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4939                               connector->base.base.id,
4940                               connector->base.name);
4941
4942                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4943                      "wrong connector dpms state\n");
4944                 WARN(connector->base.encoder != &encoder->base,
4945                      "active connector not linked to encoder\n");
4946                 WARN(!encoder->connectors_active,
4947                      "encoder->connectors_active not set\n");
4948
4949                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4950                 WARN(!encoder_enabled, "encoder not enabled\n");
4951                 if (WARN_ON(!encoder->base.crtc))
4952                         return;
4953
4954                 crtc = encoder->base.crtc;
4955
4956                 WARN(!crtc->enabled, "crtc not enabled\n");
4957                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4958                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4959                      "encoder active on the wrong pipe\n");
4960         }
4961 }
4962
4963 /* Even simpler default implementation, if there's really no special case to
4964  * consider. */
4965 void intel_connector_dpms(struct drm_connector *connector, int mode)
4966 {
4967         /* All the simple cases only support two dpms states. */
4968         if (mode != DRM_MODE_DPMS_ON)
4969                 mode = DRM_MODE_DPMS_OFF;
4970
4971         if (mode == connector->dpms)
4972                 return;
4973
4974         connector->dpms = mode;
4975
4976         /* Only need to change hw state when actually enabled */
4977         if (connector->encoder)
4978                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4979
4980         intel_modeset_check_state(connector->dev);
4981 }
4982
4983 /* Simple connector->get_hw_state implementation for encoders that support only
4984  * one connector and no cloning and hence the encoder state determines the state
4985  * of the connector. */
4986 bool intel_connector_get_hw_state(struct intel_connector *connector)
4987 {
4988         enum pipe pipe = 0;
4989         struct intel_encoder *encoder = connector->encoder;
4990
4991         return encoder->get_hw_state(encoder, &pipe);
4992 }
4993
4994 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4995                                      struct intel_crtc_config *pipe_config)
4996 {
4997         struct drm_i915_private *dev_priv = dev->dev_private;
4998         struct intel_crtc *pipe_B_crtc =
4999                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5000
5001         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5002                       pipe_name(pipe), pipe_config->fdi_lanes);
5003         if (pipe_config->fdi_lanes > 4) {
5004                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5005                               pipe_name(pipe), pipe_config->fdi_lanes);
5006                 return false;
5007         }
5008
5009         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5010                 if (pipe_config->fdi_lanes > 2) {
5011                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5012                                       pipe_config->fdi_lanes);
5013                         return false;
5014                 } else {
5015                         return true;
5016                 }
5017         }
5018
5019         if (INTEL_INFO(dev)->num_pipes == 2)
5020                 return true;
5021
5022         /* Ivybridge 3 pipe is really complicated */
5023         switch (pipe) {
5024         case PIPE_A:
5025                 return true;
5026         case PIPE_B:
5027                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5028                     pipe_config->fdi_lanes > 2) {
5029                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5030                                       pipe_name(pipe), pipe_config->fdi_lanes);
5031                         return false;
5032                 }
5033                 return true;
5034         case PIPE_C:
5035                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5036                     pipe_B_crtc->config.fdi_lanes <= 2) {
5037                         if (pipe_config->fdi_lanes > 2) {
5038                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5039                                               pipe_name(pipe), pipe_config->fdi_lanes);
5040                                 return false;
5041                         }
5042                 } else {
5043                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5044                         return false;
5045                 }
5046                 return true;
5047         default:
5048                 BUG();
5049         }
5050 }
5051
5052 #define RETRY 1
5053 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5054                                        struct intel_crtc_config *pipe_config)
5055 {
5056         struct drm_device *dev = intel_crtc->base.dev;
5057         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5058         int lane, link_bw, fdi_dotclock;
5059         bool setup_ok, needs_recompute = false;
5060
5061 retry:
5062         /* FDI is a binary signal running at ~2.7GHz, encoding
5063          * each output octet as 10 bits. The actual frequency
5064          * is stored as a divider into a 100MHz clock, and the
5065          * mode pixel clock is stored in units of 1KHz.
5066          * Hence the bw of each lane in terms of the mode signal
5067          * is:
5068          */
5069         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5070
5071         fdi_dotclock = adjusted_mode->crtc_clock;
5072
5073         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5074                                            pipe_config->pipe_bpp);
5075
5076         pipe_config->fdi_lanes = lane;
5077
5078         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5079                                link_bw, &pipe_config->fdi_m_n);
5080
5081         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5082                                             intel_crtc->pipe, pipe_config);
5083         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5084                 pipe_config->pipe_bpp -= 2*3;
5085                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5086                               pipe_config->pipe_bpp);
5087                 needs_recompute = true;
5088                 pipe_config->bw_constrained = true;
5089
5090                 goto retry;
5091         }
5092
5093         if (needs_recompute)
5094                 return RETRY;
5095
5096         return setup_ok ? 0 : -EINVAL;
5097 }
5098
5099 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5100                                    struct intel_crtc_config *pipe_config)
5101 {
5102         pipe_config->ips_enabled = i915.enable_ips &&
5103                                    hsw_crtc_supports_ips(crtc) &&
5104                                    pipe_config->pipe_bpp <= 24;
5105 }
5106
5107 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5108                                      struct intel_crtc_config *pipe_config)
5109 {
5110         struct drm_device *dev = crtc->base.dev;
5111         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5112
5113         /* FIXME should check pixel clock limits on all platforms */
5114         if (INTEL_INFO(dev)->gen < 4) {
5115                 struct drm_i915_private *dev_priv = dev->dev_private;
5116                 int clock_limit =
5117                         dev_priv->display.get_display_clock_speed(dev);
5118
5119                 /*
5120                  * Enable pixel doubling when the dot clock
5121                  * is > 90% of the (display) core speed.
5122                  *
5123                  * GDG double wide on either pipe,
5124                  * otherwise pipe A only.
5125                  */
5126                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5127                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5128                         clock_limit *= 2;
5129                         pipe_config->double_wide = true;
5130                 }
5131
5132                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5133                         return -EINVAL;
5134         }
5135
5136         /*
5137          * Pipe horizontal size must be even in:
5138          * - DVO ganged mode
5139          * - LVDS dual channel mode
5140          * - Double wide pipe
5141          */
5142         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5143              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5144                 pipe_config->pipe_src_w &= ~1;
5145
5146         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5147          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5148          */
5149         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5150                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5151                 return -EINVAL;
5152
5153         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5154                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5155         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5156                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5157                  * for lvds. */
5158                 pipe_config->pipe_bpp = 8*3;
5159         }
5160
5161         if (HAS_IPS(dev))
5162                 hsw_compute_ips_config(crtc, pipe_config);
5163
5164         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5165          * clock survives for now. */
5166         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5167                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5168
5169         if (pipe_config->has_pch_encoder)
5170                 return ironlake_fdi_compute_config(crtc, pipe_config);
5171
5172         return 0;
5173 }
5174
5175 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5176 {
5177         return 400000; /* FIXME */
5178 }
5179
5180 static int i945_get_display_clock_speed(struct drm_device *dev)
5181 {
5182         return 400000;
5183 }
5184
5185 static int i915_get_display_clock_speed(struct drm_device *dev)
5186 {
5187         return 333000;
5188 }
5189
5190 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5191 {
5192         return 200000;
5193 }
5194
5195 static int pnv_get_display_clock_speed(struct drm_device *dev)
5196 {
5197         u16 gcfgc = 0;
5198
5199         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5200
5201         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5202         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5203                 return 267000;
5204         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5205                 return 333000;
5206         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5207                 return 444000;
5208         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5209                 return 200000;
5210         default:
5211                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5212         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5213                 return 133000;
5214         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5215                 return 167000;
5216         }
5217 }
5218
5219 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5220 {
5221         u16 gcfgc = 0;
5222
5223         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5224
5225         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5226                 return 133000;
5227         else {
5228                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5229                 case GC_DISPLAY_CLOCK_333_MHZ:
5230                         return 333000;
5231                 default:
5232                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5233                         return 190000;
5234                 }
5235         }
5236 }
5237
5238 static int i865_get_display_clock_speed(struct drm_device *dev)
5239 {
5240         return 266000;
5241 }
5242
5243 static int i855_get_display_clock_speed(struct drm_device *dev)
5244 {
5245         u16 hpllcc = 0;
5246         /* Assume that the hardware is in the high speed state.  This
5247          * should be the default.
5248          */
5249         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5250         case GC_CLOCK_133_200:
5251         case GC_CLOCK_100_200:
5252                 return 200000;
5253         case GC_CLOCK_166_250:
5254                 return 250000;
5255         case GC_CLOCK_100_133:
5256                 return 133000;
5257         }
5258
5259         /* Shouldn't happen */
5260         return 0;
5261 }
5262
5263 static int i830_get_display_clock_speed(struct drm_device *dev)
5264 {
5265         return 133000;
5266 }
5267
5268 static void
5269 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5270 {
5271         while (*num > DATA_LINK_M_N_MASK ||
5272                *den > DATA_LINK_M_N_MASK) {
5273                 *num >>= 1;
5274                 *den >>= 1;
5275         }
5276 }
5277
5278 static void compute_m_n(unsigned int m, unsigned int n,
5279                         uint32_t *ret_m, uint32_t *ret_n)
5280 {
5281         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5282         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5283         intel_reduce_m_n_ratio(ret_m, ret_n);
5284 }
5285
5286 void
5287 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5288                        int pixel_clock, int link_clock,
5289                        struct intel_link_m_n *m_n)
5290 {
5291         m_n->tu = 64;
5292
5293         compute_m_n(bits_per_pixel * pixel_clock,
5294                     link_clock * nlanes * 8,
5295                     &m_n->gmch_m, &m_n->gmch_n);
5296
5297         compute_m_n(pixel_clock, link_clock,
5298                     &m_n->link_m, &m_n->link_n);
5299 }
5300
5301 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5302 {
5303         if (i915.panel_use_ssc >= 0)
5304                 return i915.panel_use_ssc != 0;
5305         return dev_priv->vbt.lvds_use_ssc
5306                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5307 }
5308
5309 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5310 {
5311         struct drm_device *dev = crtc->dev;
5312         struct drm_i915_private *dev_priv = dev->dev_private;
5313         int refclk;
5314
5315         if (IS_VALLEYVIEW(dev)) {
5316                 refclk = 100000;
5317         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5318             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5319                 refclk = dev_priv->vbt.lvds_ssc_freq;
5320                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5321         } else if (!IS_GEN2(dev)) {
5322                 refclk = 96000;
5323         } else {
5324                 refclk = 48000;
5325         }
5326
5327         return refclk;
5328 }
5329
5330 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5331 {
5332         return (1 << dpll->n) << 16 | dpll->m2;
5333 }
5334
5335 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5336 {
5337         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5338 }
5339
5340 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5341                                      intel_clock_t *reduced_clock)
5342 {
5343         struct drm_device *dev = crtc->base.dev;
5344         u32 fp, fp2 = 0;
5345
5346         if (IS_PINEVIEW(dev)) {
5347                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5348                 if (reduced_clock)
5349                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5350         } else {
5351                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5352                 if (reduced_clock)
5353                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5354         }
5355
5356         crtc->config.dpll_hw_state.fp0 = fp;
5357
5358         crtc->lowfreq_avail = false;
5359         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5360             reduced_clock && i915.powersave) {
5361                 crtc->config.dpll_hw_state.fp1 = fp2;
5362                 crtc->lowfreq_avail = true;
5363         } else {
5364                 crtc->config.dpll_hw_state.fp1 = fp;
5365         }
5366 }
5367
5368 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5369                 pipe)
5370 {
5371         u32 reg_val;
5372
5373         /*
5374          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5375          * and set it to a reasonable value instead.
5376          */
5377         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5378         reg_val &= 0xffffff00;
5379         reg_val |= 0x00000030;
5380         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5381
5382         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5383         reg_val &= 0x8cffffff;
5384         reg_val = 0x8c000000;
5385         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5386
5387         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5388         reg_val &= 0xffffff00;
5389         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5390
5391         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5392         reg_val &= 0x00ffffff;
5393         reg_val |= 0xb0000000;
5394         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5395 }
5396
5397 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5398                                          struct intel_link_m_n *m_n)
5399 {
5400         struct drm_device *dev = crtc->base.dev;
5401         struct drm_i915_private *dev_priv = dev->dev_private;
5402         int pipe = crtc->pipe;
5403
5404         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5405         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5406         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5407         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5408 }
5409
5410 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5411                                          struct intel_link_m_n *m_n)
5412 {
5413         struct drm_device *dev = crtc->base.dev;
5414         struct drm_i915_private *dev_priv = dev->dev_private;
5415         int pipe = crtc->pipe;
5416         enum transcoder transcoder = crtc->config.cpu_transcoder;
5417
5418         if (INTEL_INFO(dev)->gen >= 5) {
5419                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5420                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5421                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5422                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5423         } else {
5424                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5425                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5426                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5427                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5428         }
5429 }
5430
5431 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5432 {
5433         if (crtc->config.has_pch_encoder)
5434                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5435         else
5436                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5437 }
5438
5439 static void vlv_update_pll(struct intel_crtc *crtc)
5440 {
5441         u32 dpll, dpll_md;
5442
5443         /*
5444          * Enable DPIO clock input. We should never disable the reference
5445          * clock for pipe B, since VGA hotplug / manual detection depends
5446          * on it.
5447          */
5448         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5449                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5450         /* We should never disable this, set it here for state tracking */
5451         if (crtc->pipe == PIPE_B)
5452                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5453         dpll |= DPLL_VCO_ENABLE;
5454         crtc->config.dpll_hw_state.dpll = dpll;
5455
5456         dpll_md = (crtc->config.pixel_multiplier - 1)
5457                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5458         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5459 }
5460
5461 static void vlv_prepare_pll(struct intel_crtc *crtc)
5462 {
5463         struct drm_device *dev = crtc->base.dev;
5464         struct drm_i915_private *dev_priv = dev->dev_private;
5465         int pipe = crtc->pipe;
5466         u32 mdiv;
5467         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5468         u32 coreclk, reg_val;
5469
5470         mutex_lock(&dev_priv->dpio_lock);
5471
5472         bestn = crtc->config.dpll.n;
5473         bestm1 = crtc->config.dpll.m1;
5474         bestm2 = crtc->config.dpll.m2;
5475         bestp1 = crtc->config.dpll.p1;
5476         bestp2 = crtc->config.dpll.p2;
5477
5478         /* See eDP HDMI DPIO driver vbios notes doc */
5479
5480         /* PLL B needs special handling */
5481         if (pipe == PIPE_B)
5482                 vlv_pllb_recal_opamp(dev_priv, pipe);
5483
5484         /* Set up Tx target for periodic Rcomp update */
5485         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5486
5487         /* Disable target IRef on PLL */
5488         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5489         reg_val &= 0x00ffffff;
5490         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5491
5492         /* Disable fast lock */
5493         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5494
5495         /* Set idtafcrecal before PLL is enabled */
5496         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5497         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5498         mdiv |= ((bestn << DPIO_N_SHIFT));
5499         mdiv |= (1 << DPIO_K_SHIFT);
5500
5501         /*
5502          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5503          * but we don't support that).
5504          * Note: don't use the DAC post divider as it seems unstable.
5505          */
5506         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5507         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5508
5509         mdiv |= DPIO_ENABLE_CALIBRATION;
5510         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5511
5512         /* Set HBR and RBR LPF coefficients */
5513         if (crtc->config.port_clock == 162000 ||
5514             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5515             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5516                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5517                                  0x009f0003);
5518         else
5519                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5520                                  0x00d0000f);
5521
5522         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5523             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5524                 /* Use SSC source */
5525                 if (pipe == PIPE_A)
5526                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5527                                          0x0df40000);
5528                 else
5529                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5530                                          0x0df70000);
5531         } else { /* HDMI or VGA */
5532                 /* Use bend source */
5533                 if (pipe == PIPE_A)
5534                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5535                                          0x0df70000);
5536                 else
5537                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5538                                          0x0df40000);
5539         }
5540
5541         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5542         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5543         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5544             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5545                 coreclk |= 0x01000000;
5546         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5547
5548         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5549         mutex_unlock(&dev_priv->dpio_lock);
5550 }
5551
5552 static void chv_update_pll(struct intel_crtc *crtc)
5553 {
5554         struct drm_device *dev = crtc->base.dev;
5555         struct drm_i915_private *dev_priv = dev->dev_private;
5556         int pipe = crtc->pipe;
5557         int dpll_reg = DPLL(crtc->pipe);
5558         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5559         u32 loopfilter, intcoeff;
5560         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5561         int refclk;
5562
5563         crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5564                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5565                 DPLL_VCO_ENABLE;
5566         if (pipe != PIPE_A)
5567                 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5568
5569         crtc->config.dpll_hw_state.dpll_md =
5570                 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5571
5572         bestn = crtc->config.dpll.n;
5573         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5574         bestm1 = crtc->config.dpll.m1;
5575         bestm2 = crtc->config.dpll.m2 >> 22;
5576         bestp1 = crtc->config.dpll.p1;
5577         bestp2 = crtc->config.dpll.p2;
5578
5579         /*
5580          * Enable Refclk and SSC
5581          */
5582         I915_WRITE(dpll_reg,
5583                    crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5584
5585         mutex_lock(&dev_priv->dpio_lock);
5586
5587         /* p1 and p2 divider */
5588         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5589                         5 << DPIO_CHV_S1_DIV_SHIFT |
5590                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5591                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5592                         1 << DPIO_CHV_K_DIV_SHIFT);
5593
5594         /* Feedback post-divider - m2 */
5595         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5596
5597         /* Feedback refclk divider - n and m1 */
5598         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5599                         DPIO_CHV_M1_DIV_BY_2 |
5600                         1 << DPIO_CHV_N_DIV_SHIFT);
5601
5602         /* M2 fraction division */
5603         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5604
5605         /* M2 fraction division enable */
5606         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5607                        DPIO_CHV_FRAC_DIV_EN |
5608                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5609
5610         /* Loop filter */
5611         refclk = i9xx_get_refclk(&crtc->base, 0);
5612         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5613                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5614         if (refclk == 100000)
5615                 intcoeff = 11;
5616         else if (refclk == 38400)
5617                 intcoeff = 10;
5618         else
5619                 intcoeff = 9;
5620         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5621         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5622
5623         /* AFC Recal */
5624         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5625                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5626                         DPIO_AFC_RECAL);
5627
5628         mutex_unlock(&dev_priv->dpio_lock);
5629 }
5630
5631 static void i9xx_update_pll(struct intel_crtc *crtc,
5632                             intel_clock_t *reduced_clock,
5633                             int num_connectors)
5634 {
5635         struct drm_device *dev = crtc->base.dev;
5636         struct drm_i915_private *dev_priv = dev->dev_private;
5637         u32 dpll;
5638         bool is_sdvo;
5639         struct dpll *clock = &crtc->config.dpll;
5640
5641         i9xx_update_pll_dividers(crtc, reduced_clock);
5642
5643         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5644                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5645
5646         dpll = DPLL_VGA_MODE_DIS;
5647
5648         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5649                 dpll |= DPLLB_MODE_LVDS;
5650         else
5651                 dpll |= DPLLB_MODE_DAC_SERIAL;
5652
5653         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5654                 dpll |= (crtc->config.pixel_multiplier - 1)
5655                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5656         }
5657
5658         if (is_sdvo)
5659                 dpll |= DPLL_SDVO_HIGH_SPEED;
5660
5661         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5662                 dpll |= DPLL_SDVO_HIGH_SPEED;
5663
5664         /* compute bitmask from p1 value */
5665         if (IS_PINEVIEW(dev))
5666                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5667         else {
5668                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5669                 if (IS_G4X(dev) && reduced_clock)
5670                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5671         }
5672         switch (clock->p2) {
5673         case 5:
5674                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5675                 break;
5676         case 7:
5677                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5678                 break;
5679         case 10:
5680                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5681                 break;
5682         case 14:
5683                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5684                 break;
5685         }
5686         if (INTEL_INFO(dev)->gen >= 4)
5687                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5688
5689         if (crtc->config.sdvo_tv_clock)
5690                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5691         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5692                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5693                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5694         else
5695                 dpll |= PLL_REF_INPUT_DREFCLK;
5696
5697         dpll |= DPLL_VCO_ENABLE;
5698         crtc->config.dpll_hw_state.dpll = dpll;
5699
5700         if (INTEL_INFO(dev)->gen >= 4) {
5701                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5702                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5703                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5704         }
5705 }
5706
5707 static void i8xx_update_pll(struct intel_crtc *crtc,
5708                             intel_clock_t *reduced_clock,
5709                             int num_connectors)
5710 {
5711         struct drm_device *dev = crtc->base.dev;
5712         struct drm_i915_private *dev_priv = dev->dev_private;
5713         u32 dpll;
5714         struct dpll *clock = &crtc->config.dpll;
5715
5716         i9xx_update_pll_dividers(crtc, reduced_clock);
5717
5718         dpll = DPLL_VGA_MODE_DIS;
5719
5720         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5721                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5722         } else {
5723                 if (clock->p1 == 2)
5724                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5725                 else
5726                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5727                 if (clock->p2 == 4)
5728                         dpll |= PLL_P2_DIVIDE_BY_4;
5729         }
5730
5731         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5732                 dpll |= DPLL_DVO_2X_MODE;
5733
5734         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5735                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5736                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5737         else
5738                 dpll |= PLL_REF_INPUT_DREFCLK;
5739
5740         dpll |= DPLL_VCO_ENABLE;
5741         crtc->config.dpll_hw_state.dpll = dpll;
5742 }
5743
5744 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5745 {
5746         struct drm_device *dev = intel_crtc->base.dev;
5747         struct drm_i915_private *dev_priv = dev->dev_private;
5748         enum pipe pipe = intel_crtc->pipe;
5749         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5750         struct drm_display_mode *adjusted_mode =
5751                 &intel_crtc->config.adjusted_mode;
5752         uint32_t crtc_vtotal, crtc_vblank_end;
5753         int vsyncshift = 0;
5754
5755         /* We need to be careful not to changed the adjusted mode, for otherwise
5756          * the hw state checker will get angry at the mismatch. */
5757         crtc_vtotal = adjusted_mode->crtc_vtotal;
5758         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5759
5760         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5761                 /* the chip adds 2 halflines automatically */
5762                 crtc_vtotal -= 1;
5763                 crtc_vblank_end -= 1;
5764
5765                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5766                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5767                 else
5768                         vsyncshift = adjusted_mode->crtc_hsync_start -
5769                                 adjusted_mode->crtc_htotal / 2;
5770                 if (vsyncshift < 0)
5771                         vsyncshift += adjusted_mode->crtc_htotal;
5772         }
5773
5774         if (INTEL_INFO(dev)->gen > 3)
5775                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5776
5777         I915_WRITE(HTOTAL(cpu_transcoder),
5778                    (adjusted_mode->crtc_hdisplay - 1) |
5779                    ((adjusted_mode->crtc_htotal - 1) << 16));
5780         I915_WRITE(HBLANK(cpu_transcoder),
5781                    (adjusted_mode->crtc_hblank_start - 1) |
5782                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5783         I915_WRITE(HSYNC(cpu_transcoder),
5784                    (adjusted_mode->crtc_hsync_start - 1) |
5785                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5786
5787         I915_WRITE(VTOTAL(cpu_transcoder),
5788                    (adjusted_mode->crtc_vdisplay - 1) |
5789                    ((crtc_vtotal - 1) << 16));
5790         I915_WRITE(VBLANK(cpu_transcoder),
5791                    (adjusted_mode->crtc_vblank_start - 1) |
5792                    ((crtc_vblank_end - 1) << 16));
5793         I915_WRITE(VSYNC(cpu_transcoder),
5794                    (adjusted_mode->crtc_vsync_start - 1) |
5795                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5796
5797         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5798          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5799          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5800          * bits. */
5801         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5802             (pipe == PIPE_B || pipe == PIPE_C))
5803                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5804
5805         /* pipesrc controls the size that is scaled from, which should
5806          * always be the user's requested size.
5807          */
5808         I915_WRITE(PIPESRC(pipe),
5809                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5810                    (intel_crtc->config.pipe_src_h - 1));
5811 }
5812
5813 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5814                                    struct intel_crtc_config *pipe_config)
5815 {
5816         struct drm_device *dev = crtc->base.dev;
5817         struct drm_i915_private *dev_priv = dev->dev_private;
5818         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5819         uint32_t tmp;
5820
5821         tmp = I915_READ(HTOTAL(cpu_transcoder));
5822         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5823         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5824         tmp = I915_READ(HBLANK(cpu_transcoder));
5825         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5826         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5827         tmp = I915_READ(HSYNC(cpu_transcoder));
5828         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5829         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5830
5831         tmp = I915_READ(VTOTAL(cpu_transcoder));
5832         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5833         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5834         tmp = I915_READ(VBLANK(cpu_transcoder));
5835         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5836         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5837         tmp = I915_READ(VSYNC(cpu_transcoder));
5838         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5839         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5840
5841         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5842                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5843                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5844                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5845         }
5846
5847         tmp = I915_READ(PIPESRC(crtc->pipe));
5848         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5849         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5850
5851         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5852         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5853 }
5854
5855 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5856                                  struct intel_crtc_config *pipe_config)
5857 {
5858         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5859         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5860         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5861         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5862
5863         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5864         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5865         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5866         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5867
5868         mode->flags = pipe_config->adjusted_mode.flags;
5869
5870         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5871         mode->flags |= pipe_config->adjusted_mode.flags;
5872 }
5873
5874 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5875 {
5876         struct drm_device *dev = intel_crtc->base.dev;
5877         struct drm_i915_private *dev_priv = dev->dev_private;
5878         uint32_t pipeconf;
5879
5880         pipeconf = 0;
5881
5882         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5883             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5884                 pipeconf |= PIPECONF_ENABLE;
5885
5886         if (intel_crtc->config.double_wide)
5887                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5888
5889         /* only g4x and later have fancy bpc/dither controls */
5890         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5891                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5892                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5893                         pipeconf |= PIPECONF_DITHER_EN |
5894                                     PIPECONF_DITHER_TYPE_SP;
5895
5896                 switch (intel_crtc->config.pipe_bpp) {
5897                 case 18:
5898                         pipeconf |= PIPECONF_6BPC;
5899                         break;
5900                 case 24:
5901                         pipeconf |= PIPECONF_8BPC;
5902                         break;
5903                 case 30:
5904                         pipeconf |= PIPECONF_10BPC;
5905                         break;
5906                 default:
5907                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5908                         BUG();
5909                 }
5910         }
5911
5912         if (HAS_PIPE_CXSR(dev)) {
5913                 if (intel_crtc->lowfreq_avail) {
5914                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5915                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5916                 } else {
5917                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5918                 }
5919         }
5920
5921         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5922                 if (INTEL_INFO(dev)->gen < 4 ||
5923                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5924                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5925                 else
5926                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5927         } else
5928                 pipeconf |= PIPECONF_PROGRESSIVE;
5929
5930         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5931                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5932
5933         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5934         POSTING_READ(PIPECONF(intel_crtc->pipe));
5935 }
5936
5937 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5938                               int x, int y,
5939                               struct drm_framebuffer *fb)
5940 {
5941         struct drm_device *dev = crtc->dev;
5942         struct drm_i915_private *dev_priv = dev->dev_private;
5943         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5944         int refclk, num_connectors = 0;
5945         intel_clock_t clock, reduced_clock;
5946         bool ok, has_reduced_clock = false;
5947         bool is_lvds = false, is_dsi = false;
5948         struct intel_encoder *encoder;
5949         const intel_limit_t *limit;
5950
5951         for_each_encoder_on_crtc(dev, crtc, encoder) {
5952                 switch (encoder->type) {
5953                 case INTEL_OUTPUT_LVDS:
5954                         is_lvds = true;
5955                         break;
5956                 case INTEL_OUTPUT_DSI:
5957                         is_dsi = true;
5958                         break;
5959                 }
5960
5961                 num_connectors++;
5962         }
5963
5964         if (is_dsi)
5965                 return 0;
5966
5967         if (!intel_crtc->config.clock_set) {
5968                 refclk = i9xx_get_refclk(crtc, num_connectors);
5969
5970                 /*
5971                  * Returns a set of divisors for the desired target clock with
5972                  * the given refclk, or FALSE.  The returned values represent
5973                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5974                  * 2) / p1 / p2.
5975                  */
5976                 limit = intel_limit(crtc, refclk);
5977                 ok = dev_priv->display.find_dpll(limit, crtc,
5978                                                  intel_crtc->config.port_clock,
5979                                                  refclk, NULL, &clock);
5980                 if (!ok) {
5981                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5982                         return -EINVAL;
5983                 }
5984
5985                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5986                         /*
5987                          * Ensure we match the reduced clock's P to the target
5988                          * clock.  If the clocks don't match, we can't switch
5989                          * the display clock by using the FP0/FP1. In such case
5990                          * we will disable the LVDS downclock feature.
5991                          */
5992                         has_reduced_clock =
5993                                 dev_priv->display.find_dpll(limit, crtc,
5994                                                             dev_priv->lvds_downclock,
5995                                                             refclk, &clock,
5996                                                             &reduced_clock);
5997                 }
5998                 /* Compat-code for transition, will disappear. */
5999                 intel_crtc->config.dpll.n = clock.n;
6000                 intel_crtc->config.dpll.m1 = clock.m1;
6001                 intel_crtc->config.dpll.m2 = clock.m2;
6002                 intel_crtc->config.dpll.p1 = clock.p1;
6003                 intel_crtc->config.dpll.p2 = clock.p2;
6004         }
6005
6006         if (IS_GEN2(dev)) {
6007                 i8xx_update_pll(intel_crtc,
6008                                 has_reduced_clock ? &reduced_clock : NULL,
6009                                 num_connectors);
6010         } else if (IS_CHERRYVIEW(dev)) {
6011                 chv_update_pll(intel_crtc);
6012         } else if (IS_VALLEYVIEW(dev)) {
6013                 vlv_update_pll(intel_crtc);
6014         } else {
6015                 i9xx_update_pll(intel_crtc,
6016                                 has_reduced_clock ? &reduced_clock : NULL,
6017                                 num_connectors);
6018         }
6019
6020         return 0;
6021 }
6022
6023 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6024                                  struct intel_crtc_config *pipe_config)
6025 {
6026         struct drm_device *dev = crtc->base.dev;
6027         struct drm_i915_private *dev_priv = dev->dev_private;
6028         uint32_t tmp;
6029
6030         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6031                 return;
6032
6033         tmp = I915_READ(PFIT_CONTROL);
6034         if (!(tmp & PFIT_ENABLE))
6035                 return;
6036
6037         /* Check whether the pfit is attached to our pipe. */
6038         if (INTEL_INFO(dev)->gen < 4) {
6039                 if (crtc->pipe != PIPE_B)
6040                         return;
6041         } else {
6042                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6043                         return;
6044         }
6045
6046         pipe_config->gmch_pfit.control = tmp;
6047         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6048         if (INTEL_INFO(dev)->gen < 5)
6049                 pipe_config->gmch_pfit.lvds_border_bits =
6050                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6051 }
6052
6053 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6054                                struct intel_crtc_config *pipe_config)
6055 {
6056         struct drm_device *dev = crtc->base.dev;
6057         struct drm_i915_private *dev_priv = dev->dev_private;
6058         int pipe = pipe_config->cpu_transcoder;
6059         intel_clock_t clock;
6060         u32 mdiv;
6061         int refclk = 100000;
6062
6063         mutex_lock(&dev_priv->dpio_lock);
6064         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6065         mutex_unlock(&dev_priv->dpio_lock);
6066
6067         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6068         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6069         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6070         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6071         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6072
6073         vlv_clock(refclk, &clock);
6074
6075         /* clock.dot is the fast clock */
6076         pipe_config->port_clock = clock.dot / 5;
6077 }
6078
6079 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6080                                   struct intel_plane_config *plane_config)
6081 {
6082         struct drm_device *dev = crtc->base.dev;
6083         struct drm_i915_private *dev_priv = dev->dev_private;
6084         u32 val, base, offset;
6085         int pipe = crtc->pipe, plane = crtc->plane;
6086         int fourcc, pixel_format;
6087         int aligned_height;
6088
6089         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6090         if (!crtc->base.primary->fb) {
6091                 DRM_DEBUG_KMS("failed to alloc fb\n");
6092                 return;
6093         }
6094
6095         val = I915_READ(DSPCNTR(plane));
6096
6097         if (INTEL_INFO(dev)->gen >= 4)
6098                 if (val & DISPPLANE_TILED)
6099                         plane_config->tiled = true;
6100
6101         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6102         fourcc = intel_format_to_fourcc(pixel_format);
6103         crtc->base.primary->fb->pixel_format = fourcc;
6104         crtc->base.primary->fb->bits_per_pixel =
6105                 drm_format_plane_cpp(fourcc, 0) * 8;
6106
6107         if (INTEL_INFO(dev)->gen >= 4) {
6108                 if (plane_config->tiled)
6109                         offset = I915_READ(DSPTILEOFF(plane));
6110                 else
6111                         offset = I915_READ(DSPLINOFF(plane));
6112                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6113         } else {
6114                 base = I915_READ(DSPADDR(plane));
6115         }
6116         plane_config->base = base;
6117
6118         val = I915_READ(PIPESRC(pipe));
6119         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6120         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6121
6122         val = I915_READ(DSPSTRIDE(pipe));
6123         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6124
6125         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6126                                             plane_config->tiled);
6127
6128         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6129                                    aligned_height, PAGE_SIZE);
6130
6131         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6132                       pipe, plane, crtc->base.primary->fb->width,
6133                       crtc->base.primary->fb->height,
6134                       crtc->base.primary->fb->bits_per_pixel, base,
6135                       crtc->base.primary->fb->pitches[0],
6136                       plane_config->size);
6137
6138 }
6139
6140 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6141                                struct intel_crtc_config *pipe_config)
6142 {
6143         struct drm_device *dev = crtc->base.dev;
6144         struct drm_i915_private *dev_priv = dev->dev_private;
6145         int pipe = pipe_config->cpu_transcoder;
6146         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6147         intel_clock_t clock;
6148         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6149         int refclk = 100000;
6150
6151         mutex_lock(&dev_priv->dpio_lock);
6152         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6153         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6154         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6155         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6156         mutex_unlock(&dev_priv->dpio_lock);
6157
6158         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6159         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6160         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6161         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6162         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6163
6164         chv_clock(refclk, &clock);
6165
6166         /* clock.dot is the fast clock */
6167         pipe_config->port_clock = clock.dot / 5;
6168 }
6169
6170 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6171                                  struct intel_crtc_config *pipe_config)
6172 {
6173         struct drm_device *dev = crtc->base.dev;
6174         struct drm_i915_private *dev_priv = dev->dev_private;
6175         uint32_t tmp;
6176
6177         if (!intel_display_power_enabled(dev_priv,
6178                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6179                 return false;
6180
6181         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6182         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6183
6184         tmp = I915_READ(PIPECONF(crtc->pipe));
6185         if (!(tmp & PIPECONF_ENABLE))
6186                 return false;
6187
6188         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6189                 switch (tmp & PIPECONF_BPC_MASK) {
6190                 case PIPECONF_6BPC:
6191                         pipe_config->pipe_bpp = 18;
6192                         break;
6193                 case PIPECONF_8BPC:
6194                         pipe_config->pipe_bpp = 24;
6195                         break;
6196                 case PIPECONF_10BPC:
6197                         pipe_config->pipe_bpp = 30;
6198                         break;
6199                 default:
6200                         break;
6201                 }
6202         }
6203
6204         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6205                 pipe_config->limited_color_range = true;
6206
6207         if (INTEL_INFO(dev)->gen < 4)
6208                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6209
6210         intel_get_pipe_timings(crtc, pipe_config);
6211
6212         i9xx_get_pfit_config(crtc, pipe_config);
6213
6214         if (INTEL_INFO(dev)->gen >= 4) {
6215                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6216                 pipe_config->pixel_multiplier =
6217                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6218                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6219                 pipe_config->dpll_hw_state.dpll_md = tmp;
6220         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6221                 tmp = I915_READ(DPLL(crtc->pipe));
6222                 pipe_config->pixel_multiplier =
6223                         ((tmp & SDVO_MULTIPLIER_MASK)
6224                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6225         } else {
6226                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6227                  * port and will be fixed up in the encoder->get_config
6228                  * function. */
6229                 pipe_config->pixel_multiplier = 1;
6230         }
6231         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6232         if (!IS_VALLEYVIEW(dev)) {
6233                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6234                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6235         } else {
6236                 /* Mask out read-only status bits. */
6237                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6238                                                      DPLL_PORTC_READY_MASK |
6239                                                      DPLL_PORTB_READY_MASK);
6240         }
6241
6242         if (IS_CHERRYVIEW(dev))
6243                 chv_crtc_clock_get(crtc, pipe_config);
6244         else if (IS_VALLEYVIEW(dev))
6245                 vlv_crtc_clock_get(crtc, pipe_config);
6246         else
6247                 i9xx_crtc_clock_get(crtc, pipe_config);
6248
6249         return true;
6250 }
6251
6252 static void ironlake_init_pch_refclk(struct drm_device *dev)
6253 {
6254         struct drm_i915_private *dev_priv = dev->dev_private;
6255         struct drm_mode_config *mode_config = &dev->mode_config;
6256         struct intel_encoder *encoder;
6257         u32 val, final;
6258         bool has_lvds = false;
6259         bool has_cpu_edp = false;
6260         bool has_panel = false;
6261         bool has_ck505 = false;
6262         bool can_ssc = false;
6263
6264         /* We need to take the global config into account */
6265         list_for_each_entry(encoder, &mode_config->encoder_list,
6266                             base.head) {
6267                 switch (encoder->type) {
6268                 case INTEL_OUTPUT_LVDS:
6269                         has_panel = true;
6270                         has_lvds = true;
6271                         break;
6272                 case INTEL_OUTPUT_EDP:
6273                         has_panel = true;
6274                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6275                                 has_cpu_edp = true;
6276                         break;
6277                 }
6278         }
6279
6280         if (HAS_PCH_IBX(dev)) {
6281                 has_ck505 = dev_priv->vbt.display_clock_mode;
6282                 can_ssc = has_ck505;
6283         } else {
6284                 has_ck505 = false;
6285                 can_ssc = true;
6286         }
6287
6288         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6289                       has_panel, has_lvds, has_ck505);
6290
6291         /* Ironlake: try to setup display ref clock before DPLL
6292          * enabling. This is only under driver's control after
6293          * PCH B stepping, previous chipset stepping should be
6294          * ignoring this setting.
6295          */
6296         val = I915_READ(PCH_DREF_CONTROL);
6297
6298         /* As we must carefully and slowly disable/enable each source in turn,
6299          * compute the final state we want first and check if we need to
6300          * make any changes at all.
6301          */
6302         final = val;
6303         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6304         if (has_ck505)
6305                 final |= DREF_NONSPREAD_CK505_ENABLE;
6306         else
6307                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6308
6309         final &= ~DREF_SSC_SOURCE_MASK;
6310         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6311         final &= ~DREF_SSC1_ENABLE;
6312
6313         if (has_panel) {
6314                 final |= DREF_SSC_SOURCE_ENABLE;
6315
6316                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6317                         final |= DREF_SSC1_ENABLE;
6318
6319                 if (has_cpu_edp) {
6320                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6321                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6322                         else
6323                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6324                 } else
6325                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6326         } else {
6327                 final |= DREF_SSC_SOURCE_DISABLE;
6328                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6329         }
6330
6331         if (final == val)
6332                 return;
6333
6334         /* Always enable nonspread source */
6335         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6336
6337         if (has_ck505)
6338                 val |= DREF_NONSPREAD_CK505_ENABLE;
6339         else
6340                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6341
6342         if (has_panel) {
6343                 val &= ~DREF_SSC_SOURCE_MASK;
6344                 val |= DREF_SSC_SOURCE_ENABLE;
6345
6346                 /* SSC must be turned on before enabling the CPU output  */
6347                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6348                         DRM_DEBUG_KMS("Using SSC on panel\n");
6349                         val |= DREF_SSC1_ENABLE;
6350                 } else
6351                         val &= ~DREF_SSC1_ENABLE;
6352
6353                 /* Get SSC going before enabling the outputs */
6354                 I915_WRITE(PCH_DREF_CONTROL, val);
6355                 POSTING_READ(PCH_DREF_CONTROL);
6356                 udelay(200);
6357
6358                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6359
6360                 /* Enable CPU source on CPU attached eDP */
6361                 if (has_cpu_edp) {
6362                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6363                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6364                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6365                         } else
6366                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6367                 } else
6368                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6369
6370                 I915_WRITE(PCH_DREF_CONTROL, val);
6371                 POSTING_READ(PCH_DREF_CONTROL);
6372                 udelay(200);
6373         } else {
6374                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6375
6376                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6377
6378                 /* Turn off CPU output */
6379                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6380
6381                 I915_WRITE(PCH_DREF_CONTROL, val);
6382                 POSTING_READ(PCH_DREF_CONTROL);
6383                 udelay(200);
6384
6385                 /* Turn off the SSC source */
6386                 val &= ~DREF_SSC_SOURCE_MASK;
6387                 val |= DREF_SSC_SOURCE_DISABLE;
6388
6389                 /* Turn off SSC1 */
6390                 val &= ~DREF_SSC1_ENABLE;
6391
6392                 I915_WRITE(PCH_DREF_CONTROL, val);
6393                 POSTING_READ(PCH_DREF_CONTROL);
6394                 udelay(200);
6395         }
6396
6397         BUG_ON(val != final);
6398 }
6399
6400 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6401 {
6402         uint32_t tmp;
6403
6404         tmp = I915_READ(SOUTH_CHICKEN2);
6405         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6406         I915_WRITE(SOUTH_CHICKEN2, tmp);
6407
6408         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6409                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6410                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6411
6412         tmp = I915_READ(SOUTH_CHICKEN2);
6413         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6414         I915_WRITE(SOUTH_CHICKEN2, tmp);
6415
6416         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6417                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6418                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6419 }
6420
6421 /* WaMPhyProgramming:hsw */
6422 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6423 {
6424         uint32_t tmp;
6425
6426         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6427         tmp &= ~(0xFF << 24);
6428         tmp |= (0x12 << 24);
6429         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6430
6431         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6432         tmp |= (1 << 11);
6433         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6434
6435         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6436         tmp |= (1 << 11);
6437         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6438
6439         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6440         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6441         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6442
6443         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6444         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6445         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6446
6447         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6448         tmp &= ~(7 << 13);
6449         tmp |= (5 << 13);
6450         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6451
6452         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6453         tmp &= ~(7 << 13);
6454         tmp |= (5 << 13);
6455         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6456
6457         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6458         tmp &= ~0xFF;
6459         tmp |= 0x1C;
6460         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6461
6462         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6463         tmp &= ~0xFF;
6464         tmp |= 0x1C;
6465         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6466
6467         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6468         tmp &= ~(0xFF << 16);
6469         tmp |= (0x1C << 16);
6470         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6471
6472         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6473         tmp &= ~(0xFF << 16);
6474         tmp |= (0x1C << 16);
6475         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6476
6477         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6478         tmp |= (1 << 27);
6479         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6480
6481         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6482         tmp |= (1 << 27);
6483         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6484
6485         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6486         tmp &= ~(0xF << 28);
6487         tmp |= (4 << 28);
6488         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6489
6490         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6491         tmp &= ~(0xF << 28);
6492         tmp |= (4 << 28);
6493         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6494 }
6495
6496 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6497  * Programming" based on the parameters passed:
6498  * - Sequence to enable CLKOUT_DP
6499  * - Sequence to enable CLKOUT_DP without spread
6500  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6501  */
6502 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6503                                  bool with_fdi)
6504 {
6505         struct drm_i915_private *dev_priv = dev->dev_private;
6506         uint32_t reg, tmp;
6507
6508         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6509                 with_spread = true;
6510         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6511                  with_fdi, "LP PCH doesn't have FDI\n"))
6512                 with_fdi = false;
6513
6514         mutex_lock(&dev_priv->dpio_lock);
6515
6516         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6517         tmp &= ~SBI_SSCCTL_DISABLE;
6518         tmp |= SBI_SSCCTL_PATHALT;
6519         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6520
6521         udelay(24);
6522
6523         if (with_spread) {
6524                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6525                 tmp &= ~SBI_SSCCTL_PATHALT;
6526                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6527
6528                 if (with_fdi) {
6529                         lpt_reset_fdi_mphy(dev_priv);
6530                         lpt_program_fdi_mphy(dev_priv);
6531                 }
6532         }
6533
6534         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6535                SBI_GEN0 : SBI_DBUFF0;
6536         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6537         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6538         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6539
6540         mutex_unlock(&dev_priv->dpio_lock);
6541 }
6542
6543 /* Sequence to disable CLKOUT_DP */
6544 static void lpt_disable_clkout_dp(struct drm_device *dev)
6545 {
6546         struct drm_i915_private *dev_priv = dev->dev_private;
6547         uint32_t reg, tmp;
6548
6549         mutex_lock(&dev_priv->dpio_lock);
6550
6551         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6552                SBI_GEN0 : SBI_DBUFF0;
6553         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6554         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6555         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6556
6557         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6558         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6559                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6560                         tmp |= SBI_SSCCTL_PATHALT;
6561                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6562                         udelay(32);
6563                 }
6564                 tmp |= SBI_SSCCTL_DISABLE;
6565                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6566         }
6567
6568         mutex_unlock(&dev_priv->dpio_lock);
6569 }
6570
6571 static void lpt_init_pch_refclk(struct drm_device *dev)
6572 {
6573         struct drm_mode_config *mode_config = &dev->mode_config;
6574         struct intel_encoder *encoder;
6575         bool has_vga = false;
6576
6577         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6578                 switch (encoder->type) {
6579                 case INTEL_OUTPUT_ANALOG:
6580                         has_vga = true;
6581                         break;
6582                 }
6583         }
6584
6585         if (has_vga)
6586                 lpt_enable_clkout_dp(dev, true, true);
6587         else
6588                 lpt_disable_clkout_dp(dev);
6589 }
6590
6591 /*
6592  * Initialize reference clocks when the driver loads
6593  */
6594 void intel_init_pch_refclk(struct drm_device *dev)
6595 {
6596         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6597                 ironlake_init_pch_refclk(dev);
6598         else if (HAS_PCH_LPT(dev))
6599                 lpt_init_pch_refclk(dev);
6600 }
6601
6602 static int ironlake_get_refclk(struct drm_crtc *crtc)
6603 {
6604         struct drm_device *dev = crtc->dev;
6605         struct drm_i915_private *dev_priv = dev->dev_private;
6606         struct intel_encoder *encoder;
6607         int num_connectors = 0;
6608         bool is_lvds = false;
6609
6610         for_each_encoder_on_crtc(dev, crtc, encoder) {
6611                 switch (encoder->type) {
6612                 case INTEL_OUTPUT_LVDS:
6613                         is_lvds = true;
6614                         break;
6615                 }
6616                 num_connectors++;
6617         }
6618
6619         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6620                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6621                               dev_priv->vbt.lvds_ssc_freq);
6622                 return dev_priv->vbt.lvds_ssc_freq;
6623         }
6624
6625         return 120000;
6626 }
6627
6628 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6629 {
6630         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6632         int pipe = intel_crtc->pipe;
6633         uint32_t val;
6634
6635         val = 0;
6636
6637         switch (intel_crtc->config.pipe_bpp) {
6638         case 18:
6639                 val |= PIPECONF_6BPC;
6640                 break;
6641         case 24:
6642                 val |= PIPECONF_8BPC;
6643                 break;
6644         case 30:
6645                 val |= PIPECONF_10BPC;
6646                 break;
6647         case 36:
6648                 val |= PIPECONF_12BPC;
6649                 break;
6650         default:
6651                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6652                 BUG();
6653         }
6654
6655         if (intel_crtc->config.dither)
6656                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6657
6658         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6659                 val |= PIPECONF_INTERLACED_ILK;
6660         else
6661                 val |= PIPECONF_PROGRESSIVE;
6662
6663         if (intel_crtc->config.limited_color_range)
6664                 val |= PIPECONF_COLOR_RANGE_SELECT;
6665
6666         I915_WRITE(PIPECONF(pipe), val);
6667         POSTING_READ(PIPECONF(pipe));
6668 }
6669
6670 /*
6671  * Set up the pipe CSC unit.
6672  *
6673  * Currently only full range RGB to limited range RGB conversion
6674  * is supported, but eventually this should handle various
6675  * RGB<->YCbCr scenarios as well.
6676  */
6677 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6678 {
6679         struct drm_device *dev = crtc->dev;
6680         struct drm_i915_private *dev_priv = dev->dev_private;
6681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6682         int pipe = intel_crtc->pipe;
6683         uint16_t coeff = 0x7800; /* 1.0 */
6684
6685         /*
6686          * TODO: Check what kind of values actually come out of the pipe
6687          * with these coeff/postoff values and adjust to get the best
6688          * accuracy. Perhaps we even need to take the bpc value into
6689          * consideration.
6690          */
6691
6692         if (intel_crtc->config.limited_color_range)
6693                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6694
6695         /*
6696          * GY/GU and RY/RU should be the other way around according
6697          * to BSpec, but reality doesn't agree. Just set them up in
6698          * a way that results in the correct picture.
6699          */
6700         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6701         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6702
6703         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6704         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6705
6706         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6707         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6708
6709         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6710         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6711         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6712
6713         if (INTEL_INFO(dev)->gen > 6) {
6714                 uint16_t postoff = 0;
6715
6716                 if (intel_crtc->config.limited_color_range)
6717                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6718
6719                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6720                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6721                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6722
6723                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6724         } else {
6725                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6726
6727                 if (intel_crtc->config.limited_color_range)
6728                         mode |= CSC_BLACK_SCREEN_OFFSET;
6729
6730                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6731         }
6732 }
6733
6734 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6735 {
6736         struct drm_device *dev = crtc->dev;
6737         struct drm_i915_private *dev_priv = dev->dev_private;
6738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6739         enum pipe pipe = intel_crtc->pipe;
6740         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6741         uint32_t val;
6742
6743         val = 0;
6744
6745         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6746                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6747
6748         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6749                 val |= PIPECONF_INTERLACED_ILK;
6750         else
6751                 val |= PIPECONF_PROGRESSIVE;
6752
6753         I915_WRITE(PIPECONF(cpu_transcoder), val);
6754         POSTING_READ(PIPECONF(cpu_transcoder));
6755
6756         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6757         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6758
6759         if (IS_BROADWELL(dev)) {
6760                 val = 0;
6761
6762                 switch (intel_crtc->config.pipe_bpp) {
6763                 case 18:
6764                         val |= PIPEMISC_DITHER_6_BPC;
6765                         break;
6766                 case 24:
6767                         val |= PIPEMISC_DITHER_8_BPC;
6768                         break;
6769                 case 30:
6770                         val |= PIPEMISC_DITHER_10_BPC;
6771                         break;
6772                 case 36:
6773                         val |= PIPEMISC_DITHER_12_BPC;
6774                         break;
6775                 default:
6776                         /* Case prevented by pipe_config_set_bpp. */
6777                         BUG();
6778                 }
6779
6780                 if (intel_crtc->config.dither)
6781                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6782
6783                 I915_WRITE(PIPEMISC(pipe), val);
6784         }
6785 }
6786
6787 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6788                                     intel_clock_t *clock,
6789                                     bool *has_reduced_clock,
6790                                     intel_clock_t *reduced_clock)
6791 {
6792         struct drm_device *dev = crtc->dev;
6793         struct drm_i915_private *dev_priv = dev->dev_private;
6794         struct intel_encoder *intel_encoder;
6795         int refclk;
6796         const intel_limit_t *limit;
6797         bool ret, is_lvds = false;
6798
6799         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6800                 switch (intel_encoder->type) {
6801                 case INTEL_OUTPUT_LVDS:
6802                         is_lvds = true;
6803                         break;
6804                 }
6805         }
6806
6807         refclk = ironlake_get_refclk(crtc);
6808
6809         /*
6810          * Returns a set of divisors for the desired target clock with the given
6811          * refclk, or FALSE.  The returned values represent the clock equation:
6812          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6813          */
6814         limit = intel_limit(crtc, refclk);
6815         ret = dev_priv->display.find_dpll(limit, crtc,
6816                                           to_intel_crtc(crtc)->config.port_clock,
6817                                           refclk, NULL, clock);
6818         if (!ret)
6819                 return false;
6820
6821         if (is_lvds && dev_priv->lvds_downclock_avail) {
6822                 /*
6823                  * Ensure we match the reduced clock's P to the target clock.
6824                  * If the clocks don't match, we can't switch the display clock
6825                  * by using the FP0/FP1. In such case we will disable the LVDS
6826                  * downclock feature.
6827                 */
6828                 *has_reduced_clock =
6829                         dev_priv->display.find_dpll(limit, crtc,
6830                                                     dev_priv->lvds_downclock,
6831                                                     refclk, clock,
6832                                                     reduced_clock);
6833         }
6834
6835         return true;
6836 }
6837
6838 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6839 {
6840         /*
6841          * Account for spread spectrum to avoid
6842          * oversubscribing the link. Max center spread
6843          * is 2.5%; use 5% for safety's sake.
6844          */
6845         u32 bps = target_clock * bpp * 21 / 20;
6846         return DIV_ROUND_UP(bps, link_bw * 8);
6847 }
6848
6849 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6850 {
6851         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6852 }
6853
6854 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6855                                       u32 *fp,
6856                                       intel_clock_t *reduced_clock, u32 *fp2)
6857 {
6858         struct drm_crtc *crtc = &intel_crtc->base;
6859         struct drm_device *dev = crtc->dev;
6860         struct drm_i915_private *dev_priv = dev->dev_private;
6861         struct intel_encoder *intel_encoder;
6862         uint32_t dpll;
6863         int factor, num_connectors = 0;
6864         bool is_lvds = false, is_sdvo = false;
6865
6866         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6867                 switch (intel_encoder->type) {
6868                 case INTEL_OUTPUT_LVDS:
6869                         is_lvds = true;
6870                         break;
6871                 case INTEL_OUTPUT_SDVO:
6872                 case INTEL_OUTPUT_HDMI:
6873                         is_sdvo = true;
6874                         break;
6875                 }
6876
6877                 num_connectors++;
6878         }
6879
6880         /* Enable autotuning of the PLL clock (if permissible) */
6881         factor = 21;
6882         if (is_lvds) {
6883                 if ((intel_panel_use_ssc(dev_priv) &&
6884                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6885                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6886                         factor = 25;
6887         } else if (intel_crtc->config.sdvo_tv_clock)
6888                 factor = 20;
6889
6890         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6891                 *fp |= FP_CB_TUNE;
6892
6893         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6894                 *fp2 |= FP_CB_TUNE;
6895
6896         dpll = 0;
6897
6898         if (is_lvds)
6899                 dpll |= DPLLB_MODE_LVDS;
6900         else
6901                 dpll |= DPLLB_MODE_DAC_SERIAL;
6902
6903         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6904                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6905
6906         if (is_sdvo)
6907                 dpll |= DPLL_SDVO_HIGH_SPEED;
6908         if (intel_crtc->config.has_dp_encoder)
6909                 dpll |= DPLL_SDVO_HIGH_SPEED;
6910
6911         /* compute bitmask from p1 value */
6912         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6913         /* also FPA1 */
6914         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6915
6916         switch (intel_crtc->config.dpll.p2) {
6917         case 5:
6918                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6919                 break;
6920         case 7:
6921                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6922                 break;
6923         case 10:
6924                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6925                 break;
6926         case 14:
6927                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6928                 break;
6929         }
6930
6931         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6932                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6933         else
6934                 dpll |= PLL_REF_INPUT_DREFCLK;
6935
6936         return dpll | DPLL_VCO_ENABLE;
6937 }
6938
6939 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6940                                   int x, int y,
6941                                   struct drm_framebuffer *fb)
6942 {
6943         struct drm_device *dev = crtc->dev;
6944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6945         int num_connectors = 0;
6946         intel_clock_t clock, reduced_clock;
6947         u32 dpll = 0, fp = 0, fp2 = 0;
6948         bool ok, has_reduced_clock = false;
6949         bool is_lvds = false;
6950         struct intel_encoder *encoder;
6951         struct intel_shared_dpll *pll;
6952
6953         for_each_encoder_on_crtc(dev, crtc, encoder) {
6954                 switch (encoder->type) {
6955                 case INTEL_OUTPUT_LVDS:
6956                         is_lvds = true;
6957                         break;
6958                 }
6959
6960                 num_connectors++;
6961         }
6962
6963         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6964              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6965
6966         ok = ironlake_compute_clocks(crtc, &clock,
6967                                      &has_reduced_clock, &reduced_clock);
6968         if (!ok && !intel_crtc->config.clock_set) {
6969                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6970                 return -EINVAL;
6971         }
6972         /* Compat-code for transition, will disappear. */
6973         if (!intel_crtc->config.clock_set) {
6974                 intel_crtc->config.dpll.n = clock.n;
6975                 intel_crtc->config.dpll.m1 = clock.m1;
6976                 intel_crtc->config.dpll.m2 = clock.m2;
6977                 intel_crtc->config.dpll.p1 = clock.p1;
6978                 intel_crtc->config.dpll.p2 = clock.p2;
6979         }
6980
6981         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6982         if (intel_crtc->config.has_pch_encoder) {
6983                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6984                 if (has_reduced_clock)
6985                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6986
6987                 dpll = ironlake_compute_dpll(intel_crtc,
6988                                              &fp, &reduced_clock,
6989                                              has_reduced_clock ? &fp2 : NULL);
6990
6991                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6992                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6993                 if (has_reduced_clock)
6994                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6995                 else
6996                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6997
6998                 pll = intel_get_shared_dpll(intel_crtc);
6999                 if (pll == NULL) {
7000                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7001                                          pipe_name(intel_crtc->pipe));
7002                         return -EINVAL;
7003                 }
7004         } else
7005                 intel_put_shared_dpll(intel_crtc);
7006
7007         if (is_lvds && has_reduced_clock && i915.powersave)
7008                 intel_crtc->lowfreq_avail = true;
7009         else
7010                 intel_crtc->lowfreq_avail = false;
7011
7012         return 0;
7013 }
7014
7015 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7016                                          struct intel_link_m_n *m_n)
7017 {
7018         struct drm_device *dev = crtc->base.dev;
7019         struct drm_i915_private *dev_priv = dev->dev_private;
7020         enum pipe pipe = crtc->pipe;
7021
7022         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7023         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7024         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7025                 & ~TU_SIZE_MASK;
7026         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7027         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7028                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7029 }
7030
7031 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7032                                          enum transcoder transcoder,
7033                                          struct intel_link_m_n *m_n)
7034 {
7035         struct drm_device *dev = crtc->base.dev;
7036         struct drm_i915_private *dev_priv = dev->dev_private;
7037         enum pipe pipe = crtc->pipe;
7038
7039         if (INTEL_INFO(dev)->gen >= 5) {
7040                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7041                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7042                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7043                         & ~TU_SIZE_MASK;
7044                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7045                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7046                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7047         } else {
7048                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7049                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7050                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7051                         & ~TU_SIZE_MASK;
7052                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7053                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7054                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7055         }
7056 }
7057
7058 void intel_dp_get_m_n(struct intel_crtc *crtc,
7059                       struct intel_crtc_config *pipe_config)
7060 {
7061         if (crtc->config.has_pch_encoder)
7062                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7063         else
7064                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7065                                              &pipe_config->dp_m_n);
7066 }
7067
7068 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7069                                         struct intel_crtc_config *pipe_config)
7070 {
7071         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7072                                      &pipe_config->fdi_m_n);
7073 }
7074
7075 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7076                                      struct intel_crtc_config *pipe_config)
7077 {
7078         struct drm_device *dev = crtc->base.dev;
7079         struct drm_i915_private *dev_priv = dev->dev_private;
7080         uint32_t tmp;
7081
7082         tmp = I915_READ(PF_CTL(crtc->pipe));
7083
7084         if (tmp & PF_ENABLE) {
7085                 pipe_config->pch_pfit.enabled = true;
7086                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7087                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7088
7089                 /* We currently do not free assignements of panel fitters on
7090                  * ivb/hsw (since we don't use the higher upscaling modes which
7091                  * differentiates them) so just WARN about this case for now. */
7092                 if (IS_GEN7(dev)) {
7093                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7094                                 PF_PIPE_SEL_IVB(crtc->pipe));
7095                 }
7096         }
7097 }
7098
7099 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7100                                       struct intel_plane_config *plane_config)
7101 {
7102         struct drm_device *dev = crtc->base.dev;
7103         struct drm_i915_private *dev_priv = dev->dev_private;
7104         u32 val, base, offset;
7105         int pipe = crtc->pipe, plane = crtc->plane;
7106         int fourcc, pixel_format;
7107         int aligned_height;
7108
7109         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7110         if (!crtc->base.primary->fb) {
7111                 DRM_DEBUG_KMS("failed to alloc fb\n");
7112                 return;
7113         }
7114
7115         val = I915_READ(DSPCNTR(plane));
7116
7117         if (INTEL_INFO(dev)->gen >= 4)
7118                 if (val & DISPPLANE_TILED)
7119                         plane_config->tiled = true;
7120
7121         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7122         fourcc = intel_format_to_fourcc(pixel_format);
7123         crtc->base.primary->fb->pixel_format = fourcc;
7124         crtc->base.primary->fb->bits_per_pixel =
7125                 drm_format_plane_cpp(fourcc, 0) * 8;
7126
7127         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7128         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7129                 offset = I915_READ(DSPOFFSET(plane));
7130         } else {
7131                 if (plane_config->tiled)
7132                         offset = I915_READ(DSPTILEOFF(plane));
7133                 else
7134                         offset = I915_READ(DSPLINOFF(plane));
7135         }
7136         plane_config->base = base;
7137
7138         val = I915_READ(PIPESRC(pipe));
7139         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7140         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7141
7142         val = I915_READ(DSPSTRIDE(pipe));
7143         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7144
7145         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7146                                             plane_config->tiled);
7147
7148         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7149                                    aligned_height, PAGE_SIZE);
7150
7151         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7152                       pipe, plane, crtc->base.primary->fb->width,
7153                       crtc->base.primary->fb->height,
7154                       crtc->base.primary->fb->bits_per_pixel, base,
7155                       crtc->base.primary->fb->pitches[0],
7156                       plane_config->size);
7157 }
7158
7159 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7160                                      struct intel_crtc_config *pipe_config)
7161 {
7162         struct drm_device *dev = crtc->base.dev;
7163         struct drm_i915_private *dev_priv = dev->dev_private;
7164         uint32_t tmp;
7165
7166         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7167         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7168
7169         tmp = I915_READ(PIPECONF(crtc->pipe));
7170         if (!(tmp & PIPECONF_ENABLE))
7171                 return false;
7172
7173         switch (tmp & PIPECONF_BPC_MASK) {
7174         case PIPECONF_6BPC:
7175                 pipe_config->pipe_bpp = 18;
7176                 break;
7177         case PIPECONF_8BPC:
7178                 pipe_config->pipe_bpp = 24;
7179                 break;
7180         case PIPECONF_10BPC:
7181                 pipe_config->pipe_bpp = 30;
7182                 break;
7183         case PIPECONF_12BPC:
7184                 pipe_config->pipe_bpp = 36;
7185                 break;
7186         default:
7187                 break;
7188         }
7189
7190         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7191                 pipe_config->limited_color_range = true;
7192
7193         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7194                 struct intel_shared_dpll *pll;
7195
7196                 pipe_config->has_pch_encoder = true;
7197
7198                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7199                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7200                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7201
7202                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7203
7204                 if (HAS_PCH_IBX(dev_priv->dev)) {
7205                         pipe_config->shared_dpll =
7206                                 (enum intel_dpll_id) crtc->pipe;
7207                 } else {
7208                         tmp = I915_READ(PCH_DPLL_SEL);
7209                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7210                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7211                         else
7212                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7213                 }
7214
7215                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7216
7217                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7218                                            &pipe_config->dpll_hw_state));
7219
7220                 tmp = pipe_config->dpll_hw_state.dpll;
7221                 pipe_config->pixel_multiplier =
7222                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7223                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7224
7225                 ironlake_pch_clock_get(crtc, pipe_config);
7226         } else {
7227                 pipe_config->pixel_multiplier = 1;
7228         }
7229
7230         intel_get_pipe_timings(crtc, pipe_config);
7231
7232         ironlake_get_pfit_config(crtc, pipe_config);
7233
7234         return true;
7235 }
7236
7237 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7238 {
7239         struct drm_device *dev = dev_priv->dev;
7240         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7241         struct intel_crtc *crtc;
7242
7243         for_each_intel_crtc(dev, crtc)
7244                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7245                      pipe_name(crtc->pipe));
7246
7247         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7248         WARN(plls->spll_refcount, "SPLL enabled\n");
7249         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7250         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7251         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7252         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7253              "CPU PWM1 enabled\n");
7254         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7255              "CPU PWM2 enabled\n");
7256         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7257              "PCH PWM1 enabled\n");
7258         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7259              "Utility pin enabled\n");
7260         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7261
7262         /*
7263          * In theory we can still leave IRQs enabled, as long as only the HPD
7264          * interrupts remain enabled. We used to check for that, but since it's
7265          * gen-specific and since we only disable LCPLL after we fully disable
7266          * the interrupts, the check below should be enough.
7267          */
7268         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7269 }
7270
7271 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7272 {
7273         struct drm_device *dev = dev_priv->dev;
7274
7275         if (IS_HASWELL(dev)) {
7276                 mutex_lock(&dev_priv->rps.hw_lock);
7277                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7278                                             val))
7279                         DRM_ERROR("Failed to disable D_COMP\n");
7280                 mutex_unlock(&dev_priv->rps.hw_lock);
7281         } else {
7282                 I915_WRITE(D_COMP, val);
7283         }
7284         POSTING_READ(D_COMP);
7285 }
7286
7287 /*
7288  * This function implements pieces of two sequences from BSpec:
7289  * - Sequence for display software to disable LCPLL
7290  * - Sequence for display software to allow package C8+
7291  * The steps implemented here are just the steps that actually touch the LCPLL
7292  * register. Callers should take care of disabling all the display engine
7293  * functions, doing the mode unset, fixing interrupts, etc.
7294  */
7295 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7296                               bool switch_to_fclk, bool allow_power_down)
7297 {
7298         uint32_t val;
7299
7300         assert_can_disable_lcpll(dev_priv);
7301
7302         val = I915_READ(LCPLL_CTL);
7303
7304         if (switch_to_fclk) {
7305                 val |= LCPLL_CD_SOURCE_FCLK;
7306                 I915_WRITE(LCPLL_CTL, val);
7307
7308                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7309                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7310                         DRM_ERROR("Switching to FCLK failed\n");
7311
7312                 val = I915_READ(LCPLL_CTL);
7313         }
7314
7315         val |= LCPLL_PLL_DISABLE;
7316         I915_WRITE(LCPLL_CTL, val);
7317         POSTING_READ(LCPLL_CTL);
7318
7319         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7320                 DRM_ERROR("LCPLL still locked\n");
7321
7322         val = I915_READ(D_COMP);
7323         val |= D_COMP_COMP_DISABLE;
7324         hsw_write_dcomp(dev_priv, val);
7325         ndelay(100);
7326
7327         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7328                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7329
7330         if (allow_power_down) {
7331                 val = I915_READ(LCPLL_CTL);
7332                 val |= LCPLL_POWER_DOWN_ALLOW;
7333                 I915_WRITE(LCPLL_CTL, val);
7334                 POSTING_READ(LCPLL_CTL);
7335         }
7336 }
7337
7338 /*
7339  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7340  * source.
7341  */
7342 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7343 {
7344         uint32_t val;
7345         unsigned long irqflags;
7346
7347         val = I915_READ(LCPLL_CTL);
7348
7349         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7350                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7351                 return;
7352
7353         /*
7354          * Make sure we're not on PC8 state before disabling PC8, otherwise
7355          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7356          *
7357          * The other problem is that hsw_restore_lcpll() is called as part of
7358          * the runtime PM resume sequence, so we can't just call
7359          * gen6_gt_force_wake_get() because that function calls
7360          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7361          * while we are on the resume sequence. So to solve this problem we have
7362          * to call special forcewake code that doesn't touch runtime PM and
7363          * doesn't enable the forcewake delayed work.
7364          */
7365         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7366         if (dev_priv->uncore.forcewake_count++ == 0)
7367                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7368         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7369
7370         if (val & LCPLL_POWER_DOWN_ALLOW) {
7371                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7372                 I915_WRITE(LCPLL_CTL, val);
7373                 POSTING_READ(LCPLL_CTL);
7374         }
7375
7376         val = I915_READ(D_COMP);
7377         val |= D_COMP_COMP_FORCE;
7378         val &= ~D_COMP_COMP_DISABLE;
7379         hsw_write_dcomp(dev_priv, val);
7380
7381         val = I915_READ(LCPLL_CTL);
7382         val &= ~LCPLL_PLL_DISABLE;
7383         I915_WRITE(LCPLL_CTL, val);
7384
7385         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7386                 DRM_ERROR("LCPLL not locked yet\n");
7387
7388         if (val & LCPLL_CD_SOURCE_FCLK) {
7389                 val = I915_READ(LCPLL_CTL);
7390                 val &= ~LCPLL_CD_SOURCE_FCLK;
7391                 I915_WRITE(LCPLL_CTL, val);
7392
7393                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7394                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7395                         DRM_ERROR("Switching back to LCPLL failed\n");
7396         }
7397
7398         /* See the big comment above. */
7399         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7400         if (--dev_priv->uncore.forcewake_count == 0)
7401                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7402         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7403 }
7404
7405 /*
7406  * Package states C8 and deeper are really deep PC states that can only be
7407  * reached when all the devices on the system allow it, so even if the graphics
7408  * device allows PC8+, it doesn't mean the system will actually get to these
7409  * states. Our driver only allows PC8+ when going into runtime PM.
7410  *
7411  * The requirements for PC8+ are that all the outputs are disabled, the power
7412  * well is disabled and most interrupts are disabled, and these are also
7413  * requirements for runtime PM. When these conditions are met, we manually do
7414  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7415  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7416  * hang the machine.
7417  *
7418  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7419  * the state of some registers, so when we come back from PC8+ we need to
7420  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7421  * need to take care of the registers kept by RC6. Notice that this happens even
7422  * if we don't put the device in PCI D3 state (which is what currently happens
7423  * because of the runtime PM support).
7424  *
7425  * For more, read "Display Sequences for Package C8" on the hardware
7426  * documentation.
7427  */
7428 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7429 {
7430         struct drm_device *dev = dev_priv->dev;
7431         uint32_t val;
7432
7433         DRM_DEBUG_KMS("Enabling package C8+\n");
7434
7435         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7436                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7437                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7438                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7439         }
7440
7441         lpt_disable_clkout_dp(dev);
7442         hsw_disable_lcpll(dev_priv, true, true);
7443 }
7444
7445 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7446 {
7447         struct drm_device *dev = dev_priv->dev;
7448         uint32_t val;
7449
7450         DRM_DEBUG_KMS("Disabling package C8+\n");
7451
7452         hsw_restore_lcpll(dev_priv);
7453         lpt_init_pch_refclk(dev);
7454
7455         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7456                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7457                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7458                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7459         }
7460
7461         intel_prepare_ddi(dev);
7462 }
7463
7464 static void snb_modeset_global_resources(struct drm_device *dev)
7465 {
7466         modeset_update_crtc_power_domains(dev);
7467 }
7468
7469 static void haswell_modeset_global_resources(struct drm_device *dev)
7470 {
7471         modeset_update_crtc_power_domains(dev);
7472 }
7473
7474 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7475                                  int x, int y,
7476                                  struct drm_framebuffer *fb)
7477 {
7478         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7479
7480         if (!intel_ddi_pll_select(intel_crtc))
7481                 return -EINVAL;
7482         intel_ddi_pll_enable(intel_crtc);
7483
7484         intel_crtc->lowfreq_avail = false;
7485
7486         return 0;
7487 }
7488
7489 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7490                                     struct intel_crtc_config *pipe_config)
7491 {
7492         struct drm_device *dev = crtc->base.dev;
7493         struct drm_i915_private *dev_priv = dev->dev_private;
7494         enum intel_display_power_domain pfit_domain;
7495         uint32_t tmp;
7496
7497         if (!intel_display_power_enabled(dev_priv,
7498                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7499                 return false;
7500
7501         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7502         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7503
7504         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7505         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7506                 enum pipe trans_edp_pipe;
7507                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7508                 default:
7509                         WARN(1, "unknown pipe linked to edp transcoder\n");
7510                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7511                 case TRANS_DDI_EDP_INPUT_A_ON:
7512                         trans_edp_pipe = PIPE_A;
7513                         break;
7514                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7515                         trans_edp_pipe = PIPE_B;
7516                         break;
7517                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7518                         trans_edp_pipe = PIPE_C;
7519                         break;
7520                 }
7521
7522                 if (trans_edp_pipe == crtc->pipe)
7523                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7524         }
7525
7526         if (!intel_display_power_enabled(dev_priv,
7527                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7528                 return false;
7529
7530         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7531         if (!(tmp & PIPECONF_ENABLE))
7532                 return false;
7533
7534         /*
7535          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7536          * DDI E. So just check whether this pipe is wired to DDI E and whether
7537          * the PCH transcoder is on.
7538          */
7539         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7540         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7541             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7542                 pipe_config->has_pch_encoder = true;
7543
7544                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7545                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7546                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7547
7548                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7549         }
7550
7551         intel_get_pipe_timings(crtc, pipe_config);
7552
7553         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7554         if (intel_display_power_enabled(dev_priv, pfit_domain))
7555                 ironlake_get_pfit_config(crtc, pipe_config);
7556
7557         if (IS_HASWELL(dev))
7558                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7559                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7560
7561         pipe_config->pixel_multiplier = 1;
7562
7563         return true;
7564 }
7565
7566 static struct {
7567         int clock;
7568         u32 config;
7569 } hdmi_audio_clock[] = {
7570         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7571         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7572         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7573         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7574         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7575         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7576         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7577         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7578         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7579         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7580 };
7581
7582 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7583 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7584 {
7585         int i;
7586
7587         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7588                 if (mode->clock == hdmi_audio_clock[i].clock)
7589                         break;
7590         }
7591
7592         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7593                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7594                 i = 1;
7595         }
7596
7597         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7598                       hdmi_audio_clock[i].clock,
7599                       hdmi_audio_clock[i].config);
7600
7601         return hdmi_audio_clock[i].config;
7602 }
7603
7604 static bool intel_eld_uptodate(struct drm_connector *connector,
7605                                int reg_eldv, uint32_t bits_eldv,
7606                                int reg_elda, uint32_t bits_elda,
7607                                int reg_edid)
7608 {
7609         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7610         uint8_t *eld = connector->eld;
7611         uint32_t i;
7612
7613         i = I915_READ(reg_eldv);
7614         i &= bits_eldv;
7615
7616         if (!eld[0])
7617                 return !i;
7618
7619         if (!i)
7620                 return false;
7621
7622         i = I915_READ(reg_elda);
7623         i &= ~bits_elda;
7624         I915_WRITE(reg_elda, i);
7625
7626         for (i = 0; i < eld[2]; i++)
7627                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7628                         return false;
7629
7630         return true;
7631 }
7632
7633 static void g4x_write_eld(struct drm_connector *connector,
7634                           struct drm_crtc *crtc,
7635                           struct drm_display_mode *mode)
7636 {
7637         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7638         uint8_t *eld = connector->eld;
7639         uint32_t eldv;
7640         uint32_t len;
7641         uint32_t i;
7642
7643         i = I915_READ(G4X_AUD_VID_DID);
7644
7645         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7646                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7647         else
7648                 eldv = G4X_ELDV_DEVCTG;
7649
7650         if (intel_eld_uptodate(connector,
7651                                G4X_AUD_CNTL_ST, eldv,
7652                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7653                                G4X_HDMIW_HDMIEDID))
7654                 return;
7655
7656         i = I915_READ(G4X_AUD_CNTL_ST);
7657         i &= ~(eldv | G4X_ELD_ADDR);
7658         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7659         I915_WRITE(G4X_AUD_CNTL_ST, i);
7660
7661         if (!eld[0])
7662                 return;
7663
7664         len = min_t(uint8_t, eld[2], len);
7665         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7666         for (i = 0; i < len; i++)
7667                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7668
7669         i = I915_READ(G4X_AUD_CNTL_ST);
7670         i |= eldv;
7671         I915_WRITE(G4X_AUD_CNTL_ST, i);
7672 }
7673
7674 static void haswell_write_eld(struct drm_connector *connector,
7675                               struct drm_crtc *crtc,
7676                               struct drm_display_mode *mode)
7677 {
7678         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7679         uint8_t *eld = connector->eld;
7680         uint32_t eldv;
7681         uint32_t i;
7682         int len;
7683         int pipe = to_intel_crtc(crtc)->pipe;
7684         int tmp;
7685
7686         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7687         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7688         int aud_config = HSW_AUD_CFG(pipe);
7689         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7690
7691         /* Audio output enable */
7692         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7693         tmp = I915_READ(aud_cntrl_st2);
7694         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7695         I915_WRITE(aud_cntrl_st2, tmp);
7696         POSTING_READ(aud_cntrl_st2);
7697
7698         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7699
7700         /* Set ELD valid state */
7701         tmp = I915_READ(aud_cntrl_st2);
7702         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7703         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7704         I915_WRITE(aud_cntrl_st2, tmp);
7705         tmp = I915_READ(aud_cntrl_st2);
7706         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7707
7708         /* Enable HDMI mode */
7709         tmp = I915_READ(aud_config);
7710         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7711         /* clear N_programing_enable and N_value_index */
7712         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7713         I915_WRITE(aud_config, tmp);
7714
7715         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7716
7717         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7718
7719         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7720                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7721                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7722                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7723         } else {
7724                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7725         }
7726
7727         if (intel_eld_uptodate(connector,
7728                                aud_cntrl_st2, eldv,
7729                                aud_cntl_st, IBX_ELD_ADDRESS,
7730                                hdmiw_hdmiedid))
7731                 return;
7732
7733         i = I915_READ(aud_cntrl_st2);
7734         i &= ~eldv;
7735         I915_WRITE(aud_cntrl_st2, i);
7736
7737         if (!eld[0])
7738                 return;
7739
7740         i = I915_READ(aud_cntl_st);
7741         i &= ~IBX_ELD_ADDRESS;
7742         I915_WRITE(aud_cntl_st, i);
7743         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7744         DRM_DEBUG_DRIVER("port num:%d\n", i);
7745
7746         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7747         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7748         for (i = 0; i < len; i++)
7749                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7750
7751         i = I915_READ(aud_cntrl_st2);
7752         i |= eldv;
7753         I915_WRITE(aud_cntrl_st2, i);
7754
7755 }
7756
7757 static void ironlake_write_eld(struct drm_connector *connector,
7758                                struct drm_crtc *crtc,
7759                                struct drm_display_mode *mode)
7760 {
7761         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7762         uint8_t *eld = connector->eld;
7763         uint32_t eldv;
7764         uint32_t i;
7765         int len;
7766         int hdmiw_hdmiedid;
7767         int aud_config;
7768         int aud_cntl_st;
7769         int aud_cntrl_st2;
7770         int pipe = to_intel_crtc(crtc)->pipe;
7771
7772         if (HAS_PCH_IBX(connector->dev)) {
7773                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7774                 aud_config = IBX_AUD_CFG(pipe);
7775                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7776                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7777         } else if (IS_VALLEYVIEW(connector->dev)) {
7778                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7779                 aud_config = VLV_AUD_CFG(pipe);
7780                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7781                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7782         } else {
7783                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7784                 aud_config = CPT_AUD_CFG(pipe);
7785                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7786                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7787         }
7788
7789         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7790
7791         if (IS_VALLEYVIEW(connector->dev))  {
7792                 struct intel_encoder *intel_encoder;
7793                 struct intel_digital_port *intel_dig_port;
7794
7795                 intel_encoder = intel_attached_encoder(connector);
7796                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7797                 i = intel_dig_port->port;
7798         } else {
7799                 i = I915_READ(aud_cntl_st);
7800                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7801                 /* DIP_Port_Select, 0x1 = PortB */
7802         }
7803
7804         if (!i) {
7805                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7806                 /* operate blindly on all ports */
7807                 eldv = IBX_ELD_VALIDB;
7808                 eldv |= IBX_ELD_VALIDB << 4;
7809                 eldv |= IBX_ELD_VALIDB << 8;
7810         } else {
7811                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7812                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7813         }
7814
7815         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7816                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7817                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7818                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7819         } else {
7820                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7821         }
7822
7823         if (intel_eld_uptodate(connector,
7824                                aud_cntrl_st2, eldv,
7825                                aud_cntl_st, IBX_ELD_ADDRESS,
7826                                hdmiw_hdmiedid))
7827                 return;
7828
7829         i = I915_READ(aud_cntrl_st2);
7830         i &= ~eldv;
7831         I915_WRITE(aud_cntrl_st2, i);
7832
7833         if (!eld[0])
7834                 return;
7835
7836         i = I915_READ(aud_cntl_st);
7837         i &= ~IBX_ELD_ADDRESS;
7838         I915_WRITE(aud_cntl_st, i);
7839
7840         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7841         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7842         for (i = 0; i < len; i++)
7843                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7844
7845         i = I915_READ(aud_cntrl_st2);
7846         i |= eldv;
7847         I915_WRITE(aud_cntrl_st2, i);
7848 }
7849
7850 void intel_write_eld(struct drm_encoder *encoder,
7851                      struct drm_display_mode *mode)
7852 {
7853         struct drm_crtc *crtc = encoder->crtc;
7854         struct drm_connector *connector;
7855         struct drm_device *dev = encoder->dev;
7856         struct drm_i915_private *dev_priv = dev->dev_private;
7857
7858         connector = drm_select_eld(encoder, mode);
7859         if (!connector)
7860                 return;
7861
7862         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7863                          connector->base.id,
7864                          connector->name,
7865                          connector->encoder->base.id,
7866                          connector->encoder->name);
7867
7868         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7869
7870         if (dev_priv->display.write_eld)
7871                 dev_priv->display.write_eld(connector, crtc, mode);
7872 }
7873
7874 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7875 {
7876         struct drm_device *dev = crtc->dev;
7877         struct drm_i915_private *dev_priv = dev->dev_private;
7878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7879         uint32_t cntl;
7880
7881         if (base != intel_crtc->cursor_base) {
7882                 /* On these chipsets we can only modify the base whilst
7883                  * the cursor is disabled.
7884                  */
7885                 if (intel_crtc->cursor_cntl) {
7886                         I915_WRITE(_CURACNTR, 0);
7887                         POSTING_READ(_CURACNTR);
7888                         intel_crtc->cursor_cntl = 0;
7889                 }
7890
7891                 I915_WRITE(_CURABASE, base);
7892                 POSTING_READ(_CURABASE);
7893         }
7894
7895         /* XXX width must be 64, stride 256 => 0x00 << 28 */
7896         cntl = 0;
7897         if (base)
7898                 cntl = (CURSOR_ENABLE |
7899                         CURSOR_GAMMA_ENABLE |
7900                         CURSOR_FORMAT_ARGB);
7901         if (intel_crtc->cursor_cntl != cntl) {
7902                 I915_WRITE(_CURACNTR, cntl);
7903                 POSTING_READ(_CURACNTR);
7904                 intel_crtc->cursor_cntl = cntl;
7905         }
7906 }
7907
7908 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7909 {
7910         struct drm_device *dev = crtc->dev;
7911         struct drm_i915_private *dev_priv = dev->dev_private;
7912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7913         int pipe = intel_crtc->pipe;
7914         uint32_t cntl;
7915
7916         cntl = 0;
7917         if (base) {
7918                 cntl = MCURSOR_GAMMA_ENABLE;
7919                 switch (intel_crtc->cursor_width) {
7920                         case 64:
7921                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7922                                 break;
7923                         case 128:
7924                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7925                                 break;
7926                         case 256:
7927                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7928                                 break;
7929                         default:
7930                                 WARN_ON(1);
7931                                 return;
7932                 }
7933                 cntl |= pipe << 28; /* Connect to correct pipe */
7934         }
7935         if (intel_crtc->cursor_cntl != cntl) {
7936                 I915_WRITE(CURCNTR(pipe), cntl);
7937                 POSTING_READ(CURCNTR(pipe));
7938                 intel_crtc->cursor_cntl = cntl;
7939         }
7940
7941         /* and commit changes on next vblank */
7942         I915_WRITE(CURBASE(pipe), base);
7943         POSTING_READ(CURBASE(pipe));
7944 }
7945
7946 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7947 {
7948         struct drm_device *dev = crtc->dev;
7949         struct drm_i915_private *dev_priv = dev->dev_private;
7950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7951         int pipe = intel_crtc->pipe;
7952         uint32_t cntl;
7953
7954         cntl = 0;
7955         if (base) {
7956                 cntl = MCURSOR_GAMMA_ENABLE;
7957                 switch (intel_crtc->cursor_width) {
7958                         case 64:
7959                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7960                                 break;
7961                         case 128:
7962                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7963                                 break;
7964                         case 256:
7965                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7966                                 break;
7967                         default:
7968                                 WARN_ON(1);
7969                                 return;
7970                 }
7971         }
7972         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
7973                 cntl |= CURSOR_PIPE_CSC_ENABLE;
7974
7975         if (intel_crtc->cursor_cntl != cntl) {
7976                 I915_WRITE(CURCNTR(pipe), cntl);
7977                 POSTING_READ(CURCNTR(pipe));
7978                 intel_crtc->cursor_cntl = cntl;
7979         }
7980
7981         /* and commit changes on next vblank */
7982         I915_WRITE(CURBASE(pipe), base);
7983         POSTING_READ(CURBASE(pipe));
7984 }
7985
7986 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7987 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7988                                      bool on)
7989 {
7990         struct drm_device *dev = crtc->dev;
7991         struct drm_i915_private *dev_priv = dev->dev_private;
7992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7993         int pipe = intel_crtc->pipe;
7994         int x = intel_crtc->cursor_x;
7995         int y = intel_crtc->cursor_y;
7996         u32 base = 0, pos = 0;
7997
7998         if (on)
7999                 base = intel_crtc->cursor_addr;
8000
8001         if (x >= intel_crtc->config.pipe_src_w)
8002                 base = 0;
8003
8004         if (y >= intel_crtc->config.pipe_src_h)
8005                 base = 0;
8006
8007         if (x < 0) {
8008                 if (x + intel_crtc->cursor_width <= 0)
8009                         base = 0;
8010
8011                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8012                 x = -x;
8013         }
8014         pos |= x << CURSOR_X_SHIFT;
8015
8016         if (y < 0) {
8017                 if (y + intel_crtc->cursor_height <= 0)
8018                         base = 0;
8019
8020                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8021                 y = -y;
8022         }
8023         pos |= y << CURSOR_Y_SHIFT;
8024
8025         if (base == 0 && intel_crtc->cursor_base == 0)
8026                 return;
8027
8028         I915_WRITE(CURPOS(pipe), pos);
8029
8030         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8031                 ivb_update_cursor(crtc, base);
8032         else if (IS_845G(dev) || IS_I865G(dev))
8033                 i845_update_cursor(crtc, base);
8034         else
8035                 i9xx_update_cursor(crtc, base);
8036         intel_crtc->cursor_base = base;
8037 }
8038
8039 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
8040                                  struct drm_file *file,
8041                                  uint32_t handle,
8042                                  uint32_t width, uint32_t height)
8043 {
8044         struct drm_device *dev = crtc->dev;
8045         struct drm_i915_private *dev_priv = dev->dev_private;
8046         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8047         struct drm_i915_gem_object *obj;
8048         unsigned old_width;
8049         uint32_t addr;
8050         int ret;
8051
8052         /* if we want to turn off the cursor ignore width and height */
8053         if (!handle) {
8054                 DRM_DEBUG_KMS("cursor off\n");
8055                 addr = 0;
8056                 obj = NULL;
8057                 mutex_lock(&dev->struct_mutex);
8058                 goto finish;
8059         }
8060
8061         /* Check for which cursor types we support */
8062         if (!((width == 64 && height == 64) ||
8063                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8064                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8065                 DRM_DEBUG("Cursor dimension not supported\n");
8066                 return -EINVAL;
8067         }
8068
8069         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
8070         if (&obj->base == NULL)
8071                 return -ENOENT;
8072
8073         if (obj->base.size < width * height * 4) {
8074                 DRM_DEBUG_KMS("buffer is to small\n");
8075                 ret = -ENOMEM;
8076                 goto fail;
8077         }
8078
8079         /* we only need to pin inside GTT if cursor is non-phy */
8080         mutex_lock(&dev->struct_mutex);
8081         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8082                 unsigned alignment;
8083
8084                 if (obj->tiling_mode) {
8085                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8086                         ret = -EINVAL;
8087                         goto fail_locked;
8088                 }
8089
8090                 /* Note that the w/a also requires 2 PTE of padding following
8091                  * the bo. We currently fill all unused PTE with the shadow
8092                  * page and so we should always have valid PTE following the
8093                  * cursor preventing the VT-d warning.
8094                  */
8095                 alignment = 0;
8096                 if (need_vtd_wa(dev))
8097                         alignment = 64*1024;
8098
8099                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8100                 if (ret) {
8101                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8102                         goto fail_locked;
8103                 }
8104
8105                 ret = i915_gem_object_put_fence(obj);
8106                 if (ret) {
8107                         DRM_DEBUG_KMS("failed to release fence for cursor");
8108                         goto fail_unpin;
8109                 }
8110
8111                 addr = i915_gem_obj_ggtt_offset(obj);
8112         } else {
8113                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8114                 ret = i915_gem_object_attach_phys(obj, align);
8115                 if (ret) {
8116                         DRM_DEBUG_KMS("failed to attach phys object\n");
8117                         goto fail_locked;
8118                 }
8119                 addr = obj->phys_handle->busaddr;
8120         }
8121
8122         if (IS_GEN2(dev))
8123                 I915_WRITE(CURSIZE, (height << 12) | width);
8124
8125  finish:
8126         if (intel_crtc->cursor_bo) {
8127                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8128                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8129                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8130         }
8131
8132         mutex_unlock(&dev->struct_mutex);
8133
8134         old_width = intel_crtc->cursor_width;
8135
8136         intel_crtc->cursor_addr = addr;
8137         intel_crtc->cursor_bo = obj;
8138         intel_crtc->cursor_width = width;
8139         intel_crtc->cursor_height = height;
8140
8141         if (intel_crtc->active) {
8142                 if (old_width != width)
8143                         intel_update_watermarks(crtc);
8144                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8145         }
8146
8147         return 0;
8148 fail_unpin:
8149         i915_gem_object_unpin_from_display_plane(obj);
8150 fail_locked:
8151         mutex_unlock(&dev->struct_mutex);
8152 fail:
8153         drm_gem_object_unreference_unlocked(&obj->base);
8154         return ret;
8155 }
8156
8157 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8158 {
8159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8160
8161         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8162         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8163
8164         if (intel_crtc->active)
8165                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8166
8167         return 0;
8168 }
8169
8170 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8171                                  u16 *blue, uint32_t start, uint32_t size)
8172 {
8173         int end = (start + size > 256) ? 256 : start + size, i;
8174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8175
8176         for (i = start; i < end; i++) {
8177                 intel_crtc->lut_r[i] = red[i] >> 8;
8178                 intel_crtc->lut_g[i] = green[i] >> 8;
8179                 intel_crtc->lut_b[i] = blue[i] >> 8;
8180         }
8181
8182         intel_crtc_load_lut(crtc);
8183 }
8184
8185 /* VESA 640x480x72Hz mode to set on the pipe */
8186 static struct drm_display_mode load_detect_mode = {
8187         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8188                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8189 };
8190
8191 struct drm_framebuffer *
8192 __intel_framebuffer_create(struct drm_device *dev,
8193                            struct drm_mode_fb_cmd2 *mode_cmd,
8194                            struct drm_i915_gem_object *obj)
8195 {
8196         struct intel_framebuffer *intel_fb;
8197         int ret;
8198
8199         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8200         if (!intel_fb) {
8201                 drm_gem_object_unreference_unlocked(&obj->base);
8202                 return ERR_PTR(-ENOMEM);
8203         }
8204
8205         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8206         if (ret)
8207                 goto err;
8208
8209         return &intel_fb->base;
8210 err:
8211         drm_gem_object_unreference_unlocked(&obj->base);
8212         kfree(intel_fb);
8213
8214         return ERR_PTR(ret);
8215 }
8216
8217 static struct drm_framebuffer *
8218 intel_framebuffer_create(struct drm_device *dev,
8219                          struct drm_mode_fb_cmd2 *mode_cmd,
8220                          struct drm_i915_gem_object *obj)
8221 {
8222         struct drm_framebuffer *fb;
8223         int ret;
8224
8225         ret = i915_mutex_lock_interruptible(dev);
8226         if (ret)
8227                 return ERR_PTR(ret);
8228         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8229         mutex_unlock(&dev->struct_mutex);
8230
8231         return fb;
8232 }
8233
8234 static u32
8235 intel_framebuffer_pitch_for_width(int width, int bpp)
8236 {
8237         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8238         return ALIGN(pitch, 64);
8239 }
8240
8241 static u32
8242 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8243 {
8244         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8245         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8246 }
8247
8248 static struct drm_framebuffer *
8249 intel_framebuffer_create_for_mode(struct drm_device *dev,
8250                                   struct drm_display_mode *mode,
8251                                   int depth, int bpp)
8252 {
8253         struct drm_i915_gem_object *obj;
8254         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8255
8256         obj = i915_gem_alloc_object(dev,
8257                                     intel_framebuffer_size_for_mode(mode, bpp));
8258         if (obj == NULL)
8259                 return ERR_PTR(-ENOMEM);
8260
8261         mode_cmd.width = mode->hdisplay;
8262         mode_cmd.height = mode->vdisplay;
8263         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8264                                                                 bpp);
8265         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8266
8267         return intel_framebuffer_create(dev, &mode_cmd, obj);
8268 }
8269
8270 static struct drm_framebuffer *
8271 mode_fits_in_fbdev(struct drm_device *dev,
8272                    struct drm_display_mode *mode)
8273 {
8274 #ifdef CONFIG_DRM_I915_FBDEV
8275         struct drm_i915_private *dev_priv = dev->dev_private;
8276         struct drm_i915_gem_object *obj;
8277         struct drm_framebuffer *fb;
8278
8279         if (!dev_priv->fbdev)
8280                 return NULL;
8281
8282         if (!dev_priv->fbdev->fb)
8283                 return NULL;
8284
8285         obj = dev_priv->fbdev->fb->obj;
8286         BUG_ON(!obj);
8287
8288         fb = &dev_priv->fbdev->fb->base;
8289         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8290                                                                fb->bits_per_pixel))
8291                 return NULL;
8292
8293         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8294                 return NULL;
8295
8296         return fb;
8297 #else
8298         return NULL;
8299 #endif
8300 }
8301
8302 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8303                                 struct drm_display_mode *mode,
8304                                 struct intel_load_detect_pipe *old,
8305                                 struct drm_modeset_acquire_ctx *ctx)
8306 {
8307         struct intel_crtc *intel_crtc;
8308         struct intel_encoder *intel_encoder =
8309                 intel_attached_encoder(connector);
8310         struct drm_crtc *possible_crtc;
8311         struct drm_encoder *encoder = &intel_encoder->base;
8312         struct drm_crtc *crtc = NULL;
8313         struct drm_device *dev = encoder->dev;
8314         struct drm_framebuffer *fb;
8315         struct drm_mode_config *config = &dev->mode_config;
8316         int ret, i = -1;
8317
8318         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8319                       connector->base.id, connector->name,
8320                       encoder->base.id, encoder->name);
8321
8322         drm_modeset_acquire_init(ctx, 0);
8323
8324 retry:
8325         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8326         if (ret)
8327                 goto fail_unlock;
8328
8329         /*
8330          * Algorithm gets a little messy:
8331          *
8332          *   - if the connector already has an assigned crtc, use it (but make
8333          *     sure it's on first)
8334          *
8335          *   - try to find the first unused crtc that can drive this connector,
8336          *     and use that if we find one
8337          */
8338
8339         /* See if we already have a CRTC for this connector */
8340         if (encoder->crtc) {
8341                 crtc = encoder->crtc;
8342
8343                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8344                 if (ret)
8345                         goto fail_unlock;
8346
8347                 old->dpms_mode = connector->dpms;
8348                 old->load_detect_temp = false;
8349
8350                 /* Make sure the crtc and connector are running */
8351                 if (connector->dpms != DRM_MODE_DPMS_ON)
8352                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8353
8354                 return true;
8355         }
8356
8357         /* Find an unused one (if possible) */
8358         for_each_crtc(dev, possible_crtc) {
8359                 i++;
8360                 if (!(encoder->possible_crtcs & (1 << i)))
8361                         continue;
8362                 if (!possible_crtc->enabled) {
8363                         crtc = possible_crtc;
8364                         break;
8365                 }
8366         }
8367
8368         /*
8369          * If we didn't find an unused CRTC, don't use any.
8370          */
8371         if (!crtc) {
8372                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8373                 goto fail_unlock;
8374         }
8375
8376         ret = drm_modeset_lock(&crtc->mutex, ctx);
8377         if (ret)
8378                 goto fail_unlock;
8379         intel_encoder->new_crtc = to_intel_crtc(crtc);
8380         to_intel_connector(connector)->new_encoder = intel_encoder;
8381
8382         intel_crtc = to_intel_crtc(crtc);
8383         intel_crtc->new_enabled = true;
8384         intel_crtc->new_config = &intel_crtc->config;
8385         old->dpms_mode = connector->dpms;
8386         old->load_detect_temp = true;
8387         old->release_fb = NULL;
8388
8389         if (!mode)
8390                 mode = &load_detect_mode;
8391
8392         /* We need a framebuffer large enough to accommodate all accesses
8393          * that the plane may generate whilst we perform load detection.
8394          * We can not rely on the fbcon either being present (we get called
8395          * during its initialisation to detect all boot displays, or it may
8396          * not even exist) or that it is large enough to satisfy the
8397          * requested mode.
8398          */
8399         fb = mode_fits_in_fbdev(dev, mode);
8400         if (fb == NULL) {
8401                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8402                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8403                 old->release_fb = fb;
8404         } else
8405                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8406         if (IS_ERR(fb)) {
8407                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8408                 goto fail;
8409         }
8410
8411         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8412                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8413                 if (old->release_fb)
8414                         old->release_fb->funcs->destroy(old->release_fb);
8415                 goto fail;
8416         }
8417
8418         /* let the connector get through one full cycle before testing */
8419         intel_wait_for_vblank(dev, intel_crtc->pipe);
8420         return true;
8421
8422  fail:
8423         intel_crtc->new_enabled = crtc->enabled;
8424         if (intel_crtc->new_enabled)
8425                 intel_crtc->new_config = &intel_crtc->config;
8426         else
8427                 intel_crtc->new_config = NULL;
8428 fail_unlock:
8429         if (ret == -EDEADLK) {
8430                 drm_modeset_backoff(ctx);
8431                 goto retry;
8432         }
8433
8434         drm_modeset_drop_locks(ctx);
8435         drm_modeset_acquire_fini(ctx);
8436
8437         return false;
8438 }
8439
8440 void intel_release_load_detect_pipe(struct drm_connector *connector,
8441                                     struct intel_load_detect_pipe *old,
8442                                     struct drm_modeset_acquire_ctx *ctx)
8443 {
8444         struct intel_encoder *intel_encoder =
8445                 intel_attached_encoder(connector);
8446         struct drm_encoder *encoder = &intel_encoder->base;
8447         struct drm_crtc *crtc = encoder->crtc;
8448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8449
8450         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8451                       connector->base.id, connector->name,
8452                       encoder->base.id, encoder->name);
8453
8454         if (old->load_detect_temp) {
8455                 to_intel_connector(connector)->new_encoder = NULL;
8456                 intel_encoder->new_crtc = NULL;
8457                 intel_crtc->new_enabled = false;
8458                 intel_crtc->new_config = NULL;
8459                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8460
8461                 if (old->release_fb) {
8462                         drm_framebuffer_unregister_private(old->release_fb);
8463                         drm_framebuffer_unreference(old->release_fb);
8464                 }
8465
8466                 goto unlock;
8467                 return;
8468         }
8469
8470         /* Switch crtc and encoder back off if necessary */
8471         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8472                 connector->funcs->dpms(connector, old->dpms_mode);
8473
8474 unlock:
8475         drm_modeset_drop_locks(ctx);
8476         drm_modeset_acquire_fini(ctx);
8477 }
8478
8479 static int i9xx_pll_refclk(struct drm_device *dev,
8480                            const struct intel_crtc_config *pipe_config)
8481 {
8482         struct drm_i915_private *dev_priv = dev->dev_private;
8483         u32 dpll = pipe_config->dpll_hw_state.dpll;
8484
8485         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8486                 return dev_priv->vbt.lvds_ssc_freq;
8487         else if (HAS_PCH_SPLIT(dev))
8488                 return 120000;
8489         else if (!IS_GEN2(dev))
8490                 return 96000;
8491         else
8492                 return 48000;
8493 }
8494
8495 /* Returns the clock of the currently programmed mode of the given pipe. */
8496 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8497                                 struct intel_crtc_config *pipe_config)
8498 {
8499         struct drm_device *dev = crtc->base.dev;
8500         struct drm_i915_private *dev_priv = dev->dev_private;
8501         int pipe = pipe_config->cpu_transcoder;
8502         u32 dpll = pipe_config->dpll_hw_state.dpll;
8503         u32 fp;
8504         intel_clock_t clock;
8505         int refclk = i9xx_pll_refclk(dev, pipe_config);
8506
8507         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8508                 fp = pipe_config->dpll_hw_state.fp0;
8509         else
8510                 fp = pipe_config->dpll_hw_state.fp1;
8511
8512         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8513         if (IS_PINEVIEW(dev)) {
8514                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8515                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8516         } else {
8517                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8518                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8519         }
8520
8521         if (!IS_GEN2(dev)) {
8522                 if (IS_PINEVIEW(dev))
8523                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8524                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8525                 else
8526                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8527                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8528
8529                 switch (dpll & DPLL_MODE_MASK) {
8530                 case DPLLB_MODE_DAC_SERIAL:
8531                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8532                                 5 : 10;
8533                         break;
8534                 case DPLLB_MODE_LVDS:
8535                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8536                                 7 : 14;
8537                         break;
8538                 default:
8539                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8540                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8541                         return;
8542                 }
8543
8544                 if (IS_PINEVIEW(dev))
8545                         pineview_clock(refclk, &clock);
8546                 else
8547                         i9xx_clock(refclk, &clock);
8548         } else {
8549                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8550                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8551
8552                 if (is_lvds) {
8553                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8554                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8555
8556                         if (lvds & LVDS_CLKB_POWER_UP)
8557                                 clock.p2 = 7;
8558                         else
8559                                 clock.p2 = 14;
8560                 } else {
8561                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8562                                 clock.p1 = 2;
8563                         else {
8564                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8565                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8566                         }
8567                         if (dpll & PLL_P2_DIVIDE_BY_4)
8568                                 clock.p2 = 4;
8569                         else
8570                                 clock.p2 = 2;
8571                 }
8572
8573                 i9xx_clock(refclk, &clock);
8574         }
8575
8576         /*
8577          * This value includes pixel_multiplier. We will use
8578          * port_clock to compute adjusted_mode.crtc_clock in the
8579          * encoder's get_config() function.
8580          */
8581         pipe_config->port_clock = clock.dot;
8582 }
8583
8584 int intel_dotclock_calculate(int link_freq,
8585                              const struct intel_link_m_n *m_n)
8586 {
8587         /*
8588          * The calculation for the data clock is:
8589          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8590          * But we want to avoid losing precison if possible, so:
8591          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8592          *
8593          * and the link clock is simpler:
8594          * link_clock = (m * link_clock) / n
8595          */
8596
8597         if (!m_n->link_n)
8598                 return 0;
8599
8600         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8601 }
8602
8603 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8604                                    struct intel_crtc_config *pipe_config)
8605 {
8606         struct drm_device *dev = crtc->base.dev;
8607
8608         /* read out port_clock from the DPLL */
8609         i9xx_crtc_clock_get(crtc, pipe_config);
8610
8611         /*
8612          * This value does not include pixel_multiplier.
8613          * We will check that port_clock and adjusted_mode.crtc_clock
8614          * agree once we know their relationship in the encoder's
8615          * get_config() function.
8616          */
8617         pipe_config->adjusted_mode.crtc_clock =
8618                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8619                                          &pipe_config->fdi_m_n);
8620 }
8621
8622 /** Returns the currently programmed mode of the given pipe. */
8623 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8624                                              struct drm_crtc *crtc)
8625 {
8626         struct drm_i915_private *dev_priv = dev->dev_private;
8627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8628         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8629         struct drm_display_mode *mode;
8630         struct intel_crtc_config pipe_config;
8631         int htot = I915_READ(HTOTAL(cpu_transcoder));
8632         int hsync = I915_READ(HSYNC(cpu_transcoder));
8633         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8634         int vsync = I915_READ(VSYNC(cpu_transcoder));
8635         enum pipe pipe = intel_crtc->pipe;
8636
8637         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8638         if (!mode)
8639                 return NULL;
8640
8641         /*
8642          * Construct a pipe_config sufficient for getting the clock info
8643          * back out of crtc_clock_get.
8644          *
8645          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8646          * to use a real value here instead.
8647          */
8648         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8649         pipe_config.pixel_multiplier = 1;
8650         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8651         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8652         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8653         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8654
8655         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8656         mode->hdisplay = (htot & 0xffff) + 1;
8657         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8658         mode->hsync_start = (hsync & 0xffff) + 1;
8659         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8660         mode->vdisplay = (vtot & 0xffff) + 1;
8661         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8662         mode->vsync_start = (vsync & 0xffff) + 1;
8663         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8664
8665         drm_mode_set_name(mode);
8666
8667         return mode;
8668 }
8669
8670 static void intel_increase_pllclock(struct drm_crtc *crtc)
8671 {
8672         struct drm_device *dev = crtc->dev;
8673         struct drm_i915_private *dev_priv = dev->dev_private;
8674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8675         int pipe = intel_crtc->pipe;
8676         int dpll_reg = DPLL(pipe);
8677         int dpll;
8678
8679         if (HAS_PCH_SPLIT(dev))
8680                 return;
8681
8682         if (!dev_priv->lvds_downclock_avail)
8683                 return;
8684
8685         dpll = I915_READ(dpll_reg);
8686         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8687                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8688
8689                 assert_panel_unlocked(dev_priv, pipe);
8690
8691                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8692                 I915_WRITE(dpll_reg, dpll);
8693                 intel_wait_for_vblank(dev, pipe);
8694
8695                 dpll = I915_READ(dpll_reg);
8696                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8697                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8698         }
8699 }
8700
8701 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8702 {
8703         struct drm_device *dev = crtc->dev;
8704         struct drm_i915_private *dev_priv = dev->dev_private;
8705         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8706
8707         if (HAS_PCH_SPLIT(dev))
8708                 return;
8709
8710         if (!dev_priv->lvds_downclock_avail)
8711                 return;
8712
8713         /*
8714          * Since this is called by a timer, we should never get here in
8715          * the manual case.
8716          */
8717         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8718                 int pipe = intel_crtc->pipe;
8719                 int dpll_reg = DPLL(pipe);
8720                 int dpll;
8721
8722                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8723
8724                 assert_panel_unlocked(dev_priv, pipe);
8725
8726                 dpll = I915_READ(dpll_reg);
8727                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8728                 I915_WRITE(dpll_reg, dpll);
8729                 intel_wait_for_vblank(dev, pipe);
8730                 dpll = I915_READ(dpll_reg);
8731                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8732                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8733         }
8734
8735 }
8736
8737 void intel_mark_busy(struct drm_device *dev)
8738 {
8739         struct drm_i915_private *dev_priv = dev->dev_private;
8740
8741         if (dev_priv->mm.busy)
8742                 return;
8743
8744         intel_runtime_pm_get(dev_priv);
8745         i915_update_gfx_val(dev_priv);
8746         dev_priv->mm.busy = true;
8747 }
8748
8749 void intel_mark_idle(struct drm_device *dev)
8750 {
8751         struct drm_i915_private *dev_priv = dev->dev_private;
8752         struct drm_crtc *crtc;
8753
8754         if (!dev_priv->mm.busy)
8755                 return;
8756
8757         dev_priv->mm.busy = false;
8758
8759         if (!i915.powersave)
8760                 goto out;
8761
8762         for_each_crtc(dev, crtc) {
8763                 if (!crtc->primary->fb)
8764                         continue;
8765
8766                 intel_decrease_pllclock(crtc);
8767         }
8768
8769         if (INTEL_INFO(dev)->gen >= 6)
8770                 gen6_rps_idle(dev->dev_private);
8771
8772 out:
8773         intel_runtime_pm_put(dev_priv);
8774 }
8775
8776 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8777                         struct intel_engine_cs *ring)
8778 {
8779         struct drm_device *dev = obj->base.dev;
8780         struct drm_crtc *crtc;
8781
8782         if (!i915.powersave)
8783                 return;
8784
8785         for_each_crtc(dev, crtc) {
8786                 if (!crtc->primary->fb)
8787                         continue;
8788
8789                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8790                         continue;
8791
8792                 intel_increase_pllclock(crtc);
8793                 if (ring && intel_fbc_enabled(dev))
8794                         ring->fbc_dirty = true;
8795         }
8796 }
8797
8798 static void intel_crtc_destroy(struct drm_crtc *crtc)
8799 {
8800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8801         struct drm_device *dev = crtc->dev;
8802         struct intel_unpin_work *work;
8803         unsigned long flags;
8804
8805         spin_lock_irqsave(&dev->event_lock, flags);
8806         work = intel_crtc->unpin_work;
8807         intel_crtc->unpin_work = NULL;
8808         spin_unlock_irqrestore(&dev->event_lock, flags);
8809
8810         if (work) {
8811                 cancel_work_sync(&work->work);
8812                 kfree(work);
8813         }
8814
8815         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8816
8817         drm_crtc_cleanup(crtc);
8818
8819         kfree(intel_crtc);
8820 }
8821
8822 static void intel_unpin_work_fn(struct work_struct *__work)
8823 {
8824         struct intel_unpin_work *work =
8825                 container_of(__work, struct intel_unpin_work, work);
8826         struct drm_device *dev = work->crtc->dev;
8827
8828         mutex_lock(&dev->struct_mutex);
8829         intel_unpin_fb_obj(work->old_fb_obj);
8830         drm_gem_object_unreference(&work->pending_flip_obj->base);
8831         drm_gem_object_unreference(&work->old_fb_obj->base);
8832
8833         intel_update_fbc(dev);
8834         mutex_unlock(&dev->struct_mutex);
8835
8836         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8837         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8838
8839         kfree(work);
8840 }
8841
8842 static void do_intel_finish_page_flip(struct drm_device *dev,
8843                                       struct drm_crtc *crtc)
8844 {
8845         struct drm_i915_private *dev_priv = dev->dev_private;
8846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8847         struct intel_unpin_work *work;
8848         unsigned long flags;
8849
8850         /* Ignore early vblank irqs */
8851         if (intel_crtc == NULL)
8852                 return;
8853
8854         spin_lock_irqsave(&dev->event_lock, flags);
8855         work = intel_crtc->unpin_work;
8856
8857         /* Ensure we don't miss a work->pending update ... */
8858         smp_rmb();
8859
8860         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8861                 spin_unlock_irqrestore(&dev->event_lock, flags);
8862                 return;
8863         }
8864
8865         /* and that the unpin work is consistent wrt ->pending. */
8866         smp_rmb();
8867
8868         intel_crtc->unpin_work = NULL;
8869
8870         if (work->event)
8871                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8872
8873         drm_crtc_vblank_put(crtc);
8874
8875         spin_unlock_irqrestore(&dev->event_lock, flags);
8876
8877         wake_up_all(&dev_priv->pending_flip_queue);
8878
8879         queue_work(dev_priv->wq, &work->work);
8880
8881         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8882 }
8883
8884 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8885 {
8886         struct drm_i915_private *dev_priv = dev->dev_private;
8887         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8888
8889         do_intel_finish_page_flip(dev, crtc);
8890 }
8891
8892 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8893 {
8894         struct drm_i915_private *dev_priv = dev->dev_private;
8895         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8896
8897         do_intel_finish_page_flip(dev, crtc);
8898 }
8899
8900 /* Is 'a' after or equal to 'b'? */
8901 static bool g4x_flip_count_after_eq(u32 a, u32 b)
8902 {
8903         return !((a - b) & 0x80000000);
8904 }
8905
8906 static bool page_flip_finished(struct intel_crtc *crtc)
8907 {
8908         struct drm_device *dev = crtc->base.dev;
8909         struct drm_i915_private *dev_priv = dev->dev_private;
8910
8911         /*
8912          * The relevant registers doen't exist on pre-ctg.
8913          * As the flip done interrupt doesn't trigger for mmio
8914          * flips on gmch platforms, a flip count check isn't
8915          * really needed there. But since ctg has the registers,
8916          * include it in the check anyway.
8917          */
8918         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
8919                 return true;
8920
8921         /*
8922          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
8923          * used the same base address. In that case the mmio flip might
8924          * have completed, but the CS hasn't even executed the flip yet.
8925          *
8926          * A flip count check isn't enough as the CS might have updated
8927          * the base address just after start of vblank, but before we
8928          * managed to process the interrupt. This means we'd complete the
8929          * CS flip too soon.
8930          *
8931          * Combining both checks should get us a good enough result. It may
8932          * still happen that the CS flip has been executed, but has not
8933          * yet actually completed. But in case the base address is the same
8934          * anyway, we don't really care.
8935          */
8936         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
8937                 crtc->unpin_work->gtt_offset &&
8938                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
8939                                     crtc->unpin_work->flip_count);
8940 }
8941
8942 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8943 {
8944         struct drm_i915_private *dev_priv = dev->dev_private;
8945         struct intel_crtc *intel_crtc =
8946                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8947         unsigned long flags;
8948
8949         /* NB: An MMIO update of the plane base pointer will also
8950          * generate a page-flip completion irq, i.e. every modeset
8951          * is also accompanied by a spurious intel_prepare_page_flip().
8952          */
8953         spin_lock_irqsave(&dev->event_lock, flags);
8954         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
8955                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8956         spin_unlock_irqrestore(&dev->event_lock, flags);
8957 }
8958
8959 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8960 {
8961         /* Ensure that the work item is consistent when activating it ... */
8962         smp_wmb();
8963         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8964         /* and that it is marked active as soon as the irq could fire. */
8965         smp_wmb();
8966 }
8967
8968 static int intel_gen2_queue_flip(struct drm_device *dev,
8969                                  struct drm_crtc *crtc,
8970                                  struct drm_framebuffer *fb,
8971                                  struct drm_i915_gem_object *obj,
8972                                  struct intel_engine_cs *ring,
8973                                  uint32_t flags)
8974 {
8975         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8976         u32 flip_mask;
8977         int ret;
8978
8979         ret = intel_ring_begin(ring, 6);
8980         if (ret)
8981                 return ret;
8982
8983         /* Can't queue multiple flips, so wait for the previous
8984          * one to finish before executing the next.
8985          */
8986         if (intel_crtc->plane)
8987                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8988         else
8989                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8990         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8991         intel_ring_emit(ring, MI_NOOP);
8992         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8993                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8994         intel_ring_emit(ring, fb->pitches[0]);
8995         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8996         intel_ring_emit(ring, 0); /* aux display base address, unused */
8997
8998         intel_mark_page_flip_active(intel_crtc);
8999         __intel_ring_advance(ring);
9000         return 0;
9001 }
9002
9003 static int intel_gen3_queue_flip(struct drm_device *dev,
9004                                  struct drm_crtc *crtc,
9005                                  struct drm_framebuffer *fb,
9006                                  struct drm_i915_gem_object *obj,
9007                                  struct intel_engine_cs *ring,
9008                                  uint32_t flags)
9009 {
9010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9011         u32 flip_mask;
9012         int ret;
9013
9014         ret = intel_ring_begin(ring, 6);
9015         if (ret)
9016                 return ret;
9017
9018         if (intel_crtc->plane)
9019                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9020         else
9021                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9022         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9023         intel_ring_emit(ring, MI_NOOP);
9024         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9025                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9026         intel_ring_emit(ring, fb->pitches[0]);
9027         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9028         intel_ring_emit(ring, MI_NOOP);
9029
9030         intel_mark_page_flip_active(intel_crtc);
9031         __intel_ring_advance(ring);
9032         return 0;
9033 }
9034
9035 static int intel_gen4_queue_flip(struct drm_device *dev,
9036                                  struct drm_crtc *crtc,
9037                                  struct drm_framebuffer *fb,
9038                                  struct drm_i915_gem_object *obj,
9039                                  struct intel_engine_cs *ring,
9040                                  uint32_t flags)
9041 {
9042         struct drm_i915_private *dev_priv = dev->dev_private;
9043         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9044         uint32_t pf, pipesrc;
9045         int ret;
9046
9047         ret = intel_ring_begin(ring, 4);
9048         if (ret)
9049                 return ret;
9050
9051         /* i965+ uses the linear or tiled offsets from the
9052          * Display Registers (which do not change across a page-flip)
9053          * so we need only reprogram the base address.
9054          */
9055         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9056                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9057         intel_ring_emit(ring, fb->pitches[0]);
9058         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9059                         obj->tiling_mode);
9060
9061         /* XXX Enabling the panel-fitter across page-flip is so far
9062          * untested on non-native modes, so ignore it for now.
9063          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9064          */
9065         pf = 0;
9066         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9067         intel_ring_emit(ring, pf | pipesrc);
9068
9069         intel_mark_page_flip_active(intel_crtc);
9070         __intel_ring_advance(ring);
9071         return 0;
9072 }
9073
9074 static int intel_gen6_queue_flip(struct drm_device *dev,
9075                                  struct drm_crtc *crtc,
9076                                  struct drm_framebuffer *fb,
9077                                  struct drm_i915_gem_object *obj,
9078                                  struct intel_engine_cs *ring,
9079                                  uint32_t flags)
9080 {
9081         struct drm_i915_private *dev_priv = dev->dev_private;
9082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9083         uint32_t pf, pipesrc;
9084         int ret;
9085
9086         ret = intel_ring_begin(ring, 4);
9087         if (ret)
9088                 return ret;
9089
9090         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9091                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9092         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9093         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9094
9095         /* Contrary to the suggestions in the documentation,
9096          * "Enable Panel Fitter" does not seem to be required when page
9097          * flipping with a non-native mode, and worse causes a normal
9098          * modeset to fail.
9099          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9100          */
9101         pf = 0;
9102         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9103         intel_ring_emit(ring, pf | pipesrc);
9104
9105         intel_mark_page_flip_active(intel_crtc);
9106         __intel_ring_advance(ring);
9107         return 0;
9108 }
9109
9110 static int intel_gen7_queue_flip(struct drm_device *dev,
9111                                  struct drm_crtc *crtc,
9112                                  struct drm_framebuffer *fb,
9113                                  struct drm_i915_gem_object *obj,
9114                                  struct intel_engine_cs *ring,
9115                                  uint32_t flags)
9116 {
9117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9118         uint32_t plane_bit = 0;
9119         int len, ret;
9120
9121         switch (intel_crtc->plane) {
9122         case PLANE_A:
9123                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9124                 break;
9125         case PLANE_B:
9126                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9127                 break;
9128         case PLANE_C:
9129                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9130                 break;
9131         default:
9132                 WARN_ONCE(1, "unknown plane in flip command\n");
9133                 return -ENODEV;
9134         }
9135
9136         len = 4;
9137         if (ring->id == RCS) {
9138                 len += 6;
9139                 /*
9140                  * On Gen 8, SRM is now taking an extra dword to accommodate
9141                  * 48bits addresses, and we need a NOOP for the batch size to
9142                  * stay even.
9143                  */
9144                 if (IS_GEN8(dev))
9145                         len += 2;
9146         }
9147
9148         /*
9149          * BSpec MI_DISPLAY_FLIP for IVB:
9150          * "The full packet must be contained within the same cache line."
9151          *
9152          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9153          * cacheline, if we ever start emitting more commands before
9154          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9155          * then do the cacheline alignment, and finally emit the
9156          * MI_DISPLAY_FLIP.
9157          */
9158         ret = intel_ring_cacheline_align(ring);
9159         if (ret)
9160                 return ret;
9161
9162         ret = intel_ring_begin(ring, len);
9163         if (ret)
9164                 return ret;
9165
9166         /* Unmask the flip-done completion message. Note that the bspec says that
9167          * we should do this for both the BCS and RCS, and that we must not unmask
9168          * more than one flip event at any time (or ensure that one flip message
9169          * can be sent by waiting for flip-done prior to queueing new flips).
9170          * Experimentation says that BCS works despite DERRMR masking all
9171          * flip-done completion events and that unmasking all planes at once
9172          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9173          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9174          */
9175         if (ring->id == RCS) {
9176                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9177                 intel_ring_emit(ring, DERRMR);
9178                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9179                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9180                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9181                 if (IS_GEN8(dev))
9182                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9183                                               MI_SRM_LRM_GLOBAL_GTT);
9184                 else
9185                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9186                                               MI_SRM_LRM_GLOBAL_GTT);
9187                 intel_ring_emit(ring, DERRMR);
9188                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9189                 if (IS_GEN8(dev)) {
9190                         intel_ring_emit(ring, 0);
9191                         intel_ring_emit(ring, MI_NOOP);
9192                 }
9193         }
9194
9195         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9196         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9197         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9198         intel_ring_emit(ring, (MI_NOOP));
9199
9200         intel_mark_page_flip_active(intel_crtc);
9201         __intel_ring_advance(ring);
9202         return 0;
9203 }
9204
9205 static int intel_default_queue_flip(struct drm_device *dev,
9206                                     struct drm_crtc *crtc,
9207                                     struct drm_framebuffer *fb,
9208                                     struct drm_i915_gem_object *obj,
9209                                     struct intel_engine_cs *ring,
9210                                     uint32_t flags)
9211 {
9212         return -ENODEV;
9213 }
9214
9215 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9216                                 struct drm_framebuffer *fb,
9217                                 struct drm_pending_vblank_event *event,
9218                                 uint32_t page_flip_flags)
9219 {
9220         struct drm_device *dev = crtc->dev;
9221         struct drm_i915_private *dev_priv = dev->dev_private;
9222         struct drm_framebuffer *old_fb = crtc->primary->fb;
9223         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9225         struct intel_unpin_work *work;
9226         struct intel_engine_cs *ring;
9227         unsigned long flags;
9228         int ret;
9229
9230         /* Can't change pixel format via MI display flips. */
9231         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9232                 return -EINVAL;
9233
9234         /*
9235          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9236          * Note that pitch changes could also affect these register.
9237          */
9238         if (INTEL_INFO(dev)->gen > 3 &&
9239             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9240              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9241                 return -EINVAL;
9242
9243         if (i915_terminally_wedged(&dev_priv->gpu_error))
9244                 goto out_hang;
9245
9246         work = kzalloc(sizeof(*work), GFP_KERNEL);
9247         if (work == NULL)
9248                 return -ENOMEM;
9249
9250         work->event = event;
9251         work->crtc = crtc;
9252         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9253         INIT_WORK(&work->work, intel_unpin_work_fn);
9254
9255         ret = drm_crtc_vblank_get(crtc);
9256         if (ret)
9257                 goto free_work;
9258
9259         /* We borrow the event spin lock for protecting unpin_work */
9260         spin_lock_irqsave(&dev->event_lock, flags);
9261         if (intel_crtc->unpin_work) {
9262                 spin_unlock_irqrestore(&dev->event_lock, flags);
9263                 kfree(work);
9264                 drm_crtc_vblank_put(crtc);
9265
9266                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9267                 return -EBUSY;
9268         }
9269         intel_crtc->unpin_work = work;
9270         spin_unlock_irqrestore(&dev->event_lock, flags);
9271
9272         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9273                 flush_workqueue(dev_priv->wq);
9274
9275         ret = i915_mutex_lock_interruptible(dev);
9276         if (ret)
9277                 goto cleanup;
9278
9279         /* Reference the objects for the scheduled work. */
9280         drm_gem_object_reference(&work->old_fb_obj->base);
9281         drm_gem_object_reference(&obj->base);
9282
9283         crtc->primary->fb = fb;
9284
9285         work->pending_flip_obj = obj;
9286
9287         work->enable_stall_check = true;
9288
9289         atomic_inc(&intel_crtc->unpin_work_count);
9290         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9291
9292         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9293                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(intel_crtc->pipe)) + 1;
9294
9295         if (IS_VALLEYVIEW(dev)) {
9296                 ring = &dev_priv->ring[BCS];
9297         } else if (INTEL_INFO(dev)->gen >= 7) {
9298                 ring = obj->ring;
9299                 if (ring == NULL || ring->id != RCS)
9300                         ring = &dev_priv->ring[BCS];
9301         } else {
9302                 ring = &dev_priv->ring[RCS];
9303         }
9304
9305         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9306         if (ret)
9307                 goto cleanup_pending;
9308
9309         work->gtt_offset =
9310                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9311
9312         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags);
9313         if (ret)
9314                 goto cleanup_unpin;
9315
9316         intel_disable_fbc(dev);
9317         intel_mark_fb_busy(obj, NULL);
9318         mutex_unlock(&dev->struct_mutex);
9319
9320         trace_i915_flip_request(intel_crtc->plane, obj);
9321
9322         return 0;
9323
9324 cleanup_unpin:
9325         intel_unpin_fb_obj(obj);
9326 cleanup_pending:
9327         atomic_dec(&intel_crtc->unpin_work_count);
9328         crtc->primary->fb = old_fb;
9329         drm_gem_object_unreference(&work->old_fb_obj->base);
9330         drm_gem_object_unreference(&obj->base);
9331         mutex_unlock(&dev->struct_mutex);
9332
9333 cleanup:
9334         spin_lock_irqsave(&dev->event_lock, flags);
9335         intel_crtc->unpin_work = NULL;
9336         spin_unlock_irqrestore(&dev->event_lock, flags);
9337
9338         drm_crtc_vblank_put(crtc);
9339 free_work:
9340         kfree(work);
9341
9342         if (ret == -EIO) {
9343 out_hang:
9344                 intel_crtc_wait_for_pending_flips(crtc);
9345                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9346                 if (ret == 0 && event)
9347                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9348         }
9349         return ret;
9350 }
9351
9352 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9353         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9354         .load_lut = intel_crtc_load_lut,
9355 };
9356
9357 /**
9358  * intel_modeset_update_staged_output_state
9359  *
9360  * Updates the staged output configuration state, e.g. after we've read out the
9361  * current hw state.
9362  */
9363 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9364 {
9365         struct intel_crtc *crtc;
9366         struct intel_encoder *encoder;
9367         struct intel_connector *connector;
9368
9369         list_for_each_entry(connector, &dev->mode_config.connector_list,
9370                             base.head) {
9371                 connector->new_encoder =
9372                         to_intel_encoder(connector->base.encoder);
9373         }
9374
9375         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9376                             base.head) {
9377                 encoder->new_crtc =
9378                         to_intel_crtc(encoder->base.crtc);
9379         }
9380
9381         for_each_intel_crtc(dev, crtc) {
9382                 crtc->new_enabled = crtc->base.enabled;
9383
9384                 if (crtc->new_enabled)
9385                         crtc->new_config = &crtc->config;
9386                 else
9387                         crtc->new_config = NULL;
9388         }
9389 }
9390
9391 /**
9392  * intel_modeset_commit_output_state
9393  *
9394  * This function copies the stage display pipe configuration to the real one.
9395  */
9396 static void intel_modeset_commit_output_state(struct drm_device *dev)
9397 {
9398         struct intel_crtc *crtc;
9399         struct intel_encoder *encoder;
9400         struct intel_connector *connector;
9401
9402         list_for_each_entry(connector, &dev->mode_config.connector_list,
9403                             base.head) {
9404                 connector->base.encoder = &connector->new_encoder->base;
9405         }
9406
9407         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9408                             base.head) {
9409                 encoder->base.crtc = &encoder->new_crtc->base;
9410         }
9411
9412         for_each_intel_crtc(dev, crtc) {
9413                 crtc->base.enabled = crtc->new_enabled;
9414         }
9415 }
9416
9417 static void
9418 connected_sink_compute_bpp(struct intel_connector *connector,
9419                            struct intel_crtc_config *pipe_config)
9420 {
9421         int bpp = pipe_config->pipe_bpp;
9422
9423         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9424                 connector->base.base.id,
9425                 connector->base.name);
9426
9427         /* Don't use an invalid EDID bpc value */
9428         if (connector->base.display_info.bpc &&
9429             connector->base.display_info.bpc * 3 < bpp) {
9430                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9431                               bpp, connector->base.display_info.bpc*3);
9432                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9433         }
9434
9435         /* Clamp bpp to 8 on screens without EDID 1.4 */
9436         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9437                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9438                               bpp);
9439                 pipe_config->pipe_bpp = 24;
9440         }
9441 }
9442
9443 static int
9444 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9445                           struct drm_framebuffer *fb,
9446                           struct intel_crtc_config *pipe_config)
9447 {
9448         struct drm_device *dev = crtc->base.dev;
9449         struct intel_connector *connector;
9450         int bpp;
9451
9452         switch (fb->pixel_format) {
9453         case DRM_FORMAT_C8:
9454                 bpp = 8*3; /* since we go through a colormap */
9455                 break;
9456         case DRM_FORMAT_XRGB1555:
9457         case DRM_FORMAT_ARGB1555:
9458                 /* checked in intel_framebuffer_init already */
9459                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9460                         return -EINVAL;
9461         case DRM_FORMAT_RGB565:
9462                 bpp = 6*3; /* min is 18bpp */
9463                 break;
9464         case DRM_FORMAT_XBGR8888:
9465         case DRM_FORMAT_ABGR8888:
9466                 /* checked in intel_framebuffer_init already */
9467                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9468                         return -EINVAL;
9469         case DRM_FORMAT_XRGB8888:
9470         case DRM_FORMAT_ARGB8888:
9471                 bpp = 8*3;
9472                 break;
9473         case DRM_FORMAT_XRGB2101010:
9474         case DRM_FORMAT_ARGB2101010:
9475         case DRM_FORMAT_XBGR2101010:
9476         case DRM_FORMAT_ABGR2101010:
9477                 /* checked in intel_framebuffer_init already */
9478                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9479                         return -EINVAL;
9480                 bpp = 10*3;
9481                 break;
9482         /* TODO: gen4+ supports 16 bpc floating point, too. */
9483         default:
9484                 DRM_DEBUG_KMS("unsupported depth\n");
9485                 return -EINVAL;
9486         }
9487
9488         pipe_config->pipe_bpp = bpp;
9489
9490         /* Clamp display bpp to EDID value */
9491         list_for_each_entry(connector, &dev->mode_config.connector_list,
9492                             base.head) {
9493                 if (!connector->new_encoder ||
9494                     connector->new_encoder->new_crtc != crtc)
9495                         continue;
9496
9497                 connected_sink_compute_bpp(connector, pipe_config);
9498         }
9499
9500         return bpp;
9501 }
9502
9503 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9504 {
9505         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9506                         "type: 0x%x flags: 0x%x\n",
9507                 mode->crtc_clock,
9508                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9509                 mode->crtc_hsync_end, mode->crtc_htotal,
9510                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9511                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9512 }
9513
9514 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9515                                    struct intel_crtc_config *pipe_config,
9516                                    const char *context)
9517 {
9518         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9519                       context, pipe_name(crtc->pipe));
9520
9521         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9522         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9523                       pipe_config->pipe_bpp, pipe_config->dither);
9524         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9525                       pipe_config->has_pch_encoder,
9526                       pipe_config->fdi_lanes,
9527                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9528                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9529                       pipe_config->fdi_m_n.tu);
9530         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9531                       pipe_config->has_dp_encoder,
9532                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9533                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9534                       pipe_config->dp_m_n.tu);
9535         DRM_DEBUG_KMS("requested mode:\n");
9536         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9537         DRM_DEBUG_KMS("adjusted mode:\n");
9538         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9539         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9540         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9541         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9542                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9543         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9544                       pipe_config->gmch_pfit.control,
9545                       pipe_config->gmch_pfit.pgm_ratios,
9546                       pipe_config->gmch_pfit.lvds_border_bits);
9547         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9548                       pipe_config->pch_pfit.pos,
9549                       pipe_config->pch_pfit.size,
9550                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9551         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9552         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9553 }
9554
9555 static bool encoders_cloneable(const struct intel_encoder *a,
9556                                const struct intel_encoder *b)
9557 {
9558         /* masks could be asymmetric, so check both ways */
9559         return a == b || (a->cloneable & (1 << b->type) &&
9560                           b->cloneable & (1 << a->type));
9561 }
9562
9563 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9564                                          struct intel_encoder *encoder)
9565 {
9566         struct drm_device *dev = crtc->base.dev;
9567         struct intel_encoder *source_encoder;
9568
9569         list_for_each_entry(source_encoder,
9570                             &dev->mode_config.encoder_list, base.head) {
9571                 if (source_encoder->new_crtc != crtc)
9572                         continue;
9573
9574                 if (!encoders_cloneable(encoder, source_encoder))
9575                         return false;
9576         }
9577
9578         return true;
9579 }
9580
9581 static bool check_encoder_cloning(struct intel_crtc *crtc)
9582 {
9583         struct drm_device *dev = crtc->base.dev;
9584         struct intel_encoder *encoder;
9585
9586         list_for_each_entry(encoder,
9587                             &dev->mode_config.encoder_list, base.head) {
9588                 if (encoder->new_crtc != crtc)
9589                         continue;
9590
9591                 if (!check_single_encoder_cloning(crtc, encoder))
9592                         return false;
9593         }
9594
9595         return true;
9596 }
9597
9598 static struct intel_crtc_config *
9599 intel_modeset_pipe_config(struct drm_crtc *crtc,
9600                           struct drm_framebuffer *fb,
9601                           struct drm_display_mode *mode)
9602 {
9603         struct drm_device *dev = crtc->dev;
9604         struct intel_encoder *encoder;
9605         struct intel_crtc_config *pipe_config;
9606         int plane_bpp, ret = -EINVAL;
9607         bool retry = true;
9608
9609         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9610                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9611                 return ERR_PTR(-EINVAL);
9612         }
9613
9614         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9615         if (!pipe_config)
9616                 return ERR_PTR(-ENOMEM);
9617
9618         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9619         drm_mode_copy(&pipe_config->requested_mode, mode);
9620
9621         pipe_config->cpu_transcoder =
9622                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9623         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9624
9625         /*
9626          * Sanitize sync polarity flags based on requested ones. If neither
9627          * positive or negative polarity is requested, treat this as meaning
9628          * negative polarity.
9629          */
9630         if (!(pipe_config->adjusted_mode.flags &
9631               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9632                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9633
9634         if (!(pipe_config->adjusted_mode.flags &
9635               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9636                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9637
9638         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9639          * plane pixel format and any sink constraints into account. Returns the
9640          * source plane bpp so that dithering can be selected on mismatches
9641          * after encoders and crtc also have had their say. */
9642         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9643                                               fb, pipe_config);
9644         if (plane_bpp < 0)
9645                 goto fail;
9646
9647         /*
9648          * Determine the real pipe dimensions. Note that stereo modes can
9649          * increase the actual pipe size due to the frame doubling and
9650          * insertion of additional space for blanks between the frame. This
9651          * is stored in the crtc timings. We use the requested mode to do this
9652          * computation to clearly distinguish it from the adjusted mode, which
9653          * can be changed by the connectors in the below retry loop.
9654          */
9655         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9656         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9657         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9658
9659 encoder_retry:
9660         /* Ensure the port clock defaults are reset when retrying. */
9661         pipe_config->port_clock = 0;
9662         pipe_config->pixel_multiplier = 1;
9663
9664         /* Fill in default crtc timings, allow encoders to overwrite them. */
9665         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9666
9667         /* Pass our mode to the connectors and the CRTC to give them a chance to
9668          * adjust it according to limitations or connector properties, and also
9669          * a chance to reject the mode entirely.
9670          */
9671         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9672                             base.head) {
9673
9674                 if (&encoder->new_crtc->base != crtc)
9675                         continue;
9676
9677                 if (!(encoder->compute_config(encoder, pipe_config))) {
9678                         DRM_DEBUG_KMS("Encoder config failure\n");
9679                         goto fail;
9680                 }
9681         }
9682
9683         /* Set default port clock if not overwritten by the encoder. Needs to be
9684          * done afterwards in case the encoder adjusts the mode. */
9685         if (!pipe_config->port_clock)
9686                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9687                         * pipe_config->pixel_multiplier;
9688
9689         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9690         if (ret < 0) {
9691                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9692                 goto fail;
9693         }
9694
9695         if (ret == RETRY) {
9696                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9697                         ret = -EINVAL;
9698                         goto fail;
9699                 }
9700
9701                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9702                 retry = false;
9703                 goto encoder_retry;
9704         }
9705
9706         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9707         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9708                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9709
9710         return pipe_config;
9711 fail:
9712         kfree(pipe_config);
9713         return ERR_PTR(ret);
9714 }
9715
9716 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9717  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9718 static void
9719 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9720                              unsigned *prepare_pipes, unsigned *disable_pipes)
9721 {
9722         struct intel_crtc *intel_crtc;
9723         struct drm_device *dev = crtc->dev;
9724         struct intel_encoder *encoder;
9725         struct intel_connector *connector;
9726         struct drm_crtc *tmp_crtc;
9727
9728         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9729
9730         /* Check which crtcs have changed outputs connected to them, these need
9731          * to be part of the prepare_pipes mask. We don't (yet) support global
9732          * modeset across multiple crtcs, so modeset_pipes will only have one
9733          * bit set at most. */
9734         list_for_each_entry(connector, &dev->mode_config.connector_list,
9735                             base.head) {
9736                 if (connector->base.encoder == &connector->new_encoder->base)
9737                         continue;
9738
9739                 if (connector->base.encoder) {
9740                         tmp_crtc = connector->base.encoder->crtc;
9741
9742                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9743                 }
9744
9745                 if (connector->new_encoder)
9746                         *prepare_pipes |=
9747                                 1 << connector->new_encoder->new_crtc->pipe;
9748         }
9749
9750         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9751                             base.head) {
9752                 if (encoder->base.crtc == &encoder->new_crtc->base)
9753                         continue;
9754
9755                 if (encoder->base.crtc) {
9756                         tmp_crtc = encoder->base.crtc;
9757
9758                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9759                 }
9760
9761                 if (encoder->new_crtc)
9762                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9763         }
9764
9765         /* Check for pipes that will be enabled/disabled ... */
9766         for_each_intel_crtc(dev, intel_crtc) {
9767                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9768                         continue;
9769
9770                 if (!intel_crtc->new_enabled)
9771                         *disable_pipes |= 1 << intel_crtc->pipe;
9772                 else
9773                         *prepare_pipes |= 1 << intel_crtc->pipe;
9774         }
9775
9776
9777         /* set_mode is also used to update properties on life display pipes. */
9778         intel_crtc = to_intel_crtc(crtc);
9779         if (intel_crtc->new_enabled)
9780                 *prepare_pipes |= 1 << intel_crtc->pipe;
9781
9782         /*
9783          * For simplicity do a full modeset on any pipe where the output routing
9784          * changed. We could be more clever, but that would require us to be
9785          * more careful with calling the relevant encoder->mode_set functions.
9786          */
9787         if (*prepare_pipes)
9788                 *modeset_pipes = *prepare_pipes;
9789
9790         /* ... and mask these out. */
9791         *modeset_pipes &= ~(*disable_pipes);
9792         *prepare_pipes &= ~(*disable_pipes);
9793
9794         /*
9795          * HACK: We don't (yet) fully support global modesets. intel_set_config
9796          * obies this rule, but the modeset restore mode of
9797          * intel_modeset_setup_hw_state does not.
9798          */
9799         *modeset_pipes &= 1 << intel_crtc->pipe;
9800         *prepare_pipes &= 1 << intel_crtc->pipe;
9801
9802         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9803                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9804 }
9805
9806 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9807 {
9808         struct drm_encoder *encoder;
9809         struct drm_device *dev = crtc->dev;
9810
9811         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9812                 if (encoder->crtc == crtc)
9813                         return true;
9814
9815         return false;
9816 }
9817
9818 static void
9819 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9820 {
9821         struct intel_encoder *intel_encoder;
9822         struct intel_crtc *intel_crtc;
9823         struct drm_connector *connector;
9824
9825         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9826                             base.head) {
9827                 if (!intel_encoder->base.crtc)
9828                         continue;
9829
9830                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9831
9832                 if (prepare_pipes & (1 << intel_crtc->pipe))
9833                         intel_encoder->connectors_active = false;
9834         }
9835
9836         intel_modeset_commit_output_state(dev);
9837
9838         /* Double check state. */
9839         for_each_intel_crtc(dev, intel_crtc) {
9840                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9841                 WARN_ON(intel_crtc->new_config &&
9842                         intel_crtc->new_config != &intel_crtc->config);
9843                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9844         }
9845
9846         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9847                 if (!connector->encoder || !connector->encoder->crtc)
9848                         continue;
9849
9850                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9851
9852                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9853                         struct drm_property *dpms_property =
9854                                 dev->mode_config.dpms_property;
9855
9856                         connector->dpms = DRM_MODE_DPMS_ON;
9857                         drm_object_property_set_value(&connector->base,
9858                                                          dpms_property,
9859                                                          DRM_MODE_DPMS_ON);
9860
9861                         intel_encoder = to_intel_encoder(connector->encoder);
9862                         intel_encoder->connectors_active = true;
9863                 }
9864         }
9865
9866 }
9867
9868 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9869 {
9870         int diff;
9871
9872         if (clock1 == clock2)
9873                 return true;
9874
9875         if (!clock1 || !clock2)
9876                 return false;
9877
9878         diff = abs(clock1 - clock2);
9879
9880         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9881                 return true;
9882
9883         return false;
9884 }
9885
9886 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9887         list_for_each_entry((intel_crtc), \
9888                             &(dev)->mode_config.crtc_list, \
9889                             base.head) \
9890                 if (mask & (1 <<(intel_crtc)->pipe))
9891
9892 static bool
9893 intel_pipe_config_compare(struct drm_device *dev,
9894                           struct intel_crtc_config *current_config,
9895                           struct intel_crtc_config *pipe_config)
9896 {
9897 #define PIPE_CONF_CHECK_X(name) \
9898         if (current_config->name != pipe_config->name) { \
9899                 DRM_ERROR("mismatch in " #name " " \
9900                           "(expected 0x%08x, found 0x%08x)\n", \
9901                           current_config->name, \
9902                           pipe_config->name); \
9903                 return false; \
9904         }
9905
9906 #define PIPE_CONF_CHECK_I(name) \
9907         if (current_config->name != pipe_config->name) { \
9908                 DRM_ERROR("mismatch in " #name " " \
9909                           "(expected %i, found %i)\n", \
9910                           current_config->name, \
9911                           pipe_config->name); \
9912                 return false; \
9913         }
9914
9915 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9916         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9917                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9918                           "(expected %i, found %i)\n", \
9919                           current_config->name & (mask), \
9920                           pipe_config->name & (mask)); \
9921                 return false; \
9922         }
9923
9924 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9925         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9926                 DRM_ERROR("mismatch in " #name " " \
9927                           "(expected %i, found %i)\n", \
9928                           current_config->name, \
9929                           pipe_config->name); \
9930                 return false; \
9931         }
9932
9933 #define PIPE_CONF_QUIRK(quirk)  \
9934         ((current_config->quirks | pipe_config->quirks) & (quirk))
9935
9936         PIPE_CONF_CHECK_I(cpu_transcoder);
9937
9938         PIPE_CONF_CHECK_I(has_pch_encoder);
9939         PIPE_CONF_CHECK_I(fdi_lanes);
9940         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9941         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9942         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9943         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9944         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9945
9946         PIPE_CONF_CHECK_I(has_dp_encoder);
9947         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9948         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9949         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9950         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9951         PIPE_CONF_CHECK_I(dp_m_n.tu);
9952
9953         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9954         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9955         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9956         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9957         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9958         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9959
9960         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9961         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9962         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9963         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9964         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9965         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9966
9967         PIPE_CONF_CHECK_I(pixel_multiplier);
9968         PIPE_CONF_CHECK_I(has_hdmi_sink);
9969         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9970             IS_VALLEYVIEW(dev))
9971                 PIPE_CONF_CHECK_I(limited_color_range);
9972
9973         PIPE_CONF_CHECK_I(has_audio);
9974
9975         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9976                               DRM_MODE_FLAG_INTERLACE);
9977
9978         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9979                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9980                                       DRM_MODE_FLAG_PHSYNC);
9981                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9982                                       DRM_MODE_FLAG_NHSYNC);
9983                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9984                                       DRM_MODE_FLAG_PVSYNC);
9985                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9986                                       DRM_MODE_FLAG_NVSYNC);
9987         }
9988
9989         PIPE_CONF_CHECK_I(pipe_src_w);
9990         PIPE_CONF_CHECK_I(pipe_src_h);
9991
9992         /*
9993          * FIXME: BIOS likes to set up a cloned config with lvds+external
9994          * screen. Since we don't yet re-compute the pipe config when moving
9995          * just the lvds port away to another pipe the sw tracking won't match.
9996          *
9997          * Proper atomic modesets with recomputed global state will fix this.
9998          * Until then just don't check gmch state for inherited modes.
9999          */
10000         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10001                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10002                 /* pfit ratios are autocomputed by the hw on gen4+ */
10003                 if (INTEL_INFO(dev)->gen < 4)
10004                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10005                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10006         }
10007
10008         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10009         if (current_config->pch_pfit.enabled) {
10010                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10011                 PIPE_CONF_CHECK_I(pch_pfit.size);
10012         }
10013
10014         /* BDW+ don't expose a synchronous way to read the state */
10015         if (IS_HASWELL(dev))
10016                 PIPE_CONF_CHECK_I(ips_enabled);
10017
10018         PIPE_CONF_CHECK_I(double_wide);
10019
10020         PIPE_CONF_CHECK_I(shared_dpll);
10021         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10022         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10023         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10024         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10025
10026         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10027                 PIPE_CONF_CHECK_I(pipe_bpp);
10028
10029         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10030         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10031
10032 #undef PIPE_CONF_CHECK_X
10033 #undef PIPE_CONF_CHECK_I
10034 #undef PIPE_CONF_CHECK_FLAGS
10035 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10036 #undef PIPE_CONF_QUIRK
10037
10038         return true;
10039 }
10040
10041 static void
10042 check_connector_state(struct drm_device *dev)
10043 {
10044         struct intel_connector *connector;
10045
10046         list_for_each_entry(connector, &dev->mode_config.connector_list,
10047                             base.head) {
10048                 /* This also checks the encoder/connector hw state with the
10049                  * ->get_hw_state callbacks. */
10050                 intel_connector_check_state(connector);
10051
10052                 WARN(&connector->new_encoder->base != connector->base.encoder,
10053                      "connector's staged encoder doesn't match current encoder\n");
10054         }
10055 }
10056
10057 static void
10058 check_encoder_state(struct drm_device *dev)
10059 {
10060         struct intel_encoder *encoder;
10061         struct intel_connector *connector;
10062
10063         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10064                             base.head) {
10065                 bool enabled = false;
10066                 bool active = false;
10067                 enum pipe pipe, tracked_pipe;
10068
10069                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10070                               encoder->base.base.id,
10071                               encoder->base.name);
10072
10073                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10074                      "encoder's stage crtc doesn't match current crtc\n");
10075                 WARN(encoder->connectors_active && !encoder->base.crtc,
10076                      "encoder's active_connectors set, but no crtc\n");
10077
10078                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10079                                     base.head) {
10080                         if (connector->base.encoder != &encoder->base)
10081                                 continue;
10082                         enabled = true;
10083                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10084                                 active = true;
10085                 }
10086                 WARN(!!encoder->base.crtc != enabled,
10087                      "encoder's enabled state mismatch "
10088                      "(expected %i, found %i)\n",
10089                      !!encoder->base.crtc, enabled);
10090                 WARN(active && !encoder->base.crtc,
10091                      "active encoder with no crtc\n");
10092
10093                 WARN(encoder->connectors_active != active,
10094                      "encoder's computed active state doesn't match tracked active state "
10095                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10096
10097                 active = encoder->get_hw_state(encoder, &pipe);
10098                 WARN(active != encoder->connectors_active,
10099                      "encoder's hw state doesn't match sw tracking "
10100                      "(expected %i, found %i)\n",
10101                      encoder->connectors_active, active);
10102
10103                 if (!encoder->base.crtc)
10104                         continue;
10105
10106                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10107                 WARN(active && pipe != tracked_pipe,
10108                      "active encoder's pipe doesn't match"
10109                      "(expected %i, found %i)\n",
10110                      tracked_pipe, pipe);
10111
10112         }
10113 }
10114
10115 static void
10116 check_crtc_state(struct drm_device *dev)
10117 {
10118         struct drm_i915_private *dev_priv = dev->dev_private;
10119         struct intel_crtc *crtc;
10120         struct intel_encoder *encoder;
10121         struct intel_crtc_config pipe_config;
10122
10123         for_each_intel_crtc(dev, crtc) {
10124                 bool enabled = false;
10125                 bool active = false;
10126
10127                 memset(&pipe_config, 0, sizeof(pipe_config));
10128
10129                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10130                               crtc->base.base.id);
10131
10132                 WARN(crtc->active && !crtc->base.enabled,
10133                      "active crtc, but not enabled in sw tracking\n");
10134
10135                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10136                                     base.head) {
10137                         if (encoder->base.crtc != &crtc->base)
10138                                 continue;
10139                         enabled = true;
10140                         if (encoder->connectors_active)
10141                                 active = true;
10142                 }
10143
10144                 WARN(active != crtc->active,
10145                      "crtc's computed active state doesn't match tracked active state "
10146                      "(expected %i, found %i)\n", active, crtc->active);
10147                 WARN(enabled != crtc->base.enabled,
10148                      "crtc's computed enabled state doesn't match tracked enabled state "
10149                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10150
10151                 active = dev_priv->display.get_pipe_config(crtc,
10152                                                            &pipe_config);
10153
10154                 /* hw state is inconsistent with the pipe A quirk */
10155                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10156                         active = crtc->active;
10157
10158                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10159                                     base.head) {
10160                         enum pipe pipe;
10161                         if (encoder->base.crtc != &crtc->base)
10162                                 continue;
10163                         if (encoder->get_hw_state(encoder, &pipe))
10164                                 encoder->get_config(encoder, &pipe_config);
10165                 }
10166
10167                 WARN(crtc->active != active,
10168                      "crtc active state doesn't match with hw state "
10169                      "(expected %i, found %i)\n", crtc->active, active);
10170
10171                 if (active &&
10172                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10173                         WARN(1, "pipe state doesn't match!\n");
10174                         intel_dump_pipe_config(crtc, &pipe_config,
10175                                                "[hw state]");
10176                         intel_dump_pipe_config(crtc, &crtc->config,
10177                                                "[sw state]");
10178                 }
10179         }
10180 }
10181
10182 static void
10183 check_shared_dpll_state(struct drm_device *dev)
10184 {
10185         struct drm_i915_private *dev_priv = dev->dev_private;
10186         struct intel_crtc *crtc;
10187         struct intel_dpll_hw_state dpll_hw_state;
10188         int i;
10189
10190         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10191                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10192                 int enabled_crtcs = 0, active_crtcs = 0;
10193                 bool active;
10194
10195                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10196
10197                 DRM_DEBUG_KMS("%s\n", pll->name);
10198
10199                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10200
10201                 WARN(pll->active > pll->refcount,
10202                      "more active pll users than references: %i vs %i\n",
10203                      pll->active, pll->refcount);
10204                 WARN(pll->active && !pll->on,
10205                      "pll in active use but not on in sw tracking\n");
10206                 WARN(pll->on && !pll->active,
10207                      "pll in on but not on in use in sw tracking\n");
10208                 WARN(pll->on != active,
10209                      "pll on state mismatch (expected %i, found %i)\n",
10210                      pll->on, active);
10211
10212                 for_each_intel_crtc(dev, crtc) {
10213                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10214                                 enabled_crtcs++;
10215                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10216                                 active_crtcs++;
10217                 }
10218                 WARN(pll->active != active_crtcs,
10219                      "pll active crtcs mismatch (expected %i, found %i)\n",
10220                      pll->active, active_crtcs);
10221                 WARN(pll->refcount != enabled_crtcs,
10222                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10223                      pll->refcount, enabled_crtcs);
10224
10225                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10226                                        sizeof(dpll_hw_state)),
10227                      "pll hw state mismatch\n");
10228         }
10229 }
10230
10231 void
10232 intel_modeset_check_state(struct drm_device *dev)
10233 {
10234         check_connector_state(dev);
10235         check_encoder_state(dev);
10236         check_crtc_state(dev);
10237         check_shared_dpll_state(dev);
10238 }
10239
10240 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10241                                      int dotclock)
10242 {
10243         /*
10244          * FDI already provided one idea for the dotclock.
10245          * Yell if the encoder disagrees.
10246          */
10247         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10248              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10249              pipe_config->adjusted_mode.crtc_clock, dotclock);
10250 }
10251
10252 static void update_scanline_offset(struct intel_crtc *crtc)
10253 {
10254         struct drm_device *dev = crtc->base.dev;
10255
10256         /*
10257          * The scanline counter increments at the leading edge of hsync.
10258          *
10259          * On most platforms it starts counting from vtotal-1 on the
10260          * first active line. That means the scanline counter value is
10261          * always one less than what we would expect. Ie. just after
10262          * start of vblank, which also occurs at start of hsync (on the
10263          * last active line), the scanline counter will read vblank_start-1.
10264          *
10265          * On gen2 the scanline counter starts counting from 1 instead
10266          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10267          * to keep the value positive), instead of adding one.
10268          *
10269          * On HSW+ the behaviour of the scanline counter depends on the output
10270          * type. For DP ports it behaves like most other platforms, but on HDMI
10271          * there's an extra 1 line difference. So we need to add two instead of
10272          * one to the value.
10273          */
10274         if (IS_GEN2(dev)) {
10275                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10276                 int vtotal;
10277
10278                 vtotal = mode->crtc_vtotal;
10279                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10280                         vtotal /= 2;
10281
10282                 crtc->scanline_offset = vtotal - 1;
10283         } else if (HAS_DDI(dev) &&
10284                    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10285                 crtc->scanline_offset = 2;
10286         } else
10287                 crtc->scanline_offset = 1;
10288 }
10289
10290 static int __intel_set_mode(struct drm_crtc *crtc,
10291                             struct drm_display_mode *mode,
10292                             int x, int y, struct drm_framebuffer *fb)
10293 {
10294         struct drm_device *dev = crtc->dev;
10295         struct drm_i915_private *dev_priv = dev->dev_private;
10296         struct drm_display_mode *saved_mode;
10297         struct intel_crtc_config *pipe_config = NULL;
10298         struct intel_crtc *intel_crtc;
10299         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10300         int ret = 0;
10301
10302         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10303         if (!saved_mode)
10304                 return -ENOMEM;
10305
10306         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10307                                      &prepare_pipes, &disable_pipes);
10308
10309         *saved_mode = crtc->mode;
10310
10311         /* Hack: Because we don't (yet) support global modeset on multiple
10312          * crtcs, we don't keep track of the new mode for more than one crtc.
10313          * Hence simply check whether any bit is set in modeset_pipes in all the
10314          * pieces of code that are not yet converted to deal with mutliple crtcs
10315          * changing their mode at the same time. */
10316         if (modeset_pipes) {
10317                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10318                 if (IS_ERR(pipe_config)) {
10319                         ret = PTR_ERR(pipe_config);
10320                         pipe_config = NULL;
10321
10322                         goto out;
10323                 }
10324                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10325                                        "[modeset]");
10326                 to_intel_crtc(crtc)->new_config = pipe_config;
10327         }
10328
10329         /*
10330          * See if the config requires any additional preparation, e.g.
10331          * to adjust global state with pipes off.  We need to do this
10332          * here so we can get the modeset_pipe updated config for the new
10333          * mode set on this crtc.  For other crtcs we need to use the
10334          * adjusted_mode bits in the crtc directly.
10335          */
10336         if (IS_VALLEYVIEW(dev)) {
10337                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10338
10339                 /* may have added more to prepare_pipes than we should */
10340                 prepare_pipes &= ~disable_pipes;
10341         }
10342
10343         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10344                 intel_crtc_disable(&intel_crtc->base);
10345
10346         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10347                 if (intel_crtc->base.enabled)
10348                         dev_priv->display.crtc_disable(&intel_crtc->base);
10349         }
10350
10351         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10352          * to set it here already despite that we pass it down the callchain.
10353          */
10354         if (modeset_pipes) {
10355                 crtc->mode = *mode;
10356                 /* mode_set/enable/disable functions rely on a correct pipe
10357                  * config. */
10358                 to_intel_crtc(crtc)->config = *pipe_config;
10359                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10360
10361                 /*
10362                  * Calculate and store various constants which
10363                  * are later needed by vblank and swap-completion
10364                  * timestamping. They are derived from true hwmode.
10365                  */
10366                 drm_calc_timestamping_constants(crtc,
10367                                                 &pipe_config->adjusted_mode);
10368         }
10369
10370         /* Only after disabling all output pipelines that will be changed can we
10371          * update the the output configuration. */
10372         intel_modeset_update_state(dev, prepare_pipes);
10373
10374         if (dev_priv->display.modeset_global_resources)
10375                 dev_priv->display.modeset_global_resources(dev);
10376
10377         /* Set up the DPLL and any encoders state that needs to adjust or depend
10378          * on the DPLL.
10379          */
10380         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10381                 struct drm_framebuffer *old_fb;
10382
10383                 mutex_lock(&dev->struct_mutex);
10384                 ret = intel_pin_and_fence_fb_obj(dev,
10385                                                  to_intel_framebuffer(fb)->obj,
10386                                                  NULL);
10387                 if (ret != 0) {
10388                         DRM_ERROR("pin & fence failed\n");
10389                         mutex_unlock(&dev->struct_mutex);
10390                         goto done;
10391                 }
10392                 old_fb = crtc->primary->fb;
10393                 if (old_fb)
10394                         intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10395                 mutex_unlock(&dev->struct_mutex);
10396
10397                 crtc->primary->fb = fb;
10398                 crtc->x = x;
10399                 crtc->y = y;
10400
10401                 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10402                                                       x, y, fb);
10403                 if (ret)
10404                         goto done;
10405         }
10406
10407         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10408         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10409                 update_scanline_offset(intel_crtc);
10410
10411                 dev_priv->display.crtc_enable(&intel_crtc->base);
10412         }
10413
10414         /* FIXME: add subpixel order */
10415 done:
10416         if (ret && crtc->enabled)
10417                 crtc->mode = *saved_mode;
10418
10419 out:
10420         kfree(pipe_config);
10421         kfree(saved_mode);
10422         return ret;
10423 }
10424
10425 static int intel_set_mode(struct drm_crtc *crtc,
10426                           struct drm_display_mode *mode,
10427                           int x, int y, struct drm_framebuffer *fb)
10428 {
10429         int ret;
10430
10431         ret = __intel_set_mode(crtc, mode, x, y, fb);
10432
10433         if (ret == 0)
10434                 intel_modeset_check_state(crtc->dev);
10435
10436         return ret;
10437 }
10438
10439 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10440 {
10441         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10442 }
10443
10444 #undef for_each_intel_crtc_masked
10445
10446 static void intel_set_config_free(struct intel_set_config *config)
10447 {
10448         if (!config)
10449                 return;
10450
10451         kfree(config->save_connector_encoders);
10452         kfree(config->save_encoder_crtcs);
10453         kfree(config->save_crtc_enabled);
10454         kfree(config);
10455 }
10456
10457 static int intel_set_config_save_state(struct drm_device *dev,
10458                                        struct intel_set_config *config)
10459 {
10460         struct drm_crtc *crtc;
10461         struct drm_encoder *encoder;
10462         struct drm_connector *connector;
10463         int count;
10464
10465         config->save_crtc_enabled =
10466                 kcalloc(dev->mode_config.num_crtc,
10467                         sizeof(bool), GFP_KERNEL);
10468         if (!config->save_crtc_enabled)
10469                 return -ENOMEM;
10470
10471         config->save_encoder_crtcs =
10472                 kcalloc(dev->mode_config.num_encoder,
10473                         sizeof(struct drm_crtc *), GFP_KERNEL);
10474         if (!config->save_encoder_crtcs)
10475                 return -ENOMEM;
10476
10477         config->save_connector_encoders =
10478                 kcalloc(dev->mode_config.num_connector,
10479                         sizeof(struct drm_encoder *), GFP_KERNEL);
10480         if (!config->save_connector_encoders)
10481                 return -ENOMEM;
10482
10483         /* Copy data. Note that driver private data is not affected.
10484          * Should anything bad happen only the expected state is
10485          * restored, not the drivers personal bookkeeping.
10486          */
10487         count = 0;
10488         for_each_crtc(dev, crtc) {
10489                 config->save_crtc_enabled[count++] = crtc->enabled;
10490         }
10491
10492         count = 0;
10493         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10494                 config->save_encoder_crtcs[count++] = encoder->crtc;
10495         }
10496
10497         count = 0;
10498         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10499                 config->save_connector_encoders[count++] = connector->encoder;
10500         }
10501
10502         return 0;
10503 }
10504
10505 static void intel_set_config_restore_state(struct drm_device *dev,
10506                                            struct intel_set_config *config)
10507 {
10508         struct intel_crtc *crtc;
10509         struct intel_encoder *encoder;
10510         struct intel_connector *connector;
10511         int count;
10512
10513         count = 0;
10514         for_each_intel_crtc(dev, crtc) {
10515                 crtc->new_enabled = config->save_crtc_enabled[count++];
10516
10517                 if (crtc->new_enabled)
10518                         crtc->new_config = &crtc->config;
10519                 else
10520                         crtc->new_config = NULL;
10521         }
10522
10523         count = 0;
10524         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10525                 encoder->new_crtc =
10526                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10527         }
10528
10529         count = 0;
10530         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10531                 connector->new_encoder =
10532                         to_intel_encoder(config->save_connector_encoders[count++]);
10533         }
10534 }
10535
10536 static bool
10537 is_crtc_connector_off(struct drm_mode_set *set)
10538 {
10539         int i;
10540
10541         if (set->num_connectors == 0)
10542                 return false;
10543
10544         if (WARN_ON(set->connectors == NULL))
10545                 return false;
10546
10547         for (i = 0; i < set->num_connectors; i++)
10548                 if (set->connectors[i]->encoder &&
10549                     set->connectors[i]->encoder->crtc == set->crtc &&
10550                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10551                         return true;
10552
10553         return false;
10554 }
10555
10556 static void
10557 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10558                                       struct intel_set_config *config)
10559 {
10560
10561         /* We should be able to check here if the fb has the same properties
10562          * and then just flip_or_move it */
10563         if (is_crtc_connector_off(set)) {
10564                 config->mode_changed = true;
10565         } else if (set->crtc->primary->fb != set->fb) {
10566                 /* If we have no fb then treat it as a full mode set */
10567                 if (set->crtc->primary->fb == NULL) {
10568                         struct intel_crtc *intel_crtc =
10569                                 to_intel_crtc(set->crtc);
10570
10571                         if (intel_crtc->active && i915.fastboot) {
10572                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10573                                 config->fb_changed = true;
10574                         } else {
10575                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10576                                 config->mode_changed = true;
10577                         }
10578                 } else if (set->fb == NULL) {
10579                         config->mode_changed = true;
10580                 } else if (set->fb->pixel_format !=
10581                            set->crtc->primary->fb->pixel_format) {
10582                         config->mode_changed = true;
10583                 } else {
10584                         config->fb_changed = true;
10585                 }
10586         }
10587
10588         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10589                 config->fb_changed = true;
10590
10591         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10592                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10593                 drm_mode_debug_printmodeline(&set->crtc->mode);
10594                 drm_mode_debug_printmodeline(set->mode);
10595                 config->mode_changed = true;
10596         }
10597
10598         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10599                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10600 }
10601
10602 static int
10603 intel_modeset_stage_output_state(struct drm_device *dev,
10604                                  struct drm_mode_set *set,
10605                                  struct intel_set_config *config)
10606 {
10607         struct intel_connector *connector;
10608         struct intel_encoder *encoder;
10609         struct intel_crtc *crtc;
10610         int ro;
10611
10612         /* The upper layers ensure that we either disable a crtc or have a list
10613          * of connectors. For paranoia, double-check this. */
10614         WARN_ON(!set->fb && (set->num_connectors != 0));
10615         WARN_ON(set->fb && (set->num_connectors == 0));
10616
10617         list_for_each_entry(connector, &dev->mode_config.connector_list,
10618                             base.head) {
10619                 /* Otherwise traverse passed in connector list and get encoders
10620                  * for them. */
10621                 for (ro = 0; ro < set->num_connectors; ro++) {
10622                         if (set->connectors[ro] == &connector->base) {
10623                                 connector->new_encoder = connector->encoder;
10624                                 break;
10625                         }
10626                 }
10627
10628                 /* If we disable the crtc, disable all its connectors. Also, if
10629                  * the connector is on the changing crtc but not on the new
10630                  * connector list, disable it. */
10631                 if ((!set->fb || ro == set->num_connectors) &&
10632                     connector->base.encoder &&
10633                     connector->base.encoder->crtc == set->crtc) {
10634                         connector->new_encoder = NULL;
10635
10636                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10637                                 connector->base.base.id,
10638                                 connector->base.name);
10639                 }
10640
10641
10642                 if (&connector->new_encoder->base != connector->base.encoder) {
10643                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10644                         config->mode_changed = true;
10645                 }
10646         }
10647         /* connector->new_encoder is now updated for all connectors. */
10648
10649         /* Update crtc of enabled connectors. */
10650         list_for_each_entry(connector, &dev->mode_config.connector_list,
10651                             base.head) {
10652                 struct drm_crtc *new_crtc;
10653
10654                 if (!connector->new_encoder)
10655                         continue;
10656
10657                 new_crtc = connector->new_encoder->base.crtc;
10658
10659                 for (ro = 0; ro < set->num_connectors; ro++) {
10660                         if (set->connectors[ro] == &connector->base)
10661                                 new_crtc = set->crtc;
10662                 }
10663
10664                 /* Make sure the new CRTC will work with the encoder */
10665                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10666                                          new_crtc)) {
10667                         return -EINVAL;
10668                 }
10669                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10670
10671                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10672                         connector->base.base.id,
10673                         connector->base.name,
10674                         new_crtc->base.id);
10675         }
10676
10677         /* Check for any encoders that needs to be disabled. */
10678         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10679                             base.head) {
10680                 int num_connectors = 0;
10681                 list_for_each_entry(connector,
10682                                     &dev->mode_config.connector_list,
10683                                     base.head) {
10684                         if (connector->new_encoder == encoder) {
10685                                 WARN_ON(!connector->new_encoder->new_crtc);
10686                                 num_connectors++;
10687                         }
10688                 }
10689
10690                 if (num_connectors == 0)
10691                         encoder->new_crtc = NULL;
10692                 else if (num_connectors > 1)
10693                         return -EINVAL;
10694
10695                 /* Only now check for crtc changes so we don't miss encoders
10696                  * that will be disabled. */
10697                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10698                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10699                         config->mode_changed = true;
10700                 }
10701         }
10702         /* Now we've also updated encoder->new_crtc for all encoders. */
10703
10704         for_each_intel_crtc(dev, crtc) {
10705                 crtc->new_enabled = false;
10706
10707                 list_for_each_entry(encoder,
10708                                     &dev->mode_config.encoder_list,
10709                                     base.head) {
10710                         if (encoder->new_crtc == crtc) {
10711                                 crtc->new_enabled = true;
10712                                 break;
10713                         }
10714                 }
10715
10716                 if (crtc->new_enabled != crtc->base.enabled) {
10717                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10718                                       crtc->new_enabled ? "en" : "dis");
10719                         config->mode_changed = true;
10720                 }
10721
10722                 if (crtc->new_enabled)
10723                         crtc->new_config = &crtc->config;
10724                 else
10725                         crtc->new_config = NULL;
10726         }
10727
10728         return 0;
10729 }
10730
10731 static void disable_crtc_nofb(struct intel_crtc *crtc)
10732 {
10733         struct drm_device *dev = crtc->base.dev;
10734         struct intel_encoder *encoder;
10735         struct intel_connector *connector;
10736
10737         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10738                       pipe_name(crtc->pipe));
10739
10740         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10741                 if (connector->new_encoder &&
10742                     connector->new_encoder->new_crtc == crtc)
10743                         connector->new_encoder = NULL;
10744         }
10745
10746         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10747                 if (encoder->new_crtc == crtc)
10748                         encoder->new_crtc = NULL;
10749         }
10750
10751         crtc->new_enabled = false;
10752         crtc->new_config = NULL;
10753 }
10754
10755 static int intel_crtc_set_config(struct drm_mode_set *set)
10756 {
10757         struct drm_device *dev;
10758         struct drm_mode_set save_set;
10759         struct intel_set_config *config;
10760         int ret;
10761
10762         BUG_ON(!set);
10763         BUG_ON(!set->crtc);
10764         BUG_ON(!set->crtc->helper_private);
10765
10766         /* Enforce sane interface api - has been abused by the fb helper. */
10767         BUG_ON(!set->mode && set->fb);
10768         BUG_ON(set->fb && set->num_connectors == 0);
10769
10770         if (set->fb) {
10771                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10772                                 set->crtc->base.id, set->fb->base.id,
10773                                 (int)set->num_connectors, set->x, set->y);
10774         } else {
10775                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10776         }
10777
10778         dev = set->crtc->dev;
10779
10780         ret = -ENOMEM;
10781         config = kzalloc(sizeof(*config), GFP_KERNEL);
10782         if (!config)
10783                 goto out_config;
10784
10785         ret = intel_set_config_save_state(dev, config);
10786         if (ret)
10787                 goto out_config;
10788
10789         save_set.crtc = set->crtc;
10790         save_set.mode = &set->crtc->mode;
10791         save_set.x = set->crtc->x;
10792         save_set.y = set->crtc->y;
10793         save_set.fb = set->crtc->primary->fb;
10794
10795         /* Compute whether we need a full modeset, only an fb base update or no
10796          * change at all. In the future we might also check whether only the
10797          * mode changed, e.g. for LVDS where we only change the panel fitter in
10798          * such cases. */
10799         intel_set_config_compute_mode_changes(set, config);
10800
10801         ret = intel_modeset_stage_output_state(dev, set, config);
10802         if (ret)
10803                 goto fail;
10804
10805         if (config->mode_changed) {
10806                 ret = intel_set_mode(set->crtc, set->mode,
10807                                      set->x, set->y, set->fb);
10808         } else if (config->fb_changed) {
10809                 intel_crtc_wait_for_pending_flips(set->crtc);
10810
10811                 ret = intel_pipe_set_base(set->crtc,
10812                                           set->x, set->y, set->fb);
10813                 /*
10814                  * In the fastboot case this may be our only check of the
10815                  * state after boot.  It would be better to only do it on
10816                  * the first update, but we don't have a nice way of doing that
10817                  * (and really, set_config isn't used much for high freq page
10818                  * flipping, so increasing its cost here shouldn't be a big
10819                  * deal).
10820                  */
10821                 if (i915.fastboot && ret == 0)
10822                         intel_modeset_check_state(set->crtc->dev);
10823         }
10824
10825         if (ret) {
10826                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10827                               set->crtc->base.id, ret);
10828 fail:
10829                 intel_set_config_restore_state(dev, config);
10830
10831                 /*
10832                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10833                  * force the pipe off to avoid oopsing in the modeset code
10834                  * due to fb==NULL. This should only happen during boot since
10835                  * we don't yet reconstruct the FB from the hardware state.
10836                  */
10837                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10838                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10839
10840                 /* Try to restore the config */
10841                 if (config->mode_changed &&
10842                     intel_set_mode(save_set.crtc, save_set.mode,
10843                                    save_set.x, save_set.y, save_set.fb))
10844                         DRM_ERROR("failed to restore config after modeset failure\n");
10845         }
10846
10847 out_config:
10848         intel_set_config_free(config);
10849         return ret;
10850 }
10851
10852 static const struct drm_crtc_funcs intel_crtc_funcs = {
10853         .cursor_set = intel_crtc_cursor_set,
10854         .cursor_move = intel_crtc_cursor_move,
10855         .gamma_set = intel_crtc_gamma_set,
10856         .set_config = intel_crtc_set_config,
10857         .destroy = intel_crtc_destroy,
10858         .page_flip = intel_crtc_page_flip,
10859 };
10860
10861 static void intel_cpu_pll_init(struct drm_device *dev)
10862 {
10863         if (HAS_DDI(dev))
10864                 intel_ddi_pll_init(dev);
10865 }
10866
10867 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10868                                       struct intel_shared_dpll *pll,
10869                                       struct intel_dpll_hw_state *hw_state)
10870 {
10871         uint32_t val;
10872
10873         val = I915_READ(PCH_DPLL(pll->id));
10874         hw_state->dpll = val;
10875         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10876         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10877
10878         return val & DPLL_VCO_ENABLE;
10879 }
10880
10881 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10882                                   struct intel_shared_dpll *pll)
10883 {
10884         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10885         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10886 }
10887
10888 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10889                                 struct intel_shared_dpll *pll)
10890 {
10891         /* PCH refclock must be enabled first */
10892         ibx_assert_pch_refclk_enabled(dev_priv);
10893
10894         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10895
10896         /* Wait for the clocks to stabilize. */
10897         POSTING_READ(PCH_DPLL(pll->id));
10898         udelay(150);
10899
10900         /* The pixel multiplier can only be updated once the
10901          * DPLL is enabled and the clocks are stable.
10902          *
10903          * So write it again.
10904          */
10905         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10906         POSTING_READ(PCH_DPLL(pll->id));
10907         udelay(200);
10908 }
10909
10910 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10911                                  struct intel_shared_dpll *pll)
10912 {
10913         struct drm_device *dev = dev_priv->dev;
10914         struct intel_crtc *crtc;
10915
10916         /* Make sure no transcoder isn't still depending on us. */
10917         for_each_intel_crtc(dev, crtc) {
10918                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10919                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10920         }
10921
10922         I915_WRITE(PCH_DPLL(pll->id), 0);
10923         POSTING_READ(PCH_DPLL(pll->id));
10924         udelay(200);
10925 }
10926
10927 static char *ibx_pch_dpll_names[] = {
10928         "PCH DPLL A",
10929         "PCH DPLL B",
10930 };
10931
10932 static void ibx_pch_dpll_init(struct drm_device *dev)
10933 {
10934         struct drm_i915_private *dev_priv = dev->dev_private;
10935         int i;
10936
10937         dev_priv->num_shared_dpll = 2;
10938
10939         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10940                 dev_priv->shared_dplls[i].id = i;
10941                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10942                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10943                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10944                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10945                 dev_priv->shared_dplls[i].get_hw_state =
10946                         ibx_pch_dpll_get_hw_state;
10947         }
10948 }
10949
10950 static void intel_shared_dpll_init(struct drm_device *dev)
10951 {
10952         struct drm_i915_private *dev_priv = dev->dev_private;
10953
10954         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10955                 ibx_pch_dpll_init(dev);
10956         else
10957                 dev_priv->num_shared_dpll = 0;
10958
10959         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10960 }
10961
10962 static void intel_crtc_init(struct drm_device *dev, int pipe)
10963 {
10964         struct drm_i915_private *dev_priv = dev->dev_private;
10965         struct intel_crtc *intel_crtc;
10966         int i;
10967
10968         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10969         if (intel_crtc == NULL)
10970                 return;
10971
10972         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10973
10974         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10975         for (i = 0; i < 256; i++) {
10976                 intel_crtc->lut_r[i] = i;
10977                 intel_crtc->lut_g[i] = i;
10978                 intel_crtc->lut_b[i] = i;
10979         }
10980
10981         /*
10982          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10983          * is hooked to plane B. Hence we want plane A feeding pipe B.
10984          */
10985         intel_crtc->pipe = pipe;
10986         intel_crtc->plane = pipe;
10987         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10988                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10989                 intel_crtc->plane = !pipe;
10990         }
10991
10992         intel_crtc->cursor_base = ~0;
10993         intel_crtc->cursor_cntl = ~0;
10994
10995         init_waitqueue_head(&intel_crtc->vbl_wait);
10996
10997         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10998                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10999         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11000         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11001
11002         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11003
11004         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11005 }
11006
11007 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11008 {
11009         struct drm_encoder *encoder = connector->base.encoder;
11010         struct drm_device *dev = connector->base.dev;
11011
11012         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11013
11014         if (!encoder)
11015                 return INVALID_PIPE;
11016
11017         return to_intel_crtc(encoder->crtc)->pipe;
11018 }
11019
11020 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11021                                 struct drm_file *file)
11022 {
11023         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11024         struct drm_mode_object *drmmode_obj;
11025         struct intel_crtc *crtc;
11026
11027         if (!drm_core_check_feature(dev, DRIVER_MODESET))
11028                 return -ENODEV;
11029
11030         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11031                         DRM_MODE_OBJECT_CRTC);
11032
11033         if (!drmmode_obj) {
11034                 DRM_ERROR("no such CRTC id\n");
11035                 return -ENOENT;
11036         }
11037
11038         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11039         pipe_from_crtc_id->pipe = crtc->pipe;
11040
11041         return 0;
11042 }
11043
11044 static int intel_encoder_clones(struct intel_encoder *encoder)
11045 {
11046         struct drm_device *dev = encoder->base.dev;
11047         struct intel_encoder *source_encoder;
11048         int index_mask = 0;
11049         int entry = 0;
11050
11051         list_for_each_entry(source_encoder,
11052                             &dev->mode_config.encoder_list, base.head) {
11053                 if (encoders_cloneable(encoder, source_encoder))
11054                         index_mask |= (1 << entry);
11055
11056                 entry++;
11057         }
11058
11059         return index_mask;
11060 }
11061
11062 static bool has_edp_a(struct drm_device *dev)
11063 {
11064         struct drm_i915_private *dev_priv = dev->dev_private;
11065
11066         if (!IS_MOBILE(dev))
11067                 return false;
11068
11069         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11070                 return false;
11071
11072         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11073                 return false;
11074
11075         return true;
11076 }
11077
11078 const char *intel_output_name(int output)
11079 {
11080         static const char *names[] = {
11081                 [INTEL_OUTPUT_UNUSED] = "Unused",
11082                 [INTEL_OUTPUT_ANALOG] = "Analog",
11083                 [INTEL_OUTPUT_DVO] = "DVO",
11084                 [INTEL_OUTPUT_SDVO] = "SDVO",
11085                 [INTEL_OUTPUT_LVDS] = "LVDS",
11086                 [INTEL_OUTPUT_TVOUT] = "TV",
11087                 [INTEL_OUTPUT_HDMI] = "HDMI",
11088                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11089                 [INTEL_OUTPUT_EDP] = "eDP",
11090                 [INTEL_OUTPUT_DSI] = "DSI",
11091                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11092         };
11093
11094         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11095                 return "Invalid";
11096
11097         return names[output];
11098 }
11099
11100 static bool intel_crt_present(struct drm_device *dev)
11101 {
11102         struct drm_i915_private *dev_priv = dev->dev_private;
11103
11104         if (IS_ULT(dev))
11105                 return false;
11106
11107         if (IS_CHERRYVIEW(dev))
11108                 return false;
11109
11110         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11111                 return false;
11112
11113         return true;
11114 }
11115
11116 static void intel_setup_outputs(struct drm_device *dev)
11117 {
11118         struct drm_i915_private *dev_priv = dev->dev_private;
11119         struct intel_encoder *encoder;
11120         bool dpd_is_edp = false;
11121
11122         intel_lvds_init(dev);
11123
11124         if (intel_crt_present(dev))
11125                 intel_crt_init(dev);
11126
11127         if (HAS_DDI(dev)) {
11128                 int found;
11129
11130                 /* Haswell uses DDI functions to detect digital outputs */
11131                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11132                 /* DDI A only supports eDP */
11133                 if (found)
11134                         intel_ddi_init(dev, PORT_A);
11135
11136                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11137                  * register */
11138                 found = I915_READ(SFUSE_STRAP);
11139
11140                 if (found & SFUSE_STRAP_DDIB_DETECTED)
11141                         intel_ddi_init(dev, PORT_B);
11142                 if (found & SFUSE_STRAP_DDIC_DETECTED)
11143                         intel_ddi_init(dev, PORT_C);
11144                 if (found & SFUSE_STRAP_DDID_DETECTED)
11145                         intel_ddi_init(dev, PORT_D);
11146         } else if (HAS_PCH_SPLIT(dev)) {
11147                 int found;
11148                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11149
11150                 if (has_edp_a(dev))
11151                         intel_dp_init(dev, DP_A, PORT_A);
11152
11153                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11154                         /* PCH SDVOB multiplex with HDMIB */
11155                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
11156                         if (!found)
11157                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11158                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11159                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
11160                 }
11161
11162                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11163                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11164
11165                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11166                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11167
11168                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11169                         intel_dp_init(dev, PCH_DP_C, PORT_C);
11170
11171                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11172                         intel_dp_init(dev, PCH_DP_D, PORT_D);
11173         } else if (IS_VALLEYVIEW(dev)) {
11174                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11175                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11176                                         PORT_B);
11177                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11178                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11179                 }
11180
11181                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11182                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11183                                         PORT_C);
11184                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11185                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11186                 }
11187
11188                 if (IS_CHERRYVIEW(dev)) {
11189                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11190                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11191                                                 PORT_D);
11192                                 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11193                                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11194                         }
11195                 }
11196
11197                 intel_dsi_init(dev);
11198         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11199                 bool found = false;
11200
11201                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11202                         DRM_DEBUG_KMS("probing SDVOB\n");
11203                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11204                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11205                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11206                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11207                         }
11208
11209                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
11210                                 intel_dp_init(dev, DP_B, PORT_B);
11211                 }
11212
11213                 /* Before G4X SDVOC doesn't have its own detect register */
11214
11215                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11216                         DRM_DEBUG_KMS("probing SDVOC\n");
11217                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11218                 }
11219
11220                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11221
11222                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11223                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11224                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11225                         }
11226                         if (SUPPORTS_INTEGRATED_DP(dev))
11227                                 intel_dp_init(dev, DP_C, PORT_C);
11228                 }
11229
11230                 if (SUPPORTS_INTEGRATED_DP(dev) &&
11231                     (I915_READ(DP_D) & DP_DETECTED))
11232                         intel_dp_init(dev, DP_D, PORT_D);
11233         } else if (IS_GEN2(dev))
11234                 intel_dvo_init(dev);
11235
11236         if (SUPPORTS_TV(dev))
11237                 intel_tv_init(dev);
11238
11239         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11240                 encoder->base.possible_crtcs = encoder->crtc_mask;
11241                 encoder->base.possible_clones =
11242                         intel_encoder_clones(encoder);
11243         }
11244
11245         intel_init_pch_refclk(dev);
11246
11247         drm_helper_move_panel_connectors_to_head(dev);
11248 }
11249
11250 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11251 {
11252         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11253
11254         drm_framebuffer_cleanup(fb);
11255         WARN_ON(!intel_fb->obj->framebuffer_references--);
11256         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11257         kfree(intel_fb);
11258 }
11259
11260 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11261                                                 struct drm_file *file,
11262                                                 unsigned int *handle)
11263 {
11264         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11265         struct drm_i915_gem_object *obj = intel_fb->obj;
11266
11267         return drm_gem_handle_create(file, &obj->base, handle);
11268 }
11269
11270 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11271         .destroy = intel_user_framebuffer_destroy,
11272         .create_handle = intel_user_framebuffer_create_handle,
11273 };
11274
11275 static int intel_framebuffer_init(struct drm_device *dev,
11276                                   struct intel_framebuffer *intel_fb,
11277                                   struct drm_mode_fb_cmd2 *mode_cmd,
11278                                   struct drm_i915_gem_object *obj)
11279 {
11280         int aligned_height;
11281         int pitch_limit;
11282         int ret;
11283
11284         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11285
11286         if (obj->tiling_mode == I915_TILING_Y) {
11287                 DRM_DEBUG("hardware does not support tiling Y\n");
11288                 return -EINVAL;
11289         }
11290
11291         if (mode_cmd->pitches[0] & 63) {
11292                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11293                           mode_cmd->pitches[0]);
11294                 return -EINVAL;
11295         }
11296
11297         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11298                 pitch_limit = 32*1024;
11299         } else if (INTEL_INFO(dev)->gen >= 4) {
11300                 if (obj->tiling_mode)
11301                         pitch_limit = 16*1024;
11302                 else
11303                         pitch_limit = 32*1024;
11304         } else if (INTEL_INFO(dev)->gen >= 3) {
11305                 if (obj->tiling_mode)
11306                         pitch_limit = 8*1024;
11307                 else
11308                         pitch_limit = 16*1024;
11309         } else
11310                 /* XXX DSPC is limited to 4k tiled */
11311                 pitch_limit = 8*1024;
11312
11313         if (mode_cmd->pitches[0] > pitch_limit) {
11314                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11315                           obj->tiling_mode ? "tiled" : "linear",
11316                           mode_cmd->pitches[0], pitch_limit);
11317                 return -EINVAL;
11318         }
11319
11320         if (obj->tiling_mode != I915_TILING_NONE &&
11321             mode_cmd->pitches[0] != obj->stride) {
11322                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11323                           mode_cmd->pitches[0], obj->stride);
11324                 return -EINVAL;
11325         }
11326
11327         /* Reject formats not supported by any plane early. */
11328         switch (mode_cmd->pixel_format) {
11329         case DRM_FORMAT_C8:
11330         case DRM_FORMAT_RGB565:
11331         case DRM_FORMAT_XRGB8888:
11332         case DRM_FORMAT_ARGB8888:
11333                 break;
11334         case DRM_FORMAT_XRGB1555:
11335         case DRM_FORMAT_ARGB1555:
11336                 if (INTEL_INFO(dev)->gen > 3) {
11337                         DRM_DEBUG("unsupported pixel format: %s\n",
11338                                   drm_get_format_name(mode_cmd->pixel_format));
11339                         return -EINVAL;
11340                 }
11341                 break;
11342         case DRM_FORMAT_XBGR8888:
11343         case DRM_FORMAT_ABGR8888:
11344         case DRM_FORMAT_XRGB2101010:
11345         case DRM_FORMAT_ARGB2101010:
11346         case DRM_FORMAT_XBGR2101010:
11347         case DRM_FORMAT_ABGR2101010:
11348                 if (INTEL_INFO(dev)->gen < 4) {
11349                         DRM_DEBUG("unsupported pixel format: %s\n",
11350                                   drm_get_format_name(mode_cmd->pixel_format));
11351                         return -EINVAL;
11352                 }
11353                 break;
11354         case DRM_FORMAT_YUYV:
11355         case DRM_FORMAT_UYVY:
11356         case DRM_FORMAT_YVYU:
11357         case DRM_FORMAT_VYUY:
11358                 if (INTEL_INFO(dev)->gen < 5) {
11359                         DRM_DEBUG("unsupported pixel format: %s\n",
11360                                   drm_get_format_name(mode_cmd->pixel_format));
11361                         return -EINVAL;
11362                 }
11363                 break;
11364         default:
11365                 DRM_DEBUG("unsupported pixel format: %s\n",
11366                           drm_get_format_name(mode_cmd->pixel_format));
11367                 return -EINVAL;
11368         }
11369
11370         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11371         if (mode_cmd->offsets[0] != 0)
11372                 return -EINVAL;
11373
11374         aligned_height = intel_align_height(dev, mode_cmd->height,
11375                                             obj->tiling_mode);
11376         /* FIXME drm helper for size checks (especially planar formats)? */
11377         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11378                 return -EINVAL;
11379
11380         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11381         intel_fb->obj = obj;
11382         intel_fb->obj->framebuffer_references++;
11383
11384         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11385         if (ret) {
11386                 DRM_ERROR("framebuffer init failed %d\n", ret);
11387                 return ret;
11388         }
11389
11390         return 0;
11391 }
11392
11393 static struct drm_framebuffer *
11394 intel_user_framebuffer_create(struct drm_device *dev,
11395                               struct drm_file *filp,
11396                               struct drm_mode_fb_cmd2 *mode_cmd)
11397 {
11398         struct drm_i915_gem_object *obj;
11399
11400         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11401                                                 mode_cmd->handles[0]));
11402         if (&obj->base == NULL)
11403                 return ERR_PTR(-ENOENT);
11404
11405         return intel_framebuffer_create(dev, mode_cmd, obj);
11406 }
11407
11408 #ifndef CONFIG_DRM_I915_FBDEV
11409 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11410 {
11411 }
11412 #endif
11413
11414 static const struct drm_mode_config_funcs intel_mode_funcs = {
11415         .fb_create = intel_user_framebuffer_create,
11416         .output_poll_changed = intel_fbdev_output_poll_changed,
11417 };
11418
11419 /* Set up chip specific display functions */
11420 static void intel_init_display(struct drm_device *dev)
11421 {
11422         struct drm_i915_private *dev_priv = dev->dev_private;
11423
11424         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11425                 dev_priv->display.find_dpll = g4x_find_best_dpll;
11426         else if (IS_CHERRYVIEW(dev))
11427                 dev_priv->display.find_dpll = chv_find_best_dpll;
11428         else if (IS_VALLEYVIEW(dev))
11429                 dev_priv->display.find_dpll = vlv_find_best_dpll;
11430         else if (IS_PINEVIEW(dev))
11431                 dev_priv->display.find_dpll = pnv_find_best_dpll;
11432         else
11433                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11434
11435         if (HAS_DDI(dev)) {
11436                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11437                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11438                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11439                 dev_priv->display.crtc_enable = haswell_crtc_enable;
11440                 dev_priv->display.crtc_disable = haswell_crtc_disable;
11441                 dev_priv->display.off = haswell_crtc_off;
11442                 dev_priv->display.update_primary_plane =
11443                         ironlake_update_primary_plane;
11444         } else if (HAS_PCH_SPLIT(dev)) {
11445                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11446                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11447                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11448                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11449                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11450                 dev_priv->display.off = ironlake_crtc_off;
11451                 dev_priv->display.update_primary_plane =
11452                         ironlake_update_primary_plane;
11453         } else if (IS_VALLEYVIEW(dev)) {
11454                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11455                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11456                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11457                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11458                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11459                 dev_priv->display.off = i9xx_crtc_off;
11460                 dev_priv->display.update_primary_plane =
11461                         i9xx_update_primary_plane;
11462         } else {
11463                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11464                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11465                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11466                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11467                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11468                 dev_priv->display.off = i9xx_crtc_off;
11469                 dev_priv->display.update_primary_plane =
11470                         i9xx_update_primary_plane;
11471         }
11472
11473         /* Returns the core display clock speed */
11474         if (IS_VALLEYVIEW(dev))
11475                 dev_priv->display.get_display_clock_speed =
11476                         valleyview_get_display_clock_speed;
11477         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11478                 dev_priv->display.get_display_clock_speed =
11479                         i945_get_display_clock_speed;
11480         else if (IS_I915G(dev))
11481                 dev_priv->display.get_display_clock_speed =
11482                         i915_get_display_clock_speed;
11483         else if (IS_I945GM(dev) || IS_845G(dev))
11484                 dev_priv->display.get_display_clock_speed =
11485                         i9xx_misc_get_display_clock_speed;
11486         else if (IS_PINEVIEW(dev))
11487                 dev_priv->display.get_display_clock_speed =
11488                         pnv_get_display_clock_speed;
11489         else if (IS_I915GM(dev))
11490                 dev_priv->display.get_display_clock_speed =
11491                         i915gm_get_display_clock_speed;
11492         else if (IS_I865G(dev))
11493                 dev_priv->display.get_display_clock_speed =
11494                         i865_get_display_clock_speed;
11495         else if (IS_I85X(dev))
11496                 dev_priv->display.get_display_clock_speed =
11497                         i855_get_display_clock_speed;
11498         else /* 852, 830 */
11499                 dev_priv->display.get_display_clock_speed =
11500                         i830_get_display_clock_speed;
11501
11502         if (HAS_PCH_SPLIT(dev)) {
11503                 if (IS_GEN5(dev)) {
11504                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11505                         dev_priv->display.write_eld = ironlake_write_eld;
11506                 } else if (IS_GEN6(dev)) {
11507                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11508                         dev_priv->display.write_eld = ironlake_write_eld;
11509                         dev_priv->display.modeset_global_resources =
11510                                 snb_modeset_global_resources;
11511                 } else if (IS_IVYBRIDGE(dev)) {
11512                         /* FIXME: detect B0+ stepping and use auto training */
11513                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11514                         dev_priv->display.write_eld = ironlake_write_eld;
11515                         dev_priv->display.modeset_global_resources =
11516                                 ivb_modeset_global_resources;
11517                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11518                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11519                         dev_priv->display.write_eld = haswell_write_eld;
11520                         dev_priv->display.modeset_global_resources =
11521                                 haswell_modeset_global_resources;
11522                 }
11523         } else if (IS_G4X(dev)) {
11524                 dev_priv->display.write_eld = g4x_write_eld;
11525         } else if (IS_VALLEYVIEW(dev)) {
11526                 dev_priv->display.modeset_global_resources =
11527                         valleyview_modeset_global_resources;
11528                 dev_priv->display.write_eld = ironlake_write_eld;
11529         }
11530
11531         /* Default just returns -ENODEV to indicate unsupported */
11532         dev_priv->display.queue_flip = intel_default_queue_flip;
11533
11534         switch (INTEL_INFO(dev)->gen) {
11535         case 2:
11536                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11537                 break;
11538
11539         case 3:
11540                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11541                 break;
11542
11543         case 4:
11544         case 5:
11545                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11546                 break;
11547
11548         case 6:
11549                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11550                 break;
11551         case 7:
11552         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11553                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11554                 break;
11555         }
11556
11557         intel_panel_init_backlight_funcs(dev);
11558 }
11559
11560 /*
11561  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11562  * resume, or other times.  This quirk makes sure that's the case for
11563  * affected systems.
11564  */
11565 static void quirk_pipea_force(struct drm_device *dev)
11566 {
11567         struct drm_i915_private *dev_priv = dev->dev_private;
11568
11569         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11570         DRM_INFO("applying pipe a force quirk\n");
11571 }
11572
11573 /*
11574  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11575  */
11576 static void quirk_ssc_force_disable(struct drm_device *dev)
11577 {
11578         struct drm_i915_private *dev_priv = dev->dev_private;
11579         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11580         DRM_INFO("applying lvds SSC disable quirk\n");
11581 }
11582
11583 /*
11584  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11585  * brightness value
11586  */
11587 static void quirk_invert_brightness(struct drm_device *dev)
11588 {
11589         struct drm_i915_private *dev_priv = dev->dev_private;
11590         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11591         DRM_INFO("applying inverted panel brightness quirk\n");
11592 }
11593
11594 struct intel_quirk {
11595         int device;
11596         int subsystem_vendor;
11597         int subsystem_device;
11598         void (*hook)(struct drm_device *dev);
11599 };
11600
11601 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11602 struct intel_dmi_quirk {
11603         void (*hook)(struct drm_device *dev);
11604         const struct dmi_system_id (*dmi_id_list)[];
11605 };
11606
11607 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11608 {
11609         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11610         return 1;
11611 }
11612
11613 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11614         {
11615                 .dmi_id_list = &(const struct dmi_system_id[]) {
11616                         {
11617                                 .callback = intel_dmi_reverse_brightness,
11618                                 .ident = "NCR Corporation",
11619                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11620                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11621                                 },
11622                         },
11623                         { }  /* terminating entry */
11624                 },
11625                 .hook = quirk_invert_brightness,
11626         },
11627 };
11628
11629 static struct intel_quirk intel_quirks[] = {
11630         /* HP Mini needs pipe A force quirk (LP: #322104) */
11631         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11632
11633         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11634         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11635
11636         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11637         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11638
11639         /* Lenovo U160 cannot use SSC on LVDS */
11640         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11641
11642         /* Sony Vaio Y cannot use SSC on LVDS */
11643         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11644
11645         /* Acer Aspire 5734Z must invert backlight brightness */
11646         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11647
11648         /* Acer/eMachines G725 */
11649         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11650
11651         /* Acer/eMachines e725 */
11652         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11653
11654         /* Acer/Packard Bell NCL20 */
11655         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11656
11657         /* Acer Aspire 4736Z */
11658         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11659
11660         /* Acer Aspire 5336 */
11661         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11662 };
11663
11664 static void intel_init_quirks(struct drm_device *dev)
11665 {
11666         struct pci_dev *d = dev->pdev;
11667         int i;
11668
11669         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11670                 struct intel_quirk *q = &intel_quirks[i];
11671
11672                 if (d->device == q->device &&
11673                     (d->subsystem_vendor == q->subsystem_vendor ||
11674                      q->subsystem_vendor == PCI_ANY_ID) &&
11675                     (d->subsystem_device == q->subsystem_device ||
11676                      q->subsystem_device == PCI_ANY_ID))
11677                         q->hook(dev);
11678         }
11679         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11680                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11681                         intel_dmi_quirks[i].hook(dev);
11682         }
11683 }
11684
11685 /* Disable the VGA plane that we never use */
11686 static void i915_disable_vga(struct drm_device *dev)
11687 {
11688         struct drm_i915_private *dev_priv = dev->dev_private;
11689         u8 sr1;
11690         u32 vga_reg = i915_vgacntrl_reg(dev);
11691
11692         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11693         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11694         outb(SR01, VGA_SR_INDEX);
11695         sr1 = inb(VGA_SR_DATA);
11696         outb(sr1 | 1<<5, VGA_SR_DATA);
11697         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11698         udelay(300);
11699
11700         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11701         POSTING_READ(vga_reg);
11702 }
11703
11704 void intel_modeset_init_hw(struct drm_device *dev)
11705 {
11706         intel_prepare_ddi(dev);
11707
11708         intel_init_clock_gating(dev);
11709
11710         intel_reset_dpio(dev);
11711
11712         intel_enable_gt_powersave(dev);
11713 }
11714
11715 void intel_modeset_suspend_hw(struct drm_device *dev)
11716 {
11717         intel_suspend_hw(dev);
11718 }
11719
11720 void intel_modeset_init(struct drm_device *dev)
11721 {
11722         struct drm_i915_private *dev_priv = dev->dev_private;
11723         int sprite, ret;
11724         enum pipe pipe;
11725         struct intel_crtc *crtc;
11726
11727         drm_mode_config_init(dev);
11728
11729         dev->mode_config.min_width = 0;
11730         dev->mode_config.min_height = 0;
11731
11732         dev->mode_config.preferred_depth = 24;
11733         dev->mode_config.prefer_shadow = 1;
11734
11735         dev->mode_config.funcs = &intel_mode_funcs;
11736
11737         intel_init_quirks(dev);
11738
11739         intel_init_pm(dev);
11740
11741         if (INTEL_INFO(dev)->num_pipes == 0)
11742                 return;
11743
11744         intel_init_display(dev);
11745
11746         if (IS_GEN2(dev)) {
11747                 dev->mode_config.max_width = 2048;
11748                 dev->mode_config.max_height = 2048;
11749         } else if (IS_GEN3(dev)) {
11750                 dev->mode_config.max_width = 4096;
11751                 dev->mode_config.max_height = 4096;
11752         } else {
11753                 dev->mode_config.max_width = 8192;
11754                 dev->mode_config.max_height = 8192;
11755         }
11756
11757         if (IS_GEN2(dev)) {
11758                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11759                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11760         } else {
11761                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11762                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11763         }
11764
11765         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11766
11767         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11768                       INTEL_INFO(dev)->num_pipes,
11769                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11770
11771         for_each_pipe(pipe) {
11772                 intel_crtc_init(dev, pipe);
11773                 for_each_sprite(pipe, sprite) {
11774                         ret = intel_plane_init(dev, pipe, sprite);
11775                         if (ret)
11776                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11777                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11778                 }
11779         }
11780
11781         intel_init_dpio(dev);
11782         intel_reset_dpio(dev);
11783
11784         intel_cpu_pll_init(dev);
11785         intel_shared_dpll_init(dev);
11786
11787         /* Just disable it once at startup */
11788         i915_disable_vga(dev);
11789         intel_setup_outputs(dev);
11790
11791         /* Just in case the BIOS is doing something questionable. */
11792         intel_disable_fbc(dev);
11793
11794         drm_modeset_lock_all(dev);
11795         intel_modeset_setup_hw_state(dev, false);
11796         drm_modeset_unlock_all(dev);
11797
11798         for_each_intel_crtc(dev, crtc) {
11799                 if (!crtc->active)
11800                         continue;
11801
11802                 /*
11803                  * Note that reserving the BIOS fb up front prevents us
11804                  * from stuffing other stolen allocations like the ring
11805                  * on top.  This prevents some ugliness at boot time, and
11806                  * can even allow for smooth boot transitions if the BIOS
11807                  * fb is large enough for the active pipe configuration.
11808                  */
11809                 if (dev_priv->display.get_plane_config) {
11810                         dev_priv->display.get_plane_config(crtc,
11811                                                            &crtc->plane_config);
11812                         /*
11813                          * If the fb is shared between multiple heads, we'll
11814                          * just get the first one.
11815                          */
11816                         intel_find_plane_obj(crtc, &crtc->plane_config);
11817                 }
11818         }
11819 }
11820
11821 static void intel_enable_pipe_a(struct drm_device *dev)
11822 {
11823         struct intel_connector *connector;
11824         struct drm_connector *crt = NULL;
11825         struct intel_load_detect_pipe load_detect_temp;
11826         struct drm_modeset_acquire_ctx ctx;
11827
11828         /* We can't just switch on the pipe A, we need to set things up with a
11829          * proper mode and output configuration. As a gross hack, enable pipe A
11830          * by enabling the load detect pipe once. */
11831         list_for_each_entry(connector,
11832                             &dev->mode_config.connector_list,
11833                             base.head) {
11834                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11835                         crt = &connector->base;
11836                         break;
11837                 }
11838         }
11839
11840         if (!crt)
11841                 return;
11842
11843         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
11844                 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
11845
11846
11847 }
11848
11849 static bool
11850 intel_check_plane_mapping(struct intel_crtc *crtc)
11851 {
11852         struct drm_device *dev = crtc->base.dev;
11853         struct drm_i915_private *dev_priv = dev->dev_private;
11854         u32 reg, val;
11855
11856         if (INTEL_INFO(dev)->num_pipes == 1)
11857                 return true;
11858
11859         reg = DSPCNTR(!crtc->plane);
11860         val = I915_READ(reg);
11861
11862         if ((val & DISPLAY_PLANE_ENABLE) &&
11863             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11864                 return false;
11865
11866         return true;
11867 }
11868
11869 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11870 {
11871         struct drm_device *dev = crtc->base.dev;
11872         struct drm_i915_private *dev_priv = dev->dev_private;
11873         u32 reg;
11874
11875         /* Clear any frame start delays used for debugging left by the BIOS */
11876         reg = PIPECONF(crtc->config.cpu_transcoder);
11877         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11878
11879         /* restore vblank interrupts to correct state */
11880         if (crtc->active)
11881                 drm_vblank_on(dev, crtc->pipe);
11882         else
11883                 drm_vblank_off(dev, crtc->pipe);
11884
11885         /* We need to sanitize the plane -> pipe mapping first because this will
11886          * disable the crtc (and hence change the state) if it is wrong. Note
11887          * that gen4+ has a fixed plane -> pipe mapping.  */
11888         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11889                 struct intel_connector *connector;
11890                 bool plane;
11891
11892                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11893                               crtc->base.base.id);
11894
11895                 /* Pipe has the wrong plane attached and the plane is active.
11896                  * Temporarily change the plane mapping and disable everything
11897                  * ...  */
11898                 plane = crtc->plane;
11899                 crtc->plane = !plane;
11900                 dev_priv->display.crtc_disable(&crtc->base);
11901                 crtc->plane = plane;
11902
11903                 /* ... and break all links. */
11904                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11905                                     base.head) {
11906                         if (connector->encoder->base.crtc != &crtc->base)
11907                                 continue;
11908
11909                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11910                         connector->base.encoder = NULL;
11911                 }
11912                 /* multiple connectors may have the same encoder:
11913                  *  handle them and break crtc link separately */
11914                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11915                                     base.head)
11916                         if (connector->encoder->base.crtc == &crtc->base) {
11917                                 connector->encoder->base.crtc = NULL;
11918                                 connector->encoder->connectors_active = false;
11919                         }
11920
11921                 WARN_ON(crtc->active);
11922                 crtc->base.enabled = false;
11923         }
11924
11925         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11926             crtc->pipe == PIPE_A && !crtc->active) {
11927                 /* BIOS forgot to enable pipe A, this mostly happens after
11928                  * resume. Force-enable the pipe to fix this, the update_dpms
11929                  * call below we restore the pipe to the right state, but leave
11930                  * the required bits on. */
11931                 intel_enable_pipe_a(dev);
11932         }
11933
11934         /* Adjust the state of the output pipe according to whether we
11935          * have active connectors/encoders. */
11936         intel_crtc_update_dpms(&crtc->base);
11937
11938         if (crtc->active != crtc->base.enabled) {
11939                 struct intel_encoder *encoder;
11940
11941                 /* This can happen either due to bugs in the get_hw_state
11942                  * functions or because the pipe is force-enabled due to the
11943                  * pipe A quirk. */
11944                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11945                               crtc->base.base.id,
11946                               crtc->base.enabled ? "enabled" : "disabled",
11947                               crtc->active ? "enabled" : "disabled");
11948
11949                 crtc->base.enabled = crtc->active;
11950
11951                 /* Because we only establish the connector -> encoder ->
11952                  * crtc links if something is active, this means the
11953                  * crtc is now deactivated. Break the links. connector
11954                  * -> encoder links are only establish when things are
11955                  *  actually up, hence no need to break them. */
11956                 WARN_ON(crtc->active);
11957
11958                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11959                         WARN_ON(encoder->connectors_active);
11960                         encoder->base.crtc = NULL;
11961                 }
11962         }
11963
11964         if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
11965                 /*
11966                  * We start out with underrun reporting disabled to avoid races.
11967                  * For correct bookkeeping mark this on active crtcs.
11968                  *
11969                  * Also on gmch platforms we dont have any hardware bits to
11970                  * disable the underrun reporting. Which means we need to start
11971                  * out with underrun reporting disabled also on inactive pipes,
11972                  * since otherwise we'll complain about the garbage we read when
11973                  * e.g. coming up after runtime pm.
11974                  *
11975                  * No protection against concurrent access is required - at
11976                  * worst a fifo underrun happens which also sets this to false.
11977                  */
11978                 crtc->cpu_fifo_underrun_disabled = true;
11979                 crtc->pch_fifo_underrun_disabled = true;
11980
11981                 update_scanline_offset(crtc);
11982         }
11983 }
11984
11985 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11986 {
11987         struct intel_connector *connector;
11988         struct drm_device *dev = encoder->base.dev;
11989
11990         /* We need to check both for a crtc link (meaning that the
11991          * encoder is active and trying to read from a pipe) and the
11992          * pipe itself being active. */
11993         bool has_active_crtc = encoder->base.crtc &&
11994                 to_intel_crtc(encoder->base.crtc)->active;
11995
11996         if (encoder->connectors_active && !has_active_crtc) {
11997                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11998                               encoder->base.base.id,
11999                               encoder->base.name);
12000
12001                 /* Connector is active, but has no active pipe. This is
12002                  * fallout from our resume register restoring. Disable
12003                  * the encoder manually again. */
12004                 if (encoder->base.crtc) {
12005                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12006                                       encoder->base.base.id,
12007                                       encoder->base.name);
12008                         encoder->disable(encoder);
12009                 }
12010                 encoder->base.crtc = NULL;
12011                 encoder->connectors_active = false;
12012
12013                 /* Inconsistent output/port/pipe state happens presumably due to
12014                  * a bug in one of the get_hw_state functions. Or someplace else
12015                  * in our code, like the register restore mess on resume. Clamp
12016                  * things to off as a safer default. */
12017                 list_for_each_entry(connector,
12018                                     &dev->mode_config.connector_list,
12019                                     base.head) {
12020                         if (connector->encoder != encoder)
12021                                 continue;
12022                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12023                         connector->base.encoder = NULL;
12024                 }
12025         }
12026         /* Enabled encoders without active connectors will be fixed in
12027          * the crtc fixup. */
12028 }
12029
12030 void i915_redisable_vga_power_on(struct drm_device *dev)
12031 {
12032         struct drm_i915_private *dev_priv = dev->dev_private;
12033         u32 vga_reg = i915_vgacntrl_reg(dev);
12034
12035         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12036                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12037                 i915_disable_vga(dev);
12038         }
12039 }
12040
12041 void i915_redisable_vga(struct drm_device *dev)
12042 {
12043         struct drm_i915_private *dev_priv = dev->dev_private;
12044
12045         /* This function can be called both from intel_modeset_setup_hw_state or
12046          * at a very early point in our resume sequence, where the power well
12047          * structures are not yet restored. Since this function is at a very
12048          * paranoid "someone might have enabled VGA while we were not looking"
12049          * level, just check if the power well is enabled instead of trying to
12050          * follow the "don't touch the power well if we don't need it" policy
12051          * the rest of the driver uses. */
12052         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12053                 return;
12054
12055         i915_redisable_vga_power_on(dev);
12056 }
12057
12058 static bool primary_get_hw_state(struct intel_crtc *crtc)
12059 {
12060         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12061
12062         if (!crtc->active)
12063                 return false;
12064
12065         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12066 }
12067
12068 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12069 {
12070         struct drm_i915_private *dev_priv = dev->dev_private;
12071         enum pipe pipe;
12072         struct intel_crtc *crtc;
12073         struct intel_encoder *encoder;
12074         struct intel_connector *connector;
12075         int i;
12076
12077         for_each_intel_crtc(dev, crtc) {
12078                 memset(&crtc->config, 0, sizeof(crtc->config));
12079
12080                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12081
12082                 crtc->active = dev_priv->display.get_pipe_config(crtc,
12083                                                                  &crtc->config);
12084
12085                 crtc->base.enabled = crtc->active;
12086                 crtc->primary_enabled = primary_get_hw_state(crtc);
12087
12088                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12089                               crtc->base.base.id,
12090                               crtc->active ? "enabled" : "disabled");
12091         }
12092
12093         /* FIXME: Smash this into the new shared dpll infrastructure. */
12094         if (HAS_DDI(dev))
12095                 intel_ddi_setup_hw_pll_state(dev);
12096
12097         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12098                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12099
12100                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12101                 pll->active = 0;
12102                 for_each_intel_crtc(dev, crtc) {
12103                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12104                                 pll->active++;
12105                 }
12106                 pll->refcount = pll->active;
12107
12108                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12109                               pll->name, pll->refcount, pll->on);
12110         }
12111
12112         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12113                             base.head) {
12114                 pipe = 0;
12115
12116                 if (encoder->get_hw_state(encoder, &pipe)) {
12117                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12118                         encoder->base.crtc = &crtc->base;
12119                         encoder->get_config(encoder, &crtc->config);
12120                 } else {
12121                         encoder->base.crtc = NULL;
12122                 }
12123
12124                 encoder->connectors_active = false;
12125                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12126                               encoder->base.base.id,
12127                               encoder->base.name,
12128                               encoder->base.crtc ? "enabled" : "disabled",
12129                               pipe_name(pipe));
12130         }
12131
12132         list_for_each_entry(connector, &dev->mode_config.connector_list,
12133                             base.head) {
12134                 if (connector->get_hw_state(connector)) {
12135                         connector->base.dpms = DRM_MODE_DPMS_ON;
12136                         connector->encoder->connectors_active = true;
12137                         connector->base.encoder = &connector->encoder->base;
12138                 } else {
12139                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12140                         connector->base.encoder = NULL;
12141                 }
12142                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12143                               connector->base.base.id,
12144                               connector->base.name,
12145                               connector->base.encoder ? "enabled" : "disabled");
12146         }
12147 }
12148
12149 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12150  * and i915 state tracking structures. */
12151 void intel_modeset_setup_hw_state(struct drm_device *dev,
12152                                   bool force_restore)
12153 {
12154         struct drm_i915_private *dev_priv = dev->dev_private;
12155         enum pipe pipe;
12156         struct intel_crtc *crtc;
12157         struct intel_encoder *encoder;
12158         int i;
12159
12160         intel_modeset_readout_hw_state(dev);
12161
12162         /*
12163          * Now that we have the config, copy it to each CRTC struct
12164          * Note that this could go away if we move to using crtc_config
12165          * checking everywhere.
12166          */
12167         for_each_intel_crtc(dev, crtc) {
12168                 if (crtc->active && i915.fastboot) {
12169                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12170                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12171                                       crtc->base.base.id);
12172                         drm_mode_debug_printmodeline(&crtc->base.mode);
12173                 }
12174         }
12175
12176         /* HW state is read out, now we need to sanitize this mess. */
12177         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12178                             base.head) {
12179                 intel_sanitize_encoder(encoder);
12180         }
12181
12182         for_each_pipe(pipe) {
12183                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12184                 intel_sanitize_crtc(crtc);
12185                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12186         }
12187
12188         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12189                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12190
12191                 if (!pll->on || pll->active)
12192                         continue;
12193
12194                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12195
12196                 pll->disable(dev_priv, pll);
12197                 pll->on = false;
12198         }
12199
12200         if (HAS_PCH_SPLIT(dev))
12201                 ilk_wm_get_hw_state(dev);
12202
12203         if (force_restore) {
12204                 i915_redisable_vga(dev);
12205
12206                 /*
12207                  * We need to use raw interfaces for restoring state to avoid
12208                  * checking (bogus) intermediate states.
12209                  */
12210                 for_each_pipe(pipe) {
12211                         struct drm_crtc *crtc =
12212                                 dev_priv->pipe_to_crtc_mapping[pipe];
12213
12214                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12215                                          crtc->primary->fb);
12216                 }
12217         } else {
12218                 intel_modeset_update_staged_output_state(dev);
12219         }
12220
12221         intel_modeset_check_state(dev);
12222 }
12223
12224 void intel_modeset_gem_init(struct drm_device *dev)
12225 {
12226         struct drm_crtc *c;
12227         struct intel_framebuffer *fb;
12228
12229         mutex_lock(&dev->struct_mutex);
12230         intel_init_gt_powersave(dev);
12231         mutex_unlock(&dev->struct_mutex);
12232
12233         intel_modeset_init_hw(dev);
12234
12235         intel_setup_overlay(dev);
12236
12237         /*
12238          * Make sure any fbs we allocated at startup are properly
12239          * pinned & fenced.  When we do the allocation it's too early
12240          * for this.
12241          */
12242         mutex_lock(&dev->struct_mutex);
12243         for_each_crtc(dev, c) {
12244                 if (!c->primary->fb)
12245                         continue;
12246
12247                 fb = to_intel_framebuffer(c->primary->fb);
12248                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12249                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
12250                                   to_intel_crtc(c)->pipe);
12251                         drm_framebuffer_unreference(c->primary->fb);
12252                         c->primary->fb = NULL;
12253                 }
12254         }
12255         mutex_unlock(&dev->struct_mutex);
12256 }
12257
12258 void intel_connector_unregister(struct intel_connector *intel_connector)
12259 {
12260         struct drm_connector *connector = &intel_connector->base;
12261
12262         intel_panel_destroy_backlight(connector);
12263         drm_sysfs_connector_remove(connector);
12264 }
12265
12266 void intel_modeset_cleanup(struct drm_device *dev)
12267 {
12268         struct drm_i915_private *dev_priv = dev->dev_private;
12269         struct drm_crtc *crtc;
12270         struct drm_connector *connector;
12271
12272         /*
12273          * Interrupts and polling as the first thing to avoid creating havoc.
12274          * Too much stuff here (turning of rps, connectors, ...) would
12275          * experience fancy races otherwise.
12276          */
12277         drm_irq_uninstall(dev);
12278         cancel_work_sync(&dev_priv->hotplug_work);
12279         /*
12280          * Due to the hpd irq storm handling the hotplug work can re-arm the
12281          * poll handlers. Hence disable polling after hpd handling is shut down.
12282          */
12283         drm_kms_helper_poll_fini(dev);
12284
12285         mutex_lock(&dev->struct_mutex);
12286
12287         intel_unregister_dsm_handler();
12288
12289         for_each_crtc(dev, crtc) {
12290                 /* Skip inactive CRTCs */
12291                 if (!crtc->primary->fb)
12292                         continue;
12293
12294                 intel_increase_pllclock(crtc);
12295         }
12296
12297         intel_disable_fbc(dev);
12298
12299         intel_disable_gt_powersave(dev);
12300
12301         ironlake_teardown_rc6(dev);
12302
12303         mutex_unlock(&dev->struct_mutex);
12304
12305         /* flush any delayed tasks or pending work */
12306         flush_scheduled_work();
12307
12308         /* destroy the backlight and sysfs files before encoders/connectors */
12309         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12310                 struct intel_connector *intel_connector;
12311
12312                 intel_connector = to_intel_connector(connector);
12313                 intel_connector->unregister(intel_connector);
12314         }
12315
12316         drm_mode_config_cleanup(dev);
12317
12318         intel_cleanup_overlay(dev);
12319
12320         mutex_lock(&dev->struct_mutex);
12321         intel_cleanup_gt_powersave(dev);
12322         mutex_unlock(&dev->struct_mutex);
12323 }
12324
12325 /*
12326  * Return which encoder is currently attached for connector.
12327  */
12328 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12329 {
12330         return &intel_attached_encoder(connector)->base;
12331 }
12332
12333 void intel_connector_attach_encoder(struct intel_connector *connector,
12334                                     struct intel_encoder *encoder)
12335 {
12336         connector->encoder = encoder;
12337         drm_mode_connector_attach_encoder(&connector->base,
12338                                           &encoder->base);
12339 }
12340
12341 /*
12342  * set vga decode state - true == enable VGA decode
12343  */
12344 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12345 {
12346         struct drm_i915_private *dev_priv = dev->dev_private;
12347         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12348         u16 gmch_ctrl;
12349
12350         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12351                 DRM_ERROR("failed to read control word\n");
12352                 return -EIO;
12353         }
12354
12355         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12356                 return 0;
12357
12358         if (state)
12359                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12360         else
12361                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12362
12363         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12364                 DRM_ERROR("failed to write control word\n");
12365                 return -EIO;
12366         }
12367
12368         return 0;
12369 }
12370
12371 struct intel_display_error_state {
12372
12373         u32 power_well_driver;
12374
12375         int num_transcoders;
12376
12377         struct intel_cursor_error_state {
12378                 u32 control;
12379                 u32 position;
12380                 u32 base;
12381                 u32 size;
12382         } cursor[I915_MAX_PIPES];
12383
12384         struct intel_pipe_error_state {
12385                 bool power_domain_on;
12386                 u32 source;
12387                 u32 stat;
12388         } pipe[I915_MAX_PIPES];
12389
12390         struct intel_plane_error_state {
12391                 u32 control;
12392                 u32 stride;
12393                 u32 size;
12394                 u32 pos;
12395                 u32 addr;
12396                 u32 surface;
12397                 u32 tile_offset;
12398         } plane[I915_MAX_PIPES];
12399
12400         struct intel_transcoder_error_state {
12401                 bool power_domain_on;
12402                 enum transcoder cpu_transcoder;
12403
12404                 u32 conf;
12405
12406                 u32 htotal;
12407                 u32 hblank;
12408                 u32 hsync;
12409                 u32 vtotal;
12410                 u32 vblank;
12411                 u32 vsync;
12412         } transcoder[4];
12413 };
12414
12415 struct intel_display_error_state *
12416 intel_display_capture_error_state(struct drm_device *dev)
12417 {
12418         struct drm_i915_private *dev_priv = dev->dev_private;
12419         struct intel_display_error_state *error;
12420         int transcoders[] = {
12421                 TRANSCODER_A,
12422                 TRANSCODER_B,
12423                 TRANSCODER_C,
12424                 TRANSCODER_EDP,
12425         };
12426         int i;
12427
12428         if (INTEL_INFO(dev)->num_pipes == 0)
12429                 return NULL;
12430
12431         error = kzalloc(sizeof(*error), GFP_ATOMIC);
12432         if (error == NULL)
12433                 return NULL;
12434
12435         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12436                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12437
12438         for_each_pipe(i) {
12439                 error->pipe[i].power_domain_on =
12440                         intel_display_power_enabled_unlocked(dev_priv,
12441                                                            POWER_DOMAIN_PIPE(i));
12442                 if (!error->pipe[i].power_domain_on)
12443                         continue;
12444
12445                 error->cursor[i].control = I915_READ(CURCNTR(i));
12446                 error->cursor[i].position = I915_READ(CURPOS(i));
12447                 error->cursor[i].base = I915_READ(CURBASE(i));
12448
12449                 error->plane[i].control = I915_READ(DSPCNTR(i));
12450                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12451                 if (INTEL_INFO(dev)->gen <= 3) {
12452                         error->plane[i].size = I915_READ(DSPSIZE(i));
12453                         error->plane[i].pos = I915_READ(DSPPOS(i));
12454                 }
12455                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12456                         error->plane[i].addr = I915_READ(DSPADDR(i));
12457                 if (INTEL_INFO(dev)->gen >= 4) {
12458                         error->plane[i].surface = I915_READ(DSPSURF(i));
12459                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12460                 }
12461
12462                 error->pipe[i].source = I915_READ(PIPESRC(i));
12463
12464                 if (!HAS_PCH_SPLIT(dev))
12465                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
12466         }
12467
12468         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12469         if (HAS_DDI(dev_priv->dev))
12470                 error->num_transcoders++; /* Account for eDP. */
12471
12472         for (i = 0; i < error->num_transcoders; i++) {
12473                 enum transcoder cpu_transcoder = transcoders[i];
12474
12475                 error->transcoder[i].power_domain_on =
12476                         intel_display_power_enabled_unlocked(dev_priv,
12477                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12478                 if (!error->transcoder[i].power_domain_on)
12479                         continue;
12480
12481                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12482
12483                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12484                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12485                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12486                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12487                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12488                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12489                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12490         }
12491
12492         return error;
12493 }
12494
12495 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12496
12497 void
12498 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12499                                 struct drm_device *dev,
12500                                 struct intel_display_error_state *error)
12501 {
12502         int i;
12503
12504         if (!error)
12505                 return;
12506
12507         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12508         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12509                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12510                            error->power_well_driver);
12511         for_each_pipe(i) {
12512                 err_printf(m, "Pipe [%d]:\n", i);
12513                 err_printf(m, "  Power: %s\n",
12514                            error->pipe[i].power_domain_on ? "on" : "off");
12515                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12516                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12517
12518                 err_printf(m, "Plane [%d]:\n", i);
12519                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12520                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12521                 if (INTEL_INFO(dev)->gen <= 3) {
12522                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12523                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12524                 }
12525                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12526                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12527                 if (INTEL_INFO(dev)->gen >= 4) {
12528                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12529                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12530                 }
12531
12532                 err_printf(m, "Cursor [%d]:\n", i);
12533                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12534                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12535                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12536         }
12537
12538         for (i = 0; i < error->num_transcoders; i++) {
12539                 err_printf(m, "CPU transcoder: %c\n",
12540                            transcoder_name(error->transcoder[i].cpu_transcoder));
12541                 err_printf(m, "  Power: %s\n",
12542                            error->transcoder[i].power_domain_on ? "on" : "off");
12543                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12544                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12545                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12546                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12547                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12548                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12549                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12550         }
12551 }